/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : DMA,CACHE,TRGMUX,FLEXIO
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
*
*   (c) Copyright 2020-2021 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifdef __cplusplus
extern "C"
{
#endif

/*==================================================================================================
*                                        INCLUDE FILES
* 1) system and project includes
* 2) needed interfaces from external units
* 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Dma_Ip_Cfg.h"

/*==================================================================================================
*                                    SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define DMA_IP_VS_0_PBCFG_VENDOR_ID_C                        43
#define DMA_IP_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION_C         4
#define DMA_IP_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION_C         4
#define DMA_IP_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION_C      0
#define DMA_IP_VS_0_PBCFG_SW_MAJOR_VERSION_C                 1
#define DMA_IP_VS_0_PBCFG_SW_MINOR_VERSION_C                 0
#define DMA_IP_VS_0_PBCFG_SW_PATCH_VERSION_C                 0

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/
/* Check if Dma_Ip_VS_0_PBcfg.c file and Dma_Ip_Cfg.h file are of the same vendor */
#if (DMA_IP_VS_0_PBCFG_VENDOR_ID_C != DMA_IP_CFG_VENDOR_ID_H)
    #error "Dma_Ip_VS_0_PBcfg.c and Dma_Ip_Cfg.h have different vendor ids"
#endif

/* Check if Dma_Ip_VS_0_PBcfg.c file and Dma_Ip_Cfg.h file are of the same Autosar version */
#if ((DMA_IP_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION_C != DMA_IP_CFG_AR_RELEASE_MAJOR_VERSION_H) || \
     (DMA_IP_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION_C != DMA_IP_CFG_AR_RELEASE_MINOR_VERSION_H) || \
     (DMA_IP_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION_C != DMA_IP_CFG_AR_RELEASE_REVISION_VERSION_H) \
    )
    #error "AutoSar Version Numbers of Dma_Ip_VS_0_PBcfg.c and Dma_Ip_Cfg.h are different"
#endif

/* Check if Dma_Ip_VS_0_PBcfg.c file and Dma_Ip_Cfg.h file are of the same Software version */
#if ((DMA_IP_VS_0_PBCFG_SW_MAJOR_VERSION_C != DMA_IP_CFG_SW_MAJOR_VERSION_H) || \
     (DMA_IP_VS_0_PBCFG_SW_MINOR_VERSION_C != DMA_IP_CFG_SW_MINOR_VERSION_H) || \
     (DMA_IP_VS_0_PBCFG_SW_PATCH_VERSION_C != DMA_IP_CFG_SW_PATCH_VERSION_H) \
    )
    #error "Software Version Numbers of Dma_Ip_VS_0_PBcfg.c and Dma_Ip_Cfg.h are different"
#endif

/*==================================================================================================
*                                        LOCAL MACROS
==================================================================================================*/

/*==================================================================================================
                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
==================================================================================================*/

/*==================================================================================================
                                       LOCAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
                                       LOCAL VARIABLES
==================================================================================================*/

/*==================================================================================================
                                       GLOBAL CONSTANTS
==================================================================================================*/

/*==================================================================================================
                                       GLOBAL VARIABLES
==================================================================================================*/

/*==================================================================================================
                                   LOCAL FUNCTION PROTOTYPES
==================================================================================================*/

/*==================================================================================================
                                       LOCAL FUNCTIONS
==================================================================================================*/

/*==================================================================================================
                                       GLOBAL FUNCTIONS
==================================================================================================*/




#define MCL_START_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"
/* DMA Logic Instance Configuration */
const Dma_Ip_LogicInstanceConfigType LogicInstance0ConfigPB_VS_0 =
{
    {
        /* uint32 logicInstId; */ DMA_LOGIC_INST_0,
        /* uint8 hwVersId;     */ DMA_IP_HARDWARE_VERSION_2,
        /* uint8 hwInst;       */ DMA_IP_HW_INST_0,
    },
    /* boolean EnDebug; */                 (boolean)FALSE,
    /* boolean EnRoundRobin; */            (boolean)FALSE,
    /* boolean EnHaltAfterError; */        (boolean)FALSE,
    /* boolean EnChLinking; */             (boolean)FALSE,
    /* boolean EnGlMasterIdReplication; */ (boolean)FALSE,
};

/* DMA Logic Instance Configuration Array */
const Dma_Ip_LogicInstanceConfigType * const Dma_Ip_paxLogicInstanceConfigArrayPB_VS_0[DMA_IP_NOF_CFG_LOGIC_INSTANCES] =
{
    &LogicInstance0ConfigPB_VS_0,
};

#define MCL_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"



#define MCL_START_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"
/* DMA Logic Channel Configurations */
/* DMA Logic Channel 0 */
const Dma_Ip_GlobalConfigType LogicChannel0GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART0_RX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO0,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};
/* DMA Logic Channel 1 */
const Dma_Ip_GlobalConfigType LogicChannel1GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART1_RX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO1,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};
/* DMA Logic Channel 2 */
const Dma_Ip_GlobalConfigType LogicChannel2GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART2_RX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO2,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};
/* DMA Logic Channel 3 */
const Dma_Ip_GlobalConfigType LogicChannel3GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART0_TX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO3,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};
/* DMA Logic Channel 4 */
const Dma_Ip_GlobalConfigType LogicChannel4GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART1_TX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO4,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};
/* DMA Logic Channel 5 */
const Dma_Ip_GlobalConfigType LogicChannel5GlobalConfigPB_VS_0 =
{
    {
        /* boolean EnMasterIdReplication; */ (boolean)FALSE,
        /* boolean EnBufferedWrites; */      (boolean)FALSE,
    }, /* Control */
    {
        /* uint8 SourceMux; */               DMA_IP_REQ_MUX0_LPUART2_TX,
        /* boolean EnSourceMux; */           (boolean)TRUE,
        /* boolean EnTriggerMux; */          (boolean)FALSE,
        /* boolean EnRequest; */             (boolean)TRUE,
    }, /* Request */
    {
        /* boolean EnErrorInt; */            (boolean)FALSE,
    }, /* Interrupt */
    {
        /* uint8 Group; */                   0U,
        /* uint8 Level; */                   DMA_IP_LEVEL_PRIO5,
        /* boolean EnPreemption; */          (boolean)FALSE,
        /* boolean DisPreempt; */            (boolean)FALSE,
    }, /* Priority */
};

/* DMA Logic Channel 0 */
const Dma_Ip_TransferConfigType LogicChannel0TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};
/* DMA Logic Channel 1 */
const Dma_Ip_TransferConfigType LogicChannel1TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};
/* DMA Logic Channel 2 */
const Dma_Ip_TransferConfigType LogicChannel2TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};
/* DMA Logic Channel 3 */
const Dma_Ip_TransferConfigType LogicChannel3TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};
/* DMA Logic Channel 4 */
const Dma_Ip_TransferConfigType LogicChannel4TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};
/* DMA Logic Channel 5 */
const Dma_Ip_TransferConfigType LogicChannel5TransferConfigPB_VS_0 =
{
    {
        /* uint32 ScatterGatherAddr; */    0U,
        /* uint32 DestinationStoreAddr; */ 0U,
        /* uint8 BandwidthControl; */      DMA_IP_BWC_ENGINE_NO_STALL,
        /* boolean EnStart; */             (boolean)FALSE,
        /* boolean EnMajorInt; */          (boolean)FALSE,
        /* boolean EnHalfMajorInt; */      (boolean)FALSE,
        /* boolean DisAutoHwRequest; */    (boolean)FALSE,
        /* boolean EnEndOfPacketSignal; */ (boolean)FALSE,
    }, /* Control */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Source */
    {
        /* uint32 addr; */         0U,
        /* sint32 lastAddrAdj; */  0,
        /* sint16 signedOffset; */ 0,
        /* uint8 transferSize; */  DMA_IP_TRANSFER_SIZE_1_BYTE,
        /* uint8 modulo; */        0U,
    }, /* Destination */
    {
        /* uint32 Size; */         0U,
        /* sint32 Offset; */       0,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
        /* boolean EnSrcOffset; */ (boolean)FALSE,
        /* boolean EnDstOffset; */ (boolean)FALSE,
    }, /* MinorLoop */
    {
        /* uint16 count; */        1U,
        /* uint8 LogicLinkCh; */   0U,
        /* boolean EnLink; */      (boolean)FALSE,
    }, /* MajorLoop */
};

#define MCL_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

#define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#define MCL_START_SEC_VAR_INIT_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"
/* DMA Hardware Channel 0 */
Dma_Ip_HwChannelStateType HwChannel0StatePB_VS_0;
/* DMA Hardware Channel 1 */
Dma_Ip_HwChannelStateType HwChannel1StatePB_VS_0;
/* DMA Hardware Channel 2 */
Dma_Ip_HwChannelStateType HwChannel2StatePB_VS_0;
/* DMA Hardware Channel 3 */
Dma_Ip_HwChannelStateType HwChannel3StatePB_VS_0;
/* DMA Hardware Channel 4 */
Dma_Ip_HwChannelStateType HwChannel4StatePB_VS_0;
/* DMA Hardware Channel 5 */
Dma_Ip_HwChannelStateType HwChannel5StatePB_VS_0;

#define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

#define MCL_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"
/* DMA Hardware Channel State and DMA Logic Channel Configuration Array */
Dma_Ip_HwChannelStateType * Dma_Ip_paxHwChannelStateArrayPB_VS_0[DMA_IP_NOF_CFG_LOGIC_CHANNELS] =
{
    &HwChannel0StatePB_VS_0,
    &HwChannel1StatePB_VS_0,
    &HwChannel2StatePB_VS_0,
    &HwChannel3StatePB_VS_0,
    &HwChannel4StatePB_VS_0,
    &HwChannel5StatePB_VS_0,
};

#define MCL_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

#define MCL_START_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#define MCL_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

#define MCL_START_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"
const Dma_Ip_LogicChannelConfigType LogicChannel0ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART0_RX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_0,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_0_Uart_Ip_DmaRxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel0GlobalConfigPB_VS_0,
    &LogicChannel0TransferConfigPB_VS_0,
    NULL_PTR,
};
const Dma_Ip_LogicChannelConfigType LogicChannel1ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART1_RX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_1,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_1_Uart_Ip_DmaRxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel1GlobalConfigPB_VS_0,
    &LogicChannel1TransferConfigPB_VS_0,
    NULL_PTR,
};
const Dma_Ip_LogicChannelConfigType LogicChannel2ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART2_RX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_2,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_2_Uart_Ip_DmaRxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel2GlobalConfigPB_VS_0,
    &LogicChannel2TransferConfigPB_VS_0,
    NULL_PTR,
};
const Dma_Ip_LogicChannelConfigType LogicChannel3ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART0_TX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_3,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_0_Uart_Ip_DmaTxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel3GlobalConfigPB_VS_0,
    &LogicChannel3TransferConfigPB_VS_0,
    NULL_PTR,
};
const Dma_Ip_LogicChannelConfigType LogicChannel4ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART1_TX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_4,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_1_Uart_Ip_DmaTxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel4GlobalConfigPB_VS_0,
    &LogicChannel4TransferConfigPB_VS_0,
    NULL_PTR,
};
const Dma_Ip_LogicChannelConfigType LogicChannel5ConfigPB_VS_0 =
{
    {
        /* uint32 LogicChId; */               DMA_LOGIC_CH_UART2_TX,
        /* uint8 HwVersId; */                 DMA_IP_HARDWARE_VERSION_2,
        /* uint8 HwInst; */                   DMA_IP_HW_INST_0,
        /* uint8 HwChId; */                   DMA_IP_HW_CH_5,
        /* Dma_Ip_Callback IntCallback; */    Lpuart_2_Uart_Ip_DmaTxCompleteCallback,
        /* Dma_Ip_Callback ErrIntCallback; */ NULL_PTR,
    },  /* Dma_Ip_LogicChannelIdType */
    &LogicChannel5GlobalConfigPB_VS_0,
    &LogicChannel5TransferConfigPB_VS_0,
    NULL_PTR,
};

const Dma_Ip_LogicChannelConfigType * const Dma_Ip_paxLogicChannelConfigArrayPB_VS_0[DMA_IP_NOF_CFG_LOGIC_CHANNELS] =
{
    &LogicChannel0ConfigPB_VS_0,
    &LogicChannel1ConfigPB_VS_0,
    &LogicChannel2ConfigPB_VS_0,
    &LogicChannel3ConfigPB_VS_0,
    &LogicChannel4ConfigPB_VS_0,
    &LogicChannel5ConfigPB_VS_0,
};

/* DMA Initialization Structure */
const Dma_Ip_InitType Dma_Ip_xDmaInitPB_VS_0 =
{
    /* Dma_Ip_HwChannelStateType ** HwChStateArray */                          &Dma_Ip_paxHwChannelStateArrayPB_VS_0[0U],          /* Static */
    /* const Dma_Ip_LogicChannelConfigType * const LogicChConfigArray   */     &Dma_Ip_xLogicChannelResetConfig,                   /* Static */
    /* const Dma_Ip_LogicChannelConfigType * const * LogicChConfigArray */     &Dma_Ip_paxLogicChannelConfigArrayPB_VS_0[0U],      /* Static */
    /* const Dma_Ip_LogicInstanceConfigType * const LogicInstConfigArray   */  &Dma_Ip_xLogicInstanceResetConfig,                  /* Static */
    /* const Dma_Ip_LogicInstanceConfigType * const * LogicInstConfigArray */  &Dma_Ip_paxLogicInstanceConfigArrayPB_VS_0[0U],     /* Static */
};

#define MCL_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"



#ifdef __cplusplus
}
#endif

/*==================================================================================================
 *                                        END OF FILE
==================================================================================================*/
