1、增加ADC采集功能

.cproject

@@ -36,6 +36,7 @@
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@@ -222,6 +224,7 @@
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@@ -323,6 +326,7 @@
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@@ -408,6 +412,7 @@
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@@ -768,7 +776,7 @@
 	<storageModule moduleId="org.eclipse.embsys" parent_project="true" register_architecture="" register_board="---  none ---" register_chip="" register_core="" register_vendor=""/>
 	<storageModule moduleId="refreshScope"/>
 	<storageModule moduleId="com.nxp.s32ds.cle.uct.core">
-		<sdkComponents>platform.driver.osif;platform.driver.det;platform.driver.rte_can;platform.driver.rte_dio;platform.driver.rte_mcu;platform.driver.rte_mcl;platform.driver.rte_port;platform.driver.rte_uart;platform.os.freertos;platform.driver.Can;platform.driver.CanIf;platform.driver.dio;platform.driver.ecum;platform.driver.mcu;platform.driver.mcl;platform.driver.Platform;platform.driver.port;platform.driver.uart;platform.driver.clock</sdkComponents>
+		<sdkComponents>platform.driver.det;platform.driver.rte_can;platform.driver.rte_dio;platform.driver.rte_mcu;platform.driver.rte_mcl;platform.driver.rte_port;platform.driver.rte_uart;platform.os.freertos;platform.driver.Can;platform.driver.CanIf;platform.driver.dio;platform.driver.ecum;platform.driver.mcu;platform.driver.mcl;platform.driver.Platform;platform.driver.port;platform.driver.uart;platform.driver.clock;platform.driver.osif;platform.driver.port_ip;platform.driver.spi;platform.driver.rte_spi;platform.driver.rte_adc;platform.driver.adc</sdkComponents>
 		<COND_TOOLCHAIN_ADD_REMOVE_COMPONENTS_OPTION>true</COND_TOOLCHAIN_ADD_REMOVE_COMPONENTS_OPTION>
 		<COND_TOOLCHAIN_COPY_SOURCES>true</COND_TOOLCHAIN_COPY_SOURCES>
 	</storageModule>

RTD/include/Adc.h

@@ -0,0 +1,1733 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+#ifndef ADC_H
+#define ADC_H
+
+/**
+*   @file    Adc.h
+*   @implements      Adc.h_Artifact
+*   @addtogroup adc_driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Mcal.h"
+#include "Adc_Cfg.h"
+#include "Adc_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID                           43
+#define ADC_MODULE_ID                           123
+#define ADC_AR_RELEASE_MAJOR_VERSION            4
+#define ADC_AR_RELEASE_MINOR_VERSION            4
+#define ADC_AR_RELEASE_REVISION_VERSION         0
+#define ADC_SW_MAJOR_VERSION                    1
+#define ADC_SW_MINOR_VERSION                    0
+#define ADC_SW_PATCH_VERSION                    0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if source file and Mcal header file are of the same AutoSar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc.h and Mcal.h are different"
+#endif
+#endif
+
+/* Check if source file and ADC configuration header file are of the same vendor */
+#if (ADC_VENDOR_ID != ADC_VENDOR_ID_CFG)
+#error "Adc.h and Adc_Cfg.h have different vendor ids"
+#endif
+
+/* Check if source file and ADC configuration header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION != ADC_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (ADC_AR_RELEASE_MINOR_VERSION != ADC_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (ADC_AR_RELEASE_REVISION_VERSION != ADC_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+#error "AutoSar Version Numbers of Adc.h and Adc_Cfg.h are different"
+#endif
+
+/* Check if source file and ADC configuration header file are of the same software version */
+#if ((ADC_SW_MAJOR_VERSION != ADC_SW_MAJOR_VERSION_CFG) || \
+     (ADC_SW_MINOR_VERSION != ADC_SW_MINOR_VERSION_CFG) || \
+     (ADC_SW_PATCH_VERSION != ADC_SW_PATCH_VERSION_CFG) \
+    )
+#error "Software Version Numbers of Adc.h and Adc_Cfg.h are different"
+#endif
+
+/* Check if source file and Adc Types header file are of the same vendor */
+#if (ADC_VENDOR_ID != ADC_VENDOR_ID_TYPES_H)
+#error "Adc.h and Adc_Types.h have different vendor ids"
+#endif
+
+/* Check if source file and Adc Types header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION != ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION != ADC_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION != ADC_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+#error "AutoSar Version Numbers of Adc.h and Adc_Types.h are different"
+#endif
+
+/* Check if source file and Adc Types header file are of the same software version */
+#if ((ADC_SW_MAJOR_VERSION != ADC_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION != ADC_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION != ADC_SW_PATCH_VERSION_TYPES_H) \
+    )
+#error "Software Version Numbers of Adc.h and Adc_Types.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/**
+*       Development errors.
+*       The following errors shall be detectable by the ADC module depending on its
+*       configuration (development / production mode).
+*
+*       All error codes
+*
+*/
+
+/**
+* @brief   API service used without Adc module initialization.
+* */
+#define ADC_E_UNINIT                                 ((uint8)0x0AU)
+
+/**
+* @brief   Adc module is busy with a running operation.
+* */
+#define ADC_E_BUSY                                   ((uint8)0x0BU)
+
+/**
+* @brief   Adc module is in idle state.
+* */
+#define ADC_E_IDLE                                   ((uint8)0x0CU)
+
+/**
+* @brief   The ADC module is already initialized.
+* */
+#define ADC_E_ALREADY_INITIALIZED                    ((uint8)0x0DU)
+
+/**
+* @brief   The ADC module is not properly configured.
+* */
+#define ADC_E_PARAM_CONFIG                           ((uint8)0x0EU)
+
+/**
+* @brief   API service is called using an invalid pointer (e.g. the pointer should not be NULL).
+* */
+#define ADC_E_PARAM_POINTER                          ((uint8)0x14U)
+
+/**
+* @brief   API service used with an invalid ADC group.
+* */
+#define ADC_E_PARAM_GROUP                            ((uint8)0x15U)
+
+/**
+* @brief   API service used with an invalid ADC Conversion Mode.
+* */
+#define ADC_E_WRONG_CONV_MODE                        ((uint8)0x16U)
+
+/**
+* @brief   API service used with an invalid ADC Trigger Source.
+* */
+#define ADC_E_WRONG_TRIGG_SRC                        ((uint8)0x17U)
+
+/**
+* @brief   Check the notification capability of a group.
+* */
+#define ADC_E_NOTIF_CAPABILITY                       ((uint8)0x18U)
+
+/**
+* @brief   API service used without initializing the buffer.
+* */
+#define ADC_E_BUFFER_UNINIT                          ((uint8)0x19U)
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+/**
+* @brief   One or more ADC group/channel not in IDLE state.
+* */
+#define ADC_E_NOT_DISENGAGED                        ((uint8)0x1AU)
+
+/**
+* @brief   Unsupported power state request.
+* */
+#define ADC_E_POWER_STATE_NOT_SUPPORTED             ((uint8)0x1BU)
+
+/**
+* @brief   Requested power state can not be reached directly.
+* */
+#define ADC_E_TRANSITION_NOT_POSSIBLE               ((uint8)0x1CU)
+
+/**
+* @brief   ADC not prepared for target power state.
+* */
+#define ADC_E_PERIPHERAL_NOT_PREPARED               ((uint8)0x1DU)
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+/**
+* @brief    The Adc_StartGroupConversion and Adc_EnableHardwareTrigger services can not queue
+            another conversion (queue is full)
+*/
+#define ADC_E_QUEUE_FULL                             ((uint8)0x20U)
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+/**
+* @brief   An error occurred when the Adc_SetHwUnitPowerMode services is used.
+* */
+#define ADC_E_SET_HW_UNIT_POWER_MODE                 ((uint8)0x21U)
+#endif
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+/**
+* @brief   Wrong trigger source to be used for the group.
+* */
+#define ADC_E_PARAM_TRIGGER                          ((uint8)0x22U)
+#endif
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/**
+* @brief   Adc_EnableChannel or Adc_DisableChannel services called with a wrong channel.
+* */
+#define ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP       ((uint8)0x23U)
+/**
+* @brief   Adc_EnableChannel or Adc_DisableChannel services called with a wrong channel identifier (ID).
+* */
+#define ADC_E_WRONG_ENABLE_CH_DISABLE_CH_ID          ((uint8)0x24U)
+#endif
+
+#if (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON)
+/**
+* @brief   Adc_ConfigureThreshold service is called using wrong values.
+* */
+#define ADC_E_WRONG_CONF_THRHLD_VALUE                ((uint8)0x25U)
+#endif
+
+/**
+* @brief   API service called using a wrong ADC unit.
+* */
+#define ADC_E_PARAM_UNIT                             ((uint8)0x26U)
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+/**
+* @brief   API service called using a wrong CTU trigger.
+* */
+#define ADC_E_WRONG_CTU_TRIGGER                    ((uint8)0x28U)
+/**
+* @brief   API service called using a wrong CTU CLCR trigger.
+* */
+#define ADC_E_WRONG_CTU_CLCR_TRIGGER               ((uint8)0x29U)
+#endif
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   Adc_SetClockMode service called using an invalid clock mode.
+* */
+#define ADC_E_INVALID_CLOCK_MODE                     ((uint8)0x29U)
+#endif
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+/**
+* @brief   Adc_SetChannel service called using an invalid channel list.
+* */
+#define ADC_E_PARAM_CHANNEL                          ((uint8)0x2AU)
+#endif
+
+/**
+* @brief   An error occurred if the timeout counter variable has expired when checking status flags.
+* */
+#define ADC_E_TIMEOUT                                ((uint8)0x2BU)
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+/**
+* @brief   Error when a function which works only in CTU Control Mode is called when CTU control mode is disabled.
+* */
+#define ADC_E_CONTROL_MODE_DISABLED                  ((uint8)0x30U)
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+#define ADC_E_BUFFER_UNINIT_LIST                     ((uint32)0x00000001U)
+#define ADC_E_WRONG_TRIGG_SRC_LIST                   ((uint32)0x00000002U)
+#define ADC_E_QUEUE_FULL_LIST                        ((uint32)0x00000004U)
+#define ADC_E_WRONG_CONV_MODE_LIST                   ((uint32)0x00000008U)
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+#define ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP_LIST  ((uint32)0x00000010U)
+#define ADC_E_WRONG_ENABLE_CH_DISABLE_CH_ID_LIST     ((uint32)0x00000020U)
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+
+/**
+          All AUTOSAR API's service IDs
+*/
+
+/**
+* @brief API service ID for Adc_Init function
+* */
+#define ADC_INIT_ID                                  0x00U
+
+/**
+* @brief API service ID for Adc_DeInit function
+* */
+#define ADC_DEINIT_ID                                0x01U
+
+/**
+* @brief API service ID for Adc_StartGroupConversion function
+* */
+#define ADC_STARTGROUPCONVERSION_ID                  0x02U
+
+/**
+* @brief API service ID for Adc_StopGroupConversion function
+* */
+#define ADC_STOPGROUPCONVERSION_ID                   0x03U
+
+/**
+* @brief API service ID for Adc_ReadGroup function
+* */
+#define ADC_VALUEREADGROUP_ID                        0x04U
+
+/**
+* @brief API service ID for Adc_EnableHardwareTrigger function
+* */
+#define ADC_ENABLEHARDWARETRIGGER_ID                 0x05U
+
+/**
+* @brief API service ID for Adc_DisableHardwareTrigger function
+* */
+#define ADC_DISABLEHARDWARETRIGGER_ID                0x06U
+
+/**
+* @brief API service ID for Adc_EnableGroupNotification function
+* */
+#define ADC_ENABLEGROUPNOTIFICATION_ID               0x07U
+
+/**
+* @brief API service ID for Adc_DisableGroupNotification function
+* */
+#define ADC_DISABLEGROUPNOTIFICATION_ID              0x08U
+
+/**
+* @brief API service ID for Adc_GetGroupStatus function
+* */
+#define ADC_GETGROUPSTATUS_ID                        0x09U
+
+/**
+* @brief API service ID for Adc_GetVersionInfo function
+* */
+#define ADC_GETVERSIONINFO_ID                        0x0AU
+
+/**
+* @brief API service ID for Adc_GetStreamLastPointer function
+* */
+#define ADC_GETSTREAMLASTPOINTER_ID                  0x0BU
+
+/**
+* @brief API service ID for Adc_SetupResultBuffer function
+* */
+#define ADC_SETUPRESULTBUFFER_ID                     0x0CU
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+/**
+* @brief API service ID for Adc_SetPowerState function
+* */
+#define ADC_SETPOWERSTATE_ID                         0x10U
+
+/**
+* @brief API service ID for Adc_GetCurrentPowerState function
+* */
+#define ADC_GETCURRENTPOWERSTATE_ID                  0x11U
+
+/**
+* @brief API service ID for Adc_GetTargetPowerState function
+* */
+#define ADC_GETTARGETPOWERSTATE_ID                   0x12U
+
+/**
+* @brief API service ID for Adc_PreparePowerState function
+* */
+#define ADC_PREPAREPOWERSTATE_ID                     0x13U
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+/**
+*        All Autosar Extension API's service IDs
+**       NOTE: Parameters used when raising an error/exception
+*/
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+/**
+* @brief API service ID for Adc_HwResultReadGroup function
+* */
+#define ADC_HWRESULTREADGROUP_ID                     0x20U
+/**
+* @brief API service ID for Adc_EnableCTUTrigge function
+* */
+#define ADC_ENABLECTUTRIGGER_ID                      0x21U
+/**
+* @brief API service ID for Adc_DisableCTUTrigger function
+* */
+#define ADC_DISABLECTUTRIGGER_ID                     0x22U
+#endif
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+/**
+* @brief API service ID for Adc_SetHwUnitPowerMode function
+* */
+#define ADC_SET_HW_UNIT_POWER_MODE_ID                0x23U
+#if (ADC_BCTU_AVAILABLE == STD_ON)
+/**
+* @brief API service ID for Adc_CtuSetPowerMode function
+* */
+#define ADC_CTU_SET_POWER_MODE_ID                    0x24U
+#endif /* (ADC_BCTU_AVAILABLE == STD_ON) */
+#endif /* (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief API service ID for Adc_SetClockMode function
+* */
+#define ADC_SETCLOCKMODE_ID                          0x25U
+#endif
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/**
+* @brief API service ID for Adc_EnableChannel function
+* */
+#define ADC_ENABLE_CHANNEL_ID                        0x26U
+/**
+* @brief API service ID for Adc_DisableChannel function
+* */
+#define ADC_DISABLE_CHANNEL_ID                       0x27U
+#endif
+
+#if (ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON)
+/**
+* @brief API service ID for Adc_GetInjectedConversionStatus function
+* */
+#define ADC_GETINJECTEDCONVERSIONSTATUS_ID           0x28U
+#endif
+
+#if (ADC_CALIBRATION == STD_ON)
+/**
+* @brief API service ID for Adc_Calibrate function
+* */
+#define ADC_CALIBRATE_ID                             0x29U
+#endif
+
+#if (ADC_SELF_TEST == STD_ON)
+#define ADC_SELFTEST_ID                              0x2AU
+#endif
+
+#if (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON)
+/**
+* @brief API service ID for Adc_ConfigureThreshold function
+* */
+#define ADC_CONFIGURE_THRESHOLD_ID                   0x2BU
+#endif
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+/**
+* @brief API service ID for Adc_CtuWriteTriggerEnableMask function
+* */
+#define CTU_SET_WRITE_TRIG_EN_MASK_ID                (0x2CU)
+/**
+* @brief API service ID for Adc_CtuSetTriggerEnable function
+* */
+#define CTU_SET_TRIGGER_ENABLE_ID                    (0x2DU)
+/**
+* @brief API service ID for Adc_CtuSetTriggerAdcCmdAddress function
+* */
+#define CTU_SET_TRIGGER_ADC_CMD_ADDRESS_ID           (0x2EU)
+/**
+* @brief API service ID for Adc_CtuSetTriggerCompare function
+* */
+#define CTU_SET_TRIGGER_COMPARE_ID                   (0x2FU)
+#endif
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+/**
+* @brief API service ID for Adc_SetChannel function
+* */
+#define ADC_SETCHANNEL_ID                            (0x30U)
+#endif
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+/**
+* @brief API service ID for Adc_EnableCtuControlMode function
+* */
+#define ADC_ENABLE_CTU_CONTROL_MODE_ID               (0x32U)
+/**
+* @brief API service ID for Adc_DisableCtuControlMode function
+* */
+#define ADC_DISABLE_CTU_CONTROL_MODE_ID              (0x33U)
+
+#define ADC_CTU_ENABLE_HW_TRIGGER_ID                 (0x34U)
+#define ADC_CTU_DISABLE_HW_TRIGGER_ID                (0x35U)
+#define ADC_CTU_START_CONVERSION_ID                  (0x36U)
+#define ADC_CTU_READ_CONV_DATA_ID                    (0x37U)
+#define ADC_CTU_READ_CONV_RESULT_ID                  (0x38U)
+#define ADC_CTU_READ_FIFO_DATA_ID                    (0x39U)
+#define ADC_CTU_READ_FIFO_RESULT_ID                  (0x3AU)
+#define ADC_CTU_SET_FIFO_WATERMARK_ID                (0x3BU)
+#define ADC_CTU_ENABLE_NOTIFICATION_ID               (0x3CU)
+#define ADC_CTU_DISABLE_NOTIFICATION_ID              (0x3DU)
+#define ADC_CTU_SET_LIST_POINTER_ID                  (0x3EU)
+#define ADC_CTU_SET_LIST_ID                          (0x3FU)
+#define ADC_CTU_STOP_LOOP_CONVERSION_ID              (0x40U)
+#define ADC_CTU_MASTER_RELOAD_ID                     (0x41U)
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+#define ADC_ENABLE_READ_RAW_DATA_ID                  (0x42U)
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#ifdef ADC_WDG_SUPPORTED
+#define ADC_ENABLEWDGNOTIFICATION_ID                 (0x43U)
+#define ADC_DISABLEWDGNOTIFICATION_ID                (0x44U)
+#endif /* ADC_WDG_SUPPORTED */
+
+#if (ADC_ENABLE_TEMPSENSE_API == STD_ON)
+#define ADC_TEMPSENSE_CALCULATE_TEMP_ID              (0x4AU)
+#define ADC_TEMPSENSE_GET_TEMP_ID                    (0x4BU)
+#endif /* (ADC_ENABLE_TEMPSENSE_API == STD_ON) */
+
+/**
+* @brief          Mask used to verify the DATA registers content.
+*/
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+#define ADC_DATA_MASK_U16         (0xFFFFU)
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                 GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+/**
+* @brief          Used to point the configuration structure.
+*/
+extern const Adc_ConfigType * Adc_pCfgPtr[ADC_MAX_PARTITIONS];
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+/**
+* @brief          Clock mode in use
+*/
+extern Adc_SelectPrescalerType Adc_eClockMode[ADC_MAX_PARTITIONS];
+#endif /*if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)*/
+#endif /*if (ADC_DUAL_CLOCK_MODE == STD_ON)*/
+
+extern Adc_GroupStatusType Adc_aGroupStatus[ADC_MAX_GROUPS];
+extern Adc_UnitStatusType Adc_aUnitStatus[ADC_MAX_HW_UNITS];
+#if (ADC_SETCHANNEL_API == STD_ON)
+extern Adc_RuntimeGroupChannelType Adc_aRuntimeGroupChannel[ADC_MAX_GROUPS];
+#endif /*(ADC_SETCHANNEL_API == STD_ON)*/
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#if (ADC_PRECOMPILE_SUPPORT == STD_ON)
+    #define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+    #include "Adc_MemMap.h"
+    extern const Adc_ConfigType * const Adc_ConfigVariantPredefined[ADC_MAX_PARTITIONS];
+    #define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+    #include "Adc_MemMap.h"
+#else
+    #define ADC_START_SEC_CONST_UNSPECIFIED
+    #include "Adc_MemMap.h"
+
+    ADC_CONFIG_EXT
+
+    #define ADC_STOP_SEC_CONST_UNSPECIFIED
+    #include "Adc_MemMap.h"
+#endif /* (ADC_PRECOMPILE_SUPPORT == STD_ON) */
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Initializes the ADC hardware unit and the driver.
+* @details        This function will initialize both the ADC HW unit and the driver structures.
+*
+* @param[in]      pConfigPtr   Pointer to configuration set in Variant PB
+*                             (Variant PC requires a NULL_PTR).
+* @return         void
+*
+* @implements  Adc_Init_Activity
+*/
+void Adc_Init
+(
+    const Adc_ConfigType * ConfigPtr
+);
+
+/**
+* @brief          Initializes the group specific ADC result buffer pointer as
+*                 configured to point to the pDataBufferPtr address which is
+*                 passed as parameter.
+* @details        Initializes ADC driver with the group specific result buffer
+*                 start address where the conversion results will be stored.
+*                 The application has to ensure that the application buffer,
+*                 where pDataBufferPtr points to, can hold all the conversion
+*                 results of the specified group. The initialization with
+*                 Adc_SetupResultBuffer is required after reset, before a group
+*                 conversion can be started.
+*
+* @param[in]      Group           Numeric ID of requested ADC channel group.
+* @param[in]      pDataBufferPtr   Pointer to result data buffer
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Result buffer pointer initialized correctly.
+*                 E_NOT_OK:       Operation failed or development error
+*                                 occurred.
+*
+* @implements  Adc_SetupResultBuffer_Activity
+*/
+Std_ReturnType Adc_SetupResultBuffer
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * const DataBufferPtr
+);
+
+#if (ADC_DEINIT_API == STD_ON)
+/**
+* @brief          Returns all ADC HW Units to a state comparable to their
+*                 power on reset state.
+* @details        Returns all ADC HW Units to a state comparable to their
+*                 power on reset state, and de-initialize the ADC MCAL driver.
+*
+* @return         void
+*
+* @implements  Adc_DeInit_Activity
+*/
+void Adc_DeInit(void);
+#endif /* ADC_DEINIT_API == STD_ON */
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/**
+* @brief          Starts the conversion of all channels of
+*                 the requested ADC Channel group.
+* @details        This function will start the SW conversion of all channels
+*                 of the requested ADC channel group.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_StartGroupConversion_Activity
+*/
+void Adc_StartGroupConversion
+(
+    Adc_GroupType Group
+);
+
+/**
+* @brief          Stops the conversion of all channels of the requested ADC
+*                 Channel group.
+* @details        This function will stop the SW conversion of all channels
+*                 of the requested ADC channel group.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_StopGroupConversion_Activity
+*/
+void Adc_StopGroupConversion
+(
+    Adc_GroupType Group
+);
+#endif /* ADC_ENABLE_START_STOP_GROUP_API == STD_ON */
+
+#if (ADC_READ_GROUP_API == STD_ON)
+/**
+* @brief          Reads the group conversion results.
+* @details        Reads the group conversion results of the last completed
+*                 conversion round of the requested group and stores the
+*                 channel values starting at the pDataBufferPtr address.
+*                 The group channel values are stored in ascending channel
+*                 number order (in contrast to the storage layout of the
+*                 result buffer if streaming access is configured).
+*
+* @param[in]      Group          Numeric ID of requested ADC Channel group.
+* @param[in]      pDataBufferPtr  ADC results of all channels of the selected group
+*                                are stored in the data buffer addressed with the pointer.
+* @return         Std_ReturnType Standard return type.
+*                 E_OK:          results are available and written to the
+*                                data buffer.
+*                 E_NOT_OK:      no results are available or development
+*                                error occurred.
+*
+* @implements  Adc_ReadGroup_Activity
+*/
+Std_ReturnType Adc_ReadGroup
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * DataBufferPtr
+);
+#endif /* ADC_READ_GROUP_API == STD_ON */
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+/**
+* @brief        Read the raw result data from an ADC unit.
+* @details      Read the raw result data from an ADC unit.
+*               Intended for reading ADC results directly from ADC registers 
+*               and can eliminate surplus interrupts if there are more triggered 
+*               measurements than FIFO length.
+*               Measured values remain in ADC result registers(user must ensure 
+*               that they are not overwritten).
+*
+* @param[in]    Unit           Adc unit used. Recommended to use generated define for Adc Logical Unit Id.
+* @param[in]    ChansArray     List of channels for which results to be read
+* @param[in]    NumItems       Number of results to read
+* @param[out]   DataBufferPtr  Destination pointer in which the results will be written
+*
+* @return         void
+*
+* @implements  Adc_ReadRawData_Activity
+*/
+void Adc_ReadRawData
+(
+    Adc_HwUnitType Unit,
+    const Adc_ChannelType * const ChansArray,
+    uint8 NumItems,
+    Adc_ValueGroupType * const DataBufferPtr
+);
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+/**
+* @brief          Enables the hardware trigger for the requested ADC Channel group.
+* @details        This function will enable the HW trigger source for the requested
+*                 ADC channel group. This function does set the CTU register for all
+*                 platform that have the CTU Hw Unit.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_EnableHardwareTrigger_Activity
+*/
+void Adc_EnableHardwareTrigger
+(
+    Adc_GroupType Group
+);
+
+/**
+* @brief          Disables the hardware trigger for the requested ADC Channel group.
+* @details        This function will disable the HW trigger source for the requested
+*                 ADC channel group.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_DisableHardwareTrigger_Activity
+*/
+void Adc_DisableHardwareTrigger
+(
+    Adc_GroupType Group
+);
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+/**
+* @brief          Enables the notification mechanism for the requested ADC
+*                 channel group.
+* @details        This function will enable the notification mechanism only for
+*                 the requested ADC channel group.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_EnableGroupNotification_Activity
+*/
+void Adc_EnableGroupNotification
+(
+    Adc_GroupType Group
+);
+
+/**
+* @brief          Disables the notification mechanism for the requested ADC
+*                 channel group.
+* @details        This function will disable the notification mechanism only for
+*                 the requested ADC channel group.
+*
+* @param[in]      Group       Numeric ID of requested ADC channel group.
+* @return         void
+*
+* @implements  Adc_DisableGroupNotification_Activity
+*/
+void Adc_DisableGroupNotification
+(
+    Adc_GroupType Group
+);
+#endif /* ADC_GRP_NOTIF_CAPABILITY == STD_ON */
+
+/**
+* @brief          Returns the conversion status of the requested ADC Channel group.
+* @details        This function will return the conversion status of the requested
+*                 ADC channel group.
+*
+* @param[in]      Group             Numeric ID of requested ADC channel group.
+* @return         Adc_StatusType    Conversion status for the requested group.
+*                 ADC_IDLE          in case of errors.
+*                 conversion status in case of no errors.
+*
+* @implements  Adc_GetGroupStatus_Activity
+*/
+Adc_StatusType Adc_GetGroupStatus
+(
+    Adc_GroupType Group
+);
+
+/**
+* @brief          Returns the number of valid samples per channel.
+* @details        Returns the number of valid samples per channel, stored in
+*                 the result buffer. Reads a pointer, pointing to a position
+*                 in the group result buffer. With the pointer position, the
+*                 results of all group channels of the last completed conversion
+*                 round can be accessed. With the pointer and the return value,
+*                 all valid group conversion results can be accessed (the user
+*                 has to take the layout of the result buffer into account).
+*
+* @param[in]      Group              Numeric ID of requested ADC channel group.
+* @param[out]     PtrToSamplePtr     Pointer to result buffer pointer.
+*
+* @return         Adc_StreamNumSampleType Number of valid samples per channel.
+*                 0                 in case of errors.
+*                 >0                Number of valid samples per channel.
+*
+* @implements  Adc_GetStreamLastPointer_Activity
+*/
+Adc_StreamNumSampleType Adc_GetStreamLastPointer
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType ** PtrToSamplePtr
+);
+
+#if (ADC_VERSION_INFO_API == STD_ON)
+/**
+* @brief          Returns the version information of this module.
+* @details        Returns the version information of this module.
+*
+* @param[out]     pVersionInfo    Pointer to where to store the version
+*                                 information of this module.
+*                 structure       in case of no errors.
+*
+* @implements  Adc_GetVersionInfo_Activity
+*/
+void Adc_GetVersionInfo
+(
+    Std_VersionInfoType * versioninfo
+);
+#endif /* ADC_VERSION_INFO_API == STD_ON */
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+/**
+* @brief          Set the ADC mode either to powerdown or normal.
+* @details        Set the ADC either to powerdown or normal mode.
+*
+* @param[in]      Unit            Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+* @param[in]      SetPowerMode    Power mode to set: normal or powerdown.
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Transition successful.
+*                 E_NOT_OK:       Transition unsuccessful.
+*
+* @implements  Adc_SetHwUnitPowerMode_Activity
+*/
+Std_ReturnType Adc_SetHwUnitPowerMode
+(
+    Adc_HwUnitType Unit,
+    Adc_SetPowerModeType SetPowerMode
+);
+
+#if (ADC_BCTU_AVAILABLE == STD_ON)
+/**
+* @brief   Function to set BCTU/CTU power mode.
+*
+* @details Set BCTU/CTU power mode.
+*
+* @param[in] CtuUnit   Bctu/Ctu hardware unit. Recommended to use generated define for Bctu/Ctu Logical Unit Id.
+* @param[in] State     Power state to be set
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Transition successful.
+*                 E_NOT_OK:       Transition unsuccessful.
+*
+* @implements  Adc_CtuSetPowerMode_Activity
+*/
+Std_ReturnType Adc_CtuSetPowerMode
+(
+    Adc_HwUnitType CtuUnit,
+    Adc_PowerStateType State
+);
+#endif /* (ADC_BCTU_AVAILABLE == STD_ON) */
+#endif /* (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) */
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+/**
+* @brief          Enable the TriggerSource for group selected by Group parameter.
+* @details        This Autosar Extension API is used to enable any one of the configured
+*                 TriggerSource of the Group. When this Autosar Extension API is used to
+*                 enable the trigger source the CTU interrupt will be disabled by the driver.
+*                 So user has to call the Autosar Extension API Adc_HwResultReadGroup to read
+*                 the converted result from the ADC hardware register.
+*
+* @param[in]      Group            Index of group.
+* @param[in]      TriggerSource    Trigger source to be used for the group.
+*                                  (Configuration file should contain it for that group).
+* @return         void
+*
+* @implements  Adc_EnableCTUTrigger_Activity
+*/
+void Adc_EnableCTUTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType TriggerSource
+);
+
+/**
+* @brief          Disable the TriggerSource for group selected by Group parameter.
+* @details        This Autosar Extension API is used to disable the already enabled
+*                 TriggerSource of the Group.
+*
+* @param[in]      Group            Index of group.
+* @param[in]      TriggerSource    Trigger source to be disabled for the group.
+*                                  (Configuration file should contain it for that group).
+* @return         void
+*
+* @implements  Adc_DisableCTUTrigger_Activity
+*/
+void Adc_DisableCTUTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType TriggerSource
+);
+
+/**
+* @brief          Read the result of the hardware triggered groups conversion result.
+* @details        This Autosar Extension API is used to read the result of the hardware
+*                 triggered groups conversion result from the ADC hardware register
+*                 in this case the CTU interrupt will be disabled for the group.
+*                 The VALID bit CDR register will be cleared automatically when we read the results
+*                 from the channel data register. If the user calls Autosar Extension function
+*                 Adc_HwResultReadGroup() once again before the next conversion takes place, the
+*                 Adc_HwResultReadGroup() returns E_NOT_OK.
+*
+* @param[in]      Group      Index of group.
+* @param[in]      DataPtr    Pointer to a buffer which will be filled by the
+*                            conversion results.
+* @return         Std_ReturnType Standard return type.
+*                 E_OK:          results are available and written to the
+*                                data buffer.
+*                 E_NOT_OK:      no results are available or development
+*                                error occurred.
+*
+* @implements  Adc_HwResultReadGroup_Activity
+*/
+Std_ReturnType Adc_HwResultReadGroup
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * DataPtr
+);
+#endif /* ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON */
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/**
+ * @brief   Enable an individual channel configured in SW-triggered (non-injected) ADC Group at initialization
+ * @details Enable an individual channel configured in SW-triggered (non-injected) ADC Group at initialization
+ *          Use generated symbolic channel name defines (e.g. AdcChannel_0_0), because function assumes ChannelId to be in following format:
+ *          Logical channel id on bits until position defined by ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16, and for the rest the Logical Unit Id
+ *          The driver will not update the values in result buffers corresponding to disabled channels, keeping in the buffer the last results from when the channel was enabled.
+ *
+ * @param[in]  Adc_GroupType                Group logical ID or group symbolic name
+ * @param[in]  Adc_ChannelType              Symbolic name of channel
+ *
+ * @return         void.
+ *
+ * @implements      Adc_EnableChannel_Activity
+ */
+void Adc_EnableChannel
+(
+    Adc_GroupType Group,
+    Adc_ChannelType Channel
+);
+
+/**
+ * @brief   Disable an individual channel configured in SW-triggered (non-injected) ADC Group at initialization
+ * @details Disable an individual channel configured in SW-triggered (non-injected) ADC Group at initialization
+ *          Use generated symbolic channel name defines (e.g. AdcChannel_0_0), because function assumes ChannelId to be in following format:
+ *          Logical channel id on bits until position defined by ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16, and for the rest the Logical Unit Id
+ *          The driver will not update the values in result buffers corresponding to disabled channels, keeping in the buffer the last results from when the channel was enabled.
+ *
+ * @param[in]  Adc_GroupType                Group logical ID or group symbolic name
+ * @param[in]  Adc_ChannelType              Symbolic name of channel
+ *
+ * @return         void.
+ *
+ * @implements      Adc_DisableChannel_Activity
+ */
+void Adc_DisableChannel
+(
+    Adc_GroupType Group,
+    Adc_ChannelType Channel
+);
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+#if (ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON)
+/**
+* @brief          Get the injected conversions status.
+* @details        This function checks if an injected conversion (HW,SW) is ongoing
+*
+* @param[in]      Unit            Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+*
+* @return         Adc_StatusType  Status of the ADC HW unit.
+*                 ADC_IDLE:       SW,HW Injection or Hardware Trigger group are idle.
+*                 ADC_BUSY:       SW,HW Injection or Hardware Trigger is in progress.
+*
+* @implements  Adc_GetInjectedConversionStatus_Activity
+*/
+Adc_StatusType Adc_GetInjectedConversionStatus
+(
+    Adc_HwUnitType Unit
+);
+#endif /* ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON */
+
+#if (ADC_CALIBRATION == STD_ON)
+/**
+* @brief          Executes high accuracy calibration of a ADC HW unit.
+* @details        This function calibrates the ADC HW unit and updates calibration related registers
+*
+* @param[in]      Unit      Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+* @param[in]      pStatus   Status of the ADC HW unit calibration and
+*                           list of failed and passed tests.
+*
+* @return         void
+*
+* @implements  Adc_Calibrate_Activity
+*/
+void Adc_Calibrate
+(
+    Adc_HwUnitType Unit,
+    Adc_CalibrationStatusType * pStatus
+);
+#endif /* (ADC_CALIBRATION == STD_ON) */
+
+#if (ADC_SELF_TEST == STD_ON)
+/**
+* @brief          Executes hardware Self Test of a ADC HW unit.
+* @details        This function checks if the ADC HW unit is functioning correctly
+*
+* @param[in]      Unit      Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+*
+* @return         Std_ReturnType. Status of the ADC HW unit Self Test.
+*
+* @implements  Adc_SelfTest_Activity
+*/
+Std_ReturnType Adc_SelfTest
+(
+    Adc_HwUnitType Unit
+);
+#endif /* (ADC_SELF_TEST == STD_ON) */
+
+#if (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON)
+/**
+* @brief      Function to reconfigure High and Low thresholds for a given threshold control index.
+* @details    This function is used to reconfigure High and Low thresholds for a given threshold control index.
+*             Use generated symbolic name defines of threshold register (e.g. AdcThresholdControl_0_0), because function assumes ThresholdControlIndex to be in following format:
+*             Logical threshold id on bits until position defined by ADC_THRESHOLD_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16, and for the rest the Logical Unit Id
+*
+* @param[in]  ThresholdControlIndex       Symbolic name of threshold control
+* @param[in]  LowValue                    Low threshold value of the threshold control
+* @param[in]  HighValue                   High threshold value of the threshold control
+*
+* @return     void
+*
+* @implements      Adc_ConfigureThreshold_Activity
+*/
+void Adc_ConfigureThreshold
+(
+    Adc_ThresholdControlIndexType ThresholdControlIndex,
+    Adc_WdgThresholdValueType LowValue,
+    Adc_WdgThresholdValueType HighValue
+);
+#endif /*  ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON */
+
+#ifdef ADC_WDG_SUPPORTED
+/**
+ * @brief   Enable notification of a channel that has watchdog functionality configured at initialization
+ * @details Enable notification of a channel that has watchdog functionality configured at initialization
+ *          Use generated symbolic channel name defines (e.g. AdcChannel_0_0), because function assumes ChannelId to be in following format:
+ *          Logical channel id on bits until position defined by ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16, and for the rest the Logical Unit Id
+ *
+ * @param[in]  Adc_ChannelType              Symbolic name of channel
+ *
+ * @return         void.
+ *
+ * @implements      Adc_EnableWdgNotification_Activity
+ */
+void Adc_EnableWdgNotification
+(
+    Adc_ChannelType ChannelId
+);
+
+/**
+ * @brief   Disable notification of a channel that has watchdog functionality configured at initialization
+ * @details Disable notification of a channel that has watchdog functionality configured at initialization
+ *          Use generated symbolic channel name defines (e.g. AdcChannel_0_0), because function assumes ChannelId to be in following format:
+ *          Logical channel id on bits until position defined by ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16, and for the rest the Logical Unit Id
+ *
+ * @param[in]  Adc_ChannelType              Symbolic name of channel
+ *
+ * @return         void.
+ *
+ * @implements      Adc_DisableWdgNotification_Activity
+ */
+void Adc_DisableWdgNotification
+(
+    Adc_ChannelType ChannelId
+);
+#endif /* ADC_WDG_SUPPORTED */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief          Set the ADC clock prescaler if available and modify the conversion timings.
+* @details        This function sets the ADC clock prescaler (Analog clock frequency selector)
+*
+* @param[in]      Prescaler      Normal or Alternate mode.
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           In case of successful settings.
+*                 E_NOT_OK:       In case of unsuccessful settings.
+*
+* @implements  Adc_SetClockMode_Activity
+*/
+Std_ReturnType Adc_SetClockMode
+(
+    Adc_SelectPrescalerType Prescaler
+);
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+/**
+* @brief   Function to set the trigger handler control registers of the CTU IPL.
+*
+* @details Full configurability of CTU THCR1 & THCR2 registers of the CTU IPL.
+*          This function has in input the CTU trigger (0...7) and the mask (8 bit)
+*          to enable the External Trigger and Timer output for that Trigger, without considering
+*          the ADC command output enable.
+*          See from the RM the THCR1 and THCR2 registers for the right Thcr_value to use.
+*
+* @note    The function Service ID[hex]: 0x35.
+*
+* @param[in]  Trigger      Index of the trigger: 0...7.
+* @param[in]  ThcrValue   THCRx mask value (only with bits for Ext. Trigger and Timer) for the selected input trigger.
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+*                 E_OK            In case of successful settings.
+*                 E_NOT_OK        In case of unsuccessful settings.
+*
+* @implements  Adc_CtuWriteTriggerEnableMask_Activity
+*/
+Std_ReturnType Adc_CtuWriteTriggerEnableMask
+(
+    uint8 u8Trigger,
+    uint8 u8ThcrValue
+);
+
+/**
+* @brief   Function to set or clear the bit Tx_E of the trigger handler control registers of the CTU IPL.
+*
+* @details Full configurability of CTU THCR1 & THCR2 registers of the CTU IPL.
+*          This function has in input the CTU trigger (0...7) and a Boolean to set to clear the right trigger bit.
+*          See from the RM the THCR1 and THCR2 registers for the right API use.
+*
+* @param[in]  u8Trigger    Index of the trigger: 0...7.
+* @param[in]  bEnable      if True, the bit Tx_E shall be set to 1, 0 otherwise
+*
+* @note    The function Service ID[hex]: 0x36.
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+*                 E_OK            In case of successful settings.
+*                 E_NOT_OK        In case of unsuccessful settings.
+*
+* @implements  Adc_CtuSetTriggerEnable_Activity
+*/
+Std_ReturnType Adc_CtuSetTriggerEnable
+(
+    uint8 u8Trigger,
+    boolean bEnable
+);
+
+/**
+* @brief   Function to set the cmd list handler control registers of the CTU IPL.
+*
+* @details Full configurability of CLCR1 & CLCR2 registers of the CTU IPL.
+*          This function has in input the CTU trigger (0...7) and  the position of the first
+*          command in the command list.
+*          See from the RM the CLCR1 and CLCR2 registers for the right API use.
+*
+* @param[in]  u8Trigger      Index of the trigger: 0...7.
+* @param[in]  u8ClcrValue   Position of the first command
+*
+* @note    The function Service ID[hex]: 0x37.
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+*                 E_OK            In case of successful settings.
+*                 E_NOT_OK        In case of unsuccessful settings.
+*
+* @implements  Adc_CtuSetTriggerAdcCmdAddress_Activity
+*/
+Std_ReturnType Adc_CtuSetTriggerAdcCmdAddress
+(
+    uint8 u8Trigger,
+    uint8 u8ClcrValue
+);
+
+/**
+* @brief   Function to set the trigger compare registers of the CTU IPL.
+*
+* @details Full configurability of CTU TxCR registers of the CTU IPL.
+*          This function has in input the CTU trigger (0...7) and the comparator value
+*          See from the RM the TxCR trigger compare registers for the right compare_value to use.
+*
+* @note    The function Service ID[hex]: 0x38.
+*
+* @param[in]  u8Trigger      Index of the trigger: 0...7.
+* @param[in]  u16CompareValue  value to set in the register TxCR.
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+*                 E_OK            In case of successful settings.
+*                 E_NOT_OK        In case of unsuccessful settings.
+*
+* @implements  Adc_CtuSetTriggerCompare_Activity
+*/
+Std_ReturnType Adc_CtuSetTriggerCompare
+(
+    uint8 u8Trigger,
+    uint16 u16CompareValue
+);
+#endif /* (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+/**
+* @brief   Function to dynamic handling of ADC channels list for Adc channel group.
+*
+* @details Dynamic handling of ADC channels list.
+*          This function to dynamic handling of ADC channels list for Adc channel group.
+* @param[in]  Group                     Group Id.
+* @param[in]  Channel                   Pointer to array of channels to be reconfigured for the group. Channel value is logical channel ID. 
+* @param[in]  Delays                    Pointer to array of delay value associated with array of channels to be reconfigured.
+* @param[in]  ChannelUpdateMask         Bitmask selecting which channels to be reconfigured.
+* @param[in]  NumberOfChannel           Number of channels in channels array.
+*
+* @note    For platforms supporting delays:
+*          Delays:
+*           - If NULL_PTR: channel delay values are not reconfigured.
+*           - If group has configured only 1 delay: pointer to new delay value. 
+*           - If group has configured delay for each channel: array with new delay values - number of elements must be NumberOfChannel.
+
+*          ChannelUpdateMask:
+*           - Bitmask example: 0b0110 only reconfigures channels from positions 1 and 2.
+*           - This bit mask can be used only if number of group channels are not greater than number of SC1 registers
+*           - Last bit of this mask must be set for having interrupt if NumberOfChannel is different than number of configured channels.
+*
+* @implements  Adc_SetChannel_Activity
+*/
+void Adc_SetChannel
+(
+    const Adc_GroupType Group,
+    const Adc_GroupDefType * Channel,
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+    const uint16 * Delays,
+    const uint32 ChannelUpdateMask,
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+    const Adc_ChannelIndexType NumberOfChannel
+);
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+/**
+* @brief          Enters the already prepared power state.
+* @details        This API configures the Adc module so that it enters the already prepared power
+*                 state, chosen between a predefined set of configured ones.
+*
+* @param[out]     Result        Pointer to a variable to store the result of this function
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Power Mode changed.
+*                 E_NOT_OK:       Request rejected.
+*
+* @implements  Adc_SetPowerState_Activity
+*/
+Std_ReturnType Adc_SetPowerState
+(
+    Adc_PowerStateRequestResultType * Result
+);
+
+/**
+* @brief          Get the current power state of the ADC HW unit.
+* @details        This API returns the current power state of the ADC HW unit.
+*
+* @param[out]     CurrentPowerState     The current power mode of the ADC HW Unit is returned in this parameter
+* @param[out]     Result                Pointer to a variable to store the result of this function
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Mode could be read.
+*                 E_NOT_OK:       Service is rejected.
+*
+* @implements  Adc_GetCurrentPowerState_Activity
+*/
+Std_ReturnType Adc_GetCurrentPowerState
+(
+    Adc_PowerStateType * CurrentPowerState,
+    Adc_PowerStateRequestResultType * Result
+);
+
+/**
+* @brief          Get the target power state of the ADC HW unit.
+* @details        This API returns the target power state of the ADC HW unit.
+*
+* @param[out]     TargetPowerState      The Target power mode of the ADC HW Unit is returned in this parameter.
+* @param[out]     Result                Pointer to a variable to store the result of this function.
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Mode could be read.
+*                 E_NOT_OK:       Service is rejected.
+*
+* @implements  Adc_GetTargetPowerState_Activity
+*/
+Std_ReturnType Adc_GetTargetPowerState
+(
+    Adc_PowerStateType * TargetPowerState,
+    Adc_PowerStateRequestResultType * Result
+);
+
+/**
+* @brief          Starts the needed process to allow the ADC HW module to enter the requested power state.
+* @details        This API starts the needed process to allow the ADC HW module to enter the requested power state.
+*
+* @param[in]      PowerState      The target power state intended to be attained.
+* @param[out]     Result          Pointer to a variable to store the result of this function.
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           Mode could be read.
+*                 E_NOT_OK:       Service is rejected.
+*
+* @implements  Adc_PreparePowerState_Activity
+*/
+Std_ReturnType Adc_PreparePowerState
+(
+    Adc_PowerStateType PowerState,
+    Adc_PowerStateRequestResultType * Result
+);
+
+#if (ADC_POWER_STATE_ASYNCH_MODE_SUPPORTED == STD_ON)
+/**
+* @brief          Cyclically called and supervises the power state transitions.
+* @details        This API is cyclically called and supervises the power state transitions, checking for the readiness of the module and issuing the callbacks.
+*
+* @param[in]      none
+* @param[out]     none
+*
+* @return         void
+*/
+void Adc_Main_PowerTransitionManager(void);
+#endif /* (ADC_POWER_STATE_ASYNCH_MODE_SUPPORTED == STD_ON) */
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+/**
+* @brief   Function to enable CTU control mode for an ADC unit.
+*
+* @details Enable CTU control mode for an ADC unit.
+*          This function to enable CTU control mode for Adc. When a unit works in CTU control mode,
+*          no other conversions shall run in parallel(Adc). The only conversions occurring shall be
+*          the ones defined in the CTU configuration.
+*
+* @param[in]  Unit      Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+*
+* @return         void
+*
+* @implements  Adc_EnableCtuControlMode_Activity
+*/
+void Adc_EnableCtuControlMode
+(
+    Adc_HwUnitType Unit
+);
+
+/**
+* @brief   Function to disable CTU control mode for an ADC unit.
+*
+* @details Disable CTU control mode for an ADC unit.
+*          This function to disable CTU control mode for Adc. The other Adc conversions can run in
+*          software trigger normal mode, software trigger injected mode or hardware trigger mode.
+*
+* @param[in]  Unit      Adc unit used. Recommended to use generated define for Adc Logical Unit Id
+*
+* @return         void
+*
+* @implements  Adc_DisableCtuControlMode_Activity
+*/
+void Adc_DisableCtuControlMode
+(
+    Adc_HwUnitType Unit
+);
+
+/**
+* @brief   Function to enable CTU hardware trigger.
+*
+* @details Enable CTU hardware trigger.
+*
+* @param[in]  TrigSource      Trigger source.
+*
+* @return         void
+*
+* @implements  Adc_CtuEnableHwTrigger_Activity
+*/
+void Adc_CtuEnableHwTrigger
+(
+    Adc_CtuTrigSrcType TrigSource
+);
+
+/**
+* @brief   Function to disable CTU hardware trigger.
+*
+* @details Disable CTU hardware trigger.
+*
+* @param[in]  TrigSource      Trigger source.
+*
+* @return         void
+*
+* @implements  Adc_CtuDisableHwTrigger_Activity
+*/
+void Adc_CtuDisableHwTrigger
+(
+    Adc_CtuTrigSrcType TrigSource
+);
+
+/**
+* @brief   Function to start CTU conversion.
+*
+* @details Start CTU conversion.
+*
+* @param[in]  TrigSource      Trigger source.
+*
+* @return         void
+*
+* @implements  Adc_CtuStartConversion_Activity
+*/
+void Adc_CtuStartConversion
+(
+    Adc_CtuTrigSrcType TrigSource
+);
+
+#if (ADC_CTU_AVAILABLE == STD_ON)
+/**
+* @brief   Issue a software master reload signal for CTU.
+*
+* @details Issue a software master reload signal for CTU in CTU Control Mode.
+*
+* @param[in]    CtuUnit     CTU hardware unit. Recommended to use generated define for Ctu Logical Unit Id
+*
+* @return       void
+*
+* @implements  Adc_CtuMasterReload_Activity
+*/
+void Adc_CtuMasterReload
+(
+    Adc_HwUnitType CtuUnit
+);
+#endif /* (ADC_CTU_AVAILABLE == STD_ON) */
+
+#if (ADC_BCTU_AVAILABLE == STD_ON)
+/**
+* @brief   Function to read BCTU conversion data.
+*
+* @details Read CTU conversion data.
+*
+* @param[in]    AdcUnit             Adc HW unit. Recommended to use generated define for Adc Logical Unit Id.
+*
+* @return       Adc_ValueGroupType  Conversion result.
+*
+* @implements  Adc_CtuReadConvData_Activity
+*/
+Adc_ValueGroupType Adc_CtuReadConvData
+(
+    Adc_HwUnitType AdcUnit
+);
+
+/**
+* @brief   Function to read BCTU conversion result.
+*
+* @details Read BCTU conversion result.
+*
+* @param[in]    AdcUnit      Adc HW unit. Recommended to use generated define for Adc Logical Unit Id.
+* @param[out]   pResult      Adc result structure.
+*
+* @return       void
+*
+* @implements  Adc_CtuReadConvResult_Activity
+*/
+void Adc_CtuReadConvResult
+(
+    Adc_HwUnitType AdcUnit,
+    Adc_CtuResultType * pResult
+);
+
+/**
+* @brief   Function to stop CTU loop conversion.
+*
+* @details Stop CTU loop conversions.
+*
+* @param[in] TrigSource    Trigger source of conversions to be stopped.
+*
+* @return         void
+*
+* @implements  Adc_CtuStopLoopConversions_Activity
+*/
+void Adc_CtuStopLoopConversions
+(
+    Adc_CtuTrigSrcType TrigSource
+);
+#endif /* (ADC_BCTU_AVAILABLE == STD_ON) */
+
+/**
+* @brief   Function to read CTU conversion data from FIFO.
+*
+* @details Read CTU conversion data from FIFO.
+*
+* @param[in]   FifoIdx      CTU FIFO index.
+* @param[out]  pu16Data     Pointer to pre-allocated result array.
+* @param[in]   u8DataLength Max amount of results to be read.
+*
+* @return         void
+*
+* @implements  Adc_CtuReadFifoData_Activity
+*/
+void Adc_CtuReadFifoData
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    uint16 * pu16Data,
+    uint8 u8DataLength
+);
+
+/**
+* @brief   Function to read CTU conversion results from FIFO.
+*
+* @details Read CTU conversion results from FIFO.
+*
+* @param[in]   FifoIdx         CTU FIFO index.
+* @param[out]  pResult         Pointer to pre-allocated result array.
+* @param[in]   u8ResultLength  Max amount of results to be read.
+*
+* @return         void
+*
+* @implements  Adc_CtuReadFifoResult_Activity
+*/
+void Adc_CtuReadFifoResult
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    Adc_CtuFifoResultType * pResult,
+    uint8 u8ResultLength
+);
+
+/**
+* @brief   Function to set CTU FIFO watermark.
+*
+* @details Set CTU FIFO watermark.
+*
+* @param[in]   FifoIdx      FIFO index.
+* @param[in]   u8Watermark  Watermark value.
+*
+* @return         void
+*
+* @implements  Adc_CtuSetFifoWatermark_Activity
+*/
+void Adc_CtuSetFifoWatermark
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    uint8 u8Watermark
+);
+
+/**
+* @brief   Function to enable CTU notification.
+*
+* @details Enable CTU notification.
+*
+* @param[in] Notification  Notification to be enabled.
+*
+* @return         void
+*
+* @implements  Adc_CtuEnableNotification_Activity
+*/
+void Adc_CtuEnableNotification
+(
+    Adc_CtuNotificationType Notification
+);
+
+/**
+* @brief   Function to disable CTU notification.
+*
+* @details Disable CTU notification.
+*
+* @param[in] Notification  Notification to be disabled.
+*
+* @return         void
+*
+* @implements  Adc_CtuDisableNotification_Activity
+*/
+void Adc_CtuDisableNotification
+(
+    Adc_CtuNotificationType Notification
+);
+
+/**
+* @brief   Function to set CTU list.
+*
+* @details Reconfigure the CTU list of conversions in CTU Control Mode.
+*
+* @param[in] ListItemsArray    Pointer to list items array to be set.
+* @param[in] NumItems          Number of items in the array.
+* @param[in] ListStartPosition Start position of the list.
+*
+* @return         void
+*
+* @implements  Adc_CtuSetList_Activity
+*/
+void Adc_CtuSetList
+(
+    const Adc_CtuListItemType * const ListItemsArray,
+    const uint8 NumItems,
+    const uint8 ListStartPosition
+);
+
+/**
+* @brief   Reconfigure the list pointer of a triggered CTU source.
+*
+* @details Reconfigure the list pointer of a trigger source in CTU Control Mode.
+*
+* @param[in] TrigSource        Source trigger index.
+* @param[in] ListPtr           Position of the first channel of the command list.
+*
+* @return         void
+*
+* @implements  Adc_CtuSetListPointer_Activity
+*/
+void Adc_CtuSetListPointer
+(
+    Adc_CtuTrigSrcType TrigSource,
+    Adc_CtuListPtrType ListPtr
+);
+#endif /* ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON */
+
+#if (ADC_ENABLE_TEMPSENSE_API == STD_ON)
+/**
+* @brief   Function to calculate temperature on chip from provided data.
+*
+* @details Calculates temperature on chip from provided data.
+*
+* @param[in] Unit                 Adc unit used. Recommended to use generated define for Adc Logical Unit Id.
+* @param[in] TempSenseConvData    Data measured on the ADC internal channel for TempSense.
+* (1 bit for the sign, 11 bits for the integer part and 4 bits for the decimal part)
+*
+* @return         uint16          Temperature value on chip.in degrees C, expressed in fixed point format.
+*
+* @implements  Adc_TempSenseCalculateTemp_Activity
+*/
+uint16 Adc_TempSenseCalculateTemp
+(
+    Adc_HwUnitType Unit,
+    const uint16 TempSenseAdcConvData
+);
+
+/**
+* @brief   Function to get the temperature on chip directly.
+*
+* @details This function starts a normal software conversion with one-shot mode on tempsense
+* channel and calculates the temperature on chip from the data conversion
+* The function is synchronous: waits until the ADC conversion completes or timeout occurs
+*
+* @param[in]  Unit                Adc unit used. Recommended to use generated define for Adc Logical Unit Id.
+* @param[out] TempSenseVal        Temperature value on chip in degrees C, expressed in fixed point format.
+* (1 bit for the sign, 11 bits for the integer part and 4 bits for the decimal part)
+*
+* @return         Std_ReturnType  Standard return type.
+*                 E_OK:           temperature read successful
+*                 E_NOT_OK:       operation failed
+* @implements  Adc_TempSenseGetTemp_Activity
+*/
+Std_ReturnType Adc_TempSenseGetTemp
+(
+    Adc_HwUnitType Unit,
+    uint16 * const TempSenseVal
+);
+
+/**
+* @brief          Set the Tempsense mode either to powerdown or normal.
+* @details        Set the Tempsense mode either to powerdown or normal.
+*
+* @param[in]      SetPowerMode    Power mode to set: normal or powerdown.
+*
+* @return         Std_ReturnType  Successful/Unsuccessful transition.
+*
+* @implements  Adc_TempSenseSetPowerMode_Activity
+*/
+Std_ReturnType Adc_TempSenseSetPowerMode
+(
+    Adc_SetPowerModeType SetPowerMode
+);
+
+#endif /* (ADC_ENABLE_TEMPSENSE_API == STD_ON) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_H */

RTD/include/Adc_Ip.h

@@ -0,0 +1,448 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_H
+#define ADC_IP_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+#include "Adc_Ip_Types.h"
+#include "Adc_Ip_Cfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_H    0
+#define ADC_IP_SW_MAJOR_VERSION_H               1
+#define ADC_IP_SW_MINOR_VERSION_H               0
+#define ADC_IP_SW_PATCH_VERSION_H               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ip.h file and Adc_Ip_Types.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_H != ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Adc_Ip.h and Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip.h file and Adc_Ip_Types.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_H != ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_H != ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ip.h file and Adc_Ip_Types.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_H != ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_MINOR_VERSION_H != ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_PATCH_VERSION_H != ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ip.h file and Adc_Ip_Cfg.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_H != ADC_IP_VENDOR_ID_CFG_H)
+    #error "Adc_Ip.h and Adc_Ip_Cfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip.h file and Adc_Ip_Cfg.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_H != ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_H != ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.h and Adc_Ip_Cfg.h are different"
+#endif
+
+/* Check if Adc_Ip.h file and Adc_Ip_Cfg.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_H != ADC_IP_SW_MAJOR_VERSION_CFG_H) || \
+     (ADC_IP_SW_MINOR_VERSION_H != ADC_IP_SW_MINOR_VERSION_CFG_H) || \
+     (ADC_IP_SW_PATCH_VERSION_H != ADC_IP_SW_PATCH_VERSION_CFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip.h and Adc_Ip_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                                     DEFINITIONS
+==================================================================================================*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+/*!
+ * @brief Initialize ADC module
+ *
+ * This function initializes the ADC module by configuring all
+ * available features.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] config - configuration struct pointer
+ * @return void
+ */
+void Adc_Ip_Init(const uint32 Instance, const Adc_Ip_ConfigType * const Config);
+
+/*!
+ * @brief Deinitialize ADC module
+ *
+ * This function resets the ADC internal registers to default values.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return void
+ */
+void Adc_Ip_DeInit(const uint32 Instance);
+
+/*!
+ * @brief Configure averaging
+ *
+ * This function enables averaging and selects the number of conversions to average.
+ * The mask parameter should be set using the Adc_Ip_AvgSelectType enum elements
+ * that have the pattern ADC_IP_AVG_... e.g. ADC_IP_AVG_4_CONV.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] AvgEn - enable or disable averaging
+ * @param[in] AvgSel - selects number of conversions to average
+ * @return void
+ */
+void Adc_Ip_SetAveraging(const uint32 Instance, const boolean AvgEn, const Adc_Ip_AvgSelectType AvgSel);
+
+/*!
+ * @brief Configure sample time
+ *
+ * This function sets the sample time for selected ADC instance.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] SampleTime - sample time
+ * @return void
+ */
+void Adc_Ip_SetSampleTime(const uint32 Instance, const uint8 SampleTime);
+
+/*!
+ * @brief Enable DMA
+ *
+ * This function enables DMA.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return void
+ */
+void Adc_Ip_EnableDma(const uint32 Instance);
+
+/*!
+ * @brief Disable DMA
+ *
+ * This function disables DMA.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return void
+ */
+void Adc_Ip_DisableDma(const uint32 Instance);
+
+/*!
+ * @brief Switch between hardware and software trigger
+ *
+ * This function enables either hardware or software trigger.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] TriggerMode - selected trigger mode(sw/hw)
+ * @return void
+ */
+void Adc_Ip_SetTriggerMode(const uint32 Instance, const Adc_Ip_TrigType TriggerMode);
+
+/*!
+ * @brief Switch between continuous and one shot conversion mode
+ *
+ * This function switches between ADC continuous conversion mode and one shot mode.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ContinuousModeEnable - mode to set: continuous(TRUE) or one shot(FALSE)
+ * @return void
+ */
+void Adc_Ip_SetContinuousMode(const uint32 Instance, const boolean ContinuousModeEnable);
+
+/*!
+ * @brief Set ADC module resolution
+ *
+ * This function sets ADC module resolution.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] Resolution - resolution value
+ * @return void
+ */
+void Adc_Ip_SetResolution(const uint32 Instance, const Adc_Ip_ResolutionType Resolution);
+
+/*!
+ * @brief Set the ADC clock values
+ *
+ * This function initializes the ADC clock configuration.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] Config - the clock configuration
+ * @return void
+ */
+void Adc_Ip_SetClockMode(const uint32 Instance, const Adc_Ip_ClockConfigType * const Config);
+
+/*!
+ * @brief Configure the selected control channel with the given
+ * configuration structure
+ *
+ * When Software Trigger mode is enabled, configuring control channel index 0,
+ * implicitly triggers a new conversion on the selected ADC input channel.
+ * Therefore, Adc_Ip_ConfigChannel can be used for sw-triggering conversions.
+ *
+ * Configuring any control channel while it is actively controlling a conversion
+ * (sw or hw triggered) will implicitly abort the on-going conversion.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ChanConfig - configuration structure
+ * @return void
+ */
+void Adc_Ip_ConfigChannel(const uint32 Instance, const Adc_Ip_ChanConfigType * const ChanConfig);
+
+/*!
+ * @brief Disable selected channel
+ *
+ * This function sets the input channel of the selected control channel to
+ * ADC_IP_INPUTCHAN_DISABLED. If WithTimeout is TRUE then the function will
+ * also wait for the register to be updated.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @param[in] WithTimeout - enables loop that checks if the register was updated
+ * @return Adc_Ip_StatusType
+ */
+Adc_Ip_StatusType Adc_Ip_SetDisabledChannel(const uint32 Instance, const uint8 ControlChanIdx, const boolean WithTimeout);
+
+/*!
+ * @brief Start a software triggered conversion
+ *
+ * This function starts a software conversion on the selected input channel by
+ * writing the values given to the SC1A register.
+ * Note: hardware configuration on the control channel with index 0 will be
+ * overwritten.
+ * Note: this will not work if hardware triggered mode is selected.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] InputChannel - channel index
+ * @param[in] InterruptEnable - enables end of conversion interrupt
+ * @return void
+ */
+void Adc_Ip_StartConversion(const uint32 Instance, Adc_Ip_InputChannelType InputChannel, const boolean InterruptEnable);
+
+/*!
+ * @brief Read and return conversion active flag status.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return conversion active flag status
+ */
+boolean Adc_Ip_GetConvActiveFlag(const uint32 Instance);
+
+/*!
+ * @brief Check if selected channel has interrupt set
+ *
+ * This function checks and returns if the selected control channel has the
+ * interrupt flag set.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @return TRUE if channel has interrupt set or FALSE otherwise
+ */
+boolean Adc_Ip_GetChanInterrupt(const uint32 Instance, const uint8 ControlChanIdx);
+
+/*!
+ * @brief Get the value of conversion complete flag of a channel
+ *
+ * This function returns the value of the conversion complete(COCO) flag of a
+ * given channel.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @return value of conversion complete flag
+ */
+boolean Adc_Ip_GetConvCompleteFlag(const uint32 Instance, const uint8 ControlChanIdx);
+
+/*!
+ * @brief Get the last result for the selected control channel
+ *
+ * This function retrieves the last conversion result for the selected control
+ * channel. This function does no validity check on the result. In order to
+ * check if the result is valid, the user must call Adc_Ip_GetConvCompleteFlag
+ * function before this one.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @return conversion result
+ */
+uint16 Adc_Ip_GetConvData(const uint32 Instance, const uint8 ControlChanIdx);
+
+/*!
+ * @brief Perform calibration of the ADC module
+ *
+ * This function performs a calibration of the ADC module. The input clock frequency
+ * for calibration must be less than or equal to half of the maximum specified
+ * frequency (50Mhz) and greater than minimum specified frequency (20Mhz).
+ * Please refer to Datasheet for more details
+ *
+ * @param[in] Instance - ADC instance number
+ * @return the calibration result
+ *  - ADC_IP_STATUS_SUCCESS: calibration successful
+ *  - ADC_IP_STATUS_TIMEOUT: calibration step timed out
+ */
+Adc_Ip_StatusType Adc_Ip_DoCalibration(const uint32 Instance);
+
+/*!
+ * @brief Clear latched triggers under processing
+ *
+ * This function clears all trigger latched flags of the ADC instance.
+ * This function must be called after the hardware trigger source for the ADC has been deactivated.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return clearing status
+ *  - ADC_IP_STATUS_SUCCESS: operation successful
+ *  - ADC_IP_STATUS_TIMEOUT: operation timed out
+ */
+Adc_Ip_StatusType Adc_Ip_ClearLatchedTriggers(const uint32 Instance);
+
+/*!
+ * @brief Enable channel notification
+ *
+ * This function enables the notification for the selected channel.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ * Note: It's required to read result data in user notification in order to clear the COCO flags and avoid ISR getting invoked repeatedly
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @return void
+ */
+void Adc_Ip_EnableChannelNotification(const uint32 Instance, const uint8 ControlChanIdx);
+
+/*!
+ * @brief Disable channel notification
+ *
+ * This function disables the notification for the selected channel.
+ * Note: the control channel index is the numeric index of SC1x
+ * (e.g. SC1A has index 0), not the input channel.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] ControlChanIdx - control channel index
+ * @return void
+ */
+void Adc_Ip_DisableChannelNotification(const uint32 Instance, const uint8 ControlChanIdx);
+
+/*!
+ * @brief Clear all trigger error flags
+ *
+ * This function clears all trigger error flags of the ADC instance.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return void
+ */
+void Adc_Ip_ClearTrigErrReg(const uint32 Instance);
+
+/*!
+ * @brief Get all trigger error flags
+ *
+ * This function returns all trigger error flags of the ADC instance.
+ *
+ * @param[in] Instance - ADC instance number
+ * @return trigger error flags bit-mask
+ */
+uint32 Adc_Ip_GetTrigErrReg(const uint32 Instance);
+
+/*!
+* @brief Return the address of the specified data register
+*
+* This function returns the address of the specified data register
+*
+* @param[in] Instance - ADC instance number
+* @param[in] Index - ADC channel of the Hw unit
+* @return status:
+*  - value of the address of the data for the specified channel
+*/
+uint32 Adc_Ip_GetDataAddress(const uint32 Instance, const uint8 Index);
+
+/*!
+ * @brief Get the last result for the selected control channel
+ *
+ * This function retrieves the last conversion result for the selected input 
+ * channel, by looking which control channel was configured with it. If multiple 
+ * control channels are configured simultaneously with the same requested input 
+ * channel, the result of the first control channel found will be returned. 
+ * If no control channel is configured with the given input channel then 
+ * ADC_IP_STATUS_ERROR will be returned.
+ * This function does no validity check on the result. In order to check if 
+ * the result is valid, the user must call Adc_Ip_GetConvCompleteFlag function 
+ * before this one.
+ *
+ * @param[in] Instance - ADC instance number
+ * @param[in] Channel - input channel
+ * @param[out] Result - pointer to the buffer where the result will be written
+ * @return status
+ */
+Adc_Ip_StatusType Adc_Ip_GetChanData(const uint32 Instance, const Adc_Ip_InputChannelType Channel, uint16 * const Result);
+
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+/*!
+* @brief Set software pretrigger source
+*
+* This function sets the software pretrigger source for an ADC instance.
+* Note: Pretrigger source must be set to software in order to use this.
+* Note: Software pretriggering is available only for ADC control channels 0-3(A-D).
+*
+* @param[in] Instance - ADC instance number
+* @param[in] SoftwarePretrigger - selected software pretrigger
+*/
+void Adc_Ip_SetSoftwarePretrigger(const uint32 Instance, const Adc_Ip_SoftwarePretriggerType SoftwarePretrigger);
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if defined (__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IP_H */

RTD/include/Adc_Ip_HeaderWrapper_S32K14x_Extended.h

@@ -0,0 +1,68 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_HEADERWRAPPER_S32K14X_EXTENDED_H
+#define ADC_IP_HEADERWRAPPER_S32K14X_EXTENDED_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+/* Important Note: This file cannot be used independently.
+*  It depends on platform header files to be included before including it */
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_HEADERWRAPPER_S32K14X_EXTENDED_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H    0
+#define ADC_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H               1
+#define ADC_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H               0
+#define ADC_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H               0
+
+/*==================================================================================================
+*                                     DEFINITIONS
+==================================================================================================*/
+
+/* 
+ * ADC_SC1ZZ_COUNT is the number of extended channels, there are 16 base 
+ * channels that are available on all K14X platforms, including this one 
+ */
+#define ADC_MAX_CHAN_COUNT          (16u + ADC_SC1ZZ_COUNT)
+
+/* Register access defines */
+#define REG_ACCESS(reg, index)      (*(volatile uint32*)(&(((&(reg))[(index)]))))
+
+#define SC1(Base, RegIndex)         REG_ACCESS(Base->ASC1A, (RegIndex))
+#define R(Base, RegIndex)           REG_ACCESS(Base->ARA, (RegIndex))
+
+
+
+/** @} */
+#endif /* ADC_IP_HEADERWRAPPER_S32K14X_EXTENDED_H */

RTD/include/Adc_Ip_HeaderWrapper_S32K1xx.h

@@ -0,0 +1,62 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_HEADERWRAPPER_S32K1XX_H
+#define ADC_IP_HEADERWRAPPER_S32K1XX_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+/* Important Note: This file cannot be used independently.
+*  It depends on platform header files to be included before including it */
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_HEADERWRAPPER_S32K1XX_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32K1XX_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32K1XX_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32K1XX_H    0
+#define ADC_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32K1XX_H               1
+#define ADC_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32K1XX_H               0
+#define ADC_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32K1XX_H               0
+
+/*==================================================================================================
+*                                     DEFINITIONS
+==================================================================================================*/
+
+#define ADC_MAX_CHAN_COUNT      ADC_SC1_COUNT
+
+/* Register access defines */
+#define SC1(Base, RegIndex)     (Base->SC1[RegIndex])
+#define R(Base, RegIndex)       (Base->R[RegIndex])
+
+
+
+/** @} */
+#endif /* ADC_IP_HEADERWRAPPER_S32K1XX_H */

RTD/include/Adc_Ip_HwAccess.h

@@ -0,0 +1,262 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_HW_ACCESS_H
+#define ADC_IP_HW_ACCESS_H
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+#include "StandardTypes.h"
+
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define ADC_IP_VENDOR_ID_HWACCESS_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H    0
+#define ADC_IP_SW_MAJOR_VERSION_HWACCESS_H               1
+#define ADC_IP_SW_MINOR_VERSION_HWACCESS_H               0
+#define ADC_IP_SW_PATCH_VERSION_HWACCESS_H               0
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Adc_Ip_HwAccess.h file and StandardTypes.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_HwAccess.h and StandardTypes.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+static inline void Adc_HwAcc_SetSC2Reg(ADC_Type * const Base, const uint32 ClearMask, const uint32 Value)
+{
+    /* Clear and set SC2 register based on ClearMask and Value */
+    uint32 Sc2Reg = Base->SC2;
+    Sc2Reg &= ~(ClearMask);
+    Sc2Reg |= Value;
+    Base->SC2 = Sc2Reg;
+}
+
+static inline void Adc_HwAcc_SetClock(ADC_Type * const Base, const Adc_Ip_ClockSelType ClockDivide, const Adc_Ip_ClkSourceType InputClock)
+{
+    /* Update ClockDivide and InputClock values found in CFG1 register */
+    uint32 Cfg1Reg = Base->CFG1;
+    Cfg1Reg &= ~(ADC_CFG1_ADIV_MASK | ADC_CFG1_ADICLK_MASK);
+    Cfg1Reg |= ADC_CFG1_ADIV(ClockDivide);
+    Cfg1Reg |= ADC_CFG1_ADICLK(InputClock);
+    Base->CFG1 = Cfg1Reg;
+}
+
+static inline Adc_Ip_ClockSelType Adc_HwAcc_GetClockDivide(const uint32 Reg)
+{
+    /* 
+     * Retrieve ClockDivide value found in CFG1 register
+     * Note: Reg should be the value of CFG1 register
+     */
+    Adc_Ip_ClockSelType ReturnValue = ADC_IP_CLK_FULL_BUS;
+    switch ((Reg & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
+    {
+        case 1u:
+            ReturnValue = ADC_IP_CLK_HALF_BUS;
+            break;
+        case 2u:
+            ReturnValue = ADC_IP_CLK_QUARTER_BUS;
+            break;
+        case 3u:
+            ReturnValue = ADC_IP_CLK_EIGHTH_BUS;
+            break;
+        default:
+            ; /* no-op */
+            break;
+    }
+    return ReturnValue;
+}
+
+static inline Adc_Ip_ClkSourceType Adc_HwAcc_GetInputClock(const uint32 Reg)
+{
+    /* 
+     * Retrieve InputClock value found in CFG1 register
+     * Note: Reg should be the value of CFG1 register
+     */
+    Adc_Ip_ClkSourceType ReturnValue = ADC_IP_CLK_ALT_1;
+    switch ((Reg & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
+    {
+        case 1u:
+            ReturnValue = ADC_IP_CLK_ALT_2;
+            break;
+        case 2u:
+            ReturnValue = ADC_IP_CLK_ALT_3;
+            break;
+        case 3u:
+            ReturnValue = ADC_IP_CLK_ALT_4;
+            break;
+        default:
+            ; /* no-op */
+            break;
+    }
+    return ReturnValue;
+}
+
+static inline void Adc_HwAcc_SetSampleTime(ADC_Type * const Base, const uint8 SampleTime)
+{
+    /* Clip sample time to minimum value */
+    uint8 ClippedSampleTime = (uint8)((SampleTime > 0U) ? SampleTime : 1U);
+    /* Update SampleTime values found in SC3 register */
+    uint32 Cfg2Reg = Base->CFG2;
+    Cfg2Reg &= ~(ADC_CFG2_SMPLTS_MASK);
+    Cfg2Reg |= ADC_CFG2_SMPLTS(ClippedSampleTime);
+    Base->CFG2 = Cfg2Reg;
+}
+
+static inline void Adc_HwAcc_SetAveraging(ADC_Type * const Base, const boolean AvgEn, const Adc_Ip_AvgSelectType AvgSel)
+{
+    /* Update AvgEn and AvgSel values found in SC3 register */
+    uint32 Sc3Reg = Base->SC3;
+    Sc3Reg &= ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
+    Sc3Reg |= ADC_SC3_AVGE(AvgEn ? 1u : 0u);
+    Sc3Reg |= ADC_SC3_AVGS(AvgSel);
+    Base->SC3 = Sc3Reg;
+}
+
+static inline Adc_Ip_AvgSelectType Adc_HwAcc_GetAverageSelect(const uint32 Reg)
+{
+    /* 
+     * Retrieve AvgSelect value found in SC3 register
+     * Note: Reg should be the value of SC3 register
+     */
+    Adc_Ip_AvgSelectType ReturnValue = ADC_IP_AVG_4_CONV;
+    switch ((Reg & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
+    {
+        case 1u:
+            ReturnValue = ADC_IP_AVG_8_CONV;
+            break;
+        case 2u:
+            ReturnValue = ADC_IP_AVG_16_CONV;
+            break;
+        case 3u:
+            ReturnValue = ADC_IP_AVG_32_CONV;
+            break;
+        default:
+            ; /* no-op */
+            break;
+    }
+    return ReturnValue;
+}
+
+static inline void Adc_HwAcc_SetTriggerMode(ADC_Type * const Base, const Adc_Ip_TrigType TriggerMode)
+{
+    /* Update TriggerMode value found in SC2 register */
+    uint32 Sc2Reg = Base->SC2;
+    Sc2Reg &= ~(ADC_SC2_ADTRG_MASK);
+    Sc2Reg |= ADC_SC2_ADTRG(TriggerMode);
+    Base->SC2 = Sc2Reg;
+}
+
+static inline Adc_Ip_TrigType Adc_HwAcc_GetTriggerMode(const uint32 Reg)
+{
+    /* Retrieve TriggerMode value found in SC2 register */
+    Adc_Ip_TrigType ReturnValue = ADC_IP_TRIGGER_SOFTWARE;
+    if (((Reg & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT) == 1u)
+    {
+        ReturnValue = ADC_IP_TRIGGER_HARDWARE;
+    }
+    return ReturnValue;
+}
+
+static inline void Adc_HwAcc_SetChannel(ADC_Type * const Base, const uint8 ChnIdx, const Adc_Ip_InputChannelType InputChannel, const boolean InterruptEnable)
+{
+    /* Configure channel by writing all SC1n register fields */
+    uint32 Sc1Reg = SC1(Base, ChnIdx);
+    Sc1Reg &= ~(ADC_SC1_ADCH_MASK | ADC_SC1_AIEN_MASK);
+    Sc1Reg |= ADC_SC1_ADCH(InputChannel);
+    Sc1Reg |= ADC_SC1_AIEN(InterruptEnable ? 1u : 0u);
+    SC1(Base, ChnIdx) = Sc1Reg;
+}
+
+static inline void Adc_HwAcc_SetUserGainAndOffset(ADC_Type * const Base, const uint16 UsrGain, const uint16 UsrOffset)
+{
+    /* 
+     * Currently, user gain and user offset values are set at config time.
+     * If user gain is to be changed at runtime (e.g. after a calibration was 
+     * already executed) then the G register should also be updated.
+     * To calculate the new value of this register, it is necessary execute 
+     * the following algorithm:
+     * 1. Sum <- UsrGain + Clp0 + Clp1 + Clp2 + Clp3 + ClpS
+     * 2. RegVal <- Sum & 0xF800U
+     * 3. if RegVal != 0x0000U then RegVal <- 0xFFFFU
+     * 4. Base->G <- RegVal
+     */
+
+    Base->USR_OFS = ADC_USR_OFS_USR_OFS(UsrOffset);
+    Base->UG = ADC_UG_UG(UsrGain);
+}
+
+static inline boolean Adc_HwAcc_GetAIEN(const uint32 Reg)
+{
+    /* Retrive AIEN flag from given SC1 register */
+    return (((Reg & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT) != 0u) ? TRUE : FALSE;
+}
+
+static inline boolean Adc_HwAcc_GetCOCO(const uint32 Reg)
+{
+    /* Retrive COCO flag from given SC1 register */
+    return (((Reg & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT) != 0u) ? TRUE : FALSE;
+}
+
+static inline uint16 Adc_HwAcc_GetData(const ADC_Type * const Base, const uint8 ChnIdx)
+{
+    /* Retrieve the conversion result of a given channel */
+    uint16 Result = (uint16) R(Base, ChnIdx);
+    Result = (uint16) ((Result & ADC_R_D_MASK) >> ADC_R_D_SHIFT);
+    return Result;
+}
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if defined (__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IP_HW_ACCESS_H */

RTD/include/Adc_Ip_Types.h

@@ -0,0 +1,422 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_TYPES_H
+#define ADC_IP_TYPES_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+#include "StandardTypes.h"
+#include "Adc_Ip_CfgDefines.h"
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_TYPES_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H    0
+#define ADC_IP_SW_MAJOR_VERSION_TYPES_H               1
+#define ADC_IP_SW_MINOR_VERSION_TYPES_H               0
+#define ADC_IP_SW_PATCH_VERSION_TYPES_H               0
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Adc_Ip_Types.h file and Adc_Ip_CfgDefines.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_TYPES_H != ADC_IP_VENDOR_ID_CFGDEFINES_H)
+    #error "Adc_Ip_Types.h and Adc_Ip_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_Types.h file and Adc_Ip_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H != ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H != ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_Types.h and Adc_Ip_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ip_Types.h file and Adc_Ip_CfgDefines.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_TYPES_H != ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_SW_MINOR_VERSION_TYPES_H != ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_SW_PATCH_VERSION_TYPES_H != ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_Types.h and Adc_Ip_CfgDefines.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Adc_Ip_Types.h file and StandardTypes.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H != STD_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H != STD_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_Types.h and StandardTypes.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/*==================================================================================================
+*                              STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*!
+ * @brief ADC IP status return type
+ *
+ * This structure is used as return type
+ *
+ * Implements : Adc_Ip_StatusType_Class
+ */
+typedef enum
+{
+    ADC_IP_STATUS_SUCCESS = 0x00U,      /*!< Function completed successfully */
+    ADC_IP_STATUS_ERROR   = 0x01U,      /*!< Function didn't complete successfully */
+    ADC_IP_STATUS_TIMEOUT = 0x02U       /*!< Function operation timed out */
+} Adc_Ip_StatusType;
+
+/*!
+ * @brief Clock divider selection
+ *
+ * This structure is used to configure the converter input clock
+ *
+ * Implements : Adc_Ip_ClockSelType_Class
+ */
+typedef enum
+{
+    ADC_IP_CLK_FULL_BUS    = 0x00U,     /*!< Input clock divided by 1. */
+    ADC_IP_CLK_HALF_BUS    = 0x01U,     /*!< Input clock divided by 2. */
+    ADC_IP_CLK_QUARTER_BUS = 0x02U,     /*!< Input clock divided by 4. */
+    ADC_IP_CLK_EIGHTH_BUS  = 0x03U,     /*!< Input clock divided by 8. */
+} Adc_Ip_ClockSelType;
+
+/*!
+ * @brief Conversion resolution selection
+ *
+ * Implements : Adc_Ip_ResolutionType_Class
+ */
+typedef enum
+{
+    ADC_IP_RESOLUTION_8BIT  = 0x00U,    /*!< 8-bit resolution mode */
+    ADC_IP_RESOLUTION_12BIT = 0x01U,    /*!< 12-bit resolution mode */
+    ADC_IP_RESOLUTION_10BIT = 0x02U     /*!< 10-bit resolution mode */
+} Adc_Ip_ResolutionType;
+
+/*!
+ * @brief Input clock source selection
+ *
+ * This structure is used to select the input clock source
+ *
+ * Implements : Adc_Ip_ClkSourceType_Class
+ */
+typedef enum
+{
+    ADC_IP_CLK_ALT_1 = 0x00U,       /*!< Input clock alternative 1. */
+    ADC_IP_CLK_ALT_2 = 0x01U,       /*!< Input clock alternative 2. */
+    ADC_IP_CLK_ALT_3 = 0x02U,       /*!< Input clock alternative 3. */
+    ADC_IP_CLK_ALT_4 = 0x03U        /*!< Input clock alternative 4. */
+} Adc_Ip_ClkSourceType;
+
+/*!
+ * @brief Hardware average selection
+ *
+ * This structure is used to select the number of conversions to average
+ * in order to get the conversion data.
+ *
+ * Implements : Adc_Ip_AvgSelectType_Class
+ */
+typedef enum {
+    ADC_IP_AVG_4_CONV  = 0x00U,       /*!< 4 conversions per conversion data */
+    ADC_IP_AVG_8_CONV  = 0x01U,       /*!< 8 conversions per conversion data */
+    ADC_IP_AVG_16_CONV = 0x02U,       /*!< 16 conversions per conversion data */
+    ADC_IP_AVG_32_CONV = 0x03U,       /*!< 32 conversions per conversion data */
+} Adc_Ip_AvgSelectType;
+
+/*!
+ * @brief Trigger type selection
+ *
+ * Implements : Adc_Ip_TrigType_Class
+ */
+typedef enum
+{
+    ADC_IP_TRIGGER_SOFTWARE = 0x00U,        /*!< Software trigger. */
+    ADC_IP_TRIGGER_HARDWARE = 0x01U         /*!< Hardware trigger. */
+} Adc_Ip_TrigType;
+
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+/*!
+ * @brief Pretrigger source selection
+ * 
+ * This structure provides the pretrigger source options for the ADCxPRETRGSEL
+ * field found in SIM[ADCOPT] register
+ *
+ * Implements : Adc_Ip_PretriggerSelType_Class
+ */
+typedef enum
+{
+    ADC_IP_PRETRIGGER_SEL_PDB     = 0x00U,      /*!< PDB pretrigger selected. */
+    ADC_IP_PRETRIGGER_SEL_TRGMUX  = 0x01U,      /*!< TRGMUX pretrigger selected. */
+    ADC_IP_PRETRIGGER_SEL_SW      = 0x02U       /*!< Software pretrigger selected. */
+} Adc_Ip_PretriggerSelType;
+
+/*!
+ * @brief Software pretrigger type
+ * 
+ * This structure provides the software pretrigger options for the ADCxSWPRETRG
+ * field found in SIM[ADCOPT] register
+ *
+ * Implements : Adc_Ip_PretriggerSelType_Class
+ */
+typedef enum
+{
+    ADC_IP_SOFTWARE_PRETRIGGER_DISABLED = 0x00U,
+    ADC_IP_SOFTWARE_PRETRIGGER_0        = 0x04U,
+    ADC_IP_SOFTWARE_PRETRIGGER_1        = 0x05U,
+    ADC_IP_SOFTWARE_PRETRIGGER_2        = 0x06U,
+    ADC_IP_SOFTWARE_PRETRIGGER_3        = 0x07U
+} Adc_Ip_SoftwarePretriggerType;
+
+/*!
+ * @brief Trigger source selection
+ * 
+ * This structure provides the trigger source options for the ADCxTRGSEL
+ * field found in SIM[ADCOPT] register
+ *
+ * Implements : Adc_Ip_TrigSelType_Class
+ */
+typedef enum
+{
+    ADC_IP_TRIGGER_SEL_PDB        = 0x00U,      /*!< PDB trigger selected. */
+    ADC_IP_TRIGGER_SEL_TRGMUX     = 0x01U       /*!< TRGMUX trigger selected. */
+} Adc_Ip_TrigSelType;
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+/*!
+ * @brief Voltage reference selection
+ *
+ * Implements : Adc_Ip_VoltageReferenceType_Class
+ */
+typedef enum
+{
+    ADC_IP_VOLTAGEREF_VREF = 0x00U,        /*!< VrefH and VrefL as Voltage reference. */
+    ADC_IP_VOLTAGEREF_VALT = 0x01U         /*!< ValtH and ValtL as Voltage reference. */
+} Adc_Ip_VoltageReferenceType;
+
+/*!
+ * @brief Enumeration of input channels assignable to a control channel.
+ * \n <b>Note 0</b>: entries in this enum are affected by ::FEATURE_ADC_NUM_EXT_CHANS, which is device dependent
+ * and controlled from <i>"device_name"_features.h</i> file.
+ *
+ * \n <b>Note 1</b>: the actual number of external channels may differ between device packages
+ * and ADC instances. Reading a channel that is not connected externally, will return a random value within the range.
+ * Please refer to the Reference Manual for the maximum number of external channels for each device variant and ADC instance.
+ *
+ * \n <b>Note 2</b>: ADC_IP_INPUTCHAN_SUPPLY_ select which internal supply channel to be measured.
+ * They are only available for ADC0 and measured internally via internal input channel 0.
+ * Please note that supply monitoring needs to be enabled separately via dedicated flag in adc_converter_config_t.
+ *
+ * Implements : Adc_Ip_InputChannelType_Class
+ */
+typedef enum
+{
+    ADC_IP_INPUTCHAN_EXT0      = 0x00U,                 /*!< External input channel 0 */
+    ADC_IP_INPUTCHAN_EXT1      = 0x01U,                 /*!< External input channel 1 */
+#if (FEATURE_ADC_HAS_CHANNEL_2)
+    ADC_IP_INPUTCHAN_EXT2      = 0x02U,                 /*!< External input channel 2 */
+#endif /* (FEATURE_ADC_HAS_CHANNEL_2) */
+    ADC_IP_INPUTCHAN_EXT3      = 0x03U,                 /*!< External input channel 3 */
+    ADC_IP_INPUTCHAN_EXT4      = 0x04U,                 /*!< External input channel 4 */
+    ADC_IP_INPUTCHAN_EXT5      = 0x05U,                 /*!< External input channel 5 */
+    ADC_IP_INPUTCHAN_EXT6      = 0x06U,                 /*!< External input channel 6 */
+    ADC_IP_INPUTCHAN_EXT7      = 0x07U,                 /*!< External input channel 7 */
+#if (FEATURE_ADC_HAS_CHANNEL_8)
+    ADC_IP_INPUTCHAN_EXT8      = 0x08U,                 /*!< External input channel 8 */
+#endif /* (FEATURE_ADC_HAS_CHANNEL_8) */
+#if (FEATURE_ADC_HAS_CHANNEL_9)
+    ADC_IP_INPUTCHAN_EXT9      = 0x09U,                 /*!< External input channel 9 */
+#endif /* (FEATURE_ADC_HAS_CHANNEL_9) */
+    ADC_IP_INPUTCHAN_EXT10     = 0x0AU,                 /*!< External input channel 10 */
+    ADC_IP_INPUTCHAN_EXT11     = 0x0BU,                 /*!< External input channel 11 */
+#if (FEATURE_ADC_MAX_EXT_CHAN_ID > 11u)
+    ADC_IP_INPUTCHAN_EXT12     = 0x0CU,                 /*!< External input channel 12 */
+    ADC_IP_INPUTCHAN_EXT13     = 0x0DU,                 /*!< External input channel 13 */
+    ADC_IP_INPUTCHAN_EXT14     = 0x0EU,                 /*!< External input channel 14 */
+#if (FEATURE_ADC_MAX_EXT_CHAN_ID > 14u)
+    ADC_IP_INPUTCHAN_EXT15     = 0x0FU,                 /*!< External input channel 15 */
+#if (FEATURE_ADC_MAX_EXT_CHAN_ID > 15u)
+    ADC_IP_INPUTCHAN_EXT16     = 0x20U,                 /*!< External input channel 16 */
+    ADC_IP_INPUTCHAN_EXT17     = 0x21U,                 /*!< External input channel 17 */
+    ADC_IP_INPUTCHAN_EXT18     = 0x22U,                 /*!< External input channel 18 */
+    ADC_IP_INPUTCHAN_EXT19     = 0x23U,                 /*!< External input channel 19 */
+    ADC_IP_INPUTCHAN_EXT20     = 0x24U,                 /*!< External input channel 20 */
+    ADC_IP_INPUTCHAN_EXT21     = 0x25U,                 /*!< External input channel 21 */
+    ADC_IP_INPUTCHAN_EXT22     = 0x26U,                 /*!< External input channel 22 */
+    ADC_IP_INPUTCHAN_EXT23     = 0x27U,                 /*!< External input channel 23 */
+#if (FEATURE_ADC_MAX_EXT_CHAN_ID > 23u)
+    ADC_IP_INPUTCHAN_EXT24     = 0x28U,                 /*!< External input channel 24 */
+    ADC_IP_INPUTCHAN_EXT25     = 0x29U,                 /*!< External input channel 25 */
+    ADC_IP_INPUTCHAN_EXT26     = 0x2AU,                 /*!< External input channel 26 */
+    ADC_IP_INPUTCHAN_EXT27     = 0x2BU,                 /*!< External input channel 27 */
+    ADC_IP_INPUTCHAN_EXT28     = 0x2CU,                 /*!< External input channel 28 */
+    ADC_IP_INPUTCHAN_EXT29     = 0x2DU,                 /*!< External input channel 29 */
+    ADC_IP_INPUTCHAN_EXT30     = 0x2EU,                 /*!< External input channel 30 */
+    ADC_IP_INPUTCHAN_EXT31     = 0x2FU,                 /*!< External input channel 31 */
+#endif /* (FEATURE_ADC_MAX_EXT_CHAN_ID > 23u) */
+#endif /* (FEATURE_ADC_MAX_EXT_CHAN_ID > 15u) */
+#endif /* (FEATURE_ADC_MAX_EXT_CHAN_ID > 14u) */
+#endif /* (FEATURE_ADC_MAX_EXT_CHAN_ID > 11u) */
+
+    ADC_IP_INPUTCHAN_DISABLED  = ADC_SC1_ADCH_MASK,     /*!< Channel disabled          */
+
+    ADC_IP_INPUTCHAN_INT0      = 0x15,                  /*!< Internal input channel 0  */
+    ADC_IP_INPUTCHAN_INT1      = 0x16,                  /*!< Internal input channel 1  */
+    ADC_IP_INPUTCHAN_INT2      = 0x17,                  /*!< Internal input channel 2  */
+    ADC_IP_INPUTCHAN_INT3      = 0x1C,                  /*!< Internal input channel 3  */
+
+    ADC_IP_INPUTCHAN_TEMP      = 0x1A,                  /*!< Temperature Sensor            */
+    ADC_IP_INPUTCHAN_BANDGAP   = 0x1B,                  /*!< Band Gap                      */
+    ADC_IP_INPUTCHAN_VREFH     = 0x1D,                  /*!< Voltage Reference Select High */
+    ADC_IP_INPUTCHAN_VREFL     = 0x1E,                  /*!< Voltage Reference Select Low  */
+
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+                                                        /*!< The following channels are measured via internal input channel 0 */
+    ADC_IP_INPUTCHAN_SUPPLY_VDD            = 0xF00U,    /*!< Monitor internal supply 5 V input VDD supply.              */
+    ADC_IP_INPUTCHAN_SUPPLY_VDDA           = 0xF01U,    /*!< Monitor internal supply 5 V input analog supply.           */
+    ADC_IP_INPUTCHAN_SUPPLY_VREFH          = 0xF02U,    /*!< Monitor internal supply ADC reference supply.              */
+    ADC_IP_INPUTCHAN_SUPPLY_VDD_3V         = 0xF03U,    /*!< Monitor internal supply 3.3 V oscillator regulator output. */
+    ADC_IP_INPUTCHAN_SUPPLY_VDD_FLASH_3V   = 0xF04U,    /*!< Monitor internal supply 3.3 V flash regulator output.      */
+    ADC_IP_INPUTCHAN_SUPPLY_VDD_LV         = 0xF05U     /*!< Monitor internal supply 1.2 V core regulator output.       */
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+} Adc_Ip_InputChannelType;
+
+/*!
+ * @brief Defines the channel notification header
+ *
+ * This header is used for channel notification callbacks.
+ * Note: the return paramter is the index of the control channel(numeric index
+ * of SC1x e.g. SC1A has index 0), not the input channel.
+ *
+ * Implements : Adc_Ip_ChanNotificationType_Class
+ */
+typedef void Adc_Ip_ChanNotificationType(const uint8 ControlChanIdx);
+
+/*!
+ * @brief Defines the channel configuration
+ *
+ * This structure is used to configure channels
+ *
+ * Implements : Adc_Ip_ChanConfigType_Class
+ */
+typedef struct
+{
+    uint8 ChnIdx;                           /*!< Control channel 0 */
+    Adc_Ip_InputChannelType Channel;        /*!< Selection of input channel for measurement */
+    boolean InterruptEnable;                /*!< Enable interrupts for this channel */
+} Adc_Ip_ChanConfigType;
+
+/*!
+ * @brief Defines the ADC clock configuration
+ *
+ * This structure is used to configure ADC clock
+ *
+ * Implements : Adc_Ip_ClockConfigType_Class
+ */
+typedef struct
+{
+    Adc_Ip_ClockSelType ClockDivide;    /*!< Selected clock */
+    Adc_Ip_ClkSourceType InputClock;    /*!< Input clock source */
+    uint8 SampleTime;                   /*!< Sample time in AD Clocks */
+    boolean AvgEn;                      /*!< Enable averaging functionality */
+    Adc_Ip_AvgSelectType AvgSel;        /*!< Selection for number of samples used for averaging */
+} Adc_Ip_ClockConfigType;
+
+/*!
+ * @brief Defines the module configuration
+ *
+ * This structure is used to configure the ADC module
+ *
+ * Implements : Adc_Ip_ConfigType_Class
+ */
+typedef struct
+{
+    Adc_Ip_ClockSelType ClockDivide;            /*!< Divider of the input clock for the ADC */
+    Adc_Ip_ClockSelType CalibrationClockDivide; /*!< Divider of the input clock for Calibration */
+    Adc_Ip_ClkSourceType InputClock;            /*!< Input clock source */
+    uint8 SampleTime;                           /*!< Sample time in AD Clocks */
+    boolean AvgEn;                              /*!< Enable averaging functionality */
+    Adc_Ip_AvgSelectType AvgSel;                /*!< Selection for number of samples used for averaging */
+    Adc_Ip_ResolutionType Resolution;           /*!< ADC resolution (8,10,12 bit) */
+    Adc_Ip_TrigType TriggerMode;                /*!< ADC trigger mode (software, hardware) - affects only the first control channel */
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    Adc_Ip_PretriggerSelType PretriggerSel;     /*!< Pretrigger source selected for Trigger Latching and Arbitration Unit - affects only the first 4 control channels */
+    Adc_Ip_TrigSelType TriggerSel;              /*!< Trigger source selected for Trigger Latching and Arbitration Unit */
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+    boolean DmaEnable;                          /*!< Enable DMA for the ADC */
+    Adc_Ip_VoltageReferenceType VoltageRef;     /*!< Voltage reference used */
+    boolean ContinuousConvEnable;               /*!< Enable Continuous conversions */
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    boolean SupplyMonitoringEnable;             /*!< Only available for ADC 0. Enable internal supply monitoring - enables measurement of ADC_IP_INPUTCHAN_SUPPLY_ sources. */
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+
+    boolean CompareEnable;                      /*!< Enable the compare feature */
+    boolean CompareGreaterThanEnable;           /*!< Enable Greater-Than functionality */
+    boolean CompareRangeFuncEnable;             /*!< Enable Range functionality */
+    uint16 CompVal1;                            /*!< First Compare Value */
+    uint16 CompVal2;                            /*!< Second Compare Value */
+
+    uint16 UsrGain;                             /*!< User-configurable gain */
+    uint16 UsrOffset;                           /*!< User-configurable Offset (2's complement, subtracted from result) */
+
+    uint8 NumChannels;                          /*!< User-configurable Number of Channels */
+    const Adc_Ip_ChanConfigType * ChannelConfigs;                   /*!< User-configurable channel configuration */
+
+    Adc_Ip_ChanNotificationType * ConversionCompleteNotification;   /*!< Individual channel notification */
+} Adc_Ip_ConfigType;
+
+/*!
+ * @brief Structure used to store runtime info
+ *
+ * This structure is used to store ADC runtime info
+ *
+ * Implements : Adc_Ip_StateStructType_Class
+ */
+typedef struct
+{
+    boolean Init;                               /*!< Check if the driver was initialized. */
+    Adc_Ip_ClockSelType CalibrationClockDivide; /*!< Divider of the input clock for Calibration */
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    Adc_Ip_PretriggerSelType PretriggerSel;     /*!< Pretrigger source selected for Trigger Latching and Arbitration Unit - affects only the first 4 control channels */
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+    /* Individual channel notification */
+    Adc_Ip_ChanNotificationType * ConversionCompleteNotification;   /*!< Individual channel notification */
+
+    /* Current hardware channel config */
+    Adc_Ip_InputChannelType ChannelConfig[ADC_MAX_CHAN_COUNT];      /*!< Current hardware channel config */
+} Adc_Ip_StateStructType;
+
+/** @} */
+
+#endif /* ADC_IP_TYPES_H */

RTD/include/Adc_Ipw.h

@@ -0,0 +1,356 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_H
+#define ADC_IPW_H
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ipw Adc Ipw
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ipw_Types.h"
+#include "Adc_Ipw_Cfg.h"
+
+#include "Adc_Ip.h"
+#ifdef ADC_DMA_SUPPORTED
+#include "Dma_Ip.h"
+#endif
+#include "Pdb_Adc_Ip.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_IPW_H                       43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_H        4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_H        4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_H     0
+#define ADC_SW_MAJOR_VERSION_IPW_H                1
+#define ADC_SW_MINOR_VERSION_IPW_H                0
+#define ADC_SW_PATCH_VERSION_IPW_H                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ipw.h file and Adc_Ipw_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_H != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Ipw.h and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ipw_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ipw_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_H != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_H != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_H != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ipw_Cfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_H != ADC_VENDOR_ID_IPW_CFG_H)
+    #error "Adc_Ipw.h and Adc_Ipw_Cfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ipw_Cfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_CFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_CFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.h and Adc_Ipw_Cfg.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ipw_Cfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_H != ADC_SW_MAJOR_VERSION_IPW_CFG_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_H != ADC_SW_MINOR_VERSION_IPW_CFG_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_H != ADC_SW_PATCH_VERSION_IPW_CFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw.h and Adc_Ipw_Cfg.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ip.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_H != ADC_IP_VENDOR_ID_H)
+    #error "Adc_Ipw.h and Adc_Ip.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ip.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_H != ADC_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_H != ADC_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.h and Adc_Ip.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Adc_Ip.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_H != ADC_IP_SW_MAJOR_VERSION_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_H != ADC_IP_SW_MINOR_VERSION_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_H != ADC_IP_SW_PATCH_VERSION_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw.h and Adc_Ip.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Pdb_Adc_Ip.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_H != PDB_ADC_IP_VENDOR_ID_H)
+    #error "Adc_Ipw.h and Pdb_Adc_Ip.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw.h file and Pdb_Adc_Ip.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.h and Pdb_Adc_Ip.h are different"
+#endif
+
+/* Check if Adc_Ipw.h file and Pdb_Adc_Ip.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_H != PDB_ADC_IP_SW_MAJOR_VERSION_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_H != PDB_ADC_IP_SW_MINOR_VERSION_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_H != PDB_ADC_IP_SW_PATCH_VERSION_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw.h and Pdb_Adc_Ip.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+#ifdef ADC_DMA_SUPPORTED
+/* Check if Adc_Ipw.h file and Dma_Ip.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_H != DMA_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_H != DMA_IP_AR_RELEASE_MINOR_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.h and Dma_Ip.h are different"
+#endif
+#endif /* ADC_DMA_SUPPORTED */
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/* The macro to calculate the number of channels for each configuration */
+#define ADC_IPW_CALCULATE_CHAN_NUMBER(x) (((x) >= ADC_MAX_CHAN_COUNT) ? ADC_MAX_CHAN_COUNT : ((x)%ADC_MAX_CHAN_COUNT))
+#ifdef ADC_DMA_SUPPORTED
+#define ADC_IPW_INVALID_DATA_RESULT_DMA     (0xFFFFU)
+#define ADC_IPW_GET_COMPLEMENT_OF_2(x)      ((uint32)(~((uint32)(x)) + 1U))
+#endif /* ADC_DMA_SUPPORTED */
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if ((defined(ADC_UNIT_0_ISR_USED)) || (defined(ADC_UNIT_1_ISR_USED)) || \
+     (defined(ADC_DMA_SUPPORTED)) || (ADC_READ_GROUP_API == STD_ON) \
+    )
+uint8 Adc_Ipw_CalculateNumsBitShift
+(
+    Adc_Ip_ResolutionType Resolution
+);
+#endif  /* (defined(ADC_UNIT_0_ISR_USED) || ... */
+
+#ifdef ADC_DMA_SUPPORTED
+void Adc_Ipw_StartDmaOperation
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint8 u8NumChannel,
+    uint32 u32CoreId
+);
+#endif /* ADC_DMA_SUPPORTED */
+
+/**
+* @brief          Functions mapping.
+* @details        Middle layer versus Low layer functions mapping
+*
+*/
+Std_ReturnType Adc_Ipw_Init(const Adc_Ipw_Config * pIpwCfg, const uint32 u32CoreId);
+
+#if (ADC_DEINIT_API == STD_ON)
+Std_ReturnType Adc_Ipw_DeInit(uint32 u32CoreId);
+#endif /* ADC_DEINIT_API == STD_ON */
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+void Adc_Ipw_StartNormalConversion
+(
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+
+Std_ReturnType Adc_Ipw_StopCurrentConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* ADC_ENABLE_START_STOP_GROUP_API == STD_ON */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+Std_ReturnType Adc_Ipw_EnableHardwareTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+
+void Adc_Ipw_DisableHardwareTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+
+boolean Adc_Ipw_CheckValidConversion
+(
+    Adc_HwUnitType PhysicalHwUnitId,
+    Adc_ChannelIndexType StartIndex,
+    Adc_ChannelIndexType EndIndex
+);
+
+#if (ADC_READ_GROUP_API == STD_ON)
+Std_ReturnType Adc_Ipw_ReadGroup
+(
+    const Adc_GroupType Group,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+);
+#endif /* ADC_READ_GROUP_API == STD_ON */
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+Std_ReturnType Adc_Ipw_GetConvData
+(
+    Adc_HwUnitType Unit,
+    Adc_ChannelType Channel,
+    uint32 u32CoreId,
+    uint16 * Result
+);
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#if (ADC_CALIBRATION == STD_ON)
+void Adc_Ipw_Calibrate
+(
+    Adc_HwUnitType Unit,
+    Adc_CalibrationStatusType * Status,
+    uint32 u32CoreId
+);
+#endif /* ADC_CALIBRATION == STD_ON */
+
+void Adc_Ipw_ConfigureConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel,
+    uint32 u32CoreId
+);
+
+#ifdef ADC_DMA_SUPPORTED
+void Adc_Ipw_ConfigureDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel
+);
+#endif /* ADC_DMA_SUPPORTED */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+void Adc_Ipw_StartHwTrigConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+  Std_ReturnType Adc_Ipw_SetClockMode
+(
+   Adc_SelectPrescalerType Prescaler,
+   uint32 u32CoreId
+);
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+boolean Adc_Ipw_CheckConversionValuesInRange
+(
+    Adc_ValueGroupType Value,
+    Adc_HwUnitType LogicalHwUnitId,
+    Adc_ChannelType ChannelIndex,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+
+#if (ADC_ENABLE_QUEUING == STD_ON)
+void Adc_RemoveFromQueue
+(
+    const Adc_HwUnitType Unit,
+    const Adc_QueueIndexType CurQueueIndex
+);
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+
+uint32 Adc_GetCoreID(void);
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_H */

RTD/include/Adc_Ipw_Irq.h

@@ -0,0 +1,111 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_IRQ_H
+#define ADC_IPW_IRQ_H
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ipw Adc Ipw
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ipw_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_IPW_IRQ_H                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_H       4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_H       4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_H    0
+#define ADC_SW_MAJOR_VERSION_IPW_IRQ_H               1
+#define ADC_SW_MINOR_VERSION_IPW_IRQ_H               0
+#define ADC_SW_PATCH_VERSION_IPW_IRQ_H               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ipw_Irq.h file and Adc_Ipw_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_IRQ_H != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Ipw_Irq.h and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Irq.h file and Adc_Ipw_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.h file and Adc_Ipw_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_IRQ_H != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_IRQ_H != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_IRQ_H != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Irq.h and Adc_Ipw_Types.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_IRQ_H */

RTD/include/Adc_Ipw_Types.h

@@ -0,0 +1,340 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_TYPES_H
+#define ADC_IPW_TYPES_H
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ipw Adc Ipw
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Adc_Ipw_CfgDefines.h"
+#include "Adc_Ip_Types.h"
+#include "Pdb_Adc_Ip_Types.h"
+
+/* TODO: consider removing, or moving defines also in Ipw_CfgDefines */
+#include "Adc_CfgDefines.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_IPW_TYPES_H                       43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H        4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H        4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H     0
+#define ADC_SW_MAJOR_VERSION_IPW_TYPES_H                1
+#define ADC_SW_MINOR_VERSION_IPW_TYPES_H                0
+#define ADC_SW_PATCH_VERSION_IPW_TYPES_H                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ipw_Types.h file and Adc_Ipw_CfgDefines.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_TYPES_H != ADC_VENDOR_ID_IPW_CFGDEFINES_H)
+    #error "Adc_Ipw_Types.h and Adc_Ipw_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_Ipw_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Types.h and Adc_Ipw_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_Ipw_CfgDefines.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_TYPES_H != ADC_SW_MAJOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_TYPES_H != ADC_SW_MINOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_TYPES_H != ADC_SW_PATCH_VERSION_IPW_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Types.h and Adc_Ipw_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_Ip_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_TYPES_H != ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Adc_Ipw_Types.h and Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_Ip_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H != ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H != ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Types.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_Ip_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_TYPES_H != ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_TYPES_H != ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_TYPES_H != ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Types.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Pdb_Adc_Ip_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_TYPES_H != PDB_ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Adc_Ipw_Types.h and Pdb_Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Pdb_Adc_Ip_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Types.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Pdb_Adc_Ip_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_TYPES_H != PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_TYPES_H != PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_TYPES_H != PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Types.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* TODO: consider removing, or moving defines also in Ipw_CfgDefines */
+/* Check if Adc_Ipw_Types.h file and Adc_CfgDefines.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_TYPES_H != ADC_VENDOR_ID_CFGDEFINES_H)
+    #error "Adc_Ipw_Types.h and Adc_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H != ADC_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Types.h and Adc_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ipw_Types.h file and Adc_CfgDefines.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_TYPES_H != ADC_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_TYPES_H != ADC_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_TYPES_H != ADC_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Types.h and Adc_CfgDefines.h are different"
+#endif
+/*==================================================================================================
+*                              STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+typedef uint8 Adc_HwUnitType;             /**< @brief Numeric ID of an ADC Hw Unit */
+
+/* SWS_Adc_00506 */
+/** @implements     Adc_ChannelType_uint */
+typedef uint16 Adc_ChannelType;           /**< @brief Numeric ID of an ADC channel */
+
+/* SWS_Adc_00507 */
+/** @implements     Adc_GroupType_uint */
+typedef uint16 Adc_GroupType;             /**< @brief Numeric ID of an ADC channel group. No uC dependent */
+typedef uint16 Adc_QueueIndexType;        /**< @brief Index for the queue of groups */
+
+/* SWS_Adc_00510 */
+/** @implements     Adc_ConversionTimeType_uint */
+typedef uint8 Adc_ConversionTimeType;     /**< @brief conversion time */
+
+/* SWS_Adc_00508 */
+/** @implements     Adc_ValueGroupType_int */
+typedef uint16 Adc_ValueGroupType;        /**< @brief type for ADC result of one channel */
+
+/** @implements     Adc_HwTriggerTimerType_uint */
+typedef Pdb_Adc_Ip_TriggerSrcType Adc_HwTriggerTimerType;    /**< @brief Type for the reload value of the ADC embedded timer */
+typedef uint8 Adc_ChannelIndexType;                   /**< @brief Number of channels */
+
+/**
+* @brief          Adc group conversion.
+* @details        Used for value received by Tressos interface configuration.
+*
+*/
+typedef enum
+{
+    ADC_CONV_TYPE_NORMAL   = 0U,    /**< @brief Normal conversion mode */
+    ADC_CONV_TYPE_INJECTED = 1U     /**< @brief Injected conversion mode */
+} Adc_GroupConvType;
+
+#if (ADC_CALIBRATION == STD_ON)
+/**
+* @brief          Structure for calibration status
+*/
+typedef struct
+{
+    /** @brief Unit calibration result status */
+    Std_ReturnType Adc_UnitSelfTestStatus;
+#if (ADC_CALSTAT_AVAILABLE == STD_ON)
+    /** @brief List of failed tests */
+    uint8 Adc_au8Calibrate_Failed_Steps[ADC_MAX_CALIBRATION_STEPS];
+#endif /* (ADC_CALSTAT_AVAILABLE == STD_ON) */
+} Adc_CalibrationStatusType;
+#endif /* ADC_CALIBRATION == STD_ON */
+
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief          Group Access Mode type.
+* @details        Used for value received by Tressos interface configuration.
+*/
+typedef enum
+{
+    ADC_NORMAL = 0U, /**< @brief Normal mode */
+    ADC_ALTERNATE    /**< @brief Alternate mode */
+} Adc_SelectPrescalerType;
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+/**
+* @brief          Adc Group conversion mode.
+* @details        Used for value received by Tressos interface configuration.
+*
+* SWS_Adc_00515, SWS_Adc_00380, SWS_Adc_00381
+* @implements     Adc_GroupConvModeType_enum
+*/
+typedef enum
+{
+    ADC_CONV_MODE_ONESHOT    = 0U,  /*!< One-shot conversion mode */
+    ADC_CONV_MODE_CONTINUOUS = 1U   /*!< Scan conversion mode */
+} Adc_GroupConvModeType;
+
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+/**
+* @brief          Range select values.
+* @details        Indicates which range select is used.
+*
+* @implements  Adc_ChannelRangeSelectType_enum
+* SWS_Adc_00524
+*/
+typedef enum
+{
+    ADC_RANGE_ALWAYS = 0U,   /**< @brief Complete range - independent from channel limit settings */
+    ADC_RANGE_BETWEEN,       /**< @brief Range between low limit and high limit - high limit value included */
+    ADC_RANGE_NOT_BETWEEN,   /**< @brief Range above high limit or below low limit - low limit value included */
+    ADC_RANGE_NOT_OVER_HIGH, /**< @brief Range below high limit - high limit value included */
+    ADC_RANGE_NOT_UNDER_LOW, /**< @brief Range above low limit */
+    ADC_RANGE_OVER_HIGH,     /**< @brief Range above high limit */
+    ADC_RANGE_UNDER_LOW      /**< @briefRange below low limit - low limit value included */
+} Adc_ChannelRangeSelectType;
+
+typedef struct
+{
+    const boolean bChannelLimitCheckEnabled;        /**< @brief Channel limit checking enabled */
+    const Adc_ChannelRangeSelectType eChannelRange; /**< @brief Range conversion */
+    const uint16 ChannelHighLimit;                  /**< @brief High limit channel conversion value */
+    const uint16 ChannelLowLimit;                   /**< @brief Low limit channel conversion value */
+} Adc_ChannelLimitCheckingType;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+
+typedef struct
+{
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    /**< @brief Main Average enable status of group */
+    const uint8 u8GroupAvgEnable;
+    /**< @brief Main Average selection of group */
+    const Adc_Ip_AvgSelectType GroupAvgSelect;
+    Adc_ConversionTimeType ConvTime;
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    /**< @brief Alternate Average enable status of group */
+    const uint8 u8GroupAvgEnableAlternate;
+    /**< @brief Alternate Average selection of group */
+    const Adc_Ip_AvgSelectType GroupAvgSelectAlternate;
+    Adc_ConversionTimeType AlternateConvTime;
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+    /**< @brief The period PDB for continuous mode */
+    const uint16 PdbPeriod;
+    /**< @brief The delay for next PDB */
+    const uint16 PdbDelay;
+    /**< @brief Enables or Disables the ADC Back to Back configuration for Group Channels */
+    const boolean AdcGroupEnableBackToBack;
+    /**< @brief Enables or Disables the ADC pre-trigger delay configuration for each Group Channel */
+    const boolean AdcGroupEnableChannelDelays;
+    /**< @brief Channel delays */
+    const uint16 * pDelay;
+} Adc_Ipw_GroupConfig;
+
+typedef struct
+{
+    const uint8 u8Adc_DmaInterruptSoftware[ADC_MAX_HW_UNITS];              /**< @brief DMA or Interrupt driven */
+    const Adc_GroupType aAdc_Groups[ADC_MAX_HW_UNITS];                     /**< @brief Number of groups configured for each unit */
+    const Adc_ChannelType aAdc_Channels[ADC_MAX_HW_UNITS];                 /**< @brief Number of channels of the hw unit x */
+    const uint8 au8Adc_DmaChannel[ADC_MAX_HW_UNITS];                       /**< @brief If dma driven then indicates the dma channel number for HW UNITS */
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    const uint8 au8Adc_CountingDmaChannel[ADC_MAX_HW_UNITS];               /**< @brief If dma driven then indicates the dma linked channel number for HW UNITS in optimize DMA streaming groups multiple channels feature*/
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+    const uint8 au8Adc_HwUnit[ADC_MAX_HW_UNITS];                           /**< @brief If unit x is active STD_ON/STD_OFF on current partition. Indexed by Physical Hw Index */
+    const Adc_HwUnitType aHwLogicalId[ADC_MAX_HW_UNITS];                   /**< Mapping between Physical Id and Logical Id */
+} Adc_Ipw_MultiConfigType;
+
+typedef struct
+{
+    const Adc_Ip_ConfigType * apAdcConfig[ADC_MAX_HW_UNITS];
+    const Pdb_Adc_Ip_ConfigType * apPdbConfig[ADC_MAX_HW_UNITS];
+    Adc_HwUnitType aAdcPhysicalId[ADC_MAX_HW_UNITS];
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    const Adc_Ip_ClockConfigType * apAdcAltClockConfig[ADC_MAX_HW_UNITS];
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    const Adc_ChannelLimitCheckingType * ChannelLimitCheckingConfigs[ADC_MAX_HW_UNITS];
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+    /** @brief Miscellaneous configuration parameters */
+    const Adc_Ipw_MultiConfigType Mapping;
+} Adc_Ipw_Config;
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+/**
+* @brief           Number of ADC result registers
+*/
+#define ADC_IPW_RES_REG_NUM     (ADC_MAX_CHAN_COUNT)
+/**
+* @brief           Max channel index
+*/
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    #define ADC_IPW_MAX_CHN_ID      (ADC_IP_INPUTCHAN_SUPPLY_VDD_LV)
+#elif (FEATURE_ADC_MAX_EXT_CHAN_ID <= 15u)
+    #define ADC_IPW_MAX_CHN_ID      (ADC_IP_INPUTCHAN_VREFL)
+#elif (FEATURE_ADC_MAX_EXT_CHAN_ID <= 23u)
+    #define ADC_IPW_MAX_CHN_ID      (ADC_IP_INPUTCHAN_EXT23)
+#else
+    #define ADC_IPW_MAX_CHN_ID      (ADC_IP_INPUTCHAN_EXT31)
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_TYPES_H */

RTD/include/Adc_Types.h

@@ -0,0 +1,475 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_TYPES_H
+#define ADC_TYPES_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ipw_Types.h"
+#include "Adc_CfgDefines.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_TYPES_H                         43
+#define ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H          4
+#define ADC_AR_RELEASE_MINOR_VERSION_TYPES_H          4
+#define ADC_AR_RELEASE_REVISION_VERSION_TYPES_H       0
+#define ADC_SW_MAJOR_VERSION_TYPES_H                  1
+#define ADC_SW_MINOR_VERSION_TYPES_H                  0
+#define ADC_SW_PATCH_VERSION_TYPES_H                  0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Types.h file and Adc_Ipw_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_TYPES_H != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Types.h and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Types.h file and Adc_Ipw_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_TYPES_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_TYPES_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Types.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Types.h file and Adc_Ipw_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_TYPES_H != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_TYPES_H != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_TYPES_H != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Types.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Types.h file and Adc_CfgDefines.h file are of the same vendor */
+#if (ADC_VENDOR_ID_TYPES_H != ADC_VENDOR_ID_CFGDEFINES_H)
+    #error "Adc_Types.h and Adc_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Types.h file and Adc_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H != ADC_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_TYPES_H != ADC_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_TYPES_H != ADC_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Types.h and Adc_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Types.h file and Adc_CfgDefines.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_TYPES_H != ADC_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_MINOR_VERSION_TYPES_H != ADC_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_PATCH_VERSION_TYPES_H != ADC_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Types.h and Adc_CfgDefines.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+/**
+* @brief          ADC driver status
+* @details        Used to differentiate if ADC driver is already uninit, during init or already
+*                 initialized or not.
+*
+*/
+typedef enum
+{
+    ADC_STATE_UNINIT = 0U,  /**< @brief Adc driver uninitialized */
+    ADC_STATE_BUSY,         /**< @brief Adc driver busy */
+    ADC_STATE_IDLE          /**< @brief Adc driver idle */
+} Adc_GlobalStateType;
+
+
+/**
+* @brief          ADC group already converted type.
+* @details        Used to differentiate if group is already converted or not.
+*
+*/
+typedef enum
+{
+    ADC_NOT_YET_CONVERTED = 0U, /**< @brief Group not yet converted */
+    ADC_ALREADY_CONVERTED       /**< @brief Group is already converted */
+} Adc_GroupConversionStateType;
+
+/**
+* @brief          Adc group access Mode.
+* @details        Used for value received by Tressos interface configuration.
+*
+* @implements     Adc_GroupAccessModeType_enum
+* SWS_Adc_00528
+*/
+typedef enum
+{
+    ADC_ACCESS_MODE_SINGLE = 0U, /**< @brief Single access mode */
+    ADC_ACCESS_MODE_STREAMING    /**< @brief Streaming access mode */
+} Adc_GroupAccessModeType;
+
+/**
+* @brief          Adc group replacement.
+* @details        Used for value received by Tressos interface configuration.
+*
+* @implements     Adc_GroupReplacementType_enum
+* SWS_Adc_00523
+*/
+typedef enum
+{
+    ADC_GROUP_REPL_ABORT_RESTART, /**< @brief Abort and restart of group*/
+    ADC_GROUP_REPL_SUSPEND_RESUME /**< @brief Suspend and resuming of group*/
+}Adc_GroupReplacementType;
+
+/**
+* @brief          Adc group streaming buffer mode.
+* @details        Used for value received by Tressos interface configuration.
+*
+* @implements     Adc_StreamBufferModeType_enum
+* SWS_Adc_00519
+*/
+typedef enum
+{
+    ADC_STREAM_BUFFER_LINEAR = 0U, /**< @brief Linear streaming*/
+    ADC_STREAM_BUFFER_CIRCULAR     /**< @brief Circular streaming*/
+} Adc_StreamBufferModeType;
+
+/**
+* @brief          ADC group status.
+* @details        ADC group enumeration type.
+*
+* @implements     Adc_StatusType_enum
+* SWS_Adc_00513
+*/
+typedef enum
+{
+    ADC_IDLE = 0U,       /**< @brief Group is in IDLE state*/
+    ADC_BUSY,            /**< @brief Group is in BUSY state */
+    ADC_COMPLETED,       /**< @brief Group is in COMPLETED state*/
+    ADC_STREAM_COMPLETED /**< @brief Group is in STREAM_COMPLETED state*/
+} Adc_StatusType;
+
+/**
+* @brief          ADC group notification.
+* @details        Indicates if notification is enabled for the group.
+*
+*/
+typedef enum
+{
+    ADC_NOTIFICATION_DISABLED = 0U, /**< @brief Notification is disabled */
+    ADC_NOTIFICATION_ENABLED        /**< @brief Notification is enabled */
+} Adc_NotificationType;
+
+/**
+* @brief          Adc hardware trigger edge.
+* @details        Used for value received by Tressos interface configuration.
+*
+* @implements     Adc_HwTriggerSignalType_enum
+* SWS_Adc_00520
+*/
+
+typedef enum
+{
+    ADC_HW_TRIG_RISING_EDGE = 0U, /**< @brief Rising edge */
+    ADC_HW_TRIG_FALLING_EDGE,     /**< @brief Falling edge */
+    ADC_HW_TRIG_BOTH_EDGES        /**< @brief falling and rising edge */
+} Adc_HwTriggerSignalType;
+
+/**
+* @brief          Adc hardware trigger source.
+* @details        Used for value received by Tressos interface configuration.
+*
+* @implements     Adc_TriggerSourceType_enum
+* SWS_Adc_00514
+*/
+typedef enum
+{
+    ADC_TRIGG_SRC_SW = 0U /**< @brief Software triggered */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+,
+    ADC_TRIGG_SRC_HW      /**< @brief Hardware triggered */
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+} Adc_TriggerSourceType;
+
+#if (STD_ON == ADC_HW_TRIGGER_API)
+/**
+* @brief          Adc Hardware trigger.
+* @details        Indicates if hardware trigger is enabled for group.
+*
+*/
+typedef enum
+{
+    ADC_HWTRIGGER_DISABLED = 0U, /**< @brief Hardware trigger is disabled */
+    ADC_HWTRIGGER_ENABLED        /**< @brief Hardware trigger is enabled */
+} Adc_HwTriggeringType;
+
+#endif /* (STD_ON==ADC_HW_TRIGGER_API) */
+
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+typedef void (*Adc_NotifyType)(void);     /**< @brief Notification function pointer definition */
+
+/* SWS_Adc_00512 */
+/** @implements     Adc_ResolutionType_uint */
+typedef uint8 Adc_ResolutionType;         /**< @brief channel resolution in number of bits */
+
+#if (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE)
+/* SWS_Adc_00516 */
+/** @implements     Adc_GroupPriorityType_uint */
+typedef uint8 Adc_GroupPriorityType;      /**< @brief ADC Channel group priority */
+#endif /* (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) */
+
+/* SWS_Adc_00517 */
+/** @implements     Adc_GroupDefType_uint */
+typedef Adc_ChannelType Adc_GroupDefType; /**< @brief definition of channels in a group */
+
+/* SWS_Adc_00509 */
+/** @implements     Adc_PrescaleType_uint */
+typedef uint8 Adc_PrescaleType;           /**< @brief clock prescaler factor */
+
+/* SWS_Adc_00511 */
+/** @implements     Adc_SamplingTimeType_uint */
+typedef uint8 Adc_SamplingTimeType;       /**< @brief sampling time */
+
+/* SWS_Adc_00518 */
+/** @implements     Adc_StreamNumSampleType_uint */
+typedef uint16 Adc_StreamNumSampleType;   /**< @brief Number of samples of a streaming conversion buffer */
+
+/**
+* @brief          Structure for validation results
+* @details        This structure contains the validation information
+*
+*/
+typedef struct
+{
+    boolean bEndValidations; /**< @brief Signal if validation ended */
+    Std_ReturnType ValidParams; /**< @brief Return status */
+} Adc_ValidationResultType;
+
+/**
+* @brief          Structure for group status.
+* @details        This structure contains the group status information.
+*
+*/
+typedef struct
+{
+    volatile Adc_StatusType eConversion;   /**< @brief Group status */
+    volatile Adc_GroupConversionStateType eAlreadyConverted;     /**< @brief Group was previously converted or not */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    Adc_HwTriggeringType eHwTriggering;   /**< @brief hw trigger enabled/disabled */
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+    Adc_NotificationType eNotification;   /**< @brief notification enabled/disabled */
+#endif /* ADC_GRP_NOTIF_CAPABILITY == STD_ON */
+    volatile Adc_StreamNumSampleType ResultIndex;  /**< @brief index into streaming buffer that is currently being filled */
+#ifdef ADC_CURRENT_CHANNEL_USED
+    Adc_ChannelIndexType CurrentChannel;  /**< @brief Current channel in use */
+#endif /* ADC_CURRENT_CHANNEL_USED */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    volatile boolean bLimitCheckFailed;   /**< @brief check limit check fail */
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+} Adc_GroupStatusType;
+
+/**
+* @brief          Structure for hardware unit status.
+* @details        This structure contains the HW unit status information.
+*
+*/
+typedef struct
+{
+    /** @brief Filled slots in the queue */
+    volatile Adc_QueueIndexType SwNormalQueueIndex;
+    /** @brief Queued groups indexes, always executing Queue[0] */
+    volatile Adc_GroupType SwNormalQueue[ADC_QUEUE_MAX_DEPTH_MAX];
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    /** @brief Ongoing hardware group ID */
+    volatile Adc_GroupType OngoingHwGroup;
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    /** @brief The depth of the software injected queue */
+    volatile Adc_GroupType SwInjectedQueue[1U];
+    /** @brief Filled slots in the Sw injected queue */
+    volatile Adc_QueueIndexType SwInjectedQueueIndex;
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+    /** @brief Indicates Ctu control mode is ongoing */
+    boolean bCtuControlOngoing;
+#endif /* ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON */
+#if (ADC_PDB_AVAILABLE == STD_ON)
+    uint8 u8Sc1Used;
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+} Adc_UnitStatusType;
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+typedef struct
+{
+    /** @brief Run time assigned channels to group */
+    const Adc_GroupDefType * pChannel;
+    /** @brief Run time number of channels */
+    Adc_ChannelIndexType ChannelCount;
+    /** @brief Indicates whether the configuration has been updated or not */
+    boolean bRuntimeUpdated;
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    /* @brief Indicates whether pChannel has channel with limit checking enabled */
+    boolean bAdcRuntimeGroupLimitcheck;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#if (ADC_PDB_AVAILABLE == STD_ON)
+    /** @brief Run time assigned delay of channels group */
+    const uint16 * pu16Delays;
+    /** @brief Mask per channel - to be updated or not */
+    uint32 u32Mask;
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+} Adc_RuntimeGroupChannelType;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+typedef struct
+{
+    const Adc_GroupType GroupId;                                /**< @brief Index of group */
+    const Adc_HwUnitType AdcLogicalUnitId;                      /**< @brief The ADC Logical Unit Id that the group belongs to */
+    const Adc_GroupAccessModeType eAccessMode;                  /**< @brief Access Mode */
+    const Adc_GroupConvModeType eMode;                          /**< @brief Conversion Mode (OneShot/Continuous) */
+    const Adc_GroupConvType eType;                              /**< @brief Conversion type (Normal/Injected) */
+#if (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE)
+    const Adc_GroupPriorityType Priority;                      /**< @brief Priority of group */
+#endif /* (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) */
+    const Adc_GroupReplacementType eReplacementMode;           /**< @brief Replacement Mode */
+    const Adc_TriggerSourceType eTriggerSource;                /**< @brief Hw/Sw trigger */
+#if (STD_ON == ADC_HW_TRIGGER_API)
+    const Adc_HwTriggerTimerType HwTriggerSource;               /**< @brief Hardware trigger source for the group */
+    const Adc_HwTriggerSignalType eTriggerEdge;                 /**< @brief Hardware trigger edge */
+    #if (ADC_CTU_AVAILABLE == STD_ON)
+    const Adc_HwTriggerTimerType HwTriggerCompareValue;         /**< @brief Counter Compare Value to reload CTU Trigger */
+    #endif /* (ADC_CTU_AVAILABLE == STD_ON) */
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+#if (STD_ON == ADC_GRP_NOTIF_CAPABILITY)
+    /* SWS_Adc_00104 */
+    const Adc_NotifyType Notification;                         /**< @brief Pointer to notification function */
+#endif /* (STD_ON==ADC_GRP_NOTIF_CAPABILITY) */
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+    /* CPR-MCAL-797.adc */
+    const Adc_NotifyType ExtraNotification;                    /**< @brief Pointer to extra notification function */
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+
+    /* SWS_Adc_00319, SWS_Adc_00318 */
+    Adc_ValueGroupType ** pResultsBufferPtr; /**< @brief pointer to user result buffer array */
+    const Adc_StreamBufferModeType eBufferMode;                /**< @brief Buffer Mode */
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+    const Adc_GroupType EnableChDisableChGroupIndex;            /**< @brief Group's index if it has the support to enable/disable channel */
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+    const Adc_StreamNumSampleType NumSamples;                  /**< @brief  Number of samples */
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    const boolean bStreamResultGroupMultiSets;                 /**< @brief Arrange the results as multiple sets of group result buffer */
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+    const Adc_GroupDefType * pAssignment;                      /**< @brief Assigned channels to group */
+    const Adc_ChannelIndexType AssignedChannelCount;           /**< @brief Number of channels */
+
+    const Adc_ChannelType LastCh;                              /**< @brief Last channel configured */
+    const Adc_ChannelType FirstCh;                             /**< @brief First channel configured */
+    /* PR-MCAL-3229.adc */
+    const uint8 u8AdcWithoutInterrupt;                         /**< @brief Enables or Disables the ADC and DMA interrupts */
+    const uint8 u8AdcExtDMAChanEnable;                         /**< @brief Enables or Disables configuring external DMA channel in the group */
+    const boolean u8AdcWithoutDma;                             /**< @brief When true, disables completely DMA configuration done by ADC driver for the group */
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    const boolean bAdcOptimizeDmaStream;                         /**< @brief Enables or Disables the ADC optimize DMA streaming groups feature */
+    const boolean bHalfInterrupt;                              /**< @brief Enable half interrupt for optimize DMA streaming groups feature */
+#endif
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    const boolean bAdcGroupLimitcheck;                          /**< @brief Enables or disables the usage of limit checking for an ADC group. */
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#ifndef ADC_CMR_REGISTER_NOT_SUPPORTED
+    Adc_ChansIdxMaskType AssignedChannelMask;
+#endif /* ADC_CMR_REGISTER_NOT_SUPPORTED */
+#if (ADC_CTU_HW_TRIGGER_OPTIMIZATION == STD_ON)
+    const uint8 u8CtuTrigListPos;                               /**< @brief First position of channel in BCTU channel list or CTU command list. */
+#endif /* (ADC_CTU_HW_TRIGGER_OPTIMIZATION == STD_ON) */
+#if ((ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) || (ADC_PDB_AVAILABLE == STD_ON))
+    Adc_Ipw_GroupConfig const * pAdcIpwGroupConfig;
+#endif /* ((ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) || (ADC_PDB_AVAILABLE == STD_ON)) */
+} Adc_GroupConfigurationType;
+
+
+/**
+* @brief          Structure for ADC configuration.
+* @details        Data structure containing the set of configuration parameters required
+*                 for initializing the ADC Driver.
+* @api
+* @implements     Adc_ConfigType_struct
+* SWS_Adc_00505
+*/
+typedef struct
+{
+    Adc_Ipw_Config const * pAdcIpwConfig;
+
+    /** @brief Group configurations */
+    const Adc_GroupConfigurationType * pGroups;
+    /** @brief Total number of groups */
+    Adc_GroupType GroupCount;
+    /** @brief Miscellaneous configuration parameters */
+    const uint16 * pGroupIdToIndexMap;
+    /** @brief Configuration CoreID */
+    uint32 u32CoreId;
+    /**< @brief Assigned Partition*/
+    const uint8 * pAssignmentPartition; /* generated from ECUC partition reference. TODO: check can be moved in configurator (check that core from AdcHwUnitEcucPartitionRef is among AdcEcucPartitionRef). TBD */
+    /**< @brief Number of Partition */
+    const uint8 AssignedPartitionCount; /* remove if pAssignmentPartition is removed */
+} Adc_ConfigType;
+
+/*==================================================================================================
+                                 GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_TYPES_H */

RTD/include/Pdb_Adc_Ip.h

@@ -0,0 +1,349 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_ADC_IP_H
+#define PDB_ADC_IP_H
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip Pdb Adc IPL
+*   @{
+*/
+
+#include "Pdb_Adc_Ip_Types.h"
+#include "Pdb_Adc_Ip_Cfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define PDB_ADC_IP_VENDOR_ID_H                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_H       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_H       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_H    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_H               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_H               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_H               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Types.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_H != PDB_ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Pdb_Adc_Ip.h and Pdb_Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Types.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Types.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_H != PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_H != PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_H != PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Cfg.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_H != PDB_ADC_IP_VENDOR_ID_CFG_H)
+    #error "Pdb_Adc_Ip.h and Pdb_Adc_Ip_Cfg.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Cfg.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.h and Pdb_Adc_Ip_Cfg.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip.h file and Pdb_Adc_Ip_Cfg.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_H != PDB_ADC_IP_SW_MAJOR_VERSION_CFG_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_H != PDB_ADC_IP_SW_MINOR_VERSION_CFG_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_H != PDB_ADC_IP_SW_PATCH_VERSION_CFG_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip.h and Pdb_Adc_Ip_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                                     DEFINITIONS
+==================================================================================================*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+/*!
+ * @brief Initialize PDB module
+ *
+ * This function initializes the PDB counter, input triggers and general pretrigger settings.
+ * It resets PDB registers and enables the PDB clock. Therefore, it should be
+ * called before any other operation. After it is initialized, the PDB can
+ * act as a triggered timer, which enables other features in PDB module.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] Config - configuration struct pointer
+ * @return void
+ */
+void Pdb_Adc_Ip_Init(const uint32 Instance, const Pdb_Adc_Ip_ConfigType * const Config);
+
+/*!
+ * @brief Deinitialize PDB module
+ *
+ * This function resets the PDB internal registers to default values.
+ *
+ * When the PDB module is not used. Calling this function would shut down the
+ * PDB module and reduce the power consumption.
+ *
+ * Note: instance back to back configuration is common between PDB instances 0 and 1
+ * (configures the same register even if configured for either PDB instance)
+ * This function disables it, so affects all other instances.
+ *
+ * @param[in] Instance - PDB instance number
+ * @return void
+ */
+void Pdb_Adc_Ip_DeInit(const uint32 Instance);
+
+/*!
+ * @brief Enable the PDB module
+ *
+ * This function enables the PDB module, counter is on.
+ *
+ * @param[in] Instance - PDB instance number
+ * @return void
+ */
+void Pdb_Adc_Ip_Enable(const uint32 Instance);
+
+/*!
+ * @brief Disable the PDB module
+ *
+ * This function disables the PDB module, counter is off.
+ *
+ * @param[in] Instance - PDB instance number
+ */
+void Pdb_Adc_Ip_Disable(const uint32 Instance);
+
+/*!
+ * @brief Set PDB trigger source
+ *
+ * This function sets the PDB trigger source.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] TriggerSource - trigger source
+ * @return void
+ */
+void Pdb_Adc_Ip_SetTriggerInput(const uint32 Instance, const Pdb_Adc_Ip_TriggerSrcType TriggerSource);
+
+/*!
+ * @brief Set PDB mode
+ *
+ * This function sets the PDB mode to continuous or one shot.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] State - mode to set: continuous(true) or one shot(FALSE)
+ * @return void
+ */
+void Pdb_Adc_Ip_SetContinuousMode(const uint32 Instance, const boolean State);
+
+/*!
+ * @brief Trigger the PDB with a software trigger
+ *
+ * This function triggers the PDB with a software trigger.
+ * When the PDB is set to use the software trigger as input, calling this function
+ * triggers the PDB.
+ *
+ * @param[in] Instance - PDB instance number
+ * @return void
+ */
+void Pdb_Adc_Ip_SwTrigger(const uint32 Instance);
+
+/*!
+ * @brief Get the current value of the PDB counter
+ *
+ * This function gets the current counter value.
+ *
+ * @param[in] Instance - PDB instance number
+ * @return Current PDB counter value.
+ */
+uint32 Pdb_Adc_Ip_GetTimerValue(const uint32 Instance);
+
+/*!
+ * @brief Load buffered register values.
+ *
+ * This function sets the LDOK bit.
+ * Writing one to this bit updates the internal registers MOD, IDLY, CHnDLYm and
+ * POyDLY with the values written to their buffers. The MOD, IDLY,
+ * CHnDLYm and POyDLY take effect according to the load mode settings.
+ *
+ * After one is written to the LDOK bit, the values in the buffers of above mentioned
+ * registers are not effective and cannot be written until the values in the
+ * buffers are loaded into their internal registers. The moment when this happens
+ * depends on the value of the LDMOD register. Only when this register is in it's
+ * default state(0), the load operation will happen immediately. Please check the
+ * reference manual for more information.
+ * The LDOK can be written only when the the PDB is enabled or as alone with it. It is
+ * automatically cleared either when the values in the buffers are loaded into the
+ * internal registers or when the PDB is disabled.
+ *
+ * @param[in] Instance - PDB instance number
+ * @return void
+ */
+void Pdb_Adc_Ip_LoadRegValues(const uint32 Instance);
+
+/*!
+ * @brief Set the period of the counter
+ *
+ * This function sets the PDB Modulus value.
+ * Note: This function writes in an internal buffer. Depending on the
+ * value of the LDMOD register, it might be necessary to call
+ * Pdb_Adc_Ip_LoadRegValues in order to update the value of the register.
+ * The value of the register can be changed only when the PDB module is enabled.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ModVal - modulus value
+ * @return void
+ */
+void Pdb_Adc_Ip_SetModulus(const uint32 Instance, const uint16 ModVal);
+
+/*!
+ * @brief Configure all pretriggers on the selected channel
+ *
+ * This function configures the back to back modes, delay enable and output
+ * enable settings for all pretriggers on the selected channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] Config - pretriggers config
+ * @return void
+ */
+void Pdb_Adc_Ip_ConfigAdcPretriggers(const uint32 Instance, const uint8 ChanIdx, const Pdb_Adc_Ip_PretriggersConfigType * const Config);
+
+/*!
+ * @brief Get ADC pretrigger channel flags from the PDB module
+ *
+ * This function gets all ADC pretrigger flags from the selected channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @return bitmask of channel flags selected by pretriggMask
+ */
+uint32 Pdb_Adc_Ip_GetAdcPretriggerFlags(const uint32 Instance, const uint8 ChanIdx);
+
+/*!
+ * @brief Clear ADC pretrigger channel flags from the PDB module
+ *
+ * This function clears the ADC pretrigger channel flags selected by pretriggMask
+ * from channel channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] PretriggMask - ADC pretriggers mask
+ */
+void Pdb_Adc_Ip_ClearAdcPretriggerFlags(const uint32 Instance, const uint8 ChanIdx, const uint16 PretriggMask);
+
+/*!
+ * @brief Set back to back mode for the selected pretrigger
+ *
+ * This function sets back to back mode for the selected pretrigger on
+ * the given channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] PretriggIdx - ADC pretrigger index
+ * @param[in] Value - enable(true) or disable(FALSE)
+ */
+void Pdb_Adc_Ip_SetAdcPretriggerBackToBack(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value);
+
+/*!
+ * @brief Enable or disable the selected pretrigger
+ *
+ * This function enables or disables the selected pretrigger on the given channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] PretriggIdx - ADC pretrigger mask
+ * @param[in] Value - enable(true) or disable(FALSE)
+ */
+void Pdb_Adc_Ip_SetAdcPretriggerEnable(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value);
+
+/*!
+ * @brief Set the delay enable for the selected pretrigger
+ *
+ * This function sets the delay enable value for the selected pretrigger on
+ * the given channel.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] PretriggIdx - ADC pretrigger index
+ * @param[in] Value - enable(true) or disable(FALSE)
+ */
+void Pdb_Adc_Ip_SetAdcPretriggerDelayEnable(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value);
+
+/*!
+ * @brief Set the pretrigger delay value.
+ *
+ * This function sets the pretrigger delay value
+ * Note: This function writes in an internal buffer. Depending on the
+ * value of the LDMOD register, it might be necessary to call
+ * Pdb_Adc_Ip_LoadRegValues in order to update the value of the register.
+ * The value of the register can be changed only when the PDB module is enabled.
+ *
+ * @param[in] Instance - PDB instance number
+ * @param[in] ChanIdx - PDB channel
+ * @param[in] PretriggIdx - ADC pretrigger index
+ * @param[in] DelayValue - pretrigger delay value
+ */
+void Pdb_Adc_Ip_SetAdcPretriggerDelayValue(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const uint16 DelayValue);
+
+/*!
+ * @brief Disable and clear PDB module
+ *
+ * This function disables PDB module and clears all channels
+ * configuration and status registers.
+ * Note: This function does not deinitialize the module.
+ *
+ * @param[in] Instance - PDB instance number
+ */
+void Pdb_Adc_Ip_DisableAndClearPdb(const uint32 Instance);
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if defined (__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* PDB_ADC_IP_H */

RTD/include/Pdb_Adc_Ip_HwAccess.h

@@ -0,0 +1,128 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_PDB_ADC_IP_HW_ACCESS_H
+#define PDB_PDB_ADC_IP_HW_ACCESS_H
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup pdb_adc_ip Pdb Adc IPL
+*   @{
+*/
+
+#include "StandardTypes.h"
+
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define PDB_ADC_IP_VENDOR_ID_HWACCESS_H                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_HWACCESS_H               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_HWACCESS_H               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_HWACCESS_H               0
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Pdb_Adc_Ip_HwAccess.h file and StandardTypes.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MAJOR_VERSION) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_HwAccess.h and StandardTypes.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+static inline void Pdb_Adc_HwAcc_SetAdcPretriggerMask(PDB_Type * const Base, const uint8 ChanIdx, const uint32 Mask, const boolean Value)
+{
+    /* Set C1 register of a channel based on mask */
+    if (Value == TRUE)
+    {
+        Base->CH[ChanIdx].C1 |= Mask;
+    }
+    else
+    {
+        Base->CH[ChanIdx].C1 &= ~(Mask);
+    }
+}
+
+static inline void Pdb_Adc_HwAcc_DisablePdb(PDB_Type * const Base)
+{
+    /* Disable PDB by clearing PDBEN bit of SC register */
+    Base->SC &= ~(PDB_SC_PDBEN_MASK);
+}
+
+static inline void Pdb_Adc_HwAcc_SetContinuousMode(PDB_Type * const Base, const boolean State)
+{
+    /* Update ContinuousMode value found in SC register */
+    if (State == TRUE)
+    {
+        Base->SC |= PDB_SC_CONT_MASK;
+    }
+    else
+    {
+        Base->SC &= ~(PDB_SC_CONT_MASK);
+    }
+}
+
+static inline void Pdb_Adc_HwAcc_ConfigAdcPretriggers(PDB_Type * const Base, const uint8 ChanIdx, const Pdb_Adc_Ip_PretriggersConfigType * const Config)
+{
+    /* Configure all channel's pretriggers by updating all fields of the C1 register */
+    uint32 C1Reg = Base->CH[ChanIdx].C1;
+    C1Reg &= ~(PDB_C1_EN_MASK | PDB_C1_TOS_MASK | PDB_C1_BB_MASK);
+    C1Reg |= PDB_C1_EN(Config->EnableMask);
+    C1Reg |= PDB_C1_TOS(Config->EnableDelayMask);
+    C1Reg |= PDB_C1_BB(Config->BackToBackEnableMask);
+    Base->CH[ChanIdx].C1 = C1Reg;
+}
+
+static inline void Pdb_Adc_HwAcc_ClearAdcPretriggerFlags(PDB_Type * const Base, const uint8 ChanIdx, const uint16 PretriggMask)
+{
+    /* Clear pretrigger status flags found in S register based on PretriggMask */
+    Base->CH[ChanIdx].S &= ~PDB_S_CF(PretriggMask);
+}
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if defined (__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* PDB_PDB_ADC_IP_HW_ACCESS_H */

RTD/include/Pdb_Adc_Ip_Types.h

@@ -0,0 +1,226 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_ADC_IP_TYPES_H
+#define PDB_ADC_IP_TYPES_H
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip Pdb Adc IPL
+*   @{
+*/
+
+#include "StandardTypes.h"
+#include "Pdb_Adc_Ip_CfgDefines.h"
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define PDB_ADC_IP_VENDOR_ID_TYPES_H                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H               0
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Pdb_Adc_Ip_Types.h file and Pdb_Adc_Ip_CfgDefines.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_TYPES_H != PDB_ADC_IP_VENDOR_ID_CFGDEFINES_H)
+    #error "Pdb_Adc_Ip_Types.h and Pdb_Adc_Ip_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_Types.h file and Pdb_Adc_Ip_CfgDefines.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_Types.h and Pdb_Adc_Ip_CfgDefines.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_Types.h file and Pdb_Adc_Ip_CfgDefines.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H != PDB_ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H != PDB_ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H != PDB_ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_Types.h and Pdb_Adc_Ip_CfgDefines.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Pdb_Adc_Ip_Types.h file and StandardTypes.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H != STD_AR_RELEASE_MAJOR_VERSION) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H != STD_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_Types.h and StandardTypes.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/*==================================================================================================
+*                              STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*!
+ * @brief Defines the type of value load mode for the PDB module.
+ *
+ * Some timing related registers, such as the MOD, IDLY, CHnDLYm, INTx and POyDLY,
+ * buffer the setting values. Only the load operation is triggered.
+ * The setting value is loaded from a buffer and takes effect. There are
+ * four loading modes to fit different applications.
+ * Implements : Pdb_Adc_Ip_LoadValueModeType_Class
+ */
+typedef enum
+{
+    PDB_ADC_IP_LOAD_VAL_IMMEDIATELY                        = 0U, /*!< Loaded immediately after load operation. */
+    PDB_ADC_IP_LOAD_VAL_AT_MODULO_COUNTER                  = 1U, /*!< Loaded when counter hits the modulo after load operation. */
+    PDB_ADC_IP_LOAD_VAL_AT_NEXT_TRIGGER                    = 2U, /*!< Loaded when detecting an input trigger after load operation. */
+    PDB_ADC_IP_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER  = 3U  /*!< Loaded when counter hits the modulo or detecting an input trigger after load operation. */
+} Pdb_Adc_Ip_LoadValueModeType;
+
+/*!
+ * @brief Defines the type of prescaler divider for the PDB counter clock.
+ * Implements : Pdb_Adc_Ip_ClkPrescalerDivType_Class
+ */
+typedef enum
+{
+    PDB_ADC_IP_CLK_PREDIV_BY_1   = 0U, /*!< Counting divided by 1 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_2   = 1U, /*!< Counting divided by 2 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_4   = 2U, /*!< Counting divided by 4 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_8   = 3U, /*!< Counting divided by 8 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_16  = 4U, /*!< Counting divided by 16 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_32  = 5U, /*!< Counting divided by 32 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_64  = 6U, /*!< Counting divided by 64 x prescaler multiplication factor (selected by MULT). */
+    PDB_ADC_IP_CLK_PREDIV_BY_128 = 7U  /*!< Counting divided by 128 x prescaler multiplication factor (selected by MULT). */
+} Pdb_Adc_Ip_ClkPrescalerDivType;
+
+/*!
+ * @brief Defines the type of the multiplication source mode for PDB.
+ *
+ * Selects the multiplication factor of the prescaler divider for the PDB counter clock.
+ * Implements : Pdb_Adc_Ip_ClkPrescalerMultFactType_Class
+ */
+typedef enum
+{
+    PDB_ADC_IP_CLK_PREMULT_FACT_AS_1  = 0U, /*!< Multiplication factor is 1. */
+    PDB_ADC_IP_CLK_PREMULT_FACT_AS_10 = 1U, /*!< Multiplication factor is 10. */
+    PDB_ADC_IP_CLK_PREMULT_FACT_AS_20 = 2U, /*!< Multiplication factor is 20. */
+    PDB_ADC_IP_CLK_PREMULT_FACT_AS_40 = 3U  /*!< Multiplication factor is 40. */
+} Pdb_Adc_Ip_ClkPrescalerMultFactType;
+
+/*!
+ * @brief Defines the type of trigger source mode for the PDB.
+ *
+ * Selects the trigger input source for the PDB. The trigger input source can
+ * be internal or the software trigger.
+ * Implements : Pdb_Adc_Ip_TriggerSrcType_Class
+ */
+typedef enum
+{
+    PDB_ADC_IP_TRIGGER_IN0         = 0U,    /*!< Source trigger comes from TRGMUX. */
+    PDB_ADC_IP_SOFTWARE_TRIGGER    = 15U    /*!< Select software trigger. */
+} Pdb_Adc_Ip_TriggerSrcType;
+
+/*!
+ * @brief Defines the sequence error notification header
+ *
+ * This header is used for sequence error notification callbacks
+ *
+ * Implements : Pdb_Adc_Ip_SeqErrNotificationType_Class
+ */
+typedef void Pdb_Adc_Ip_SeqErrNotificationType(uint8 ChanIdx, uint16 SeqErrMask);
+
+/*!
+ * @brief Defines the type of structure for configuring an ADC pretrigger.
+ * Implements : Pdb_Adc_Ip_PretriggerConfigType_Class
+ */
+typedef struct
+{
+    uint8 EnableMask;           /*!< Mask of enabled pretriggers. */
+    uint8 EnableDelayMask;      /*!< Mask of pretriggers with delays enabled. */
+    uint8 BackToBackEnableMask; /*!< Mask of pretriggers with back to back mode enabled.
+                                    If enabled, the pretrigger will be activated automatically when the ADC COCO flag corresponding to the previous pretrigger in the chain, is set.
+                                    The previous pretrigger for pretriggers with index 0, depend on features InstanceBackToBackEnable and InterChannelBackToBackEnable. */
+} Pdb_Adc_Ip_PretriggersConfigType;
+
+/*!
+ * @brief Defines the type of structure for configuring a single PDB channel.
+ * Implements : Pdb_Adc_Ip_ChanConfigType_Class
+ */
+typedef struct
+{
+    uint8 ChnIdx;                                       /*!< PDB channel index. */
+    Pdb_Adc_Ip_PretriggersConfigType PretriggersConfig; /*!< Pretriggers configuration. */
+    uint16 PretriggerDelays[PDB_DLY_COUNT];             /*!< Pretriggers delay array, positional dependent(delay for pretrigger 0 must be at index 0) */
+} Pdb_Adc_Ip_ChanConfigType;
+
+/*!
+ * @brief Defines the type of structure for basic timer in PDB.
+ *
+ * Implements : Pdb_Adc_Ip_ConfigType_Class
+ */
+typedef struct
+{
+    Pdb_Adc_Ip_LoadValueModeType LoadValueMode;           /*!< Select the load mode. */
+    Pdb_Adc_Ip_ClkPrescalerDivType PrescalerDiv;          /*!< Select the prescaler divider. */
+    Pdb_Adc_Ip_ClkPrescalerMultFactType ClkPreMultFactor; /*!< Select multiplication factor for prescaler. */
+    Pdb_Adc_Ip_TriggerSrcType TriggerSource;              /*!< Select the trigger input source. */
+    boolean ContinuousModeEnable;                         /*!< Enable the continuous mode. */
+    boolean DmaEnable;                                    /*!< Enable the dma for timer. */
+    uint16 ModValue;                                      /*!< Modulus register value. */
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+    boolean InstanceBackToBackEnable;                     /*!< Enable the instance back to back mode between PDB0 CH0 and PDB1 CH0 pretriggers, forming a ring (PDB0_CH0_pretrigger7 -> PDB1_CH0_pretrigger0 and PDB1_CH0_pretrigger7 -> PDB0_CH0_pretrigger0).
+                                                            Note: this configuration is common between all PDB instances (configures the same register SIM_CHIPCTL[PDB_BB_SEL] even if configured for either PDB instance)
+                                                            Enabling when configuring PDB0, then disabling when configuring PDB1, will result in being disabled.
+                                                            Note: must not be enabled simultaneously with inter-channel back to back on any PDB instance. */
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+    boolean InterChannelBackToBackEnable;   /*!< Enable the inter-channel back to back mode between PDBx CH0 and PDBx CH1 pretriggers, forming a ring (PDBx_CH0_pretrigger7 -> PDBx_CH1_pretrigger0 and PDBx_CH1_pretrigger7 -> PDBx_CH0_pretrigger0).
+                                                Note: this configuration is dedicated to each PDB instance.
+                                                Note: must not be enabled simultaneously with instance back to back on any PDB instance. */
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+
+    uint8 NumChans;                                         /*!< Number of PDB Channels */
+    const Pdb_Adc_Ip_ChanConfigType * ChanConfigs;          /*!< PDB Channel configuration */
+
+    Pdb_Adc_Ip_SeqErrNotificationType * SeqErrNotification; /*!< Sequence error notification. */
+} Pdb_Adc_Ip_ConfigType;
+
+/*!
+ * @brief Structure used to store runtime info
+ *
+ * This structure is used to store PDB runtime info
+ *
+ * Implements : Pdb_Adc_Ip_StateStructType_Class
+ */
+typedef struct
+{
+    boolean Init;      /*!< Check if the driver was initialized. */
+
+    /* Sequence error notification */
+    Pdb_Adc_Ip_SeqErrNotificationType * SeqErrNotification; /*!< Sequence error notification */
+} Pdb_Adc_Ip_StateStructType;
+/** @} */
+
+#endif /* PDB_ADC_IP_TYPES_H */

RTD/include/SchM_Adc.h

@@ -0,0 +1,334 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : 
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SCHM_ADC_H
+#define SCHM_ADC_H
+
+/**
+*   @file
+*
+*   @addtogroup RTE_MODULE
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SCHM_ADC_AR_RELEASE_MAJOR_VERSION     4
+#define SCHM_ADC_AR_RELEASE_MINOR_VERSION     4
+#define SCHM_ADC_AR_RELEASE_REVISION_VERSION  0
+#define SCHM_ADC_SW_MAJOR_VERSION             1
+#define SCHM_ADC_SW_MINOR_VERSION             0
+#define SCHM_ADC_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                           CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+/*==================================================================================================
+*                                           CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+/* Number of cores id */
+#define NUMBER_OF_CORES         (uint8)(1U)
+
+
+
+
+#ifdef MCAL_TESTING_ENVIRONMENT
+/** 
+@brief   This function checks that all entered exclusive areas were also exited. 
+@details This function checks that all entered exclusive areas were also exited. The check
+         is done by verifying that all reentry_guard_* static variables are back to the
+         zero value.
+    
+@param[in]     void       No input parameters
+@return        void       This function does not return a value. Test asserts are used instead. 
+
+@pre  None
+@post None
+
+@remarks Covers 
+@remarks Implements 
+*/
+void SchM_Check_adc(void);
+#endif /*MCAL_TESTING_ENVIRONMENT*/
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_06(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_06(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_54(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_54(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_55(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_55(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_56(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_56(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_57(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_57(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_58(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_58(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_59(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_59(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_60(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_60(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_61(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_61(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_62(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_62(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_63(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_63(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_64(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_64(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_66(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_66(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_67(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_67(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_68(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_68(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_69(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_69(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_70(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_70(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_71(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_71(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_72(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_72(void);
+
+extern void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_73(void);
+extern void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_73(void);
+
+
+
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* SCHM_ADC_H */

RTD/src/Adc.c

@@ -0,0 +1,5862 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Adc.c
+*   @implements      Adc.c_Artifact
+*   @addtogroup adc_driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc.h"
+#include "Adc_Ipw.h"
+#include "Det.h"
+#include "SchM_Adc.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_C                         43
+#define ADC_AR_RELEASE_MAJOR_VERSION_C          4
+#define ADC_AR_RELEASE_MINOR_VERSION_C          4
+#define ADC_AR_RELEASE_REVISION_VERSION_C       0
+#define ADC_SW_MAJOR_VERSION_C                  1
+#define ADC_SW_MINOR_VERSION_C                  0
+#define ADC_SW_PATCH_VERSION_C                  0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc.c and Adc.h are of the same vendor */
+#if (ADC_VENDOR_ID_C != ADC_VENDOR_ID)
+#error "Adc.c and Adc.h have different vendor ids"
+#endif
+
+/* Check if Adc.c and Adc.h are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_C != ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_C != ADC_AR_RELEASE_MINOR_VERSION) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_C != ADC_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc.c and Adc.h are different"
+#endif
+
+/* Check if Adc.c and Adc.h are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_C != ADC_SW_MAJOR_VERSION) || \
+     (ADC_SW_MINOR_VERSION_C != ADC_SW_MINOR_VERSION) || \
+     (ADC_SW_PATCH_VERSION_C != ADC_SW_PATCH_VERSION) \
+    )
+#error "Software Version Numbers of Adc.c and Adc.h are different"
+#endif
+
+/* Check if Adc.c and Adc_Ipw.h are of the same vendor */
+#if (ADC_VENDOR_ID_C != ADC_VENDOR_ID_IPW_H)
+    #error "Adc.c and Adc_Ipw.h have different vendor ids"
+#endif
+
+/* Check if Adc.c and Adc_Ipw.h are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_H) \
+    )
+#error "AutoSar Version Numbers of Adc.c and Adc_Ipw.h are different"
+#endif
+
+/* Check if Adc.c and Adc_Ipw.h are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_C != ADC_SW_MAJOR_VERSION_IPW_H) || \
+     (ADC_SW_MINOR_VERSION_C != ADC_SW_MINOR_VERSION_IPW_H) || \
+     (ADC_SW_PATCH_VERSION_C != ADC_SW_PATCH_VERSION_IPW_H) \
+    )
+#error "Software Version Numbers of Adc.c and Adc_Ipw.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Adc.c and SchM_Adc.h are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_C != SCHM_ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_C != SCHM_ADC_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc.c and SchM_Adc.h are different"
+#endif
+
+/* Check if Adc.c and Det.h are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_C != DET_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_C != DET_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc.c and Det.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Global Configuration Pointer.
+* @details        Data structure containing the set of configuration parameters required for
+*                 initializing the ADC Driver and ADC HW Unit(s).
+*
+*/
+const Adc_ConfigType * Adc_pCfgPtr[ADC_MAX_PARTITIONS];
+
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+/**
+* @brief          Global Driver Status.
+* @details        Data structure containing the ADC driver status
+*                 uninit, during init or already init.
+*
+*/
+static Adc_GlobalStateType Adc_eGlobalState[ADC_MAX_PARTITIONS];
+#endif /* ADC_VALIDATE_GLOBAL_CALL == STD_ON */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+/**
+* @brief          Clock mode in use
+* @details        The current used clock mode: normal or alternate clock.
+*/
+Adc_SelectPrescalerType Adc_eClockMode[ADC_MAX_PARTITIONS];
+#endif /*if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)*/
+#endif /*if (ADC_DUAL_CLOCK_MODE == STD_ON)*/
+
+/**
+* @brief          Group status array structure
+* @details        Array to hold all the groups status information are indexed by group id.
+*/
+Adc_GroupStatusType Adc_aGroupStatus[ADC_MAX_GROUPS];
+
+/**
+* @brief          Unit status structure
+* @details        Structure for the units status are indexed by logical id.
+*/
+Adc_UnitStatusType Adc_aUnitStatus[ADC_MAX_HW_UNITS];
+
+/**
+* @brief          Runtime group channels array
+* @details        Hold the runtime group channels.
+*/
+#if (ADC_SETCHANNEL_API == STD_ON)
+Adc_RuntimeGroupChannelType Adc_aRuntimeGroupChannel[ADC_MAX_GROUPS];
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+static Adc_PowerStateType Adc_eCurrentState[ADC_MAX_PARTITIONS];
+static Adc_PowerStateType Adc_eTargetState[ADC_MAX_PARTITIONS];
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/**
+* @brief          Unit status structure
+* @details        Structure for the unit status.
+*
+*/
+Adc_ChansIdxMaskType Adc_aNCMRxMask[ADC_NO_OF_ENABLE_CH_DISABLE_CH_GROUPS]; /* TODO: rename to Adc_aRuntimeChansEnMask */
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+#define ADC_START_SEC_VAR_CLEARED_8
+#include "Adc_MemMap.h"
+/**
+* @brief          Active BCTU triggers for the group in the HW queue
+* @details        This array is used in Adc_Ipw_EnableCtuTrigger. For the group currently in the HW queue,
+*                 if an element is 1 in this array, the corresponding trigger from the group's configuration structure
+*                 has been activated.
+*/
+static uint8 Adc_au8CtuGroupTriggersActive[ADC_MAX_HW_UNITS][ADC_MAX_HARDWARE_TRIGGERS];
+
+#define ADC_STOP_SEC_VAR_CLEARED_8
+#include "Adc_MemMap.h"
+#endif /* (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) */
+
+#if (ADC_ENABLE_TEMPSENSE_API == STD_ON)
+#define ADC_START_SEC_VAR_CLEARED_BOOLEAN
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Temperature channel is on-going conversion or not
+* @details        Temperature channel is on-going conversion or not
+*/
+static boolean bTempsenseInUsed;
+
+#define ADC_STOP_SEC_VAR_CLEARED_BOOLEAN
+#include "Adc_MemMap.h"
+#endif /* (ADC_ENABLE_TEMPSENSE_API == STD_ON) */
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if ((ADC_VALIDATE_PARAMS == STD_ON) && \
+     ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+      (ADC_HW_TRIGGER_API == STD_ON) || \
+      (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+      (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+     ) \
+    )
+static inline Std_ReturnType Adc_ValidateExtraParams
+(
+    uint8 u8ServiceId,
+    uint32 u32ErrorIdList,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+static inline Std_ReturnType Adc_ValidateCallAndGroup
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+static inline Std_ReturnType Adc_NotifyCapablity
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+#endif
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline void Adc_ReportDetError
+(
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+);
+
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+static inline void Adc_ReportDetRuntimeError
+(
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+);
+
+#if ((ADC_DEV_ERROR_DETECT == STD_ON) && \
+     ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+      (ADC_HW_TRIGGER_API == STD_ON) || \
+      (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+      (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+     ) \
+    )
+static void Adc_ReportValidationError
+(
+    Adc_ValidationResultType * pResult,
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+);
+#endif
+
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+static inline Std_ReturnType Adc_ValidateGloballCall
+(
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+static inline Std_ReturnType Adc_ValidatePtrInit
+(
+    const Adc_ConfigType * pConfigPtr
+);
+
+static inline Std_ReturnType Adc_ValidatePtr
+(
+    uint8 u8ServiceId,
+    const void * pPtrVal
+);
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON))
+static inline void Adc_ValidateBufferUninit
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+     (ADC_HW_TRIGGER_API == STD_ON) || \
+     (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+     (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+    )
+static inline void Adc_ValidateTriggerSrc
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+static inline void Adc_ValidateQueueNotFull
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON) || \
+    (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+static inline void Adc_ValidateConvMode
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+static inline void Adc_ValidateEnableDisbleGroupList
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+
+static inline Std_ReturnType Adc_ValidateEnableDisbleIdList
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    Adc_ChannelType Channel,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+static inline Std_ReturnType Adc_ValidateCallAndTrigger
+(
+    uint8 u8ServiceId,
+    uint8 u8Trigger,
+    uint32 u32CoreId
+);
+#endif
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+static inline Std_ReturnType Adc_ValidateSetHwUnitPowerMode
+(
+    Adc_SetPowerModeType eSetHwUnitPowerMode,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+static inline void Adc_EndValidateGloballCall
+(
+    Std_ReturnType ValidCall,
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_DEINIT_API == STD_ON)
+static inline Std_ReturnType Adc_ValidateDeInitNotBusy
+(
+    uint32 u32CoreId
+);
+#endif /* (ADC_DEINIT_API == STD_ON) */
+
+static inline Std_ReturnType Adc_ValidateSetupBufferNotBusy
+(
+    Adc_GroupType Group
+);
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+static inline Std_ReturnType Adc_ValidateStateStartGroupConvNotBusy
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if ((ADC_HW_TRIGGER_API == STD_ON))
+static inline Std_ReturnType Adc_ValidateStateEnableHwTriggNotBusy
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* ((ADC_HW_TRIGGER_API == STD_ON)) */
+
+static inline Std_ReturnType Adc_ValidateStateNotIdle
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+
+#if ((ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) && ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON)))
+static inline Std_ReturnType Adc_ValidateNotBusyWithPrio
+(
+    Adc_GroupType Group,
+    boolean bImplicitly,
+    uint32 u32CoreId
+);
+#endif /* ((ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) && ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON))) */
+
+#if ((ADC_HW_TRIGGER_API == STD_ON) || (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON))
+static inline Std_ReturnType Adc_ValidateNotBusyEnableHwTrig
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+#if ((ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) && (ADC_ENABLE_START_STOP_GROUP_API == STD_ON))
+static inline Std_ReturnType Adc_ValidateNotBusyNoPrio
+(
+    Adc_GroupType Group,
+    boolean bImplicitly,
+    uint32 u32CoreId
+);
+#endif /* ((ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) && (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)) */
+
+#if (((ADC_HW_TRIGGER_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+      || ((ADC_DEINIT_API == STD_ON))        \
+      ||  (ADC_CALIBRATION == STD_ON) || (ADC_DUAL_CLOCK_MODE == STD_ON) \
+      || (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) || (ADC_POWER_STATE_SUPPORTED == STD_ON) \
+      || ((ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) && (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+      || (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || (ADC_POWER_STATE_SUPPORTED == STD_ON) \
+      || (ADC_ENABLE_TEMPSENSE_API == STD_ON) || ((ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+    )
+static inline Std_ReturnType Adc_ValidateNotBusyNoQueue
+(
+    Adc_HwUnitType Unit,
+    uint8 u8ServiceId
+);
+#endif /* (((ADC_HW_TRIGGER_API == STD_ON) && ...  */
+
+#if (((ADC_DEINIT_API == STD_ON)) \
+      || (ADC_CALIBRATION == STD_ON) || (ADC_DUAL_CLOCK_MODE == STD_ON) || (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) \
+      || (ADC_ENABLE_TEMPSENSE_API == STD_ON) \
+    )
+static inline Std_ReturnType Adc_ValidateCheckGroupNotConversion
+(
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+);
+#endif /* (((ADC_DEINIT_API == STD_ON) ... */
+
+#if (((ADC_ENABLE_READ_RAW_DATA_API == STD_ON) || (ADC_CALIBRATION == STD_ON) \
+   || (ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON) || defined(__DOXYGEN__) \
+   || (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON) || (ADC_SELF_TEST == STD_ON) \
+   || (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || defined(ADC_WDG_SUPPORTED) \
+   || (ADC_ENABLE_TEMPSENSE_API == STD_ON)) && (ADC_VALIDATE_CALL_AND_UNIT == STD_ON))
+static inline Std_ReturnType Adc_ValidateCallAndUnit
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+#endif /* (ADC_VALIDATE_CALL_AND_UNIT == STD_ON) ... */
+
+static inline void Adc_InitGroupsStatus
+(
+    uint32 u32CoreId
+);
+
+static inline void Adc_InitUnitStatus
+(
+    uint32 u32CoreId
+);
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) && (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE))
+static inline Std_ReturnType Adc_InsertIntoQueue
+(
+    const Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+static inline void Adc_UpdateStatusStartConversion
+(
+    const Adc_GroupType Group,
+    const Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+
+static inline Std_ReturnType Adc_StopSwGroupConversion
+(
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType * RemovedPos,
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+
+static inline void Adc_UpdateStatusStopConversion
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_READ_GROUP_API == STD_ON)
+static inline void Adc_UpdateStatusReadGroup
+(
+    const Adc_GroupType Group,
+    const boolean bFlag,
+    uint32 u32CoreId
+);
+
+static inline void Adc_UpdateStatusReadGroupNoInt
+(
+    const Adc_GroupType Group,
+    const boolean bFlag,
+    uint32 u32CoreId
+);
+
+static inline void Adc_UpdateSwQueueIndexNoInt
+(
+    const Adc_GroupType Group,
+    uint32 u32CoreId
+);
+
+static inline void Adc_UpdateStatusReadGroupInt
+(
+    const Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+static inline void Adc_UpdateStatusEnableHardware
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit
+);
+
+static inline void Adc_UpdateStatusDisableHardware
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit
+);
+#endif
+
+static inline void Adc_UpdateStatusAfterGetStream
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_ValidateUnitActive
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+static inline Std_ReturnType Adc_ValidateStateCtuControlMode
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit
+);
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+static inline Std_ReturnType Adc_ValidateStateAndPtr
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+);
+static inline Std_ReturnType Adc_ValidateIdleState
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+);
+static inline Std_ReturnType Adc_ValidatePowerStateSupport
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateType ePowerState,
+    Adc_PowerStateRequestResultType * pResult
+);
+static inline Std_ReturnType Adc_ValidatePowerStatePrepare
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+);
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+static inline Std_ReturnType Adc_CheckCurrentCoreId
+(
+    const Adc_ConfigType * pCfgPtr,
+    uint32 u32CoreId
+);
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) || defined(__DOXYGEN__)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_CheckTriggerSourceRange
+(
+    uint8 u8ServiceId,
+    Adc_HwTriggerTimerType TriggerSource,
+    boolean bTriggFound
+);
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+#endif /* (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) || defined(__DOXYGEN__) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_CheckSetChannelParams
+(
+    const Adc_GroupType Group,
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+    const uint16 * Delays,
+    const uint32 ChannelUpdateMask,
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+    const Adc_ChannelIndexType NumberOfChannel
+);
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+#if ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON))
+static inline Std_ReturnType Adc_CheckSetChannelCtuTriggers
+(
+    const Adc_GroupType GroupIndex,
+    const Adc_HwUnitType LogicalHwUnitId,
+    const Adc_ChannelIndexType NumberOfChannel,
+    const uint32 u32CoreId
+);
+#endif /* ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON)) */
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+#if ((ADC_DUAL_CLOCK_MODE == STD_ON) && (ADC_DEV_ERROR_DETECT == STD_ON))
+static inline boolean Adc_CheckSetClockModeCoreAndParam
+(
+    const Adc_SelectPrescalerType Prescaler,
+    const uint32 u32CoreId
+);
+#endif /* ((ADC_DUAL_CLOCK_MODE == STD_ON) && (ADC_DEV_ERROR_DETECT == STD_ON)) */
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief      This function reports an development error to the Det module and records the failure in the local structure.
+* @details    This function reports an development error to the Det module and records the failure in the local structure.
+*
+* @param[in]  u8ServiceId       The service id of the caller function
+* @param[in]  u8ErrorId         The error id to be reported
+*
+* @return     void
+* SWS_Adc_00377
+*/
+static inline void Adc_ReportDetError
+(
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+)
+{
+    (void)Det_ReportError((uint16)ADC_MODULE_ID, (uint8)0U, u8ServiceId, u8ErrorId);
+}
+
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+/**
+* @brief      This function reports an runtime error to the Det module and records the failure in the local structure.
+* @details    This function reports an runtime error to the Det module and records the failure in the local structure.
+*
+* @param[in]  u8ServiceId       The service id of the caller function
+* @param[in]  u8ErrorId         The error id to be reported
+*
+* @return     void
+* SWS_Adc_00530
+*/
+static inline void Adc_ReportDetRuntimeError
+(
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+)
+{
+    (void)Det_ReportRuntimeError((uint16)ADC_MODULE_ID, (uint8)0U, u8ServiceId, u8ErrorId);
+}
+
+#if ((ADC_DEV_ERROR_DETECT == STD_ON) && \
+     ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+      (ADC_HW_TRIGGER_API == STD_ON) || \
+      (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+      (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+     ) \
+    )
+/**
+* @brief      This function reports an error to the Det module and records the failure in the local structure.
+* @details    This function reports an error to the Det module and records the failure in the local structure.
+*
+* @param[in]  u8ServiceId       The service id of the caller function
+* @param[in]  u8ErrorId         The error id to be reported
+* @param[in]  pResult           Pointer to the structure where the failure must be recorded
+*
+* @return     void
+*/
+static void Adc_ReportValidationError
+(
+    Adc_ValidationResultType * pResult,
+    uint8 u8ServiceId,
+    uint8 u8ErrorId
+)
+{
+    pResult->bEndValidations = TRUE;
+    pResult->ValidParams = (Std_ReturnType)E_NOT_OK;
+
+    Adc_ReportDetError(u8ServiceId, u8ErrorId);
+}
+#endif
+
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+/**
+* @brief      This function validates the global call parameters.
+* @details    This service is a non reentrant function used for validating the calls for functions
+*               like Adc_Init, Adc_DeInit.
+*
+* @param[in]  u8ServiceId       The service id of the caller function
+* @param[in]  u32CoreId         Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid call
+* @retval     E_NOT_OK:       Invalid call
+*
+* @api
+*
+* @note       Non Re-entrant function.
+* @implements  Adc_ValidateGlobalCall_Activity
+*
+*/
+static inline Std_ReturnType Adc_ValidateGloballCall
+(
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+
+    if (ADC_STATE_UNINIT == Adc_eGlobalState[u32CoreId])
+    {
+        if (ADC_INIT_ID == u8ServiceId)
+        {
+            ValidState = (Std_ReturnType)E_OK;
+        }
+        else
+        {
+            /* SWS_Adc_00154 */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+        }
+    }
+    else
+    {
+        if (ADC_INIT_ID == u8ServiceId)
+        {
+            /* Error: ADC already initialized */
+            /* SWS_Adc_00107 */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_ALREADY_INITIALIZED);
+        }
+        else
+        {
+            ValidState = (Std_ReturnType)E_OK;
+        }
+    }
+
+    return ValidState;
+}
+#endif /* ADC_VALIDATE_GLOBAL_CALL == STD_ON */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+/**
+* @brief      This function validates the global call parameters.
+* @details    This service is a non reentrant function used for validating parameters
+*               for Adc_Init.
+*
+* @param[in]  pConfigPtr   Pointer to configuration set in Variant PB
+*                         (Variant PC requires a NULL_PTR).
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid parameter
+* @retval     E_NOT_OK:       Invalid parameter
+*
+* @api
+*
+* @note       Non Reentrant function.
+*
+*/
+static inline Std_ReturnType Adc_ValidatePtrInit
+(
+    const Adc_ConfigType * pConfigPtr
+)
+{
+    Std_ReturnType ValidPtr = (Std_ReturnType)E_OK;
+
+#if (ADC_PRECOMPILE_SUPPORT == STD_ON)
+    /* ADC344 */
+    if (NULL_PTR != pConfigPtr)
+#else
+    /* ADC343 */
+    if (NULL_PTR == pConfigPtr)
+#endif /* (ADC_PRECOMPILE_SUPPORT == STD_ON) */
+    {
+        ValidPtr = (Std_ReturnType)E_NOT_OK;
+        Adc_ReportDetError((uint8)ADC_INIT_ID, (uint8) ADC_E_PARAM_POINTER);
+    }
+    return ValidPtr;
+}
+
+/**
+* @brief      This function validates the pointer is NULL or not
+* @details    This service is a reentrant function used for validating parameters
+*
+* @param[in]  PtrVal          Pointer to validate
+* @param[in]  u8ServiceId     The service id of the caller function
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid parameter
+* @retval     E_NOT_OK:       Invalid parameter
+*
+* @api
+*
+* @note       ...
+* ADC_VALUEREADGROUP_ID
+*/
+static inline Std_ReturnType Adc_ValidatePtr
+(
+    uint8 u8ServiceId,
+    const void * pPtrVal
+)
+{
+    Std_ReturnType ValidPtr = (Std_ReturnType)E_OK;
+
+    /* SWS_Adc_00458, SWS_Adc_00457, CPR_RTD_00264.adc */
+    if (NULL_PTR == pPtrVal)
+    {
+        ValidPtr = (Std_ReturnType)E_NOT_OK;
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_POINTER);
+    }
+
+    return ValidPtr;
+}
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON))
+static inline void Adc_ValidateBufferUninit
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    switch (u8ServiceId)
+    {
+        case ADC_STARTGROUPCONVERSION_ID:
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        case ADC_ENABLEHARDWARETRIGGER_ID:
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+        {
+            if (NULL_PTR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].pResultsBufferPtr[Group])
+            {
+                /* SWS_Adc_00425, SWS_Adc_00424 */
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_BUFFER_UNINIT);
+            }
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+}
+#endif
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+     (ADC_HW_TRIGGER_API == STD_ON) || \
+     (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+     (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+    )
+static inline void Adc_ValidateTriggerSrc
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    /* Get the mapping index of group in the current partition */
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    switch (u8ServiceId)
+    {
+        case ADC_STARTGROUPCONVERSION_ID:
+        case ADC_STOPGROUPCONVERSION_ID:
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+        case ADC_ENABLE_CHANNEL_ID:
+        case ADC_DISABLE_CHANNEL_ID:
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+        {
+            if (ADC_TRIGG_SRC_SW != Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource)
+            {
+                /* SWS_Adc_00164, SWS_Adc_00133 */
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_WRONG_TRIGG_SRC);
+            }
+            break;
+        }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        case ADC_ENABLEHARDWARETRIGGER_ID:
+        case ADC_DISABLEHARDWARETRIGGER_ID:
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+        case ADC_ENABLECTUTRIGGER_ID:
+        case ADC_DISABLECTUTRIGGER_ID:
+#endif /* ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON */
+        {
+            if (ADC_TRIGG_SRC_SW == (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource))
+            {
+                /* SWS_Adc_00136, SWS_Adc_00137 */
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_WRONG_TRIGG_SRC);
+            }
+            break;
+        }
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+}
+#endif
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+static inline void Adc_ValidateQueueNotFull
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+
+    /* Get the mapping index of group in the current partition */
+    GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+
+    switch (u8ServiceId)
+    {
+        case ADC_STARTGROUPCONVERSION_ID:
+        {
+            if (ADC_CONV_TYPE_NORMAL == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType)
+            {
+                if (Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex >= ADC_QUEUE_MAX_DEPTH_MAX)
+                {
+                    Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_QUEUE_FULL);
+                }
+            }
+            break;
+        }
+
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON) || \
+    (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+static inline void Adc_ValidateConvMode
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    switch (u8ServiceId)
+    {
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        case ADC_ENABLEHARDWARETRIGGER_ID:
+        case ADC_DISABLEHARDWARETRIGGER_ID:
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+        case ADC_ENABLECTUTRIGGER_ID:
+        case ADC_DISABLECTUTRIGGER_ID:
+#endif /* ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON */
+        {
+            if (ADC_CONV_MODE_CONTINUOUS == (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode))
+            {
+                /* SWS_Adc_00282, SWS_Adc_00281 */
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_WRONG_CONV_MODE);
+            }
+            break;
+        }
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+        case ADC_ENABLE_CHANNEL_ID:
+        case ADC_DISABLE_CHANNEL_ID:
+        {
+            if(ADC_CONV_TYPE_INJECTED == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType)
+            {
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_WRONG_CONV_MODE);
+            }
+            break;
+        }
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+}
+#endif
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/** @brief @implements Adc_ValidateEnableDisbleGroupList_Activity */
+static inline void Adc_ValidateEnableDisbleGroupList
+(
+    Adc_ValidationResultType * pReturnValue,
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    switch (u8ServiceId)
+    {
+        case ADC_ENABLE_CHANNEL_ID:
+        case ADC_DISABLE_CHANNEL_ID:
+        {
+            if((Adc_GroupType)ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX == \
+               Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].EnableChDisableChGroupIndex
+              )
+            {
+                Adc_ReportValidationError(pReturnValue, u8ServiceId, (uint8)ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP);
+            }
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+}
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/** @brief @implements Adc_ValidateEnableDisbleIdList_Activity */
+static inline Std_ReturnType Adc_ValidateEnableDisbleIdList
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    Adc_ChannelType Channel,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupDefType * pGroupChIndexPtr;
+    Adc_ChannelIndexType Index = 0U;
+    boolean bChannelFound = FALSE;
+    Std_ReturnType ReturnValue = (Std_ReturnType)E_NOT_OK;
+
+    switch (u8ServiceId)
+    {
+        case ADC_ENABLE_CHANNEL_ID:
+        case ADC_DISABLE_CHANNEL_ID:
+        {
+            pGroupChIndexPtr = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].pAssignment;
+            /* Check if ChannelId is valid: assigned to that group */
+            for (Index = 0U; Index < Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AssignedChannelCount; Index++)
+            {
+                if ((Adc_ChannelType)Channel == (Adc_ChannelType)pGroupChIndexPtr[Index])
+                {
+                    bChannelFound = TRUE;
+                    break;
+                }
+            }
+            if (TRUE == bChannelFound)
+            {
+                ReturnValue = (Std_ReturnType)E_OK;
+            }
+            else
+            {
+                Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_WRONG_ENABLE_CH_DISABLE_CH_ID);
+            }
+            break;
+        }
+
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+    return ReturnValue;
+}
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || \
+     (ADC_HW_TRIGGER_API == STD_ON) || \
+     (ADC_ENABLE_CTUTRIG_NONAUTO_API ==STD_ON) || \
+     (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) \
+    )
+static inline Std_ReturnType Adc_ValidateExtraParams
+(
+    uint8 u8ServiceId,
+    uint32 u32ErrorIdList,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_ValidationResultType ValidationStatus;
+
+    ValidationStatus.bEndValidations = FALSE;
+    ValidationStatus.ValidParams = (Std_ReturnType)E_OK;
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON))
+    if ((0U != (u32ErrorIdList&ADC_E_BUFFER_UNINIT_LIST)) && (FALSE == ValidationStatus.bEndValidations))
+    {
+        Adc_ValidateBufferUninit(&ValidationStatus, u8ServiceId, Group, u32CoreId);
+    }
+#endif
+    if ((0U != (u32ErrorIdList&ADC_E_WRONG_TRIGG_SRC_LIST)) && (FALSE == ValidationStatus.bEndValidations))
+    {
+       Adc_ValidateTriggerSrc(&ValidationStatus, u8ServiceId, Group, u32CoreId);
+    }
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+    if ((0U != (u32ErrorIdList&ADC_E_QUEUE_FULL_LIST)) && (FALSE == ValidationStatus.bEndValidations))
+    {
+        Adc_ValidateQueueNotFull(&ValidationStatus, u8ServiceId, Group, u32CoreId);
+    }
+#endif
+#if ((ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON) || (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON))
+    if ((0U != (u32ErrorIdList&ADC_E_WRONG_CONV_MODE_LIST)) && (FALSE == ValidationStatus.bEndValidations))
+    {
+        Adc_ValidateConvMode(&ValidationStatus, u8ServiceId, Group, u32CoreId);
+    }
+#endif
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+    if ((0U != (u32ErrorIdList&ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP_LIST)) && (FALSE == ValidationStatus.bEndValidations))
+    {
+        Adc_ValidateEnableDisbleGroupList(&ValidationStatus, u8ServiceId, Group, u32CoreId);
+    }
+#endif /* ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON */
+
+    return ValidationStatus.ValidParams;
+}
+#endif
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+/** @brief @implements Adc_ValidateCallAndTrigger_Activity */
+static inline Std_ReturnType Adc_ValidateCallAndTrigger
+(
+    uint8 u8ServiceId,
+    uint8 u8Trigger,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ReturnValue = (Std_ReturnType)E_OK;
+    Std_ReturnType ValidCoreId = (Std_ReturnType)E_NOT_OK;
+
+    if (NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+        ReturnValue = (Std_ReturnType)E_NOT_OK;
+        (void)ValidCoreId;
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_OK == ValidCoreId)
+        {
+            if ((uint8)ADC_IPW_MAX_CTU_TRIG_SOURCE_ID < u8Trigger)
+            {
+                Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_WRONG_CTU_TRIGGER);
+                ReturnValue = (Std_ReturnType)E_NOT_OK;
+            }
+            else
+            {
+                /* no-op*/
+            }
+        }
+        else
+        {
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+            ReturnValue = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    return ReturnValue;
+}
+#endif /* ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON */
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+/**
+* @brief      This function validates the Adc_SetHwUnitPowerMode call.
+* @details    This function validates the Adc_SetHwUnitPowerMode call.
+*
+* @param[in]  u8ServiceId   The service id of the caller function
+* @param[in]  u32CoreId     Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The Adc_SetHwUnitPowerMode call is valid
+* @retval     E_NOT_OK:       The Adc_SetHwUnitPowerMode call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateSetHwUnitPowerMode
+(
+    Adc_SetPowerModeType eSetHwUnitPowerMode,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType SleepModeStatus = (Std_ReturnType)E_OK;
+    Std_ReturnType ValidCoreId;
+
+    if(NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        /* Report error to DET */
+        Adc_ReportDetError((uint8)ADC_SET_HW_UNIT_POWER_MODE_ID, (uint8)ADC_E_UNINIT);
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+        SleepModeStatus = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_OK == ValidCoreId)
+        {
+            if ((ADC_NORMAL_MODE != eSetHwUnitPowerMode) && (ADC_POWER_DOWN_MODE != eSetHwUnitPowerMode))
+            {
+                SleepModeStatus = (Std_ReturnType)E_NOT_OK;
+                #if (ADC_DEV_ERROR_DETECT == STD_ON)
+                Adc_ReportDetError((uint8)ADC_SET_HW_UNIT_POWER_MODE_ID, (uint8)ADC_E_SET_HW_UNIT_POWER_MODE);
+                #endif
+            }
+        }
+        else
+        {
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError((uint8)ADC_SET_HW_UNIT_POWER_MODE_ID, (uint8)ADC_E_PARAM_CONFIG);
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+            SleepModeStatus = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    return SleepModeStatus;
+}
+#endif /* ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON */
+
+
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+/**
+* @brief        This function ends the validation of the global call parameters.
+* @details      This service is a non reentrant function used for end the validation the calls
+*               for functions like Adc_Init, Adc_DeInit.
+*
+* @param[in]    ValidCall validity of the call
+* @param[in]    u8ServiceId The service id of the caller function
+* @param[in]    u32CoreId    Current CoreID
+*
+* @return void
+*/
+static inline void Adc_EndValidateGloballCall
+(
+    Std_ReturnType ValidCall,
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+)
+{
+    if ((Std_ReturnType)E_OK == ValidCall)
+    {
+        if (ADC_DEINIT_ID == u8ServiceId)
+        {
+            Adc_eGlobalState[u32CoreId] = ADC_STATE_UNINIT;
+        }
+        else
+        {
+            Adc_eGlobalState[u32CoreId] = ADC_STATE_IDLE;
+        }
+    }
+}
+#endif /* ADC_VALIDATE_GLOBAL_CALL == STD_ON */
+
+#if ((ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) && ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON)))
+/**
+* @brief        This function validates the state of a group when priorities are used.
+* @details      This service is a non reentrant function used for validating the state of a group
+*                when priorities are used
+*
+* @param[in]    Group         The group id
+* @param[in]    bImplicitly    Indicates if the group can be implicitly stopped
+* @param[in]    u32CoreId    Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateNotBusyWithPrio
+(
+    Adc_GroupType Group,
+    boolean bImplicitly,
+    uint32 u32CoreId
+)
+{
+    boolean bFlag = FALSE;
+    Adc_QueueIndexType Index = 0U;
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Adc_HwUnitType LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+    Adc_QueueIndexType SwNormalQueueIndex;
+    Adc_StatusType eConversion;
+
+    if (Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+    {
+        for (Index = 0U; Index < Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex; Index++)
+        {
+            if (Group == Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[Index])
+            {
+                bFlag = TRUE;
+                break;
+            }
+        }
+    }
+    SwNormalQueueIndex = Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex;
+    eConversion = Adc_aGroupStatus[Group].eConversion;
+    /* SWS_Adc_00348 */
+    if ((((Group == Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[0U]) && (SwNormalQueueIndex > (Adc_QueueIndexType)0U)) || (TRUE == bFlag)) && \
+        (FALSE == bImplicitly) \
+       )
+    {
+        Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_BUSY);
+    }
+    /* SWS_Adc_00427 */
+    else if (((eConversion != ADC_IDLE) && (eConversion != ADC_STREAM_COMPLETED)) && \
+             (TRUE == bImplicitly) \
+            )
+    {
+        Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_BUSY);
+    }
+    else
+    {
+        ValidState = (Std_ReturnType)E_OK;
+    }
+    return ValidState;
+}
+#endif /*(ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) && ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON)) */
+
+#if (((ADC_HW_TRIGGER_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+      || ((ADC_DEINIT_API == STD_ON))        \
+      ||  (ADC_CALIBRATION == STD_ON) || (ADC_DUAL_CLOCK_MODE == STD_ON) \
+      || (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) || (ADC_POWER_STATE_SUPPORTED == STD_ON) \
+      || ((ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) && (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+      || (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || (ADC_POWER_STATE_SUPPORTED == STD_ON) \
+      || (ADC_ENABLE_TEMPSENSE_API == STD_ON) || ((ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) && (ADC_ENABLE_QUEUING == STD_OFF)) \
+    )
+/**
+* @brief        This function validates the state of a group when the queue is not used.
+* @details      This service is a non reentrant function used for validating the state of a group
+*                when the queue is not used
+*
+* @param[in]    Unit          The Logical Unit Id
+* @param[in]    Group         The group id
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call means that unit is not busy
+* @retval     E_NOT_OK:       The call means that unit is busy
+*/
+static inline Std_ReturnType Adc_ValidateNotBusyNoQueue
+(
+    Adc_HwUnitType Unit,
+    uint8 u8ServiceId
+)
+{
+    Std_ReturnType ErrorFound = (Std_ReturnType)E_OK;
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    Adc_GroupType OngoingHwGroupId;
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+    Adc_GroupType NoGroupsInSwNormalQueue;
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    Adc_GroupType NoGroupsInSwInjectedQueue;
+
+    NoGroupsInSwInjectedQueue = Adc_aUnitStatus[Unit].SwInjectedQueueIndex;
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+    /* Get HW and SW queue sizes */
+    NoGroupsInSwNormalQueue = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    OngoingHwGroupId = Adc_aUnitStatus[Unit].OngoingHwGroup;
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+    /* CPR_RTD_00035.adc, CPR_RTD_00325.adc, CPR_RTD_00326.adc, CPR_RTD_00327.adc */
+    /* Check for ongoing conversions */
+    if ((NoGroupsInSwNormalQueue > (Adc_QueueIndexType)0U)
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+        || (NoGroupsInSwInjectedQueue > (Adc_QueueIndexType)0U)
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        || (OngoingHwGroupId != ADC_INVALID_HW_GROUP_ID)
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+       )
+    {
+        /* SWS_Adc_00321, SWS_Adc_00346, SWS_Adc_00426 */
+        Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_BUSY);
+        ErrorFound = (Std_ReturnType)E_NOT_OK;
+    }
+    return ErrorFound;
+}
+#endif
+
+#if ((ADC_HW_TRIGGER_API == STD_ON) || (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON))
+/**
+* @brief        This function validates the state of a group when the hardware trigger is enabled.
+* @details      This service is a non reentrant function used for validating the state of a group
+*                when the hardware trigger is enabled.
+*
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId     Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateNotBusyEnableHwTrig
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+    Adc_HwUnitType LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType NoGroupsInSwNormalQueue;
+    Adc_GroupConvType eGroupType;
+    Adc_GroupType OngoingHwGroupId;
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    Adc_QueueIndexType NoGroupsInSwInjectedQueue;
+
+    NoGroupsInSwInjectedQueue = Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex;
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+    /* Get HW and SW queue sizes */
+    NoGroupsInSwNormalQueue = Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex;
+    eGroupType = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType;
+    OngoingHwGroupId = Adc_aUnitStatus[LogicalHwUnitId].OngoingHwGroup;
+#endif /* ADC_ENABLE_QUEUING == STD_ON  */
+
+#if (ADC_ENABLE_QUEUING == STD_OFF)
+    ValidState = Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, u8ServiceId);
+#else
+    switch (u8ServiceId)
+    {
+        case ADC_ENABLEHARDWARETRIGGER_ID:
+        {
+            /* It's possible to run (normal HW - injected SW) or (injected HW - normal SW) combination */
+            if ((ADC_INVALID_HW_GROUP_ID == OngoingHwGroupId) &&
+                (
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+                    ((ADC_CONV_TYPE_INJECTED == eGroupType) && (0U == NoGroupsInSwInjectedQueue)) ||
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+                    ((ADC_CONV_TYPE_NORMAL == eGroupType) && (0U == NoGroupsInSwNormalQueue)) \
+                ) \
+            )
+            {
+                ValidState = (Std_ReturnType)E_OK;
+            }
+            break;
+        }
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+        case ADC_ENABLECTUTRIGGER_ID:
+        {
+            /* CTU trigger is injected conversion so can be run with normal SW groups */
+            /* It allows to have multiple BCTU trigger source enabled for one group */
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+            if (0U == NoGroupsInSwInjectedQueue)
+            {
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+                if (ADC_INVALID_HW_GROUP_ID == OngoingHwGroupId)
+                {
+                    ValidState = (Std_ReturnType)E_OK;
+                }
+                else if ((Group == OngoingHwGroupId) && (ADC_HWTRIGGER_ENABLED != Adc_aGroupStatus[OngoingHwGroupId].eHwTriggering))
+                {
+                    ValidState = (Std_ReturnType)E_OK;
+                }
+                else
+                {
+                    ; /* Empty else branch to avoid MISRA */
+                }
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+            }
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+            break;
+        }
+#endif /* ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON */
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+
+    if ((Std_ReturnType) E_NOT_OK == ValidState)
+    {
+        /* SWS_Adc_00353 */
+        Adc_ReportDetRuntimeError((uint8)u8ServiceId, (uint8)ADC_E_BUSY);
+    }
+#endif /* ADC_ENABLE_QUEUING == STD_OFF  */
+
+    return ValidState;
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON)*/
+
+#if ((ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) && (ADC_ENABLE_START_STOP_GROUP_API == STD_ON))
+/**
+* @brief        This function validates the state of a group when priorities are not used.
+* @details      This service is a non reentrant function used for validating the state of a group
+*                when priorities are not used
+*
+* @param[in]    Unit          The hardware unit
+* @param[in]    Group         The group id
+* @param[in]    bImplicitly   Indicates if the group can be implicitly stopped
+* @param[in]    u32CoreId     Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateNotBusyNoPrio
+(
+    Adc_GroupType Group,
+    boolean bImplicitly,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+#if (ADC_ENABLE_QUEUING == STD_OFF)
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Adc_HwUnitType LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+#else /* ADC_ENABLE_QUEUING == STD_ON */
+    Adc_StatusType eConversion;
+#endif
+
+#if (ADC_ENABLE_QUEUING == STD_OFF)
+    /* All queue need to be empty */
+    ValidState =  Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, ADC_STARTGROUPCONVERSION_ID);
+
+    (void)bImplicitly;
+    (void)Group;
+#else /* ADC_ENABLE_QUEUING == STD_ON */
+    eConversion = Adc_aGroupStatus[Group].eConversion;
+    /* SWS_Adc_00351 */
+    if ((FALSE == bImplicitly) && (ADC_IDLE != eConversion))
+    {
+        Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_BUSY);
+    }
+    /* SWS_Adc_00428 */
+    else if ((TRUE == bImplicitly) && (ADC_IDLE != eConversion) && \
+             (ADC_STREAM_COMPLETED != eConversion) \
+            )
+    {
+        Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_BUSY);
+    }
+    else
+    {
+        ValidState = (Std_ReturnType)E_OK;
+    }
+    (void)u32CoreId;
+#endif /* ADC_ENABLE_QUEUING */
+
+    return ValidState;
+}
+#endif /* (ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE) */
+
+#if (((ADC_DEINIT_API == STD_ON)) \
+      || (ADC_CALIBRATION == STD_ON) || (ADC_DUAL_CLOCK_MODE == STD_ON) || (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) \
+      || (ADC_ENABLE_TEMPSENSE_API == STD_ON) \
+    )
+/**
+* @brief        This function validates the state of all group.
+* @details      This service is a non reentrant function used for validating the state of all group
+*
+* @param[in]    u8ServiceId     The service id of the caller function
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return       Std_ReturnType  Standard return type.
+* @retval       E_OK:           The call means that at least one group is not busy
+* @retval       E_NOT_OK:       The call means that at least one group is busy
+*/
+static inline Std_ReturnType Adc_ValidateCheckGroupNotConversion
+(
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+)
+{
+    Adc_StatusType eConversion;
+    Adc_GroupType GroupIter;
+    Adc_GroupType GroupId;
+    Std_ReturnType ErrorFound = (Std_ReturnType)E_OK;
+
+    for (GroupIter = 0U; GroupIter < (Adc_GroupType)Adc_pCfgPtr[u32CoreId]->GroupCount; GroupIter++)
+    {
+        GroupId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIter].GroupId;
+        eConversion = Adc_aGroupStatus[GroupId].eConversion;
+        /*  Check if ADC is still converting */
+        /* SWS_Adc_00112 */
+        if((ADC_IDLE != eConversion) && (ADC_STREAM_COMPLETED != eConversion))
+        {
+            Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_BUSY);
+            ErrorFound = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    return ErrorFound;
+}
+#endif /* (((ADC_DEINIT_API == STD_ON)) ... */
+
+#if (ADC_DEINIT_API == STD_ON)
+/**
+* @brief        This function validates the state of a group when De-init (should not be busy).
+* @details      This service is a non reentrant function used for validating the state of a group
+*
+* @param[in]    void
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateDeInitNotBusy
+(
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ErrorFound = (Std_ReturnType)E_OK;
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+
+    for(LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+    {
+        if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            ErrorFound = Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, ADC_DEINIT_ID);
+            if ((Std_ReturnType)E_NOT_OK == ErrorFound)
+            {
+                break;
+            }
+        }
+    }
+    if ((Std_ReturnType)E_OK == ErrorFound)
+    {
+        if ((Std_ReturnType)E_OK == Adc_ValidateCheckGroupNotConversion(ADC_DEINIT_ID, u32CoreId))
+        {
+            ValidState = (Std_ReturnType)E_OK;
+        }
+    }
+
+    return ValidState;
+}
+
+#endif /* (ADC_DEINIT_API == STD_ON) */
+/**
+* @brief        This function validates the state of a group when Setup result buffer (should not be busy).
+* @details      This service is a non reentrant function used for validating the state of a group
+*
+* @param[in]    Group         The group id
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateSetupBufferNotBusy
+(
+    Adc_GroupType Group
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+
+    if (ADC_IDLE != Adc_aGroupStatus[Group].eConversion)
+    {
+        /* SWS_Adc_00433 */
+        Adc_ReportDetRuntimeError(ADC_SETUPRESULTBUFFER_ID, (uint8)ADC_E_BUSY);
+    }
+    else
+    {
+        ValidState = (Std_ReturnType)E_OK;
+    }
+    return ValidState;
+}
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/**
+* @brief        This function validates the state of a group when start group conversion (should not be busy).
+* @details      This service is a non reentrant function used for validating the state of a group
+*
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateStateStartGroupConvNotBusy
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex;
+    Std_ReturnType ValidState = (Std_ReturnType)E_OK;
+    boolean bImplicitly = FALSE;
+#if ((STD_ON == ADC_HW_TRIGGER_API) || (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) || \
+    (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON))
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+#endif /* ((STD_ON == ADC_HW_TRIGGER_API) || ... */
+#if (STD_ON == ADC_HW_TRIGGER_API)
+    Adc_GroupConvType eTypeSwGroup;
+    Adc_GroupType OngoingHwGroupId;
+    Adc_GroupType HwGroupId;
+    Adc_GroupConvType eTypeHwGroup;
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+
+    /* Get the mapping index of group in the current partition */
+    GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    if ((ADC_CONV_MODE_ONESHOT == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode) || \
+        ((ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode) && \
+        (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode) && \
+        (ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode)
+        )
+       )
+    {
+        /* The current group can be implicitly stopped */
+        bImplicitly = TRUE;
+    }
+
+#if ((STD_ON == ADC_HW_TRIGGER_API) || (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) || \
+    (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON))
+    /* Get the unit to which the group belongs to */
+    LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+#endif /* ((STD_ON == ADC_HW_TRIGGER_API) || ... */
+
+#if (STD_ON == ADC_HW_TRIGGER_API)
+    OngoingHwGroupId = Adc_aUnitStatus[LogicalHwUnitId].OngoingHwGroup;
+#endif /* (STD_ON==ADC_HW_TRIGGER_API) */
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    /* Check for ongoing injected conversion */
+    if (Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex != (Adc_QueueIndexType)0U)
+    {
+        ValidState = (Std_ReturnType)E_NOT_OK;
+    }
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+#if (STD_ON == ADC_HW_TRIGGER_API)
+    if (ADC_INVALID_HW_GROUP_ID != OngoingHwGroupId)
+    {
+        eTypeSwGroup = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType;
+        HwGroupId = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[OngoingHwGroupId];
+        eTypeHwGroup = Adc_pCfgPtr[u32CoreId]->pGroups[HwGroupId].eType;
+        /* SW Injected conversions should be entertained only if there are no other HW or CTU injected chains enabled, same as Sw normal conversions */
+        if (((ADC_CONV_TYPE_INJECTED == eTypeSwGroup) && (ADC_CONV_TYPE_INJECTED == eTypeHwGroup)) || \
+            ((ADC_CONV_TYPE_NORMAL == eTypeSwGroup) && (ADC_CONV_TYPE_NORMAL == eTypeHwGroup)) \
+           )
+        {
+            ValidState = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+#endif /* (STD_ON==ADC_HW_TRIGGER_API) */
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+    if (TRUE == Adc_aUnitStatus[LogicalHwUnitId].bCtuControlOngoing)
+    {
+        ValidState = (Std_ReturnType)E_NOT_OK;
+    }
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+    if ((Std_ReturnType)E_NOT_OK == ValidState)
+    {
+        Adc_ReportDetRuntimeError(ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_BUSY);
+    }
+    else
+    {
+#if (ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE)
+        ValidState = Adc_ValidateNotBusyNoPrio(Group, bImplicitly, u32CoreId);
+#else /* ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE */
+        ValidState = Adc_ValidateNotBusyWithPrio(Group, bImplicitly, u32CoreId);
+#endif  /* ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE */
+    }
+    return ValidState;
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if ((ADC_HW_TRIGGER_API == STD_ON))
+/**
+* @brief        This function validates the state of a group when enable hw trigger (should not be busy).
+* @details      This service is a non reentrant function used for validating the state of a group
+*
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateStateEnableHwTriggNotBusy
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_NOT_OK;
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+    LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+    /* SWS_Adc_00349 */
+    if (TRUE == Adc_aUnitStatus[LogicalHwUnitId].bCtuControlOngoing)
+    {
+        Adc_ReportDetRuntimeError(ADC_ENABLEHARDWARETRIGGER_ID, (uint8)ADC_E_BUSY);
+    }
+    else
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    {
+        ValidState = Adc_ValidateNotBusyEnableHwTrig(ADC_ENABLEHARDWARETRIGGER_ID, Group, u32CoreId);
+    }
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+    return ValidState;
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+
+/**
+* @brief        This function validates the state of a group (should not be idle).
+* @details      This service is a non reentrant function used for validating the state of a group
+*
+* @param[in]    u8ServiceId     The service id of the caller function
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           The call is valid
+* @retval     E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateStateNotIdle
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_OK;
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_QueueIndexType SwNormalQueueIndex;
+    Adc_QueueIndexType SwInjectedQueueIndex;
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+    SwNormalQueueIndex = Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex;
+    SwInjectedQueueIndex = Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex;
+#else
+    (void)u32CoreId;
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+
+    switch (u8ServiceId)
+    {
+#if (ADC_READ_GROUP_API == STD_ON)
+        case ADC_VALUEREADGROUP_ID:
+        {
+            if (ADC_IDLE == Adc_aGroupStatus[Group].eConversion)
+            {
+                if(ADC_NOT_YET_CONVERTED == Adc_aGroupStatus[Group].eAlreadyConverted)
+                {
+                    /* SWS_Adc_00388 */
+                    Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_IDLE);
+                    ValidState = (Std_ReturnType)E_NOT_OK;
+                }
+            }
+            break;
+        }
+#endif /* ADC_READ_GROUP_API == STD_ON */
+        case ADC_STOPGROUPCONVERSION_ID:
+        {
+            if (ADC_IDLE == Adc_aGroupStatus[Group].eConversion)
+            {
+                /* SWS_Adc_00241 */
+                Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_IDLE);
+                ValidState = (Std_ReturnType)E_NOT_OK;
+            }
+            else
+            {
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+                /* This condition happens when injected SW is available */
+                if ((Group == Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[0U])
+                    && (SwNormalQueueIndex > 0U)
+                    && (SwInjectedQueueIndex > 0U)
+                   )
+                {
+                    Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_BUSY);
+                    ValidState = (Std_ReturnType)E_NOT_OK;
+                }
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+            }
+            break;
+        }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        case ADC_DISABLEHARDWARETRIGGER_ID:
+        {
+            /* SWS_Adc_00304 */
+            /* HW trigger streaming linear group will be removed in OngoingHwGroup when all conversion samples finished,
+            so eHwTriggering remains the status of the group was previously enabled by Adc_EnableHardwareTrigger. */
+            if (ADC_HWTRIGGER_DISABLED == Adc_aGroupStatus[Group].eHwTriggering)
+            {
+                Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_IDLE);
+                ValidState = (Std_ReturnType)E_NOT_OK;
+            }
+            break;
+        }
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+        case ADC_GETSTREAMLASTPOINTER_ID:
+        {
+             if (ADC_IDLE == Adc_aGroupStatus[Group].eConversion)
+             {
+                 /* SWS_Adc_00215 */
+                 Adc_ReportDetRuntimeError(u8ServiceId, (uint8)ADC_E_IDLE);
+                 ValidState = (Std_ReturnType)E_NOT_OK;
+             }
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+
+    return ValidState;
+}
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+/**
+* @brief        This function validates the call for a specific group
+* @details      This function checks for Uninit, valid CoreID, and that Group is in range.
+*
+* @param[in]    u8ServiceId     The service id of the caller function
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid call and group
+* @retval     E_NOT_OK:       Invalid call or group
+*
+* @api
+* @implements     Adc_ValidateCallAndGroup_Activity
+*/
+static inline Std_ReturnType Adc_ValidateCallAndGroup
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidCallAndGroup = (Std_ReturnType)E_NOT_OK;
+    Std_ReturnType ValidCoreId = (Std_ReturnType)E_NOT_OK;
+    Adc_GroupType GroupIndex = 0U;
+
+    if (NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        /* SWS_Adc_00300, SWS_Adc_00301, SWS_Adc_00302, SWS_Adc_00299, SWS_Adc_00298, SWS_Adc_00297, SWS_Adc_00296, SWS_Adc_00295, SWS_Adc_00294, SWS_Adc_00434 */
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+        (void)GroupIndex;
+        (void)ValidCoreId;
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_OK == ValidCoreId)
+        {
+            if (Group >= ADC_MAX_GROUPS)
+            {
+                /* SWS_Adc_00218, SWS_Adc_00225, SWS_Adc_00131, SWS_Adc_00130, SWS_Adc_00129, SWS_Adc_00128, SWS_Adc_00152, SWS_Adc_00126, SWS_Adc_00125, SWS_Adc_00423 */
+                Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_GROUP);
+                (void)GroupIndex;
+            }
+            else
+            {
+                /* Get the mapping index of group in the current partition */
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                if (Group != Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].GroupId)
+                {
+                    /* Group doesn't belong to current core */
+                    Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+                }
+                else
+                {
+                    ValidCallAndGroup = (Std_ReturnType)E_OK;
+                }
+            }
+        }
+        else
+        {
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+        }
+    }
+
+    return ValidCallAndGroup;
+}
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+#if (((ADC_ENABLE_READ_RAW_DATA_API == STD_ON) || (ADC_CALIBRATION == STD_ON) \
+   || (ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON) || defined(__DOXYGEN__) \
+   || (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON) || (ADC_SELF_TEST == STD_ON) \
+   || (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || defined(ADC_WDG_SUPPORTED) \
+   || (ADC_ENABLE_TEMPSENSE_API == STD_ON)) && (ADC_VALIDATE_CALL_AND_UNIT == STD_ON))
+/**
+* @brief        This function validates the call for a specific unit
+* @details      This service is non reentrant function on channel used for validating the calls
+*               for functions that use a unit
+*
+* @param[in]    u8ServiceId   The service id of the caller function
+* @param[in]    Unit          The Logical Unit id
+* @param[in]    u32CoreId     Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid call and group
+* @retval     E_NOT_OK:       Invalid call or group
+*
+* @api
+* @implements     Adc_ValidateCallAndUnit_Activity
+*/
+static inline Std_ReturnType Adc_ValidateCallAndUnit
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ValidCallAndUnit = (Std_ReturnType)E_NOT_OK;
+    Std_ReturnType ValidCoreId;
+
+    if (NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        /* CPR_RTD_00272.adc, CPR_RTD_00273.adc */
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+    }
+    else if (Unit >= ADC_MAX_HW_UNITS_CFG)
+    {
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_UNIT);
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_OK == ValidCoreId)
+        {
+            if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[Unit] == (uint8)STD_ON) /* HW unit enabled on current partition */
+            {
+                ValidCallAndUnit = (Std_ReturnType)E_OK;
+            }
+            else
+            {
+                Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+            }
+        }
+        else
+        {
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+        }
+    }
+
+    return ValidCallAndUnit;
+}
+#endif /* (ADC_VALIDATE_CALL_AND_UNIT == STD_ON) ... */
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+/**
+* @brief        This function checks the notification capability of a group.
+* @details      This service is non reentrant function on channel used for validating the
+*               notification capability of a group.
+*
+* @param[in]    u8ServiceId     The service id of the caller function
+* @param[in]    Group         The group id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return     Std_ReturnType  Standard return type.
+* @retval     E_OK:           Valid notification capability
+* @retval     E_NOT_OK:       Invalid notification capability
+*/
+static inline Std_ReturnType Adc_NotifyCapablity
+(
+    uint8 u8ServiceId,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Std_ReturnType ValidCapability = (Std_ReturnType)E_OK;
+
+    switch (u8ServiceId)
+    {
+        case ADC_ENABLEGROUPNOTIFICATION_ID:
+        case ADC_DISABLEGROUPNOTIFICATION_ID:
+        {
+            if (NULL_PTR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].Notification)
+            {
+                ValidCapability = (Std_ReturnType)E_NOT_OK;
+                /* SWS_Adc_00166, SWS_Adc_00165 */
+                Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_NOTIF_CAPABILITY);
+            }
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+    return ValidCapability;
+}
+#endif /* ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON */
+#endif /* ADC_GRP_NOTIF_CAPABILITY == STD_ON */
+
+/**
+* @brief          Initializes the group status structures.
+* @details        Initializes the group status structures with the default values.
+*
+* @param[in]      u32CoreId       Current CoreID
+*
+* @return         void
+*
+* @pre            Driver must be initialized.
+*/
+static inline void Adc_InitGroupsStatus
+(
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType u16GroupCnt = 0U;
+    Adc_GroupType GroupId = 0U;
+
+    /* Initialize Group Status structures to beginning values */
+    for (u16GroupCnt = 0U; u16GroupCnt < Adc_pCfgPtr[u32CoreId]->GroupCount; u16GroupCnt++)
+    {
+        GroupId = Adc_pCfgPtr[u32CoreId]->pGroups[u16GroupCnt].GroupId;
+        /* SWS_Adc_00221, SWS_Adc_00307 */
+        Adc_aGroupStatus[GroupId].eConversion = ADC_IDLE;
+        /* this group was not converted yet */
+        Adc_aGroupStatus[GroupId].eAlreadyConverted = ADC_NOT_YET_CONVERTED;
+
+        Adc_aGroupStatus[GroupId].ResultIndex = 0U;
+#ifdef ADC_CURRENT_CHANNEL_USED
+        Adc_aGroupStatus[GroupId].CurrentChannel = 0U;
+#endif /* ADC_CURRENT_CHANNEL_USED */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        Adc_aGroupStatus[GroupId].bLimitCheckFailed = FALSE;
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+
+        /* SWS_Adc_00077 */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        Adc_aGroupStatus[GroupId].eHwTriggering = ADC_HWTRIGGER_DISABLED;
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+        Adc_aGroupStatus[GroupId].eNotification = ADC_NOTIFICATION_DISABLED;
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+        Adc_aRuntimeGroupChannel[GroupId].pChannel = Adc_pCfgPtr[u32CoreId]->pGroups[u16GroupCnt].pAssignment;
+        Adc_aRuntimeGroupChannel[GroupId].ChannelCount = Adc_pCfgPtr[u32CoreId]->pGroups[u16GroupCnt].AssignedChannelCount;
+        Adc_aRuntimeGroupChannel[GroupId].bRuntimeUpdated = FALSE;
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        Adc_aRuntimeGroupChannel[GroupId].bAdcRuntimeGroupLimitcheck = FALSE;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#if (ADC_PDB_AVAILABLE == STD_ON)
+        Adc_aRuntimeGroupChannel[GroupId].pu16Delays = Adc_pCfgPtr[u32CoreId]->pGroups[u16GroupCnt].pAdcIpwGroupConfig->pDelay;
+        Adc_aRuntimeGroupChannel[GroupId].u32Mask = 0xFFFFFFFFUL;
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    }
+}
+
+/**
+* @brief          Initializes the Unit status structures.
+* @details        Initializes the Unit status structures with the default values.
+*
+* @param[in]      u32CoreId       Current CoreID
+*
+* @return         void
+*
+* @pre            Driver must be initialized.
+*/
+static inline void Adc_InitUnitStatus
+(
+    uint32 u32CoreId
+)
+{
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_QueueIndexType QueueIdx = 0U;
+
+    /* Loop for all configured hardware units in current partition */
+    for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+    {
+        if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            /* Filled slots in the queue */
+            Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex = 0U;
+            /* Mark all the queue slots as "empty" */
+            for(QueueIdx = 0U; QueueIdx < ADC_QUEUE_MAX_DEPTH_MAX; QueueIdx++)
+            {
+                Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[QueueIdx] = 0U;
+            }
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+            /* SW Injected queue initialization */
+            Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueue[0U] = 0U;
+            /* Filled slots in the sw injected queue */
+            Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex = 0U;
+#endif /* (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON) */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+            /* SWS_Adc_00077 */
+            /* If there is no ongoing HW group then HW trigger capability is disabled */
+            Adc_aUnitStatus[LogicalHwUnitId].OngoingHwGroup = ADC_INVALID_HW_GROUP_ID;
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+#if (ADC_PDB_AVAILABLE == STD_ON)
+            Adc_aUnitStatus[LogicalHwUnitId].u8Sc1Used = 0U;
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+        }
+    }
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+    Adc_eCurrentState[u32CoreId] = ADC_FULL_POWER;
+    Adc_eTargetState[u32CoreId] = ADC_NODEFINE_POWER;
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    Adc_eClockMode[u32CoreId] = ADC_NORMAL;
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+}
+
+/**
+* @brief        This function check CoreId is used.
+* @details      This function check CoreId is used.
+*
+* @param[in]      pCfgPtr           Configuration data pointer.
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return       Std_ReturnType  Standard return type.
+* @retval       E_OK:           CoreId is valid
+* @retval       E_NOT_OK:       CoreId is not valid
+*/
+static inline Std_ReturnType Adc_CheckCurrentCoreId
+(
+    const Adc_ConfigType * pCfgPtr,
+    uint32 u32CoreId
+)
+{
+    uint8 Index = 0U;
+    Std_ReturnType ValidCoreId = (Std_ReturnType)E_NOT_OK;
+
+    if(u32CoreId == pCfgPtr->u32CoreId)
+    {
+        for(Index = 0U; Index < pCfgPtr->AssignedPartitionCount; Index++)
+        {
+            if(u32CoreId == pCfgPtr->pAssignmentPartition[Index])
+            {
+                ValidCoreId = (Std_ReturnType)E_OK;
+                break;
+            }
+        }
+    }
+
+    return ValidCoreId;
+}
+
+#if (ADC_ENABLE_QUEUING == STD_ON)
+/**
+* @brief          This function performs the dequeue operation on the internal ADC queue.
+* @details        This function performs the dequeue operation on the internal ADC queue.
+*
+* @param[in]      Unit            Adc unit used. Recommended to use generated define for Adc Logical Unit Id.
+* @param[in]      CurQueueIndex   The current queue index.
+*
+* @return         void
+*
+* @pre This function must be called from a critical region. It is not protecting itself against interruptions.
+*/
+void Adc_RemoveFromQueue
+(
+    const Adc_HwUnitType Unit,
+    const Adc_QueueIndexType CurQueueIndex
+)
+{
+    Adc_QueueIndexType PositionIndex = 0U;
+    Adc_QueueIndexType CurrentIndex = 0U;
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00();
+    CurrentIndex = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+    if((Adc_QueueIndexType)1U >= CurrentIndex)
+    {
+        /* Zero or one element present in the queue */
+        Adc_aUnitStatus[Unit].SwNormalQueueIndex = 0U;
+    }
+    else
+    {
+        /* More than one element in the queue */
+        /* Move all elements after the one to remove (from CurQueueIndex position) one place to the left */
+        for(PositionIndex = (CurQueueIndex + 1U); PositionIndex < CurrentIndex; PositionIndex++)
+        {
+            Adc_aUnitStatus[Unit].SwNormalQueue[PositionIndex - 1U] = (Adc_GroupType)Adc_aUnitStatus[Unit].SwNormalQueue[PositionIndex];
+        }
+        Adc_aUnitStatus[Unit].SwNormalQueueIndex--;
+    }
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00();
+}
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+
+#if ((ADC_ENABLE_START_STOP_GROUP_API == STD_ON) && (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE))
+/**
+* @brief          This function inserts a group into the queue.
+* @details        This function inserts a group into the queue.
+*
+* @param[in]      Unit      The hardware Unit.
+* @param[in]      Group     The group id.
+* @param[in]      u32CoreId       Current CoreID
+*
+* @return         void
+* SWS_Adc_00311, SWS_Adc_00310
+*/
+static inline Std_ReturnType Adc_InsertIntoQueue
+(
+    const Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#if (ADC_QUEUE_MAX_DEPTH_MAX != 1U)
+    /* Temporary index in the Queue */
+    Adc_QueueIndexType QueueTemp = 0U;
+#endif /* (ADC_QUEUE_MAX_DEPTH_MAX != 1U) */
+    /* Position of the new Group in the Queue */
+    Adc_QueueIndexType Pos = 0U;
+    Adc_GroupPriorityType gPri = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].Priority;
+    Adc_QueueIndexType qPtr = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+    Std_ReturnType TimeOutStatus = (Std_ReturnType)E_OK;
+
+    /* Find the right place in Queue (SWS_Adc_00332, SWS_Adc_00417) */
+    while(Adc_pCfgPtr[u32CoreId]->pGroups[(Adc_aUnitStatus[Unit].SwNormalQueue[Pos])].Priority >= gPri)
+    {
+        Pos++;
+        if (Pos >= qPtr)
+        {
+            break;
+        }
+    }
+    if(0U == Pos)
+    {
+        /* Highest priority group detected */
+        TimeOutStatus = Adc_Ipw_StopCurrentConversion(Unit, Adc_aUnitStatus[Unit].SwNormalQueue[0U], u32CoreId);
+    }
+#if (ADC_QUEUE_MAX_DEPTH_MAX != 1U)
+    /* Make space for the new Group */
+    if(qPtr > Pos)
+    {
+        for(QueueTemp = qPtr; QueueTemp > Pos; QueueTemp--)
+        {
+            /* Move elements to the right */
+            Adc_aUnitStatus[Unit].SwNormalQueue[QueueTemp] = (Adc_GroupType)Adc_aUnitStatus[Unit].SwNormalQueue[QueueTemp- 1U];
+        }
+    }
+#endif /* (ADC_QUEUE_MAX_DEPTH_MAX != 1U) */
+    /* Place the Group in the Queue */
+    Adc_aUnitStatus[Unit].SwNormalQueue[Pos] = Group;
+    /* Increase the Queue Index */
+    Adc_aUnitStatus[Unit].SwNormalQueueIndex++;
+
+    return TimeOutStatus;
+}
+#endif  /* (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) */
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/**
+* @brief          This function update queue before start a group conversion.
+* @details        This function update queue before start a group conversion.
+*
+* @param[in]      Group         The Group Id.
+* @param[in]      Unit          The Logical Unit Id.
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*
+* SWS_Adc_00335
+*/
+static inline void Adc_UpdateStatusStartConversion
+(
+    const Adc_GroupType Group,
+    const Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#endif /* ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON */
+    /* First available slot in the Queue */
+#if ((ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE) || ((ADC_ENABLE_QUEUING == STD_ON) && (ADC_QUEUE_MAX_DEPTH_MAX != 1U)))
+    Adc_QueueIndexType qPtr = 0U;
+#endif
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType SwNormalQueueIndex;
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    Std_ReturnType TimeOutStatus = (Std_ReturnType)E_OK;
+
+    /* Mark the Group as BUSY when the Group goes to the Queue or gets started */
+    /* SWS_Adc_00222 */
+    Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+    /* SWS_Adc_00431 */
+    Adc_aGroupStatus[Group].ResultIndex = 0U;
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    /* Injected conversion mode */
+    if (ADC_CONV_TYPE_INJECTED == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType)
+    {
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01();
+#ifdef ADC_DMA_SUPPORTED
+        if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit]) || \
+            ((uint8)STD_ON == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcExtDMAChanEnable) \
+           )
+        {
+            if (Adc_aUnitStatus[Unit].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+            {
+                /* Queue is NOT Empty */
+                TimeOutStatus = Adc_Ipw_StopCurrentConversion(Unit, Adc_aUnitStatus[Unit].SwNormalQueue[0U], u32CoreId);
+
+                if ((Std_ReturnType)E_NOT_OK == TimeOutStatus)
+                {
+                    /* Timeout is expired.*/
+                    Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_TIMEOUT);
+                }
+            }
+        }
+#endif /* ADC_DMA_SUPPORTED */
+        /* Place the Group in the SW Inj Queue */
+        Adc_aUnitStatus[Unit].SwInjectedQueue[0U] = Group;
+        /* Increase the Queue Index */
+        Adc_aUnitStatus[Unit].SwInjectedQueueIndex++;
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();
+
+        Adc_Ipw_StartInjectedConversion(Unit, u32CoreId);
+
+    }
+    else
+#endif /* ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON */
+    {
+        /* Normal conversion */
+#if (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE)
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01();
+        qPtr = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+        if (qPtr > (Adc_QueueIndexType)0U)
+        {
+            /* Queue is NOT Empty */
+            TimeOutStatus = Adc_InsertIntoQueue(Unit, Group, u32CoreId);
+
+            if ((Std_ReturnType)E_NOT_OK == TimeOutStatus)
+            {
+                /* Timeout is expired.*/
+                Adc_ReportDetRuntimeError((uint8)ADC_STARTGROUPCONVERSION_ID, (uint8)ADC_E_TIMEOUT);
+            }
+        }
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();
+#else /* ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE */
+#if (ADC_ENABLE_QUEUING == STD_ON) && (ADC_QUEUE_MAX_DEPTH_MAX != 1U)
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01();
+        qPtr = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+        if (qPtr > (Adc_QueueIndexType)0U)
+        {
+            /* Place the Group in the Queue */
+            Adc_aUnitStatus[Unit].SwNormalQueue[qPtr] = Group;
+            /* Increase the Queue Index */
+            Adc_aUnitStatus[Unit].SwNormalQueueIndex++;
+        }
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();
+#else /* ADC_ENABLE_QUEUING == STD_OFF*/
+    /* In this case all the StartConversion should be rejected by DET */
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+#endif /* ADC_PRIORITY_IMPLEMENTATION == ADC_PRIORITY_NONE */
+
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01();
+#if (ADC_ENABLE_QUEUING == STD_ON)
+        SwNormalQueueIndex = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+        /* SWS_Adc_00338, SWS_Adc_00417 */
+        if((Adc_aUnitStatus[Unit].SwNormalQueue[0U] == Group) || (0U == SwNormalQueueIndex))
+        {
+            /* No_priorities OR Queue_is_empty */
+            /* Indicate a new group was added to the queue */
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+            if (0U == Adc_aUnitStatus[Unit].SwNormalQueueIndex)
+            {
+                /* Place the Group in the Queue */
+                Adc_aUnitStatus[Unit].SwNormalQueue[0U] = Group;
+                Adc_aUnitStatus[Unit].SwNormalQueueIndex++;
+            }
+            /* exit critical region */
+            SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();
+            /* ADC will not be running - no ISR can occur now */
+            Adc_Ipw_StartNormalConversion(Unit, u32CoreId);
+
+#if (ADC_ENABLE_QUEUING == STD_ON)
+        }
+        else
+        {
+        /* exit critical region */
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01();
+        }
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    }
+    (void)TimeOutStatus;
+}
+
+/**
+* @brief          This function stop the current sofware group conversion.
+* @details        This function stop the current sofware group conversion.
+*
+* @param[out]     RemovedPos The removed position in queue.
+* @param[in]      Group      The group id.
+* @param[in]      Unit       The hardware Unit.
+* @param[in]      u32CoreId  Current CoreID
+*
+* @return         Std_ReturnType
+*
+*/
+static inline Std_ReturnType Adc_StopSwGroupConversion
+(
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType * RemovedPos,
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType TimeOutStatus = (Std_ReturnType)E_OK;
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType SwNormalQueueIndex;
+    Adc_QueueIndexType NumOfSwNormalQueue;
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    if (ADC_CONV_TYPE_INJECTED == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType)
+    {
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02();
+        if (Group == Adc_aUnitStatus[Unit].SwInjectedQueue[0U])
+        {
+            /* SWS_Adc_00386, SWS_Adc_00385 */
+            TimeOutStatus = Adc_Ipw_StopCurrentConversion(Unit, Group, u32CoreId);
+            /* zero elements in the sw injected queue */
+            Adc_aUnitStatus[Unit].SwInjectedQueueIndex = 0U;
+        }
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02();
+    }
+    else
+#endif /* ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON */
+    {
+#if (ADC_ENABLE_QUEUING == STD_ON)
+        /* SWS_Adc_00437 */
+        /* Find the Group in the Queue */
+        *RemovedPos = Adc_aUnitStatus[Unit].SwNormalQueueIndex;  /* initialize with something invalid */
+        NumOfSwNormalQueue = Adc_aUnitStatus[Unit].SwNormalQueueIndex;
+        for (SwNormalQueueIndex = 0U; SwNormalQueueIndex < NumOfSwNormalQueue; SwNormalQueueIndex++)
+        {
+            if (Group == Adc_aUnitStatus[Unit].SwNormalQueue[SwNormalQueueIndex])
+            {
+                /* The group is found in the Queue */
+                /* Store the position of the group to be removed */
+                *RemovedPos = SwNormalQueueIndex;
+
+                /* Stop the conversion of all channels belonging to this group */
+                if((Adc_QueueIndexType)0U == SwNormalQueueIndex) /* In this case the group might be under conversion */
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+                {
+                    /* SWS_Adc_00386 */
+                    TimeOutStatus = Adc_Ipw_StopCurrentConversion(Unit, Group, u32CoreId);
+                }
+#if (ADC_ENABLE_QUEUING == STD_ON)
+                /* SWS_Adc_00438 */
+                /* Remove group from Queue */
+                Adc_RemoveFromQueue(Unit, SwNormalQueueIndex);
+            }
+        }
+#else
+        /* No element will be present in the queue */
+        Adc_aUnitStatus[Unit].SwNormalQueueIndex = 0U;
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    }
+
+    return TimeOutStatus;
+}
+
+/**
+* @brief          This function update queue before start a group conversion.
+* @details        This function update queue before start a group conversion.
+*
+* @param[in]      Group     The group id.
+* @param[in]      Unit      The hardware Unit.
+* @param[in]      u32CoreId       Current CoreID
+*
+* @return         void
+*
+* SWS_Adc_00437
+*/
+static inline void Adc_UpdateStatusStopConversion
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType RemovedPos = 0U;
+#endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+    Std_ReturnType TimeOutStatus = (Std_ReturnType)E_OK;
+    Adc_GroupConvModeType eMode;
+    Adc_GroupAccessModeType eAccessMode;
+    Adc_StreamBufferModeType eBufferMode;
+    Adc_StatusType eConversion;
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    Adc_aGroupStatus[Group].bLimitCheckFailed = FALSE;
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+
+    eMode = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode;
+    eAccessMode = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode;
+    eBufferMode = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode;
+    eConversion = Adc_aGroupStatus[Group].eConversion;
+
+     /* FD reset number of samples completed */
+     Adc_aGroupStatus[Group].ResultIndex = 0U;
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+     /* disable group notification (SWS_Adc_00155) */
+     Adc_aGroupStatus[Group].eNotification = ADC_NOTIFICATION_DISABLED;
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+#if ((ADC_SETCHANNEL_API == STD_ON) && (ADC_PDB_AVAILABLE == STD_ON))
+     Adc_aRuntimeGroupChannel[Group].u32Mask = 0xFFFFFFFFUL;
+#endif /* ((ADC_SETCHANNEL_API == STD_ON) && (ADC_PDB_AVAILABLE == STD_ON)) */
+    if(((ADC_CONV_MODE_ONESHOT == eMode) || \
+        ((ADC_ACCESS_MODE_STREAMING == eAccessMode) && (ADC_STREAM_BUFFER_LINEAR == eBufferMode)) \
+       ) && (ADC_STREAM_COMPLETED == eConversion) \
+      )
+    {
+        /* SWS_Adc_00221, SWS_Adc_00360 */
+        /* group is stopped, change its status to IDLE  */
+        Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+    }
+    else /* Continuous single or streaming circular */
+    {
+#if (ADC_ENABLE_QUEUING == STD_ON)
+        TimeOutStatus = Adc_StopSwGroupConversion(&RemovedPos, Group, Unit, u32CoreId);
+#else
+        TimeOutStatus = Adc_StopSwGroupConversion(Group, Unit, u32CoreId);
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+
+        /* SWS_Adc_00221, SWS_Adc_00360 */
+        /* group is stopped, change its status to IDLE  */
+        Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+
+    #if (ADC_ENABLE_QUEUING == STD_ON)
+        /* Start the next group in the Queue (if any) */
+        if((Adc_QueueIndexType)0U == RemovedPos)
+        {
+            if(Adc_aUnitStatus[Unit].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+            {
+                /* Structures and pointers will be initialized when the next Group starts */
+                Adc_Ipw_StartNormalConversion(Unit, u32CoreId);
+            }
+        }
+    #endif /* (ADC_ENABLE_QUEUING == STD_ON) */
+        if ((Std_ReturnType)E_NOT_OK == TimeOutStatus)
+        {
+            /* Timeout is expired.*/
+            Adc_ReportDetRuntimeError((uint8)ADC_STOPGROUPCONVERSION_ID, (uint8)ADC_E_TIMEOUT);
+        }
+    }
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if (ADC_READ_GROUP_API == STD_ON)
+/**
+* @brief          This function updates the status variables after the read group operation.
+* @details        This function updates the status variables after the read group operation.
+*
+* @param[in]      Group       The group of which conversion will be started.
+* @param[in]      bFlag       Indicates if the values are in the configured limit range.
+* @param[in]      u32CoreId   Current CoreID
+*
+* @return         void
+*
+*/
+static inline void Adc_UpdateStatusReadGroup
+(
+    const Adc_GroupType Group,
+    const boolean bFlag,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    if((uint8)STD_ON == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcWithoutInterrupt)
+    {
+        Adc_UpdateStatusReadGroupNoInt(Group, bFlag, u32CoreId);
+    }
+    else
+    {
+        Adc_UpdateStatusReadGroupInt(Group, u32CoreId);
+    }
+}
+
+static inline void Adc_UpdateStatusReadGroupNoInt
+(
+    const Adc_GroupType Group,
+    const boolean bFlag,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    /* at least once the group was converted */
+    Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+    /* Update conversion status*/
+    /* Conversion values are not in the configured range */
+    if (TRUE == bFlag)
+    {
+        /* NOTE: Streaming groups are NOT allowed without interrupts in configuration */
+        if(ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode)
+        {
+            Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+        }
+        /* Case of software - one shot mode */
+        else
+        {
+            /* CPR_RTD_00265.adc */
+            if(ADC_TRIGG_SRC_SW == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource)
+            {
+                /* SWS_Adc_00221 */
+                Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+                /* Update queue index status */
+                Adc_UpdateSwQueueIndexNoInt(Group, u32CoreId);
+            }
+        }
+    }
+    #if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    else
+    {
+        if(ADC_CONV_MODE_ONESHOT == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode)
+        {
+            /* SWS_Adc_00449, SWS_Adc_00450 */
+            Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+        }
+    }
+    #endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+}
+
+static inline void Adc_UpdateSwQueueIndexNoInt
+(
+    const Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Adc_HwUnitType LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AdcLogicalUnitId;
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    Adc_QueueIndexType SwNormalQueueIndex;
+    Adc_QueueIndexType NumOfSwNormalQueue;
+#endif
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+    if (ADC_CONV_TYPE_INJECTED == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eType)
+    {
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03();
+        if (Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex > (Adc_QueueIndexType)0U)
+        {
+            /* empty queue of  SW injected conversions */
+            Adc_aUnitStatus[LogicalHwUnitId].SwInjectedQueueIndex--;
+        }
+        SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03();
+    }
+    else /* SW NORMAL CONVERSION */
+#endif /* ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON */
+    {
+        if (Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+        {
+#if (ADC_ENABLE_QUEUING == STD_ON)
+            /* remove group without interrupts from queue  */
+            NumOfSwNormalQueue = Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex;
+            for (SwNormalQueueIndex = 0U; SwNormalQueueIndex < NumOfSwNormalQueue; SwNormalQueueIndex++)
+            {
+                if (Group == Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[SwNormalQueueIndex])
+                {
+                    /* The group is found in the Queue */
+                    Adc_RemoveFromQueue(LogicalHwUnitId, SwNormalQueueIndex);
+                    break;
+                }
+            }
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+            /* Start / restore next conversion in the queue*/
+            if (0U == SwNormalQueueIndex)
+            {
+                if(Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex > 0U)
+                {
+                    Adc_Ipw_StartNormalConversion(LogicalHwUnitId, u32CoreId);
+                }
+            }
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+#else
+            Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex--;
+#endif
+        }
+    }
+}
+
+static inline void Adc_UpdateStatusReadGroupInt
+(
+    const Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    /* The following code has been added to respect the State Diagram of Streaming Access Mode */
+    if (ADC_COMPLETED == Adc_aGroupStatus[Group].eConversion)
+    {
+        /* SWS_Adc_00331 -- SWS_Adc_00222 */
+        Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+    }
+    else if (ADC_STREAM_COMPLETED == Adc_aGroupStatus[Group].eConversion)
+    {
+        /* Compliance with State Diagram */
+        if (ADC_TRIGG_SRC_SW == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource)
+        {
+            if((ADC_CONV_MODE_ONESHOT == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode)|| \
+               ((ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode) && \
+                (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode) && \
+                (ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode) \
+               )
+              )
+            {
+                /* SWS_Adc_00330 - SWS_Adc_00221 */
+                Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+            }
+            else
+            {
+                /* Continuous single access or circular streaming buffer mode */
+                /* SWS_Adc_00329 -- SWS_Adc_00222 */
+                Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+            }
+        }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        else
+        {
+            if((ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode)&& \
+               (ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode)
+              )
+            {
+                /* SWS_Adc_00330 - SWS_Adc_00221 */
+                Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+            }
+            else
+            { /* Simple One-shot mode, in other words in single access mode*/
+                /* SWS_Adc_00329 -- SWS_Adc_00222 */
+                Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+            }
+        }
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+    }
+    else
+    {
+        ; /* Empty else branch to avoid MISRA */
+    }
+}
+
+#endif /* (ADC_READ_GROUP_API == STD_ON) */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+static inline void Adc_UpdateStatusEnableHardware
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit
+)
+{
+    /* Save enabled hardware group ID */
+    Adc_aUnitStatus[Unit].OngoingHwGroup = Group;
+
+    /* Mark the Group as BUSY */
+    /* SWS_Adc_00222 */
+    Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+
+    /* if HW trigger is enabled for a group, its HW trigger status becomes ENABLED */
+    Adc_aGroupStatus[Group].eHwTriggering = ADC_HWTRIGGER_ENABLED;
+
+    /* SWS_Adc_00432 */
+    /* Put the conversion results from Results Buffer Base Address */
+    Adc_aGroupStatus[Group].ResultIndex = 0U;
+}
+
+static inline void Adc_UpdateStatusDisableHardware
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit
+)
+{
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+    /* [SWS_Adc_00157] If enabled, the function Adc_DisableHardwareTrigger shall disable the notification mechanism for the requested group */
+    Adc_aGroupStatus[Group].eNotification = ADC_NOTIFICATION_DISABLED;
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+#if ((ADC_SETCHANNEL_API == STD_ON) && (ADC_PDB_AVAILABLE == STD_ON))
+     Adc_aRuntimeGroupChannel[Group].u32Mask = 0xFFFFFFFFUL;
+#endif /* ((ADC_SETCHANNEL_API == STD_ON) && (ADC_PDB_AVAILABLE == STD_ON)) */
+
+    /* SWS_Adc_00361, SWS_Adc_00221 */
+    /* Mark the Group status as IDLE */
+    Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+
+    /* Hardware trigger is disabled */
+    Adc_aGroupStatus[Group].eHwTriggering = ADC_HWTRIGGER_DISABLED;
+
+    /* Remove hardware group ID */
+    Adc_aUnitStatus[Unit].OngoingHwGroup = ADC_INVALID_HW_GROUP_ID;
+
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+/**
+* @brief          This function updates the status variables after the getstreamlastpointer operation.
+* @details        This function updates the status variables after the getstreamlastpointer operation.
+*
+* @param[in]      Group       The group of which conversion will be started.
+* @param[in]      u32CoreId       Current CoreID
+*
+* @return         void
+*
+*/
+static inline void Adc_UpdateStatusAfterGetStream
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    /* The following code has been added to respect the State Diagram of Streaming Access Mode */
+    if (ADC_COMPLETED == Adc_aGroupStatus[Group].eConversion)
+    {
+        /* SWS_Adc_00328 -- SWS_Adc_00222 */
+        Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+    }
+
+    if (ADC_STREAM_COMPLETED == Adc_aGroupStatus[Group].eConversion)
+    {
+        /* Compliance with State Diagram */
+        if (ADC_TRIGG_SRC_SW == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource)
+        {
+            if((ADC_CONV_MODE_ONESHOT == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode) || \
+               ((ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode) && \
+                (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode) && \
+                (ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode) \
+               )
+              )
+            {
+                /* SWS_Adc_00327 -- SWS_Adc_00221 */
+                Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+            }
+            else
+            {
+                /* Continuous single access or circular streaming buffer mode */
+                /* SWS_Adc_00326 -- SWS_Adc_00222 */
+                Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+            }
+        }
+#if (STD_ON == ADC_HW_TRIGGER_API)
+        else
+        {
+            /* Hw Trigger */
+            if((ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode) && \
+               (ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode)
+              )
+            {
+                /* SWS_Adc_00327 -- SWS_Adc_00221 */
+                Adc_aGroupStatus[Group].eConversion = ADC_IDLE;
+            }
+            else
+            {
+                /* Single access mode or circular streaming buffer mode */
+                /* SWS_Adc_00326 -- SWS_Adc_00222 */
+                Adc_aGroupStatus[Group].eConversion = ADC_BUSY;
+            }
+        }
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+    }
+}
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+
+/**
+* @brief        This function validates the Adc unit is activated for Ctu control mode.
+* @details      This service is a non reentrant function used for validating the Adc unit when
+*               Ctu control mode is used.
+*
+* @param[in]    u8ServiceId     Service id
+* @param[in]    Unit            The unit id
+* @param[in]    u32CoreId       Current CoreID
+*
+* @return       Std_ReturnType  Standard return type.
+* @retval       E_OK:           The call is valid
+* @retval       E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateUnitActive
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType Return = (Std_ReturnType)E_OK;
+
+    if (0u == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcUnitSupportCtuControlMode[Unit])
+    {
+        /* CPR_RTD_00272.adc */
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_UNIT);
+        Return = (Std_ReturnType)E_NOT_OK;
+    }
+
+    return Return;
+}
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+/**
+* @brief        This function validates the state of s unit when the Ctu Control is enabled.
+* @details      This service is a non reentrant function used for validating the state of a unit
+*               when the ctu control is enabled.
+*
+* @param[in]    Unit            The unit id
+*
+* @return       Std_ReturnType  Standard return type.
+* @retval       E_OK:           The call is valid
+* @retval       E_NOT_OK:       The call is not valid
+*/
+static inline Std_ReturnType Adc_ValidateStateCtuControlMode
+(
+    uint8 u8ServiceId,
+    Adc_HwUnitType Unit
+)
+{
+    Std_ReturnType ValidState = (Std_ReturnType)E_OK;
+
+    switch(u8ServiceId)
+    {
+        case ADC_ENABLE_CTU_CONTROL_MODE_ID:
+        {
+            ValidState = Adc_ValidateNotBusyNoQueue(Unit, ADC_ENABLE_CTU_CONTROL_MODE_ID);
+
+            /* Check for ongoing conversions */
+            if (((Std_ReturnType)E_NOT_OK == ValidState) ||
+                (TRUE == Adc_aUnitStatus[Unit].bCtuControlOngoing)
+               )
+            {
+                /* CPR_RTD_00272.adc */
+                ValidState = (Std_ReturnType)E_NOT_OK;
+                Adc_ReportDetRuntimeError((uint8)ADC_ENABLE_CTU_CONTROL_MODE_ID, (uint8)ADC_E_BUSY);
+            }
+            break;
+        }
+        case ADC_DISABLE_CTU_CONTROL_MODE_ID:
+        {
+            /* Ctu control mode is not already enabled for this unit */
+            if(FALSE == Adc_aUnitStatus[Unit].bCtuControlOngoing)
+            {
+                /* CPR_RTD_00273.adc */
+                ValidState = (Std_ReturnType)E_NOT_OK;
+                Adc_ReportDetRuntimeError((uint8)ADC_DISABLE_CTU_CONTROL_MODE_ID, (uint8)ADC_E_IDLE);
+            }
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+    return ValidState;
+}
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_ValidateCtuControlModeApi
+(
+    uint8 u8ServiceId,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType Status = E_OK;
+    uint8 AdcHwUnit = 0u;
+    boolean CtuControlModeEnabled = FALSE;
+
+    if (Adc_pCfgPtr[u32CoreId] == NULL_PTR)
+    {
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+        Status = E_NOT_OK;
+    }
+    else
+    {
+        for (AdcHwUnit = 0u; AdcHwUnit < ADC_MAX_HW_UNITS; AdcHwUnit++)
+        {
+            if (Adc_aUnitStatus[AdcHwUnit].bCtuControlOngoing)
+            {
+                CtuControlModeEnabled = TRUE; /* CtuControl Mode is considered enabled, if it is enabled for at least one AdcHwUnit */
+            }
+        }
+    }
+    if (CtuControlModeEnabled == FALSE)
+    {
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_CONTROL_MODE_DISABLED);
+        Status = E_NOT_OK;
+    }
+
+    return Status;
+}
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+static inline Std_ReturnType Adc_ValidateStateAndPtr
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType RetVal = (Std_ReturnType)E_OK;
+    Std_ReturnType ValidCoreId = (Std_ReturnType)E_NOT_OK;
+
+    if (NULL_PTR == pResult)
+    {
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_POINTER);
+#else
+        (void)u8ServiceId;
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+        RetVal = (Std_ReturnType)E_NOT_OK;
+        (void)ValidCoreId;
+    }
+    else if(NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        /* Adc module is not initialized */
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        /* SWS_Adc_00496, SWS_Adc_00493, SWS_Adc_00491, SWS_Adc_00486 */
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_UNINIT);
+#else
+        (void)u8ServiceId;
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        *pResult = ADC_NOT_INIT;
+        RetVal = (Std_ReturnType)E_NOT_OK;
+        (void)ValidCoreId;
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_NOT_OK == ValidCoreId)
+        {
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_PARAM_CONFIG);
+#else
+            (void)u8ServiceId;
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            *pResult = ADC_NOT_INIT;
+            RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    return RetVal;
+}
+
+static inline Std_ReturnType Adc_ValidateIdleState
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType RetVal = (Std_ReturnType)E_OK;
+    Adc_HwUnitType LogicalHwUnitId;
+
+    for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+    {
+        if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            if (((Std_ReturnType)E_NOT_OK == Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, u8ServiceId))
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+               || (TRUE == Adc_aUnitStatus[LogicalHwUnitId].bCtuControlOngoing)
+#endif /* if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) */
+               )
+            {
+                /* Adc conversion is ongoing */
+                /* SWS_Adc_00487 */
+                Adc_ReportDetRuntimeError(u8ServiceId, ADC_E_NOT_DISENGAGED);
+                *pResult = ADC_SEQUENCE_ERROR;
+                RetVal = (Std_ReturnType)E_NOT_OK;
+                break;
+            }
+        }
+    }
+    return RetVal;
+}
+
+static inline Std_ReturnType Adc_ValidatePowerStateSupport
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateType ePowerState,
+    Adc_PowerStateRequestResultType * pResult
+)
+{
+    Std_ReturnType RetVal = (Std_ReturnType)E_OK;
+
+    /* If the power state is not supported or low power state is not supported at all */
+    if(ePowerState >= ADC_NODEFINE_POWER)
+    {
+        /* The state is not supported */
+        #if (ADC_DEV_ERROR_DETECT == STD_ON)
+        Adc_ReportDetError(u8ServiceId, ADC_E_POWER_STATE_NOT_SUPPORTED);
+        #else
+        (void)u8ServiceId;
+        #endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        *pResult = ADC_POWER_STATE_NOT_SUPP;
+        RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    return RetVal;
+}
+
+static inline Std_ReturnType Adc_ValidatePowerStatePrepare
+(
+    uint8 u8ServiceId,
+    Adc_PowerStateRequestResultType * pResult,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType RetVal = (Std_ReturnType)E_OK;
+
+    /* If the terget state is invalid state */
+    if(Adc_eTargetState[u32CoreId] >= ADC_NODEFINE_POWER)
+    {
+        /* The target power state is not prepared */
+        #if (ADC_DEV_ERROR_DETECT == STD_ON)
+        /* SWS_Adc_00490 */
+        Adc_ReportDetError(u8ServiceId, ADC_E_PERIPHERAL_NOT_PREPARED);
+        #else
+        (void)u8ServiceId;
+        #endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        *pResult = ADC_SEQUENCE_ERROR;
+        RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    return RetVal;
+}
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) || defined(__DOXYGEN__)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_CheckTriggerSourceRange
+(
+    uint8 u8ServiceId,
+    Adc_HwTriggerTimerType TriggerSource,
+    boolean bTriggFound
+)
+{
+    Std_ReturnType Status = E_OK;
+
+    if ((TriggerSource > (Adc_HwTriggerTimerType)ADC_IPW_MAX_CTU_TRIG_SOURCE_ID) || (bTriggFound == FALSE))
+    {
+        Adc_ReportDetError(u8ServiceId, (uint8)ADC_E_WRONG_TRIGG_SRC);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+
+    return Status;
+}
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+#endif /* (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) || defined(__DOXYGEN__) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+static inline Std_ReturnType Adc_CheckSetChannelParams
+(
+    const Adc_GroupType Group,
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+    const uint16 * Delays,
+    const uint32 ChannelUpdateMask,
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+    const Adc_ChannelIndexType NumberOfChannel
+)
+{
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint32 u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+    Std_ReturnType StatusChecks = (Std_ReturnType)E_OK;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    if(0U == NumberOfChannel)
+    {
+        Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+        StatusChecks = (Std_ReturnType)E_NOT_OK;
+    }
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+    else if ((0U == ((1UL << (NumberOfChannel - 1U)) & ChannelUpdateMask))
+                && (NumberOfChannel != Adc_pCfgPtr[u32CoreIdTemp]->pGroups[GroupIndex].AssignedChannelCount)
+            )
+    {
+        /* Last channel bit must be enabled for having interrupt */
+        Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+    }
+    else if (((Std_ReturnType)E_NOT_OK == Adc_ValidatePtr(ADC_SETCHANNEL_ID, Delays))
+                && (TRUE == Adc_pCfgPtr[u32CoreIdTemp]->pGroups[GroupIndex].pAdcIpwGroupConfig->AdcGroupEnableChannelDelays)
+                && (NumberOfChannel != Adc_pCfgPtr[u32CoreIdTemp]->pGroups[GroupIndex].AssignedChannelCount)
+            )
+    {
+        /* If NumberOfChannel is different from number already configured, Delays pointer != NULL. */
+        Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_POINTER);
+    }
+    else if ( \
+                ((uint8)STD_ON == Adc_pCfgPtr[u32CoreIdTemp]->pGroups[GroupIndex].u8AdcWithoutInterrupt)
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+                || (TRUE == Adc_pCfgPtr[u32CoreIdTemp]->pGroups[GroupIndex].bAdcOptimizeDmaStream)
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+            )
+    {
+        /* Number of channels won't be greater than maximum number of SC1 registers */
+        if(ADC_MAX_CHAN_COUNT < NumberOfChannel)
+        {
+            Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+            StatusChecks = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON)
+    else
+    {
+        /* Number of channels won't be greater than maximum number of SC1 registers */
+        if(ADC_MAX_CHAN_COUNT < NumberOfChannel)
+        {
+            Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+            StatusChecks = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+#else
+    else
+    {
+        ; /* Empty else branch to avoid MISRA */
+    }
+#endif /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON) */
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+
+    return StatusChecks;
+}
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+#if ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON))
+static inline Std_ReturnType Adc_CheckSetChannelCtuTriggers
+(
+    const Adc_GroupType GroupIndex,
+    const Adc_HwUnitType LogicalHwUnitId,
+    const Adc_ChannelIndexType NumberOfChannel,
+    const uint32 u32CoreId
+)
+{
+    Std_ReturnType StatusChecks = (Std_ReturnType)E_OK;
+    if (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eTriggerSource == ADC_TRIGG_SRC_HW)
+    {
+        /* Check number of channel in the list if the HW trigger source comes from CTU or BCTU */
+        if (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].HwTriggerSource <= (Adc_HwTriggerTimerType)ADC_IPW_MAX_CTU_TRIG_SOURCE_ID)
+        {
+#if (ADC_CTU_HW_TRIGGER_OPTIMIZATION == STD_OFF)
+            /* Number channel should be less than maximum element of the CTU or BCTU List */
+            if(NumberOfChannel > Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->CtuListMaxNumElems[LogicalHwUnitId])
+            {
+                Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+                StatusChecks = (Std_ReturnType)E_NOT_OK;
+            }
+#else
+            /* Adc_SetChannel doesn't support ADC_CTU_HW_TRIGGER_OPTIMIZATION feature */
+            Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_GROUP);
+            StatusChecks = (Std_ReturnType)E_NOT_OK;
+#endif /* (ADC_CTU_HW_TRIGGER_OPTIMIZATION == STD_OFF) */
+            /* TODO: in case of CTU Trigger, need to check Channel ID is not greater than 15 due to limitation of CTU Hardware */
+        }
+    }
+    return StatusChecks;
+}
+#endif /* ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON)) */
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+#if ((ADC_DUAL_CLOCK_MODE == STD_ON) && (ADC_DEV_ERROR_DETECT == STD_ON))
+static inline boolean Adc_CheckSetClockModeCoreAndParam
+(
+    const Adc_SelectPrescalerType Prescaler,
+    const uint32 u32CoreId
+)
+{
+    boolean Valid = FALSE;
+    Std_ReturnType ValidCoreId = (Std_ReturnType)E_NOT_OK;
+
+    if (NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        Adc_ReportDetError((uint8)ADC_SETCLOCKMODE_ID, (uint8)ADC_E_UNINIT);
+    }
+    else
+    {
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreId);
+        if((Std_ReturnType)E_NOT_OK == ValidCoreId)
+        {
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError((uint8)ADC_SETCLOCKMODE_ID, (uint8)ADC_E_PARAM_CONFIG);
+        }
+        else if ((ADC_NORMAL != Prescaler) && (ADC_ALTERNATE != Prescaler))
+        {
+            Adc_ReportDetError((uint8)ADC_SETCLOCKMODE_ID, (uint8)ADC_E_INVALID_CLOCK_MODE);
+        }
+        else
+        {
+            Valid = TRUE;
+        }
+    }
+
+    return Valid;
+}
+#endif /* ((ADC_DUAL_CLOCK_MODE == STD_ON) && (ADC_DEV_ERROR_DETECT == STD_ON)) */
+
+/*==================================================================================================
+                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+/* SWS_Adc_00365, SWS_Adc_00246, SWS_Adc_00056 */
+/** @implements      Adc_Init_Activity */
+void Adc_Init
+(
+    const Adc_ConfigType * ConfigPtr
+)
+{
+    volatile uint32 u32CoreId;
+    uint32 u32CoreIdTemp;
+    Std_ReturnType ValidCoreId;
+    Std_ReturnType TimeOutStatus;
+#if (ADC_DEV_ERROR_DETECT == STD_ON) && ((ADC_VALIDATE_GLOBAL_CALL == STD_ON) || (ADC_VALIDATE_PARAMS == STD_ON))
+    Std_ReturnType ValidStatus;
+#endif
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+#if (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+        ValidStatus = Adc_ValidateGloballCall(ADC_INIT_ID, u32CoreId);
+        if ((Std_ReturnType)E_OK == ValidStatus)
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_GLOBAL_CALL == STD_ON) */
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_PARAMS == STD_ON)
+            ValidStatus = Adc_ValidatePtrInit(ConfigPtr);
+            if ((Std_ReturnType)E_OK == ValidStatus)
+            {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_PARAMS == STD_ON) */
+#if (ADC_PRECOMPILE_SUPPORT == STD_ON)
+                ValidCoreId = Adc_CheckCurrentCoreId(Adc_ConfigVariantPredefined[u32CoreId], u32CoreIdTemp);
+#else
+                ValidCoreId = Adc_CheckCurrentCoreId(ConfigPtr, u32CoreId);
+#endif /* (ADC_PRECOMPILE_SUPPORT == STD_ON) */
+                if((Std_ReturnType)E_OK == ValidCoreId)
+                {
+#if (ADC_PRECOMPILE_SUPPORT == STD_ON)
+                    (void)ConfigPtr;
+                    /* ADC342 */
+                    const Adc_ConfigType * predefined = Adc_ConfigVariantPredefined[u32CoreId];
+                    Adc_pCfgPtr[u32CoreId] = predefined;
+#else
+                    /* SWS_Adc_00054 */
+                    Adc_pCfgPtr[u32CoreId] = ConfigPtr;
+#endif /* (ADC_PRECOMPILE_SUPPORT == STD_ON) */
+                    /* Initialize the unit status for all units */
+                    Adc_InitUnitStatus(u32CoreId);
+                    /* Initialize the group status for all groups */
+                    Adc_InitGroupsStatus(u32CoreId);
+                    /* Call the low level function to initialize driver */
+                    TimeOutStatus = Adc_Ipw_Init(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig, u32CoreIdTemp);
+
+                    if ((Std_ReturnType)E_NOT_OK == TimeOutStatus)
+                    {
+                        /* Timeout is expired.*/
+                        Adc_ReportDetRuntimeError((uint8)ADC_INIT_ID, (uint8)ADC_E_TIMEOUT);
+                    }
+#if ((ADC_ENABLE_TEMPSENSE_API == STD_ON) && (ADC_POWER_ON_TEMPSENSE == STD_ON))
+                    else
+                    {
+                        (void)Adc_TempSenseSetPowerMode(ADC_NORMAL_MODE);
+                    }
+#endif /* ((ADC_ENABLE_TEMPSENSE_API == STD_ON) && (ADC_POWER_ON_TEMPSENSE == STD_ON)) */
+                }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+                else
+                {
+                    ValidStatus = (Std_ReturnType)E_NOT_OK;
+                    /* CPR_RTD_00420.adc */
+                    Adc_ReportDetError((uint8)ADC_INIT_ID, (uint8)ADC_E_PARAM_CONFIG);
+                }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+        }
+        if((Std_ReturnType)E_OK == ValidStatus)
+        {
+            Adc_EndValidateGloballCall(ValidStatus, ADC_INIT_ID, u32CoreId);
+        }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) && (ADC_VALIDATE_GLOBAL_CALL == STD_ON) */
+}
+
+/* SWS_Adc_00419 */
+/** @implements      Adc_SetupResultBuffer_Activity */
+Std_ReturnType Adc_SetupResultBuffer
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * const DataBufferPtr
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex;
+    Std_ReturnType TempReturn = (Std_ReturnType)E_NOT_OK;
+    const Adc_GroupConfigurationType * pGroupPtr = NULL_PTR;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_SETUPRESULTBUFFER_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+        /* Get the mapping index of group in the current partition */
+        GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_SETUPRESULTBUFFER_ID, DataBufferPtr))
+        {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+            if ((Std_ReturnType)E_OK == Adc_ValidateSetupBufferNotBusy(Group))
+            {
+                pGroupPtr = &Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex];
+                /* SWS_Adc_00420 */
+                (pGroupPtr->pResultsBufferPtr[Group]) = DataBufferPtr;
+#ifdef ADC_DMA_SUPPORTED
+                if(((uint8)STD_ON == pGroupPtr->u8AdcExtDMAChanEnable) && ((uint8)STD_ON == pGroupPtr->u8AdcWithoutInterrupt))
+                {
+                    /* Need to reset last buffer to invalid value before starting conversion. Because since External Dma Channel is used,
+                    last buffer will be used to check by Adc_ReadGroup to make sure the results of all channel was available. */
+                    DataBufferPtr[(pGroupPtr->AssignedChannelCount - 1U)] = ADC_IPW_INVALID_DATA_RESULT_DMA;
+                }
+#endif /* ADC_DMA_SUPPORTED */
+                TempReturn = (Std_ReturnType)E_OK;
+            }
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    return TempReturn;
+}
+
+#if (ADC_DEINIT_API == STD_ON)
+/* SWS_Adc_00366, SWS_Adc_00111 */
+/** @implements      Adc_DeInit_Activity */
+void Adc_DeInit(void)
+{
+    volatile uint32 u32CoreId;
+#if (ADC_PDB_AVAILABLE == STD_ON)
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+    Std_ReturnType ValidCoreId;
+    uint32 u32CoreIdTemp;
+    Std_ReturnType TempReturn;
+
+    Std_ReturnType ValidStatus;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+    ValidStatus = Adc_ValidateGloballCall(ADC_DEINIT_ID, u32CoreId);
+    if ((Std_ReturnType)E_OK == ValidStatus)
+    {
+#endif /* ADC_VALIDATE_GLOBAL_CALL == STD_ON */
+        ValidCoreId = Adc_CheckCurrentCoreId(Adc_pCfgPtr[u32CoreId], u32CoreIdTemp);
+        if((Std_ReturnType)E_OK == ValidCoreId)
+        {
+            ValidStatus = Adc_ValidateDeInitNotBusy(u32CoreId);
+            if ((Std_ReturnType)E_OK == ValidStatus)
+            {
+
+                TempReturn = Adc_Ipw_DeInit(u32CoreId);
+                if ((Std_ReturnType)E_NOT_OK == TempReturn)
+                {
+                    Adc_ReportDetRuntimeError((uint8)ADC_DEINIT_ID, (uint8)ADC_E_TIMEOUT);
+                }
+#if (ADC_PDB_AVAILABLE == STD_ON)
+                for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+                {
+                    if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+                    {
+                        Adc_aUnitStatus[LogicalHwUnitId].u8Sc1Used = 0U;
+                    }
+                }
+#endif /* (ADC_PDB_AVAILABLE == STD_ON) */
+                /* Undefined the global pointer to the configuration */
+                Adc_pCfgPtr[u32CoreId] = NULL_PTR;
+
+            }
+        }
+#if (ADC_VALIDATE_GLOBAL_CALL == STD_ON)
+        else
+        {
+            /* CPR_RTD_00420.adc */
+            Adc_ReportDetError(ADC_DEINIT_ID, (uint8)ADC_E_PARAM_CONFIG);
+        }
+    }
+    Adc_EndValidateGloballCall(ValidStatus, ADC_DEINIT_ID, u32CoreId);
+#endif /* ADC_VALIDATE_GLOBAL_CALL == STD_ON */
+}
+#endif /* (ADC_DEINIT_API == STD_ON) */
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/* SWS_Adc_00367, SWS_Adc_00356, SWS_Adc_00156, SWS_Adc_00061, SWS_Adc_00413 */
+/** @implements      Adc_StartGroupConversion_Activity */
+void Adc_StartGroupConversion
+(
+    Adc_GroupType Group
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+    /* ADC Hardware unit on which the requested group will run */
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_STARTGROUPCONVERSION_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+        /* Get the mapping index of group in the current partition */
+        GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+        if ((Std_ReturnType)E_OK == Adc_ValidateStateStartGroupConvNotBusy(Group, u32CoreId))
+        {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_STARTGROUPCONVERSION_ID,
+                                                                ADC_E_BUFFER_UNINIT_LIST | \
+                                                                ADC_E_WRONG_TRIGG_SRC_LIST | \
+                                                                ADC_E_QUEUE_FULL_LIST,
+                                                                Group,
+                                                                u32CoreId
+                                                               )
+               )
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+                /* Get the unit to which the group belongs to */
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+                /* Update queue */
+                Adc_UpdateStatusStartConversion(Group, LogicalHwUnitId, u32CoreId);
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        }
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+
+/* SWS_Adc_00368, SWS_Adc_00356, SWS_Adc_00413 */
+/** @implements      Adc_StopGroupConversion_Activity */
+void Adc_StopGroupConversion
+(
+    Adc_GroupType Group
+)
+{
+    /* ADC Logical Unit Id on which the requested group will run */
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_STOPGROUPCONVERSION_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+        if ((Std_ReturnType)E_OK == Adc_ValidateStateNotIdle(ADC_STOPGROUPCONVERSION_ID, Group, u32CoreId))
+        {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_STOPGROUPCONVERSION_ID,
+                                                                ADC_E_WRONG_TRIGG_SRC_LIST,
+                                                                Group,
+                                                                u32CoreId
+                                                               )
+               )
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                /* Get the unit to which the group belongs to */
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+                Adc_UpdateStatusStopConversion(Group, LogicalHwUnitId, u32CoreId);
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        }
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if (ADC_READ_GROUP_API == STD_ON)
+/* SWS_Adc_00369, SWS_Adc_00383, SWS_Adc_00503 */
+/** @implements      Adc_ReadGroup_Activity */
+Std_ReturnType Adc_ReadGroup
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * DataBufferPtr
+)
+{
+    volatile uint32 u32CoreId;
+    /* Return Value */
+    Std_ReturnType GroupRet = (Std_ReturnType)E_NOT_OK;
+    boolean bFlag = TRUE;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_VALUEREADGROUP_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_VALUEREADGROUP_ID, DataBufferPtr))
+        {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+            if ((Std_ReturnType)E_OK == Adc_ValidateStateNotIdle(ADC_VALUEREADGROUP_ID, Group, u32CoreId))
+            {
+                /* SWS_Adc_00447 */
+                GroupRet = Adc_Ipw_ReadGroup(Group, DataBufferPtr, &bFlag, u32CoreId);
+                /*if the conversion is finished or if the limit checking was failed for the group without interrupts*/
+                if(((Std_ReturnType)E_OK == GroupRet) || (FALSE == bFlag))
+                {
+                    Adc_UpdateStatusReadGroup(Group, bFlag, u32CoreId);
+                }
+            }
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    return(GroupRet);
+}
+#endif /* (ADC_READ_GROUP_API == STD_ON) */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+/* SWS_Adc_00370, SWS_Adc_00114, SWS_Adc_00114, SWS_Adc_00413 */
+/** @implements      Adc_EnableHardwareTrigger_Activity */
+void Adc_EnableHardwareTrigger
+(
+    Adc_GroupType Group
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+    /* ADC Logical Unit Id on which the requested group will run */
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Std_ReturnType ValidStatus;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_ENABLEHARDWARETRIGGER_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+        /* Get the mapping index of group in the current partition */
+        GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+        if ((Std_ReturnType)E_OK == Adc_ValidateStateEnableHwTriggNotBusy(Group, u32CoreId))
+        {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_ENABLEHARDWARETRIGGER_ID,
+                                                                ADC_E_BUFFER_UNINIT_LIST | \
+                                                                ADC_E_WRONG_TRIGG_SRC_LIST | \
+                                                                ADC_E_WRONG_CONV_MODE_LIST,
+                                                                Group,
+                                                                u32CoreId
+                                                               )
+               )
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+                /* Get the unit to which the group belongs to */
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+                Adc_UpdateStatusEnableHardware(Group, LogicalHwUnitId);
+
+                ValidStatus = Adc_Ipw_EnableHardwareTrigger(Group, LogicalHwUnitId, u32CoreId);
+                if ((Std_ReturnType)E_NOT_OK == ValidStatus)
+                {
+                    /* There is a running conversion.*/
+                    Adc_ReportDetRuntimeError((uint8)ADC_ENABLEHARDWARETRIGGER_ID, (uint8)ADC_E_BUSY);
+                }
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        }
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+
+/* SWS_Adc_00371, SWS_Adc_00413, SWS_Adc_00145 */
+/** @implements      Adc_DisableHardwareTrigger_Activity */
+void Adc_DisableHardwareTrigger
+(
+    Adc_GroupType Group
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+    /* ADC Logical Unit Id on which the requested group will run */
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_DISABLEHARDWARETRIGGER_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+        if ((Std_ReturnType)E_OK == Adc_ValidateStateNotIdle(ADC_DISABLEHARDWARETRIGGER_ID, Group, u32CoreId))
+        {
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_DISABLEHARDWARETRIGGER_ID,
+                                                                ADC_E_WRONG_TRIGG_SRC_LIST | \
+                                                                ADC_E_WRONG_CONV_MODE_LIST,
+                                                                Group,
+                                                                u32CoreId
+                                                               )
+               )
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                /* Get the unit to which the group belongs to */
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[(GroupIndex)].AdcLogicalUnitId;
+                Adc_UpdateStatusDisableHardware(Group, LogicalHwUnitId);
+
+                Adc_Ipw_DisableHardwareTrigger(Group, LogicalHwUnitId, u32CoreId);
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        }
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+/* SWS_Adc_00372, SWS_Adc_00413 */
+/** @implements      Adc_EnableGroupNotification_Activity */
+void Adc_EnableGroupNotification
+(
+    Adc_GroupType Group
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_ENABLEGROUPNOTIFICATION_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_NotifyCapablity(ADC_ENABLEGROUPNOTIFICATION_ID, Group, u32CoreId))
+        {
+#endif /* ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON */
+            /* SWS_Adc_00057 */
+            Adc_aGroupStatus[Group].eNotification = ADC_NOTIFICATION_ENABLED;
+
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+        }
+#endif /* ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+
+/* SWS_Adc_00373, SWS_Adc_00413, SWS_Adc_00416 */
+/** @implements      Adc_DisableGroupNotification_Activity */
+void Adc_DisableGroupNotification
+(
+    Adc_GroupType Group
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_DISABLEGROUPNOTIFICATION_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_NotifyCapablity(ADC_DISABLEGROUPNOTIFICATION_ID, Group, u32CoreId))
+        {
+#endif /* ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON */
+            /* SWS_Adc_00058 */
+            Adc_aGroupStatus[Group].eNotification = ADC_NOTIFICATION_DISABLED;
+
+#if (ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON)
+        }
+#endif /* ADC_VALIDATE_NOTIFY_CAPABILITY == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+
+/* SWS_Adc_00374, SWS_Adc_00140, SWS_Adc_00503, SWS_Adc_00413 */
+/** @implements      Adc_GetGroupStatus_Activity */
+Adc_StatusType Adc_GetGroupStatus
+(
+    Adc_GroupType Group
+)
+{
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    volatile uint32 u32CoreId;
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+    Adc_StatusType eTempReturn = ADC_IDLE;
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_GETGROUPSTATUS_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+        /* SWS_Adc_00220 */
+        eTempReturn = Adc_aGroupStatus[Group].eConversion;
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    return(eTempReturn);
+}
+
+/* SWS_Adc_00375, SWS_Adc_00382 */
+/** @implements      Adc_GetStreamLastPointer_Activity */
+Adc_StreamNumSampleType Adc_GetStreamLastPointer
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType ** PtrToSamplePtr
+)
+{
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    Adc_GroupType GroupIndex = 0U;
+    const Adc_GroupConfigurationType * pGroupPtr;
+    /* Number of samples to return */
+    Adc_StreamNumSampleType NumberOfResults = 0U;
+    Adc_StreamNumSampleType ResultIndex = 0U;
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    Adc_ChannelIndexType ChannelCount;
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    Std_ReturnType ValidStatus = Adc_ValidateCallAndGroup(ADC_GETSTREAMLASTPOINTER_ID, Group, u32CoreId);
+    if (ValidStatus == (Std_ReturnType)E_OK)
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+        pGroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+#if (ADC_SETCHANNEL_API == STD_ON)
+        /* Get channel count at runtime */
+        ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+        /* Get channel count from configuration */
+        ChannelCount = pGroupPtr->AssignedChannelCount;
+#endif
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+
+        if ((Std_ReturnType)E_OK == Adc_ValidateStateNotIdle(ADC_GETSTREAMLASTPOINTER_ID, Group, u32CoreId))
+        {
+            *PtrToSamplePtr = NULL_PTR;
+
+            if ((ADC_IDLE != Adc_aGroupStatus[Group].eConversion) && \
+                (ADC_BUSY != Adc_aGroupStatus[Group].eConversion)) /* SWS_Adc_00216 */
+            {
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                if ((Adc_StreamNumSampleType)0U == Adc_aGroupStatus[Group].ResultIndex)
+                {
+                    ResultIndex = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].NumSamples - (Adc_StreamNumSampleType)1U;
+                    /* SWS_Adc_00387 */
+                    NumberOfResults = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].NumSamples;
+                }
+                else
+                {
+                    ResultIndex = Adc_aGroupStatus[Group].ResultIndex - (Adc_StreamNumSampleType)1U;
+                    /* SWS_Adc_00387 */
+                    NumberOfResults = Adc_aGroupStatus[Group].ResultIndex;
+                }
+
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+                /* SWS_Adc_00214 -- SWS_Adc_00418 -- ADC382 */
+                if (FALSE == pGroupPtr->bStreamResultGroupMultiSets)
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+                {
+                    *PtrToSamplePtr = (Adc_ValueGroupType *)(&(pGroupPtr->pResultsBufferPtr[Group][ResultIndex]));
+                }
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+                else
+                {
+                    *PtrToSamplePtr = (Adc_ValueGroupType *)(&(pGroupPtr->pResultsBufferPtr[Group][ResultIndex * ChannelCount]));
+                }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+                Adc_UpdateStatusAfterGetStream(Group, u32CoreId);
+            }
+        }
+        else
+        {
+            *PtrToSamplePtr = NULL_PTR;
+        }
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+    else
+    {
+        /* SWS_Adc_00302, SWS_Adc_00218 */
+        *PtrToSamplePtr = NULL_PTR;
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    return (NumberOfResults);
+}
+
+#if (ADC_VERSION_INFO_API == STD_ON)
+/* SWS_Adc_00376 */
+/** @implements      Adc_GetVersionInfo_Activity */
+void Adc_GetVersionInfo
+(
+    Std_VersionInfoType * versioninfo
+)
+{
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_GETVERSIONINFO_ID, versioninfo))
+    {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+        (versioninfo)->vendorID = (uint16)ADC_VENDOR_ID;
+        (versioninfo)->moduleID = (uint16)ADC_MODULE_ID;
+        (versioninfo)->sw_major_version = (uint8)ADC_SW_MAJOR_VERSION;
+        (versioninfo)->sw_minor_version = (uint8)ADC_SW_MINOR_VERSION;
+        (versioninfo)->sw_patch_version = (uint8)ADC_SW_PATCH_VERSION;
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+    }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+}
+#endif /* (ADC_VERSION_INFO_API == STD_ON) */
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+/* SWS_Adc_00475, SWS_Adc_00481 */
+/** @implements      Adc_SetPowerState_Activity */
+Std_ReturnType Adc_SetPowerState
+(
+    Adc_PowerStateRequestResultType * Result
+)
+{
+    volatile uint32 u32CoreId;
+    uint32 u32CoreIdTemp;
+    Adc_PowerStateType StateTemp;
+    Std_ReturnType RetVal = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+    if((Std_ReturnType)E_OK == Adc_ValidateStateAndPtr(ADC_SETPOWERSTATE_ID, Result, u32CoreId))
+    {
+        if((Std_ReturnType)E_OK == Adc_ValidatePowerStatePrepare(ADC_SETPOWERSTATE_ID, Result, u32CoreId))
+        {
+            if((Std_ReturnType)E_OK == Adc_ValidatePowerStateSupport(ADC_SETPOWERSTATE_ID, Adc_eTargetState[u32CoreId], Result))
+            {
+                RetVal = Adc_ValidateIdleState(ADC_SETPOWERSTATE_ID, Result, u32CoreId);
+            }
+        }
+    }
+
+    if((Std_ReturnType)E_OK == RetVal)
+    {
+        RetVal = Adc_Ipw_SetPowerState(Adc_eTargetState[u32CoreId], u32CoreIdTemp);
+        if((Std_ReturnType)E_OK == RetVal)
+        {
+            /* SWS_Adc_00482 */
+            /* Everything is ok */
+            *Result = ADC_SERVICE_ACCEPTED;
+            /* Use StateTemp and u32CoreIdTemp to avoid IAR warning */
+            StateTemp = Adc_eTargetState[u32CoreIdTemp];
+            Adc_eCurrentState[u32CoreId] = StateTemp;
+            Adc_eTargetState[u32CoreId] = ADC_NODEFINE_POWER;
+        }
+        else
+        {
+            /* Hardware failure */
+            *Result = ADC_HW_FAILURE;
+        }
+    }
+
+    return RetVal;
+}
+
+/* SWS_Adc_00476 */
+/** @implements      Adc_GetCurrentPowerState_Activity */
+Std_ReturnType Adc_GetCurrentPowerState
+(
+    Adc_PowerStateType * CurrentPowerState,
+    Adc_PowerStateRequestResultType * Result
+)
+{
+    volatile uint32 u32CoreId;
+    Std_ReturnType RetVal = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if((Std_ReturnType)E_OK == Adc_ValidateStateAndPtr(ADC_GETCURRENTPOWERSTATE_ID, Result, u32CoreId))
+    {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_GETCURRENTPOWERSTATE_ID, CurrentPowerState))
+#endif /* (ADC_VALIDATE_PARAMS == STD_ON) */
+        {
+            *CurrentPowerState = Adc_eCurrentState[u32CoreId];
+            *Result = ADC_SERVICE_ACCEPTED;
+            RetVal = (Std_ReturnType)E_OK;
+        }
+    }
+    return RetVal;
+}
+
+/* SWS_Adc_00477 */
+/** @implements      Adc_GetTargetPowerState_Activity */
+Std_ReturnType Adc_GetTargetPowerState
+(
+    Adc_PowerStateType * TargetPowerState,
+    Adc_PowerStateRequestResultType * Result
+)
+{
+    volatile uint32 u32CoreId;
+    Std_ReturnType RetVal = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if((Std_ReturnType)E_OK == Adc_ValidateStateAndPtr(ADC_GETTARGETPOWERSTATE_ID, Result, u32CoreId))
+    {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_GETTARGETPOWERSTATE_ID, TargetPowerState))
+#endif /* (ADC_VALIDATE_PARAMS == STD_ON) */
+        {
+            /* SWS_Adc_00492 */
+            if(Adc_eTargetState[u32CoreId] < ADC_NODEFINE_POWER)
+            {
+                /* A transition is ongoing */
+                *TargetPowerState = Adc_eTargetState[u32CoreId];
+            }
+            else
+            {
+                /* No transition is ongoing */
+                *TargetPowerState = Adc_eCurrentState[u32CoreId];
+            }
+            *Result = ADC_SERVICE_ACCEPTED;
+            RetVal = (Std_ReturnType)E_OK;
+        }
+    }
+    return RetVal;
+}
+
+/* SWS_Adc_00478 */
+/** @implements      Adc_PreparePowerState_Activity */
+Std_ReturnType Adc_PreparePowerState
+(
+    Adc_PowerStateType PowerState,
+    Adc_PowerStateRequestResultType * Result
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_HwUnitType LogicalHwUnitId;
+    Std_ReturnType RetVal = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if ((Std_ReturnType)E_OK == Adc_ValidateStateAndPtr(ADC_PREPAREPOWERSTATE_ID, Result, u32CoreId))
+    {
+        if ((Std_ReturnType)E_OK == Adc_ValidatePowerStateSupport(ADC_PREPAREPOWERSTATE_ID, PowerState, Result))
+        {
+            RetVal = (Std_ReturnType)E_OK;
+            for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+            {
+                if (Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+                {
+                    RetVal = (Std_ReturnType)Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, ADC_PREPAREPOWERSTATE_ID);
+                }
+                if ((Std_ReturnType)E_NOT_OK == RetVal)
+                {
+                    /* Break the loop to avoid overwriting RetVal */
+                    break;
+                }
+            }
+            if ((Std_ReturnType)E_NOT_OK == RetVal)
+            {
+                *Result = ADC_TRANS_NOT_POSSIBLE;
+            }
+            else
+            {
+                /* SWS_Adc_00495 */
+                /* Everything is ok */
+                Adc_eTargetState[u32CoreId] = PowerState;
+                *Result = ADC_SERVICE_ACCEPTED;
+            }
+        }
+    }
+    return RetVal;
+}
+
+#if (ADC_POWER_STATE_ASYNCH_MODE_SUPPORTED == STD_ON)
+void Adc_Main_PowerTransitionManager(void)
+{
+
+}
+#endif /* (ADC_POWER_STATE_ASYNCH_MODE_SUPPORTED == STD_ON) */
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+#if (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON)
+/* CPR_RTD_00034.adc */
+/** @implements      Adc_SetHwUnitPowerMode_Activity */
+Std_ReturnType Adc_SetHwUnitPowerMode
+(
+    Adc_HwUnitType Unit,
+    Adc_SetPowerModeType SetPowerMode
+)
+{
+    /* TODO: update to use logical Unit ID */
+    volatile uint32 u32CoreId;
+    /* Return standard value */
+    Std_ReturnType TempReturn = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if ((Std_ReturnType)E_OK == Adc_ValidateSetHwUnitPowerMode(SetPowerMode, u32CoreId))
+    {
+        TempReturn = Adc_ValidateNotBusyNoQueue(Unit, ADC_SET_HW_UNIT_POWER_MODE_ID);
+
+        if ((Std_ReturnType)E_OK == TempReturn)
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidateCheckGroupNotConversion(ADC_SET_HW_UNIT_POWER_MODE_ID, u32CoreId))
+            {
+                TempReturn = Adc_Ipw_SetHwUnitPowerMode(Unit, SetPowerMode, u32CoreId);
+                if ((Std_ReturnType)E_NOT_OK == TempReturn)
+                {
+                    Adc_ReportDetRuntimeError((uint8)ADC_SET_HW_UNIT_POWER_MODE_ID, (uint8)ADC_E_TIMEOUT);
+                }
+            }
+        }
+    }
+    return TempReturn;
+}
+
+#if (ADC_BCTU_AVAILABLE == STD_ON)
+/* The next condition is true if CTU/BCTU Unit is used */
+#if ((ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) || (ADC_HW_TRIGGER_API == STD_ON))
+/* CPR_RTD_00453.adc, CPR_RTD_00454.adc */
+/** @implements      Adc_CtuSetPowerMode */
+Std_ReturnType Adc_CtuSetPowerMode
+(
+    Adc_HwUnitType CtuUnit,
+    Adc_PowerStateType State
+)
+{
+    volatile uint32 u32CoreId;
+    Std_ReturnType TempReturn = (Std_ReturnType)E_NOT_OK;
+    u32CoreId = (uint32)Adc_GetCoreID();
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    if (NULL_PTR == Adc_pCfgPtr[u32CoreId])
+    {
+        Adc_ReportDetError((uint8)ADC_CTU_SET_POWER_MODE_ID, (uint8)ADC_E_UNINIT);
+    }
+    else
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+        TempReturn = Adc_ValidateCheckGroupNotConversion(ADC_CTU_SET_POWER_MODE_ID, u32CoreId);
+        if ((Std_ReturnType)E_OK == TempReturn)
+        {
+            if ((Std_ReturnType)E_OK != Adc_Ipw_CtuSetPowerMode(CtuUnit, State))
+            {
+                /* CTU unit out of range */
+                Adc_ReportDetRuntimeError((uint8)ADC_CTU_SET_POWER_MODE_ID, (uint8)ADC_E_PARAM_CONFIG);
+            }
+        }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+
+    return TempReturn;
+}
+#endif /* (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON) || */
+#endif /* (ADC_BCTU_AVAILABLE == STD_ON) */
+#endif /* (ADC_SET_HW_UNIT_POWER_MODE_API == STD_ON) */
+
+#if (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON)
+/** @implements      Adc_EnableCTUTrigger_Activity */
+void Adc_EnableCTUTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType TriggerSource
+)
+{
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+    const Adc_GroupConfigurationType * pGroupConfig;
+    Adc_GroupType GroupIndex;
+    Adc_HwUnitType LogicalHwUnitId;
+    Std_ReturnType ValidStatus;
+    uint8 u8TrigIdx = 0U;
+    boolean bTriggFound;
+
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+    boolean isValidateOK = FALSE;
+    ValidStatus = Adc_ValidateCallAndGroup((uint8)ADC_ENABLECTUTRIGGER_ID, Group, u32CoreId);
+    if (ValidStatus == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+        /* Map TriggerSource to TriggerIndex */
+        bTriggFound = Adc_Ipw_MapCTUTriggerIndex(TriggerSource, u32CoreId, &u8TrigIdx);
+        (void)bTriggFound;
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+        /* Check that TriggerSource is in range */
+        Std_ReturnType TriggSrcStatus = Adc_CheckTriggerSourceRange((uint8)ADC_ENABLECTUTRIGGER_ID, TriggerSource, bTriggFound);
+        if (TriggSrcStatus == (Std_ReturnType)E_OK)
+        {
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+            GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+            pGroupConfig = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+            LogicalHwUnitId = pGroupConfig->AdcLogicalUnitId;
+
+            if ((Std_ReturnType)E_OK == Adc_ValidateNotBusyEnableHwTrig(ADC_ENABLECTUTRIGGER_ID, Group, u32CoreId))
+            {
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+                if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_ENABLECTUTRIGGER_ID,
+                                                                    ADC_E_WRONG_TRIGG_SRC_LIST | ADC_E_WRONG_CONV_MODE_LIST,
+                                                                    Group,
+                                                                    u32CoreId))
+                {
+                    isValidateOK = TRUE;
+                }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+            }
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+        }
+    }
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+    if (isValidateOK == TRUE)
+    {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04();
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        /* Check if trigger already enabled */
+        if (0U == Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][u8TrigIdx])
+        {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+            boolean bFirstTrigger = TRUE;
+            uint8 TriggerIndex;
+            for(TriggerIndex = 0U; TriggerIndex < ADC_MAX_HARDWARE_TRIGGERS; TriggerIndex++)
+            {
+                if(0U != Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][TriggerIndex])
+                {
+                    bFirstTrigger = FALSE;
+                    break;
+                }
+            }
+            /* Mark trigger as enabled */
+            Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][u8TrigIdx] = 1U;
+            SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04();
+            ValidStatus = Adc_Ipw_EnableCtuTrigger(Group, TriggerSource, bFirstTrigger, u32CoreId);
+            if ((Std_ReturnType)E_NOT_OK == ValidStatus)
+            {
+                /* There is a running conversion.*/
+                Adc_ReportDetRuntimeError((uint8)ADC_ENABLECTUTRIGGER_ID, (uint8)ADC_E_BUSY);
+            }
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        }
+        else
+        {
+            SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04();
+            /* This trigger has already been enabled for this group */
+            Adc_ReportDetError(ADC_ENABLECTUTRIGGER_ID, (uint8)ADC_E_PARAM_TRIGGER);
+        }
+    }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+}
+
+/** @implements      Adc_DisableCTUTrigger_Activity */
+void Adc_DisableCTUTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType TriggerSource
+)
+{
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+    const Adc_GroupConfigurationType * pGroupConfig;
+    Adc_GroupType GroupIndex;
+    Adc_HwUnitType LogicalHwUnitId;
+    boolean bLastTrigger = TRUE;
+    uint8 u8TrigIdx = 0U;
+    boolean bTriggFound;
+
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+    boolean isValidateOK = FALSE;
+    Std_ReturnType ValidStatus = Adc_ValidateCallAndGroup((uint8)ADC_DISABLECTUTRIGGER_ID, Group, u32CoreId);
+    if (ValidStatus == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+        /* Map TriggerSource to TriggerIndex */
+        bTriggFound = Adc_Ipw_MapCTUTriggerIndex(TriggerSource, u32CoreId, &u8TrigIdx);
+        (void)bTriggFound;
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+        /* Check that TriggerSource is in range */
+        Std_ReturnType TriggSrcStatus = Adc_CheckTriggerSourceRange((uint8)ADC_DISABLECTUTRIGGER_ID, TriggerSource, bTriggFound);
+        if (TriggSrcStatus == (Std_ReturnType)E_OK)
+        {
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+            GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+            pGroupConfig = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+            LogicalHwUnitId = pGroupConfig->AdcLogicalUnitId;
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_DISABLECTUTRIGGER_ID,
+                                                                ADC_E_WRONG_TRIGG_SRC_LIST | ADC_E_WRONG_CONV_MODE_LIST,
+                                                                Group,
+                                                                u32CoreId))
+            {
+                isValidateOK = TRUE;
+            }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON)
+        }
+    }
+#endif /* (ADC_VALIDATE_CALL_AND_GROUP  == STD_ON) */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+    if (isValidateOK == TRUE)
+    {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+        SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05();
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        /* Check if trigger already disabled */
+        if (0U != Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][u8TrigIdx])
+        {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+            /* Mark trigger as disabled */
+            Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][u8TrigIdx] = 0U;
+            /* Check the trigger is last or not */
+            uint8 TriggerIndex;
+            for (TriggerIndex = 0U; TriggerIndex < ADC_MAX_HARDWARE_TRIGGERS; TriggerIndex++)
+            {
+                if (0U != Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][TriggerIndex])
+                {
+                    bLastTrigger = FALSE;
+                    break;
+                }
+            }
+            /* Mark trigger as disabled */
+            Adc_au8CtuGroupTriggersActive[LogicalHwUnitId][u8TrigIdx] = 0U;
+            SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05();
+
+            Adc_Ipw_DisableCtuTrigger(Group, TriggerSource, bLastTrigger, u32CoreId);
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        }
+        else
+        {
+            SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05();
+            /* This trigger has already been disabled for this group */
+            Adc_ReportDetError(ADC_DISABLECTUTRIGGER_ID, (uint8)ADC_E_PARAM_TRIGGER);
+        }
+    }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+}
+
+/** @implements      Adc_HwResultReadGroup_Activity */
+Std_ReturnType Adc_HwResultReadGroup
+(
+    Adc_GroupType Group,
+    Adc_ValueGroupType * DataPtr
+)
+{
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+    /* Standard return value */
+    Std_ReturnType GroupRet = (Std_ReturnType)E_NOT_OK;
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_HWRESULTREADGROUP_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if (NULL_PTR == DataPtr)
+        {
+            GroupRet = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+#endif
+        {
+            GroupRet = Adc_Ipw_HwResultReadGroup(Group, DataPtr, u32CoreId);
+        }
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+    return(GroupRet);
+}
+#endif /* (ADC_ENABLE_CTUTRIG_NONAUTO_API == STD_ON) */
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+/** @implements      Adc_ReadRawData_Activity */
+void Adc_ReadRawData
+(
+    Adc_HwUnitType Unit,
+    const Adc_ChannelType * const ChansArray,
+    uint8 NumItems,
+    Adc_ValueGroupType * const DataBufferPtr
+)
+{
+    uint8 i;
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+    Std_ReturnType Status;
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_ENABLE_READ_RAW_DATA_ID, Unit, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_ENABLE_READ_RAW_DATA_ID, DataBufferPtr))
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_ENABLE_READ_RAW_DATA_ID, ChansArray))
+            {
+                /* Check input channel id if it's greater than maximum number of available channels */
+                if (NumItems <= ADC_IPW_RES_REG_NUM)
+                {
+    #endif /* ADC_VALIDATE_PARAMS == STD_ON */
+                    for (i = 0U; i < NumItems; i++)
+                    {
+                        Status = (Std_ReturnType)E_OK;
+                        if (ChansArray[i] < (Adc_ChannelType)ADC_IPW_MAX_CHN_ID)
+                        {
+                            Status = Adc_Ipw_GetConvData(Unit, ChansArray[i], u32CoreId, &DataBufferPtr[i]);
+                        }
+    #if (ADC_VALIDATE_PARAMS == STD_ON)
+                        else
+                        {
+                            Status = (Std_ReturnType)E_NOT_OK;
+                        }
+
+                        if ((Std_ReturnType)E_NOT_OK == Status)
+                        {
+                            Adc_ReportDetError(ADC_ENABLE_READ_RAW_DATA_ID, (uint8)ADC_E_PARAM_CONFIG);
+                        }
+    #else
+                        (void)Status;
+    #endif /* ADC_VALIDATE_PARAMS == STD_ON */
+                    }
+    #if (ADC_VALIDATE_PARAMS == STD_ON)
+                }
+                else
+                {
+                    Adc_ReportDetError(ADC_ENABLE_READ_RAW_DATA_ID, (uint8)ADC_E_PARAM_CONFIG);
+                }
+            }
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+}
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+/* CPR_RTD_00050.adc, SWS_Adc_00413 */
+void Adc_EnableChannel
+(
+   Adc_GroupType Group,
+   Adc_ChannelType Channel
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_ChannelType LogicalChannelId;
+    Adc_ChannelType PhysicalChannelId;
+    Adc_GroupType GroupId = ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX;
+    Adc_ChansIdxMaskType CmrMask;
+    uint8 i;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_ENABLE_CHANNEL_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    LogicalChannelId = Channel & ADC_CHANNEL_SYMBOLIC_NAME_MASK_CHANNEL_ID_U16;
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_ENABLE_CHANNEL_ID,
+                                                            ADC_E_WRONG_TRIGG_SRC_LIST | \
+                                                            ADC_E_WRONG_CONV_MODE_LIST | \
+                                                            ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP_LIST | \
+                                                            ADC_E_WRONG_ENABLE_CH_DISABLE_CH_ID_LIST, \
+                                                            Group, \
+                                                            u32CoreId \
+                                                           )
+           )
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidateEnableDisbleIdList(ADC_ENABLE_CHANNEL_ID, Group, LogicalChannelId, u32CoreId))
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+                /* Get the unit to which the group belongs to */
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AdcLogicalUnitId;
+                PhysicalChannelId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId]->pChannelConfigs[LogicalChannelId].u8ChannelIndex;
+                GroupId = (Adc_GroupType)Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].EnableChDisableChGroupIndex;
+
+                Adc_GetCmrRegister(LogicalHwUnitId, Group, &CmrMask, u32CoreId);
+                for (i = 0; i < ADC_SAR_NUM_GROUP_CHAN; i++)
+                {
+                    Adc_aNCMRxMask[GroupId].aChanMask[i] = CmrMask.aChanMask[i];
+                }
+                Adc_Ipw_SetChansMask(&(Adc_aNCMRxMask[GroupId]), PhysicalChannelId);
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+
+/* CPR_RTD_00050.adc, SWS_Adc_00413 */
+void Adc_DisableChannel
+(
+    Adc_GroupType Group,
+    Adc_ChannelType Channel
+)
+{
+    volatile uint32 u32CoreId;
+    Adc_GroupType GroupIndex = 0U;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_ChannelType LogicalChannelId;
+    Adc_ChannelType PhysicalChannelId;
+    Adc_GroupType GroupId = ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX;
+    Adc_ChansIdxMaskType CmrMask;
+    uint8 i;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndGroup(ADC_DISABLE_CHANNEL_ID, Group, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+
+    LogicalChannelId = Channel & ADC_CHANNEL_SYMBOLIC_NAME_MASK_CHANNEL_ID_U16;
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidateExtraParams(ADC_DISABLE_CHANNEL_ID,
+                                                            ADC_E_WRONG_TRIGG_SRC_LIST | \
+                                                            ADC_E_WRONG_CONV_MODE_LIST | \
+                                                            ADC_E_WRONG_ENABLE_CH_DISABLE_CH_GROUP_LIST | \
+                                                            ADC_E_WRONG_ENABLE_CH_DISABLE_CH_ID_LIST, \
+                                                            Group, \
+                                                            u32CoreId \
+                                                           )
+           )
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidateEnableDisbleIdList(ADC_DISABLE_CHANNEL_ID, Group, LogicalChannelId, u32CoreId))
+            {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+                GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+                LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AdcLogicalUnitId;
+                PhysicalChannelId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId]->pChannelConfigs[LogicalChannelId].u8ChannelIndex;
+                GroupId = (Adc_GroupType)Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].EnableChDisableChGroupIndex;
+
+                Adc_GetCmrRegister(LogicalHwUnitId, Group, &CmrMask, u32CoreId);
+                for (i = 0; i < ADC_SAR_NUM_GROUP_CHAN; i++)
+                {
+                    Adc_aNCMRxMask[GroupId].aChanMask[i] = CmrMask.aChanMask[i];
+                }
+                Adc_Ipw_ClearChansMask(&(Adc_aNCMRxMask[GroupId]), PhysicalChannelId);
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+            }
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_GROUP == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_GROUP == STD_ON */
+}
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+
+#if (ADC_GET_INJECTED_CONVERSION_STATUS_API == STD_ON)
+/* CPR_RTD_00275.adc, SWS_Adc_00413 */
+/** @implements      Adc_GetInjectedConversionStatus_Activity */
+Adc_StatusType Adc_GetInjectedConversionStatus
+(
+    Adc_HwUnitType Unit
+)
+{
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    volatile uint32 u32CoreId;
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+    Adc_StatusType eTempReturn = ADC_IDLE;
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    u32CoreId = (uint32)Adc_GetCoreID();
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_GETINJECTEDCONVERSIONSTATUS_ID, Unit, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+
+#if (ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON)
+        if (Adc_aUnitStatus[Unit].SwInjectedQueueIndex > (Adc_QueueIndexType)0U)
+        {
+            eTempReturn = ADC_BUSY;
+        }
+#endif /* ADC_SOFTWARE_INJECTED_CONVERSIONS_USED == STD_ON */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        if (ADC_INVALID_HW_GROUP_ID != Adc_aUnitStatus[Unit].OngoingHwGroup)
+        {
+            eTempReturn = ADC_BUSY;
+        }
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+
+    return (eTempReturn);
+}
+#endif /* (ADC_GET_INJECTED_CONVERSION_STATUS_API) */
+
+#if (ADC_CALIBRATION == STD_ON)
+/* CPR_RTD_00014.adc, CPR_RTD_00029.adc */
+/** @implements      Adc_Calibrate_Activity */
+void Adc_Calibrate
+(
+    Adc_HwUnitType Unit,
+    Adc_CalibrationStatusType * pStatus
+)
+{
+    volatile uint32 u32CoreId;
+    boolean isCalibrateCalled = FALSE;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_CALIBRATE_ID, Unit, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_CALIBRATE_ID, pStatus))
+        {
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+            /* Reset Status before executing the calibration */
+            pStatus->Adc_UnitSelfTestStatus = E_NOT_OK;
+            if ((Std_ReturnType)E_OK == Adc_ValidateNotBusyNoQueue(Unit, ADC_CALIBRATE_ID))
+            {
+                if ((Std_ReturnType)E_OK == Adc_ValidateCheckGroupNotConversion(ADC_CALIBRATE_ID, u32CoreId))
+                {
+                    Adc_Ipw_Calibrate(Unit, pStatus, u32CoreId);
+                    isCalibrateCalled = TRUE;
+                }
+            }
+            if (TRUE == isCalibrateCalled)
+            {
+                if ((Std_ReturnType)E_NOT_OK == pStatus->Adc_UnitSelfTestStatus)
+                {
+                    Adc_ReportDetRuntimeError((uint8)ADC_CALIBRATE_ID, (uint8)ADC_E_TIMEOUT);
+                }
+            }
+#if (ADC_VALIDATE_PARAMS == STD_ON)
+        }
+#endif /* ADC_VALIDATE_PARAMS == STD_ON */
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+}
+#endif /* ADC_CALIBRATION == STD_ON */
+
+#if (ADC_SELF_TEST == STD_ON)
+/** @implements      Adc_SelfTest_Activity */
+Std_ReturnType Adc_SelfTest
+(
+    Adc_HwUnitType Unit
+)
+{
+    volatile uint32 u32CoreId;
+    Std_ReturnType ReturnValue = (Std_ReturnType)E_NOT_OK;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_SELFTEST_ID , Unit, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+
+        ReturnValue = Adc_Ipw_SelfTest(Unit, u32CoreId);
+        if ((Std_ReturnType)E_NOT_OK == ReturnValue)
+        {
+            Adc_ReportDetRuntimeError((uint8)ADC_SELFTEST_ID, (uint8)ADC_E_TIMEOUT);
+        }
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    }
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+    return ReturnValue;
+}
+#endif
+
+#if (ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON)
+void Adc_ConfigureThreshold
+(
+    Adc_ThresholdControlIndexType ThresholdControlIndex,
+    Adc_WdgThresholdValueType LowValue,
+    Adc_WdgThresholdValueType HighValue
+)
+{
+    Std_ReturnType Status;
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_WdgThresholdValueType MaxHighThreshold = ((Adc_WdgThresholdValueType)1U << ADC_MAX_RESOLUTION) - 1U;
+    Adc_WdgThresholdValueType MaxLowThreshold = ((Adc_WdgThresholdValueType)1U << ADC_MAX_RESOLUTION) - 1U;
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+    volatile uint32 u32CoreId;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    LogicalHwUnitId = (uint8)(ThresholdControlIndex >> ADC_THRESHOLD_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16);
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_CONFIGURE_THRESHOLD_ID, LogicalHwUnitId, u32CoreId))
+    {
+        if ((HighValue < LowValue) || (HighValue > MaxHighThreshold) || (LowValue > MaxLowThreshold))
+        {
+            /* Error if High Threshold value is less than Low Threshold value or value > register size */
+            Adc_ReportDetError((uint8)ADC_CONFIGURE_THRESHOLD_ID, (uint8)ADC_E_WRONG_CONF_THRHLD_VALUE);
+        }
+        else
+        {
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            Status = Adc_Ipw_ConfigureThreshold(ThresholdControlIndex, LowValue, HighValue, u32CoreId);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+            if ((Std_ReturnType)E_NOT_OK == Status)
+            {
+                Adc_ReportDetError((uint8)ADC_CONFIGURE_THRESHOLD_ID, (uint8)ADC_E_WRONG_CONF_THRHLD_VALUE);
+            }
+        }
+    }
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+    (void)Status;
+}
+#endif /* ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API == STD_ON */
+
+#ifdef ADC_WDG_SUPPORTED
+/* CPR_RTD_00449.adc */
+void Adc_EnableWdgNotification
+(
+    Adc_ChannelType ChannelId
+)
+{
+    /* update enable/disable channel */
+    Std_ReturnType Status;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    volatile uint32 u32CoreId;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    LogicalHwUnitId = (Adc_HwUnitType)(ChannelId >> ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_ENABLEWDGNOTIFICATION_ID, LogicalHwUnitId, u32CoreId))
+    {
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        Status = Adc_Ipw_EnableWdgNotification(LogicalHwUnitId, ChannelId, u32CoreId);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        if ((Std_ReturnType)E_NOT_OK == Status)
+        {
+            Adc_ReportDetError((uint8)ADC_ENABLEWDGNOTIFICATION_ID, (uint8)ADC_E_PARAM_CONFIG);
+        }
+    }
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+    (void)Status;
+}
+
+/* CPR_RTD_00451.adc */
+void Adc_DisableWdgNotification
+(
+    Adc_ChannelType ChannelId
+)
+{
+    /* update enable/disable channel */
+    Std_ReturnType Status;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    volatile uint32 u32CoreId;
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+    LogicalHwUnitId = (Adc_HwUnitType)(ChannelId >> ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_DISABLEWDGNOTIFICATION_ID, LogicalHwUnitId, u32CoreId))
+    {
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        Status = Adc_Ipw_DisableWdgNotification(LogicalHwUnitId, ChannelId, u32CoreId);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        if ((Std_ReturnType)E_NOT_OK == Status)
+        {
+            Adc_ReportDetError((uint8)ADC_DISABLEWDGNOTIFICATION_ID, (uint8)ADC_E_PARAM_CONFIG);
+        }
+    }
+#endif /* if (ADC_DEV_ERROR_DETECT == STD_ON) */
+    (void)Status;
+}
+#endif /* ADC_WDG_SUPPORTED */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/* CPR_RTD_00044.adc */
+/** @implements      Adc_SetClockMode_Activity */
+Std_ReturnType Adc_SetClockMode
+(
+    Adc_SelectPrescalerType Prescaler
+)
+{
+    volatile uint32 u32CoreId;
+    Std_ReturnType Ret = (Std_ReturnType)E_NOT_OK;
+    Adc_HwUnitType LogicalHwUnitId;
+    Std_ReturnType ErrorFound = (Std_ReturnType)E_OK;
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreIdTemp;
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+
+    u32CoreId = (uint32)Adc_GetCoreID();
+#if (ADC_DEV_ERROR_DETECT == STD_ON) 
+    u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+    if (TRUE == Adc_CheckSetClockModeCoreAndParam(Prescaler, u32CoreIdTemp))
+    {
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+        for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS; LogicalHwUnitId++)
+        {
+            /* HW unit enabled on current partition */
+            if(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON)
+            {
+                ErrorFound = Adc_ValidateNotBusyNoQueue(LogicalHwUnitId, ADC_SETCLOCKMODE_ID);
+                if ((Std_ReturnType)E_NOT_OK == ErrorFound)
+                {
+                    break;
+                }
+            }
+        }
+        if ((Std_ReturnType)E_OK == ErrorFound)
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidateCheckGroupNotConversion(ADC_SETCLOCKMODE_ID, u32CoreId))
+            {
+
+                Ret = Adc_Ipw_SetClockMode(Prescaler, u32CoreId);
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+                Adc_eClockMode[u32CoreId] = Prescaler;
+#endif
+            }
+        }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+    return Ret;
+}
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+#if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)
+/* CPR_RTD_00056.adc */
+/** @implements      Adc_CtuWriteTriggerEnableMask_Activity */
+Std_ReturnType Adc_CtuWriteTriggerEnableMask
+(
+    uint8 u8Trigger,
+    uint8 u8ThcrValue
+)
+{
+    Std_ReturnType Ret = (Std_ReturnType)E_OK;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+    Ret = Adc_ValidateCallAndTrigger(CTU_SET_WRITE_TRIG_EN_MASK_ID, u8Trigger, u32CoreId);
+    if((Std_ReturnType)E_OK == Ret)
+#endif
+    {
+        Adc_Ipw_SetCtuWriteTriggerEnableMask(0U, u8Trigger, u8ThcrValue);
+    }
+    return Ret;
+}
+
+/* CPR_RTD_00059.adc */
+/** @implements      Adc_CtuSetTriggerEnable_Activity */
+Std_ReturnType Adc_CtuSetTriggerEnable
+(
+    uint8 u8Trigger,
+    boolean bEnable
+)
+{
+    Std_ReturnType Ret = (Std_ReturnType)E_OK;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+    Ret = Adc_ValidateCallAndTrigger(CTU_SET_TRIGGER_ENABLE_ID, u8Trigger, u32CoreId);
+    if((Std_ReturnType)E_OK == Ret)
+#endif
+    {
+        Adc_Ipw_CtuSetTriggerEnable(0U, u8Trigger, bEnable);
+    }
+    return Ret;
+}
+
+/* CPR_RTD_00057.adc */
+/** @implements      Adc_CtuSetTriggerAdcCmdAddress_Activity */
+Std_ReturnType Adc_CtuSetTriggerAdcCmdAddress
+(
+    uint8 u8Trigger,
+    uint8 u8ClcrValue
+)
+{
+    Std_ReturnType Ret = (Std_ReturnType)E_OK;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+    Ret = Adc_ValidateCallAndTrigger(CTU_SET_TRIGGER_ADC_CMD_ADDRESS_ID, u8Trigger, u32CoreId);
+    if((Std_ReturnType)E_OK == Ret)
+    {
+        if ((uint32)u8ClcrValue > 24u) /* TODO: Update hardcoded value */
+        {
+            Adc_ReportDetError(CTU_SET_TRIGGER_ADC_CMD_ADDRESS_ID, ADC_E_WRONG_CTU_CLCR_TRIGGER);
+            Ret = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    if((Std_ReturnType)E_OK == Ret)
+#endif
+    {
+        Adc_Ipw_SetCtuTrigAdcCmd(0U, u8Trigger, u8ClcrValue);
+    }
+    return Ret;
+}
+
+/* CPR_RTD_00058.adc */
+/** @implements      Adc_CtuSetTriggerCompare_Activity */
+Std_ReturnType Adc_CtuSetTriggerCompare
+(
+    uint8 u8Trigger,
+    uint16 u16CompareValue
+)
+{
+    Std_ReturnType Ret = (Std_ReturnType)E_OK;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+    Ret = Adc_ValidateCallAndTrigger(CTU_SET_TRIGGER_COMPARE_ID, u8Trigger, u32CoreId);
+    if((Std_ReturnType)E_OK == Ret)
+#endif
+    {
+        Adc_Ipw_SetCtuTriggerCompare(0U, u8Trigger, u16CompareValue);
+    }
+    return Ret;
+}
+#endif /* if (ADC_CTU_CONTROL_MODE_EXTRA_APIS == STD_ON)  */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+/** @implements      Adc_SetChannel_Activity */
+void Adc_SetChannel
+(
+    const Adc_GroupType Group,
+    const Adc_GroupDefType * Channel,
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+    const uint16 * Delays,
+    const uint32 ChannelUpdateMask,
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+    const Adc_ChannelIndexType NumberOfChannel
+)
+{
+#if ((ADC_DEV_ERROR_DETECT == STD_ON) || (ADC_ENABLE_LIMIT_CHECK == STD_ON))
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_GroupType GroupIndex = 0U;
+#endif /* ((ADC_DEV_ERROR_DETECT == STD_ON) || (ADC_ENABLE_LIMIT_CHECK == STD_ON)) */
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreIdTemp = u32CoreId; /* Used to avoid MISRA */
+    uint32 Index = 0u;
+    Std_ReturnType StatusChecks = Adc_ValidateCallAndGroup(ADC_SETCHANNEL_ID, Group, u32CoreId);
+
+    if (StatusChecks == (Std_ReturnType)E_OK)
+    {
+        GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+        LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AdcLogicalUnitId;
+        if ((Std_ReturnType)E_OK == Adc_ValidatePtr(ADC_SETCHANNEL_ID, Channel))
+        {
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+            StatusChecks = Adc_CheckSetChannelParams(Group, Delays, ChannelUpdateMask, NumberOfChannel);
+#else
+            StatusChecks = Adc_CheckSetChannelParams(Group, NumberOfChannel);
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+
+            for (Index = 0; Index < NumberOfChannel; Index++)
+            {
+                /* Check if input channel is configured at initialization */
+                if (
+                    (Channel[Index] >= Adc_pCfgPtr[u32CoreIdTemp]->pAdcIpwConfig->Mapping.aAdc_Channels[LogicalHwUnitId])
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+                    || ((NumberOfChannel > 1U) && (TRUE == Adc_pCfgPtr[u32CoreIdTemp]->pAdcIpwConfig->ChannelLimitCheckingConfigs[LogicalHwUnitId][Channel[Index]].bChannelLimitCheckEnabled))
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+                   )
+                {
+                    Adc_ReportDetError(ADC_SETCHANNEL_ID, (uint8)ADC_E_PARAM_CHANNEL);
+                    StatusChecks = (Std_ReturnType)E_NOT_OK;
+                    break;
+                }
+            }
+        }
+    }
+
+#if ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON))
+    if (StatusChecks == (Std_ReturnType)E_OK)
+    {
+        StatusChecks = Adc_CheckSetChannelCtuTriggers(GroupIndex, LogicalHwUnitId, NumberOfChannel, u32CoreId);
+    }
+#endif /* ((ADC_HW_TRIGGER_API == STD_ON) && (ADC_CTU_TRIGGER_MODE_SUPPORTED == STD_ON)) */
+
+    if (StatusChecks == (Std_ReturnType)E_OK)
+    {
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+        Adc_aRuntimeGroupChannel[Group].pChannel = Channel;
+        Adc_aRuntimeGroupChannel[Group].ChannelCount = NumberOfChannel;
+        Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated = TRUE;
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+#if (ADC_DEV_ERROR_DETECT == STD_OFF)
+        GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+        LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AdcLogicalUnitId;
+#endif /* (ADC_DEV_ERROR_DETECT == STD_OFF) */
+        Adc_aRuntimeGroupChannel[Group].bAdcRuntimeGroupLimitcheck = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->ChannelLimitCheckingConfigs[LogicalHwUnitId][Channel[0U]].bChannelLimitCheckEnabled;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#if (ADC_DELAY_AVAILABLE == STD_ON)
+        Adc_aRuntimeGroupChannel[Group].pu16Delays = Delays;
+        if (NumberOfChannel <= ADC_MAX_CHAN_COUNT)
+        {
+            Adc_aRuntimeGroupChannel[Group].u32Mask = ChannelUpdateMask;
+        }
+        else
+        {
+            Adc_aRuntimeGroupChannel[Group].u32Mask = 0xFFFFFFFFUL;
+        }
+#endif /* (ADC_DELAY_AVAILABLE == STD_ON) */
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+}
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+
+#ifndef ADC_CMR_REGISTER_NOT_SUPPORTED
+void Adc_GetCmrRegister /* TODO: rename and move to IPW */
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_ChansIdxMaskType * pCmrMask,
+    uint32 u32CoreId
+)
+{
+#if ((ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) || (ADC_SETCHANNEL_API == STD_OFF))
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * pGroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) || (ADC_SETCHANNEL_API == STD_OFF) */
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+    Adc_GroupType Adc_IndividualGroupId;
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    Adc_ChannelType ChId;
+    Adc_ChannelIndexType Ch;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    (void)Unit;
+
+    uint8 i;
+
+        for (i = 0; i < ADC_SAR_NUM_GROUP_CHAN; i++)
+        {
+            pCmrMask->aChanMask[i] = 0UL;
+        }
+
+    /* If the Individual group channel enable capability is ON*/
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+    Adc_IndividualGroupId = pGroupPtr->EnableChDisableChGroupIndex;
+    if(ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX != Adc_IndividualGroupId)
+    {
+        for (i = 0; i < ADC_SAR_NUM_GROUP_CHAN; i++)
+        {
+            pCmrMask->aChanMask[i] = Adc_aNCMRxMask[Adc_IndividualGroupId].aChanMask[i];
+        }
+    }
+    else
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+    {
+#if (ADC_SETCHANNEL_API == STD_ON)
+        for(Ch = 0U; Ch < Adc_aRuntimeGroupChannel[Group].ChannelCount; Ch++)
+        {
+            ChId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[Unit]->pChannelConfigs[Adc_aRuntimeGroupChannel[Group].pChannel[Ch]].u8ChannelIndex;
+            Adc_Ipw_SetChansMask(pCmrMask, ChId);
+        }
+#else
+        /* Program the mask registers */
+        for (i = 0; i < ADC_SAR_NUM_GROUP_CHAN; i++)
+        {
+            pCmrMask->aChanMask[i] = pGroupPtr->AssignedChannelMask.aChanMask[i];
+        }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    }
+}
+#endif /* ADC_CMR_REGISTER_NOT_SUPPORTED */
+
+
+#if (ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON)
+/* CPR_RTD_00271.adc */
+/** @implements      Adc_EnableCtuControlMode_Activity */
+void Adc_EnableCtuControlMode
+(
+    Adc_HwUnitType Unit
+)
+{
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_ENABLE_CTU_CONTROL_MODE_ID, Unit, u32CoreId))
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    {
+        if ((Std_ReturnType)E_OK == Adc_ValidateUnitActive(ADC_ENABLE_CTU_CONTROL_MODE_ID, Unit, u32CoreId))
+        {
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+            if ((Std_ReturnType)E_OK == Adc_ValidateStateCtuControlMode(ADC_ENABLE_CTU_CONTROL_MODE_ID, Unit))
+            {
+                Adc_Ipw_EnableCtuControlMode(Unit, u32CoreId);
+            }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+}
+
+/* CPR_RTD_00271.adc */
+/** @implements      Adc_DisableCtuControlMode_Activity */
+void Adc_DisableCtuControlMode
+(
+    Adc_HwUnitType Unit
+)
+{
+    volatile uint32 u32CoreId = (uint32)Adc_GetCoreID();
+
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_DISABLE_CTU_CONTROL_MODE_ID, Unit, u32CoreId))
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    {
+        if ((Std_ReturnType)E_OK == Adc_ValidateUnitActive(ADC_DISABLE_CTU_CONTROL_MODE_ID, Unit, u32CoreId))
+        {
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+            if ((Std_ReturnType)E_OK == Adc_ValidateStateCtuControlMode(ADC_DISABLE_CTU_CONTROL_MODE_ID, Unit))
+            {
+                Adc_Ipw_DisableCtuControlMode(Unit, u32CoreId);
+            }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* ADC_DEV_ERROR_DETECT == STD_ON */
+}
+
+/* CPR_RTD_00455.adc */
+/** @implements      Adc_CtuEnableHwTrigger_Activity */
+void Adc_CtuEnableHwTrigger
+(
+    Adc_CtuTrigSrcType TrigSource
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_ENABLE_HW_TRIGGER_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(TrigSource > ADC_IPW_MAX_CTU_TRIG_SOURCE_ID)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC);
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            Adc_Ipw_CtuEnableHwTrigger(0u, (uint8)TrigSource);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuDisableHwTrigger_Activity */
+void Adc_CtuDisableHwTrigger
+(
+    Adc_CtuTrigSrcType TrigSource
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_DISABLE_HW_TRIGGER_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(TrigSource > ADC_IPW_MAX_CTU_TRIG_SOURCE_ID)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC);
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            Adc_Ipw_CtuDisableHwTrigger(0u, (uint8)TrigSource);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuStartConversion_Activity */
+void Adc_CtuStartConversion
+(
+    Adc_CtuTrigSrcType TrigSource
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_START_CONVERSION_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(TrigSource > ADC_IPW_MAX_CTU_TRIG_SOURCE_ID)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC);
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            Adc_Ipw_CtuStartConversion(0u, (uint8)TrigSource);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+#if (ADC_CTU_AVAILABLE == STD_ON)
+/** @implements      Adc_CtuMasterReload_Activity */
+void Adc_CtuMasterReload
+(
+    Adc_HwUnitType CtuUnit
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_MASTER_RELOAD_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        Adc_Ipw_CtuMasterReload(CtuUnit);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+#endif /* (ADC_CTU_AVAILABLE == STD_ON) */
+
+#if (ADC_BCTU_AVAILABLE == STD_ON)
+/** @implements      Adc_CtuReadConvData_Activity */
+Adc_ValueGroupType Adc_CtuReadConvData
+(
+    Adc_HwUnitType AdcUnit
+)
+{
+    Adc_ValueGroupType ConvData = 0u;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_READ_CONV_DATA_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        ConvData = Adc_Ipw_CtuReadConvData(0u, AdcUnit);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+    return ConvData;
+}
+
+/** @implements      Adc_CtuReadConvResult_Activity */
+void Adc_CtuReadConvResult
+(
+    Adc_HwUnitType AdcUnit,
+    Adc_CtuResultType * pResult
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_READ_CONV_RESULT_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+        Adc_Ipw_CtuReadConvResult(0u, AdcUnit, pResult);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuStopLoopConversions_Activity */
+void Adc_CtuStopLoopConversions
+(
+    Adc_CtuTrigSrcType TrigSource
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_STOP_LOOP_CONVERSION_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(TrigSource > ADC_IPW_MAX_CTU_TRIG_SOURCE_ID)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC);
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+            Adc_Ipw_CtuStopLoopConversions(0u, (uint8)TrigSource);
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+#endif /* (ADC_BCTU_AVAILABLE == STD_ON) */
+
+/** @implements      Adc_CtuReadFifoData_Activity */
+void Adc_CtuReadFifoData
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    uint16 * pu16Data,
+    uint8 u8DataLength
+)
+{
+    uint8 Index;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_READ_FIFO_DATA_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(FifoIdx >= ADC_IPW_NUM_CTU_FIFO)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC); /* TODO update error code. Add rest of DET checks. */
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+           for(Index = 0u; Index < u8DataLength; Index++)
+           {
+               pu16Data[Index] = Adc_Ipw_CtuReadFifoData(0u, FifoIdx);
+           }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuReadFifoResult_Activity */
+void Adc_CtuReadFifoResult
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    Adc_CtuFifoResultType * pResult,
+    uint8 u8ResultLength
+)
+{
+    uint8 Index;
+
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_READ_FIFO_RESULT_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(FifoIdx >= ADC_IPW_NUM_CTU_FIFO)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC); /* TODO update error code. Add rest of DET checks. */
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+            for(Index = 0u; Index < u8ResultLength; Index++)
+            {
+                Adc_Ipw_CtuReadFifoResult(0u, FifoIdx, &(pResult[Index]));
+            }
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuSetFifoWatermark_Activity */
+void Adc_CtuSetFifoWatermark
+(
+    Adc_CtuFifoIdxType FifoIdx,
+    uint8 u8Watermark
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_SET_FIFO_WATERMARK_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(FifoIdx >= ADC_IPW_NUM_CTU_FIFO)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC); /* TODO update error code. Add rest of DET checks. */
+        }
+        else
+        {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+            Adc_Ipw_CtuSetFifoWatermark(0u, FifoIdx, u8Watermark);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuEnableNotification_Activity */
+void Adc_CtuEnableNotification
+(
+    Adc_CtuNotificationType Notification
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_ENABLE_NOTIFICATION_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+            Adc_Ipw_CtuEnableNotification(0u, Notification);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuDisableNotification_Activity */
+void Adc_CtuDisableNotification
+(
+    Adc_CtuNotificationType Notification
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_DISABLE_NOTIFICATION_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+            Adc_Ipw_CtuDisableNotification(0u, Notification);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuSetList_Activity */
+void Adc_CtuSetList
+(
+    const Adc_CtuListItemType * const ListItemsArray,
+    const uint8 NumItems,
+    const uint8 ListStartPosition
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_SET_LIST_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+        if(ListItemsArray == NULL_PTR)
+        {
+            Adc_ReportDetError(u8ServiceId, ADC_E_PARAM_POINTER);
+        }
+        else
+        {
+            if((NumItems >= ADC_IPW_NUM_CTU_LIST_ELEMS) || (ListStartPosition >= ADC_IPW_NUM_CTU_LIST_ELEMS))
+            {
+                Adc_ReportDetError(u8ServiceId, ADC_E_WRONG_TRIGG_SRC);
+            }
+            else
+            {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+               Adc_Ipw_CtuSetList(0u, ListStartPosition, ListItemsArray, NumItems);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+            }
+        }
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+
+/** @implements      Adc_CtuSetListPointer_Activity */
+void Adc_CtuSetListPointer
+(
+    Adc_CtuTrigSrcType TrigSource,
+    Adc_CtuListPtrType ListPtr
+)
+{
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    uint32 u32CoreId = (uint32)Adc_GetCoreID();
+    const uint8 u8ServiceId = ADC_CTU_SET_LIST_POINTER_ID;
+
+    if (Adc_ValidateCtuControlModeApi(u8ServiceId, u32CoreId) == (Std_ReturnType)E_OK)
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+        Adc_Ipw_CtuSetListPointer(0u, TrigSource, ListPtr);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+}
+#endif /* ADC_ENABLE_CTU_CONTROL_MODE_API == STD_ON */
+
+#if (ADC_ENABLE_TEMPSENSE_API == STD_ON)
+/** @implements      Adc_TempSenseCalculateTemp_Activity */
+uint16 Adc_TempSenseCalculateTemp
+(
+    Adc_HwUnitType Unit,
+    const uint16 TempSenseAdcConvData
+)
+{
+    uint16 TempSenseVal;
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    if (TempSenseAdcConvData >= TEMPSENSE_RESOLUTION_12B)
+    {
+        /* The data conversion must be converted to 12bit resolution */
+        Adc_ReportDetError(ADC_TEMPSENSE_CALCULATE_TEMP_ID, ADC_E_PARAM_CONFIG);
+        TempSenseVal = 0u; /* Invalid value */
+    }
+    else
+    {
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+        TempSenseVal = Adc_Ipw_TempSenseCalculateTemp(Unit, 0u, TempSenseAdcConvData);
+#if (ADC_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* (ADC_DEV_ERROR_DETECT == STD_ON) */
+
+    return TempSenseVal;
+}
+
+/** @implements      Adc_TempSenseGetTemp_Activity */
+Std_ReturnType Adc_TempSenseGetTemp
+(
+    Adc_HwUnitType Unit,
+    uint16 * const TempSenseVal
+)
+{
+    Std_ReturnType RetVal;
+    boolean isGetTempCalled = FALSE;
+    bTempsenseInUsed = TRUE;
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    if ((Std_ReturnType)E_OK == Adc_ValidateCallAndUnit(ADC_TEMPSENSE_GET_TEMP_ID, Unit, u32CoreId))
+    {
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+        if ((Std_ReturnType)E_OK == Adc_ValidateNotBusyNoQueue(Unit, ADC_TEMPSENSE_GET_TEMP_ID))
+        {
+            if ((Std_ReturnType)E_OK == Adc_ValidateCheckGroupNotConversion(ADC_TEMPSENSE_GET_TEMP_ID, u32CoreId))
+            {
+                RetVal = Adc_Ipw_TempSenseGetTemp(Unit, 0u, TempSenseVal, u32CoreId);
+                isGetTempCalled = TRUE;
+            }
+        }
+        if (FALSE == isGetTempCalled)
+        {
+            RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+#if (ADC_VALIDATE_CALL_AND_UNIT == STD_ON)
+    }
+    else
+    {
+        RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+#endif /* ADC_VALIDATE_CALL_AND_UNIT == STD_ON */
+    bTempsenseInUsed = FALSE;
+
+    return RetVal;
+}
+
+/** @implements      Adc_TempSenseSetPowerMode_Activity */
+Std_ReturnType Adc_TempSenseSetPowerMode
+(
+    Adc_SetPowerModeType SetPowerMode
+)
+{
+    Std_ReturnType ReturnStatus = (Std_ReturnType)E_OK;
+
+    if (ADC_POWER_DOWN_MODE == SetPowerMode)
+    {
+        if (bTempsenseInUsed == FALSE)
+        {
+            Adc_Ipw_TempSenseDisable(0u);
+        }
+        else
+        {
+            ReturnStatus = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    else
+    {
+        Adc_Ipw_TempSenseEnable(0u);
+    }
+
+    return ReturnStatus;
+}
+
+#endif /* (ADC_ENABLE_TEMPSENSE_API == STD_ON) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Adc_Ip.c

@@ -0,0 +1,1351 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+#include "Adc_Ip.h"
+#include "Adc_Ip_HwAccess.h"
+#include "SchM_Adc.h"
+#include "OsIf.h"
+
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+#include "Devassert.h"
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+/* USER_MODE_REG_PROT_ENABLED is defined for Base sanity check in RegLockMacros.h */
+#define USER_MODE_REG_PROT_ENABLED      (ADC_IP_ENABLE_USER_MODE_SUPPORT)
+#include "RegLockMacros.h"
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define ADC_IP_VENDOR_ID_C                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_C       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_C       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_C    0
+#define ADC_IP_SW_MAJOR_VERSION_C               1
+#define ADC_IP_SW_MINOR_VERSION_C               0
+#define ADC_IP_SW_PATCH_VERSION_C               0
+
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+/* Check if Adc_Ip.c file and Adc_Ip.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_C != ADC_IP_VENDOR_ID_H)
+    #error "Adc_Ip.c and Adc_Ip.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip.c file and Adc_Ip.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_C != ADC_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_C != ADC_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.c and Adc_Ip.h are different"
+#endif
+
+/* Check if Adc_Ip.c file and Adc_Ip.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_C != ADC_IP_SW_MAJOR_VERSION_H) || \
+     (ADC_IP_SW_MINOR_VERSION_C != ADC_IP_SW_MINOR_VERSION_H) || \
+     (ADC_IP_SW_PATCH_VERSION_C != ADC_IP_SW_PATCH_VERSION_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip.c and Adc_Ip.h are different"
+#endif
+
+/* Check if Adc_Ip.c file and Adc_Ip_HwAccess.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_C != ADC_IP_VENDOR_ID_HWACCESS_H)
+    #error "Adc_Ip.c and Adc_Ip_HwAccess.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip.c file and Adc_Ip_HwAccess.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_C != ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_C != ADC_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.c and Adc_Ip_HwAccess.h are different"
+#endif
+
+/* Check if Adc_Ip.c file and Adc_Ip_HwAccess.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_C != ADC_IP_SW_MAJOR_VERSION_HWACCESS_H) || \
+     (ADC_IP_SW_MINOR_VERSION_C != ADC_IP_SW_MINOR_VERSION_HWACCESS_H) || \
+     (ADC_IP_SW_PATCH_VERSION_C != ADC_IP_SW_PATCH_VERSION_HWACCESS_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip.c and Adc_Ip_HwAccess.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Adc_Ip.c file and OsIf.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+        (ADC_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.c and OsIf.h are different"
+#endif
+
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    /* Checks against RegLockMacros.h */
+    #if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
+         (ADC_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Adc_Ip.c and RegLockMacros.h are different"
+    #endif
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+
+/* Check if Adc_Ip.c and SchM_Adc.h are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_ADC_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc_Ip.c and SchM_Adc.h are different"
+#endif
+
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+/* Check if Adc_Ip.c and Devassert.h are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip.c and Devassert.h are different"
+#endif
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/*******************************************************************************
+ * Pre-check
+ ******************************************************************************/
+#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
+    #if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+        #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running ADC in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
+    #endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */
+
+/*******************************************************************************
+ * Local function prototypes
+ ******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+static void ADC_SetSupplyMonitoringEnable_TrustedCall(const boolean SupplyEnable);
+static void ADC_SetSupplyMonitoringEnable(const boolean SupplyEnable);
+static void ADC_ConfigSupplyMonitoringChannel_TrustedCall(const uint32 SupplyChannel);
+static void ADC_ConfigSupplyMonitoringChannel(const uint32 SupplyChannel);
+static void ADC_ResetSupplyMonitoringChannel_TrustedCall(void);
+static void ADC_ResetSupplyMonitoringChannel(void);
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+static void ADC_SetTriggerSourceSelect_TrustedCall(const uint32 Instance, const uint8 TriggerSource);
+static void ADC_SetTriggerSourceSelect(const uint32 Instance, const uint8 TriggerSource);
+static void ADC_SetPretriggerSourceSelect_TrustedCall(const uint32 Instance, const uint8 PretriggerSource);
+static void ADC_SetPretriggerSourceSelect(const uint32 Instance, const uint8 PretriggerSource);
+static void ADC_SetSoftwarePretrigger_TrustedCall(const uint32 Instance, const uint8 SoftwarePretrigger);
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#define ADC_START_SEC_CONST_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/* Table of Base addresses for ADC instances. */
+static ADC_Type * const AdcBase[ADC_INSTANCE_COUNT] = IP_ADC_BASE_PTRS;
+
+#define ADC_STOP_SEC_CONST_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+/* Global state structure */
+static Adc_Ip_StateStructType AdcIpState[ADC_INSTANCE_COUNT];
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_DoCalibration_SetParams
+* Description   : This function configures averaging, sample time, input clock and trigger
+* mode for Adc_Ip_DoCalibration service.
+*
+* END**************************************************************************/
+static inline void Adc_DoCalibration_SetParams(ADC_Type * const Base, const Adc_Ip_ClockConfigType * const Config, const Adc_Ip_TrigType TriggerMode);
+
+static inline void Adc_DoCalibration_SetParams(ADC_Type * const Base, const Adc_Ip_ClockConfigType * const Config, const Adc_Ip_TrigType TriggerMode)
+{
+    /* Configure averaging */
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29();
+    Adc_HwAcc_SetAveraging(Base, Config->AvgEn, Config->AvgSel);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29();
+
+    /* Configure trigger mode */
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24();
+    Adc_HwAcc_SetTriggerMode(Base, TriggerMode);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24();
+
+    /* Configure sample time */
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15();
+    Adc_HwAcc_SetSampleTime(Base, Config->SampleTime);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15();
+
+    /* Configure input clock */
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13();
+    Adc_HwAcc_SetClock(Base, Config->ClockDivide, Config->InputClock);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_Init
+* Description   : This function initializes the ADC module by configuring all
+* available features.
+*
+* @implements     Adc_Ip_Init_Activity
+* END**************************************************************************/
+void Adc_Ip_Init(const uint32 Instance, const Adc_Ip_ConfigType * const Config)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(Config != NULL_PTR);
+    DevAssert(Config->NumChannels <= ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    uint32 SC2Reg = 0u;
+    uint32 SC2ClearMask = 0u;
+    uint8 Index;
+
+    Adc_HwAcc_SetClock(Base, Config->ClockDivide, Config->InputClock);
+    Adc_HwAcc_SetSampleTime(Base, Config->SampleTime);
+    Adc_HwAcc_SetAveraging(Base, Config->AvgEn, Config->AvgSel);
+
+    Adc_Ip_SetResolution(Instance, Config->Resolution);
+
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    ADC_SetTriggerSourceSelect(Instance, Config->TriggerSel);
+    ADC_SetPretriggerSourceSelect(Instance, Config->PretriggerSel);
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    if (Instance == 0U)
+    {
+        ADC_SetSupplyMonitoringEnable(Config->SupplyMonitoringEnable);
+    }
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+
+    /* Configure trigger mode */
+    SC2ClearMask |= ADC_SC2_ADTRG_MASK;
+    SC2Reg |= ADC_SC2_ADTRG(Config->TriggerMode);
+
+    /* Configure DMA enable */
+    if (Config->DmaEnable)
+    {
+        SC2Reg |= ADC_SC2_DMAEN_MASK;
+    }
+    else
+    {
+        SC2ClearMask |= ADC_SC2_DMAEN_MASK;
+    }
+
+    /* Configure voltage reference selector */
+    SC2ClearMask |= ADC_SC2_REFSEL_MASK;
+    SC2Reg |= ADC_SC2_REFSEL(Config->VoltageRef);
+
+    /* Configure compare enables and values */
+    SC2ClearMask |= ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
+    SC2Reg |= ADC_SC2_ACFE(Config->CompareEnable ? 1u : 0u);
+    SC2Reg |= ADC_SC2_ACFGT(Config->CompareGreaterThanEnable ? 1u : 0u);
+    SC2Reg |= ADC_SC2_ACREN(Config->CompareRangeFuncEnable ? 1u : 0u);
+    Base->CV[0u] = ADC_CV_CV(Config->CompVal1);
+    Base->CV[1u] = ADC_CV_CV(Config->CompVal2);
+
+    Adc_HwAcc_SetSC2Reg(Base, SC2ClearMask, SC2Reg);
+
+    Adc_HwAcc_SetUserGainAndOffset(Base, Config->UsrGain, Config->UsrOffset);
+
+    Adc_Ip_SetContinuousMode(Instance, Config->ContinuousConvEnable);
+
+    if (Config->ChannelConfigs != NULL_PTR)
+    {
+        for (Index = 0u; Index < Config->NumChannels; Index++)
+        {
+            Adc_Ip_ConfigChannel(Instance, &(Config->ChannelConfigs[Index]));
+        }
+    }
+
+    AdcIpState[Instance].ConversionCompleteNotification = Config->ConversionCompleteNotification;
+    AdcIpState[Instance].CalibrationClockDivide = Config->CalibrationClockDivide;
+    AdcIpState[Instance].Init = TRUE;
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    AdcIpState[Instance].PretriggerSel = Config->PretriggerSel;
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_DeInit
+* Description   : This function resets the ADC internal registers to default values.
+*
+* @implements     Adc_Ip_Deinit_Activity
+* END**************************************************************************/
+void Adc_Ip_DeInit(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    Adc_Ip_ConfigType DefaultConfig;
+    Adc_Ip_ChanConfigType ChannelConfigs[ADC_MAX_CHAN_COUNT];
+    uint8 Index;
+
+    DefaultConfig.ClockDivide = ADC_IP_CLK_FULL_BUS;
+    DefaultConfig.CalibrationClockDivide = ADC_IP_CLK_EIGHTH_BUS;
+    DefaultConfig.InputClock = ADC_IP_CLK_ALT_1;
+    DefaultConfig.SampleTime = ADC_IP_DEFAULT_SAMPLE_TIME;
+    DefaultConfig.AvgEn = FALSE;
+    DefaultConfig.AvgSel = ADC_IP_AVG_4_CONV;
+    DefaultConfig.Resolution = ADC_IP_RESOLUTION_8BIT;
+    DefaultConfig.TriggerMode = ADC_IP_TRIGGER_SOFTWARE;
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    DefaultConfig.PretriggerSel = ADC_IP_PRETRIGGER_SEL_PDB;
+    DefaultConfig.TriggerSel = ADC_IP_TRIGGER_SEL_PDB;
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+    DefaultConfig.DmaEnable = FALSE;
+    DefaultConfig.VoltageRef = ADC_IP_VOLTAGEREF_VREF;
+    DefaultConfig.ContinuousConvEnable = FALSE;
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    DefaultConfig.SupplyMonitoringEnable = FALSE;
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+    DefaultConfig.CompareEnable = FALSE;
+    DefaultConfig.CompareGreaterThanEnable = FALSE;
+    DefaultConfig.CompareRangeFuncEnable = FALSE;
+    DefaultConfig.CompVal1 = 0u;
+    DefaultConfig.CompVal2 = 0u;
+    DefaultConfig.UsrGain = ADC_IP_DEFAULT_USER_GAIN;
+    DefaultConfig.UsrOffset = 0u;
+    DefaultConfig.NumChannels = ADC_MAX_CHAN_COUNT;
+    for (Index = 0u; Index < ADC_MAX_CHAN_COUNT; Index++)
+    {
+        ChannelConfigs[Index].ChnIdx = Index;
+        ChannelConfigs[Index].Channel = ADC_IP_INPUTCHAN_DISABLED;
+        ChannelConfigs[Index].InterruptEnable = FALSE;
+    }
+    DefaultConfig.ChannelConfigs = ChannelConfigs;
+    DefaultConfig.ConversionCompleteNotification = NULL_PTR;
+
+    Adc_Ip_Init(Instance, &DefaultConfig);
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    if (Instance == 0U)
+    {
+        ADC_ResetSupplyMonitoringChannel();
+    }
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+
+    AdcIpState[Instance].Init = FALSE;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetAveraging
+* Description   : This function enables averaging and selects the number of 
+* conversions to average.
+* The mask parameter should be set using the Adc_Ip_AvgSelectType enum elements
+* that have the pattern ADC_IP_AVG_... e.g. ADC_IP_AVG_4_CONV.
+*
+* @implements     Adc_Ip_SetAveraging_Activity
+* END**************************************************************************/
+void Adc_Ip_SetAveraging(const uint32 Instance, const boolean AvgEn, const Adc_Ip_AvgSelectType AvgSel)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27();
+    Adc_HwAcc_SetAveraging(Base, AvgEn, AvgSel);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetSampleTime
+* Description   : This function sets the sample time for selected ADC instance.
+*
+* @implements     Adc_Ip_SetSampleTime_Activity
+* END**************************************************************************/
+void Adc_Ip_SetSampleTime(const uint32 Instance, const uint8 SampleTime)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16();
+    Adc_HwAcc_SetSampleTime(Base, SampleTime);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_EnableDma
+* Description   : This function enables DMA.
+*
+* @implements     Adc_Ip_EnableDma_Activity
+* END**************************************************************************/
+void Adc_Ip_EnableDma(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26();
+    Base->SC2 |= ADC_SC2_DMAEN_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_DisableDma
+* Description   : This function disables DMA.
+*
+* @implements     Adc_Ip_DisableDma_Activity
+* END**************************************************************************/
+void Adc_Ip_DisableDma(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22();
+    Base->SC2 &= ~(ADC_SC2_DMAEN_MASK);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetTriggerMode
+* Description   : This function enables either hardware or software trigger.
+*
+* @implements     Adc_Ip_SetTriggerMode_Activity
+* END**************************************************************************/
+void Adc_Ip_SetTriggerMode(const uint32 Instance, const Adc_Ip_TrigType TriggerMode)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23();
+    Adc_HwAcc_SetTriggerMode(Base, TriggerMode);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetContinuousMode
+* Description   : This function switches between ADC continuous conversion mode 
+* and one shot mode.
+*
+* @implements     Adc_Ip_SetContinuousMode_Activity
+* END**************************************************************************/
+void Adc_Ip_SetContinuousMode(const uint32 Instance, const boolean ContinuousModeEnable)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30();
+    uint32 Sc3Reg = Base->SC3;
+    Sc3Reg &= ~(ADC_SC3_ADCO_MASK);
+    Sc3Reg |= ADC_SC3_ADCO(ContinuousModeEnable ? 1u : 0u);
+    Base->SC3 = Sc3Reg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetResolution
+* Description   : This function sets ADC module resolution.
+*
+* @implements     Adc_Ip_SetResolution_Activity
+* END**************************************************************************/
+void Adc_Ip_SetResolution(const uint32 Instance, const Adc_Ip_ResolutionType Resolution)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10();
+    uint32 Cfg1Reg = Base->CFG1;
+    Cfg1Reg &= ~(ADC_CFG1_MODE_MASK);
+    Cfg1Reg |= ADC_CFG1_MODE(Resolution);
+    Base->CFG1 = Cfg1Reg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetClockMode
+* Description   : This function initializes the ADC clock configuration.
+*
+* @implements     Adc_Ip_SetClockMode_Activity
+* END**************************************************************************/
+void Adc_Ip_SetClockMode(const uint32 Instance, const Adc_Ip_ClockConfigType * const Config)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(Config != NULL_PTR);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11();
+    Adc_HwAcc_SetClock(Base, Config->ClockDivide, Config->InputClock);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11();
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14();
+    Adc_HwAcc_SetSampleTime(Base, Config->SampleTime);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14();
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28();
+    Adc_HwAcc_SetAveraging(Base, Config->AvgEn, Config->AvgSel);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_ConfigChannel
+* Description   : Configures the selected control channel with the given
+* configuration structure.
+*
+* When Software Trigger mode is enabled, configuring control channel index 0,
+* implicitly triggers a new conversion on the selected ADC input channel.
+* Therefore, Adc_Ip_ConfigChannel can be used for sw-triggering conversions.
+*
+* Configuring any control channel while it is actively controlling a conversion
+* (sw or hw triggered) will implicitly abort the on-going conversion.
+*
+* @implements     Adc_Ip_ConfigChannel_Activity
+* END**************************************************************************/
+void Adc_Ip_ConfigChannel(const uint32 Instance, const Adc_Ip_ChanConfigType * const ChanConfig)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ChanConfig != NULL_PTR);
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    DevAssert((Instance == 0u) || ((uint32)ChanConfig->Channel < (uint32)ADC_IP_INPUTCHAN_SUPPLY_VDD));
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    Adc_Ip_InputChannelType InputChanDemapped;
+
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    /* Internal supply monitor channels need special configuration */
+    if (ChanConfig->Channel >= ADC_IP_INPUTCHAN_SUPPLY_VDD)
+    {
+        /* De-map ADC_IP_INPUTCHAN_SUPPLY_ into actual index. */
+        const uint32 SupplyChannel = (uint32)ChanConfig->Channel - (uint32)ADC_IP_INPUTCHAN_SUPPLY_VDD;
+        ADC_ConfigSupplyMonitoringChannel(SupplyChannel);
+        /* Supply monitor channels are measured on ADC internal input channel 0 */
+        InputChanDemapped = ADC_IP_INPUTCHAN_INT0;
+    }
+    else
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+    {
+        InputChanDemapped = ChanConfig->Channel;
+    }
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21();
+    Adc_HwAcc_SetChannel(Base, ChanConfig->ChnIdx, InputChanDemapped, ChanConfig->InterruptEnable);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21();
+
+    /* Also update in state structure */
+    AdcIpState[Instance].ChannelConfig[ChanConfig->ChnIdx] = ChanConfig->Channel;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetDisabledChannel
+* Description   : This function sets the input channel of the selected control 
+* channel to ADC_IP_INPUTCHAN_DISABLED. If WithTimeout is TRUE then the 
+* function will also wait for the register to be updated.
+* Note: the control channel index is the numeric index of SC1x 
+* (e.g. SC1A has index 0), not the input channel.
+*
+* @implements     Adc_Ip_SetDisabledChannel_Activity
+* END**************************************************************************/
+Adc_Ip_StatusType Adc_Ip_SetDisabledChannel(const uint32 Instance, const uint8 ControlChanIdx, const boolean WithTimeout)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    Adc_Ip_StatusType Status = ADC_IP_STATUS_SUCCESS;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_IP_TIMEOUT_VAL, ADC_IP_TIMEOUT_TYPE);
+    uint32 CurrentTicks = OsIf_GetCounter(ADC_IP_TIMEOUT_TYPE);
+    uint32 ElapsedTicks = 0u;
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17();
+    /* Set input channel select to disabled */
+    SC1(Base, ControlChanIdx) |= ADC_SC1_ADCH_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17();
+
+    if (WithTimeout == TRUE)
+    {
+        while (((SC1(Base, ControlChanIdx) & ADC_SC1_ADCH_MASK) != ADC_SC1_ADCH_MASK) && (ElapsedTicks < TimeoutTicks))
+        {
+            ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_IP_TIMEOUT_TYPE);
+        }
+        if (ElapsedTicks >= TimeoutTicks)
+        {
+            Status = ADC_IP_STATUS_TIMEOUT;
+        }
+    }
+
+    return Status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_StartConversion
+* Description   : This function starts a software conversion on the selected 
+* input channel by writing the given values to the SC1A register.
+* The result can be read with Adc_Ip_GetConvData with index 0.
+* Note: hardware configuration on the control channel with index 0 will be 
+* overwritten.
+* Note: this will not work if hardware triggered mode is selected.
+*
+* @implements     Adc_Ip_StartConversion_Activity
+* END**************************************************************************/
+void Adc_Ip_StartConversion(const uint32 Instance, Adc_Ip_InputChannelType InputChannel, const boolean InterruptEnable)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18();
+    /* Configure SC1A register */
+    Adc_HwAcc_SetChannel(Base, 0u, InputChannel, InterruptEnable);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetConvActiveFlag
+* Description   : Reads and return conversion active flag status.
+*
+* @implements     Adc_Ip_GetConvActiveFlag_Activity
+* END**************************************************************************/
+boolean Adc_Ip_GetConvActiveFlag(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+    uint32 Sc2Reg = Base->SC2;
+
+    Sc2Reg = (Sc2Reg & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT;
+
+    return (Sc2Reg != 0u) ? TRUE : FALSE;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetChanInterrupt
+* Description   :  This function checks and returns if the selected control 
+* channel has the interrupt flag set.
+*
+* @implements     Adc_Ip_GetChanInterrupt_Activity
+* END**************************************************************************/
+boolean Adc_Ip_GetChanInterrupt(const uint32 Instance, const uint8 ControlChanIdx)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+    const uint32 Sc1Reg = SC1(Base, ControlChanIdx);
+
+    return Adc_HwAcc_GetAIEN(Sc1Reg);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetConvCompleteFlag
+* Description   :  This function returns the value of the conversion 
+* complete(COCO) flag of a given channel.
+*
+* @implements     Adc_Ip_GetConvCompleteFlag_Activity
+* END**************************************************************************/
+boolean Adc_Ip_GetConvCompleteFlag(const uint32 Instance, const uint8 ControlChanIdx)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+    const uint32 Sc1Reg = SC1(Base, ControlChanIdx);
+
+    return Adc_HwAcc_GetCOCO(Sc1Reg);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetConvData
+* Description   : This function retrieves the last conversion result for the 
+* selected control channel. This function does no validity check on the result. 
+* In order to check if the result is valid, the user must call 
+* Adc_Ip_GetConvCompleteFlag function before this one.
+*
+* @implements     Adc_Ip_GetConvData_Activity
+* END**************************************************************************/
+uint16 Adc_Ip_GetConvData(const uint32 Instance, const uint8 ControlChanIdx)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+
+    return Adc_HwAcc_GetData(Base, ControlChanIdx);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_DoCalibration
+* Description   : This function performs a calibration of the ADC. The input
+* clock frequency for calibration must be less than or equal to half of the maximum
+* specified frequency (50Mhz) and greater than minimum specified frequency (20Mhz).
+*
+* @implements     Adc_Ip_DoCalibration_Activity
+* END**************************************************************************/
+Adc_Ip_StatusType Adc_Ip_DoCalibration(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    Adc_Ip_StatusType Status = ADC_IP_STATUS_SUCCESS;
+    Adc_Ip_TrigType TriggerMode;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_IP_TIMEOUT_VAL, ADC_IP_TIMEOUT_TYPE);
+    uint32 CurrentTicks = OsIf_GetCounter(ADC_IP_TIMEOUT_TYPE);
+    uint32 ElapsedTicks = 0u;
+    uint32 Reg;
+    Adc_Ip_ClockConfigType PreClockConfig;
+    Adc_Ip_ClockConfigType CalClockConfig;
+
+    /* Store settings before calibration */
+    Reg = Base->SC3;
+    PreClockConfig.AvgEn = ((Reg & ADC_SC3_AVGE_MASK) != 0u) ? TRUE : FALSE;
+    PreClockConfig.AvgSel = Adc_HwAcc_GetAverageSelect(Reg);
+
+    Reg = Base->CFG2;
+    PreClockConfig.SampleTime = (uint8) ((Reg & ADC_CFG2_SMPLTS_MASK) >> ADC_CFG2_SMPLTS_SHIFT);
+    TriggerMode = Adc_HwAcc_GetTriggerMode(Base->SC2);
+
+    Reg = Base->CFG1;
+    PreClockConfig.ClockDivide = Adc_HwAcc_GetClockDivide(Reg);
+    PreClockConfig.InputClock = Adc_HwAcc_GetInputClock(Reg);
+
+    CalClockConfig.AvgEn = TRUE;
+    CalClockConfig.AvgSel = ADC_IP_AVG_32_CONV;
+    CalClockConfig.SampleTime = ADC_IP_DEFAULT_SAMPLE_TIME;
+    CalClockConfig.ClockDivide = AdcIpState[Instance].CalibrationClockDivide;
+    CalClockConfig.InputClock = PreClockConfig.InputClock;
+
+    /* Prepare required settings for calibration. */
+    Adc_DoCalibration_SetParams(Base, &CalClockConfig, ADC_IP_TRIGGER_SOFTWARE);
+
+    Base->CLPS = 0u;
+    Base->CLP3 = 0u;
+    Base->CLP2 = 0u;
+    Base->CLP1 = 0u;
+    Base->CLP0 = 0u;
+    Base->CLPX = 0u;
+    Base->CLP9 = 0u;
+
+    /* Start calibration by writing to the calibration field */
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29();
+    Reg = Base->SC3;
+    Reg &= ~(ADC_SC3_CAL_MASK);
+    Reg |= ADC_SC3_CAL(1u);
+    Base->SC3 = Reg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29();
+
+    /* Wait for the calibration to finish */
+    while (((Base->SC3 & ADC_SC3_CAL_MASK) != 0u) && (ElapsedTicks < TimeoutTicks))
+    {
+        ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_IP_TIMEOUT_TYPE);
+    }
+    if (ElapsedTicks >= TimeoutTicks)
+    {
+        Status = ADC_IP_STATUS_TIMEOUT;
+    }
+
+    /* Revert settings as same as before calibration. */
+    Adc_DoCalibration_SetParams(Base, &PreClockConfig, TriggerMode);
+
+    /* Clear COCO flag */
+    (void) R(Base, 0u);
+
+    return Status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_ClearLatchedTriggers
+* Description   : This function clears all trigger latched flags of the ADC instance.
+* This function must be called after the hardware trigger source for the ADC 
+* has been deactivated.
+*
+* @implements     Adc_Ip_ClearLatchedTriggers_Activity
+* END**************************************************************************/
+Adc_Ip_StatusType Adc_Ip_ClearLatchedTriggers(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(Instance != 0u);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    Adc_Ip_StatusType Status = ADC_IP_STATUS_SUCCESS;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(ADC_IP_TIMEOUT_VAL, ADC_IP_TIMEOUT_TYPE);
+    uint32 CurrentTicks = OsIf_GetCounter(ADC_IP_TIMEOUT_TYPE);
+    uint32 ElapsedTicks = 0u;
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12();
+    /* Write bit to clear latched triggers */
+    Base->CFG1 |= ADC_CFG1_CLRLTRG(0x01u);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12();
+
+    /* Wait for latched triggers to be cleared */
+    while (((Base->SC2 & ADC_SC2_TRGSTLAT_MASK) != 0u) && (ElapsedTicks < TimeoutTicks))
+    {
+        ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, ADC_IP_TIMEOUT_TYPE);
+    }
+    if (ElapsedTicks >= TimeoutTicks)
+    {
+        Status = ADC_IP_STATUS_TIMEOUT;
+    }
+
+    return Status;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_EnableChannelNotification
+* Description   : This function enables the notification for the selected channel.
+* Note          : It's required to read result data in user notification in order to clear the COCO flags and avoid ISR getting invoked repeatedly
+*
+* @implements     Adc_Ip_EnableChannelNotification_Activity
+* END**************************************************************************/
+void Adc_Ip_EnableChannelNotification(const uint32 Instance, const uint8 ControlChanIdx)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19();
+    SC1(Base, ControlChanIdx) |= ADC_SC1_AIEN_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_DisableChannelNotification
+* Description   : This function disables the notification for the selected channel.
+*
+* @implements     Adc_Ip_DisableChannelNotification_Activity
+* END**************************************************************************/
+void Adc_Ip_DisableChannelNotification(const uint32 Instance, const uint8 ControlChanIdx)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(ControlChanIdx < ADC_MAX_CHAN_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20();
+    SC1(Base, ControlChanIdx) &= ~(ADC_SC1_AIEN_MASK);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_ClearTrigErrReg
+* Description   : This function clears all trigger error flags of the ADC instance.
+*
+* @implements     Adc_Ip_ClearTrigErrReg_Activity
+* END**************************************************************************/
+void Adc_Ip_ClearTrigErrReg(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(Instance != 0u);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    ADC_Type * const Base = AdcBase[Instance];
+    
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25();
+    Base->SC2 |= ADC_SC2_TRGSTERR_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetTrigErrReg
+* Description   : This function returns all trigger error flags of the ADC instance.
+*
+* @implements     Adc_Ip_GetTrigErrReg_Activity
+* END**************************************************************************/
+uint32 Adc_Ip_GetTrigErrReg(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    DevAssert(Instance != 0u);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+
+    return (Base->SC2 & ADC_SC2_TRGSTERR_MASK) >> ADC_SC2_TRGSTERR_SHIFT;
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : Adc_Ip_GetDataAddress
+ * Description   : Returns the address of the specified Rn register.
+ *
+ * @implements     Adc_Ip_GetDataAddress_Activity
+ *END*************************************************************************/
+uint32 Adc_Ip_GetDataAddress(const uint32 Instance, const uint8 Index)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+    return (uint32)&(R(AdcBase[Instance], Index));
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_GetChanData
+* Description   : This function retrieves the last conversion result for the
+* selected input channel, by looking which control channel was configured
+* with it. If multiple control channels are configured simultaneously with
+* the same requested input channel, the result of the first control channel
+* found will be returned. If no control channel is configured with the given
+* input channel then ADC_IP_STATUS_ERROR will be returned.
+* This function does no validity check on the result.
+* In order to check if the result is valid, the user must call
+* Adc_Ip_GetConvCompleteFlag function before this one.
+*
+* @implements     Adc_Ip_GetChanData_Activity
+* END**************************************************************************/
+Adc_Ip_StatusType Adc_Ip_GetChanData(const uint32 Instance, const Adc_Ip_InputChannelType Channel, uint16 * const Result)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    DevAssert((Instance == 0u) || ((uint32)Channel < (uint32)ADC_IP_INPUTCHAN_SUPPLY_VDD));
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+    Adc_Ip_StatusType Status = ADC_IP_STATUS_SUCCESS;
+    uint16 Temp = 0u;
+    uint8 ControlChanIdx;
+    boolean Found = FALSE;
+
+    for (ControlChanIdx = 0u; ControlChanIdx < ADC_MAX_CHAN_COUNT; ControlChanIdx++)
+    {
+        if (AdcIpState[Instance].ChannelConfig[ControlChanIdx] == Channel)
+        {
+            Found = TRUE;
+            break;
+        }
+    }
+
+    if (Found == TRUE)
+    {
+        Temp = (uint16) R(Base, ControlChanIdx);
+        Temp = (uint16) ((Temp & ADC_R_D_MASK) >> ADC_R_D_SHIFT);
+    }
+    else
+    {
+        Status = ADC_IP_STATUS_ERROR;
+    }
+
+    *Result = Temp;
+
+    return Status;
+}
+
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+/*FUNCTION**********************************************************************
+*
+* Function Name : Adc_Ip_SetSoftwarePretrigger
+* Description   : This function sets the software pretrigger source for 
+* an ADC instance.
+*
+* @implements     Adc_Ip_SetSoftwarePretrigger_Activity
+* END**************************************************************************/
+void Adc_Ip_SetSoftwarePretrigger(const uint32 Instance, const Adc_Ip_SoftwarePretriggerType SoftwarePretrigger)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+    /* If SW Pretrigger Select is not enabled, the SW pretriggers will be ignored by ADC. */
+    DevAssert(AdcIpState[Instance].PretriggerSel == ADC_IP_PRETRIGGER_SEL_SW);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call2params(ADC_SetSoftwarePretrigger_TrustedCall, Instance, (uint8)SoftwarePretrigger);
+#else
+    ADC_SetSoftwarePretrigger_TrustedCall(Instance, (uint8)SoftwarePretrigger);
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : Adc_Ip_IRQHandler
+ * Description   : Handles Adc interrupts.
+ * Note          : It's required to read result data in user notification in order to clear the COCO flags and avoid ISR getting invoked repeatedly
+ *
+ * @implements     Adc_Ip_IRQHandler_Activity
+ *END*************************************************************************/
+/* The IAR build wants to see function prototypes */
+void Adc_Ip_IRQHandler(const uint32 Instance);
+
+void Adc_Ip_IRQHandler(const uint32 Instance)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < ADC_INSTANCE_COUNT);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const ADC_Type * const Base = AdcBase[Instance];
+    uint32 Sc1Reg;
+    uint8 ControlChanIdx;
+    boolean ChanIntFlag = FALSE;
+    boolean ChanCocoFlag = FALSE;
+
+    /* NOTE: CPR_RTD_00028 wasn't fulfilled in because ISR cannot distinguish if an interrupt is spurious or if conversion was initiated on purpose with AIEN = 0
+    * The reasons are:
+    *  - There is a single interrupt line for all COCO flags
+    *  - It is a valid usecase to have COCO flag set but AIEN=0 (e.g. in HLD only interrupt for last channel in group is enabled)
+    *  - Clearing of COCO flag is only done by reading the result register - COCO is not w1c
+    */
+
+    /* Check if the Adc unit is initialized and if the interrupt is not NULL 
+     * first since all channels use the same callback */
+    if ((AdcIpState[Instance].Init == TRUE) && 
+        (AdcIpState[Instance].ConversionCompleteNotification != NULL_PTR))
+    {
+        for (ControlChanIdx = 0u; ControlChanIdx < ADC_MAX_CHAN_COUNT; ControlChanIdx++)
+        {
+            Sc1Reg = SC1(Base, ControlChanIdx);
+            ChanIntFlag = Adc_HwAcc_GetAIEN(Sc1Reg);
+            ChanCocoFlag = Adc_HwAcc_GetCOCO(Sc1Reg);
+            /* Check if the interrupt was spurrios by checking if the interrupt 
+             * is enabled and equivalent conversion has finished */
+            if ((TRUE == ChanIntFlag) && (TRUE == ChanCocoFlag))
+            {
+                AdcIpState[Instance].ConversionCompleteNotification(ControlChanIdx);
+            }
+            else if ((ADC_IP_INPUTCHAN_DISABLED == AdcIpState[Instance].ChannelConfig[ControlChanIdx]) && (TRUE == ChanCocoFlag))
+            {
+                /* This will only clear the obvious spurious COCO flags. If the flag will be spuriously set on active channels it will not be caught by this. */
+                (void)Adc_HwAcc_GetData(Base, ControlChanIdx);
+            }
+            else
+            {
+                ; /* Empty else branch to avoid MISRA */
+            }
+        }
+    }
+    else
+    {
+        for (ControlChanIdx = 0u; ControlChanIdx < ADC_MAX_CHAN_COUNT; ControlChanIdx++)
+        {
+            /* Do a dummy read to clear the COCO flags */
+            (void)Adc_HwAcc_GetData(Base, ControlChanIdx);
+        }
+    }
+}
+
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+static void ADC_SetSupplyMonitoringEnable_TrustedCall(const boolean SupplyEnable)
+{
+    /* Set or clear ADC_SUPPLY field of CHIPCTL register from SIM based on SupplyEnable */
+    if (SupplyEnable == TRUE)
+    {
+        IP_SIM->CHIPCTL |= SIM_CHIPCTL_ADC_SUPPLYEN_MASK;
+    }
+    else
+    {
+        IP_SIM->CHIPCTL &= ~SIM_CHIPCTL_ADC_SUPPLYEN_MASK;
+    }
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_SetSupplyMonitoringEnable
+* Description   : This function enable supply monitoring for the internal channels
+* on SIM registers
+*
+* END**************************************************************************/
+static void ADC_SetSupplyMonitoringEnable(const boolean SupplyEnable)
+{
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call1param(ADC_SetSupplyMonitoringEnable_TrustedCall, SupplyEnable);
+#else
+    ADC_SetSupplyMonitoringEnable_TrustedCall(SupplyEnable);
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+
+static void ADC_ConfigSupplyMonitoringChannel_TrustedCall(const uint32 SupplyChannel)
+{
+#if (ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert((IP_SIM->CHIPCTL & SIM_CHIPCTL_ADC_SUPPLYEN_MASK) != 0UL);
+#endif /* (ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32();
+    uint32 Reg = IP_SIM->CHIPCTL;
+    Reg &= ~SIM_CHIPCTL_ADC_SUPPLY_MASK;
+    Reg |= SIM_CHIPCTL_ADC_SUPPLY(SupplyChannel);
+    IP_SIM->CHIPCTL = Reg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_ConfigSupplyMonitoringChannel
+* Description   : This function configures the internal channels on on SIM registers
+*
+* END**************************************************************************/
+static void ADC_ConfigSupplyMonitoringChannel(const uint32 SupplyChannel)
+{
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call1param(ADC_ConfigSupplyMonitoringChannel_TrustedCall, SupplyChannel);
+#else
+    ADC_ConfigSupplyMonitoringChannel_TrustedCall(SupplyChannel);
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+
+static void ADC_ResetSupplyMonitoringChannel_TrustedCall(void)
+{
+    /* Clear ADC supply mask from CHIPCTL of SIM register */
+    IP_SIM->CHIPCTL &= ~SIM_CHIPCTL_ADC_SUPPLY_MASK;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_ResetSupplyMonitoringChannel
+* Description   : This function resets the muxing for ADC channel on SIM register to reset value
+*
+* END**************************************************************************/
+static void ADC_ResetSupplyMonitoringChannel(void)
+{
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call(ADC_ResetSupplyMonitoringChannel_TrustedCall);
+#else
+    ADC_ResetSupplyMonitoringChannel_TrustedCall();
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_SetTriggerSourceSelect
+* Description   : This function selects trigger source for an ADC instance
+*
+* END**************************************************************************/
+static void ADC_SetTriggerSourceSelect(const uint32 Instance, const uint8 TriggerSource)
+{
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call2params(ADC_SetTriggerSourceSelect_TrustedCall, Instance, TriggerSource);
+#else
+    ADC_SetTriggerSourceSelect_TrustedCall(Instance, TriggerSource);
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+
+static void ADC_SetTriggerSourceSelect_TrustedCall(const uint32 Instance, const uint8 TriggerSource)
+{
+    uint32 Reg = (uint32)IP_SIM->ADCOPT;
+
+#if (ADC_INSTANCE_COUNT > 1u)
+    switch (Instance)
+    {
+        case 0u:
+        {
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+            Reg &= ~SIM_ADCOPT_ADC0TRGSEL_MASK;
+            Reg |= SIM_ADCOPT_ADC0TRGSEL(TriggerSource);
+#if (ADC_INSTANCE_COUNT > 1u)
+            break;
+        }
+        case 1u:
+        {
+            Reg &= ~SIM_ADCOPT_ADC1TRGSEL_MASK;
+            Reg |= SIM_ADCOPT_ADC1TRGSEL(TriggerSource);
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+#else
+    (void)Instance;
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+    IP_SIM->ADCOPT = Reg;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_SetPretriggerSourceSelect
+* Description   : This function selects pretrigger source for an ADC instance
+*
+* END**************************************************************************/
+static void ADC_SetPretriggerSourceSelect(const uint32 Instance, const uint8 PretriggerSource)
+{
+#if (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call2params(ADC_SetPretriggerSourceSelect_TrustedCall, Instance, PretriggerSource);
+#else
+    ADC_SetPretriggerSourceSelect_TrustedCall(Instance, PretriggerSource);
+#endif /* (STD_ON == ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+}
+
+static void ADC_SetPretriggerSourceSelect_TrustedCall(const uint32 Instance, const uint8 PretriggerSource)
+{
+    uint32 Reg = (uint32)IP_SIM->ADCOPT;
+
+#if (ADC_INSTANCE_COUNT > 1u)
+    switch (Instance)
+    {
+        case 0u:
+        {
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+            Reg &= ~SIM_ADCOPT_ADC0PRETRGSEL_MASK;
+            Reg |= SIM_ADCOPT_ADC0PRETRGSEL(PretriggerSource);
+#if (ADC_INSTANCE_COUNT > 1u)
+            break;
+        }
+        case 1u:
+        {
+            Reg &= ~SIM_ADCOPT_ADC1PRETRGSEL_MASK;
+            Reg |= SIM_ADCOPT_ADC1PRETRGSEL(PretriggerSource);
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+#else
+    (void)Instance;
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+    IP_SIM->ADCOPT = Reg;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : ADC_SetSoftwarePretrigger_TrustedCall
+* Description   : This function writes the software pretrigger source to be 
+* configured for an ADC instance
+*
+* END**************************************************************************/
+static void ADC_SetSoftwarePretrigger_TrustedCall(const uint32 Instance, const uint8 SoftwarePretrigger)
+{
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31();
+    uint32 Reg = (uint32)IP_SIM->ADCOPT;
+
+#if (ADC_INSTANCE_COUNT > 1u)
+    switch (Instance)
+    {
+        case 0u:
+        {
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+            Reg &= ~SIM_ADCOPT_ADC0SWPRETRG_MASK;
+            Reg |= SIM_ADCOPT_ADC0SWPRETRG(SoftwarePretrigger);
+#if (ADC_INSTANCE_COUNT > 1u)
+            break;
+        }
+        case 1u:
+        {
+            Reg &= ~SIM_ADCOPT_ADC1SWPRETRG_MASK;
+            Reg |= SIM_ADCOPT_ADC1SWPRETRG(SoftwarePretrigger);
+            break;
+        }
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+#else
+    (void)Instance;
+#endif /* (ADC_INSTANCE_COUNT > 1u) */
+    IP_SIM->ADCOPT = Reg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31();
+}
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+/** @} */

RTD/src/Adc_Ip_Isr.c

@@ -0,0 +1,111 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip Adc IPL
+*   @{
+*/
+
+#include "OsIf.h"
+#include "Mcal.h"
+#include "Adc_Ip_CfgDefines.h"
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define ADC_IP_VENDOR_ID_ISR_C                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_ISR_C    0
+#define ADC_IP_SW_MAJOR_VERSION_ISR_C               1
+#define ADC_IP_SW_MINOR_VERSION_ISR_C               0
+#define ADC_IP_SW_PATCH_VERSION_ISR_C               0
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Adc_Ip_Isr.c file and OsIf.h file are of the same Autosar version */
+    #if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != OSIF_AR_RELEASE_MINOR_VERSION)    \
+        )
+        #error "AutoSar Version Numbers of Adc_Ip_Isr.c and OsIf.h are different"
+    #endif
+
+    /* Check if Adc_Ip_Isr.c file and Mcal.h file are of the same Autosar version */
+    #if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != MCAL_AR_RELEASE_MINOR_VERSION)    \
+        )
+        #error "AutoSar Version Numbers of Adc_Ip_Isr.c and Mcal.h are different"
+    #endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/* Check if Adc_Ip_Isr.c file and Adc_Ip_CfgDefines.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_ISR_C != ADC_IP_VENDOR_ID_CFGDEFINES_H)
+    #error "Adc_Ip_Isr.c and Adc_Ip_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_Isr.c file and Adc_Ip_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_ISR_C != ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_Isr.c and Adc_Ip_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ip_Isr.c file and Adc_Ip_CfgDefines.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_ISR_C != ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_SW_MINOR_VERSION_ISR_C != ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_IP_SW_PATCH_VERSION_ISR_C != ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_Isr.c and Adc_Ip_CfgDefines.h are different"
+#endif
+
+/******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+extern void Adc_Ip_IRQHandler(const uint32 Instance);
+
+ISR(Adc_0_Isr); /* IAR requires prototypes. */
+ISR(Adc_0_Isr)
+{
+    Adc_Ip_IRQHandler(0UL);
+
+    EXIT_INTERRUPT();
+}
+
+#if (ADC_INSTANCE_COUNT > 1)
+ISR(Adc_1_Isr); /* IAR requires prototypes. */
+ISR(Adc_1_Isr)
+{
+    Adc_Ip_IRQHandler(1UL);
+
+    EXIT_INTERRUPT();
+}
+#endif /* (ADC_INSTANCE_COUNT > 1) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+/** @} */

RTD/src/Adc_Ipw.c

@@ -0,0 +1,2233 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ipw Adc Ipw
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ipw.h"
+#include "Adc.h" /*TODO: to be removed when separating ADC HLD from IPW*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_IPW_C                    43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_C     4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_C     4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_C  0
+#define ADC_SW_MAJOR_VERSION_IPW_C             1
+#define ADC_SW_MINOR_VERSION_IPW_C             0
+#define ADC_SW_PATCH_VERSION_IPW_C             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if source file and ADC IPW header file are from the same vendor */
+#if (ADC_VENDOR_ID_IPW_C != ADC_VENDOR_ID_IPW_H)
+    #error "Adc_Ipw.c and Adc_Ipw.h have different vendor ids"
+#endif
+
+/* Check if source file and ADC IPW header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw.c and Adc_Ipw.h are different"
+#endif
+
+/* Check if source file and ADC IPW header file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_C != ADC_SW_MAJOR_VERSION_IPW_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_C != ADC_SW_MINOR_VERSION_IPW_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_C != ADC_SW_PATCH_VERSION_IPW_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw.c and Adc_Ipw.h are different"
+#endif
+
+/* Check if source file and ADC header file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_C != ADC_VENDOR_ID)
+#error "Adc_Ipw.c and Adc.h have different vendor ids"
+#endif
+
+/* Check if source file and ADC header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_C != ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_C != ADC_AR_RELEASE_MINOR_VERSION) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_C != ADC_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc_Ipw.c and Adc.h are different"
+#endif
+
+/* Check if source file and ADC header file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_C != ADC_SW_MAJOR_VERSION) || \
+     (ADC_SW_MINOR_VERSION_IPW_C != ADC_SW_MINOR_VERSION) || \
+     (ADC_SW_PATCH_VERSION_IPW_C != ADC_SW_PATCH_VERSION) \
+    )
+#error "Software Version Numbers of Adc_Ipw.c and Adc.h are different"
+#endif
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+#define ADC_IPW_NUM_CHANNELS_USED(x) ((((x) >> 3U) != 0U) ? 8U : (x))
+#define ADC_IPW_PDB_CHANNELS_USED(x) ((((x)%8U) != 0U) ? (((x)/8U) + 1U) : ((x)/8U))
+#define ADC_IPW_PDB_PRETRIGG_MASK(x) (0xFFU >> (8U-(x)))
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+#if (ADC_SETCHANNEL_API == STD_ON)
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+extern Adc_RuntimeGroupChannelType Adc_aRuntimeGroupChannel[ADC_MAX_GROUPS];
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+#ifdef ADC_DMA_SUPPORTED
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+#define ADC_START_SEC_VAR_CLEARED_8_NO_CACHEABLE
+#include "Adc_MemMap.h"
+
+#define ADC_STOP_SEC_VAR_CLEARED_8_NO_CACHEABLE
+#include "Adc_MemMap.h"
+#endif /*  (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+
+#define ADC_START_SEC_VAR_CLEARED_16_NO_CACHEABLE
+#include "Adc_MemMap.h"
+
+/* Internal Dma Buffer filled in by DMA for groups having Without Interrupts enabled. It stores full results, to be read and masked accordingly when Adc_ReadGroup is called. */
+static uint16 u16DmaNoIrqBuffer[ADC_MAX_HW_UNITS][ADC_MAX_CHANNEL_PER_HW_UNIT];
+
+#define ADC_STOP_SEC_VAR_CLEARED_16_NO_CACHEABLE
+#include "Adc_MemMap.h"
+#endif /* ADC_DMA_SUPPORTED */
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if (ADC_READ_GROUP_API == STD_ON)
+#ifdef ADC_DMA_SUPPORTED
+static inline uint16 Adc_Ipw_GetAdcDataMask
+(
+    Adc_Ip_ResolutionType Resolution
+);
+#endif /* ADC_DMA_SUPPORTED */
+
+static inline Std_ReturnType Adc_Ipw_ReadGroupConvData
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+);
+
+static inline Std_ReturnType Adc_Ipw_ReadGroupNoInt
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+);
+
+static inline void Adc_Ipw_WriteDataBuffer
+(
+    const Adc_GroupType Group,
+    Adc_ValueGroupType * pDataPtr,
+    uint32 u32CoreId
+);
+#endif /* (ADC_READ_GROUP_API == STD_ON) */
+
+static inline uint8 Adc_Ipw_ConfigurePdbChannels
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint8 NumChannel
+);
+
+static inline void Adc_Ipw_ConfigurePdbConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel
+);
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+static inline Std_ReturnType Adc_Ipw_StopConversionCheckTimeout
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+static inline void Adc_Ipw_PrepareGroupStart
+(
+    Adc_HwUnitType Unit,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint32 u32CoreId
+);
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+#if (ADC_READ_GROUP_API == STD_ON)
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief          This function gets data mask based on selected Adc resolution
+* @details        This function gets data mask based on selected Adc resolution
+*
+* @param[in]      Resolution    Adc resolution enum value
+*
+* @return         uint16        Data mask
+*/
+static inline uint16 Adc_Ipw_GetAdcDataMask
+(
+    Adc_Ip_ResolutionType Resolution
+)
+{
+    uint16 Mask;
+    switch (Resolution)
+    {
+        case ADC_IP_RESOLUTION_8BIT:
+            Mask = 0xFFu;
+            break;
+        case ADC_IP_RESOLUTION_10BIT:
+            Mask = 0x3FFu;
+            break;
+        case ADC_IP_RESOLUTION_12BIT:
+            Mask = 0xFFFu;
+            break;
+        default:
+            /* Default is 12 bits */
+            Mask = 0xFFFu;
+            break;
+    }
+    return Mask;
+}
+#endif /* ADC_DMA_SUPPORTED */
+
+static inline Std_ReturnType Adc_Ipw_ReadGroupConvData
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+)
+{
+    uint8 Channel;
+    Adc_ValueGroupType AdcResult;
+    Std_ReturnType ReadGroupRet = (Std_ReturnType) E_OK;
+    const Adc_HwUnitType LogicalHwUnitId = pGroupPtr->AdcLogicalUnitId;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[LogicalHwUnitId];
+    const uint8 NumsBitShift = Adc_Ipw_CalculateNumsBitShift(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId]->Resolution);
+#if (defined(ADC_DMA_SUPPORTED) || (ADC_ENABLE_LIMIT_CHECK == STD_ON) || (ADC_SETCHANNEL_API == STD_ON))
+    const Adc_GroupType Group = pGroupPtr->GroupId;
+#endif /* (defined(ADC_DMA_SUPPORTED) || ... */
+#ifdef ADC_DMA_SUPPORTED
+    /* When DMA is used, the masking result is required according to safety analysis. For interrupt case, this is done by Adc_Ip_GetConvData. */
+    const uint16 DmaBufferMask = Adc_Ipw_GetAdcDataMask(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId]->Resolution);
+#endif /* ADC_DMA_SUPPORTED */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    Adc_ChannelType ChIndex;
+    /* Flag to set if ADC results are in the selected range */
+    boolean bWriteFlag = TRUE;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    const Adc_ChannelIndexType ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    const Adc_ChannelIndexType ChannelCount = pGroupPtr->AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    for (Channel = 0U; Channel < ChannelCount; Channel++)
+    {
+#ifdef ADC_DMA_SUPPORTED
+        if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId]) && (pGroupPtr->u8AdcWithoutDma == FALSE))
+        {
+            if((uint8)STD_OFF == pGroupPtr->u8AdcExtDMAChanEnable)
+            {
+                AdcResult = (uint16) (u16DmaNoIrqBuffer[PhysicalHwUnitId][Channel] & DmaBufferMask);
+            }
+            else
+            {
+                AdcResult = (uint16) (pGroupPtr->pResultsBufferPtr[Group][Channel] & DmaBufferMask);
+            }
+        }
+        else
+#endif /* ADC_DMA_SUPPORTED */
+        {
+            AdcResult = Adc_Ip_GetConvData(PhysicalHwUnitId, Channel);
+            /* Assumption: the width of the register is less than 16 */
+            AdcResult = AdcResult << (NumsBitShift);
+        }
+#if (ADC_ENABLE_LIMIT_CHECK == STD_OFF)
+        (*pFlag) = TRUE;
+#else
+        if (
+            (TRUE == pGroupPtr->bAdcGroupLimitcheck)
+#if (ADC_SETCHANNEL_API == STD_ON)
+            || (TRUE == Adc_aRuntimeGroupChannel[Group].bAdcRuntimeGroupLimitcheck)
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+        )
+        {
+#if (ADC_SETCHANNEL_API == STD_ON)
+            ChIndex = Adc_aRuntimeGroupChannel[Group].pChannel[Channel];
+#else
+            ChIndex = pGroupPtr->pAssignment[Channel];
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+            (*pFlag) =  Adc_Ipw_CheckConversionValuesInRange(AdcResult, LogicalHwUnitId, ChIndex, u32CoreId);
+            if (FALSE == (*pFlag))
+            {
+                /* SWS_Adc_00448, SWS_Adc_00449, SWS_Adc_00450 */
+                Adc_aGroupStatus[Group].bLimitCheckFailed = TRUE;
+                ReadGroupRet = (Std_ReturnType)E_NOT_OK;
+                bWriteFlag = FALSE;
+            }
+            else
+            {
+                Adc_aGroupStatus[Group].bLimitCheckFailed = FALSE;
+            }
+        }
+        if (TRUE == bWriteFlag)
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_OFF */
+        {
+            pDataPtr[Channel] = AdcResult;
+        }
+    }
+    return ReadGroupRet;
+}
+
+/**
+* @brief          This function reads the converted data for the requested group without interrupt.
+* @details        Reads the converted data for the requested group.
+*
+* @param[in]      Group           The group number.
+* @param[in]      pDataPtr        Pointer to a buffer which will be filled by the conversion results.
+* @param[in]      pFlag           Pointer to limit check flag
+* @param[in]      u32CoreId       Current CoreID.
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+* @retval         E_OK            In case of successful read of the converted data.
+* @retval         E_NOT_OK        In case of an ongoing conversion.
+*/
+static inline Std_ReturnType Adc_Ipw_ReadGroupNoInt
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+)
+{
+    Adc_ChannelIndexType ChannelCount;
+    boolean ValidConversion = TRUE;
+    Std_ReturnType ReadGroupRet = (Std_ReturnType) E_OK;
+    const Adc_HwUnitType LogicalHwUnitId = pGroupPtr->AdcLogicalUnitId;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[LogicalHwUnitId];
+#if ((ADC_SETCHANNEL_API == STD_ON) || defined(ADC_DMA_SUPPORTED))
+    const Adc_GroupType Group = pGroupPtr->GroupId;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) || defined(ADC_DMA_SUPPORTED) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    ChannelCount = pGroupPtr->AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    /* Checking conversion is completed (valid) for all channels by check COCO bit in SC1n.
+     If all COCO bits are set, it means that all the conversions in the group have completed.
+     In case of DMA Transfering, just make sure that the result of last conversion was available
+     by checking value of u16DmaNoIrqBuffer (not equal default init value ADC_IPW_INVALID_DATA_RESULT_DMA)
+     because when DMA copied data from Rn to internal buffer then COCO bit is cleared.*/
+#ifdef ADC_DMA_SUPPORTED
+    if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId]) && (pGroupPtr->u8AdcWithoutDma == FALSE))
+    {
+        if((uint8)STD_OFF == pGroupPtr->u8AdcExtDMAChanEnable)
+        {
+            if(ADC_IPW_INVALID_DATA_RESULT_DMA == u16DmaNoIrqBuffer[PhysicalHwUnitId][(ChannelCount - 1U)])
+            {
+                ValidConversion = FALSE;
+            }
+        }
+        else
+        {
+            if(ADC_IPW_INVALID_DATA_RESULT_DMA == pGroupPtr->pResultsBufferPtr[Group][ChannelCount - 1U])
+            {
+                ValidConversion = FALSE;
+            }
+        }
+    }
+    else
+#endif /* ADC_DMA_SUPPORTED */
+    {
+        ValidConversion = Adc_Ipw_CheckValidConversion(PhysicalHwUnitId, 0U, ChannelCount);
+    }
+
+    /* All results are valid, so all conversions from the group have been completed */
+    if (ValidConversion)
+    {
+        ReadGroupRet = Adc_Ipw_ReadGroupConvData(pGroupPtr, pDataPtr, pFlag, u32CoreId);
+        
+#ifdef ADC_DMA_SUPPORTED
+        if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId]) && (pGroupPtr->u8AdcWithoutDma == FALSE))
+        {
+            if((uint8)STD_OFF == pGroupPtr->u8AdcExtDMAChanEnable)
+            {
+                /* Because all conversions were completed so need to reset last buffer to invalid value before starting next conversion */
+                u16DmaNoIrqBuffer[PhysicalHwUnitId][(ChannelCount - 1U)] = ADC_IPW_INVALID_DATA_RESULT_DMA;
+            }
+            else
+            {
+                pGroupPtr->pResultsBufferPtr[Group][(ChannelCount - 1U)] = ADC_IPW_INVALID_DATA_RESULT_DMA;
+            }
+        }
+#endif /* ADC_DMA_SUPPORTED */
+    }
+    else
+    {
+        ReadGroupRet = (Std_ReturnType)E_NOT_OK;
+    }
+
+    return ReadGroupRet;
+}
+
+static inline void Adc_Ipw_WriteDataBuffer
+(
+    const Adc_GroupType Group,
+    Adc_ValueGroupType * pDataPtr,
+    uint32 u32CoreId
+)
+{
+    uint8 Index;
+    uint16 ResultOffset;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+#ifdef ADC_DMA_SUPPORTED
+    const Adc_HwUnitType LogicalHwUnitId = GroupPtr->AdcLogicalUnitId;
+    /* When DMA is used, the masking result is required according to safety analysis. Interrupt was done by Adc_Ip_GetConvData. */
+    uint16 DmaBufferMask = Adc_Ipw_GetAdcDataMask(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId]->Resolution);
+#endif /* ADC_DMA_SUPPORTED */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    const Adc_ChannelIndexType ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    const Adc_ChannelIndexType ChannelCount = GroupPtr->AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    Adc_ValueGroupType * pResultPtr = NULL_PTR;
+    Adc_StreamNumSampleType ResultIndex = 0U;
+
+    /* Get index of last completed sample */
+    ResultIndex = Adc_aGroupStatus[Group].ResultIndex - (Adc_StreamNumSampleType)1U;
+    if ((Adc_StreamNumSampleType)0U == Adc_aGroupStatus[Group].ResultIndex)
+    {
+        ResultIndex = GroupPtr->NumSamples - (Adc_StreamNumSampleType)1U;
+    }
+
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    /* Get the result buffer pointer */
+    if (FALSE == GroupPtr->bStreamResultGroupMultiSets)
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+    {
+        pResultPtr = (Adc_ValueGroupType *)(&(GroupPtr->pResultsBufferPtr[Group][ResultIndex]));
+        ResultOffset = GroupPtr->NumSamples;
+
+        /* Copy results of last conversion from streaming buffer to internal buffer */
+        for (Index = 0U; Index < ChannelCount; Index++)
+        {
+#ifdef ADC_DMA_SUPPORTED
+            if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId])
+            {
+                pDataPtr[Index] = (Adc_ValueGroupType)((*pResultPtr) & DmaBufferMask);
+            }
+            else
+#endif /* ADC_DMA_SUPPORTED */
+            {
+                pDataPtr[Index] = (*pResultPtr);
+            }
+            pResultPtr = &(pResultPtr[ResultOffset]);
+        }
+    }
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    else
+    {
+        pResultPtr = (Adc_ValueGroupType *)(&(GroupPtr->pResultsBufferPtr[Group][ResultIndex * ChannelCount]));
+
+        /* Copy results of last conversion from streaming buffer to internal buffer */
+        for (Index = 0U; Index < ChannelCount; Index++)
+        {
+#ifdef ADC_DMA_SUPPORTED
+            if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId])
+            {
+                pDataPtr[Index] = (Adc_ValueGroupType)(pResultPtr[Index] & DmaBufferMask);
+            }
+            else
+#endif /* ADC_DMA_SUPPORTED */
+            {
+                pDataPtr[Index] = pResultPtr[Index];
+            }
+        }
+    }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+}
+#endif /* (ADC_READ_GROUP_API == STD_ON) */
+
+/**
+* @brief            Configure PDB channels
+* @details          This function configures PDB channels
+*
+* @param[in]      Unit              Adc Logical Unit Id
+* @param[in]      Group             Group number
+* @param[in]      GroupPtr          Group config pointer
+* @param[in]      NumChannel        Number of channels used for this conversion
+*
+* @return       void
+*/
+static inline uint8 Adc_Ipw_ConfigurePdbChannels
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint8 NumChannel
+)
+{
+    uint8 PdbIndex;
+    uint8 PreTriggerCtr;
+    uint8 ChUsed;
+    uint8 LeftChannel = NumChannel;
+    uint8 PdbChannelUsed = (uint8)ADC_IPW_PDB_CHANNELS_USED(NumChannel);
+    uint16 PdbDelay;
+    const uint16 * GroupDelay = NULL_PTR;
+    uint16 CurrentCh = Adc_aGroupStatus[Group].CurrentChannel;
+    Pdb_Adc_Ip_PretriggersConfigType PdbPretriggsConfig;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[0U]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+    Adc_HwUnitType LogicalHwUnitId = GroupPtr->AdcLogicalUnitId;
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    uint32 TempMask = Adc_aRuntimeGroupChannel[Group].u32Mask;
+    /* Get delay configuration of each pre-trigger at runtime */
+    GroupDelay = Adc_aRuntimeGroupChannel[Group].pu16Delays;
+#else
+    /* Follow user configuration */
+    GroupDelay = GroupPtr->pAdcIpwGroupConfig->pDelay;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    /* Configure PDB channels */
+    for (PdbIndex = 0U; PdbIndex < PdbChannelUsed; PdbIndex++)
+    {
+        /* Get channels used depending on number of pre-triggers per PDB channel */
+        ChUsed = ADC_IPW_NUM_CHANNELS_USED(LeftChannel);
+
+        /* If group channel delay, not bypass mode */
+        if ((GroupPtr->pAdcIpwGroupConfig->AdcGroupEnableChannelDelays == TRUE)
+#if (ADC_SETCHANNEL_API == STD_ON)
+                && (GroupDelay != NULL_PTR)
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+           )
+        {
+            /* If Back to Back mode is disabled, enable and configure delays for all channels */
+            if (GroupPtr->pAdcIpwGroupConfig->AdcGroupEnableBackToBack == FALSE)
+            {
+                PdbPretriggsConfig.EnableDelayMask = (uint8) ADC_IPW_PDB_PRETRIGG_MASK(ChUsed);
+                for (PreTriggerCtr = 0U; PreTriggerCtr < ChUsed; PreTriggerCtr++)
+                {
+#if (ADC_SETCHANNEL_API == STD_ON)
+                    if ((uint32)1U == (TempMask & (uint32)1U))
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+                    {
+                        Pdb_Adc_Ip_SetAdcPretriggerDelayValue(PhysicalHwUnitId, PdbIndex, PreTriggerCtr, GroupDelay[CurrentCh + PreTriggerCtr]);
+                    }
+#if (ADC_SETCHANNEL_API == STD_ON)
+                    TempMask = TempMask >> (uint32)1U;
+                    if ((uint32)0U == TempMask)
+                    {
+                        break;
+                    }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+                }
+            }
+            else
+            {
+                /* Beginning part (8 ADC channels) of group will be configured in PDB channel 0 */
+                if (PdbIndex == 0U)
+                {
+                    PdbPretriggsConfig.EnableDelayMask = 1U;
+                    /* First pre-trigger need to be configured as delay, others will be in back to back mode */
+                    PdbDelay = GroupDelay[0U];
+                    Pdb_Adc_Ip_SetAdcPretriggerDelayValue(PhysicalHwUnitId, PdbIndex, 0U, PdbDelay);
+                }
+                else
+                {
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+                    if (FALSE == Adc_pCfgPtr[0U]->pAdcIpwConfig->apPdbConfig[LogicalHwUnitId]->InterChannelBackToBackEnable)
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+                    {
+                        /* The other parts will be configured in following PDB channels */
+                        PdbPretriggsConfig.EnableDelayMask = 1U;
+                        PdbDelay = (GroupPtr->pAdcIpwGroupConfig->PdbDelay)*PdbIndex;
+                        Pdb_Adc_Ip_SetAdcPretriggerDelayValue(PhysicalHwUnitId, PdbIndex, 0U, PdbDelay);
+                    }
+                }
+            }
+        }
+        else    /* Back-to-back mode only */
+        {
+            if (PdbIndex == 0U)
+            {
+                /* Configure the delay for the second PDB in case of only back to back used */
+                /* The first PDB channel, pre-trigger 0 also need to use channel delay (TOS bit = 1) in order to work with continuous PDB mode */
+                PdbPretriggsConfig.EnableDelayMask = 1U;
+                Pdb_Adc_Ip_SetAdcPretriggerDelayValue(PhysicalHwUnitId, PdbIndex, 0U, 0U);
+            }
+            else
+            {
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+                if (FALSE == Adc_pCfgPtr[0U]->pAdcIpwConfig->apPdbConfig[LogicalHwUnitId]->InterChannelBackToBackEnable)
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+                {
+                    PdbPretriggsConfig.EnableDelayMask = 1U;
+                    PdbDelay = (GroupPtr->pAdcIpwGroupConfig->PdbDelay)*PdbIndex;
+                    Pdb_Adc_Ip_SetAdcPretriggerDelayValue(PhysicalHwUnitId, PdbIndex, 0U, PdbDelay);
+                }
+            }
+        }
+
+        Pdb_Adc_Ip_LoadRegValues(PhysicalHwUnitId);
+
+        /* Update status channel for configuring PDB channel in next loop */
+        LeftChannel -= ChUsed;
+        CurrentCh += ChUsed;
+
+
+        /* Use back to back mode for all channels but using delay in pre-trigger 0 */
+        if (GroupPtr->pAdcIpwGroupConfig->AdcGroupEnableBackToBack == TRUE)
+        {
+            if (PdbIndex == 0U)
+            {
+                PdbPretriggsConfig.BackToBackEnableMask = (uint8) ADC_IPW_PDB_PRETRIGG_MASK(ChUsed) - 1U;
+            }
+            else
+            {
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+                if (TRUE == Adc_pCfgPtr[0U]->pAdcIpwConfig->apPdbConfig[LogicalHwUnitId]->InterChannelBackToBackEnable)
+                {
+                    PdbPretriggsConfig.BackToBackEnableMask = (uint8) ADC_IPW_PDB_PRETRIGG_MASK(ChUsed);
+                }
+                else
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+                {
+                    PdbPretriggsConfig.BackToBackEnableMask = (uint8) ADC_IPW_PDB_PRETRIGG_MASK(ChUsed) - 1U;
+                }
+            }
+        }
+        else
+        {
+            PdbPretriggsConfig.BackToBackEnableMask = 0u;
+        }
+        PdbPretriggsConfig.EnableMask = (uint8) ADC_IPW_PDB_PRETRIGG_MASK(ChUsed);
+        /* Update configuration to CHnC1 register for pre-trigger */
+        Pdb_Adc_Ip_ConfigAdcPretriggers(PhysicalHwUnitId, PdbIndex, &PdbPretriggsConfig);
+    }
+    return PdbIndex;
+}
+
+/**
+* @brief            Configure PDB IPL module for each conversion
+* @details          This function configures PDB IPL module for each conversion
+*
+* @param[in]      Unit              Adc Logical Unit Id
+* @param[in]      Group             Group number
+* @param[in]      GroupPtr          Group config pointer
+* @param[in]      Trigger           PDB trigger
+* @param[in]      NumChannel        Number of channels used for this conversion
+*
+* @return       void
+*
+* @pre  ADC Unit is in stand by, there is no ongoing conversion.
+*/
+static inline void Adc_Ipw_ConfigurePdbConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel
+)
+{
+    uint8 PdbIndex;
+    uint8 PdbChannelUsed;
+    uint16 PdbPeriod = 0U;
+    const uint16 * GroupDelay = NULL_PTR;
+    Pdb_Adc_Ip_PretriggersConfigType PdbPretriggsConfig;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[0U]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+
+    /* Calculate number of PDB channels depending on the ADC channels used */
+    /* Note that 1 PDB channel triggers to 8 ADC channels */
+    PdbChannelUsed = (uint8)ADC_IPW_PDB_CHANNELS_USED(NumChannel);
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Get delay configuration of each pre-trigger */
+    /* At runtime */
+    GroupDelay = Adc_aRuntimeGroupChannel[Group].pu16Delays;
+#else
+    /* Follow user configuration */
+    GroupDelay = GroupPtr->pAdcIpwGroupConfig->pDelay;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    /* Select the input trigger source for PDB */
+    Pdb_Adc_Ip_Enable(PhysicalHwUnitId);
+    Pdb_Adc_Ip_SetTriggerInput(PhysicalHwUnitId, Trigger);
+
+    PdbIndex = Adc_Ipw_ConfigurePdbChannels(Unit, Group, GroupPtr, NumChannel);
+
+#if (defined(ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED) || (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS))
+    /* If the continuous group is configured without interrupts or Optimize DMA Streaming Groups
+        then PDB need to be configured as continuous mode.*/
+    if ((ADC_CONV_MODE_CONTINUOUS == GroupPtr->eMode) &&
+        (((uint8)STD_ON == GroupPtr->u8AdcWithoutInterrupt)
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+        || (TRUE == GroupPtr->bAdcOptimizeDmaStream)
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+        ))
+    {
+        PdbPeriod = GroupPtr->pAdcIpwGroupConfig->PdbPeriod;
+    }
+    else
+#endif /* ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED */
+    {
+        /* If group channel delay, not bypass mode */
+        if (GroupPtr->pAdcIpwGroupConfig->AdcGroupEnableChannelDelays == TRUE)
+        {
+            if (GroupPtr->pAdcIpwGroupConfig->AdcGroupEnableBackToBack == FALSE)
+            {
+                /* If delay mode for all pre-triggers, PDB period equals to value of last pre-trigger delay (i.e longest delay) */
+                PdbPeriod = GroupDelay[(Adc_aGroupStatus[Group].CurrentChannel + NumChannel) - 1U];
+            }
+            else
+            {
+                /* Period will be calculated depending on user configuration in back to back mode */
+                PdbPeriod = GroupDelay[0U] + (uint16)((GroupPtr->pAdcIpwGroupConfig->PdbDelay)*((uint16)PdbChannelUsed - 1U));
+            }
+        }
+        else
+        {
+            /* All pre-trigger configured as user PdbDelay */
+            PdbPeriod = (GroupPtr->pAdcIpwGroupConfig->PdbDelay)*((uint16)PdbChannelUsed - 1U);
+        }
+    }
+
+    /* Configure the period of counter */
+    Pdb_Adc_Ip_SetModulus(PhysicalHwUnitId, PdbPeriod);
+
+    /* Load the configuration */
+    Pdb_Adc_Ip_LoadRegValues(PhysicalHwUnitId);
+
+    PdbPretriggsConfig.EnableMask = 0u;
+    PdbPretriggsConfig.EnableDelayMask = 0u;
+    PdbPretriggsConfig.BackToBackEnableMask = 0u;
+
+    /* Disable others PDB channels to avoid errors when PDB trigger the disabled channels */
+    for (; PdbIndex < PDB_CH_COUNT; PdbIndex++)
+    {
+        Pdb_Adc_Ip_ConfigAdcPretriggers(PhysicalHwUnitId, PdbIndex, &PdbPretriggsConfig);
+    }
+
+    /* Update current channel */
+    Adc_aGroupStatus[Group].CurrentChannel += NumChannel;
+
+    /* ADC356, ADC357 */
+    /* Start software trigger */
+    /* If trigger is not software trigger, hardware trigger or external trigger will be used */
+    if (PDB_ADC_IP_SOFTWARE_TRIGGER == Trigger)
+    {
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+        if (TRUE == GroupPtr->bAdcOptimizeDmaStream)
+        {
+            /* PDB operation in Continuous mode for software */
+            Pdb_Adc_Ip_SetContinuousMode(PhysicalHwUnitId, TRUE);
+        }
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+
+        Pdb_Adc_Ip_SwTrigger(PhysicalHwUnitId);
+    }
+#if (ADC_SETCHANNEL_API == STD_OFF)
+    /* Avoid compiler warning */
+    (void)Group;
+#endif /* (ADC_SETCHANNEL_API == STD_OFF) */
+}
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/**
+* @brief          This function stops the current conversion.
+* @details        This function stops the current conversion and checks if the hardware has responded to the command.
+*
+* @param[in]      Unit           The hardware Unit.
+* @param[in]      Group          The group id.
+* @param[in]      u32Timeout     Time for conversion is aborted.
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+* @retval         E_OK            If the conversion has stopped as expected.
+* @retval         E_NOT_OK        In case of timeout while waiting for adc hardware to stop a conversion.
+*
+*/
+static inline Std_ReturnType Adc_Ipw_StopConversionCheckTimeout
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Std_ReturnType Status = E_OK;
+    Adc_Ip_StatusType IPLStatus;
+    uint8 ChIndex;
+
+    /* Stop PDB hardware trigger unit */
+    Pdb_Adc_Ip_DisableAndClearPdb(PhysicalHwUnitId);
+
+    /* Check if ADC is in continuous mode */
+    if(((uint8)STD_ON == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcWithoutInterrupt) && (ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode))
+    {
+        /* Set to Oneshot mode */
+        Adc_Ip_SetContinuousMode(PhysicalHwUnitId, FALSE);
+    }
+
+    /* Disable all channels */
+    for (ChIndex = 0U; ChIndex < Adc_aUnitStatus[Unit].u8Sc1Used; ChIndex++)
+    {
+        /* Stop conversion in SC1n register and wait until conversion is aborted. */
+        /* Because some channels in chain are not converted yet */
+        IPLStatus = Adc_Ip_SetDisabledChannel(PhysicalHwUnitId, ChIndex, TRUE);
+        if (IPLStatus == ADC_IP_STATUS_TIMEOUT)
+        {
+            Status = E_NOT_OK;
+        }
+    }
+    return Status;
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief        This function configures the DMA Transfer involved in the ADC conversion process.
+* @details      This function configures the Dma Ip to Transfer data from Data Register to Result Buffer.
+*               It should be called with the ADC Unit on standby (no ADC interrupt event allowed
+*               because its code is not protected by critical regions) - no conversions is ongoing.
+*
+* @param[in]    Unit        The Adc Logical Unit Id.
+* @param[in]    u32CoreId   Current CoreID
+*
+* @return       void
+*
+* @pre  ADC Unit is in stand by, there is no ongoing conversion.
+*/
+void Adc_Ipw_StartDmaOperation
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint8 u8NumChannel,
+    uint32 u32CoreId
+)
+{
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    /* This variable is used to make a temp DMA transfer by itself. */
+    static uint8 Adc_Ipw_u8DmaDraftBuffer;
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+    uint8 u8Index;
+    uint8 LocTransferListNumElems;
+    Adc_ChannelIndexType ChannelCount;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group]; /* Group index in each partition */
+    const uint32 u32AdcDmaLogicChId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_DmaChannel[Unit];
+    const Adc_GroupConfigurationType * pGroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]); /* Pointer to AdcGroup */
+    Adc_StreamNumSampleType u8GroupNumSample = pGroupPtr->NumSamples;
+    Dma_Ip_LogicChannelTransferListType LocTransferList[16U];
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    Dma_Ip_LogicChannelTransferListType CountingDmaLocTransferList[16U];
+    const uint32 u32AdcCountingDmaLogicChId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_CountingDmaChannel[Unit];
+#endif /* (ADC_OPTIMIZE_DMA_STREAMING_GROUPS = STD_ON) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)*/
+
+    /* Get number of channel in the Group */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    ChannelCount = pGroupPtr->AssignedChannelCount;
+#endif
+
+    if ((uint8)STD_ON == pGroupPtr->u8AdcWithoutInterrupt)
+    {
+        /* Reset u16DmaNoIrqBuffer to invalid value when enabling the group, because this buffer is used by ReadGroup to check that conversions are complete and results available */
+        for (u8Index = 0; u8Index < ADC_MAX_CHANNEL_PER_HW_UNIT; u8Index++)
+        {
+            u16DmaNoIrqBuffer[PhysicalHwUnitId][u8Index] = ADC_IPW_INVALID_DATA_RESULT_DMA;
+        }
+    }
+
+    /* Prepare for Software TCD Configuration:
+    0. Source Address (SADDR): Starting address of the first ADC channel
+    1. Source Transfer Size (SSIZE): Number of bytes to read each time.
+    2. Source Address Offset (SOFF): [Datasize * 2 (4 bytes)] (offset to starting address of next ADC channel data field)
+    3. Destination Address (DADDR): Starting address of group user buffer
+    4. Destination Transfer Size (DSIZE): [Datasize (or 1 or DMA_SIZE_2BYTES)] (write 2 bytes/Doffset).
+    5. Destination Address Offset (DOFF): [No.Samples * Datasize (=2bytes)] (next channel of sample)
+    6. Minor Loop Size (NBYTES): [No.Channels * Datasize (=2bytes)] (number of bytes to transfer per service request).
+    7. Major Loop Count (CITER): [No.Channels] (Number of minor loop in a major loop)
+    8. Start to Transfer by Software (TCDn_CSR.START). TODO can be removed?
+    9. Enable Major Interrupt (INTMAJOR): Enable Interrupt If Major count complete.
+    10. Enable Half Major Interrupt (INTHALF): Enable Interrupt If Major Counter Half-complete
+    11. Disable Automatic Hardware Request (DREQ): clear automatically the ERQ bit.
+    12. The Source Signed Last Address Adjustment: will adjust source address after major is done.
+         [-(No.Channels * u32soff)] (<two's complement> number of bytes that source address offsets in a loop)
+    13. Destination Signed Last Address Adjustment: will adjust destination address after major is done.
+    */
+    LocTransferList[0].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    LocTransferList[0].Value = Adc_Ip_GetDataAddress(PhysicalHwUnitId, 0U);
+    LocTransferList[1].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    LocTransferList[1].Value = (uint32)1U; /* 2 Bytes */
+    LocTransferList[2].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    LocTransferList[2].Value = (uint32)4U; /* offset to starting address of next data field */
+    LocTransferList[3].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    LocTransferList[3].Value = (uint32)(&(pGroupPtr->pResultsBufferPtr[Group][0U]));
+    LocTransferList[4].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    LocTransferList[4].Value = (uint32)1U; /* 2 Bytes */
+    LocTransferList[5].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    LocTransferList[5].Value = (uint32)u8GroupNumSample << 1U;
+    LocTransferList[6].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    LocTransferList[6].Value = (uint32)2U;
+    LocTransferList[7].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    LocTransferList[7].Value = (uint32)u8NumChannel;
+    LocTransferList[8].Param = DMA_IP_CH_SET_CONTROL_SOFTWARE_REQUEST;
+    LocTransferList[8].Value = FALSE;
+    LocTransferList[9].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+    LocTransferList[9].Value = TRUE;
+    LocTransferList[10].Param = DMA_IP_CH_SET_CONTROL_EN_HALF_MAJOR_INTERRUPT;
+    LocTransferList[10].Value = FALSE;
+    LocTransferList[11].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    LocTransferList[11].Value = TRUE;
+    LocTransferList[12].Param = DMA_IP_CH_SET_SOURCE_SIGNED_LAST_ADDR_ADJ;
+    LocTransferList[12].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)u8NumChannel << 2UL);
+    LocTransferList[13].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
+    if (u8GroupNumSample == 1U)
+    {
+        LocTransferList[13].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)u8NumChannel << 1U); /* multiply by 2U because this is the ADC result data size */
+    }
+    else
+    {
+        LocTransferList[13].Value = ADC_IPW_GET_COMPLEMENT_OF_2((((uint32)(ChannelCount) * (uint32)u8GroupNumSample) - 1UL) << 1U); /* multiply by 2U because this is the ADC result data size */
+    }
+
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    if ((TRUE == pGroupPtr->bStreamResultGroupMultiSets) && (u8GroupNumSample > 1U))
+    {
+        LocTransferList[5].Value = (uint32)2U;
+        LocTransferList[13].Value = (uint32)0U;
+    }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+
+    LocTransferListNumElems = 14U;
+    if((uint8)STD_ON == pGroupPtr->u8AdcWithoutInterrupt)
+    {
+        LocTransferList[3].Value = (uint32)(&(u16DmaNoIrqBuffer[PhysicalHwUnitId][0])); /* Transfer results in internal buffer first */
+        LocTransferList[9].Value = FALSE;
+        LocTransferList[11].Value = FALSE;
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        if (pGroupPtr->eAccessMode == ADC_ACCESS_MODE_STREAMING)
+        {
+            /* Link to counting DMA channel to transfer results from u16DmaNoIrqBuffer to buffer setup by user.
+            Use extra transfer via u16DmaNoIrqBuffer to allow usage of ReadGroup */
+            LocTransferList[13].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)u8NumChannel << 1U); /* multiply by 2U because this is the ADC result data size */
+            LocTransferList[14].Param = DMA_IP_CH_SET_MAJORLOOP_EN_LINK;
+            LocTransferList[14].Value = TRUE;
+            LocTransferList[15].Param = DMA_IP_CH_SET_MAJORLOOP_LOGIC_LINK_CH;
+            LocTransferList[15].Value = u32AdcCountingDmaLogicChId;
+            LocTransferListNumElems = 16U;
+        }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+    }
+
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    /* Setchannel/EnableChannel/DisableChannel cannot be used with optimize DMA streaming groups multiple group channels */
+    if (TRUE == pGroupPtr->bAdcOptimizeDmaStream)
+    {
+        if (1U == ChannelCount)
+        {
+            LocTransferList[2].Value = (uint32)0U; /* Group has only one channel */
+
+            LocTransferList[5].Value = (uint32)(2U);
+            LocTransferList[7].Value = (uint32)u8GroupNumSample;
+            LocTransferList[10].Value = (pGroupPtr->bHalfInterrupt == TRUE) ? 1UL : 0UL;
+            LocTransferList[12].Value = (uint32)0U;
+            /* Each minor loop, DMA will transfer 2 bytes. So adjustment value will be [(-((No.Sample) * u32doff))]
+            (<two's complement> number of bytes that destination address offsets in a major loop) */
+            LocTransferList[13].Value = ADC_IPW_GET_COMPLEMENT_OF_2(((uint32)(u8GroupNumSample) * LocTransferList[5].Value));
+
+        }
+        else
+        {
+            /* Configuration of counter DMA channel for optimize DMA streaming groups:
+            * DMA_IP_CH_SET_SOURCE_ADDRESS      = [Starting address of a dummy byte] with offset = 0
+            * DMA_IP_CH_SET_DESTINATION_ADDRESS = [Starting address of a dummy byte] with offset = 0
+            * DMA_IP_CH_SET_MINORLOOP_SIZE      = [1] (total transferred bytes of 1 loop)
+            * DMA_IP_CH_SET_MAJORLOOP_COUNT (citer/biter) = [No.Samples] (The DMA acts as an hardware counter. Number of samples imply citer/biter count)
+            * Control register flags = [  DMA_IP_CH_SET_CONTROL_EN_HALF_MAJOR_INTERRUPT=1 (if Adc Group Enable Half Interrupt is enabled)
+            *                           | DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT=1
+            *                           | DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST=1]
+            * <other field> = 0 */
+            CountingDmaLocTransferList[0].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+            CountingDmaLocTransferList[0].Value = (uint32)&Adc_Ipw_u8DmaDraftBuffer;
+            CountingDmaLocTransferList[1].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+            CountingDmaLocTransferList[1].Value = 0U; /* 1 Bytes */
+            CountingDmaLocTransferList[2].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+            CountingDmaLocTransferList[2].Value = 0U;
+            CountingDmaLocTransferList[3].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+            CountingDmaLocTransferList[3].Value = (uint32)&Adc_Ipw_u8DmaDraftBuffer;
+            CountingDmaLocTransferList[4].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+            CountingDmaLocTransferList[4].Value = 0U; /* 1 Bytes */
+            CountingDmaLocTransferList[5].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+            CountingDmaLocTransferList[5].Value = 0U;
+            CountingDmaLocTransferList[6].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+            CountingDmaLocTransferList[6].Value = 1U;
+            CountingDmaLocTransferList[7].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+            CountingDmaLocTransferList[7].Value = (uint32)u8GroupNumSample;
+            CountingDmaLocTransferList[8].Param = DMA_IP_CH_SET_CONTROL_SOFTWARE_REQUEST;
+            CountingDmaLocTransferList[8].Value = FALSE;
+            CountingDmaLocTransferList[9].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+            CountingDmaLocTransferList[9].Value = TRUE;
+            CountingDmaLocTransferList[10].Param = DMA_IP_CH_SET_CONTROL_EN_HALF_MAJOR_INTERRUPT;
+            CountingDmaLocTransferList[10].Value = (pGroupPtr->bHalfInterrupt == TRUE) ? 1UL : 0UL;
+
+            (void)Dma_Ip_SetLogicChannelTransferList(u32AdcCountingDmaLogicChId, CountingDmaLocTransferList, 11U);
+
+            /* Configuration of transferring data DMA channel for optimize DMA streaming groups
+            Disable Major and Half-Major Interrupt for main DMA Channel. Interrupt was handled by Counting Dma Channel */
+            LocTransferList[9].Value = FALSE;
+            LocTransferList[10].Value = FALSE;
+            /* Need to keep receiving DMA request from ADC */
+            LocTransferList[11].Value = FALSE;
+
+            /* Link to counting DMA channel to count number of completed sample and use DMA callback to update group status. */
+            LocTransferList[14].Param = DMA_IP_CH_SET_MAJORLOOP_EN_LINK;
+            LocTransferList[14].Value = TRUE;
+            LocTransferList[15].Param = DMA_IP_CH_SET_MAJORLOOP_LOGIC_LINK_CH;
+            LocTransferList[15].Value = (uint32)u32AdcCountingDmaLogicChId;
+            LocTransferListNumElems = 16U;
+        }
+    }
+#endif /*  (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    /* Note that AdcEnableOptimizeDmaStreamingGroups cannot be enabled simultaneously with Without Interrupts.
+    So the CountingDmaLocTransferList configured for bAdcOptimizeDmaStream is NOT overwritten by these. */
+    /* Configure Counting DMA channel to transfer results from u16DmaNoIrqBuffer to buffer setup by user.
+     Streaming results reorder feature must be enabled to allow running without interrupts for groups with ChannelCount > 1,
+     and also ChannelCount == 1, but for the latter reorder is not necessary to be enabled at group level. */
+    if ((pGroupPtr->eAccessMode == ADC_ACCESS_MODE_STREAMING) && ((uint8)STD_ON == pGroupPtr->u8AdcWithoutInterrupt))
+    {
+        if ((ChannelCount == 1U) || ((ChannelCount > 1U) && (pGroupPtr->bStreamResultGroupMultiSets == TRUE))) /* TODO: rename bStreamResultGroupMultiSets to reorder */
+        {
+            CountingDmaLocTransferList[0].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+            CountingDmaLocTransferList[0].Value = (uint32)&(u16DmaNoIrqBuffer[PhysicalHwUnitId][0U]);
+            CountingDmaLocTransferList[1].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+            CountingDmaLocTransferList[1].Value = (uint32)1U; /* 2 Bytes */
+            CountingDmaLocTransferList[2].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+            CountingDmaLocTransferList[2].Value = (uint32)2U; /* move by 2 Bytes */
+            CountingDmaLocTransferList[3].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+            CountingDmaLocTransferList[3].Value = (uint32) & (pGroupPtr->pResultsBufferPtr[Group][0U]);
+            CountingDmaLocTransferList[4].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+            CountingDmaLocTransferList[4].Value = (uint32)1U; /* 2 Bytes */
+            CountingDmaLocTransferList[5].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+            CountingDmaLocTransferList[5].Value = (uint32)2U; /* 2U because this is ADC result register size. TODO: replace with CDATA SIZE */
+            CountingDmaLocTransferList[6].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+            CountingDmaLocTransferList[6].Value = (uint32)u8NumChannel << 1UL; /* multiply by 2U because this is the ADC result data size */
+            CountingDmaLocTransferList[7].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+            CountingDmaLocTransferList[7].Value = (uint32)u8GroupNumSample;
+            CountingDmaLocTransferList[8].Param = DMA_IP_CH_SET_MINORLOOP_EN_SRC_OFFSET;
+            CountingDmaLocTransferList[8].Value = TRUE;
+            CountingDmaLocTransferList[9].Param = DMA_IP_CH_SET_MINORLOOP_SIGNED_OFFSET;
+            CountingDmaLocTransferList[9].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)u8NumChannel << 1UL); /* multiply by 4U because 2 is the ADC result register size and 2 are additional info u16DmaNoIrqBuffer because needed for ReadGroup*/
+            CountingDmaLocTransferList[10].Param = DMA_IP_CH_SET_CONTROL_SOFTWARE_REQUEST;
+            CountingDmaLocTransferList[10].Value = FALSE;
+            CountingDmaLocTransferList[11].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+            CountingDmaLocTransferList[11].Value = FALSE;
+            CountingDmaLocTransferList[12].Param = DMA_IP_CH_SET_CONTROL_EN_HALF_MAJOR_INTERRUPT;
+            CountingDmaLocTransferList[12].Value = FALSE;
+            CountingDmaLocTransferList[13].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+            CountingDmaLocTransferList[13].Value = TRUE;
+            CountingDmaLocTransferList[14].Param = DMA_IP_CH_SET_SOURCE_SIGNED_LAST_ADDR_ADJ;
+            CountingDmaLocTransferList[14].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)u8NumChannel << 1UL); /* multiply by 4U because 2 is the ADC result register size and 2 are additional info u16DmaNoIrqBuffer because needed for ReadGroup*/
+            CountingDmaLocTransferList[15].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
+            CountingDmaLocTransferList[15].Value = ADC_IPW_GET_COMPLEMENT_OF_2(((uint32)u8NumChannel * (uint32)u8GroupNumSample) << 1U); /* multiply by 2U because this is the ADC result data size */
+
+            (void)Dma_Ip_SetLogicChannelTransferList(u32AdcCountingDmaLogicChId, CountingDmaLocTransferList, 16U);
+            /* Enable Hardware Request for Counting Dma channel */
+            (void)Dma_Ip_SetLogicChannelCommand(u32AdcCountingDmaLogicChId, DMA_IP_CH_SET_HARDWARE_REQUEST);
+        }
+    }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+
+    (void)Dma_Ip_SetLogicChannelTransferList(u32AdcDmaLogicChId, LocTransferList, LocTransferListNumElems);
+    /* Enable Hardware Request for Dma */
+    (void)Dma_Ip_SetLogicChannelCommand(u32AdcDmaLogicChId, DMA_IP_CH_SET_HARDWARE_REQUEST);
+
+}
+#endif /* ADC_DMA_SUPPORTED */
+
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+/**
+* @brief          This function performs general configurations to the adc hardware prior to starting a conversion.
+* @details        This function performs general configurations to the adc hardware prior to starting a conversion.
+*
+* @param[in]      Unit                  The Adc Logical Unit Id.
+* @param[in]      GroupPtr              The pointer to the group configuration structure.
+* @param[in]      u32CoreId             Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_PrepareGroupStart
+(
+    Adc_HwUnitType Unit,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint32 u32CoreId
+)
+{
+    Adc_ConversionTimeType ConvTime;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    if (ADC_NORMAL == Adc_eClockMode[u32CoreId])
+    {
+        if ((uint8)STD_ON == GroupPtr->pAdcIpwGroupConfig->u8GroupAvgEnable)
+        {
+            Adc_Ip_SetAveraging(PhysicalHwUnitId, TRUE, GroupPtr->pAdcIpwGroupConfig->GroupAvgSelect);
+        }
+    }
+    else
+    {
+        if ((uint8)STD_ON == GroupPtr->pAdcIpwGroupConfig->u8GroupAvgEnableAlternate)
+        {
+            Adc_Ip_SetAveraging(PhysicalHwUnitId, TRUE, GroupPtr->pAdcIpwGroupConfig->GroupAvgSelectAlternate);
+        }
+    }
+#else /* (ADC_DUAL_CLOCK_MODE == STD_OFF) */
+    {
+        if ((uint8)STD_ON == GroupPtr->pAdcIpwGroupConfig->u8GroupAvgEnable)
+        {
+            Adc_Ip_SetAveraging(PhysicalHwUnitId, TRUE, GroupPtr->pAdcIpwGroupConfig->GroupAvgSelect);
+        }
+    }
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+    /* Get the configuration value of conversion time */
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    if (ADC_NORMAL == Adc_eClockMode[u32CoreId])
+    {
+        ConvTime = GroupPtr->pAdcIpwGroupConfig->ConvTime;
+    }
+    else
+    {
+        ConvTime = GroupPtr->pAdcIpwGroupConfig->AlternateConvTime;
+    }
+#else /* (ADC_DUAL_CLOCK_MODE == STD_OFF) */
+    ConvTime = GroupPtr->pAdcIpwGroupConfig->ConvTime;
+    (void)u32CoreId;
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+    /*  Program Conversion Time */
+    Adc_Ip_SetSampleTime(PhysicalHwUnitId, ConvTime);
+}
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+#if ((defined(ADC_UNIT_0_ISR_USED)) || (defined(ADC_UNIT_1_ISR_USED)) || \
+     (defined(ADC_DMA_SUPPORTED)) || (ADC_READ_GROUP_API == STD_ON) \
+    )
+/**
+* @brief          This function calculates number of bits that need to shift according the alignment configuration
+* @details        This function calculates number of bits that need to shift according the alignment configuration
+*
+* @param[in]      Resolution    Adc resolution enum value
+*
+* @return         uint8        Number of bits shift
+*/
+uint8 Adc_Ipw_CalculateNumsBitShift
+(
+    Adc_Ip_ResolutionType Resolution
+)
+{
+    uint8 NumsBitShift;
+#if (ADC_RESULT_ALIGNMENT == ADC_ALIGN_LEFT)
+    switch (Resolution)
+    {
+        case ADC_IP_RESOLUTION_8BIT:
+            NumsBitShift = 8u;
+            break;
+        case ADC_IP_RESOLUTION_10BIT:
+            NumsBitShift = 6u;
+            break;
+        case ADC_IP_RESOLUTION_12BIT:
+            NumsBitShift = 4u;
+            break;
+        default:
+            /* Default is 12 bits */
+            NumsBitShift = 4u;
+            break;
+    }
+#else
+    NumsBitShift = 0u;
+    (void) Resolution;
+#endif /* (ADC_RESULT_ALIGNMENT == ADC_ALIGN_LEFT) */
+
+    return NumsBitShift;
+}
+#endif  /* (defined(ADC_UNIT_0_ISR_USED) || ... */
+
+/**
+* @brief            Configure channels of a group
+* @details          This function configure channels of a group
+*                   if number of channels in group excess maximum channels allowed for a conversion,
+*                   a part of channels of group (= max allowed channels) will be configured in start conversion in the first time.
+*                   the remaining channels of group will be seperated into other parts which are configured and converted in group interrupt.
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Group number
+* @param[in]      Trigger       PDB trigger
+* @param[in]      NumChannel    Number of channels to be configured
+*
+* @return       void
+*
+* @pre  ADC Unit is in stand by, there is no ongoing conversion.
+*/
+void Adc_Ipw_ConfigureConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel,
+    uint32 u32CoreId
+)
+{
+    uint8 ChIndex;
+    Adc_ChannelIndexType CurrentChannel;
+    Adc_Ip_ChanConfigType ChannelConfig;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Adc_Ip_InputChannelType Channel;
+    const Adc_GroupDefType * ChannelsDefinition = NULL_PTR;
+
+    /* Next channel will be converted */
+    CurrentChannel = Adc_aGroupStatus[Group].CurrentChannel;
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Get status of channels are changed at runtime */
+    uint32 TempMask = Adc_aRuntimeGroupChannel[Group].u32Mask;
+#endif /* ADC_SETCHANNEL_API */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Get configured channels */
+    /* At runtime */
+    ChannelsDefinition = Adc_aRuntimeGroupChannel[Group].pChannel;
+#else
+    /* Pre-configuration */
+    ChannelsDefinition = GroupPtr->pAssignment;
+#endif /* ADC_SETCHANNEL_API */
+
+    /* Configure channels from current to (last channel - 1) */
+    for (ChIndex = 0U; ChIndex < (NumChannel - 1U); ChIndex++)
+    {
+        /* Physical channel ID */
+        Channel = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[Unit]->ChannelConfigs[ChannelsDefinition[(CurrentChannel + ChIndex)]].Channel;
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+        /* Channel was changed? */
+        if (1U == (TempMask & 1U))
+#endif /* ADC_SETCHANNEL_API */
+        {
+            /* Configure all channels except the last one with interrupts disabled */
+            ChannelConfig.ChnIdx = ChIndex;
+            ChannelConfig.Channel = Channel;
+            ChannelConfig.InterruptEnable = FALSE;
+            Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+        }
+#if (ADC_SETCHANNEL_API == STD_ON)
+        TempMask = TempMask >> (uint32)1U;
+        /* There are no channels changed then break out the loop */
+        if (0U == TempMask)
+        {
+            break;
+        }
+#endif /* ADC_SETCHANNEL_API */
+    }
+
+    /* Configure last channel */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Last channel was changed? */
+    if (1U == (TempMask & 1U))
+#endif
+    {
+        /* Get channel ID */
+        Channel = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[Unit]->ChannelConfigs[ChannelsDefinition[(CurrentChannel + ChIndex)]].Channel;
+        ChannelConfig.ChnIdx = ChIndex;
+        ChannelConfig.Channel = Channel;
+        /* In case of group is configured with interrupt, the complete int bit of the last channel must be enabled */
+        if ((uint8)STD_OFF == GroupPtr->u8AdcWithoutInterrupt)
+        {
+            ChannelConfig.InterruptEnable = TRUE;
+        }
+        else
+        {
+            ChannelConfig.InterruptEnable = FALSE;
+        }
+
+        /* Configure last channel */
+        Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+    }
+
+#if ((ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) || (ADC_SETCHANNEL_API == STD_ON))
+    for (ChIndex = NumChannel; ChIndex < ADC_MAX_CHAN_COUNT; ChIndex++)
+    {
+        /* Disable other channels by configuring them as disabled */
+        ChannelConfig.ChnIdx = ChIndex;
+        ChannelConfig.Channel = ADC_IP_INPUTCHAN_DISABLED;
+        ChannelConfig.InterruptEnable = FALSE;
+        Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+    }
+#endif /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) || (ADC_SETCHANNEL_API == STD_ON) */
+
+     /* Save the Sc1Used register equal the number of channels configured */
+     Adc_aUnitStatus[Unit].u8Sc1Used = NumChannel;
+     /* Start software trigger through PDB or enable PDB hardware trigger */
+     Adc_Ipw_ConfigurePdbConversion(Unit, Group, GroupPtr, Trigger, NumChannel);
+}
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief        This function configures IPL for DMA Transfer.
+* @details      This function configures IP layer in order to Transfer data from Data Register to Result Buffer.
+*
+* @param[in]    Unit        Adc Logical Unit Id
+* @param[in]    Group       Group number
+* @param[in]    Trigger     PDB trigger
+* @param[in]    NumChannel  number of conversion channels
+*
+* @return       void
+*
+* @pre  ADC Unit is in stand by, there is no ongoing conversion.
+*/
+/* TODO: Merged this to Adc_Ipw_ConfigureConversion for Optimization */
+void Adc_Ipw_ConfigureDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_HwTriggerTimerType Trigger,
+    uint8 NumChannel
+)
+{
+    uint8 ChIndex;
+    Adc_ChannelIndexType CurrentChannel;
+    Adc_Ip_ChanConfigType ChannelConfig;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[0U]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[0U]->pGroups[GroupIndex]);
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[0U]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Adc_Ip_InputChannelType Channel;
+    const Adc_GroupDefType * ChannelsDefinition = NULL_PTR;
+
+    /* Next channel will be converted */
+    CurrentChannel = Adc_aGroupStatus[Group].CurrentChannel;
+
+    /* Ensure that PDB does not run when ADC configured */
+    Pdb_Adc_Ip_Disable(PhysicalHwUnitId);
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Get configured channels */
+    /* At runtime */
+    ChannelsDefinition = Adc_aRuntimeGroupChannel[Group].pChannel;
+#else
+    /* Pre-configuration */
+    ChannelsDefinition = GroupPtr->pAssignment;
+#endif /* ADC_SETCHANNEL_API */
+
+    /* Because the transfer type is DMA so need to disable interrupt for all used channels */
+    /* Interrupt will be generated through DMA Callback */
+    for (ChIndex = 0U; ChIndex < NumChannel; ChIndex++)
+    {
+        /* Logical channel ID */
+        Channel = Adc_pCfgPtr[0U]->pAdcIpwConfig->apAdcConfig[Unit]->ChannelConfigs[ChannelsDefinition[(CurrentChannel + ChIndex)]].Channel;
+        /* Disable other channels by configuring them as disabled */
+        ChannelConfig.ChnIdx = ChIndex;
+        ChannelConfig.Channel = Channel;
+        ChannelConfig.InterruptEnable = FALSE;
+        Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+    }
+
+#if ((ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) || (ADC_SETCHANNEL_API == STD_ON))
+    for (ChIndex = NumChannel; ChIndex < ADC_MAX_CHAN_COUNT; ChIndex++)
+    {
+        /* Disable other channels by configuring them as disabled */
+        ChannelConfig.ChnIdx = ChIndex;
+        ChannelConfig.Channel = ADC_IP_INPUTCHAN_DISABLED;
+        ChannelConfig.InterruptEnable = FALSE;
+        Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+    }
+#endif /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) || (ADC_SETCHANNEL_API == STD_ON) */
+
+    /* Save the Sc1Used register equal the number of channels configured */
+     Adc_aUnitStatus[Unit].u8Sc1Used = NumChannel;
+
+    /* Start software trigger through PDB or enable PDB hardware trigger */
+     Adc_Ipw_ConfigurePdbConversion(Unit, Group, GroupPtr, Trigger, NumChannel);
+}
+#endif /* ADC_DMA_SUPPORTED */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+/**
+* @brief          This function starts a hardware trigger conversion.
+* @details        This function starts a hardware trigger conversion.
+*
+* @param[in]      Unit        Adc Logical Unit Id
+* @param[in]      Group       Group number
+*
+* @return         void
+*/
+void Adc_Ipw_StartHwTrigConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    uint8 NumChannel;
+#ifdef ADC_DMA_SUPPORTED
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+#endif /* ADC_DMA_SUPPORTED */
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+
+    /* Calculate the number of channels for current configuration */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    NumChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(Adc_aRuntimeGroupChannel[Group].ChannelCount);
+#else
+    NumChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(GroupPtr->AssignedChannelCount);
+#endif
+
+    /* If it is the first group, u8Sc1Used is assigned as the number channels of group */
+    if(0U == Adc_aUnitStatus[Unit].u8Sc1Used)
+    {
+        Adc_aUnitStatus[Unit].u8Sc1Used = NumChannel;
+    }
+    Adc_aGroupStatus[Group].CurrentChannel = 0U;
+
+#ifdef ADC_DMA_SUPPORTED
+    /* Not required to check u8AdcWithoutDma == FALSE, because u8AdcWithoutDma is only supported for SW normal triggered which cannot be HW Trigger when DMA transfer selected for HW unit */
+    if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit]))
+    {
+        /* Enable DMA for ADC Module */
+        Adc_Ip_EnableDma(PhysicalHwUnitId);
+
+        if((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+        {
+            /* Configure for DMA transfer */
+            Adc_Ipw_StartDmaOperation(Unit, Group, NumChannel, u32CoreId);
+        }
+
+        /* Setting for ADC in case of DMA transfer was selected, in the first time DMA should not be re-configured */
+        Adc_Ipw_ConfigureDmaConversion(Unit, Group, GroupPtr->HwTriggerSource, NumChannel);
+    }
+    else
+#endif /* ADC_DMA_SUPPORTED */
+    {
+        /* Setting for ADC hardware in case of DMA transfer was not selected */
+        Adc_Ipw_ConfigureConversion(Unit, Group, GroupPtr->HwTriggerSource, NumChannel, u32CoreId);
+    }
+#if (ADC_SETCHANNEL_API == STD_ON)
+    if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+    {
+        /* Roll back to the first sample */
+        Adc_aGroupStatus[Group].ResultIndex = 0U;
+        /* Reset the update status */
+        Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated =  FALSE;
+    }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+
+/**
+* @brief          This function initializes the ADC hardware modules, triggering units and the ADC driver.
+* @details        This function initializes the ADC hardware module, and the ADC driver.
+*
+* @param[in]      pIpwCfg           Configuration data pointer.
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType    E_OK or E_NOT_OK.
+* @retval         E_OK              If Power up/Power down activities return status as expected.
+* @retval         E_NOT_OK          If Power up/Power down activities couldn't return status as expected.
+*
+*/
+Std_ReturnType Adc_Ipw_Init
+(
+    const Adc_Ipw_Config * pIpwCfg,
+    const uint32 u32CoreId
+)
+{
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_HwUnitType PhysicalHwUnitId = 0U;
+    Std_ReturnType TimeOutStatus = (Std_ReturnType)E_OK;
+
+    for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS_CFG; LogicalHwUnitId++)
+    {
+        if (pIpwCfg->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            PhysicalHwUnitId = pIpwCfg->aAdcPhysicalId[LogicalHwUnitId];
+            Adc_Ip_Init(PhysicalHwUnitId, pIpwCfg->apAdcConfig[LogicalHwUnitId]);
+            Pdb_Adc_Ip_Init(PhysicalHwUnitId, pIpwCfg->apPdbConfig[LogicalHwUnitId]);
+        }
+    }
+
+    (void)u32CoreId;
+
+    return TimeOutStatus;
+}
+
+#if (ADC_DEINIT_API == STD_ON)
+/**
+* @brief          This function de-initializes the ADC driver, and the ADC hardware.
+* @details        This function de-initializes the ADC driver, and ensures that the ADC hardware
+*                 will be in the power on after reset state.
+*
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType    E_OK or E_NOT_OK.
+* @retval         E_OK              If the operation completed successfully.
+* @retval         E_NOT_OK          In case of timeout while waiting for adc hardware operations.
+*
+*/
+Std_ReturnType Adc_Ipw_DeInit
+(
+    uint32 u32CoreId
+)
+{
+    Adc_HwUnitType PhysicalHwUnitId = 0U;
+    Adc_HwUnitType LogicalHwUnitId = 0U;
+    Adc_GroupType GroupId = 0U;
+    Adc_GroupType GroupIter = 0U;
+    Std_ReturnType ReturnStatus = E_OK;
+
+    for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS_CFG; LogicalHwUnitId++)
+    {
+        if (Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[LogicalHwUnitId];
+            Adc_Ip_DeInit(PhysicalHwUnitId);
+            Pdb_Adc_Ip_DeInit(PhysicalHwUnitId);
+        }
+    }
+
+    for (GroupIter = 0U; GroupIter < (Adc_GroupType)Adc_pCfgPtr[u32CoreId]->GroupCount; GroupIter++)
+    {
+        GroupId = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIter].GroupId;
+        Adc_pCfgPtr[u32CoreId]->pGroups[GroupIter].pResultsBufferPtr[GroupId] = NULL_PTR;
+#if (ADC_SETCHANNEL_API == STD_ON)
+        Adc_aRuntimeGroupChannel[GroupId].pChannel = NULL_PTR;
+        Adc_aRuntimeGroupChannel[GroupId].ChannelCount = 0U;
+        Adc_aRuntimeGroupChannel[GroupId].bRuntimeUpdated = FALSE;
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        Adc_aRuntimeGroupChannel[GroupId].bAdcRuntimeGroupLimitcheck = FALSE;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#endif
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+        Adc_aGroupStatus[GroupId].eNotification = ADC_NOTIFICATION_DISABLED;
+#endif  /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+    }
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    Adc_eClockMode[u32CoreId] = ADC_NORMAL;
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+    return ReturnStatus;
+}
+#endif /* (ADC_DEINIT_API == STD_ON) */
+
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/**
+* @brief          This function starts the conversion on the specified hardware Unit.
+* @details        This function starts the conversion on the specified hardware Unit.
+*                 This function should be called with the ADC Unit on standby (no ADC interruptions
+*                 allowed because its code is not protected by critical regions) - no conversions must
+*                 be running.
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*
+*/
+void Adc_Ipw_StartNormalConversion
+(
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType Group = Adc_aUnitStatus[Unit].SwNormalQueue[0U]; /* Active group in the Queue */
+#if (defined(ADC_DMA_SUPPORTED) || defined(ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED) || \
+    (ADC_ENABLE_LIMIT_CHECK == STD_ON) || (ADC_SETCHANNEL_API == STD_OFF) || \
+    (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF))
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group]; /* Group index in each partition */
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]); /* Pointer to AdcGroup */
+#endif /* (defined(ADC_DMA_SUPPORTED) ||... */
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    uint8 NumChannel;
+    uint8 ChIndex;
+#ifdef ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED
+    boolean PdbMode;
+#endif /* ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED */
+
+    /* Do nothing if there is no request available in queue */
+    if ((Adc_aUnitStatus[Unit].SwNormalQueueIndex != (Adc_QueueIndexType)0U)
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        || ((Adc_aGroupStatus[Group].bLimitCheckFailed == FALSE) && (GroupPtr->eMode == ADC_CONV_MODE_ONESHOT))
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+        )
+    {
+
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+        /* Configure group params (e.g. conversion time) if needed before starting conversion */
+        Adc_Ipw_PrepareGroupStart(Unit, GroupPtr, u32CoreId);
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+
+        /* Reset to start conversion from channel logical index 0 */
+        Adc_aGroupStatus[Group].CurrentChannel = 0U;
+
+        /* Calculate the number of channels for current configuration */
+#if (ADC_SETCHANNEL_API == STD_ON)
+        /* Channel enabled at runtime */
+        NumChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(Adc_aRuntimeGroupChannel[Group].ChannelCount);
+#else
+        /* Channel enabled from initialzing */
+        NumChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(GroupPtr->AssignedChannelCount);
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+        /* Update u8Sc1Used for the first time */
+        if (0U == Adc_aUnitStatus[Unit].u8Sc1Used)
+        {
+            Adc_aUnitStatus[Unit].u8Sc1Used = NumChannel;
+        }
+
+#ifdef ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED
+        PdbMode = (ADC_CONV_MODE_CONTINUOUS == GroupPtr->eMode) && ((uint8)STD_ON == GroupPtr->u8AdcWithoutInterrupt);
+        Pdb_Adc_Ip_SetContinuousMode(PhysicalHwUnitId, PdbMode);
+#endif /* ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED */
+
+#ifdef ADC_DMA_SUPPORTED
+        if ((ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit]) && (GroupPtr->u8AdcWithoutDma == FALSE))
+        {
+            /* Enable DMA for ADC module */
+            Adc_Ip_EnableDma(PhysicalHwUnitId);
+            if ((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+            {
+                /* Setting for DMA transfer */
+                Adc_Ipw_StartDmaOperation(Unit, Group, NumChannel, u32CoreId);
+            }
+            /* Setting for Adc in case of DMA transfer was selected, in the first time DMA should not be re-configured */
+            Adc_Ipw_ConfigureDmaConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel);
+        }
+        else
+#endif /* ADC_DMA_SUPPORTED */
+        {
+            /* Clear all of COCO flag by reading Rn registers */
+            for (ChIndex = 0U; ChIndex < Adc_aUnitStatus[Unit].u8Sc1Used; ChIndex++)
+            {
+                (void)Adc_Ip_GetConvData(PhysicalHwUnitId, ChIndex);
+            }
+            Adc_Ip_SetTriggerMode(PhysicalHwUnitId, ADC_IP_TRIGGER_HARDWARE);
+
+            /* Update group configuration to registers and start conversion */
+            Adc_Ipw_ConfigureConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel, u32CoreId);
+        }
+#if (ADC_SETCHANNEL_API == STD_ON)
+        if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+        {
+            /* Reset the update status */
+            Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated =  FALSE;
+        }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    }
+}
+
+/**
+* @brief          This function stops the current conversion of a group.
+* @details        This function stops the current conversion of a group.
+*
+* @param[in]      Unit              Adc Logical Unit Id
+* @param[in]      Group             The group id
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType    E_OK or E_NOT_OK.
+* @retval         E_OK              If the conversion has stopped as expected.
+* @retval         E_NOT_OK          In case of timeout while waiting for adc hardware to stop a conversion.
+*
+*/
+Std_ReturnType Adc_Ipw_StopCurrentConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+#if ((ADC_BYPASS_ABORT_CHAIN_CHECK == STD_ON) || defined(ADC_DMA_SUPPORTED))
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#endif /* (ADC_BYPASS_ABORT_CHAIN_CHECK == STD_ON) */
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    uint8 ChIndex;
+
+    /* Disable Adc hardware unit and clear all of COCO flag by reading Rn register */
+    for (ChIndex = 0U; ChIndex < Adc_aUnitStatus[Unit].u8Sc1Used; ChIndex++)
+    {
+        (void) Adc_Ip_SetDisabledChannel(PhysicalHwUnitId, ChIndex, FALSE);
+
+        /* Make a dummy read to clear COCO flag */
+        (void) Adc_Ip_GetConvData(PhysicalHwUnitId, ChIndex);
+    }
+#ifdef ADC_DMA_SUPPORTED
+    if (((uint8)ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit]) && (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcWithoutDma == FALSE))
+    {
+        /* Disable DMA for Adc */
+        Adc_Ip_DisableDma(PhysicalHwUnitId);
+        if((uint8)STD_OFF == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcExtDMAChanEnable)
+        {
+            /* Disable DMA hardware request */
+            (void)Dma_Ip_SetLogicChannelCommand(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_DmaChannel[Unit], DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+        }
+    }
+#endif /* ADC_DMA_SUPPORTED */
+    /* Reset current channel status to 0 */
+    Adc_aGroupStatus[Group].CurrentChannel = 0U;
+
+    /* Stop the conversion and abort the current group conversion */
+#if (ADC_BYPASS_ABORT_CHAIN_CHECK == STD_ON)
+    if ((uint8)STD_OFF == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcWithoutInterrupt)
+    {
+        Status = Adc_Ipw_StopConversionCheckTimeout(Unit, Group, u32CoreId);
+    }
+#ifdef ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED
+    else
+    {
+        /* If group is continuous and configured without interrupts, clear the CONTINUOUS bit */
+        if (ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode)
+        {
+            Pdb_Adc_Ip_DisableAndClearPdb(PhysicalHwUnitId);
+        }
+    }
+#endif /* ADC_CONTINUOUS_NO_INTERRUPT_SUPPORTED */
+#else
+    Status = Adc_Ipw_StopConversionCheckTimeout(Unit, Group, u32CoreId);
+#endif /* (ADC_BYPASS_ABORT_CHAIN_CHECK == STD_OFF) */
+
+    return Status;
+}
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+/**
+* @brief          This function enables the hardware triggers for the specified group.
+* @details        This function enables the hardware triggers for the specified group.
+*
+* @param[in]      Group             The group for which the hardware triggers will be enabled
+* @param[in]      Unit              Adc Logical Unit Id
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType    E_OK or E_NOT_OK.
+* @retval         E_OK              If there is no running conversion.
+* @retval         E_NOT_OK          If there is a running conversion.
+*
+*/
+Std_ReturnType Adc_Ipw_EnableHardwareTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    uint8 ChIndex;
+
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Adc_aGroupStatus[Group].ResultIndex = 0U;
+
+    /* Clear all of COCO flag by reading Rn registers */
+    for(ChIndex = 0U; ChIndex < Adc_aUnitStatus[Unit].u8Sc1Used; ChIndex++)
+    {
+        (void)Adc_Ip_GetConvData(PhysicalHwUnitId, ChIndex);
+    }
+
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    /* Configure group params (e.g. conversion time) if needed before starting conversion */
+    Adc_Ipw_PrepareGroupStart(Unit, GroupPtr, u32CoreId);
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+
+    Adc_Ipw_StartHwTrigConversion(Unit, Group, u32CoreId);
+
+    return E_OK;
+}
+
+/**
+* @brief          This function disables the hardware triggers for the specified group.
+* @details        This function disables the hardware triggers for the specified group.
+*
+* @param[in]      Group           The group for which the hardware triggers will be enabled
+* @param[in]      Unit            Adc Logical Unit Id
+*
+* @return         void
+*
+*/
+void Adc_Ipw_DisableHardwareTrigger
+(
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+    uint8 ChIndex;
+    Adc_Ip_ChanConfigType ChannelConfig;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+#ifdef ADC_DMA_SUPPORTED
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#endif /* ADC_DMA_SUPPORTED */
+
+    (void) Group;
+
+#ifdef ADC_DMA_SUPPORTED
+    /* Not required to check u8AdcWithoutDma == FALSE, because u8AdcWithoutDma is only supported for SW normal triggered which cannot be HW Trigger when DMA transfer selected for HW unit */
+    if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+    {
+        if ((uint8)STD_ON == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[Unit])
+        {
+            /* Disable DMA for ADC Module */
+            Adc_Ip_DisableDma(PhysicalHwUnitId);
+            if((uint8)STD_OFF == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcExtDMAChanEnable)
+            {
+                /* Disable Hardware Request for Dma */
+                (void)Dma_Ip_SetLogicChannelCommand(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_DmaChannel[Unit], DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+            }
+        }
+    }
+#endif /* ADC_DMA_SUPPORTED */
+
+    /* Disable Pdb hardware unit */
+    Pdb_Adc_Ip_DisableAndClearPdb(PhysicalHwUnitId);
+
+    /* Disable Adc hardware unit */
+    for(ChIndex = 0U; ChIndex < Adc_aUnitStatus[Unit].u8Sc1Used; ChIndex++)
+    {
+        ChannelConfig.ChnIdx = ChIndex;
+        ChannelConfig.Channel = ADC_IP_INPUTCHAN_DISABLED;
+        ChannelConfig.InterruptEnable = FALSE;
+        Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+    }
+}
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+
+/**
+* @brief          Small function that validates current conversion.
+* @details        Validates current conversion.
+*
+* @param[in]      PhysicalHwUnitId  The group number.
+* @param[in]      StartIndex        Starting index of the check.
+* @param[in]      EndIndex          End index of the check.
+* @return         boolean  TRUE or FALSE.
+* @retval         TRUE              Valid conversion.
+* @retval         FALSE             Invalid conversion.
+*
+*/
+boolean Adc_Ipw_CheckValidConversion
+(
+    Adc_HwUnitType PhysicalHwUnitId,
+    Adc_ChannelIndexType StartIndex,
+    Adc_ChannelIndexType EndIndex
+)
+{
+    Adc_ChannelIndexType Index;
+    boolean ValidConversion = TRUE;
+
+    for (Index = StartIndex; Index < EndIndex; Index++)
+    {
+        ValidConversion = Adc_Ip_GetConvCompleteFlag(PhysicalHwUnitId, Index - StartIndex);
+        if (!ValidConversion)
+        {
+            break;
+        }
+    }
+
+    return ValidConversion;
+}
+
+#if (ADC_READ_GROUP_API == STD_ON)
+/**
+* @brief          This function reads the converted data for the requested group.
+* @details        Reads the converted data for the requested group.
+*
+* @param[in]      Group           The group number.
+* @param[in]      pDataPtr        Pointer to a buffer which will be filled by the
+*                                 conversion results.
+* @param[in]      pFlag
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+* @retval         E_OK            In case of successful read of the converted data.
+* @retval         E_NOT_OK        In case of an ongoing conversion.
+*
+*/
+Std_ReturnType Adc_Ipw_ReadGroup
+(
+    const Adc_GroupType Group,
+    Adc_ValueGroupType * pDataPtr,
+    boolean * pFlag,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ReadGroupRet = (Std_ReturnType)E_OK;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+    const Adc_HwUnitType LogicalHwUnitId = GroupPtr->AdcLogicalUnitId;
+
+    /* If the group is configured for without interrupts */
+    if ((uint8)STD_ON == GroupPtr->u8AdcWithoutInterrupt)
+    {
+        /* Return error if group is not at the first of queue */
+        if (ADC_CONV_TYPE_NORMAL == GroupPtr->eType)
+        {
+            if (ADC_TRIGG_SRC_SW == GroupPtr->eTriggerSource)
+            {
+                if (Group != Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[0U])
+                {
+                    ReadGroupRet = (Std_ReturnType)E_NOT_OK;
+                }
+            }
+#if (STD_ON == ADC_HW_TRIGGER_API)
+            else
+            {
+                if (Group != Adc_aUnitStatus[LogicalHwUnitId].OngoingHwGroup)
+                {
+                    ReadGroupRet = (Std_ReturnType)E_NOT_OK;
+                }
+            }
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+        }
+        if ((Std_ReturnType)E_OK == ReadGroupRet)
+        {
+            ReadGroupRet = Adc_Ipw_ReadGroupNoInt(GroupPtr, pDataPtr, pFlag, u32CoreId);
+        }
+    }
+    else  /* If the group is configured with interrupts */
+    {
+        if (ADC_BUSY == Adc_aGroupStatus[Group].eConversion)
+        {
+            ReadGroupRet = (Std_ReturnType)E_NOT_OK;
+        }
+
+        if ((Std_ReturnType)E_OK == ReadGroupRet)
+        {
+            Adc_Ipw_WriteDataBuffer(Group, pDataPtr, u32CoreId);
+        }
+    }
+
+    return ReadGroupRet;
+}
+#endif /* (ADC_READ_GROUP_API == STD_ON) */
+
+
+#if (ADC_ENABLE_READ_RAW_DATA_API == STD_ON)
+/**
+* @brief          This function reads the converted data for the requested channel.
+* @details        Reads the converted data for the requested channel.
+* @note           The function might return E_NOT_OK in case the number of configured
+*                 channels are greater than number of SC1 register (ADC_MAX_CHAN_COUNT)
+*
+* @param[in]      Unit            Adc Logical Unit Id
+* @param[in]      Channel         Channel to be read
+* @param[in]      u32CoreId       Current CoreID
+* @param[out]     Result          Conversion result
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+* @retval         E_OK            In case of successful read of the converted data.
+* @retval         E_NOT_OK        In case of not found channel.
+*
+*/
+Std_ReturnType Adc_Ipw_GetConvData
+(
+    Adc_HwUnitType Unit,
+    Adc_ChannelType Channel,
+    uint32 u32CoreId,
+    uint16 * Result
+)
+{
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Std_ReturnType Status = (Std_ReturnType)E_NOT_OK;
+
+    *Result = 0u;
+
+    if (ADC_IP_STATUS_SUCCESS == Adc_Ip_GetChanData(PhysicalHwUnitId, (Adc_Ip_InputChannelType)Channel, Result))
+    {
+        Status = (Std_ReturnType)E_OK;
+    }
+
+    return Status;
+}
+#endif /* (ADC_ENABLE_READ_RAW_DATA_API == STD_ON) */
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+/**
+* @brief          Checks if conversion values are in the configured range.
+* @details        Return true if conversion values are in the configured range, otherwise false.
+*
+* @param[in]      Value                 Adc conversion value.
+*                 LogicalHwUnitId       Adc Hardware Unit.
+*                 Index                 Adc channel index assigned to a group.
+*                 u32CoreId             Current CoreID
+*
+* @return         boolean               Conversion value in range flag.
+* @retval         TRUE                  If conversion values are in the configured range.
+* @retval         FALSE                 If conversion values are not in the configured range.
+*
+* @pre            Driver must be initialized.
+*/
+boolean Adc_Ipw_CheckConversionValuesInRange
+(
+    Adc_ValueGroupType Value,
+    Adc_HwUnitType LogicalHwUnitId,
+    Adc_ChannelType ChannelIndex,
+    uint32 u32CoreId
+)
+{
+    const Adc_ChannelLimitCheckingType * const pChannelLimitCheckingCfg = &(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->ChannelLimitCheckingConfigs[LogicalHwUnitId][ChannelIndex]);
+    boolean bValInRange = FALSE;
+    const Adc_ChannelRangeSelectType eChRange = pChannelLimitCheckingCfg->eChannelRange;
+    const Adc_ValueGroupType LowLimit = pChannelLimitCheckingCfg->ChannelLowLimit;
+    const Adc_ValueGroupType HighLimit = pChannelLimitCheckingCfg->ChannelHighLimit;
+
+    switch (eChRange)
+    {
+        /* Complete range - independent from channel limit settings. */
+        case ADC_RANGE_ALWAYS:
+        {
+            bValInRange = TRUE;
+            break;
+        }
+        /* Range between low limit and high limit - high limit value included. */
+        case ADC_RANGE_BETWEEN:
+        {
+            if ((Value > LowLimit) && (Value <= HighLimit))
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Range above high limit or below low limit - low limit value included. */
+        case ADC_RANGE_NOT_BETWEEN:
+        {
+            if ((Value > HighLimit) || (Value <= LowLimit))
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Range below high limit -high limit value included. */
+        case ADC_RANGE_NOT_OVER_HIGH:
+        {
+            if (Value <= HighLimit)
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Range above low limit. */
+        case ADC_RANGE_NOT_UNDER_LOW:
+        {
+            if (Value > LowLimit)
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Range above high limit. */
+        case ADC_RANGE_OVER_HIGH:
+        {
+            if (Value > HighLimit)
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Range below low limit - low limit value included. */
+        case ADC_RANGE_UNDER_LOW:
+        {
+            if (Value <= LowLimit)
+            {
+                bValInRange = TRUE;
+            }
+            break;
+        }
+        /* Unexpected value */
+        default:
+        {
+            ; /* no-op */
+            break;
+        }
+    }
+    return bValInRange;
+}
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief          This function sets the Prescaler value only when ADC is in power down mode.
+* @details        Set prescaler clock divider only in power down mode.
+*
+* @param[in]      Prescaler         ADC_NORMAL, ADC_ALTERNATE.
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType  E_OK or E_NOT_OK.
+* @retval         E_OK            In case of successful set hw unit power mode.
+* @retval         E_NOT_OK        In case of unsuccessful set hw unit power mode.
+*
+*/
+Std_ReturnType Adc_Ipw_SetClockMode
+(
+   Adc_SelectPrescalerType Prescaler,
+   uint32 u32CoreId
+)
+{
+    Adc_HwUnitType LogicalHwUnitId = 0U; /* Hardware Unit index */
+    Adc_HwUnitType PhysicalHwUnitId = 0U; /* Hardware Unit index */
+    Adc_Ip_ClockConfigType AdcNormalClockConfig;
+    const Adc_Ip_ConfigType * pAdc;
+
+    for (LogicalHwUnitId = 0U; LogicalHwUnitId < ADC_MAX_HW_UNITS_CFG; LogicalHwUnitId++)
+    {
+        if (Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_HwUnit[LogicalHwUnitId] == (uint8)STD_ON) /* HW unit enabled on current partition */
+        {
+            PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[LogicalHwUnitId];
+            pAdc = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[LogicalHwUnitId];
+            if (Prescaler == ADC_NORMAL)
+            {
+                AdcNormalClockConfig.ClockDivide = pAdc->ClockDivide;
+                AdcNormalClockConfig.InputClock = pAdc->InputClock;
+                AdcNormalClockConfig.SampleTime = pAdc->SampleTime;
+                AdcNormalClockConfig.AvgEn = pAdc->AvgEn;
+                AdcNormalClockConfig.AvgSel = pAdc->AvgSel;
+                Adc_Ip_SetClockMode(PhysicalHwUnitId, &AdcNormalClockConfig);
+            }
+            else
+            {
+                Adc_Ip_SetClockMode(PhysicalHwUnitId, Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcAltClockConfig[LogicalHwUnitId]);
+            }
+        }
+    }
+
+    return E_OK;
+}
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+
+#if (ADC_CALIBRATION == STD_ON)
+void Adc_Ipw_Calibrate
+(
+    Adc_HwUnitType Unit,
+    Adc_CalibrationStatusType * Status,
+    uint32 u32CoreId
+)
+{
+    Adc_Ip_StatusType IpStatus;
+    const Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+
+    Status->Adc_UnitSelfTestStatus = E_OK;
+    IpStatus = Adc_Ip_DoCalibration(PhysicalHwUnitId);
+
+    if (IpStatus != ADC_IP_STATUS_SUCCESS)
+    {
+        Status->Adc_UnitSelfTestStatus = E_NOT_OK;
+#if (ADC_CALSTAT_AVAILABLE == STD_ON)
+        /* TODO: populate Status->Adc_au8Calibrate_Failed_Steps */
+#endif /* (ADC_CALSTAT_AVAILABLE == STD_ON) */
+    }
+}
+#endif /* ADC_CALIBRATION == STD_ON */
+
+/**
+* @brief        This function returns the id of the core from which it is called.
+* @details      This function returns the result of the OsIf_GetCoreID OS function
+*               (which is called in the appropriate context depending on USER MODE)
+*               If the multicore feature is disabled for ADC, this function will return 0.
+*
+* @param[in]    void
+*
+* @return      uint32  the core number.
+*/
+uint32 Adc_GetCoreID(void)
+{
+    return 0UL;
+}
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Adc_Ipw_Irq.c

@@ -0,0 +1,1701 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @internal
+*   @addtogroup adc_ipw Adc Ipw
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external Units
+* 3) internal and external interfaces from this Unit
+==================================================================================================*/
+
+/* TODO: only added for: extern const Adc_ConfigType * Adc_pCfgPtr[ADC_MAX_PARTITIONS]*/
+#include "Adc.h"
+#include "Adc_Ipw.h"
+#include "Adc_Ipw_Irq.h"
+#include "Adc_Ipw_Types.h"
+#include "Mcal.h"
+#include "Det.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_IPW_IRQ_C                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C       4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C       4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_C    0
+#define ADC_SW_MAJOR_VERSION_IPW_IRQ_C               1
+#define ADC_SW_MINOR_VERSION_IPW_IRQ_C               0
+#define ADC_SW_PATCH_VERSION_IPW_IRQ_C               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ipw_Irq.c file and Adc.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_IRQ_C != ADC_VENDOR_ID)
+    #error "Adc_Ipw_Irq.c and Adc.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MINOR_VERSION) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Adc.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_IRQ_C != ADC_SW_MAJOR_VERSION) || \
+     (ADC_SW_MINOR_VERSION_IPW_IRQ_C != ADC_SW_MINOR_VERSION) || \
+     (ADC_SW_PATCH_VERSION_IPW_IRQ_C != ADC_SW_PATCH_VERSION) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Irq.c and Adc.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_IRQ_C != ADC_VENDOR_ID_IPW_H)
+    #error "Adc_Ipw_Irq.c and Adc_Ipw.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_IRQ_C != ADC_SW_MAJOR_VERSION_IPW_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_IRQ_C != ADC_SW_MINOR_VERSION_IPW_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_IRQ_C != ADC_SW_PATCH_VERSION_IPW_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Irq.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_IRQ_C != ADC_VENDOR_ID_IPW_IRQ_H)
+    #error "Adc_Ipw_Irq.c and Adc_Ipw_Irq.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Irq.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw_Irq.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Irq.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_IRQ_C != ADC_SW_MAJOR_VERSION_IPW_IRQ_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_IRQ_C != ADC_SW_MINOR_VERSION_IPW_IRQ_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_IRQ_C != ADC_SW_PATCH_VERSION_IPW_IRQ_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw_Irq.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_IRQ_C != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Ipw_Irq.c and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_IRQ_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Adc_Ipw_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_IRQ_C != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_IRQ_C != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_IRQ_C != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Irq.c and Adc_Ipw_Types.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if source file and Mcal header file are of the same AutoSar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+    (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != MCAL_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Mcal.h are different"
+#endif
+
+/* Check if Adc_Ipw_Irq.c file and Det.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_IRQ_C != DET_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_IRQ_C != DET_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Irq.c and Det.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+/* The macro to calculate the index of the first channel in the previous configuration */
+#define ADC_IPW_PREV_CHANNEL_INDEX(x) ((((x) % ADC_MAX_CHAN_COUNT) == 0U) ? ((x) - ADC_MAX_CHAN_COUNT) : ((Adc_ChannelIndexType)((x)-((x) % ADC_MAX_CHAN_COUNT))))
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+extern Adc_RuntimeGroupChannelType Adc_aRuntimeGroupChannel[ADC_MAX_GROUPS];
+#endif
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+#if ((defined(ADC_UNIT_0_ISR_USED)) || (defined(ADC_UNIT_1_ISR_USED)) || \
+     (defined(ADC_DMA_SUPPORTED)) \
+    )
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+static inline void Adc_Ipw_CallNotification
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* ADC_GRP_NOTIF_CAPABILITY == STD_ON */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+static inline void Adc_Ipw_UpdateQueue
+(
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+);
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+static inline void Adc_Ipw_CallExtraNotification
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+
+static inline Std_ReturnType Adc_Ipw_CheckConversionChannels
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+);
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+static inline void Adc_Ipw_HandleConversionCheckFail
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+static inline void Adc_Ipw_RestartConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+);
+
+static inline void Adc_Ipw_UpdateSoftwareGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+);
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+#ifdef ADC_DMA_SUPPORTED
+static inline void Adc_Ipw_CheckAndUpdateDmaHwGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const uint32 u32AdcDmaLogicChId,
+    uint32 u32CoreId
+);
+#endif /* ADC_DMA_SUPPORTED */
+
+static inline uint32 Adc_Ipw_GetCurrentSampleCount
+(
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+#else
+    Adc_GroupType Group
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+);
+
+static inline void Adc_Ipw_UpdateHardwareGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+);
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+static inline void Adc_Ipw_EndConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    boolean IsSoftwareConversion,
+    uint32 u32CoreId
+);
+
+#ifdef ADC_DMA_SUPPORTED
+static inline void Adc_Ipw_EndDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    boolean IsSoftwareConversion,
+    uint32 u32CoreId
+);
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+static inline void Adc_Ipw_UpdateDmaConfig
+(
+    const Adc_ValueGroupType * DataPtr,
+    const uint32 DmaLogicChId,
+    uint8 NumChannel
+);
+
+static inline void Adc_Ipw_ContinueDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_ChannelIndexType ChannelCount,
+    const uint32 AdcDmaLogicChId,
+    uint32 u32CoreId
+);
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+static inline Std_ReturnType Adc_Ipw_CheckGroupConvResultDma
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    uint32 u32CoreId
+);
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#endif /* ADC_DMA_SUPPORTED */
+
+static inline void Adc_Ipw_ReadData
+(
+    const Adc_GroupConfigurationType * GroupPtr,
+    Adc_ValueGroupType * pResult,
+    const Adc_StreamNumSampleType GroupSamples,
+    const Adc_ChannelIndexType Index,
+    const uint16 ConvResult
+);
+
+static inline void Adc_Ipw_EndConversionNotification
+(
+    const Adc_HwUnitType PhysicalAdcUnit
+);
+#endif  /* (defined(ADC_UNIT_0_ISR_USED) || ... */
+
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#if ((defined(ADC_UNIT_0_ISR_USED)) || (defined(ADC_UNIT_1_ISR_USED)) || \
+     (defined(ADC_DMA_SUPPORTED)))
+
+
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+/**
+* @brief          This function checks and calls group notification
+* @details        This function checks and calls group notification
+*
+* @param[in]      Group             The group to be converted
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         void
+*
+*/
+static inline void Adc_Ipw_CallNotification
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    /* SWS_Adc_00080, SWS_Adc_00083 */
+    if ((ADC_NOTIFICATION_ENABLED == Adc_aGroupStatus[Group].eNotification) && \
+        (NULL_PTR != Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].Notification)
+       )
+    {
+        /* Execute notification function */
+        Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].Notification();
+    }
+}
+#endif /* ADC_GRP_NOTIF_CAPABILITY == STD_ON */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+/**
+* @brief          This function updates queue
+* @details        This function updates queue elements after a conversion
+*                 and start conversion if requests are still available in queue
+*
+* @param[in]      Unit              The ADC hardware unit
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         void
+*
+*/
+static inline void Adc_Ipw_UpdateQueue
+(
+    Adc_HwUnitType Unit,
+    uint32 u32CoreId
+)
+{
+#if (ADC_ENABLE_QUEUING == STD_ON)
+    /* Remove current request element in queue */
+    Adc_RemoveFromQueue(Unit, 0U);
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+    if (Adc_aUnitStatus[Unit].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+    {
+        /* Start conversion if request elements are still available in queue */
+        Adc_Ipw_StartNormalConversion(Unit, u32CoreId);
+    }
+#endif /* (ADC_ENABLE_START_STOP_GROUP_API == STD_ON) */
+#else
+    /* No element will be present in the queue */
+    Adc_aUnitStatus[Unit].SwNormalQueueIndex = (Adc_QueueIndexType)0;
+#endif /* ADC_ENABLE_QUEUING == STD_ON */
+    (void)u32CoreId;
+}
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+/**
+* @brief          This function calls extra notification
+* @details        This function calls extra notification
+*
+* @param[in]      Group         The channel group to be converted
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+* CPR-MCAL-797.adc, SWS_Adc_00140
+*/
+static inline void Adc_Ipw_CallExtraNotification
+(
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+
+    /* Call notification if available */
+    if (Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].ExtraNotification != NULL_PTR)
+    {
+        Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].ExtraNotification();
+    }
+}
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+
+/**
+* @brief          This function checks conversion results
+* @details        This function checks conversion results
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Selected group Id
+* @param[in]      GroupSamples  Number of samples
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*/
+static inline Std_ReturnType Adc_Ipw_CheckConversionChannels
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr; /* Pointer to AdcGroup */
+    Adc_ChannelIndexType CurrentChannel = Adc_aGroupStatus[Group].CurrentChannel;
+    Adc_ChannelIndexType Temp;
+    Adc_ChannelIndexType Index;
+    uint16 ConvResult;
+    Adc_ValueGroupType * ResultIndex = NULL_PTR;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    const uint8 NumsBitShift = Adc_Ipw_CalculateNumsBitShift(Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->apAdcConfig[Unit]->Resolution);
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    Adc_ChannelType HwChannel;
+    boolean bFlag = FALSE;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+    boolean ValidConversion = TRUE;
+
+    /* record the result of the Channel conversion and update group status */
+#if (ADC_SETCHANNEL_API == STD_ON)
+    Index = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    Index = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+
+    if (CurrentChannel <= Index)
+    {
+        /* Calculate the index of the first channel in the previous configuration */
+        Temp = (Adc_ChannelIndexType)ADC_IPW_PREV_CHANNEL_INDEX(CurrentChannel);
+
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        /* Get the result buffer pointer */
+        if (FALSE == GroupPtr->bStreamResultGroupMultiSets)
+        {
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+            ResultIndex = GroupPtr->pResultsBufferPtr[Group] + Adc_aGroupStatus[Group].ResultIndex;
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        }
+        else
+        {
+            ResultIndex = GroupPtr->pResultsBufferPtr[Group] + (Adc_aGroupStatus[Group].ResultIndex * Index);
+        }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+
+        ValidConversion = Adc_Ipw_CheckValidConversion(PhysicalHwUnitId, Temp, CurrentChannel);
+
+        if (ValidConversion)
+        {
+            /* For each of channels in the list of previous configuration, read data and take result into user buffer */
+            for (Index = Temp; Index < CurrentChannel; Index++)
+            {
+                ConvResult = Adc_Ip_GetConvData(PhysicalHwUnitId, Index - Temp);
+                /* Assumption: the width of the register is less than 16 */
+                ConvResult = ConvResult << (NumsBitShift);
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+                if (
+                        (TRUE == GroupPtr->bAdcGroupLimitcheck)
+#if (ADC_SETCHANNEL_API == STD_ON)
+                        || (TRUE == Adc_aRuntimeGroupChannel[Group].bAdcRuntimeGroupLimitcheck)
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+                   )
+                {
+#if (ADC_SETCHANNEL_API == STD_ON)
+                    HwChannel = Adc_aRuntimeGroupChannel[Group].pChannel[Index];
+#else
+                    HwChannel = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].pAssignment[Index];
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+                    /* ADC446, ADC447 */
+                    bFlag = Adc_Ipw_CheckConversionValuesInRange(ConvResult, Unit, HwChannel, u32CoreId);
+                    if (TRUE == bFlag)
+                    {
+                        Adc_Ipw_ReadData(GroupPtr, ResultIndex, GroupSamples, Index, ConvResult);
+                        Adc_aGroupStatus[Group].bLimitCheckFailed = FALSE;
+                    }
+                    else
+                    {
+                        Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+                        Adc_aGroupStatus[Group].bLimitCheckFailed = TRUE;
+
+                        Status = E_NOT_OK;
+                        break;
+                    }
+                }
+                else
+                {
+                    Adc_Ipw_ReadData(GroupPtr, ResultIndex, GroupSamples, Index, ConvResult);
+                }
+#else
+                Adc_Ipw_ReadData(GroupPtr, ResultIndex, GroupSamples, Index, ConvResult);
+#endif /* ADC_ENABLE_LIMIT_CHECK == STD_ON */
+            }
+        }
+        else
+        {
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+
+    return Status;
+}
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+/**
+* @brief          This function handles the case where conversion check fails
+* @details        This function stop all ongoing conversions, clears channel
+*                 configurations and conversion complete flag if the one shot
+*                 mode is selected, but reconfigures hardware if continuous mode
+*                 is selected for the group.
+*
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Selected group Id
+* @param[in]      GroupPtr      Pointer to group config
+*
+* @return         void
+*/
+static inline void Adc_Ipw_HandleConversionCheckFail
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint32 u32CoreId
+)
+{
+    uint8 Channel;
+    Adc_Ip_ChanConfigType ChannelConfig;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+
+    if (ADC_CONV_MODE_ONESHOT == GroupPtr->eMode)
+    {
+        /* Stop and clear all internal channels */
+        for (Channel = 0U; Channel < Adc_aUnitStatus[Unit].u8Sc1Used; Channel++)
+        {
+            ChannelConfig.ChnIdx = Channel;
+            ChannelConfig.Channel = ADC_IP_INPUTCHAN_DISABLED;
+            ChannelConfig.InterruptEnable = FALSE;
+            Adc_Ip_ConfigChannel(PhysicalHwUnitId, &ChannelConfig);
+        }
+    }
+    /* Group configured as continuous will be re-configured*/
+    else
+    {
+        Adc_aGroupStatus[Group].CurrentChannel = 0U;
+        Adc_Ipw_ConfigureConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, 1U, u32CoreId);
+    }
+}
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+/**
+* @brief          This function reconfigures runtime updated channels
+* @details        This function reconfigures runtime updated channels
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      GroupPtr      Selected group pointer
+* @param[in]      NumChannel    Calculated number of channels within range of SC1 registers
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_ConfigureRuntimeChannels
+(
+    Adc_HwUnitType Unit,
+    const Adc_GroupConfigurationType * GroupPtr,
+    uint8 NumChannel,
+    uint32 CoreId
+)
+{
+    Adc_GroupType Group = GroupPtr->GroupId;
+
+    Adc_aGroupStatus[Group].CurrentChannel = 0U;
+    Adc_aGroupStatus[Group].ResultIndex = 0U;
+
+#ifdef ADC_DMA_SUPPORTED
+    /* Not required to check u8AdcWithoutDma == FALSE in DMA notification handler */
+    if ((ADC_DMA == Adc_pCfgPtr[CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit]))
+    {
+        if((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+        {
+            /* Configure for DMA transfer, starting from first sample, consider both Optimize DMA stream and normal DMA scenarios */
+            Adc_Ipw_StartDmaOperation(Unit, Group, NumChannel, CoreId);
+        }
+
+        /* Reconfigure DMA transfer */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        Adc_Ipw_ConfigureDmaConversion(Unit, Group, GroupPtr->HwTriggerSource, NumChannel);
+#else
+        Adc_Ipw_ConfigureDmaConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel);
+#endif
+    }
+    else
+#endif /* ADC_DMA_SUPPORTED */
+    {
+        /* Re-configure group channels and trigger PDB by software */
+#if (ADC_HW_TRIGGER_API == STD_ON)
+        Adc_Ipw_ConfigureConversion(Unit, Group, GroupPtr->HwTriggerSource, NumChannel, CoreId);
+#else
+        Adc_Ipw_ConfigureConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel, CoreId);
+#endif
+    }
+
+    /* Reset runtime update status */
+    Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated = FALSE;
+}
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+/**
+* @brief          This function restarts a conversion
+* @details        This function restarts a conversion and reconfigure the
+*                 hardware if necessary
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Selected group Id
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_RestartConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#if ((ADC_SETCHANNEL_API == STD_ON) || defined(ADC_DMA_SUPPORTED))
+    /* Pointer to AdcGroup */
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+#endif /* ((ADC_SETCHANNEL_API == STD_ON) || (defined(ADC_DMA_SUPPORTED)) */
+#ifdef ADC_DMA_SUPPORTED
+    const uint32 AdcDmaLogicChId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_DmaChannel[Unit];
+    uint16 ResultIndex;
+#endif /*ADC_DMA_SUPPORTED*/
+
+    uint8 NumChannel;
+    Adc_ChannelIndexType ChannelCount;
+    Adc_HwUnitType PhysicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->aAdcPhysicalId[Unit];
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Get channel count in case of changing at runtime */
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    /* Get channel count from configuration */
+    ChannelCount = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    /* Get left channel from channel count */
+    NumChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(ChannelCount);
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Configure again Adc hardware unit in case of channels of group configured */
+    if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+    {
+        Adc_Ipw_ConfigureRuntimeChannels(Unit, GroupPtr, NumChannel, u32CoreId);
+    }
+    else
+#endif  /* (ADC_SETCHANNEL_API == STD_ON) */
+    {
+#ifdef ADC_DMA_SUPPORTED
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+        if (FALSE == GroupPtr->bAdcOptimizeDmaStream)
+#endif /*  (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#endif /*ADC_DMA_SUPPORTED*/
+        {
+            /* Incase of the number of channels in group less than the SC1 register used then update group status and start Pdb */
+            if (ChannelCount <= ADC_MAX_CHAN_COUNT)
+            {
+                /* No need to re-configure channels if they are not changed */
+                /* End of chain interrupt (if used) is still in last channel (= ChannelCount) */
+                Adc_aGroupStatus[Group].CurrentChannel = ChannelCount;
+
+                /* Trigger PDB by software */
+                Pdb_Adc_Ip_SwTrigger(PhysicalHwUnitId);
+            }
+            /* Incase of the number of channels greater than max SC1 register, re-configure Adc hardware unit for the next conversion */
+            else
+            {
+                Adc_aGroupStatus[Group].CurrentChannel = 0U;
+#ifdef ADC_DMA_SUPPORTED
+                if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+                {
+                    /* Dma need to be re-init for next result index */
+                    if ((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+                    {
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+                        if (TRUE == GroupPtr->bStreamResultGroupMultiSets)
+                        {
+                            ResultIndex = Adc_aGroupStatus[Group].ResultIndex * ChannelCount;
+                        }
+                        else
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+                        {
+                            ResultIndex = Adc_aGroupStatus[Group].ResultIndex;
+                        }
+
+                        /* Update DMA configuration for new samples */
+                        Adc_Ipw_UpdateDmaConfig((&(GroupPtr->pResultsBufferPtr[Group][ResultIndex])), AdcDmaLogicChId, NumChannel);
+                    }
+
+                    Adc_Ipw_ConfigureDmaConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel);
+                }
+                else
+#endif /*ADC_DMA_SUPPORTED*/
+                {
+                    /* Re-configure other segment channels of groups And start next conversion*/
+                    Adc_Ipw_ConfigureConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, NumChannel, u32CoreId);
+                }
+            }
+        }
+    }
+}
+
+static inline uint32 Adc_Ipw_GetCurrentSampleCount
+(
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    Adc_GroupType Group,
+    Adc_HwUnitType Unit,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+#else
+    Adc_GroupType Group
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+)
+{
+    Adc_StreamNumSampleType CurrentSampleCount;
+#ifdef ADC_DMA_SUPPORTED
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    uint32 CurrentIter = 0U;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_Ipw_Config * const pAdcIpwConfigPtr = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig;
+    const uint32 u32AdcDmaLogicChId = (uint32) pAdcIpwConfigPtr->Mapping.au8Adc_DmaChannel[Unit];
+    const uint32 u32AdcCountingDmaLogicChId = (uint32) pAdcIpwConfigPtr->Mapping.au8Adc_CountingDmaChannel[Unit];
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#endif /* ADC_DMA_SUPPORTED */
+
+#ifdef ADC_DMA_SUPPORTED
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    if (TRUE == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].bAdcOptimizeDmaStream)
+    {
+        if (1U < Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AssignedChannelCount)
+        {
+            (void)Dma_Ip_GetLogicChannelParam(u32AdcCountingDmaLogicChId, DMA_IP_CH_GET_CURRENT_ITER_COUNT, &CurrentIter);
+        }
+        else
+        {
+            (void)Dma_Ip_GetLogicChannelParam(u32AdcDmaLogicChId, DMA_IP_CH_GET_CURRENT_ITER_COUNT, &CurrentIter);
+        }
+
+        /* This condition only occurs at half interrupt */
+        if ((Adc_StreamNumSampleType)CurrentIter != GroupSamples)
+        {
+            /* Re-calculate CurrentSampleCount because CITER decrements its value from GroupSamples to 1 */
+            CurrentSampleCount = GroupSamples - (Adc_StreamNumSampleType)CurrentIter;
+        }
+        else
+        {
+            /* When major loop completed, CITER roll back to be equal to GroupSamples so no need to re-calculate */
+            CurrentSampleCount = (Adc_StreamNumSampleType)CurrentIter;
+        }
+        Adc_aGroupStatus[Group].ResultIndex = CurrentSampleCount;
+    }
+    else
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#endif /* ADC_DMA_SUPPORTED */
+    {
+        CurrentSampleCount = Adc_aGroupStatus[Group].ResultIndex;
+    }
+
+    return CurrentSampleCount;
+}
+
+/**
+* @brief          This function update state of software conversion according to AutoSar diagrams
+* @details        This function update state of software conversion according to AutoSar diagrams
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Selected group Id
+* @param[in]      GroupSamples  Number of samples
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_UpdateSoftwareGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+)
+{
+    uint32 CurrentSampleCount;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+#ifdef ADC_DMA_SUPPORTED
+    const Adc_Ipw_Config * const pAdcIpwConfigPtr = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig;
+    const uint32 u32AdcDmaLogicChId = (uint32) pAdcIpwConfigPtr->Mapping.au8Adc_DmaChannel[Unit];
+    Adc_HwUnitType PhysicalHwUnitId = pAdcIpwConfigPtr->aAdcPhysicalId[Unit];
+    Dma_Ip_LogicChannelScatterGatherListType LocTransferList[1U];
+#endif /* ADC_DMA_SUPPORTED */
+
+    /* At least once the group was converted */
+    /* It's already check for validation */
+    Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+
+    /* Although updating eConversion is a RMW operation, it does not need an
+     * exclusive area because two simultaneous interrupts will not access the
+     * same areas e.g. the interrupt for ADC1 will not have the same group as
+     * an interrupt on ADC0 */
+    /* Change when configuration is ADC streaming access mode */
+    if (ADC_BUSY == Adc_aGroupStatus[Group].eConversion)
+    {
+        Adc_aGroupStatus[Group].eConversion = ADC_COMPLETED;
+    }
+
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    CurrentSampleCount = Adc_Ipw_GetCurrentSampleCount(Group, Unit, GroupSamples, u32CoreId);
+#else
+    CurrentSampleCount = Adc_Ipw_GetCurrentSampleCount(Group);
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+
+    /* If buffer is full of samples */
+    if (CurrentSampleCount >= GroupSamples)
+    {
+        /* Change to stream complete according to AutoSar diagram */
+        Adc_aGroupStatus[Group].eConversion = ADC_STREAM_COMPLETED;
+
+        if ((ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode) && \
+            (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode) \
+           )
+        {
+#ifdef ADC_DMA_SUPPORTED
+            /* Not required to check u8AdcWithoutDma == FALSE, because u8AdcWithoutDma is only supported for SW normal triggered which cannot be ADC_ACCESS_MODE_STREAMING when DMA transfer selected for HW unit */
+            if (ADC_DMA == pAdcIpwConfigPtr->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+            {
+                /* Disable ADC DMA Request */
+                Adc_Ip_DisableDma(PhysicalHwUnitId);
+            }
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+            /* Because of PDB was configured as CONT MODE then need to disable */
+            if (TRUE == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].bAdcOptimizeDmaStream)
+            {
+                Pdb_Adc_Ip_DisableAndClearPdb(PhysicalHwUnitId);
+            }
+#endif /*  (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#endif /* ADC_DMA_SUPPORTED */
+            /* Update queue and execute new start conversion request from queue if available */
+            Adc_Ipw_UpdateQueue(Unit, u32CoreId);
+        }
+        else
+        {
+            /* ADC_ACCESS_MODE_STREAMING && ADC_STREAM_BUFFER_CIRCULAR */
+            if (ADC_CONV_MODE_CONTINUOUS == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eMode)
+            {
+                /* Restart new continuous conversion */
+                Adc_aGroupStatus[Group].ResultIndex = 0U;
+#ifdef ADC_DMA_SUPPORTED
+                /* TODO: Optimization: It's not necessary to reload the destination address in case of groups have 1 sample (continuous single access or continuous circular with 1 sample) since it's automatically reloaded by DLAST field*/
+                if (ADC_DMA == pAdcIpwConfigPtr->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+                {
+                    if((uint8)STD_OFF == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcExtDMAChanEnable)
+                    {
+                        LocTransferList[0].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+                        LocTransferList[0].Value = (uint32)(&(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].pResultsBufferPtr[Group][0U]));
+                        (void)Dma_Ip_SetLogicChannelTransferList(u32AdcDmaLogicChId, LocTransferList, 1U);
+                    }
+                }
+#endif /*ADC_DMA_SUPPORTED*/
+                Adc_Ipw_RestartConversion(Unit, Group, u32CoreId);
+            }
+            else
+            {
+                /* Update queue and execute new request from queue if available */
+                Adc_Ipw_UpdateQueue(Unit, u32CoreId);
+            }
+        }
+    }
+    else
+    {
+        /* Need to restart conversion until buffer is full */
+        Adc_Ipw_RestartConversion(Unit, Group, u32CoreId);
+    }
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+    /* Implement user notification function if available */
+    Adc_Ipw_CallNotification(Group, u32CoreId);
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+}
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+#ifdef ADC_DMA_SUPPORTED
+static inline void Adc_Ipw_CheckAndUpdateDmaHwGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const uint32 u32AdcDmaLogicChId,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    Dma_Ip_LogicChannelScatterGatherListType LocTransferList[1U];
+    /* ADC_ACCESS_MODE_STREAMING && ADC_STREAM_BUFFER_CIRCULAR */
+    if ((ADC_STREAM_BUFFER_CIRCULAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode) && \
+        (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode)
+        )
+    {
+        if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+        {
+            if((uint8)STD_OFF == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].u8AdcExtDMAChanEnable)
+            {
+                LocTransferList[0].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+                LocTransferList[0].Value = (uint32)(&(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].pResultsBufferPtr[Group][0U]));
+                (void)Dma_Ip_SetLogicChannelTransferList(u32AdcDmaLogicChId, LocTransferList, 1U);
+            }
+        }
+    }
+}
+#endif /* ADC_DMA_SUPPORTED */
+
+/**
+* @brief          This function update state of hardware conversion according to AutoSar diagrams
+* @details        This function update state of hardware conversion according to AutoSar diagrams
+*
+* @param[in]      Unit          Adc Logical Unit Id
+* @param[in]      Group         Selected group Id
+* @param[in]      GroupSamples  Number of samples
+* @param[in]      u32CoreId     Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_UpdateHardwareGroupState
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    Adc_StreamNumSampleType GroupSamples,
+    uint32 u32CoreId
+)
+{
+    boolean NotificationCalled = FALSE;
+    uint32 CurrentSampleCount;
+    Adc_ChannelIndexType ChannelCount;
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_Ipw_Config * const pAdcIpwConfigPtr = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig;
+    Adc_HwUnitType PhysicalHwUnitId = pAdcIpwConfigPtr->aAdcPhysicalId[Unit];
+#ifdef ADC_DMA_SUPPORTED
+    const uint32 u32AdcDmaLogicChId = (uint32) pAdcIpwConfigPtr->Mapping.au8Adc_DmaChannel[Unit];
+#endif /* ADC_DMA_SUPPORTED */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+#else
+    ChannelCount = Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].AssignedChannelCount;
+#endif
+
+    /* At least once the group was converted */
+    Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+
+    /* Although updating eConversion is a RMW operation, it does not need an
+     * exclusive area because two simultaneous interrupts will not access the
+     * same areas e.g. the interrupt for ADC1 will not have the same group as
+     * an interrupt on ADC0 */
+    if (ADC_BUSY == Adc_aGroupStatus[Group].eConversion)
+    {
+        Adc_aGroupStatus[Group].eConversion = ADC_COMPLETED;
+    }
+
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+    CurrentSampleCount = Adc_Ipw_GetCurrentSampleCount(Group, Unit, GroupSamples, u32CoreId);
+#else
+    CurrentSampleCount = Adc_Ipw_GetCurrentSampleCount(Group);
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+
+    if (CurrentSampleCount >= GroupSamples)
+    {
+        Adc_aGroupStatus[Group].eConversion = ADC_STREAM_COMPLETED;
+
+        if ((ADC_STREAM_BUFFER_LINEAR == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eBufferMode) && \
+            (ADC_ACCESS_MODE_STREAMING == Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex].eAccessMode)
+           )
+        {
+            Adc_Ip_DisableChannelNotification(PhysicalHwUnitId, (Adc_aUnitStatus[Unit].u8Sc1Used - 1U));
+#ifdef ADC_DMA_SUPPORTED
+            /* Not required to check u8AdcWithoutDma == FALSE, because u8AdcWithoutDma is only supported for SW normal triggered which cannot be ADC_ACCESS_MODE_STREAMING when DMA transfer selected for HW unit */
+            if (ADC_DMA == pAdcIpwConfigPtr->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+            {
+                /* Disable ADC DMA Request */
+                Adc_Ip_DisableDma(PhysicalHwUnitId);
+            }
+#endif /* ADC_DMA_SUPPORTED */
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+            Adc_Ipw_CallNotification(Group, u32CoreId);
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+            NotificationCalled = TRUE;
+        }
+        else
+        {
+            Adc_aGroupStatus[Group].ResultIndex = 0U;
+#ifdef ADC_DMA_SUPPORTED
+            Adc_Ipw_CheckAndUpdateDmaHwGroupState(Unit, Group, u32AdcDmaLogicChId, u32CoreId);
+#endif /* ADC_DMA_SUPPORTED */
+        }
+    }
+
+    if (NotificationCalled == FALSE)
+    {
+        /* Setting up to PDB HW trigger mode for each completed sample in case of configured channels > SC */
+        if ((ChannelCount > ADC_MAX_CHAN_COUNT)
+#if (ADC_SETCHANNEL_API == STD_ON)
+            || (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+        )
+        {
+            Adc_Ipw_StartHwTrigConversion(Unit, Group, u32CoreId);
+        }
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+        Adc_Ipw_CallNotification(Group, u32CoreId);
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+    }
+}
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+/**
+* @brief          This function handles conversion ending routines
+* @details        This function handles conversion ending routines
+*
+* @param[in]      Unit                  Adc Logical Unit Id
+* @param[in]      Group                 Selected group Id
+* @param[in]      IsSoftwareConversion  Software or Hardware triggered conversion
+* @param[in]      u32CoreId             Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_EndConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    boolean IsSoftwareConversion,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr; /* Pointer to AdcGroup */
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+    Adc_ChannelIndexType NumChannel;
+    uint8 LeftChannel;
+#endif /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+#if ((ADC_SETCHANNEL_API == STD_ON) || ((ADC_SETCHANNEL_API == STD_OFF) && (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)))
+    Adc_ChannelIndexType ChannelCount;
+#endif /* ((ADC_SETCHANNEL_API == STD_ON) || ((ADC_SETCHANNEL_API == STD_OFF) && (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF))) */
+
+
+    /* Get the group configuration */
+    GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Channels configured at runtime */
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+
+    /* Check if channel was updated before interrupt of previous conversions */
+    if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+    {
+        Adc_Ipw_ConfigureRuntimeChannels(Unit, GroupPtr, (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(ChannelCount), u32CoreId);
+    }
+    else
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    {
+        /* Limit checking */
+        if (Adc_Ipw_CheckConversionChannels(Unit, Group, GroupPtr->NumSamples, u32CoreId) == (Std_ReturnType)E_OK)
+        {
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+            /* Following code will not be reduced when oneshot hardware trigger optimization is not enabled */
+
+#if (ADC_SETCHANNEL_API == STD_OFF)
+            /* Channels configured when initializing */
+            ChannelCount = GroupPtr->AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+            /* More channels in group */
+            /* Both HW and SW groups are using PDB SW trigger mode to restart conversion when ChannelCount > Max SC registers */
+            if (Adc_aGroupStatus[Group].CurrentChannel < ChannelCount)
+            {
+                /* Get left channel */
+                NumChannel = ChannelCount - Adc_aGroupStatus[Group].CurrentChannel;
+
+                /* In case of left channels excess maximum allowed channels */
+                LeftChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(NumChannel);
+
+                /* Configure left channels and start more conversions */
+                Adc_Ipw_ConfigureConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, LeftChannel, u32CoreId);
+            }
+            /* All of channels converted */
+            else
+#endif
+            {
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+            Adc_Ipw_CallExtraNotification(Group, u32CoreId);
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON)
+                /* At least once the group was converted */
+                Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+
+                Adc_aGroupStatus[Group].eConversion = ADC_STREAM_COMPLETED;
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+                /* Check if channel was updated in Adc_Ipw_CallExtraNotification */ 
+                if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+                {
+                    Adc_Ipw_ConfigureRuntimeChannels(Unit, GroupPtr, (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(ChannelCount), u32CoreId);
+                }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_OFF)
+            (void)IsSoftwareConversion;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_OFF) */
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+                /* Check notification of a group and call the notification function if needed */
+                Adc_Ipw_CallNotification(Group, u32CoreId);
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+
+#else /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+                /* Although this is a RMW operation, it does not need an exclusive area because two
+                * simultaneous interrupts will not access the same areas e.g. the interrupt for
+                * ADC1 will not have the same group as an interrupt on ADC0 */
+                /* Increment ResultIndex with modulo 'NumSamples' to remember that another sample is completed */
+                Adc_aGroupStatus[Group].ResultIndex++;
+
+                /* Update state following AutoSar diagrams */
+                if (TRUE == IsSoftwareConversion)
+                {
+                    Adc_Ipw_UpdateSoftwareGroupState(Unit, Group, GroupPtr->NumSamples, u32CoreId);
+                }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+                else
+                {
+                    Adc_Ipw_UpdateHardwareGroupState(Unit, Group, GroupPtr->NumSamples, u32CoreId);
+                }
+#endif  /* (ADC_HW_TRIGGER_API == STD_ON) */
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON) */
+            }
+        }
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        else
+        {
+            if (TRUE == IsSoftwareConversion)
+            {
+                Adc_Ipw_HandleConversionCheckFail(Unit, Group, GroupPtr, u32CoreId);
+            }
+        }
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+    }
+}
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief          This function handles conversion ending routines incase of DMA Transfering
+* @details        This function handles conversion ending routines incase of DMA Transfering
+*
+* @param[in]      Unit                  Adc Logical Unit Id
+* @param[in]      Group                 Selected group Id
+* @param[in]      IsSoftwareConversion  Software or Hardware triggered conversion
+* @param[in]      u32CoreId             Current CoreID
+*
+* @return         void
+*/
+static inline void Adc_Ipw_EndDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    boolean IsSoftwareConversion,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_GroupConfigurationType * GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]); /* Pointer to AdcGroup */
+    const uint32 AdcDmaLogicChId = (uint32) Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.au8Adc_DmaChannel[Unit];
+#if ((ADC_SETCHANNEL_API == STD_ON) || ((ADC_SETCHANNEL_API == STD_OFF) && (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)))
+    Adc_ChannelIndexType ChannelCount;
+#endif /* ((ADC_SETCHANNEL_API == STD_ON) || ((ADC_SETCHANNEL_API == STD_OFF) && (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF))) */
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+    /* Channels configured at runtime */
+    ChannelCount = Adc_aRuntimeGroupChannel[Group].ChannelCount;
+
+    /* Check if channel was updated before interrupt of previous conversions */
+    if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+    {
+        Adc_Ipw_ConfigureRuntimeChannels(Unit, GroupPtr, (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(ChannelCount), u32CoreId);
+    }
+    else
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+    {
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        if (Adc_Ipw_CheckGroupConvResultDma(GroupPtr, u32CoreId) == (Std_ReturnType)E_OK)
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+        {
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+            /* Following code will not be reduced when oneshot hardware trigger optimization is not enabled */
+
+#if (ADC_SETCHANNEL_API == STD_OFF)
+            /* Channels configured when initializing */
+            ChannelCount = GroupPtr->AssignedChannelCount;
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+            /* More channels in group */
+            if (Adc_aGroupStatus[Group].CurrentChannel < ChannelCount)
+            {
+                Adc_Ipw_ContinueDmaConversion(Unit, Group, ChannelCount, AdcDmaLogicChId, u32CoreId);
+            }
+            /* All of channels converted */
+            else
+#endif /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+            {
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+                Adc_Ipw_CallExtraNotification(Group, u32CoreId);
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON)
+                /* At least once the group was converted */
+                Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+
+                Adc_aGroupStatus[Group].eConversion = ADC_STREAM_COMPLETED;
+
+#if (ADC_SETCHANNEL_API == STD_ON)
+                /* Check if channel was updated in Adc_Ipw_CallExtraNotification */ 
+                if (TRUE == Adc_aRuntimeGroupChannel[Group].bRuntimeUpdated)
+                {
+                    Adc_Ipw_ConfigureRuntimeChannels(Unit, GroupPtr, (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(ChannelCount), u32CoreId);
+                }
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_OFF)
+            (void)IsSoftwareConversion;
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_OFF) */
+
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+                /* Check notification of a group and call the notification function if needed */
+                Adc_Ipw_CallNotification(Group, u32CoreId);
+#endif /* (ADC_GRP_NOTIF_CAPABILITY == STD_ON) */
+
+#else /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+                /* Although this is a RMW operation, it does not need an exclusive area because two
+                * simultaneous interrupts will not access the same areas e.g. the interrupt for
+                * ADC1 will not have the same group as an interrupt on ADC0 */
+                /* Increment ResultIndex with modulo 'NumSamples' to remember that another sample is completed */
+                Adc_aGroupStatus[Group].ResultIndex++;
+
+                /* Update state following AutoSar diagrams */
+                if (TRUE == IsSoftwareConversion)
+                {
+                    Adc_Ipw_UpdateSoftwareGroupState(Unit, Group, GroupPtr->NumSamples, u32CoreId);
+                }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+                else
+                {
+                    Adc_Ipw_UpdateHardwareGroupState(Unit, Group, GroupPtr->NumSamples, u32CoreId);
+                }
+#endif  /* (ADC_HW_TRIGGER_API == STD_ON) */
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_ON) */
+
+                if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[Unit])
+                {
+                    if((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+                    {
+                        /* DMA Hardware Request was disabled after transfer completed, to avoid overwriting any new results before this gets processed. Re-enable DMA here. */
+                        (void)Dma_Ip_SetLogicChannelCommand(AdcDmaLogicChId, DMA_IP_CH_SET_HARDWARE_REQUEST);
+                    }
+                }
+            }
+        }
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        else
+        {
+            if (TRUE == IsSoftwareConversion)
+            {
+                Adc_Ipw_HandleConversionCheckFail(Unit, Group, GroupPtr, u32CoreId);
+            }
+        }
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+    }
+}
+
+#if (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF)
+/**
+* @brief          This function updates Dma configuration
+* @details        This function updates Dma configuration if number of configured channels
+*                 are greater than number of SC1 register
+*
+* @param[in]      DataPtr       Adc_ValueGroupType * DataPtr,
+* @param[in]      DmaLogicChId  Dma logical channel
+* @param[in]      NumChannel    Number of channel to be converted
+*
+* @return         void
+*/
+static inline void Adc_Ipw_UpdateDmaConfig
+(
+    const Adc_ValueGroupType * DataPtr,
+    const uint32 DmaLogicChId,
+    uint8 NumChannel
+)
+{
+    Dma_Ip_LogicChannelTransferListType LocTransferList[3U];
+
+    LocTransferList[0].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    LocTransferList[0].Value = (uint32)(DataPtr);
+    LocTransferList[1].Param = DMA_IP_CH_SET_SOURCE_SIGNED_LAST_ADDR_ADJ;
+    LocTransferList[1].Value = ADC_IPW_GET_COMPLEMENT_OF_2((uint32)NumChannel << 2UL);
+    LocTransferList[2].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    LocTransferList[2].Value = (uint32)NumChannel;
+
+    /* Setting for DMA transfer */
+    (void)Dma_Ip_SetLogicChannelTransferList(DmaLogicChId, LocTransferList, 3U);
+    (void)Dma_Ip_SetLogicChannelCommand(DmaLogicChId, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+
+
+static inline void Adc_Ipw_ContinueDmaConversion
+(
+    Adc_HwUnitType Unit,
+    Adc_GroupType Group,
+    const Adc_ChannelIndexType ChannelCount,
+    const uint32 AdcDmaLogicChId,
+    uint32 u32CoreId
+)
+{
+    const Adc_GroupType GroupIndex = Adc_pCfgPtr[u32CoreId]->pGroupIdToIndexMap[Group];
+    const Adc_ChannelIndexType NumChannel = ChannelCount - Adc_aGroupStatus[Group].CurrentChannel;
+    /* In case of left channels excess maximum allowed channels */
+    const uint8 LeftChannel = (uint8)ADC_IPW_CALCULATE_CHAN_NUMBER(NumChannel);
+    const Adc_GroupConfigurationType * GroupPtr; /* Pointer to AdcGroup */
+    uint16 ResultIndex;
+
+    GroupPtr = &(Adc_pCfgPtr[u32CoreId]->pGroups[GroupIndex]);
+
+    if ((uint8)STD_OFF == GroupPtr->u8AdcExtDMAChanEnable)
+    {
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        if (TRUE == GroupPtr->bStreamResultGroupMultiSets)
+        {
+            ResultIndex = (Adc_aGroupStatus[Group].ResultIndex * ChannelCount) + Adc_aGroupStatus[Group].CurrentChannel;
+        }
+        else
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+        {
+            ResultIndex = ((Adc_aGroupStatus[Group].CurrentChannel) * (GroupPtr->NumSamples)) + Adc_aGroupStatus[Group].ResultIndex;
+        }
+
+        /* Update DMA configuration for remaining channels */
+        Adc_Ipw_UpdateDmaConfig((&(GroupPtr->pResultsBufferPtr[Group][ResultIndex])), AdcDmaLogicChId, LeftChannel);
+    }
+
+    /* Configure left channels and start more conversions */
+    Adc_Ipw_ConfigureDmaConversion(Unit, Group, PDB_ADC_IP_SOFTWARE_TRIGGER, LeftChannel);
+
+}
+#endif  /* (ADC_OPTIMIZE_ONESHOT_HW_TRIGGER == STD_OFF) */
+
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+/**
+* @brief          This function checks the conversion result when Limit Check and DMA are enabled.
+* @details        This function checks the conversion result when Limit Check and DMA are enabled.
+*
+* @param[in]      pGroupPtr         The Adc Group Pointer.
+* @param[in]      u32CoreId         Current CoreID
+*
+* @return         Std_ReturnType
+*
+*/
+static inline Std_ReturnType Adc_Ipw_CheckGroupConvResultDma
+(
+    const Adc_GroupConfigurationType * pGroupPtr,
+    uint32 u32CoreId
+)
+{
+    Std_ReturnType ReturnValue = (Std_ReturnType)E_OK;
+    const Adc_GroupType Group = pGroupPtr->GroupId;
+    const Adc_HwUnitType Unit = pGroupPtr->AdcLogicalUnitId;
+    Adc_ValueGroupType * pResultData = &(pGroupPtr->pResultsBufferPtr[Group][Adc_aGroupStatus[Group].ResultIndex]);
+    Adc_ChannelType HwChannel;
+#if (ADC_SETCHANNEL_API == STD_ON)
+    HwChannel = Adc_aRuntimeGroupChannel[Group].pChannel[0];
+#else
+    HwChannel = pGroupPtr->pAssignment[0];
+#endif /* (ADC_SETCHANNEL_API == STD_ON) */
+
+    if (
+            (TRUE == pGroupPtr->bAdcGroupLimitcheck)
+#if (ADC_SETCHANNEL_API == STD_ON)
+            || (TRUE == Adc_aRuntimeGroupChannel[Group].bAdcRuntimeGroupLimitcheck)
+#endif /* ADC_SETCHANNEL_API == STD_ON */
+       )
+    {
+        /* Assumption: because of SWS_Adc_00451, the number of channels configured for a group when limit checking is disabled, must be one.*/
+        if (FALSE == Adc_Ipw_CheckConversionValuesInRange(pResultData[0], Unit, HwChannel, u32CoreId))
+        {
+            /* SWS_Adc_00448 */
+            /* Return an error */
+            Adc_aGroupStatus[Group].eAlreadyConverted = ADC_ALREADY_CONVERTED;
+            Adc_aGroupStatus[Group].bLimitCheckFailed = TRUE;
+            pResultData[0] = 0U;
+            ReturnValue = (Std_ReturnType) E_NOT_OK;
+        }
+        else
+        {
+            Adc_aGroupStatus[Group].bLimitCheckFailed = FALSE;
+        }
+    }
+
+    return ReturnValue;
+}
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+#endif /* ADC_DMA_SUPPORTED */
+
+
+/**
+* @brief          This function read conversion results
+* @details        This function read conversion results
+*
+* @param[in]      GroupPtr      Group Pointer
+* @param[in]      pResult       Pointer to conversion results
+* @param[in]      GroupSamples  Number of samples
+* @param[in]      Index         Current index of result
+* @param[in]      ConvResult    Conversion result
+*
+* @return         void
+*/
+static inline void Adc_Ipw_ReadData
+(
+    const Adc_GroupConfigurationType * GroupPtr,
+    Adc_ValueGroupType * pResult,
+    const Adc_StreamNumSampleType GroupSamples,
+    const Adc_ChannelIndexType Index,
+    const uint16 ConvResult
+)
+{
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    if (FALSE == GroupPtr->bStreamResultGroupMultiSets)
+    {
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+        pResult[(Index * GroupSamples)] = ConvResult;
+        (void)GroupPtr;
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+    }
+    else
+    {
+        pResult[Index] = ConvResult;
+    }
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+}
+
+
+/**
+* @brief          This function handles the end conversion notification.
+* @details        This function handles the end conversion notification.
+*
+* @param[in]      PhysicalAdcUnit   ADC Hardware Unit
+*
+* @return         void
+*/
+static inline void Adc_Ipw_EndConversionNotification
+(
+    const Adc_HwUnitType PhysicalAdcUnit
+)
+{
+    /* Check that ADC unit is assigned to current core partition */
+    const volatile uint32 u32CoreId = Adc_GetCoreID();
+    const Adc_HwUnitType LogicalHwUnitId = Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.aHwLogicalId[PhysicalAdcUnit];
+    const Adc_GroupType SwGroupId = Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueue[0U];
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    const Adc_GroupType HwGroupId = Adc_aUnitStatus[LogicalHwUnitId].OngoingHwGroup;
+#endif /* ADC_HW_TRIGGER_API == STD_ON */
+
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    /* Check if requests are available in queue */
+    if (ADC_INVALID_HW_GROUP_ID != HwGroupId)
+    {
+#ifdef ADC_DMA_SUPPORTED
+        if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId])
+        {
+            Adc_Ipw_EndDmaConversion(LogicalHwUnitId, HwGroupId, FALSE, u32CoreId);
+        }
+        else
+#endif /* ADC_DMA_SUPPORTED */
+        {
+            Adc_Ipw_EndConversion(LogicalHwUnitId, HwGroupId, FALSE, u32CoreId);
+        }
+    }
+    else
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+    if (Adc_aUnitStatus[LogicalHwUnitId].SwNormalQueueIndex > (Adc_QueueIndexType)0U)
+    {
+#ifdef ADC_DMA_SUPPORTED
+        if (ADC_DMA == Adc_pCfgPtr[u32CoreId]->pAdcIpwConfig->Mapping.u8Adc_DmaInterruptSoftware[LogicalHwUnitId])
+        {
+            Adc_Ipw_EndDmaConversion(LogicalHwUnitId, SwGroupId, TRUE, u32CoreId);
+        }
+        else
+#endif /* ADC_DMA_SUPPORTED */
+        {
+            Adc_Ipw_EndConversion(LogicalHwUnitId, SwGroupId, TRUE, u32CoreId);
+        }
+    }
+#if (ADC_HW_TRIGGER_API == STD_ON)
+    else
+    {
+        ; /* Empty else branch to avoid MISRA */
+    }
+#endif /* (ADC_HW_TRIGGER_API == STD_ON) */
+}
+
+/*==================================================================================================
+*                                   GLOBAL FUNCTION PROTOTYPES
+==================================================================================================*/
+/* IAR wants prototypes due to --require-prototypes */
+#ifdef ADC_UNIT_0_ISR_USED
+void Adc_Ipw_Adc0EndConversionNotification(const uint8 ControlChanIdx);
+#endif /* ADC_UNIT_0_ISR_USED */
+
+#ifdef ADC_UNIT_1_ISR_USED
+void Adc_Ipw_Adc1EndConversionNotification(const uint8 ControlChanIdx);
+#endif /* ADC_UNIT_1_ISR_USED */
+
+#ifdef ADC_DMA_SUPPORTED
+void Adc_Ipw_Adc0DmaTransferCompleteNotification(void);
+void Adc_Ipw_Adc1DmaTransferCompleteNotification(void);
+#endif /* ADC_DMA_SUPPORTED */
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+                                          ADC HW UNIT 0
+==================================================================================================*/
+#ifdef ADC_UNIT_0_ISR_USED
+/**
+* @brief          This function handles the ISR for the conversion done of
+*                 the ADC Hardware Unit 0.
+* @details        The function handles the ISR for the ADC Hardware Unit 0.
+*
+* @return         void
+*
+*/
+void Adc_Ipw_Adc0EndConversionNotification(const uint8 ControlChanIdx)
+{
+    const Adc_HwUnitType PhysicalAdcUnit = 0U;
+
+    (void)ControlChanIdx;
+
+    Adc_Ipw_EndConversionNotification(PhysicalAdcUnit);
+}
+#endif /* ADC_UNIT_0_ISR_USED */
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief          This function implements the end of DMA transfer notification for
+*                 ADC Hardware Unit 0.
+* @details        This function implements the end of DMA transfer notification for
+*                 ADC Hardware Unit 0.
+*
+* @return         void
+*
+*/
+void Adc_Ipw_Adc0DmaTransferCompleteNotification(void)
+{
+    const Adc_HwUnitType PhysicalAdcUnit = 0U;
+
+    Adc_Ipw_EndConversionNotification(PhysicalAdcUnit);
+}
+#endif /* ADC_DMA_SUPPORTED */
+
+/*==================================================================================================
+                                          ADC HW UNIT 1
+==================================================================================================*/
+#ifdef ADC_UNIT_1_ISR_USED
+/**
+* @brief          This function handles the ISR for the conversion done of
+*                 the ADC Hardware Unit 1.
+* @details        The function handles the ISR for the ADC Hardware Unit 1.
+*
+* @return         void
+*
+*/
+void Adc_Ipw_Adc1EndConversionNotification(const uint8 ControlChanIdx)
+{
+    const Adc_HwUnitType PhysicalAdcUnit = 1U;
+
+    (void)ControlChanIdx;
+
+    Adc_Ipw_EndConversionNotification(PhysicalAdcUnit);
+}
+#endif /* ADC_UNIT_1_ISR_USED */
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief          This function implements the end of DMA transfer notification for
+*                 ADC Hardware Unit 0.
+* @details        This function implements the end of DMA transfer notification for
+*                 ADC Hardware Unit 0.
+*
+* @return         void
+*
+*/
+void Adc_Ipw_Adc1DmaTransferCompleteNotification(void)
+{
+    const Adc_HwUnitType PhysicalAdcUnit = 1U;
+
+    Adc_Ipw_EndConversionNotification(PhysicalAdcUnit);
+}
+#endif /* ADC_DMA_SUPPORTED */
+#endif  /* (defined(ADC_UNIT_0_ISR_USED) || ... */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Pdb_Adc_Ip.c

@@ -0,0 +1,832 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip Pdb Adc IPL
+*   @{
+*/
+
+#include "Pdb_Adc_Ip.h"
+#include "Pdb_Adc_Ip_HwAccess.h"
+#include "SchM_Adc.h"
+#include "OsIf.h"
+
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+#include "Devassert.h"
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+#if (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    /* USER_MODE_REG_PROT_ENABLED is defined for Base sanity check in RegLockMacros.h */
+    #define USER_MODE_REG_PROT_ENABLED      (PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    #include "RegLockMacros.h"
+#endif /* (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define PDB_ADC_IP_VENDOR_ID_C                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_C    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_C               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_C               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_C               0
+
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+/* Check if Pdb_Adc_Ip.c file and Pdb_Adc_Ip.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_C != PDB_ADC_IP_VENDOR_ID_H)
+    #error "Pdb_Adc_Ip.c and Pdb_Adc_Ip.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip.c file and Pdb_Adc_Ip.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_C != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.c and Pdb_Adc_Ip.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip.c file and Pdb_Adc_Ip.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_C != PDB_ADC_IP_SW_MAJOR_VERSION_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_C != PDB_ADC_IP_SW_MINOR_VERSION_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_C != PDB_ADC_IP_SW_PATCH_VERSION_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip.c and Pdb_Adc_Ip.h are different"
+#endif
+
+#if (PDB_ADC_IP_VENDOR_ID_C != PDB_ADC_IP_VENDOR_ID_HWACCESS_H)
+    #error "Pdb_Adc_Ip.c and Pdb_Adc_Ip_HwAccess.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip.c file and Pdb_Adc_Ip_HwAccess.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_C != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.c and Pdb_Adc_Ip_HwAccess.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip.c file and Pdb_Adc_Ip_HwAccess.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_C != PDB_ADC_IP_SW_MAJOR_VERSION_HWACCESS_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_C != PDB_ADC_IP_SW_MINOR_VERSION_HWACCESS_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_C != PDB_ADC_IP_SW_PATCH_VERSION_HWACCESS_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip.c and Pdb_Adc_Ip_HwAccess.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check if Pdb_Adc_Ip.c file and OsIf.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+        (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.c and OsIf.h are different"
+#endif
+
+#if (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    /* Checks against RegLockMacros.h */
+    #if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
+         (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
+        #error "AUTOSAR Version Numbers of Pdb_Adc_Ip.c and RegLockMacros.h are different"
+    #endif
+#endif /* (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+
+/* Check if Pdb_Adc_Ip.c and SchM_Adc.h are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_ADC_AR_RELEASE_MINOR_VERSION) \
+    )
+#error "AutoSar Version Numbers of Pdb_Adc_Ip.c and SchM_Adc.h are different"
+#endif
+
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+ /* Check if Pdb_Adc_Ip.c and Devassert.h are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip.c and Devassert.h are different"
+#endif
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/*******************************************************************************
+ * Pre-check
+ ******************************************************************************/
+#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
+    #if (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+        #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running PDB in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
+    #endif /* (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT) */
+#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT*/
+
+/*******************************************************************************
+ * Local function prototypes
+ ******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+static inline void PDB_ADC_ResetChannel(PDB_Type * const Base, const uint8 ChanIdx, const Pdb_Adc_Ip_PretriggersConfigType * PdbPretriggsConfig);
+
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+static void PDB_ADC_ConfigInstanceBackToBack_TrustedCall(const boolean InstanceBackToBackEnable);
+static void PDB_ADC_ConfigInstanceBackToBack(const boolean InstanceBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+static void PDB_ADC_ConfigInterChannelBackToBack_TrustedCall(const uint32 Instance, const boolean InterChannelBackToBackEnable);
+static void PDB_ADC_ConfigInterChannelBackToBack(const uint32 Instance, const boolean InterChannelBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CONST_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/* Table of Base addresses for PDB instances. */
+static PDB_Type * const PdbBase[PDB_INSTANCE_COUNT] = IP_PDB_BASE_PTRS;
+
+#define ADC_STOP_SEC_CONST_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+/* Global state structure */
+static Pdb_Adc_Ip_StateStructType PdbAdcState[PDB_INSTANCE_COUNT];
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_Init
+* Description   : This function initializes the PDB counter, input triggers and
+* general pretrigger settings.
+* It resets PDB registers and enables the PDB clock. Therefore, it should be
+* called before any other operation. After it is initialized, the PDB can
+* act as a triggered timer, which enables other features in PDB module.
+*
+* @implements     Pdb_Adc_Ip_Init_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_Init(const uint32 Instance, const Pdb_Adc_Ip_ConfigType * const Config)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(Config != NULL_PTR);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint8 ChannelIndex, PretriggerIndex;
+    uint32 Reg = 0u;
+
+    Reg |= PDB_SC_LDMOD(Config->LoadValueMode);
+    Reg |= PDB_SC_PRESCALER(Config->PrescalerDiv);
+    Reg |= PDB_SC_MULT(Config->ClkPreMultFactor);
+    Reg |= PDB_SC_TRGSEL(Config->TriggerSource);
+
+    if (Config->ContinuousModeEnable == TRUE)
+    {
+        Reg |= PDB_SC_CONT_MASK;
+    }
+    if (Config->DmaEnable == TRUE)
+    {
+        Reg |= PDB_SC_DMAEN_MASK;
+    }
+    if (Config->SeqErrNotification != NULL_PTR)
+    {
+        Reg |= PDB_SC_PDBEIE_MASK;
+    }
+
+    Base->SC = Reg;
+
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+    PDB_ADC_ConfigInstanceBackToBack(Config->InstanceBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+    PDB_ADC_ConfigInterChannelBackToBack(Instance, Config->InterChannelBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+
+    Pdb_Adc_Ip_SetModulus(Instance, Config->ModValue);
+
+    if ((Config->NumChans > 0u) && (Config->ChanConfigs != NULL_PTR))
+    {
+        for (ChannelIndex = 0u; ChannelIndex < Config->NumChans; ChannelIndex++)
+        {
+            const Pdb_Adc_Ip_ChanConfigType * ChanConfig = &(Config->ChanConfigs[ChannelIndex]);
+            Pdb_Adc_HwAcc_ConfigAdcPretriggers(Base, ChanConfig->ChnIdx, &(ChanConfig->PretriggersConfig));
+            for (PretriggerIndex = 0u; PretriggerIndex < PDB_DLY_COUNT; PretriggerIndex++)
+            {
+                Pdb_Adc_Ip_SetAdcPretriggerDelayValue(Instance, ChanConfig->ChnIdx, PretriggerIndex, ChanConfig->PretriggerDelays[PretriggerIndex]);
+            }
+        }
+    }
+
+    Pdb_Adc_Ip_Enable(Instance);
+
+    /* Modulus and pretrigger delay values require call to LoadRegValues */
+    Pdb_Adc_Ip_LoadRegValues(Instance);
+
+    PdbAdcState[Instance].SeqErrNotification = Config->SeqErrNotification;
+    PdbAdcState[Instance].Init = TRUE;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_DeInit
+* Description   : This function resets the PDB internal registers to default values.
+*
+* When the PDB module is not used. Calling this function would shut down the
+* PDB module and reduce the power consumption.
+*
+* Note: instance back to back configuration is common between PDB instances 0 and 1
+* (configures the same register even if configured for either PDB instance)
+* This function disables it, so affects all other instances.
+*
+* @implements     Pdb_Adc_Ip_Deinit_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_DeInit(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    Pdb_Adc_Ip_ConfigType DefaultConfig;
+    Pdb_Adc_Ip_ChanConfigType ChanConfigs[PDB_CH_COUNT];
+    uint8 ChannelIndex, PretriggerIndex;
+
+    DefaultConfig.LoadValueMode = PDB_ADC_IP_LOAD_VAL_IMMEDIATELY;
+    DefaultConfig.PrescalerDiv = PDB_ADC_IP_CLK_PREDIV_BY_1;
+    DefaultConfig.ClkPreMultFactor = PDB_ADC_IP_CLK_PREMULT_FACT_AS_1;
+    DefaultConfig.TriggerSource = PDB_ADC_IP_TRIGGER_IN0;
+    DefaultConfig.ContinuousModeEnable = FALSE;
+    DefaultConfig.DmaEnable = FALSE;
+    DefaultConfig.ModValue = 0u;
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+    DefaultConfig.InstanceBackToBackEnable = FALSE;
+    PDB_ADC_ConfigInstanceBackToBack(DefaultConfig.InstanceBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+    DefaultConfig.InterChannelBackToBackEnable = FALSE;
+    PDB_ADC_ConfigInterChannelBackToBack(Instance, DefaultConfig.InterChannelBackToBackEnable);
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+
+    DefaultConfig.NumChans = PDB_CH_COUNT;
+    for (ChannelIndex = 0u; ChannelIndex < PDB_CH_COUNT; ChannelIndex++)
+    {
+        ChanConfigs[ChannelIndex].ChnIdx = ChannelIndex;
+        ChanConfigs[ChannelIndex].PretriggersConfig.EnableMask = 0u;
+        ChanConfigs[ChannelIndex].PretriggersConfig.EnableDelayMask = 0u;
+        ChanConfigs[ChannelIndex].PretriggersConfig.BackToBackEnableMask = 0u;
+        for (PretriggerIndex = 0u; PretriggerIndex < PDB_DLY_COUNT; PretriggerIndex++)
+        {
+            ChanConfigs[ChannelIndex].PretriggerDelays[PretriggerIndex] = 0u;
+        }
+    }
+    DefaultConfig.ChanConfigs = ChanConfigs;
+    DefaultConfig.SeqErrNotification = NULL_PTR;
+
+    Pdb_Adc_Ip_Init(Instance, &DefaultConfig);
+
+    Pdb_Adc_Ip_Disable(Instance);
+
+    PdbAdcState[Instance].Init = FALSE;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_Enable
+* Description   : This function enables the PDB module, counter is on.
+*
+* @implements     Pdb_Adc_Ip_Enable_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_Enable(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34();
+    Base->SC |= PDB_SC_PDBEN_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_Disable
+* Description   : This function disables the PDB module, counter is off.
+*
+* @implements     Pdb_Adc_Ip_Disable_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_Disable(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35();
+    Pdb_Adc_HwAcc_DisablePdb(Base);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetTriggerInput
+* Description   : This function sets the PDB trigger source.
+*
+* @implements     Pdb_Adc_Ip_SetTriggerInput_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetTriggerInput(const uint32 Instance, const Pdb_Adc_Ip_TriggerSrcType TriggerSource)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint32 SCReg;
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36();
+    SCReg = Base->SC;
+    SCReg &= ~(PDB_SC_TRGSEL_MASK);
+    SCReg |= PDB_SC_TRGSEL(TriggerSource);
+    Base->SC = SCReg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetContinuousMode
+* Description   : This function sets the PDB mode to continuous or one shot.
+*
+* @implements     Pdb_Adc_Ip_SetContinuousMode_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetContinuousMode(const uint32 Instance, const boolean State)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37();
+    Pdb_Adc_HwAcc_SetContinuousMode(Base, State);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SwTrigger
+* Description   : This function triggers the PDB with a software trigger.
+* When the PDB is set to use the software trigger as input, calling this function
+* triggers the PDB.
+*
+* @implements     Pdb_Adc_Ip_SwTrigger_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SwTrigger(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38();
+    Base->SC |= PDB_SC_SWTRIG_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_GetTimerValue
+* Description   : This function gets the current counter value.
+*
+* @implements     Pdb_Adc_Ip_GetTimerValue_Activity
+* END**************************************************************************/
+uint32 Pdb_Adc_Ip_GetTimerValue(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const PDB_Type * const Base = PdbBase[Instance];
+
+    return ((Base->CNT & PDB_CNT_CNT_MASK) >> PDB_CNT_CNT_SHIFT);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_LoadRegValues
+* Description   : This function sets the LDOK bit.
+* Writing one to this bit updates the internal registers MOD, IDLY, CHnDLYm and
+* POyDLY with the values written to their buffers. The MOD, IDLY,
+* CHnDLYm and POyDLY take effect according to the load mode settings.
+*
+* After one is written to the LDOK bit, the values in the buffers of above mentioned
+* registers are not effective and cannot be written until the values in the
+* buffers are loaded into their internal registers. The moment when this happens
+* depends on the value of the LDMOD register. Only when this register is in it's
+* default state(0), the load operation will happen immediately. Please check the
+* reference manual for more information.
+* The LDOK can be written only when the the PDB is enabled or as alone with it. It is
+* automatically cleared either when the values in the buffers are loaded into the
+* internal registers or when the PDB is disabled.
+*
+* @implements     Pdb_Adc_Ip_LoadRegValues_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_LoadRegValues(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    /* PDB must be enabled in order to load register values */
+    DevAssert((Base->SC & PDB_SC_PDBEN_MASK) != 0u);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39();
+    Base->SC |= PDB_SC_LDOK_MASK;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetModulus
+* Description   : This function sets the PDB Modulus value.
+* When the counter reaches the setting value, it is automatically reset to zero.
+* When in continuous mode, the counter begins to increase again.
+* Note: This function writes in an internal buffer. Depending on the
+* value of the LDMOD register, it might be necessary to call
+* Pdb_Adc_Ip_LoadRegValues in order to update the value of the register.
+* The value of the register can be changed only when the PDB module is enabled.
+*
+* @implements     Pdb_Adc_Ip_SetModulus_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetModulus(const uint32 Instance, const uint16 ModVal)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint32 ModReg;
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48();
+    ModReg = Base->MOD;
+    ModReg &= ~(PDB_MOD_MOD_MASK);
+    ModReg |= PDB_MOD_MOD(ModVal);
+    Base->MOD = ModReg;
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_ConfigAdcPretriggers
+* Description   : This function configures the back to back modes, delay enable
+* and output enable settings for all pretriggers on the selected channel.
+*
+* @implements     Pdb_Adc_Ip_ConfigAdcPretriggers_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_ConfigAdcPretriggers(const uint32 Instance, const uint8 ChanIdx, const Pdb_Adc_Ip_PretriggersConfigType * const Config)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+    DevAssert(Config != NULL_PTR);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41();
+    Pdb_Adc_HwAcc_ConfigAdcPretriggers(Base, ChanIdx, Config);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_GetAdcPretriggerFlags
+* Description   : This function gets all ADC pretrigger flags from the selected channel.
+*
+* @implements     Pdb_Adc_Ip_GetAdcPretriggerFlags_Activity
+* END**************************************************************************/
+uint32 Pdb_Adc_Ip_GetAdcPretriggerFlags(const uint32 Instance, const uint8 ChanIdx)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    const PDB_Type * const Base = PdbBase[Instance];
+    uint32 Result;
+
+    Result = Base->CH[ChanIdx].S;
+    Result = (Result & PDB_S_CF_MASK) >> PDB_S_CF_SHIFT;
+
+    return Result;
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_ClearAdcPretriggerFlags
+* Description   : This function clears the ADC pretrigger channel flags selected
+* by pretriggMask from channel channel.
+*
+* @implements     Pdb_Adc_Ip_ClearAdcPretriggerFlags_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_ClearAdcPretriggerFlags(const uint32 Instance, const uint8 ChanIdx, const uint16 PretriggMask)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46();
+    /* Write 0 to clear */
+    Pdb_Adc_HwAcc_ClearAdcPretriggerFlags(Base, ChanIdx, PretriggMask);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetAdcPretriggerBackToBack
+* Description   : This function sets back to back mode for the selected
+* pretrigger on the given channel.
+*
+* @implements     Pdb_Adc_Ip_SetAdcPretriggerBackToBack_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetAdcPretriggerBackToBack(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+    DevAssert(PretriggIdx < PDB_DLY_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint32 Mask = (uint32)1u << PretriggIdx;
+
+    Mask = PDB_C1_BB(Mask);
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42();
+    Pdb_Adc_HwAcc_SetAdcPretriggerMask(Base, ChanIdx, Mask, Value);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetAdcPretriggerEnable
+* Description   : This function enables or disables the selected pretrigger on
+* the given channel.
+*
+* @implements     Pdb_Adc_Ip_SetAdcPretriggerEnable_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetAdcPretriggerEnable(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+    DevAssert(PretriggIdx < PDB_DLY_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint32 Mask = (uint32)1u << PretriggIdx;
+
+    Mask = PDB_C1_EN(Mask);
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43();
+    Pdb_Adc_HwAcc_SetAdcPretriggerMask(Base, ChanIdx, Mask, Value);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetAdcPretriggerDelayEnable
+* Description   : This function sets the delay enable value for the selected
+* pretrigger on the given channel.
+*
+* @implements     Pdb_Adc_Ip_SetAdcPretriggerDelayEnable_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetAdcPretriggerDelayEnable(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const boolean Value)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+    DevAssert(PretriggIdx < PDB_DLY_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint32 Mask = (uint32)1u << PretriggIdx;
+
+    Mask = PDB_C1_TOS(Mask);
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44();
+    Pdb_Adc_HwAcc_SetAdcPretriggerMask(Base, ChanIdx, Mask, Value);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44();
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_SetAdcPretriggerDelayValue
+* Description   : This function sets the pretrigger delay value.
+* Note: This function writes in an internal buffer. Depending on the
+* value of the LDMOD register, it might be necessary to call
+* Pdb_Adc_Ip_LoadRegValues in order to update the value of the register.
+* The value of the register can be changed only when the PDB module is enabled.
+*
+* @implements     Pdb_Adc_Ip_SetAdcPretriggerDelayValue_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_SetAdcPretriggerDelayValue(const uint32 Instance, const uint8 ChanIdx, const uint8 PretriggIdx, const uint16 DelayValue)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+    DevAssert(ChanIdx < PDB_CH_COUNT);
+    DevAssert(PretriggIdx < PDB_DLY_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+
+    Base->CH[ChanIdx].DLY[PretriggIdx] = PDB_DLY_DLY(DelayValue);
+}
+
+/*FUNCTION**********************************************************************
+*
+* Function Name : Pdb_Adc_Ip_DisableAndClearPdb
+* Description   : This function disables PDB module and clears all channels
+* configuration and status registers.
+*
+* @implements     Pdb_Adc_Ip_DisableAndClearPdb_Activity
+* END**************************************************************************/
+void Pdb_Adc_Ip_DisableAndClearPdb(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint8 ChanIdx;
+    const Pdb_Adc_Ip_PretriggersConfigType PdbPretriggsConfig = { 0u, 0u, 0u };
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40();
+    Pdb_Adc_HwAcc_DisablePdb(Base);
+    Pdb_Adc_HwAcc_SetContinuousMode(Base, FALSE);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40();
+
+    for (ChanIdx = 0U; ChanIdx < PDB_CH_COUNT; ChanIdx++)
+    {
+        PDB_ADC_ResetChannel(Base, ChanIdx, &PdbPretriggsConfig);
+    }
+}
+
+/*FUNCTION*********************************************************************
+ *
+ * Function Name : Pdb_Adc_Ip_IRQHandler
+ * Description   : Handles Pdb sequence error interrupt.
+ *
+ * @implements     Pdb_Adc_Ip_IRQHandler_Activity
+ *END*************************************************************************/
+/* The IAR build wants to see function prototypes */
+void Pdb_Adc_Ip_IRQHandler(const uint32 Instance);
+
+void Pdb_Adc_Ip_IRQHandler(const uint32 Instance)
+{
+#if (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON)
+    DevAssert(Instance < PDB_INSTANCE_COUNT);
+#endif /* (PDB_ADC_IP_DEV_ERROR_DETECT == STD_ON) */
+
+    PDB_Type * const Base = PdbBase[Instance];
+    uint8 ChanIdx;
+    uint16 SeqErrMask;
+
+    /* Check if the Pdb unit is initialized, if the interrupt is not NULL
+    * first since all channels use the same callback and if sequence error
+    * interrupt is enabled. */
+    if ((PdbAdcState[Instance].Init == TRUE) &&
+        (PdbAdcState[Instance].SeqErrNotification != NULL_PTR) &&
+        ((Base->SC & PDB_SC_PDBEIE_MASK) != 0u)\
+       )
+    {
+        for (ChanIdx = 0u; ChanIdx < PDB_CH_COUNT; ChanIdx++)
+        {
+            SeqErrMask = (uint16) ((Base->CH[ChanIdx].S & PDB_S_ERR_MASK) >> PDB_S_ERR_SHIFT);
+            if (SeqErrMask != 0u)
+            {
+                PdbAdcState[Instance].SeqErrNotification(ChanIdx, SeqErrMask);
+            }
+        }
+    }
+
+    for (ChanIdx = 0u; ChanIdx < PDB_CH_COUNT; ChanIdx++)
+    {
+        /* Clear all sequence error flags triggered from the current channel
+            * by writing 0 to raised bits. */
+        Base->CH[ChanIdx].S &= ~(PDB_S_ERR_MASK);
+    }
+}
+
+static inline void PDB_ADC_ResetChannel(PDB_Type * const Base, const uint8 ChanIdx, const Pdb_Adc_Ip_PretriggersConfigType * PdbPretriggsConfig)
+{
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45();
+    Pdb_Adc_HwAcc_ConfigAdcPretriggers(Base, ChanIdx, PdbPretriggsConfig);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45();
+
+    SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47();
+    Pdb_Adc_HwAcc_ClearAdcPretriggerFlags(Base, ChanIdx, 0xFFu);
+
+    /* Clear all sequence error flags. */
+    Base->CH[ChanIdx].S &= ~(PDB_S_ERR_MASK);
+    SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47();
+}
+
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+static void PDB_ADC_ConfigInstanceBackToBack_TrustedCall(const boolean InstanceBackToBackEnable)
+{
+    if(InstanceBackToBackEnable == TRUE)
+    {
+        IP_SIM->CHIPCTL |= SIM_CHIPCTL_PDB_BB_SEL_MASK;
+    }
+    else
+    {
+        IP_SIM->CHIPCTL &= ~SIM_CHIPCTL_PDB_BB_SEL_MASK;
+    }
+}
+
+static void PDB_ADC_ConfigInstanceBackToBack(const boolean InstanceBackToBackEnable)
+{
+#if (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call1param(PDB_ADC_ConfigInstanceBackToBack_TrustedCall,(InstanceBackToBackEnable));
+#else
+    PDB_ADC_ConfigInstanceBackToBack_TrustedCall(InstanceBackToBackEnable);
+#endif
+}
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+static void PDB_ADC_ConfigInterChannelBackToBack_TrustedCall(const uint32 Instance, const boolean InterChannelBackToBackEnable)
+{
+    if(InterChannelBackToBackEnable == TRUE)
+    {
+        if (0U == Instance)
+        {
+            IP_SIM->CHIPCTL |= SIM_CHIPCTL_PDB_BB_SEL_1_MASK;
+        }
+        else
+        {
+            IP_SIM->CHIPCTL |= SIM_CHIPCTL_PDB_BB_SEL_2_MASK;
+        }
+    }
+    else
+    {
+        if (0U == Instance)
+        {
+            IP_SIM->CHIPCTL &= ~(SIM_CHIPCTL_PDB_BB_SEL_1_MASK);
+        }
+        else
+        {
+            IP_SIM->CHIPCTL &= ~(SIM_CHIPCTL_PDB_BB_SEL_2_MASK);
+        }
+        
+    }
+}
+
+static void PDB_ADC_ConfigInterChannelBackToBack(const uint32 Instance, const boolean InterChannelBackToBackEnable)
+{
+#if (STD_ON == PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call2params(PDB_ADC_ConfigInterChannelBackToBack_TrustedCall,(Instance),(InterChannelBackToBackEnable));
+#else
+    PDB_ADC_ConfigInterChannelBackToBack_TrustedCall(Instance, InterChannelBackToBackEnable);
+#endif
+}
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+/** @} */

RTD/src/Pdb_Adc_Ip_Isr.c

@@ -0,0 +1,111 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip Pdb Adc IPL
+*   @{
+*/
+
+#include "OsIf.h"
+#include "Mcal.h"
+#include "Pdb_Adc_Ip_CfgDefines.h"
+/*******************************************************************************
+ *   Source file version information
+ ******************************************************************************/
+#define PDB_ADC_IP_VENDOR_ID_ISR_C                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_ISR_C    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_ISR_C               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_ISR_C               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_ISR_C               0
+/*******************************************************************************
+ *   File version checks
+ ******************************************************************************/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Pdb_Adc_Ip_Isr.c file and OsIf.h file are of the same Autosar version */
+    #if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != OSIF_AR_RELEASE_MINOR_VERSION)    \
+        )
+        #error "AutoSar Version Numbers of Pdb_Adc_Ip_Isr.c and OsIf.h are different"
+    #endif
+
+    /* Check if Pdb_Adc_Ip_Isr.c file and Mcal.h file are of the same Autosar version */
+    #if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != MCAL_AR_RELEASE_MINOR_VERSION)    \
+        )
+        #error "AutoSar Version Numbers of Pdb_Adc_Ip_Isr.c and Mcal.h are different"
+    #endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/* Check if Pdb_Adc_Ip_Isr.c file and Pdb_Adc_Ip_CfgDefines.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_ISR_C != PDB_ADC_IP_VENDOR_ID_CFGDEFINES_H)
+    #error "Pdb_Adc_Ip_Isr.c and Pdb_Adc_Ip_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_Isr.c file and Pdb_Adc_Ip_CfgDefines.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_ISR_C != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_ISR_C != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_ISR_C != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_Isr.c and Pdb_Adc_Ip_CfgDefines.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_Isr.c file and Pdb_Adc_Ip_CfgDefines.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_ISR_C != PDB_ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_ISR_C != PDB_ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_ISR_C != PDB_ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_Isr.c and Pdb_Adc_Ip_CfgDefines.h are different"
+#endif
+/******************************************************************************/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+extern void Pdb_Adc_Ip_IRQHandler(const uint32 Instance);
+
+ISR(Pdb_0_Isr); /* IAR requires prototypes. */
+ISR(Pdb_0_Isr)
+{
+    Pdb_Adc_Ip_IRQHandler(0UL);
+
+    EXIT_INTERRUPT();
+}
+
+#if (PDB_INSTANCE_COUNT >= 1)
+ISR(Pdb_1_Isr); /* IAR requires prototypes. */
+ISR(Pdb_1_Isr)
+{
+    Pdb_Adc_Ip_IRQHandler(1UL);
+
+    EXIT_INTERRUPT();
+}
+#endif /* (PDB_INSTANCE_COUNT >= 1) */
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+/** @} */

RTD/src/SchM_Adc.c

@@ -0,0 +1,3197 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : 
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup RTE_MODULE
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Std_Types.h"
+#include "Mcal.h"
+#include "OsIf.h"
+#include "SchM_Adc.h"
+#ifdef MCAL_TESTING_ENVIRONMENT
+#include "EUnit.h" /* EUnit Test Suite */
+#endif
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SCHM_ADC_AR_RELEASE_MAJOR_VERSION_C     4
+#define SCHM_ADC_AR_RELEASE_MINOR_VERSION_C     4
+#define SCHM_ADC_AR_RELEASE_REVISION_VERSION_C  0
+#define SCHM_ADC_SW_MAJOR_VERSION_C             1
+#define SCHM_ADC_SW_MINOR_VERSION_C             0
+#define SCHM_ADC_SW_PATCH_VERSION_C             0
+
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+#ifdef MCAL_PLATFORM_ARM
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        #define ISR_STATE_MASK     ((uint32)0x00000002UL)   /**< @brief DAIF bit I and F */
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        #define ISR_STATE_MASK     ((uint32)0x00000080UL)   /**< @brief CPSR bit I */
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+            #define ISR_STATE_MASK     ((uint32)0x000000FFUL)   /**< @brief BASEPRI[7:0] mask */
+        #else
+            #define ISR_STATE_MASK     ((uint32)0x00000001UL)   /**< @brief PRIMASK bit 0 */
+        #endif
+    #endif 
+#else
+    #ifdef MCAL_PLATFORM_S12
+        #define ISR_STATE_MASK     ((uint32)0x00000010L)   /**< @brief I bit of CCR */
+    #else
+        #define ISR_STATE_MASK     ((uint32)0x00008000UL)   /**< @brief EE bit of MSR */
+    #endif
+#endif
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+#ifdef MCAL_PLATFORM_ARM
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)3)
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
+    #else
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
+    #endif    
+#else
+    #ifdef MCAL_PLATFORM_S12
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
+    #else
+        #define ISR_ON(msr)            (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
+    #endif
+#endif
+
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+#define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
+#include "Rte_MemMap.h"
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_64[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_65[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_66[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_67[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_68[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_69[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_70[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_71[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_72[NUMBER_OF_CORES];
+static volatile uint32 msr_ADC_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_ADC_EXCLUSIVE_AREA_73[NUMBER_OF_CORES];
+
+#define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
+#include "Rte_MemMap.h"
+/*==================================================================================================
+*                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifndef _COSMIC_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Adc_schm_read_msr(void); 
+#endif /*ifndef _COSMIC_C_S32K1XX_*/
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+#if (defined(_GREENHILLS_C_S32K1XX_) || defined(_CODEWARRIOR_C_S32K1XX_))
+/*================================================================================================*/
+/** 
+* @brief   This macro returns the MSR register value (32 bits). 
+* @details This macro function implementation returns the MSR register value in r3 (32 bits). 
+*     
+* @pre  None
+* @post None
+* 
+*/
+#ifdef MCAL_PLATFORM_ARM
+#if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+    mrs x0, S3_3_c4_c2_1
+}
+#elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+    mrs r0, CPSR
+}
+#else
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+    mrs r0, BASEPRI
+#else
+    mrs r0, PRIMASK
+#endif
+}
+#endif
+#else
+#ifdef MCAL_PLATFORM_S12
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+   tfr ccr, d6
+}
+#else
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+    mfmsr r3
+}
+#endif
+#endif
+#endif /*#ifdef GHS||CW*/
+
+#ifdef _DIABDATA_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+#ifdef MCAL_PLATFORM_ARM
+uint32 Adc_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#else
+ASM_KEYWORD uint32 Adc_schm_read_msr(void)
+{
+    mfmsr r3
+}    
+#endif  /* MCAL_PLATFORM_ARM */
+
+#endif   /* _DIABDATA_C_S32K1XX_*/
+
+#ifdef _COSMIC_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+
+#ifdef MCAL_PLATFORM_S12
+    #define Adc_schm_read_msr()  ASM_KEYWORD("tfr ccr, d6")
+#else
+    #define Adc_schm_read_msr() ASM_KEYWORD("mfmsr r3")
+#endif
+
+#endif  /*Cosmic compiler only*/
+
+
+#ifdef _HITECH_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Adc_schm_read_msr(void)
+{
+    uint32 result;
+    __asm volatile("mfmsr %0" : "=r" (result) :);
+    return result;
+}
+
+#endif  /*HighTec compiler only*/
+ /*================================================================================================*/
+#ifdef _LINARO_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Adc_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#endif   /* _LINARO_C_S32K1XX_*/
+/*================================================================================================*/
+
+#ifdef _ARM_DS5_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Adc_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#endif   /* _ARM_DS5_C_S32K1XX_ */
+
+#ifdef _IAR_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Adc_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+   __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+#else
+   __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+#endif
+
+    return (uint32)reg_tmp;
+}
+#endif   /* _IAR_C_S32K1XX_ */
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+/*==================================================================================================
+*                                        GLOBAL FUNCTIONS
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_00(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_00[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_00[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_00[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_00(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_01(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_01[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_01[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_01[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_01(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_02(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_02[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_02[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_02[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_02(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_03(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_03[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_03[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_03[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_03(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_04(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_04[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_04[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_04[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_04(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_05(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_05[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_05[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_05[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_05(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_06(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_06[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_06[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_06[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_06(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_10(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_10[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_10[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_10[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_10(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_11(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_11[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_11[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_11[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_11(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_12(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_12[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_12[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_12[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_12(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_13(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_13[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_13[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_13[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_13(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_14(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_14[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_14[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_14[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_14(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_15(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_15[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_15[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_15[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_15(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_16(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_16[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_16[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_16[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_16(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_17(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_17[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_17[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_17[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_17(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_18(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_18[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_18[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_18[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_18(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_19(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_19[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_19[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_19[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_19(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_20(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_20[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_20[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_20[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_20(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_21(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_21[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_21[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_21[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_21(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_22(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_22[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_22[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_22[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_22(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_23(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_23[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_23[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_23[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_23(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_24(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_24[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_24[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_24[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_24(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_25(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_25[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_25[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_25[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_25(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_26(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_26[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_26[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_26[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_26(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_27(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_27[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_27[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_27[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_27(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_28(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_28[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_28[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_28[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_28(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_29(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_29[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_29[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_29[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_29(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_30(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_30[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_30[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_30[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_30(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_31(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_31[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_31[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_31[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_31(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_32(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_32[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_32[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_32[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_32(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_33(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_33[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_33[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_33[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_33(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_34(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_34[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_34[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_34[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_34(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_35(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_35[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_35[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_35[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_35(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_36(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_36[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_36[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_36[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_36(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_37(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_37[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_37[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_37[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_37(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_37[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_38(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_38[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_38[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_38[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_38(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_39(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_39[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_39[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_39[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_39(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_40(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_40[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_40[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_40[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_40(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_41(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_41[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_41[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_41[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_41(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_42(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_42[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_42[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_42[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_42(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_43(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_43[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_43[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_43[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_43(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_44(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_44[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_44[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_44[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_44(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_45(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_45[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_45[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_45[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_45(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_46(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_46[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_46[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_46[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_46(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_47(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_47[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_47[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_47[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_47(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_48(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_48[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_48[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_48[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_48(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_49(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_49[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_49[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_49[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_49(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_50(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_50[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_50[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_50[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_50(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_54(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_54[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_54[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_54[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_54(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_55(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_55[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_55[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_55[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_55(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_56(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_56[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_56[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_56[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_56(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_57(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_57[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_57[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_57[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_57(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_58(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_58[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_58[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_58[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_58(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_59(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_59[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_59[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_59[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_59(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_60(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_60[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_60[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_60[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_60(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_61(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_61[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_61[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_61[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_61(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_62(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_62[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_62[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_62[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_62(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_63(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_63[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_63[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_63[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_63(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_64(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_64[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_64[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_64[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_64(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_64[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_65[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_65[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_65[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_65[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_66(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_66[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_66[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_66[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_66(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_66[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_67(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_67[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_67[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_67[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_67(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_67[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_68(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_68[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_68[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_68[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_68(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_68[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_69(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_69[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_69[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_69[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_69(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_69[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_70(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_70[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_70[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_70[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_70(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_70[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_71(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_71[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_71[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_71[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_71(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_71[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_72(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_72[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_72[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_72[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_72(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_72[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_73(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_ADC_EXCLUSIVE_AREA_73[u32CoreId] = OsIf_Trusted_Call_Return(Adc_schm_read_msr);
+#else
+        msr_ADC_EXCLUSIVE_AREA_73[u32CoreId] = Adc_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_ADC_EXCLUSIVE_AREA_73[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]++;
+}
+
+void SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_73(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]--;
+    if ((ISR_ON(msr_ADC_EXCLUSIVE_AREA_73[u32CoreId]))&&(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+
+#ifdef MCAL_TESTING_ENVIRONMENT
+/** 
+@brief   This function checks that all entered exclusive areas were also exited. 
+@details This function checks that all entered exclusive areas were also exited. The check
+         is done by verifying that all reentry_guard_* static variables are back to the
+         zero value.
+    
+@param[in]     void       No input parameters
+@return        void       This function does not return a value. Test asserts are used instead. 
+
+@pre  None
+@post None
+
+@remarks Covers 
+@remarks Implements 
+*/
+void SchM_Check_adc(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_00 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_01 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_02 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_03 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_04 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_05 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_06 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_10 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_11 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_12 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_13 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_14 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_15 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_16 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_17 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_18 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_19 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_20 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_21 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_22 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_23 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_24 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_25 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_26 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_27 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_28 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_29 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_30 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_31 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_32 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_33 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_34 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_35 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_36 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_37[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_37 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_38 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_39 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_40 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_41 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_42 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_43 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_44 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_45 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_46 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_47 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_48 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_49 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_50 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_54 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_55 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_56 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_57 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_58 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_59 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_60 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_61 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_62 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_63 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_64[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_64 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_65[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_65 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_66[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_66 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_67[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_67 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_68[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_68 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_69[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_69 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_70[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_70 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_71[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_71 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_72[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_72 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId]);
+    reentry_guard_ADC_EXCLUSIVE_AREA_73[u32CoreId] = 0UL; /*reset reentry_guard_ADC_EXCLUSIVE_AREA_73 for the next test in the suite*/
+
+
+}
+#endif /*MCAL_TESTING_ENVIRONMENT*/
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

S32K146_4G.mex

@@ -229,6 +229,16 @@
                   <data type="Version">1.0.0</data>
                </feature>
             </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.adc" description="工具链/IDE工程中未找到adc。工程不会被编译！" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.adc" description="工具链/IDE工程不支持adc版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">1.0.0</data>
+               </feature>
+            </dependency>
          </dependencies>
          <peripherals_profile>
             <processor_version>0.0.0</processor_version>
@@ -421,6 +431,186 @@
                         </struct>
                      </config_set>
                   </instance>
+                  <instance name="Adc_1" uuid="e3846b95-5ea4-4dea-a75a-542ba0492199" type="Adc" type_id="Adc" mode="autosar" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="Adc" quick_selection="defaultConfig">
+                        <setting name="Name" value="AdcUserCfg"/>
+                        <struct name="ConfigTimeSupport">
+                           <setting name="POST_BUILD_VARIANT_USED" value="false"/>
+                           <setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-POST-BUILD"/>
+                        </struct>
+                        <struct name="AdcConfigSet">
+                           <setting name="Name" value="AdcConfigSet"/>
+                           <array name="AdcHwUnit">
+                              <struct name="0">
+                                 <setting name="Name" value="AdcHwUnit_0"/>
+                                 <setting name="AdcHwUnitId" value="ADC0"/>
+                                 <setting name="AdcLogicalUnitId" value="0"/>
+                                 <setting name="AdcTransferType" value="ADC_INTERRUPT"/>
+                                 <array name="AdcDmaChannelId"/>
+                                 <array name="AdcCountingDmaChannelId"/>
+                                 <array name="AdcClockSource"/>
+                                 <array name="AdcPrescale"/>
+                                 <setting name="AdcAltPrescale" value="2"/>
+                                 <setting name="AdcCalibrationPrescale" value="8"/>
+                                 <setting name="AdcHwUnitUsrOffset" value="0"/>
+                                 <setting name="AdcHwUnitUsrGain" value="4"/>
+                                 <setting name="AdcHwUnitResolution" value="RESOLUTION_12"/>
+                                 <array name="AdcNormalConvTimings"/>
+                                 <array name="AdcAlternateConvTimings"/>
+                                 <struct name="PdbHwUnit">
+                                    <setting name="Name" value="PdbHwUnit"/>
+                                    <setting name="AdcPdbPrescalerDividerSelect" value="0"/>
+                                    <setting name="AdcPdbMultiplicationFactorSelect" value="0"/>
+                                    <setting name="AdcPdbCounterPeriod" value="65535"/>
+                                    <setting name="AdcPdbErrorNotification" value="NULL_PTR"/>
+                                 </struct>
+                                 <array name="AdcChannel">
+                                    <struct name="0">
+                                       <setting name="Name" value="AdcChannel_0"/>
+                                       <setting name="AdcLogicalChannelId" value="0"/>
+                                       <setting name="AdcChannelName" value="SE0_ADCH0"/>
+                                       <setting name="AdcChannelId" value="0"/>
+                                       <array name="AdcChannelConvTime"/>
+                                       <array name="AdcChannelLimitCheck"/>
+                                       <array name="AdcChannelHighLimit"/>
+                                       <array name="AdcChannelLowLimit"/>
+                                       <array name="AdcChannelRangeSelect"/>
+                                       <array name="AdcChannelRefVoltsrcHigh"/>
+                                       <array name="AdcChannelRefVoltsrcLow"/>
+                                       <array name="AdcChannelResolution"/>
+                                       <array name="AdcChannelSampTime"/>
+                                    </struct>
+                                 </array>
+                                 <array name="AdcGroup">
+                                    <struct name="0">
+                                       <setting name="Name" value="AdcGroup_0"/>
+                                       <setting name="AdcGroupAccessMode" value="ADC_ACCESS_MODE_SINGLE"/>
+                                       <setting name="AdcGroupConversionMode" value="ADC_CONV_MODE_ONESHOT"/>
+                                       <setting name="AdcGroupConversionType" value="ADC_CONV_TYPE_NORMAL"/>
+                                       <setting name="AdcGroupId" value="0"/>
+                                       <array name="AdcGroupPriority"/>
+                                       <array name="AdcGroupReplacement"/>
+                                       <setting name="AdcGroupTriggSrc" value="ADC_TRIGG_SRC_SW"/>
+                                       <setting name="AdcGroupHwTriggerSource" value=""/>
+                                       <array name="AdcHwTrigSignal"/>
+                                       <array name="AdcHwTrigTimer">
+                                          <setting name="0" value="10"/>
+                                       </array>
+                                       <array name="AdcNotification"/>
+                                       <setting name="AdcExtraNotification" value="NULL_PTR"/>
+                                       <setting name="AdcStreamingBufferMode" value="ADC_STREAM_BUFFER_LINEAR"/>
+                                       <setting name="AdcEnableOptimizeDmaStreamingGroups" value="false"/>
+                                       <setting name="AdcEnableHalfInterrupt" value="false"/>
+                                       <setting name="AdcStreamingNumSamples" value="1"/>
+                                       <setting name="AdcStreamResultGroup" value="false"/>
+                                       <setting name="AdcEnableChDisableChGroup" value="false"/>
+                                       <setting name="AdcWithoutInterrupts" value="false"/>
+                                       <setting name="AdcWithoutDma" value="false"/>
+                                       <setting name="AdcExtDMAChanEnable" value="false"/>
+                                       <setting name="AdcGroupInBacktoBackMode" value="true"/>
+                                       <setting name="AdcGroupUsesChannelDelays" value="false"/>
+                                       <setting name="AdcDelayNextPdb" value="0"/>
+                                       <setting name="AdcPdbPeriodContinuousMode" value="1000"/>
+                                       <array name="AdcChannelDelay"/>
+                                       <struct name="AdcGroupConversionConfiguration">
+                                          <setting name="Name" value="AdcGroupConversionConfiguration"/>
+                                          <setting name="AdcGroupHardwareAverageEnable" value="false"/>
+                                          <setting name="AdcGroupHardwareAverageSelect" value="SAMPLES_4"/>
+                                          <setting name="AdcGroupSampleTimeDuration" value="20"/>
+                                       </struct>
+                                       <struct name="AdcAlternateGroupConvTimings">
+                                          <setting name="Name" value="AdcAlternateGroupConvTimings"/>
+                                          <setting name="AdcGroupAltHardwareAverageEnable" value="false"/>
+                                          <setting name="AdcGroupAltHardwareAverageSelect" value="SAMPLES_4"/>
+                                          <setting name="AdcGroupAltSampleTimeDuration" value="1"/>
+                                       </struct>
+                                       <array name="AdcGroupDefinition">
+                                          <setting name="0" value="/Adc_1/AdcUserCfg/AdcConfigSet/AdcHwUnit_0/AdcChannel_0"/>
+                                       </array>
+                                       <array name="AdcGroupEcucPartitionRef"/>
+                                    </struct>
+                                 </array>
+                                 <array name="AdcHwUnitEcucPartitionRef"/>
+                              </struct>
+                           </array>
+                           <array name="AdcHwTrigger">
+                              <struct name="0">
+                                 <setting name="Name" value="AdcHwTrigger_0"/>
+                                 <setting name="AdcHwTrigSrc" value="TRIGGER_IN0"/>
+                              </struct>
+                           </array>
+                        </struct>
+                        <struct name="AdcGeneral">
+                           <setting name="Name" value="AdcGeneral"/>
+                           <setting name="AdcDeInitApi" value="true"/>
+                           <setting name="AdcDevErrorDetect" value="false"/>
+                           <setting name="AdcEnableLimitCheck" value="true"/>
+                           <setting name="AdcEnableQueuing" value="true"/>
+                           <setting name="AdcPriorityQueueMaxDepth" value="1"/>
+                           <setting name="AdcEnableStartStopGroupApi" value="true"/>
+                           <setting name="AdcGrpNotifCapability" value="true"/>
+                           <setting name="AdcHwTriggerApi" value="false"/>
+                           <setting name="AdcPriorityImplementation" value="ADC_PRIORITY_NONE"/>
+                           <setting name="AdcReadGroupApi" value="true"/>
+                           <setting name="AdcResultAlignment" value="ADC_ALIGN_RIGHT"/>
+                           <setting name="AdcVersionInfoApi" value="true"/>
+                           <array name="AdcLowPowerStatesSupport"/>
+                           <array name="AdcPowerStateAsynchTransitionMode"/>
+                           <array name="AdcEcucPartitionRef"/>
+                           <array name="AdcKernelEcucPartitionRef"/>
+                           <array name="AdcPowerStateConfig"/>
+                        </struct>
+                        <array name="AdcInterrupt">
+                           <struct name="0">
+                              <setting name="Name" value="AdcInterrupt_0"/>
+                              <setting name="AdcInterruptSource" value="ADC0_COCO"/>
+                              <setting name="AdcInterruptEnable" value="true"/>
+                           </struct>
+                        </array>
+                        <struct name="AdcPublishedInformation">
+                           <setting name="Name" value="AdcPublishedInformation"/>
+                           <setting name="AdcChannelValueSigned" value="false"/>
+                           <setting name="AdcGroupFirstChannelFixed" value="false"/>
+                           <setting name="AdcMaxChannelResolution" value="12"/>
+                        </struct>
+                        <struct name="CommonPublishedInformation">
+                           <setting name="Name" value="CommonPublishedInformation"/>
+                           <setting name="ArReleaseMajorVersion" value="4"/>
+                           <setting name="ArReleaseMinorVersion" value="4"/>
+                           <setting name="ArReleaseRevisionVersion" value="0"/>
+                           <setting name="ModuleId" value="123"/>
+                           <setting name="SwMajorVersion" value="1"/>
+                           <setting name="SwMinorVersion" value="0"/>
+                           <setting name="SwPatchVersion" value="0"/>
+                           <setting name="VendorApiInfix" value=""/>
+                           <setting name="VendorId" value="43"/>
+                        </struct>
+                        <struct name="AutosarExt">
+                           <setting name="Name" value="AutosarExt"/>
+                           <setting name="AdcTimeoutMethod" value="OSIF_COUNTER_DUMMY"/>
+                           <setting name="AdcTimeoutVal" value="10000"/>
+                           <setting name="AdcIplDevErrorDetect" value="false"/>
+                           <setting name="PdbDevErrorDetect" value="false"/>
+                           <setting name="AdcMulticoreSupport" value="false"/>
+                           <setting name="AdcEnableGroupDependentChannelNames" value="false"/>
+                           <setting name="AdcBypassAbortChainCheck" value="false"/>
+                           <setting name="AdcConvTimeOnce" value="false"/>
+                           <setting name="AdcOptimizeOneShotHwTriggerConversions" value="false"/>
+                           <setting name="AdcOptimizeDmaStreamingGroups" value="false"/>
+                           <setting name="AdcContinuousWithoutInterrupt" value="false"/>
+                           <setting name="AdcEnableChDisableChApi" value="false"/>
+                           <setting name="AdcEnableInitialNotification" value="false"/>
+                           <setting name="AdcEnableDmaTrasferMode" value="false"/>
+                           <setting name="AdcEnableUserModeSupport" value="false"/>
+                           <setting name="AdcEnableSimSupplyMonitor" value="false"/>
+                           <setting name="AdcEnableSetChannel" value="false"/>
+                           <setting name="AdcEnableDualClockMode" value="false"/>
+                           <setting name="AdcEnableCalibration" value="false"/>
+                           <setting name="AdcEnableReadRawDataApi" value="false"/>
+                           <setting name="AdcEnableGroupStreamingResultReorder" value="false"/>
+                        </struct>
+                     </config_set>
+                  </instance>
                </instances>
             </functional_group>
          </functional_groups>

generate/include/Adc_Cfg.h

@@ -0,0 +1,164 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_CFG_H
+#define ADC_CFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver_config Adc Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_CfgDefines.h"
+#include "Adc_Types.h"
+#include "Adc_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_CFG                       43
+#define ADC_AR_RELEASE_MAJOR_VERSION_CFG        4
+#define ADC_AR_RELEASE_MINOR_VERSION_CFG        4
+#define ADC_AR_RELEASE_REVISION_VERSION_CFG     0
+#define ADC_SW_MAJOR_VERSION_CFG                1
+#define ADC_SW_MINOR_VERSION_CFG                0
+#define ADC_SW_PATCH_VERSION_CFG                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if header file and Adc_CfgDefines header file are of the same vendor */
+#if (ADC_VENDOR_ID_CFG != ADC_VENDOR_ID_CFGDEFINES_H)
+    #error "Adc_Cfg.h and Adc_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if header file and Adc_CfgDefines header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_CFG != ADC_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_CFG != ADC_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_CFG != ADC_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Cfg.h and Adc_CfgDefines.h are different"
+#endif
+
+/* Check if header file and Adc Cfg header file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_CFG != ADC_SW_MAJOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_MINOR_VERSION_CFG != ADC_SW_MINOR_VERSION_CFGDEFINES_H) || \
+     (ADC_SW_PATCH_VERSION_CFG != ADC_SW_PATCH_VERSION_CFGDEFINES_H) \
+    )
+    #error "Software Version Numbers of Adc_Cfg.h and Adc_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Cfg.h file and Adc_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_CFG != ADC_VENDOR_ID_TYPES_H)
+    #error "Adc_Cfg.h and Adc_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Cfg.h file and Adc_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_CFG != ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_CFG != ADC_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_CFG != ADC_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Cfg.h and Adc_Types.h are different"
+#endif
+
+/* Check if Adc_Cfg.h file and Adc_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_CFG != ADC_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_CFG != ADC_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_CFG != ADC_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Cfg.h and Adc_Types.h are different"
+#endif
+
+/* Check if source file and Adc configuration header file are of the same vendor */
+#if (ADC_VENDOR_ID_VS_0_PBCFG_H != ADC_VENDOR_ID_CFG)
+    #error "Adc_VS_0_PBcfg.h and Adc_Cfg.h have different vendor IDs"
+#endif
+/* Check if header file and Adc configuration header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Adc_VS_0_PBcfg.h and Adc_Cfg.h are different"
+#endif
+/* Check if header file and Adc configuration header file are of the same software version */
+#if ((ADC_SW_MAJOR_VERSION_VS_0_PBCFG_H != ADC_SW_MAJOR_VERSION_CFG) || \
+     (ADC_SW_MINOR_VERSION_VS_0_PBCFG_H != ADC_SW_MINOR_VERSION_CFG) || \
+     (ADC_SW_PATCH_VERSION_VS_0_PBCFG_H != ADC_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Adc_VS_0_PBcfg.h and Adc_Cfg.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+#define ADC_CONFIG_EXT \
+ ADC_CONFIG_VS_0_PB \
+
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_CFG_H */
+

generate/include/Adc_CfgDefines.h

@@ -0,0 +1,459 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_CFGDEFINES_H
+#define ADC_CFGDEFINES_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver_config Adc Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_CFGDEFINES_H                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H       4
+#define ADC_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H       4
+#define ADC_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H    0
+#define ADC_SW_MAJOR_VERSION_CFGDEFINES_H               1
+#define ADC_SW_MINOR_VERSION_CFGDEFINES_H               0
+#define ADC_SW_PATCH_VERSION_CFGDEFINES_H               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/**
+* @brief          CMR register not present on this platform.
+*/
+#define ADC_CMR_REGISTER_NOT_SUPPORTED
+
+/**
+* @brief          Specifies if Current channel is used
+*/
+#define ADC_CURRENT_CHANNEL_USED
+
+/**
+* @brief          Multicore feature is disabled on this platform.
+*/
+#define ADC_MULTICORE_SUPPORT               (STD_OFF)
+
+/**
+* @brief          Number of configured partitions.
+*/
+#define ADC_MAX_PARTITIONS                  (1U)
+
+/**
+* @brief          ADC unit 0 available
+*/
+#define ADC_UNIT_0                          (0U)
+
+/**
+* @brief          ADC unit 1 available
+*/
+#define ADC_UNIT_1                          (1U)
+
+
+/**
+* @brief           Adds/removes ((STD_ON)/(STD_OFF)) the services Adc_EnableHardwareTrigger() and Adc_DisableHardwareTrigger() from the code.
+*/
+#define ADC_HW_TRIGGER_API                  (STD_ON)
+
+/**
+* @brief           AdcSetHwUnitPowerMode api enabled/disabled ((STD_ON)/(STD_OFF)).
+*/
+#define ADC_SET_HW_UNIT_POWER_MODE_API                    (STD_OFF)
+
+/**
+* @brief           Enables or disables limit checking feature in the ADC driver.
+*/
+#define ADC_ENABLE_LIMIT_CHECK              (STD_OFF)
+
+/**
+* @brief           Group notification mechanism is/is not ((STD_ON)/(STD_OFF)) available at runtime.
+*/
+#define ADC_GRP_NOTIF_CAPABILITY            (STD_ON)
+
+/**
+* @brief           Type of prioritization mechanism ADC_PRIORITY_HW, ADC_PRIORITY_HW_SW and ADC_PRIORITY_NONE.
+*/
+/* SWS_Adc_00522 */
+#define ADC_PRIORITY_HW                     (0U)
+#define ADC_PRIORITY_HW_SW                  (1U)
+#define ADC_PRIORITY_NONE                   (2U)
+
+/**
+* @brief           Priority implementation.
+*/
+#define ADC_PRIORITY_IMPLEMENTATION         (ADC_PRIORITY_NONE)
+
+/**
+* @brief           Type of alignment mechanism ADC_ALIGN_RIGHT, ADC_ALIGN_LEFT.
+*/
+/* SWS_Adc_00525 */
+#define ADC_ALIGN_RIGHT                     (0U)
+#define ADC_ALIGN_LEFT                      (1U)
+
+/**
+* @brief           Result Alignment.
+*/
+#define ADC_RESULT_ALIGNMENT                (ADC_ALIGN_RIGHT)
+
+/**
+* @brief         This is a timeout value which is used to wait until
+*                  - the conversion is not aborted.
+*                  - ADC hardware is not entered in power down state.
+*                  - ADC hardware is not entered in idle state.
+*/
+#define ADC_TIMEOUT_COUNTER                 (100000UL)
+
+/**
+* @brief           Specifies for reducing the number of interrupts for streaming groups
+*/
+#define ADC_OPTIMIZE_DMA_STREAMING_GROUPS   (STD_OFF)
+
+
+
+/**
+* @brief           Specifies to optimize conversions for hw triggered, one shot group.
+*/
+#define ADC_OPTIMIZE_ONESHOT_HW_TRIGGER     (STD_OFF)
+
+/**
+* @brief           Specifies to configure BCTU/CTU list at initialization for ctu hardware trigger mode groups.
+*/
+#define ADC_CTU_HW_TRIGGER_OPTIMIZATION     (STD_OFF)
+
+/**
+ * @brief   Define the number of maximum hardware unit configured
+ */
+#define ADC_MAX_HW_UNITS_CFG                      (1U)
+
+/**
+* @brief           Add/Remove Autosar Extension Adc_EnableChannel() and Adc_DisableChannel() api.
+*/
+#define ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API      (STD_OFF)
+
+/**
+* @brief           Get injected conversion status api enabled/disabled (STD_ON/STD_OFF).
+*/
+#define ADC_GET_INJECTED_CONVERSION_STATUS_API    (STD_OFF)
+
+/**
+* @brief           Adc transfer type.
+*/
+#ifdef ADC_DMA_SUPPORTED
+#define ADC_DMA                             (0U)
+#endif /* ADC_DMA_SUPPORTED */
+#define ADC_INTERRUPT                       (1U)
+
+/**
+* @brief          Add/Remove Autosar Extension Adc_SetClockMode().
+*/
+#define ADC_DUAL_CLOCK_MODE                       (STD_OFF)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the service Adc_Calibration() from the code.
+*/
+#define ADC_CALIBRATION                           (STD_ON)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the service Adc_SetChannel() from the code.
+*/
+#define ADC_SETCHANNEL_API                        (STD_OFF)
+
+/**
+* @brief          Extra group notification mechanism is/is not ((STD_ON)/(STD_OFF)) available at runtime.
+*/
+#define ADC_ENABLE_INITIAL_NOTIFICATION           (STD_OFF)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the service Adc_SelfTest() from the code.
+*/
+#define ADC_SELF_TEST                             (STD_OFF)
+
+/**
+* @brief           ADC Configure Threshold enabled/disabled (STD_ON/STD_OFF).
+*/
+#define ADC_ENABLE_CONFIGURE_THRESHOLD_NONAUTO_API  (STD_OFF)
+
+/**
+* @brief           Switch to enable/disable the API for the CPR_RTD_00056, CPR_RTD_00057, CPR_RTD_00058, CPR_RTD_00059 and CPR_RTD_00060.
+*/
+#define ADC_CTU_CONTROL_MODE_EXTRA_APIS           (STD_OFF)
+
+/**
+* @brief           This switch is used to enable the hardware trigger Autosar Extension API for the CPR_RTD_00037, CPR_RTD_00038, CPR_RTD_00039, CPR_RTD_00040, CPR_RTD_00041.
+*/
+#define ADC_ENABLE_CTUTRIG_NONAUTO_API            (STD_OFF)
+
+/**
+* @brief           Switch to enable/disable the API for the CPR-MCAL-726, CPR-MCAL-727, CPR-MCAL-728.
+*/
+#define ADC_ENABLE_CTU_CONTROL_MODE_API           (STD_OFF)
+
+/**
+* @brief           Switch to enable/disable the API for Tempsense.
+*/
+#define ADC_ENABLE_TEMPSENSE_API                  (STD_OFF)
+#define ADC_POWER_ON_TEMPSENSE                    (STD_OFF)
+
+/**
+* @brief           Enable the read of raw data API (CPR_RTD_00508).
+*/
+#define ADC_ENABLE_READ_RAW_DATA_API              (STD_OFF)
+
+/**
+* @brief           Enable Group Streaming Result as multiple set.
+*/
+#define ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER (STD_OFF)
+
+/**
+* @brief IRQ definition
+*/
+
+#define ADC_UNIT_1_ISR_USED
+
+/**
+* @brief           max queue depth configured across all configset.
+*/
+#define ADC_QUEUE_MAX_DEPTH_MAX             (1U)
+
+/**
+* @brief           max number of groups configured across all configset.
+*/
+#define ADC_MAX_GROUPS                      (2U)
+
+/**
+* @brief           Invalid Hardware group ID to determine there is no ongoing hardware group
+*/
+#define ADC_INVALID_HW_GROUP_ID             (0xFFFFU)
+
+#ifdef ADC_DMA_SUPPORTED
+/**
+* @brief           Maximum number of channels across all hardware units.
+*/
+#define ADC_MAX_CHANNEL_PER_HW_UNIT         (7U)
+#endif /* ADC_DMA_SUPPORTED */
+
+/**
+* @brief           Software injected conversion use
+*/
+#define ADC_SOFTWARE_INJECTED_CONVERSIONS_USED    (STD_OFF)
+
+/**
+* @brief          Configuration Precompile variant.
+* @details        Configuration Precompile variant.
+*/
+#define ADC_PRECOMPILE_SUPPORT                    (STD_OFF)
+
+/**
+* @brief          Development error detection enabled/disabled ((STD_ON)/(STD_OFF)).
+*/
+#define ADC_DEV_ERROR_DETECT                      (STD_ON)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the service Adc_GetVersionInfo() from the code.
+*/
+#define ADC_VERSION_INFO_API                      (STD_ON)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the service Adc_DeInit() from the code.
+*/
+#define ADC_DEINIT_API                            (STD_ON)
+
+/**
+* @brief          Add/remove ((STD_ON)/(STD_OFF)) the services Adc_StartGroupConversion()and Adc_StopGroupConversion() from the code.
+*/
+#define ADC_ENABLE_START_STOP_GROUP_API           (STD_ON)
+
+/**
+* @brief          Add/Remove the services Adc_ReadGroup() from the code.
+*/
+#define ADC_READ_GROUP_API                        (STD_ON)
+
+/**
+* @brief          Add/Remove One time setting of Conversion time registers from Init() function.
+*/
+#define ADC_SET_ADC_CONV_TIME_ONCE                (STD_OFF)
+
+/**
+* @brief   Switch to enable that power state mode is supported
+*
+*/
+#define ADC_POWER_STATE_SUPPORTED                 (STD_OFF)
+
+#if (ADC_POWER_STATE_SUPPORTED == STD_ON)
+/**
+* @brief   Enable/Disable the asynchronous power mode
+*
+*/
+#define ADC_POWER_STATE_ASYNCH_MODE_SUPPORTED     (STD_OFF)
+#endif /* (ADC_POWER_STATE_SUPPORTED == STD_ON) */
+
+/**
+* @brief           This switch is used to enable the queue.
+*/
+#define ADC_ENABLE_QUEUING                        (STD_ON)
+
+/**
+* @brief           This switch is used to enable the Autosar Extension ADC performance optimization feature.
+*/
+#define ADC_BYPASS_ABORT_CHAIN_CHECK              (STD_OFF)
+
+/**
+* @brief           Symbolic names of ADC Hardware units.
+* @details         Values generated are the ADC Logical Unit ID selected from configurator.
+*                  These defines are recommended to be used with any ADC driver API that takes as input parameter Adc Unit.
+*/
+#define AdcHwUnit_0                               (0U)
+
+/**
+* @brief          Adc channel id.
+*/
+#define ADC_ID_CHANNEL_U8(Id)                     (Id)
+
+/**
+* @brief          macros to simplify access to structures.
+* @details        Streaming number of samples
+*/
+#define ADC_STREAMING_NUM_SAMPLES(num)            (num)
+
+/**
+* @brief          Adc group priority.
+*/
+#define ADC_GROUP_PRIORITY(Priority)              (Priority)
+
+/**
+* @brief           AUTOSAR Symbolic names of channels on all HW units with encoded value.
+* @details         Bit fields [12-15]:  HW unit physical id
+*                  Bit fields [0-11]:   Logical id of channel in HW unit (used in Adc_EnableChannel()/Adc_DisableChannel())
+*/
+#define Adc1_VREFH                       (0x1000U)
+#define Adc1_BANDGAP                       (0x1001U)
+#define Adc1_VREFL                       (0x1002U)
+#define PTB13_ADC1_SE8_MCU_CC1                       (0x1003U)
+#define PTB12_ADC1_SE7_MCU_TP1                       (0x1004U)
+#define PTD4_ADC1_SE6_MCU_TP2                       (0x1005U)
+#define PTE6_ADC1_SE11_MCU_SYS_TP                       (0x1006U)
+
+/**
+* @brief          Definitions used for extracting the ADC Logical Unit Id and logical id of channels in each unit from equivalent channel symbolic name
+*/
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+#define ADC_CHANNEL_SYMBOLIC_NAME_MASK_CHANNEL_ID_U16           (0xFFFU)
+#define ADC_CHANNEL_SYMBOLIC_NAME_SHIFT_HW_UNIT_ID_U16          (12U)
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+
+/**
+* @brief           Autosar Extension symbolic names of channels per groups, on all HW units, with value set to channel index in the group.
+*/
+#define AdcGroupSoftwareOneShot_Adc1_VREFH                   (0U)
+#define AdcGroupSoftwareOneShot_Adc1_BANDGAP                   (1U)
+#define AdcGroupSoftwareOneShot_Adc1_VREFL                   (2U)
+#define AdcGroupSoftwareOneShot_PTE6_ADC1_SE11_MCU_SYS_TP                   (3U)
+#define AdcGroupSoftwareOneShot_PTD4_ADC1_SE6_MCU_TP2                   (4U)
+#define AdcGroupSoftwareOneShot_PTB12_ADC1_SE7_MCU_TP1                   (5U)
+#define AdcGroupSoftwareOneShot_PTB13_ADC1_SE8_MCU_CC1                   (6U)
+#define AdcGroupHardwareOneShot_Adc1_VREFH                   (0U)
+#define AdcGroupHardwareOneShot_Adc1_BANDGAP                   (1U)
+#define AdcGroupHardwareOneShot_Adc1_VREFL                   (2U)
+#define AdcGroupHardwareOneShot_PTE6_ADC1_SE11_MCU_SYS_TP                   (3U)
+#define AdcGroupHardwareOneShot_PTD4_ADC1_SE6_MCU_TP2                   (4U)
+#define AdcGroupHardwareOneShot_PTB12_ADC1_SE7_MCU_TP1                   (5U)
+#define AdcGroupHardwareOneShot_PTB13_ADC1_SE8_MCU_CC1                   (6U)
+
+/**
+* @brief           Symbolic names of groups.
+*/
+
+#define AdcGroupSoftwareOneShot                                (0U)
+#define AdcGroupHardwareOneShot                                (1U)
+
+/**
+* @brief           Symbolic names of groups - ecuc 2108 compliant.
+*/
+
+#define AdcConf_AdcGroup_AdcGroupSoftwareOneShot               (0U)
+#define AdcConf_AdcGroup_AdcGroupHardwareOneShot               (1U)
+
+/**
+* @brief          ADC Global Validation.
+*/
+#define ADC_VALIDATE_GLOBAL_CALL         (ADC_DEV_ERROR_DETECT)
+#define ADC_VALIDATE_CALL_AND_GROUP      (ADC_DEV_ERROR_DETECT)
+#define ADC_VALIDATE_CALL_AND_UNIT       (ADC_DEV_ERROR_DETECT)
+#define ADC_VALIDATE_PARAMS              (ADC_DEV_ERROR_DETECT)
+#define ADC_VALIDATE_NOTIFY_CAPABILITY   (ADC_DEV_ERROR_DETECT)
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_CFGDEFINES_H */
+

generate/include/Adc_Ip_Cfg.h

@@ -0,0 +1,140 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_CFG_H
+#define ADC_IP_CFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip_config Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ip_Types.h"
+#include "Adc_Ip_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_IP_VENDOR_ID_CFG_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H    0
+#define ADC_IP_SW_MAJOR_VERSION_CFG_H               1
+#define ADC_IP_SW_MINOR_VERSION_CFG_H               0
+#define ADC_IP_SW_PATCH_VERSION_CFG_H               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_Types.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_CFG_H != ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Adc_Ip_Cfg.h and Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_Types.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H != ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H != ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_Cfg.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_Types.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_CFG_H != ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_MINOR_VERSION_CFG_H != ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_PATCH_VERSION_CFG_H != ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_Cfg.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_CFG_H != ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Adc_Ip_Cfg.h and Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H != ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H != ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_Cfg.h and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ip_Cfg.h file and Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_CFG_H != ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_SW_MINOR_VERSION_CFG_H != ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_SW_PATCH_VERSION_CFG_H != ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_Cfg.h and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IP_CFG_H */
+

generate/include/Adc_Ip_CfgDefines.h

@@ -0,0 +1,159 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_CFGDEFINES_H
+#define ADC_IP_CFGDEFINES_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip_config Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/* Important Note: The header warapper file depends on header platform and can not be used independently.
+*  Do not change #include order in this file */
+#include "S32K146_ADC.h"
+#include "S32K146_SIM.h"
+#include "Adc_Ip_HeaderWrapper_S32K14x_Extended.h"
+#include "OsIf.h"
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_CFGDEFINES_H                      43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H       4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H       4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H    0
+#define ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H               1
+#define ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H               0
+#define ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H               0
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Adc_Ip_CfgDefines.h file and Adc_Ip_HeaderWrapper_S32K14x_Extended.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_CFGDEFINES_H != ADC_IP_VENDOR_ID_HEADERWRAPPER_S32K14X_EXTENDED_H)
+    #error "Adc_Ip_CfgDefines.h and Adc_Ip_HeaderWrapper_S32K14x_Extended.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_CfgDefines.h file and Adc_Ip_HeaderWrapper_S32K14x_Extended.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H != ADC_IP_AR_RELEASE_MINOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H != ADC_IP_AR_RELEASE_REVISION_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_CfgDefines.h and Adc_Ip_HeaderWrapper_S32K14x_Extended.h are different"
+#endif
+
+/* Check if Adc_Ip_CfgDefines.h file and Adc_Ip_HeaderWrapper_S32K14x_Extended.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H != ADC_IP_SW_MAJOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) || \
+     (ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H != ADC_IP_SW_MINOR_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) || \
+     (ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H != ADC_IP_SW_PATCH_VERSION_HEADERWRAPPER_S32K14X_EXTENDED_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_CfgDefines.h and Adc_Ip_HeaderWrapper_S32K14x_Extended.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check AutoSar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H != OSIF_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_CfgDefines.h and OsIf.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+#define ADC_IP_DEV_ERROR_DETECT                (STD_OFF)
+#define ADC_IP_TIMEOUT_TYPE                    (OSIF_COUNTER_DUMMY)
+#define ADC_IP_TIMEOUT_VAL                     (100000UL)
+#define ADC_IP_ENABLE_USER_MODE_SUPPORT        (STD_OFF)
+#define ADC_IP_SUPPLY_MONITORING_ENABLED       (STD_OFF)
+#define ADC_IP_ENABLE_SIM_SOURCE_SELECTION     (STD_OFF)
+
+/*! @brief ADC default Sample Time from RM */
+#define ADC_IP_DEFAULT_SAMPLE_TIME             (0x0CU)
+/*! @brief ADC default User Gain from RM */
+#define ADC_IP_DEFAULT_USER_GAIN               (0x04U)
+
+/*! @brief ADC Max external channel ID */
+#define FEATURE_ADC_MAX_EXT_CHAN_ID            (15U)
+/*! @brief ADC has external channels */
+#define FEATURE_ADC_HAS_CHANNEL_2              (1U)
+#define FEATURE_ADC_HAS_CHANNEL_8              (1U)
+#define FEATURE_ADC_HAS_CHANNEL_9              (1U)
+
+
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IP_CFGDEFINES_H */
+

generate/include/Adc_Ip_VS_0_PBcfg.h

@@ -0,0 +1,118 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IP_VS_0_PBCFG_H
+#define ADC_IP_VS_0_PBCFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip_config Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ip_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_VS_0_PBCFG_H                     43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H      4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H      4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H   0
+#define ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H              1
+#define ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H              0
+#define ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H              0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ip_VS_0_PBcfg.h file and Adc_Ip_Types.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_VS_0_PBCFG_H != ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Adc_Ip_VS_0_PBcfg.h and Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_VS_0_PBcfg.h file and Adc_Ip_Types.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_VS_0_PBcfg.h and Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Adc_Ip_VS_0_PBcfg.h file and Adc_Ip_Types.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H != ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H != ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H != ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_VS_0_PBcfg.h and Adc_Ip_Types.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+void Adc_Ipw_Adc1EndConversionNotification(const uint8 ControlChanIdx);
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          ADC Ip Config for Logical ID 0 corresponding to the ADC1 configuration variant VS_0.
+*/
+extern const Adc_Ip_ConfigType AdcIpConfig_0_VS_0;
+
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IP_VS_0_PBCFG_H */
+

generate/include/Adc_Ipw_Cfg.h

@@ -0,0 +1,141 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_CFG_H
+#define ADC_IPW_CFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ipw_config Adc Ipw Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Adc_Ipw_Types.h"
+#include "Adc_Ipw_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_IPW_CFG_H                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFG_H       4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_CFG_H       4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_CFG_H    0
+#define ADC_SW_MAJOR_VERSION_IPW_CFG_H               1
+#define ADC_SW_MINOR_VERSION_IPW_CFG_H               0
+#define ADC_SW_PATCH_VERSION_IPW_CFG_H               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_Types.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_CFG_H != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Ipw_Cfg.h and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_Types.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFG_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_CFG_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_CFG_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Cfg.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_Types.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_CFG_H != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_CFG_H != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_CFG_H != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Cfg.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_CFG_H != ADC_VENDOR_ID_IPW_VS_0_PBCFG_H)
+    #error "Adc_Ipw_Cfg.h and Adc_Ipw_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFG_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_CFG_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_CFG_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_Cfg.h and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_Cfg.h file and Adc_Ipw_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_CFG_H != ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_CFG_H != ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_CFG_H != ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_Cfg.h and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_CFG_H */
+

generate/include/Adc_Ipw_CfgDefines.h

@@ -0,0 +1,100 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_CFGDEFINES_H
+#define ADC_IPW_CFGDEFINES_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ipw_config Adc Ipw Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_IPW_CFGDEFINES_H                     43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFGDEFINES_H      4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_CFGDEFINES_H      4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_CFGDEFINES_H   0
+#define ADC_SW_MAJOR_VERSION_IPW_CFGDEFINES_H              1
+#define ADC_SW_MINOR_VERSION_IPW_CFGDEFINES_H              0
+#define ADC_SW_PATCH_VERSION_IPW_CFGDEFINES_H              0
+
+/*==================================================================================================
+*                              DEFINES AND MACROS
+==================================================================================================*/
+#define ADC_IPW_INVALID_LOGICAL_UNIT_ID     (0xFFU)
+
+#define ADC_IPW_INVALID_DMA_CHANNEL_ID      (0xFFU)
+
+#define ADC_IPW_INVALID_TRANSFER_TYPE       (0xFFU)
+
+/**
+ * @brief          Max number of ADC Hw units.
+ */
+#define ADC_MAX_HW_UNITS                    (2U)
+
+
+/**
+* @brief           PDB available/unavailable (STD_ON/STD_OFF).
+*/
+#define ADC_PDB_AVAILABLE                   (STD_ON)
+
+/**
+* @brief           BCTU available/unavailable (STD_ON/STD_OFF).
+*/
+#define ADC_BCTU_AVAILABLE                  (STD_OFF)
+
+/**
+* @brief           CTU available/unavailable (STD_ON/STD_OFF).
+*/
+#define ADC_CTU_AVAILABLE                   (STD_OFF)
+
+/**
+* @brief           ADC hardware is supported CALSTAT register
+*/
+#define ADC_CALSTAT_AVAILABLE               (STD_OFF)
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_CFGDEFINES_H */
+

generate/include/Adc_Ipw_VS_0_PBcfg.h

@@ -0,0 +1,136 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_IPW_VS_0_PBCFG_H
+#define ADC_IPW_VS_0_PBCFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_ipw_config Adc Ipw Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Adc_Ipw_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_IPW_VS_0_PBCFG_H                       43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_H        4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_H        4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_H     0
+#define ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_H                1
+#define ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_H                0
+#define ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_H                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check vendor id */
+#if (ADC_VENDOR_ID_IPW_VS_0_PBCFG_H != ADC_VENDOR_ID_IPW_TYPES_H)
+    #error "Adc_Ipw_VS_0_PBcfg.h and Adc_Ipw_Types.h have different vendor ids"
+#endif
+
+/* Check Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_H != ADC_AR_RELEASE_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_H != ADC_AR_RELEASE_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_H != ADC_AR_RELEASE_REVISION_VERSION_IPW_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_VS_0_PBcfg.h and Adc_Ipw_Types.h are different"
+#endif
+
+/* Check Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_H != ADC_SW_MAJOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_H != ADC_SW_MINOR_VERSION_IPW_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_H != ADC_SW_PATCH_VERSION_IPW_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_VS_0_PBcfg.h and Adc_Ipw_Types.h are different"
+#endif
+
+/*==================================================================================================
+*                              STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Adc Ipw Config configuration variant VS_0.
+*/
+extern const Adc_Ipw_Config AdcIpwCfg_VS_0;
+
+/**
+* @brief          ADC Ipw Group 0 Config VS_0.
+*/
+extern const Adc_Ipw_GroupConfig AdcIpwGroupConfig_0_VS_0;
+
+/**
+* @brief          ADC Ipw Group 1 Config VS_0.
+*/
+extern const Adc_Ipw_GroupConfig AdcIpwGroupConfig_1_VS_0;
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+
+/**
+* @brief         ADC Notification functions.
+* @details       ADC Nofification functions defined inside the Plugin.
+*
+*/
+extern void Notification_0(void);
+extern void Notification_1(void);
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_IPW_VS_0_PBCFG_H */
+

generate/include/Adc_VS_0_PBcfg.h

@@ -0,0 +1,116 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef ADC_VS_0_PBCFG_H
+#define ADC_VS_0_PBCFG_H
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver_config Adc Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Adc_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_VS_0_PBCFG_H                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H       4
+#define ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H       4
+#define ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H    0
+#define ADC_SW_MAJOR_VERSION_VS_0_PBCFG_H               1
+#define ADC_SW_MINOR_VERSION_VS_0_PBCFG_H               0
+#define ADC_SW_PATCH_VERSION_VS_0_PBCFG_H               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Adc Configuration header file and Adc Types header file are of the same vendor */
+#if (ADC_VENDOR_ID_VS_0_PBCFG_H != ADC_VENDOR_ID_TYPES_H)
+    #error "Adc_VS_0_PBcfg.h and Adc_Types.h have different vendor ids"
+#endif
+
+/* Check if Adc Configuration header file and Adc Types header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != ADC_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_VS_0_PBcfg.h and Adc_Types.h are different"
+#endif
+
+/* Check if Adc Configuration header file and Adc Types header file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_VS_0_PBCFG_H != ADC_SW_MAJOR_VERSION_TYPES_H) || \
+     (ADC_SW_MINOR_VERSION_VS_0_PBCFG_H != ADC_SW_MINOR_VERSION_TYPES_H) || \
+     (ADC_SW_PATCH_VERSION_VS_0_PBCFG_H != ADC_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Adc_VS_0_PBcfg.h and Adc_Types.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+#define ADC_CONFIG_VS_0_PB \
+ extern const Adc_ConfigType Adc_Config_VS_0;\
+
+/**
+* @brief           Number of channels configured for each group.
+*
+*/
+
+#define ADC_CFGSET_VS_0_GROUP_0_CHANNELS      (7U)
+#define ADC_CFGSET_VS_0_GROUP_1_CHANNELS      (7U)
+
+/**
+* @brief          Total number of groups in Config.
+*
+*/
+#define ADC_GROUPS_VS_0                       (2U)
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* ADC_VS_0_PBCFG_H */
+

generate/include/CDD_Mcl_Cfg.h

@@ -189,7 +189,7 @@ extern "C"{
 /-----------------------------------------------*/
 #define MCL_DEM_IS_AVAILABLE                       STD_OFF
 
-#define MCL_DET_IS_AVAILABLE                       STD_ON
+#define MCL_DET_IS_AVAILABLE                       STD_OFF
 
 /*-----------------------------------------------/
 /  DMA                                           /

generate/include/Ftm_Mcl_Ip_Cfg.h

@@ -100,7 +100,7 @@ extern "C"
 #define FTM_MCL_ENABLE_USER_MODE_SUPPORT             (STD_OFF)
 
 /** @brief Switches the Development Error Detection and Notification on or off.  */
-#define FTM_MCL_IP_DEV_ERROR_DETECT                  (STD_ON)
+#define FTM_MCL_IP_DEV_ERROR_DETECT                  (STD_OFF)
 
 /** @brief */
 #define USER_MODE_REG_PROT_ENABLED                   (FTM_MCL_ENABLE_USER_MODE_SUPPORT)

generate/include/IntCtrl_Ip_Cfg.h

@@ -106,6 +106,7 @@ extern void Lpspi_Ip_LPSPI_2_IRQHandler(void);
 extern void LPUART_UART_IP_0_IRQHandler(void);
 extern void LPUART_UART_IP_1_IRQHandler(void);
 extern void LPUART_UART_IP_2_IRQHandler(void);
+extern void Adc_1_Isr(void);
 extern void MCL_FLEXIO_ISR(void);
 extern void CAN0_ORED_IRQHandler(void);
 extern void CAN0_Error_IRQHandler(void);

generate/include/Pdb_Adc_Ip_Cfg.h

@@ -0,0 +1,140 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_ADC_IP_CFG_H
+#define PDB_ADC_IP_CFG_H
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip_config Pdb Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Pdb_Adc_Ip_Types.h"
+#include "Pdb_Adc_Ip_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define PDB_ADC_IP_VENDOR_ID_CFG_H                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_CFG_H               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_CFG_H               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_CFG_H               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_Types.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_CFG_H != PDB_ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_Types.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_Types.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_CFG_H != PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_CFG_H != PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_CFG_H != PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_CFG_H != PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFG_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_Cfg.h file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_CFG_H != PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_CFG_H != PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_CFG_H != PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_Cfg.h and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* PDB_ADC_IP_CFG_H */
+

generate/include/Pdb_Adc_Ip_CfgDefines.h

@@ -0,0 +1,122 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_ADC_IP_CFGDEFINES_H
+#define PDB_ADC_IP_CFGDEFINES_H
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip_config Pdb Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "S32K146_PDB.h"
+#include "S32K146_SIM.h"
+#include "OsIf.h"
+
+/*==================================================================================================
+*                                SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define PDB_ADC_IP_VENDOR_ID_CFGDEFINES_H                      43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H       4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H       4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_CFGDEFINES_H    0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_CFGDEFINES_H               1
+#define PDB_ADC_IP_SW_MINOR_VERSION_CFGDEFINES_H               0
+#define PDB_ADC_IP_SW_PATCH_VERSION_CFGDEFINES_H               0
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+/* Check AutoSar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_CFGDEFINES_H != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_CFGDEFINES_H != OSIF_AR_RELEASE_MINOR_VERSION)    \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_CfgDefines.h and OsIf.h are different"
+#endif
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+/* @brief PDB has instance back to back mode between PDB0 CH0 and PDB1 CH0 pre-triggers */
+#define FEATURE_PDB_HAS_INSTANCE_BACKTOBACK     (STD_OFF)
+
+/* @brief PDB has inter-channel back to back mode between PDBx CH0 and PDBx CH1 pre-triggers */
+#define FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK (STD_OFF)
+
+#define PDB_ADC_IP_DEV_ERROR_DETECT             (STD_OFF)
+#define PDB_ADC_IP_ENABLE_USER_MODE_SUPPORT     (STD_OFF)
+
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* PDB_ADC_IP_CFGDEFINES_H */
+

generate/include/Pdb_Adc_Ip_VS_0_PBcfg.h

@@ -0,0 +1,118 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef PDB_ADC_IP_VS_0_PBCFG_H
+#define PDB_ADC_IP_VS_0_PBCFG_H
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip_config Pdb Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Pdb_Adc_Ip_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_H                     43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H      4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H      4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H   0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H              1
+#define PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H              0
+#define PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H              0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.h file and Pdb_Adc_Ip_Types.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_H != PDB_ADC_IP_VENDOR_ID_TYPES_H)
+    #error "Pdb_Adc_Ip_VS_0_PBcfg.h and Pdb_Adc_Ip_Types.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.h file and Pdb_Adc_Ip_Types.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_TYPES_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_VS_0_PBcfg.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.h file and Pdb_Adc_Ip_Types.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_SW_MAJOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_SW_MINOR_VERSION_TYPES_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H != PDB_ADC_IP_SW_PATCH_VERSION_TYPES_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_VS_0_PBcfg.h and Pdb_Adc_Ip_Types.h are different"
+#endif
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      EXTERN DECLARATIONS
+==================================================================================================*/
+#define ADC_START_SEC_CODE
+#include "Adc_MemMap.h"
+
+
+#define ADC_STOP_SEC_CODE
+#include "Adc_MemMap.h"
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          PDB Ip Config for Hardware Unit ADC1 for configuration variant VS_0.
+*/
+extern const Pdb_Adc_Ip_ConfigType PdbAdcIpConfig_0_VS_0;
+
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* PDB_ADC_IP_VS_0_PBCFG_H */
+

generate/include/modules.h

@@ -108,7 +108,7 @@ extern "C" {
 * @brief This constant used for other modules to check if ADC is present in the project.  
 * @violates @ref modules_h_REF_1 MISRA 2012 Advisory Rule 2.5, unused macro. 
 */
-#define USE_ADC_MODULE              (STD_OFF)
+#define USE_ADC_MODULE              (STD_ON)
 
 /** 
 * @brief This constant used for other modules to check if CAN is present in the project.  

generate/output/Adc.epc

@@ -0,0 +1,844 @@
+<?xml version='1.0'?>
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0"
+         xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+         xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_00046.xsd">
+  <AR-PACKAGES>
+    <AR-PACKAGE>
+      <SHORT-NAME>Adc</SHORT-NAME>
+      <ELEMENTS>
+        <ECUC-MODULE-CONFIGURATION-VALUES>
+          <SHORT-NAME>Adc</SHORT-NAME>
+          <DEFINITION-REF DEST="ECUC-MODULE-DEF">/TS_T40D2M10I0R0/Adc</DEFINITION-REF>
+          <IMPLEMENTATION-CONFIG-VARIANT>VARIANT-POST-BUILD</IMPLEMENTATION-CONFIG-VARIANT>
+          <POST-BUILD-VARIANT-USED>true</POST-BUILD-VARIANT-USED>
+          <CONTAINERS>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>AdcConfigSet</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet</DEFINITION-REF>
+              <SUB-CONTAINERS>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>AdcHwTrigger_0</SHORT-NAME>
+                  <INDEX>0</INDEX>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwTrigger</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwTrigger/AdcHwTrigSrc</DEFINITION-REF>
+                      <VALUE>TRIGGER_IN0</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>AdcHwUnit_0</SHORT-NAME>
+                  <INDEX>0</INDEX>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcAltPrescale</DEFINITION-REF>
+                      <VALUE>2</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcCalibrationPrescale</DEFINITION-REF>
+                      <VALUE>8</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcHwUnitId</DEFINITION-REF>
+                      <VALUE>ADC1</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcHwUnitResolution</DEFINITION-REF>
+                      <VALUE>RESOLUTION_12</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcHwUnitUsrGain</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcHwUnitUsrOffset</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcLogicalUnitId</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcPrescale</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcTransferType</DEFINITION-REF>
+                      <VALUE>ADC_INTERRUPT</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <SUB-CONTAINERS>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>AdcAlternateConvTimings</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcAlternateConvTimings</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcAlternateConvTimings/AdcHardwareAverageEnableAlternate</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcAlternateConvTimings/AdcHardwareAverageSelectAlternate</DEFINITION-REF>
+                          <VALUE>SAMPLES_4</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcAlternateConvTimings/AdcSampleTimeDurationAlternate</DEFINITION-REF>
+                          <VALUE>12</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>Adc1_VREFH</SHORT-NAME>
+                      <INDEX>0</INDEX>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelId</DEFINITION-REF>
+                          <VALUE>29</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelName</DEFINITION-REF>
+                          <VALUE>VREFH_ADCH29</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcLogicalChannelId</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>Adc1_BANDGAP</SHORT-NAME>
+                      <INDEX>1</INDEX>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelId</DEFINITION-REF>
+                          <VALUE>27</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelName</DEFINITION-REF>
+                          <VALUE>BANDGAP_ADCH27</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcLogicalChannelId</DEFINITION-REF>
+                          <VALUE>1</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>Adc1_VREFL</SHORT-NAME>
+                      <INDEX>2</INDEX>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelId</DEFINITION-REF>
+                          <VALUE>30</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelName</DEFINITION-REF>
+                          <VALUE>VREFL_ADCH30</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcLogicalChannelId</DEFINITION-REF>
+                          <VALUE>2</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTB13_ADC1_SE8_MCU_CC1</SHORT-NAME>
+                      <INDEX>3</INDEX>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelId</DEFINITION-REF>
+                          <VALUE>8</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelName</DEFINITION-REF>
+                          <VALUE>SE8_ADCH8</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcLogicalChannelId</DEFINITION-REF>
+                          <VALUE>3</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTB12_ADC1_SE7_MCU_TP1</SHORT-NAME>
+                      <INDEX>4</INDEX>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelId</DEFINITION-REF>
+                          <VALUE>7</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelName</DEFINITION-REF>
+                          <VALUE>SE7_ADCH7</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcLogicalChannelId</DEFINITION-REF>
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+                          <VALUE>NULL_PTR</VALUE>
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+                          <VALUE>ADC_ACCESS_MODE_SINGLE</VALUE>
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+                          <VALUE>ADC_CONV_TYPE_NORMAL</VALUE>
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+                          <VALUE>ADC_TRIGG_SRC_SW</VALUE>
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+                          <VALUE>0</VALUE>
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+                        <ECUC-TEXTUAL-PARAM-VALUE>
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+                          <VALUE>Notification_0</VALUE>
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+                          <VALUE>1000</VALUE>
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+                          <VALUE>ADC_STREAM_BUFFER_LINEAR</VALUE>
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+                        <ECUC-CONTAINER-VALUE>
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+                              <VALUE>0</VALUE>
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+                              <VALUE>SAMPLES_4</VALUE>
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+                              <VALUE>2</VALUE>
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+                              <VALUE>1</VALUE>
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+                              <VALUE>SAMPLES_8</VALUE>
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+                              <VALUE>255</VALUE>
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+                          <VALUE>ADC_ACCESS_MODE_SINGLE</VALUE>
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+                          <VALUE>ADC_CONV_TYPE_NORMAL</VALUE>
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+                          <VALUE>ADC_TRIGG_SRC_HW</VALUE>
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+                          <VALUE>Notification_1</VALUE>
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+                              <VALUE>SAMPLES_8</VALUE>
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+                          <VALUE>SAMPLES_4</VALUE>
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+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AutosarExt/AdcOptimizeOneShotHwTriggerConversions</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-TEXTUAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AutosarExt/AdcTimeoutMethod</DEFINITION-REF>
+                  <VALUE>OSIF_COUNTER_DUMMY</VALUE>
+                </ECUC-TEXTUAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AutosarExt/AdcTimeoutVal</DEFINITION-REF>
+                  <VALUE>100000</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Adc/AutosarExt/PdbDevErrorDetect</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+            </ECUC-CONTAINER-VALUE>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>CommonPublishedInformation</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation</DEFINITION-REF>
+              <PARAMETER-VALUES>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/ArReleaseMajorVersion</DEFINITION-REF>
+                  <VALUE>4</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/ArReleaseMinorVersion</DEFINITION-REF>
+                  <VALUE>4</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/ArReleaseRevisionVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/ModuleId</DEFINITION-REF>
+                  <VALUE>123</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/SwMajorVersion</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/SwMinorVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/SwPatchVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-TEXTUAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/VendorApiInfix</DEFINITION-REF>
+                  <VALUE></VALUE>
+                </ECUC-TEXTUAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Adc/CommonPublishedInformation/VendorId</DEFINITION-REF>
+                  <VALUE>43</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+            </ECUC-CONTAINER-VALUE>
+          </CONTAINERS>
+        </ECUC-MODULE-CONFIGURATION-VALUES>
+      </ELEMENTS>
+    </AR-PACKAGE>
+  </AR-PACKAGES>
+</AUTOSAR>

generate/output/Mcl.epc

@@ -2385,7 +2385,7 @@
                 </ECUC-NUMERICAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcl/MclGeneral/MclEnableDevErrorDetect</DEFINITION-REF>
-                  <VALUE>1</VALUE>
+                  <VALUE>0</VALUE>
                 </ECUC-NUMERICAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcl/MclGeneral/MclEnableUserModeSupport</DEFINITION-REF>

generate/output/Mcu.epc

@@ -1462,11 +1462,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockFrequency</DEFINITION-REF>
-                          <VALUE>0.0</VALUE>
+                          <VALUE>4.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockSelect</DEFINITION-REF>
-                          <VALUE>CLOCK_IS_OFF</VALUE>
+                          <VALUE>SPLL</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockUnderMcuControl</DEFINITION-REF>
@@ -2078,7 +2078,7 @@
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl/McuLowPowerBiasEnable</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl/McuLowVoltageDetectInterruptEnable</DEFINITION-REF>

generate/output/Platform.epc

@@ -611,7 +611,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrEnabled</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>
@@ -2453,7 +2453,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-FUNCTION-NAME-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrHandler</DEFINITION-REF>
-                      <VALUE>undefined_handler</VALUE>
+                      <VALUE>Adc_1_Isr</VALUE>
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>

generate/src/Adc_Cfg.c

@@ -0,0 +1,120 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver_config Adc Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_VENDOR_ID_CFG_C                    43
+#define ADC_AR_RELEASE_MAJOR_VERSION_CFG_C     4
+#define ADC_AR_RELEASE_MINOR_VERSION_CFG_C     4
+#define ADC_AR_RELEASE_REVISION_VERSION_CFG_C  0
+#define ADC_SW_MAJOR_VERSION_CFG_C             1
+#define ADC_SW_MINOR_VERSION_CFG_C             0
+#define ADC_SW_PATCH_VERSION_CFG_C             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if source file and ADC header file are of the same vendor */
+#if (ADC_VENDOR_ID_CFG_C != ADC_VENDOR_ID)
+    #error "Adc_Cfg.c and Adc.h have different vendor ids"
+#endif
+
+/* Check if source file and ADC header file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_CFG_C != ADC_AR_RELEASE_MAJOR_VERSION) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_CFG_C != ADC_AR_RELEASE_MINOR_VERSION) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_CFG_C != ADC_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Adc_Cfg.c and Adc.h are different"
+#endif
+
+/* Check if source file and ADC header file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_CFG_C != ADC_SW_MAJOR_VERSION) || \
+     (ADC_SW_MINOR_VERSION_CFG_C != ADC_SW_MINOR_VERSION) || \
+     (ADC_SW_PATCH_VERSION_CFG_C != ADC_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Adc_Cfg.c and Adc.h are different"
+#endif
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Adc_Ip_VS_0_PBcfg.c

@@ -0,0 +1,206 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_ip_config Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_Ip_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define ADC_IP_VENDOR_ID_VS_0_PBCFG_C                     43
+#define ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C      4
+#define ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C      4
+#define ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C   0
+#define ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_C              1
+#define ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_C              0
+#define ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_C              0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Adc_Ip_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_IP_VENDOR_ID_VS_0_PBCFG_C != ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Adc_Ip_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ip_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ip_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ip_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_C != ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_C != ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_C != ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ip_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          ADC Ip List of Channels Configuration for Logical ID 0 corresponding to the ADC1 configuration variant VS_0.
+*/
+static const Adc_Ip_ChanConfigType AdcIpChansConfig_0_VS_0[7U] =
+{
+    {
+        0U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_VREFH, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        1U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_BANDGAP, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        2U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_VREFL, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        3U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_EXT8, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        4U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_EXT7, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        5U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_EXT6, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    },
+    {
+        6U, /* ChnIdx */
+        ADC_IP_INPUTCHAN_EXT11, /* Channel */
+        (boolean)FALSE /* InterruptEnable */
+    }
+};
+
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+/**
+* @brief          ADC Ip Config for Logical ID 0 corresponding to the ADC1 configuration variant VS_0.
+*/
+const Adc_Ip_ConfigType AdcIpConfig_0_VS_0 =
+{
+    ADC_IP_CLK_FULL_BUS, /* ClockDivide */
+    ADC_IP_CLK_EIGHTH_BUS, /* CalibrationClockDivide */
+    ADC_IP_CLK_ALT_1, /* InputClock */
+    ADC_IP_DEFAULT_SAMPLE_TIME, /* SampleTime */
+    (boolean)FALSE, /* AvgEn */
+    ADC_IP_AVG_4_CONV, /* AvgSel */
+    ADC_IP_RESOLUTION_12BIT, /* Resolution */
+    ADC_IP_TRIGGER_HARDWARE, /* TriggerMode */
+#if (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON)
+    ADC_IP_PRETRIGGER_SEL_PDB, /* PretriggerSel */
+    ADC_IP_TRIGGER_SEL_PDB, /* TriggerSel */
+#endif /* (ADC_IP_ENABLE_SIM_SOURCE_SELECTION == STD_ON) */
+    (boolean)FALSE, /* DmaEnable */
+    ADC_IP_VOLTAGEREF_VREF, /* VoltageRef */
+    (boolean)FALSE, /* ContinuousConvEnable */
+#if (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON)
+    (boolean)FALSE, /* SupplyMonitoringEnable */
+#endif /* (ADC_IP_SUPPLY_MONITORING_ENABLED == STD_ON) */
+    (boolean)FALSE, /* CompareEnable */
+    (boolean)FALSE, /* CompareGreaterThanEnable */
+    (boolean)FALSE, /* CompareRangeFuncEnable */
+    0U, /* CompVal1 */
+    255U, /* CompVal2 */
+    0U, /* UsrGain */
+    0U, /* UsrOffset */
+    0U, /* NumChannels */
+    AdcIpChansConfig_0_VS_0, /* ChannelConfigs */
+    Adc_Ipw_Adc1EndConversionNotification /* ConversionCompleteNotification */
+};
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Adc_Ipw_VS_0_PBcfg.c

@@ -0,0 +1,298 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_ipw_config Adc Ipw Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Adc_Ipw_CfgDefines.h"
+#include "Adc_Ipw_VS_0_PBcfg.h"
+#include "Adc_Ip_VS_0_PBcfg.h"
+#include "Pdb_Adc_Ip_VS_0_PBcfg.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_IPW_VS_0_PBCFG_C                      43
+#define ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_C       4
+#define ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_C       4
+#define ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_C    0
+#define ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_C               1
+#define ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_C               0
+#define ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_C               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_CfgDefines.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_VS_0_PBCFG_C != ADC_VENDOR_ID_IPW_CFGDEFINES_H)
+    #error "Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_CfgDefines.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_CfgDefines.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_CFGDEFINES_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_CfgDefines.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_MAJOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_MINOR_VERSION_IPW_CFGDEFINES_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_PATCH_VERSION_IPW_CFGDEFINES_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_CfgDefines.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_VS_0_PBCFG_C != ADC_VENDOR_ID_IPW_VS_0_PBCFG_H)
+    #error "Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_C != ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_VS_0_PBCFG_C != ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Adc_Ipw_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_C != ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_IPW_VS_0_PBCFG_C != PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Adc_Ipw_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_Ipw_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_C != PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_Ipw_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+
+/*==================================================================================================
+*                                   GLOBAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CONFIG_DATA_16
+#include "Adc_MemMap.h"
+/**
+* @brief          Group Channel Delays for configuration variant VS_0.
+*
+*/
+
+#define ADC_STOP_SEC_CONFIG_DATA_16
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Adc Ipw Config configuration variant VS_0.
+*/
+const Adc_Ipw_Config AdcIpwCfg_VS_0 =
+{
+    { &AdcIpConfig_0_VS_0, NULL_PTR }, /* apAdcConfig */
+    { &PdbAdcIpConfig_0_VS_0, NULL_PTR }, /* apPdbConfig */
+    { 1U, ADC_IPW_INVALID_LOGICAL_UNIT_ID }, /* aAdcPhysicalId */
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    { NULL_PTR, NULL_PTR }, /* apAdcAltClockConfig */
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+    { NULL_PTR, NULL_PTR }, /* ChannelLimitCheckingConfigs */
+#endif /* (ADC_ENABLE_LIMIT_CHECK == STD_ON) */
+    /* Mapping */
+    {
+        { ADC_INTERRUPT, ADC_IPW_INVALID_TRANSFER_TYPE /* Unit not used */ }, /* u8Adc_DmaInterruptSoftware */
+        /**< @brief number of groups per hw unit > */
+        { 2U, 0U }, /* aAdc_Groups */
+        /**< @brief number of channels per hw unit > */
+        { 7U, 0U }, /* aAdc_Channels */
+        { ADC_IPW_INVALID_DMA_CHANNEL_ID, ADC_IPW_INVALID_DMA_CHANNEL_ID }, /* au8Adc_DmaChannel */
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        { ADC_IPW_INVALID_DMA_CHANNEL_ID, ADC_IPW_INVALID_DMA_CHANNEL_ID }, /* au8Adc_CountingDmaChannel */
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) || (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+        { STD_ON, STD_OFF }, /* au8Adc_HwUnit */
+        { ADC_IPW_INVALID_LOGICAL_UNIT_ID, 0U } /* aHwLogicalId */
+    }
+};
+
+/**
+* @brief          ADC Ipw Group 0 Config VS_0.
+*/
+const Adc_Ipw_GroupConfig AdcIpwGroupConfig_0_VS_0 =
+{
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    /**< @brief Main Average enable status of group */
+    STD_ON, /* u8GroupAvgEnable */
+    /**< @brief Main Average selection of group */
+    ADC_IP_AVG_8_CONV, /* GroupAvgSelect */
+    255U, /* ConvTime */
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    /**< @brief Alternate Average enable status of group */
+    STD_OFF, /* u8GroupAvgEnableAlternate */
+    /**< @brief Alternate Average selection of group */
+    ADC_IP_AVG_4_CONV, /* GroupAvgSelectAlternate */
+    ADC_IP_DEFAULT_SAMPLE_TIME, /* AlternateConvTime */
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+    0U, /* PdbPeriod */
+    0U, /* PdbDelay */
+    (boolean)TRUE, /* AdcGroupEnableBackToBack */
+    (boolean)FALSE, /* AdcGroupEnableChannelDelays */
+    NULL_PTR /* pDelay */
+};
+
+/**
+* @brief          ADC Ipw Group 1 Config VS_0.
+*/
+const Adc_Ipw_GroupConfig AdcIpwGroupConfig_1_VS_0 =
+{
+#if (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF)
+    /**< @brief Main Average enable status of group */
+    STD_ON, /* u8GroupAvgEnable */
+    /**< @brief Main Average selection of group */
+    ADC_IP_AVG_8_CONV, /* GroupAvgSelect */
+    255U, /* ConvTime */
+#if (ADC_DUAL_CLOCK_MODE == STD_ON)
+    /**< @brief Alternate Average enable status of group */
+    STD_OFF, /* u8GroupAvgEnableAlternate */
+    /**< @brief Alternate Average selection of group */
+    ADC_IP_AVG_4_CONV, /* GroupAvgSelectAlternate */
+    ADC_IP_DEFAULT_SAMPLE_TIME, /* AlternateConvTime */
+#endif /* (ADC_DUAL_CLOCK_MODE == STD_ON) */
+#endif /* (ADC_SET_ADC_CONV_TIME_ONCE == STD_OFF) */
+    0U, /* PdbPeriod */
+    0U, /* PdbDelay */
+    (boolean)TRUE, /* AdcGroupEnableBackToBack */
+    (boolean)FALSE, /* AdcGroupEnableChannelDelays */
+    NULL_PTR /* pDelay */
+};
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Adc_VS_0_PBcfg.c

@@ -0,0 +1,414 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup adc_driver_config Adc Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Adc_VS_0_PBcfg.h"
+#include "Adc_Ipw_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define ADC_VENDOR_ID_VS_0_PBCFG_C                    43
+#define ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C     4
+#define ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C     4
+#define ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C  0
+#define ADC_SW_MAJOR_VERSION_VS_0_PBCFG_C             1
+#define ADC_SW_MINOR_VERSION_VS_0_PBCFG_C             0
+#define ADC_SW_PATCH_VERSION_VS_0_PBCFG_C             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_VS_0_PBCFG_C != ADC_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Adc_VS_0_PBcfg.c and Adc_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_VS_0_PBcfg.c and Adc_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_VS_0_PBCFG_C != ADC_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_VS_0_PBCFG_C != ADC_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_VS_0_PBCFG_C != ADC_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_VS_0_PBcfg.c and Adc_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same vendor */
+#if (ADC_VENDOR_ID_VS_0_PBCFG_C != ADC_VENDOR_ID_IPW_VS_0_PBCFG_H)
+    #error "Adc_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((ADC_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C != ADC_AR_RELEASE_REVISION_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Adc_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Adc_VS_0_PBcfg.c file and Adc_Ipw_VS_0_PBcfg.h file are of the same Software version */
+#if ((ADC_SW_MAJOR_VERSION_VS_0_PBCFG_C != ADC_SW_MAJOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_MINOR_VERSION_VS_0_PBCFG_C != ADC_SW_MINOR_VERSION_IPW_VS_0_PBCFG_H) || \
+     (ADC_SW_PATCH_VERSION_VS_0_PBCFG_C != ADC_SW_PATCH_VERSION_IPW_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Adc_VS_0_PBcfg.c and Adc_Ipw_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+#define ADC_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Adc Result Buffer RAM initializations.
+* @details        Array for all ADC group result ram buffers.
+*/
+static Adc_ValueGroupType * Adc_aResultsBufferPtr[2];
+
+#define ADC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          Group Assignments on ADC1 VS_0.
+*
+*/
+static const Adc_ChannelType Adc_Group0_Assignment_1_VS_0[ADC_CFGSET_VS_0_GROUP_0_CHANNELS] =
+{
+    0U,
+    1U,
+    2U,
+    6U,
+    5U,
+    4U,
+    3U
+};
+
+/**
+* @brief          Group Assignments on ADC1 VS_0.
+*
+*/
+static const Adc_ChannelType Adc_Group1_Assignment_1_VS_0[ADC_CFGSET_VS_0_GROUP_1_CHANNELS] =
+{
+    0U,
+    1U,
+    2U,
+    6U,
+    5U,
+    4U,
+    3U
+};
+
+/**
+* @brief          Definition of all ADC groups for configuration variant VS_0.
+*/
+static const Adc_GroupConfigurationType Adc_GroupsCfg_VS_0[] =
+{
+    /**< @brief Group0 -- Logical Unit Id 0 -- Hardware Unit ADC1 */
+    {
+        /**< @brief Index of group */
+        0, /* GroupId */
+        /**< @brief ADC Logical Unit Id that the group belongs to */
+        (Adc_HwUnitType)0, /* AdcLogicalUnitId */
+        /**< @brief Access mode */
+        ADC_ACCESS_MODE_SINGLE, /* eAccessMode */
+        /**< @brief Conversion mode */
+        ADC_CONV_MODE_ONESHOT, /* eMode */
+        /**< @brief Conversion type */
+        ADC_CONV_TYPE_NORMAL, /* eType */
+#if (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE)
+        /**< @brief Priority configured */
+        (Adc_GroupPriorityType)ADC_GROUP_PRIORITY, /* Priority */
+#endif /* ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE */
+        /**< @brief Replacement mode */
+        ADC_GROUP_REPL_ABORT_RESTART, /* eReplacementMode */
+        /**< @brief Trigger source configured */
+        ADC_TRIGG_SRC_SW, /* eTriggerSource */
+#if (STD_ON == ADC_HW_TRIGGER_API)
+        /**< @brief Hardware trigger source for the group */
+        PDB_ADC_IP_SOFTWARE_TRIGGER, /* HwTriggerSource */
+        /**< @brief Hardware trigger signal */
+        ADC_HW_TRIG_RISING_EDGE, /* eTriggerEdge */
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+#if (STD_ON == ADC_GRP_NOTIF_CAPABILITY)
+        /**< @brief Notification function */
+        Notification_0, /* Notification */
+#endif /* (STD_ON == ADC_GRP_NOTIF_CAPABILITY) */
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+        /**< @brief Extra notification function */
+        NULL_PTR, /* ExtraNotification */
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+        /**< @brief ADC Group Result Buffers RAM array */
+        Adc_aResultsBufferPtr, /* pResultsBufferPtr */
+        /**< @brief Group Streaming Buffer Mode */
+        ADC_STREAM_BUFFER_LINEAR, /* eBufferMode */
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+        /**< @brief Index of the group with AdcEnableChDisableChGroup enabled */
+        (Adc_GroupType)ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX, /* EnableChDisableChGroupIndex */
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+        /**< @brief Number of streaming samples */
+        (Adc_StreamNumSampleType)ADC_STREAMING_NUM_SAMPLES(1), /* NumSamples */
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        /**< @brief Arrange the adc results as multiple sets of group result buffer */
+        (boolean)FALSE, /* bStreamResultGroupMultiSets */
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+        /**< @brief Channels assigned to the group*/
+        Adc_Group0_Assignment_1_VS_0, /* pAssignment */
+        /**< @brief Number of channels in the group*/
+        (Adc_ChannelIndexType)ADC_CFGSET_VS_0_GROUP_0_CHANNELS, /* AssignedChannelCount */
+        /**< @brief Last Channel configured */
+        (Adc_ChannelType)(ADC_ID_CHANNEL_U8(30)), /* LastCh */
+        /**< @brief First Channel configured */
+        (Adc_ChannelType)(ADC_ID_CHANNEL_U8(6)), /* FirstCh */
+        /**< @brief Enables or Disables the ADC and DMA interrupts */
+        (uint8)(STD_OFF), /* u8AdcWithoutInterrupt */
+        /**< @brief Enables or Disables configuring external DMA channel in the group */
+        (uint8)(STD_OFF), /* u8AdcExtDMAChanEnable */
+        /**< @brief When true, disables completely DMA configuration done by ADC driver for the group */
+        (boolean)FALSE, /* u8AdcWithoutDma */
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+        /**< @brief Enables or Disables the ADC optimize DMA streaming groups feature */
+        (boolean)FALSE, /* bAdcOptimizeDmaStream */
+        /**< @brief Enable/disable half interrupt for group with optimize DMA streaming groups */
+        (boolean)FALSE, /* bHalfInterrupt */
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        /**< @brief Enables or disables the usage of limit checking for an ADC group. */
+        (boolean)FALSE, /* bAdcGroupLimitcheck */
+#endif /* (STD_ON == ADC_ENABLE_LIMIT_CHECK) */
+        &AdcIpwGroupConfig_0_VS_0 /* pAdcIpwGroupConfig */
+    },
+    /**< @brief Group1 -- Logical Unit Id 0 -- Hardware Unit ADC1 */
+    {
+        /**< @brief Index of group */
+        1, /* GroupId */
+        /**< @brief ADC Logical Unit Id that the group belongs to */
+        (Adc_HwUnitType)0, /* AdcLogicalUnitId */
+        /**< @brief Access mode */
+        ADC_ACCESS_MODE_SINGLE, /* eAccessMode */
+        /**< @brief Conversion mode */
+        ADC_CONV_MODE_ONESHOT, /* eMode */
+        /**< @brief Conversion type */
+        ADC_CONV_TYPE_NORMAL, /* eType */
+#if (ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE)
+        /**< @brief Priority configured */
+        (Adc_GroupPriorityType)ADC_GROUP_PRIORITY, /* Priority */
+#endif /* ADC_PRIORITY_IMPLEMENTATION != ADC_PRIORITY_NONE */
+        /**< @brief Replacement mode */
+        ADC_GROUP_REPL_ABORT_RESTART, /* eReplacementMode */
+        /**< @brief Trigger source configured */
+        ADC_TRIGG_SRC_HW, /* eTriggerSource */
+#if (STD_ON == ADC_HW_TRIGGER_API)
+        /**< @brief Hardware trigger source for the group */
+        PDB_ADC_IP_TRIGGER_IN0, /* HwTriggerSource */
+        /**< @brief Hardware trigger signal */
+        ADC_HW_TRIG_RISING_EDGE, /* eTriggerEdge */
+#endif /* (STD_ON == ADC_HW_TRIGGER_API) */
+#if (STD_ON == ADC_GRP_NOTIF_CAPABILITY)
+        /**< @brief Notification function */
+        Notification_1, /* Notification */
+#endif /* (STD_ON == ADC_GRP_NOTIF_CAPABILITY) */
+#if (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON)
+        /**< @brief Extra notification function */
+        NULL_PTR, /* ExtraNotification */
+#endif /* (ADC_ENABLE_INITIAL_NOTIFICATION == STD_ON) */
+        /**< @brief ADC Group Result Buffers RAM array */
+        Adc_aResultsBufferPtr, /* pResultsBufferPtr */
+        /**< @brief Group Streaming Buffer Mode */
+        ADC_STREAM_BUFFER_LINEAR, /* eBufferMode */
+#if (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON)
+        /**< @brief Index of the group with AdcEnableChDisableChGroup enabled */
+        (Adc_GroupType)ADC_ENABLE_CH_DISABLE_CH_INVALID_GROUP_INDEX, /* EnableChDisableChGroupIndex */
+#endif /* (ADC_ENABLE_CH_DISABLE_CH_NONAUTO_API == STD_ON) */
+        /**< @brief Number of streaming samples */
+        (Adc_StreamNumSampleType)ADC_STREAMING_NUM_SAMPLES(1), /* NumSamples */
+#if (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON)
+        /**< @brief Arrange the adc results as multiple sets of group result buffer */
+        (boolean)FALSE, /* bStreamResultGroupMultiSets */
+#endif /* (ADC_ENABLE_GROUP_STREAMING_RESULTS_REORDER == STD_ON) */
+        /**< @brief Channels assigned to the group*/
+        Adc_Group1_Assignment_1_VS_0, /* pAssignment */
+        /**< @brief Number of channels in the group*/
+        (Adc_ChannelIndexType)ADC_CFGSET_VS_0_GROUP_1_CHANNELS, /* AssignedChannelCount */
+        /**< @brief Last Channel configured */
+        (Adc_ChannelType)(ADC_ID_CHANNEL_U8(30)), /* LastCh */
+        /**< @brief First Channel configured */
+        (Adc_ChannelType)(ADC_ID_CHANNEL_U8(6)), /* FirstCh */
+        /**< @brief Enables or Disables the ADC and DMA interrupts */
+        (uint8)(STD_OFF), /* u8AdcWithoutInterrupt */
+        /**< @brief Enables or Disables configuring external DMA channel in the group */
+        (uint8)(STD_OFF), /* u8AdcExtDMAChanEnable */
+        /**< @brief When true, disables completely DMA configuration done by ADC driver for the group */
+        (boolean)FALSE, /* u8AdcWithoutDma */
+#if (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS)
+        /**< @brief Enables or Disables the ADC optimize DMA streaming groups feature */
+        (boolean)FALSE, /* bAdcOptimizeDmaStream */
+        /**< @brief Enable/disable half interrupt for group with optimize DMA streaming groups */
+        (boolean)FALSE, /* bHalfInterrupt */
+#endif /* (STD_ON == ADC_OPTIMIZE_DMA_STREAMING_GROUPS) */
+#if (ADC_ENABLE_LIMIT_CHECK == STD_ON)
+        /**< @brief Enables or disables the usage of limit checking for an ADC group. */
+        (boolean)FALSE, /* bAdcGroupLimitcheck */
+#endif /* (STD_ON == ADC_ENABLE_LIMIT_CHECK) */
+        &AdcIpwGroupConfig_1_VS_0 /* pAdcIpwGroupConfig */
+    }
+};
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CONFIG_DATA_16
+#include "Adc_MemMap.h"
+
+/**
+* @brief         Array of index for mapping the groups.
+* @details       Array of index for mapping the groups in each partition.
+*
+*/
+static const uint16 au16Adc_GroupIdToIndexMap_VS_0[ADC_MAX_GROUPS] =
+{
+    0,
+    1
+};
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_16
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+#define ADC_START_SEC_CONFIG_DATA_8
+#include "Adc_MemMap.h"
+
+/**
+* @brief         Array contains coreId used for VS_0.
+* @details       Array contains coreId used for VS_0.
+*
+*/
+static const uint8 Adc_Partition_Assignment_VS_0[1] =
+{
+    (uint8)(0UL)
+};
+
+#define ADC_STOP_SEC_CONFIG_DATA_8
+#include "Adc_MemMap.h"
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/* VariantPostBuild or more than 1 configured variant */
+
+/**
+* @brief          ADC driver Configuration structure VS_0.
+*/
+const Adc_ConfigType Adc_Config_VS_0 =
+{
+    &AdcIpwCfg_VS_0, /* pAdcIpwConfig */
+    /** @brief Group configurations */
+    Adc_GroupsCfg_VS_0, /* pGroups */
+    ADC_GROUPS_VS_0, /* GroupCount */
+    /**< @brief Array for mapping the groups */
+    au16Adc_GroupIdToIndexMap_VS_0, /* pGroupIdToIndexMap */
+    /** @brief Configuration CoreID */
+    (uint32)(0UL), /* u32CoreId */
+    /**< @brief Array contains CoreId */
+    Adc_Partition_Assignment_VS_0, /* pAssignmentPartition */
+    /**< @brief Number of Partitions */
+    (uint8)1UL /* AssignedPartitionCount */
+};
+
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Clock_Ip_VS_0_PBcfg.c

@@ -327,7 +327,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_SELECTORS_NO > 10U
             {
                 ADC1_CLK,                     /* Clock name associated to selector */
-                CLOCK_IS_OFF,                       /* Name of the selected input source */
+                SPLLDIV2_CLK,                       /* Name of the selected input source */
             },
             #endif
         

generate/src/IntCtrl_Ip_Cfg.c

@@ -94,7 +94,7 @@ static const IntCtrl_Ip_IrqConfigType aIrqConfiguration[] = {
     {LPUART1_RxTx_IRQn, (boolean)TRUE, 3U},
     {LPUART2_RxTx_IRQn, (boolean)TRUE, 3U},
     {ADC0_IRQn, (boolean)FALSE, 0U},
-    {ADC1_IRQn, (boolean)FALSE, 0U},
+    {ADC1_IRQn, (boolean)TRUE, 0U},
     {CMP0_IRQn, (boolean)FALSE, 0U},
     {ERM_single_fault_IRQn, (boolean)FALSE, 0U},
     {ERM_double_fault_IRQn, (boolean)FALSE, 0U},
@@ -206,7 +206,7 @@ static const IntCtrl_Ip_IrqRouteConfigType aIrqRouteConfig[] = {
         {LPUART1_RxTx_IRQn, 0U, LPUART_UART_IP_1_IRQHandler},
         {LPUART2_RxTx_IRQn, 0U, LPUART_UART_IP_2_IRQHandler},
         {ADC0_IRQn, 0U, undefined_handler},
-        {ADC1_IRQn, 0U, undefined_handler},
+        {ADC1_IRQn, 0U, Adc_1_Isr},
         {CMP0_IRQn, 0U, undefined_handler},
         {ERM_single_fault_IRQn, 0U, undefined_handler},
         {ERM_double_fault_IRQn, 0U, undefined_handler},

generate/src/Pdb_Adc_Ip_VS_0_PBcfg.c

@@ -0,0 +1,151 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : ADC
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup pdb_adc_ip_config Pdb Adc IPL Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Pdb_Adc_Ip_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_C                     43
+#define PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C      4
+#define PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C      4
+#define PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C   0
+#define PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_C              1
+#define PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_C              0
+#define PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_C              0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same vendor */
+#if (PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_C != PDB_ADC_IP_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Pdb_Adc_Ip_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Autosar version */
+#if ((PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H) \
+    )
+    #error "AutoSar Version Numbers of Pdb_Adc_Ip_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/* Check if Pdb_Adc_Ip_VS_0_PBcfg.c file and Pdb_Adc_Ip_VS_0_PBcfg.h file are of the same Software version */
+#if ((PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_C != PDB_ADC_IP_SW_PATCH_VERSION_VS_0_PBCFG_H) \
+    )
+  #error "Software Version Numbers of Pdb_Adc_Ip_VS_0_PBcfg.c and Pdb_Adc_Ip_VS_0_PBcfg.h are different"
+#endif
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+#define ADC_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/**
+* @brief          PDB Ip Config for Hardware Unit ADC1 for configuration variant VS_0.
+*/
+const Pdb_Adc_Ip_ConfigType PdbAdcIpConfig_0_VS_0 =
+{
+    PDB_ADC_IP_LOAD_VAL_IMMEDIATELY, /* LoadValueMode */
+    (Pdb_Adc_Ip_ClkPrescalerDivType) 0U, /* PrescalerDiv */
+    (Pdb_Adc_Ip_ClkPrescalerMultFactType) 0U, /* ClkPreMultFactor */
+    PDB_ADC_IP_SOFTWARE_TRIGGER, /* TriggerSource */
+    (boolean)FALSE, /* ContinuousModeEnable */
+    (boolean)FALSE, /* DmaEnable */
+    65535U, /* ModValue */
+#if  (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK)
+    (boolean)FALSE, /* InstanceBackToBackEnable */
+#endif /* (STD_ON == FEATURE_PDB_HAS_INSTANCE_BACKTOBACK) */
+#if  (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK)
+    (boolean)FALSE, /* InterChannelBackToBackEnable */
+#endif /* (STD_ON == FEATURE_PDB_HAS_INTERCHANNEL_BACKTOBACK) */
+    0u, /* NumChans */
+    NULL_PTR, /* ChanConfigs */
+    NULL_PTR /* SeqErrNotification */
+};
+
+
+
+#define ADC_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Adc_MemMap.h"
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Power_Ip_VS_0_PBcfg.c

@@ -201,7 +201,7 @@ static const Power_Ip_PMC_ConfigType Power_Ip_PMC_ConfigPB_VS_0 =
     (
         PMC_REGSC_LPO_ENABLE_U8 |
         PMC_REGSC_CLKBIAS_ENABLE_U8 |
-        PMC_REGSC_BIAS_DISABLE_U8
+        PMC_REGSC_BIAS_ENABLE_U8
     )
 };
 

src/hal_adapter.c

@@ -9,6 +9,11 @@
 
  uint8_t __attribute__((section(".non_cacheable_data"))) RX_Buffer[3][BUFFER_SIZE];
  uint32_t bufferIdx[3] = {0};
+
+
+volatile uint32 VarNotification_0 = 0;
+volatile uint32 VarNotification_1 = 0;
+
  Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen,uint32 T_timeout)
  {
      volatile Std_ReturnType R_Uart_Status;
@@ -342,3 +347,82 @@
      (void)Error;
  }
 
+ void Notification_0(void)
+ {
+     VarNotification_0++;
+ }
+
+ void Notification_1(void)
+ {
+     VarNotification_1++;
+ }
+
+
+
+ Std_ReturnType  ADC_Converter(Adc_ValueGroupType* Buffer, TP_Value_Type* ConvertedValueR)
+ {
+	 Adc_ValueGroupType REFH,REFL;
+	 REFH = Buffer[0];
+	 REFL = Buffer[2];
+	 for(int i = 3; i < NUM_RESULTS; i++)
+	 {
+		 ConvertedValueR[i] = (TP_Value_Type)((float)(10000 * Buffer[i]/(float)(REFH - REFL))/(1-(float)(Buffer[i]/(float)(REFH - REFL))));
+	 }
+ }
+
+ Std_ReturnType  ADC_ReadValue(ADC_TP_Channel_Type channel, TP_Value_Type* value)
+ {
+	 Std_ReturnType ret = E_NOT_OK;
+
+	 Adc_ValueGroupType    ResultBuffer[NUM_RESULTS];
+	 Adc_ValueGroupType    AdcReadGroupBuffer[NUM_RESULTS];
+
+	 TP_Value_Type    ConvertedBuffer[NUM_RESULTS];
+	 volatile Std_ReturnType Status = TRUE;
+
+	 for(int i = 0; i<NUM_RESULTS; i++)
+	 {
+		 ResultBuffer[i] = 0xFFFF;
+		 AdcReadGroupBuffer[i] = 0xFFFE;
+		 ConvertedBuffer[i] = 0x00;
+	 }
+
+	 Adc_SetupResultBuffer(AdcGroupSoftwareOneShot, ResultBuffer);
+	 Adc_EnableGroupNotification(AdcGroupSoftwareOneShot);
+	 VarNotification_0 = 0;
+	 Adc_StartGroupConversion(AdcGroupSoftwareOneShot);
+
+	 while(VarNotification_0 == 0)
+	 {}
+	 Status = Adc_ReadGroup(AdcGroupSoftwareOneShot, AdcReadGroupBuffer);
+	 if(Status == E_NOT_OK)
+	 {
+		 return Status;
+	 }
+	 else
+	 {
+		 ret = E_OK;
+	 }
+
+	 ADC_Converter(ResultBuffer,ConvertedBuffer);
+	 switch(channel)
+	 {
+		 case SystemTPChannel:
+			 *value = ConvertedBuffer[3];
+			 break;
+		 case SlowChargeTPChannel:
+			 *value = ConvertedBuffer[4];
+			 break;
+		 case QuickChargeTPChannel:
+			 *value = ConvertedBuffer[5];
+			 break;
+		 case CC1TPChannel:
+			 *value = ConvertedBuffer[6];
+			 break;
+		 default:
+			 *value = 0xFFF;
+			 Status = E_NOT_OK;
+			 break;
+	 }
+	 return ret;
+ }

src/hal_adapter.h

@@ -36,6 +36,8 @@
  #include "timers.h"
  #include "task.h"
  #include "semphr.h"
+ #include "Adc.h"
+
  #define UART_LPUART0 0
  #define UART_LPUART1 1
  #define UART_LPUART2 2
@@ -49,12 +51,18 @@
 
  #define BUFFER_SIZE 1000
  #define DMA_SIZE 20
+
+
+#define RESULT_ADC_VREFL        (0u)        /* VrefL is 0V */
+#define RESULT_ADC_VREFH        (4096u)     /* VrefH is 5V */
+#define RESULT_ADC_BANDGAP      (819u)      /* Vbandgap ~ 1.15V at 5V reference */
+#define RESULT_TOLERANCE        (150u)
+
+#define NUM_RESULTS             ADC_CFGSET_VS_0_GROUP_0_CHANNELS
+
  extern uint8_t RX_Buffer[3][BUFFER_SIZE];
 // extern uint8 GpsBufferGet[GPSBUFFER_SIZE];
- Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen,uint32 T_timeout);
- Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout);
- Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer,uint16 *rxlen, sint32 T_timeout);
- void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event);
+
 
  /*CAN*/
  typedef enum
@@ -84,4 +92,22 @@
 	 uint8 data[8];
  }Can_Msg_Type_Data;
  extern Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg);
+
+ typedef enum
+ {
+	 SystemTPChannel = 0,
+	 SlowChargeTPChannel,
+	 QuickChargeTPChannel,
+	 CC1TPChannel,
+	 ChannelCounter = 4,
+ }ADC_TP_Channel_Type;
+
+ typedef uint32 TP_Value_Type;
+
+ Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen,uint32 T_timeout);
+ Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout);
+ Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer,uint16 *rxlen, sint32 T_timeout);
+ void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event);
+ Std_ReturnType  ADC_ReadValue(ADC_TP_Channel_Type channel, TP_Value_Type* value);
+
 #endif /* HAL_ADAPTER_H_ */

src/main.c

@@ -52,9 +52,13 @@
 
 #include "AppTaskUart1.h"
 #include "AppTaskCan.h"
+
+
 int main(void)
 {
 	volatile int exit_code = 0;
+
+
 	/* Initialize the Mcu driver */
 #if (MCU_PRECOMPILE_SUPPORT == STD_ON)
 	Mcu_Init(NULL_PTR);
@@ -75,23 +79,9 @@ int main(void)
 
 	Mcu_SetMode(McuModeSettingConf_Run);
 	OsIf_Init(NULL_PTR);
+
+	/* Initialize Platform driver */
 	Platform_Init(NULL_PTR);
-	//    Platform_InstallIrqHandler(LPUART0_RxTx_IRQn, LPUART_UART_IP_0_IRQHandler, NULL_PTR);
-	//    Platform_InstallIrqHandler(LPUART1_RxTx_IRQn, LPUART_UART_IP_1_IRQHandler, NULL_PTR);
-	//    Platform_InstallIrqHandler(LPUART2_RxTx_IRQn, LPUART_UART_IP_2_IRQHandler, NULL_PTR);
-	//    Platform_InstallIrqHandler(FLEXIO_IRQn, MCL_FLEXIO_ISR, NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA0_IRQn,Dma0_Ch0_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA1_IRQn,Dma0_Ch1_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA2_IRQn,Dma0_Ch2_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA3_IRQn,Dma0_Ch3_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA4_IRQn,Dma0_Ch4_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(DMA5_IRQn,Dma0_Ch5_IRQHandler,NULL_PTR);
-
-	//    Platform_InstallIrqHandler(CAN0_ORed_IRQn,IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(CAN0_Error_IRQn,Dma0_Ch5_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(CAN0_Wake_Up_IRQn,Dma0_Ch5_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(CAN0_ORed_0_15_MB_IRQn,Dma0_Ch5_IRQHandler,NULL_PTR);
-	//    Platform_InstallIrqHandler(CAN0_ORed_16_31_MB_IRQn,Dma0_Ch5_IRQHandler,NULL_PTR);
 
 	/* Initialize all pins*/
 #if (PORT_PRECOMPILE_SUPPORT == STD_ON)
@@ -106,33 +96,45 @@ int main(void)
 #elif (UART_PRECOMPILE_SUPPORT == STD_OFF)
 	Uart_Init(&Uart_xConfig_VS_0);
 #endif
+	IP_LPUART1->CTRL |= LPUART_CTRL_ILT(1);
+	IP_LPUART2->CTRL |= LPUART_CTRL_ILT(1);
+
 
-#if 1 /* Initialize Platform driver */
 #if (CAN_PRECOMPILE_SUPPORT == STD_ON)
 	Can_Init(NULL_PTR);
 #elif (CAN_PRECOMPILE_SUPPORT == STD_OFF)
 	Can_Init(&Can_Config_VS_0);
 #endif
 	Can_SetControllerMode(CanController_0, CAN_CS_STARTED);
-#endif
-	//	Can_SetControllerMode(CanController_1, CAN_CS_STARTED);
-	//	Dio_WriteChannel(DioConf_DioChannel_PTE4_GPIO_OUT_MCU_4G_POW_EN,STD_ON);  //ʹÄÜpower
-	//	Dio_WriteChannel(DioConf_DioChannel_PTB20_GPIO_OUT_MCU_4G_PWRKEY,STD_ON);
-	// Dio_WriteChannel(DioConf_DioChannel_PTB20_GPIO_OUT_MCU_4G_PWRKEY,STD_OFF);
-
-	//	Dio_WriteChannel(DioConf_DioChannel_PTB19_GPIO_OUT_MCU_4G_DTR,STD_ON); //DTR À­µÍ
-	// Dio_WriteChannel(DioConf_DioChannel_PTB19_GPIO_OUT_MCU_4G_DTR,STD_OFF); //DTR À­µÍ
-
-	//	Dio_WriteChannel(PortConfigSet_PortContainer_GPIO_PTE7_GPIO_OUT_MCU_BT_MOD,STD_ON);
-	//	Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN,STD_ON);
-	// Dio_WriteChannel(DioConf_DioChannel_PTB18_GPIO_OUT_MCU_4G_RESET,STD_OFF);
-	// DioConf_DioChannel_PTB18_GPIO_OUT_MCU_4G_RESET
-	IP_LPUART1->CTRL |= LPUART_CTRL_ILT(1);
-	IP_LPUART2->CTRL |= LPUART_CTRL_ILT(1);
+
+
+#if (ADC_PRECOMPILE_SUPPORT == STD_ON)
+    Adc_Init(NULL_PTR);
+#else
+    Adc_Init(&Adc_Config_VS_0);
+#endif /* ADC_PRECOMPILE_SUPPORT == STD_ON */
+
+
+    //this function should be called in ADC Task at once
+    Adc_CalibrationStatusType CalibStatus;
+    Adc_Calibrate(AdcHwUnit_0, &CalibStatus);
+	if(CalibStatus.Adc_UnitSelfTestStatus == E_NOT_OK)
+	{
+		//if so, the adc is failed to Calibrate;
+	}
+	TP_Value_Type value = 0;
+	for(ADC_TP_Channel_Type channel = 0; channel <ChannelCounter; channel++ )
+	{
+		ADC_ReadValue(channel,&value);
+	}
+
+
+
 	xTaskCreate(Uart_4G_Task, (const char *const)"Uart_4G_Task", 256 + 64, (void *)0, main_TASK_PRIORITY, NULL);
 	xTaskCreate(CanTask, (const char *const)"CanTask", 256, (void *)0, main_TASK_PRIORITY + 1, NULL);
 	xTaskCreate(GpsTask, (const char *const)"GpsTask", 256, (void *)0, main_TASK_PRIORITY + 2, NULL);
 	vTaskStartScheduler();
+
 	for (;;)
 	{
 		if (exit_code != 0)