平峰测试，更改了UART，增加了电表数据读取，更改了锁定解锁，FTP更新未加，UART存在 偶发性读不到

.cproject

@@ -37,6 +37,7 @@
 								<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.2141010934" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.203066772" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../FreeRTOS/Source/include"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
 									<listOptionValue builtIn="false" value="../RTD/include"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/Source/portable/GCC/ARM_CM4F}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/Source/portable/MemMang}&quot;"/>
@@ -772,7 +773,20 @@
 	</storageModule>
 	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
 	<storageModule moduleId="org.eclipse.embsys" parent_project="true" register_architecture="" register_board="---  none ---" register_chip="" register_core="" register_vendor=""/>
-	<storageModule moduleId="refreshScope"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="Release_FLASH">
+			<resource resourceType="PROJECT" workspacePath="/S32K146_4G"/>
+		</configuration>
+		<configuration configurationName="Release_RAM">
+			<resource resourceType="PROJECT" workspacePath="/S32K146_4G"/>
+		</configuration>
+		<configuration configurationName="Debug_FLASH">
+			<resource resourceType="PROJECT" workspacePath="/S32K146_4G"/>
+		</configuration>
+		<configuration configurationName="Debug_RAM">
+			<resource resourceType="PROJECT" workspacePath="/S32K146_4G"/>
+		</configuration>
+	</storageModule>
 	<storageModule moduleId="com.nxp.s32ds.cle.uct.core">
 		<sdkComponents>platform.driver.osif;platform.driver.det;platform.driver.rte_can;platform.driver.rte_dio;platform.driver.rte_mcu;platform.driver.rte_mcl;platform.driver.rte_port;platform.driver.rte_uart;platform.os.freertos;platform.driver.Can;platform.driver.CanIf;platform.driver.dio;platform.driver.ecum;platform.driver.mcu;platform.driver.mcl;platform.driver.Platform;platform.driver.port;platform.driver.uart;platform.driver.clock;platform.driver.adc;platform.driver.rte_adc</sdkComponents>
 		<COND_TOOLCHAIN_ADD_REMOVE_COMPONENTS_OPTION>true</COND_TOOLCHAIN_ADD_REMOVE_COMPONENTS_OPTION>

.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="317783601230043299" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1869165178597326029" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -16,7 +16,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="317783601230043299" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1869165178597326029" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -27,7 +27,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="317783601230043299" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1869165178597326029" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -38,7 +38,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="317783601230043299" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1869165178597326029" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

Project_Settings/Debugger/S32K146_4G_Debug_FLASH_PNE.launch

@@ -216,5 +216,5 @@
 </listAttribute>
 <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;&gt;&#13;&#10;&lt;gdbmemoryBlockExpression address=&quot;536806032&quot; label=&quot;RX_Buffer[UART_LPUART2]&quot;/&gt;&#13;&#10;&lt;gdbmemoryBlockExpression address=&quot;536823956&quot; label=&quot;GpsBufferGet&quot;/&gt;&#13;&#10;&lt;gdbmemoryBlockExpression address=&quot;255&quot; label=&quot;SocketId&quot;/&gt;&#13;&#10;&lt;gdbmemoryBlockExpression address=&quot;536805632&quot; label=&quot;0x1fff0100&quot;/&gt;&#13;&#10;&lt;gdbmemoryBlockExpression address=&quot;536806632&quot; label=&quot;0x1fff04e8&quot;/&gt;&#13;&#10;&lt;/memoryBlockExpressionList&gt;&#13;&#10;"/>
 <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-<stringAttribute key="saved_expressions&lt;seperator&gt;Unknown" value="1fff3798,0x1fff3798,0x1fffab2c,0x1fffa82c,0x1fff01f3,0x1fff050e,0,0x14200,0x14000,0x0,0x1fffb21c,0x1fffb600,0x1fff04e8,14000000,0x14000000"/>
+<stringAttribute key="saved_expressions&lt;seperator&gt;Unknown" value="0x1fff050e,0,0x14200,0x14000,0x0,0x1fffb21c,0x1fffb600,0x1fff04e8,14000000,0x14000000,0x1fffbd12,0x1fffb0f0,0x1fff0500,0x1fffbe28,0x1fffbca0"/>
 </launchConfiguration>

RTD/include/Fls.h

@@ -0,0 +1,198 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef FLS_H
+#define FLS_H
+
+/**
+*   @file Fls.h
+*
+*   @addtogroup FLS FLS Driver
+*   @{
+*/
+
+/* implements Fls.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "OsIf.h"
+#include "Fls_Cfg.h"
+#include "Fls_Api.h"
+
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VENDOR_ID                    43
+#define FLS_AR_RELEASE_MAJOR_VERSION     4
+#define FLS_AR_RELEASE_MINOR_VERSION     4
+#define FLS_AR_RELEASE_REVISION_VERSION  0
+#define FLS_SW_MAJOR_VERSION             1
+#define FLS_SW_MINOR_VERSION             0
+#define FLS_SW_PATCH_VERSION             0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if header file and Mcal.h header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls.h and Mcal.h are different"
+    #endif
+    /* Check if header file and OsIf.h header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION != OSIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls.h and OsIf.h are different"
+    #endif
+#endif
+
+/* Check if header file and Fls_Cfg.h header file are of the same vendor */
+#if (FLS_VENDOR_ID != FLS_VENDOR_ID_CFG)
+    #error "Fls.h and Fls_Cfg.h have different vendor ids"
+#endif
+/* Check if header file and Fls_Cfg.h header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION    != FLS_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_MINOR_VERSION    != FLS_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_REVISION_VERSION != FLS_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls.h and Fls_Cfg.h are different"
+#endif
+/* Check if header file and Fls_Cfg.h header file are of the same software version */
+#if ((FLS_SW_MAJOR_VERSION != FLS_SW_MAJOR_VERSION_CFG) || \
+     (FLS_SW_MINOR_VERSION != FLS_SW_MINOR_VERSION_CFG) || \
+     (FLS_SW_PATCH_VERSION != FLS_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls.h and Fls_Cfg.h are different"
+#endif
+
+/* Check if header file and Fls_Api.h header file are of the same vendor */
+#if (FLS_VENDOR_ID != FLS_API_VENDOR_ID)
+    #error "Fls.h and Fls_Api.h have different vendor ids"
+#endif
+/* Check if header file and Fls_Api.h header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION    != FLS_API_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_AR_RELEASE_MINOR_VERSION    != FLS_API_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_AR_RELEASE_REVISION_VERSION != FLS_API_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls.h and Fls_Api.h are different"
+#endif
+/* Check if header file and Fls_Api.h header file are of the same software version */
+#if ((FLS_SW_MAJOR_VERSION != FLS_API_SW_MAJOR_VERSION) || \
+     (FLS_SW_MINOR_VERSION != FLS_API_SW_MINOR_VERSION) || \
+     (FLS_SW_PATCH_VERSION != FLS_API_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls.h and Fls_Api.h are different"
+#endif
+
+
+
+/*==================================================================================================
+                                          CONSTANTS
+==================================================================================================*/
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+FLS_CONFIG_EXT
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/*! Invalid device instance */
+#define FLS_DEVICE_INSTANCE_INVALID       (0xFFU)
+
+
+/*==================================================================================================
+                                       GLOBAL VARIABLES
+==================================================================================================*/
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+#define FLS_START_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+
+extern boolean Fls_bACloaded;
+
+#define FLS_STOP_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+#endif
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/**
+ * @brief Logical address of data block currently processed by Fls_MainFunction
+ */
+extern Fls_AddressType Fls_u32JobAddrIt;
+/**
+ * @brief Last logical address to be processed by a job
+ */
+extern Fls_AddressType Fls_u32JobAddrEnd;
+/**
+ * @brief Index of flash sector currently processed by a job
+ * @details Used by all types of job
+ */
+extern volatile Fls_SectorIndexType Fls_u32JobSectorIt;
+/**
+ * @brief Index of last flash sector by current job
+ * @details Used to check status of all external flash chips before start jobs
+ * or is the last sector in Erease job
+ */
+extern Fls_SectorIndexType Fls_u32JobSectorEnd;
+/**
+ * @brief Result of last flash hardware job
+ */
+extern volatile MemIf_JobResultType Fls_eLLDJobResult;
+/**
+ * @brief Type of current flash hardware job - used for asynchronous operating mode.
+ */
+extern Fls_LLDJobType Fls_eLLDJob;
+
+/**
+ * @brief Pointer to current flash module configuration set
+ */
+extern const Fls_ConfigType * Fls_pConfigPtr;
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FLS_H */

RTD/include/Fls_Api.h

@@ -0,0 +1,548 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef FLS_API_H
+#define FLS_API_H
+
+/**
+*   @file Fls_Api.h
+*
+*   @addtogroup FLS FLS Driver
+*   @{
+*/
+
+/* implements Fls_Api.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls_Cfg.h"
+#include "MemIf_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+/**
+* @brief          Version Check parameters.
+*/
+#define FLS_API_VENDOR_ID                    43
+#define FLS_API_AR_RELEASE_MAJOR_VERSION     4
+#define FLS_API_AR_RELEASE_MINOR_VERSION     4
+#define FLS_API_AR_RELEASE_REVISION_VERSION  0
+#define FLS_API_SW_MAJOR_VERSION             1
+#define FLS_API_SW_MINOR_VERSION             0
+#define FLS_API_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls_Cfg.h file are of the same vendor */
+#if (FLS_API_VENDOR_ID != FLS_VENDOR_ID_CFG)
+    #error "Fls_Api.h and Fls_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Fls_Cfg.h file are of the same Autosar version */
+#if ((FLS_API_AR_RELEASE_MAJOR_VERSION    != FLS_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_API_AR_RELEASE_MINOR_VERSION    != FLS_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_API_AR_RELEASE_REVISION_VERSION != FLS_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_Api.h and Fls_Cfg.h are different"
+#endif
+/* Check if current file and Fls_Cfg.h file are of the same software version */
+#if ((FLS_API_SW_MAJOR_VERSION != FLS_SW_MAJOR_VERSION_CFG) || \
+     (FLS_API_SW_MINOR_VERSION != FLS_SW_MINOR_VERSION_CFG) || \
+     (FLS_API_SW_PATCH_VERSION != FLS_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_Api.h and Fls_Cfg.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and MemIf_Types.h file are of the same Autosar version */
+    #if ((FLS_API_AR_RELEASE_MAJOR_VERSION    != MEMIF_AR_RELEASE_MAJOR_VERSION) || \
+        (FLS_API_AR_RELEASE_MINOR_VERSION    != MEMIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls_Api.h and MemIf_Types.h are different"
+    #endif
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/**
+*  @brief AUTOSAR module identification
+*/
+#define FLS_MODULE_ID            92
+/**
+*  @brief AUTOSAR module instance identification
+*/
+#define FLS_INSTANCE_ID          0U
+/**
+* @brief          Development error codes (passed to DET).
+* @implements     DETERRORCODE_enumeration
+*/
+
+/**
+*  @brief API service called with wrong config parameter
+*/
+#define FLS_E_PARAM_CONFIG           0x01U
+/**
+*  @brief API service called with wrong address parameter
+*/
+#define FLS_E_PARAM_ADDRESS          0x02U
+/**
+*  @brief API service called with wrong length parameter
+*/
+#define FLS_E_PARAM_LENGTH           0x03U
+/**
+*  @brief API service called with wrong data parameter
+*/
+#define FLS_E_PARAM_DATA             0x04U
+/**
+*  @brief API service called without module initialization
+*/
+#define FLS_E_UNINIT                 0x05U
+/**
+*  @brief API service called while driver still busy
+*/
+#define FLS_E_BUSY                   0x06U
+/**
+*  @brief API service called with NULL pointer
+*/
+#define FLS_E_PARAM_POINTER          0x0AU
+/**
+* @brief          Runtime error codes (passed to DET).
+*/
+
+/**
+* @brief          Erase verification (blank check) failed
+*/
+#define FLS_E_VERIFY_ERASE_FAILED    0x07U
+/**
+* @brief          Write verification (compare) failed
+*/
+#define FLS_E_VERIFY_WRITE_FAILED    0x08U
+/**
+* @brief           Timeout exceeded
+*/
+#define FLS_E_TIMEOUT                0x09U
+
+/**
+* @brief          Transient Faults codes (passed to DET).
+*/
+/**
+* @brief           Flash erase failed (HW)
+*/
+#define FLS_E_ERASE_FAILED           0x01U
+/**
+* @brief           Flash write failed (HW)
+*/
+#define FLS_E_WRITE_FAILED           0x02U
+/**
+* @brief           Flash read failed (HW)
+*/
+#define FLS_E_READ_FAILED            0x03U
+/**
+* @brief           Flash compare failed (HW)
+*/
+#define FLS_E_COMPARE_FAILED         0x04U
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+    #define FLS_E_UNEXPECTED_FLASH_ID    0x05U /* Expected hardware ID not matched */
+#endif
+/**
+* @brief          All service IDs (passed to DET).
+* @implements     SERVICEIDs_enumeration
+*/
+
+/**
+*   @brief service ID of function: Fls_Init. (passed to DET)
+*/
+#define FLS_INIT_ID                  0x00U
+/**
+*   @brief service ID of function: Fls_Erase. (passed to DET)
+*/
+#define FLS_ERASE_ID                 0x01U
+/**
+*   @brief service ID of function: Fls_Write. (passed to DET)
+*/
+#define FLS_WRITE_ID                 0x02U
+/**
+*   @brief service ID of function: Fls_Cancel. (passed to DET)
+*/
+#define FLS_CANCEL_ID                0x03U
+/**
+*   @brief service ID of function: Fls_GetJobResult. (passed to DET)
+*/
+#define FLS_GETJOBRESULT_ID          0x05U
+/**
+*   @brief service ID of function: Fls_MainFunction. (passed to DET)
+*/
+#define FLS_MAINFUNCTION_ID          0x06U
+/**
+*   @brief service ID of function: Fls_Read. (passed to DET)
+*/
+#define FLS_READ_ID                  0x07U
+/**
+*   @brief service ID of function: Fls_Compare. (passed to DET)
+*/
+#define FLS_COMPARE_ID               0x08U
+/**
+*   @brief service ID of function: Fls_SetMode. (passed to DET)
+*/
+#define FLS_SETMODE_ID               0x09U
+/**
+*   @brief service ID of function: Fls_GetVersionInfo. (passed to DET)
+*/
+#define FLS_GETVERSIONINFO_ID        0x10U
+/**
+*   @brief service ID of function: Fls_BlankCheck. (passed to DET)
+*/
+#define FLS_BLANK_CHECK_ID           0x11U
+
+/**
+* @brief          All sector flags.
+*/
+
+/**
+*   @brief fls sector erase asynch
+*/
+#define FLS_SECTOR_ERASE_ASYNCH      0x01U
+/**
+*   @brief fls page write asynch
+*/
+#define FLS_PAGE_WRITE_ASYNCH        0x02U
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/**
+* @brief    Start of Fls section CODE
+*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+/**
+ * @brief        The function initializes Fls module.
+ * @details      The function sets the internal module variables according to given
+ *               configuration set.
+ *
+ * @param[in]    pConfigPtr        Pointer to flash driver configuration set.
+ *
+ * @api
+ *
+ * @pre          @p pConfigPtr must not be @p NULL_PTR and the module status must not
+ *               be @p MEMIF_BUSY.
+ *
+ *
+ */
+extern void Fls_Init(const Fls_ConfigType * pConfigPtr);
+
+/**
+ * @brief            Write one or more complete flash pages to the flash device.
+ * @details          Starts a write job asynchronously. The actual job is performed by
+ *                   @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress        Target address in flash memory.
+ * @param[in]        pSourceAddressPtr       Pointer to source data buffer.
+ * @param[in]        u32Length               Number of bytes to write.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                 Write command has been accepted.
+ * @retval           E_NOT_OK             Write command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Write changes module status and some internal variables
+ *                  (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                  @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ */
+extern Std_ReturnType Fls_Write(Fls_AddressType u32TargetAddress,
+                                const uint8 * pSourceAddressPtr,
+                                Fls_LengthType u32Length
+                               );
+
+/**
+ * @brief            Erase one or more complete flash sectors.
+ * @details          Starts an erase job asynchronously. The actual job is performed
+ *                   by the @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress        Target address in flash memory.
+ * @param[in]        u32Length               Number of bytes to erase.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                    Erase command has been accepted.
+ * @retval           E_NOT_OK                Erase command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Erase changes module status and some internal variables
+ *                   (@p Fls_u32JobSectorIt, @p Fls_u32JobSectorEnd, @p Fls_Job,
+ *                   @p Fls_eJobResult).
+ *
+ *
+ */
+extern Std_ReturnType Fls_Erase(Fls_AddressType u32TargetAddress,
+                                Fls_LengthType u32Length
+                               );
+
+#if ( FLS_CANCEL_API == STD_ON )
+/**
+ * @brief            Cancel an ongoing flash read, write, erase or compare job.
+ * @details          Abort a running job synchronously so that directly after returning
+ *                   from this function a new job can be started.
+ *
+ * @api
+ *
+ * @pre              The module must be initialized.
+ * @post             @p Fls_Cancel changes module status and @p Fls_eJobResult
+ *                   internal variable.
+ *
+ *
+ */
+extern void Fls_Cancel( void );
+#endif    /* FLS_CANCEL_API == STD_ON */
+
+#if ( FLS_GET_STATUS_API == STD_ON )
+/**
+ * @brief            Returns the FLS module status.
+ * @details          Returns the FLS module status synchronously.
+ *
+ * @return           MemIf_StatusType
+ * @retval           MEMIF_UNINIT        Module has not been initialized (yet).
+ * @retval           MEMIF_IDLE          Module is currently idle.
+ * @retval           MEMIF_BUSY          Module is currently busy.
+ *
+ * @api
+ *
+ */
+extern MemIf_StatusType Fls_GetStatus( void );
+#endif    /* FLS_GET_STATUS_API == STD_ON */
+
+#if ( FLS_GET_JOB_RESULT_API == STD_ON )
+/**
+ * @brief            Returns the result of the last job.
+ * @details          Returns synchronously the result of the last job.
+ *
+ * @return           MemIf_JobResultType
+ * @retval           MEMIF_JOB_OK              Successfully completed job.
+ * @retval           MEMIF_JOB_FAILED          Not successfully completed job.
+ * @retval           MEMIF_JOB_PENDING         Still pending job (not yet completed).
+ * @retval           MEMIF_JOB_CANCELED        Job has been cancelled.
+ * @retval           MEMIF_BLOCK_INCONSISTENT  Inconsistent block requested, it may
+ *                                             contains corrupted data.
+ * @retval           MEMIF_BLOCK_INVALID       Invalid block requested.
+ *
+ * @api
+ *
+ * @implements       Fls_GetJobResult_Activity
+ *
+ */
+extern MemIf_JobResultType Fls_GetJobResult( void );
+#endif    /* FLS_GET_JOB_RESULT_API == STD_ON */
+
+
+/**
+ * @brief            Reads from flash memory.
+ * @details          Starts a read job asynchronously. The actual job is performed by
+ *                   @p Fls_MainFunction.
+ *
+ * @param[in]        u32SourceAddress        Source address in flash memory.
+ * @param[in]        u32Length               Number of bytes to read.
+ * @param[out]       pTargetAddressPtr       Pointer to target data buffer.
+ *
+ * @return           MemIf_JobResultType
+ * @retval           MEMIF_JOB_OK              Successfully completed job.
+ * @retval           MEMIF_JOB_FAILED          Not successfully completed job.
+ * @retval           MEMIF_JOB_PENDING         Still pending job (not yet completed).
+ * @retval           MEMIF_JOB_CANCELED        Job has been canceled.
+ * @retval           MEMIF_BLOCK_INCONSISTENT  Inconsistent block requested, it may
+ *                                             contains corrupted data.
+ * @retval           MEMIF_BLOCK_INVALID       Invalid block requested.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_Read changes module status and some internal variables
+ *                 (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                 @p Fls_pJobDataDestPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ *
+ */
+extern Std_ReturnType Fls_Read(Fls_AddressType u32SourceAddress,
+                               uint8 * pTargetAddressPtr,
+                               Fls_LengthType u32Length
+                              );
+
+#if ( FLS_COMPARE_API == STD_ON )
+/**
+ * @brief           Compares a flash memory area with an application data buffer.
+ * @details         Starts a compare job asynchronously. The actual job is performed by
+ *                  @p Fls_MainFunction.
+ *
+ * @param[in]        u32SourceAddress          Source address in flash memory.
+ * @param[in]        pTargetAddressPtr        Pointer to source data buffer.
+ * @param[in]        u32Length                 Number of bytes to compare.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                      Compare command has been accepted.
+ * @retval           E_NOT_OK                   Compare command has not been accepted.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_Read changes module status and some internal variables
+ *                (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ */
+extern Std_ReturnType Fls_Compare(Fls_AddressType u32SourceAddress,
+                                  const uint8 * pTargetAddressPtr,
+                                  Fls_LengthType u32Length
+                                 );
+
+#endif /* FLS_COMPARE_API == STD_ON */
+
+
+#if (FLS_BLANK_CHECK_API == STD_ON)
+/**
+ * @brief           Verify whether a given memory area has been erased but not (yet) programmed.
+ * @details         Starts a compare job asynchronously. The actual job is performed by
+ *                  @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress          Address in flash memory from which the blank check should be started.
+ * @param[in]        u32Length                 Number of bytes to be checked for erase pattern.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                   Blank checking command has been accepted.
+ * @retval           E_NOT_OK               Blank checking command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Read changes module status and some internal variables
+ *                   (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                   @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ * @implements       Fls_BlankCheck_Activity
+ *
+ */
+Std_ReturnType Fls_BlankCheck(Fls_AddressType u32TargetAddress,
+                              Fls_LengthType u32Length
+                             );
+#endif /* FLS_BLANK_CHECK_API == STD_ON */
+
+#if (FLS_SET_MODE_API == STD_ON) || defined(__DOXYGEN__)
+/**
+ * @brief           Sets the FLS module's operation mode to the given Mode.
+ * @details         Every given mode determinates maximum bytes for read-write
+ *                  operations. Every mode has a set of pre-configured values.
+ *
+ * @param[in]       eMode        MEMIF_MODE_FAST or MEMIF_MODE_SLOW.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_SetMode changes internal variables @p Fls_u32MaxRead and
+ *                 @p Fls_u32MaxWrite.
+ *
+ */
+extern void Fls_SetMode(MemIf_ModeType eMode);
+#endif /* FLS_SET_MODE_API == STD_ON */
+
+#if ( FLS_VERSION_INFO_API == STD_ON )
+/**
+ * @brief        Returns version information about FLS module.
+ * @details      Version information includes:
+ *               - Module Id
+ *               - Vendor Id
+ *               - Vendor specific version numbers (BSW00407).
+ *
+ * @param[inout] pVersionInfoPtr  Pointer to where to store the version information of this module.
+ *
+ * @api
+ *
+ */
+extern void Fls_GetVersionInfo(Std_VersionInfoType * pVersionInfoPtr);
+#endif /* FLS_VERSION_INFO_API == STD_ON */
+
+#if ( STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED )
+#if ( (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) )
+/**
+* @brief          Low level data storage exception handler.
+* @details        Low level data storage exception handler.
+*
+* @param[in] pExceptionDetailsPtr  Exception pointer
+*
+* @return         Exc_CompHandlerReturnType
+* @retval         EXC_HANDLED_SKIP The data storage exception was
+*                 caused by currently pending flash read or compare job
+* @retval         EXC_UNHANDLED The data storage exception was
+*                 NOT caused by currently pending flash read or compare job
+*
+* @implements    Fls_DsiHandler_Activity
+*/
+extern Fls_CompHandlerReturnType Fls_DsiHandler(const Fls_ExceptionDetailsType * pExceptionDetailsPtr);
+#endif /* (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) */
+
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+/**
+ * @brief         In the FlsReadFunctionCallout, user can start a task and call this function to performs the actual copy operation.
+ *
+ * @implements    Fls_ReadEachBlock_Activity
+ */
+extern void Fls_ReadEachBlock(void);
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+
+#endif /* STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED */
+
+/**
+* @brief    Stop of Fls section CODE
+*/
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+
+#endif /* FLS_API_H */

RTD/include/Fls_IPW.h

@@ -0,0 +1,173 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef FLS_IPW_H
+#define FLS_IPW_H
+
+/**
+*   @file Fls_IPW.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+/* implements Fls_IPW.h_Artifact */
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls.h"
+#include "Qspi_Ip_Features.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_IPW_VENDOR_ID_H                       43
+#define FLS_IPW_AR_RELEASE_MAJOR_VERSION_H        4
+#define FLS_IPW_AR_RELEASE_MINOR_VERSION_H        4
+#define FLS_IPW_AR_RELEASE_REVISION_VERSION_H     0
+#define FLS_IPW_SW_MAJOR_VERSION_H                1
+#define FLS_IPW_SW_MINOR_VERSION_H                0
+#define FLS_IPW_SW_PATCH_VERSION_H                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls header file are of the same vendor */
+#if (FLS_IPW_VENDOR_ID_H != FLS_VENDOR_ID)
+    #error "Fls_IPW.c and Fls.h have different vendor ids"
+#endif
+/* Check if current file and Fls header file are of the same Autosar version */
+#if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_H    != FLS_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_IPW_AR_RELEASE_MINOR_VERSION_H    != FLS_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_IPW_AR_RELEASE_REVISION_VERSION_H != FLS_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls_IPW.c and Fls.h are different"
+#endif
+/* Check if current file and Fls header file are of the same Software version */
+#if ((FLS_IPW_SW_MAJOR_VERSION_H != FLS_SW_MAJOR_VERSION) || \
+     (FLS_IPW_SW_MINOR_VERSION_H != FLS_SW_MINOR_VERSION) || \
+     (FLS_IPW_SW_PATCH_VERSION_H != FLS_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_IPW.c and Fls.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (FLS_IPW_VENDOR_ID_H != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Fls_IPW.c and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_IPW_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_IPW_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_IPW.c and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((FLS_IPW_SW_MAJOR_VERSION_H != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (FLS_IPW_SW_MINOR_VERSION_H != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (FLS_IPW_SW_PATCH_VERSION_H != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_IPW.c and Qspi_Ip_Features.h are different"
+#endif
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*! Invalid configuration, specifies unused device */
+#define FLS_IPW_CFG_INVALID          (uint8)0xFFU
+
+
+/*==================================================================================================
+*                                    VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    DEFINES AND MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+void Fls_IPW_Init(void);
+void Fls_IPW_AbortSuspended(void);
+void Fls_IPW_ClearHVJob(void);
+void Fls_IPW_Cancel(void);
+void Fls_IPW_LLDMainFunction(void);
+
+Fls_LLDReturnType Fls_IPW_SectorRead(const Fls_AddressType u32SectorOffset,
+                                     const Fls_AddressType u32Length,
+                                     uint8 * pJobDataDestPtr,
+                                     const uint8 * pJobDataSrcPtr
+                                    );
+
+Fls_LLDReturnType Fls_IPW_SectorErase(const Fls_AddressType u32SectorOffset,
+                                      const Fls_LengthType u32PhysicalSectorSize,
+                                      const boolean bAsynch
+                                     );
+
+Fls_LLDReturnType Fls_IPW_SectorWrite(const Fls_AddressType u32SectorOffset,
+                                      const Fls_AddressType u32Length,
+                                      const uint8 * pJobDataSrcPtr,
+                                      const boolean bAsynch
+                                     );
+
+#if ( STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED )
+#if ( (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) )
+Fls_CompHandlerReturnType Fls_IPW_DsiHandler(const Fls_ExceptionDetailsType  *pExceptionDetailsPtr);
+#endif /* (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) */
+
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+void Fls_IPW_ReadEachBlock(void);
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+#endif /* STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED */
+
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+Fls_BlockNumberOfSectorType Fls_IPW_GetBlockNumberFromAddress(Fls_AddressType targetAddress);
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FLS_IPW_H */

RTD/include/Fls_Types.h

@@ -0,0 +1,482 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef FLS_TYPES_H
+#define FLS_TYPES_H
+
+/**
+*   @file Fls_Types.h
+*
+*   @addtogroup FLS FLS Driver
+*   @{
+*/
+
+/* implements Fls_Types.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "StandardTypes.h"
+#include "MemIf_Types.h"
+
+
+#include "Ftfc_Fls_Ip_Types.h"
+
+
+
+#include "Qspi_Ip_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_TYPES_VENDOR_ID                    43
+#define FLS_TYPES_AR_RELEASE_MAJOR_VERSION     4
+#define FLS_TYPES_AR_RELEASE_MINOR_VERSION     4
+#define FLS_TYPES_AR_RELEASE_REVISION_VERSION  0
+#define FLS_TYPES_SW_MAJOR_VERSION             1
+#define FLS_TYPES_SW_MINOR_VERSION             0
+#define FLS_TYPES_SW_PATCH_VERSION             0
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and StandardTypes.h file are of the same version */
+    #if ((FLS_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)\
+        )
+        #error "AutoSar Version Numbers of Fls_Types.h and StandardTypes.h are different"
+    #endif
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and MemIf_Types.h file are of the same version */
+    #if ((FLS_TYPES_AR_RELEASE_MAJOR_VERSION != MEMIF_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_TYPES_AR_RELEASE_MINOR_VERSION != MEMIF_AR_RELEASE_MINOR_VERSION)\
+        )
+        #error "AutoSar Version Numbers of Fls_Types.h and MemIf_Types.h are different"
+    #endif
+#endif
+
+/* Check if current file and Ftfc_Fls_Ip_Types.h header file are of the same vendor */
+#if (FLS_TYPES_VENDOR_ID != FTFC_FLS_IP_TYPES_VENDOR_ID)
+    #error "Fls_Types.h and Ftfc_Fls_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types.h header file are of the same Autosar version */
+#if ((FLS_TYPES_AR_RELEASE_MAJOR_VERSION    != FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_TYPES_AR_RELEASE_MINOR_VERSION    != FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_TYPES_AR_RELEASE_REVISION_VERSION != FTFC_FLS_IP_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Fls_Types.h and Ftfc_Fls_Ip_Types.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types.h header file are of the same software version */
+#if ((FLS_TYPES_SW_MAJOR_VERSION != FTFC_FLS_IP_TYPES_SW_MAJOR_VERSION) || \
+     (FLS_TYPES_SW_MINOR_VERSION != FTFC_FLS_IP_TYPES_SW_MINOR_VERSION) || \
+     (FLS_TYPES_SW_PATCH_VERSION != FTFC_FLS_IP_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_Types.h and Ftfc_Fls_Ip_Types.h are different"
+#endif
+
+
+/* Check if current file and Qspi_Ip_Types.h header file are of the same vendor */
+#if (FLS_TYPES_VENDOR_ID != FLS_QSPI_TYPES_VENDOR_ID)
+    #error "Fls_Types.h and Qspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Types.h header file are of the same Autosar version */
+#if ((FLS_TYPES_AR_RELEASE_MAJOR_VERSION    != FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_TYPES_AR_RELEASE_MINOR_VERSION    != FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_TYPES_AR_RELEASE_REVISION_VERSION != FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Fls_Types.h and Qspi_Ip_Types.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Types.h header file are of the same software version */
+#if ((FLS_TYPES_SW_MAJOR_VERSION != FLS_QSPI_TYPES_SW_MAJOR_VERSION) || \
+     (FLS_TYPES_SW_MINOR_VERSION != FLS_QSPI_TYPES_SW_MINOR_VERSION) || \
+     (FLS_TYPES_SW_PATCH_VERSION != FLS_QSPI_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_Types.h and Qspi_Ip_Types.h are different"
+#endif
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/**
+    @brief Flash sector channel type.
+*/
+typedef enum
+{
+    FLS_CH_INTERN = 0,
+    FLS_CH_QSPI = 1
+} Fls_HwChType;
+
+/**
+* @brief          Type of job currently executed by Fls_MainFunction.
+*/
+typedef enum
+{
+    /**
+    * @brief erase one or more complete flash sectors
+    */
+    FLS_JOB_ERASE = 0,
+    /**
+    * @brief write one or more complete flash pages
+    */
+    FLS_JOB_WRITE,
+    /**
+    * @brief read one or more bytes from flash memory
+    */
+    FLS_JOB_READ,
+    /**
+    * @brief compare data buffer with content of flash memory
+    */
+    FLS_JOB_COMPARE,
+    /**
+    * @brief check content of erased flash memory area
+    */
+    FLS_JOB_BLANK_CHECK
+} Fls_JobType;
+
+/**
+* @brief          Result of low-level flash operation.
+*/
+typedef enum
+{
+    FLASH_E_OK = 0,                 /**< @brief operation succeeded */
+    FLASH_E_FAILED,                 /**< @brief operation failed due to hardware error */
+    FLASH_E_BLOCK_INCONSISTENT,     /**< @brief data buffer doesn't match with content of flash memory */
+    FLASH_E_PENDING,                /**< @brief operation is pending */
+    FLASH_E_PARTITION_ERR           /**< @brief FlexNVM partition ratio error */
+} Fls_LLDReturnType;
+
+/**
+* @brief          Type of job currently executed by Fls_LLDMainFunction.
+*/
+typedef enum
+{
+    /**
+    * @brief no job executed by Fls_LLDMainFunction
+    */
+    FLASH_JOB_NONE = 0,
+    /**
+    * @brief erase one flash sector
+    */
+    FLASH_JOB_ERASE,
+    /**
+    * @brief complete erase and start an interleaved erase flash sector
+    */
+    FLASH_JOB_ERASE_TEMP,
+    /**
+    * @brief write one or more complete flash pages
+    */
+    FLASH_JOB_WRITE,
+    /**
+    * @brief erase blank check of flash sector
+    */
+    FLASH_JOB_ERASE_BLANK_CHECK
+
+} Fls_LLDJobType;
+
+/**
+* @brief          Size of data to be processeed by CRC.
+*
+* @implements     Fls_CrcDataSizeType_enumeration
+*/
+typedef enum
+{
+    /**
+    * @brief crc 8 bits
+    */
+    FLS_CRC_8_BITS = 0,
+    /**
+    * @brief crc 16 bits
+    */
+    FLS_CRC_16_BITS
+} Fls_CrcDataSizeType;
+
+
+/**
+* @brief          Logical sector index.
+*/
+typedef uint32 Fls_SectorIndexType;
+
+/**
+* @brief          Fls CRC Type.
+* @details        CRC computed over config set.
+* @implements     Fls_CrcType_typedef
+*/
+typedef uint16 Fls_CrcType;
+
+/**
+* @brief          Fls Address Type.
+* @details        Address offset from the configured flash base address to access a certain flash
+*                 memory area.
+* @implements     Fls_AddressType_typedef */
+typedef uint32 Fls_AddressType;
+
+/**
+* @brief          Fls Length Type.
+* @details        Number of bytes to read,write,erase,compare
+* @implements     Fls_LengthType_typedef */
+typedef uint32 Fls_LengthType;
+
+/**
+* @brief          Fls Sector Count Type
+* @details        Number of configured sectors
+*/
+typedef uint32 Fls_SectorCountType;
+
+/**
+* @brief          Fls BLock Count Type
+* @details        Block number of sectors type
+*/
+typedef uint8 Fls_BlockNumberOfSectorType;
+
+/**
+* @brief          Fls Internal Flash Type
+* @details        Configuration structure of internal flash.
+*/
+typedef Ftfc_ConfigType Fls_InternalConfigType;
+
+
+/**
+* @brief          Fls Job End Notification Pointer Type
+* @details        Pointer type of Fls_JobEndNotification function
+* @implements     Fls_JobEndNotificationPtrType_typedef */
+typedef void (*Fls_JobEndNotificationPtrType)(void);
+
+/**
+* @brief          Fls Job Error Notification Pointer Type
+* @details        Pointer type of Fls_JobErrorNotification function
+* @implements     Fls_JobErrorNotificationPtrType_typedef */
+typedef void (*Fls_JobErrorNotificationPtrType)(void);
+
+
+/**
+ * @brief Pointer type of Fls_AC_Callback function
+*/
+typedef void (*Fls_ACCallbackPtrType)  ( void );
+/**
+    @brief Define pointer type of erase access code function
+*/
+typedef void (*Fls_AcErasePtrType)  ( void (*CallBack)( void ));
+
+/**
+    @brief Define pointer type of write access code function
+*/
+typedef void (*Fls_AcWritePtrType)  ( void (*CallBack)( void ));
+
+/**
+ * @brief Pointer type of Fls_ReadFunctionPtrType function
+ *
+ * @details      The callout for the user to check for ECC errors for Internal Flash memories.
+ *               In this callout, the user can schedule a task that reads from flash memory
+ *               to a read source buffer and check/handle for an ECC exception.
+ *
+ *
+*/
+typedef void (*Fls_ReadFunctionPtrType) (void);
+
+/**
+    @brief FLASH physical sector description
+*/
+typedef struct
+{
+    uint32 pSectorStartAddressPtr;                          /**< @brief FLASH physical sector start address */
+    Fls_BlockNumberOfSectorType blockNumberOfSector;        /**< @brief block number of sector */
+    boolean bEccTriggersExc;               /**< @brief Triggers reading ECC data exception? */
+    uint32 u32SectorId;                    /**< @brief Corresponding number in sector location to calc cfgCRC */
+} Fls_Flash_InternalSectorInfoType;
+
+
+
+/**
+* @brief          Fls Qspi CfgConfig Type
+* @details        Fls Qspi CfgConfig Type
+* @implements     Fls_QspiCfgConfigType_typedef */
+typedef struct
+{
+    /**
+    * @brief External flash unit assigned to each sector. Size: u32SectorCount
+    */
+    const uint8 (*u8SectFlashUnit)[];
+    /**
+    * @brief Number of serial flash instances.
+    */
+    const uint8 u8FlashUnitsCount;
+    /**
+    * @brief Connection for each external memory device to available controllers. Size: u8FlashUnitsCount
+    */
+    const Qspi_Ip_MemoryConnectionType (*paFlashConnectionCfg)[];
+    /**
+    * @brief Configuration index used for each flash unit. Size: u8FlashUnitsCount
+    */
+    const uint8 (*u8FlashConfig)[];
+    /**
+    * @brief AHB direct reads configurations. Size: u8FlashUnitsCount
+    */
+    const boolean (*paAHBReadCfg)[];
+
+    /**
+    * @brief Number of serial flash configurations.
+    */
+    const uint8 u8FlashConfigCount;
+    /**
+    * @brief External memory devices configurations. Size: u8FlashConfigCount
+    */
+    const Qspi_Ip_MemoryConfigType (*paFlashCfg)[];
+
+    /**
+    * @brief Number of QSPI hardware instances.
+    */
+    const uint8 u8QspiUnitsCount;
+    /**
+    * @brief Configuration for each QSPI unit. Size: u8QspiUnitsCount ]
+    */
+    const uint8 (*u8QspiConfig)[];
+    /**
+    * @brief Number of QSPI configurations.
+    */
+    const uint8 u8QspiConfigCount;
+    /**
+    * @brief QSPI configurations. Size: u8QspiConfigCount
+    */
+    const Qspi_Ip_ControllerConfigType (*paQspiUnitCfg)[];
+}Fls_QspiCfgConfigType;
+/**
+* @brief          Fls Config Type
+* @details        Fls module initialization data structure
+* @implements     Fls_ConfigType_typedef */
+typedef struct
+{
+    /**
+    * @brief pointer to erase access code function in RAM or ROM
+    */
+    Fls_AcErasePtrType acErasePtr;
+    /**
+    * @brief pointer to write access code function in RAM or ROM
+    */
+    Fls_AcWritePtrType acWritePtr;
+    /**
+    * @brief pointer to ac callback function
+    */
+    Fls_ACCallbackPtrType acCallBackPtr;
+    /**
+    * @brief pointer to job end notification function
+    */
+    Fls_JobEndNotificationPtrType jobEndNotificationPtr;
+    /**
+    * @brief pointer to job error notification function
+    */
+    Fls_JobErrorNotificationPtrType jobErrorNotificationPtr;
+    /**
+    * @brief pointer to read to flash memory callout
+    */
+    Fls_ReadFunctionPtrType FlsReadFunctionCallout;
+    /**
+    * @brief default FLS device mode after initialization (MEMIF_MODE_FAST, MEMIF_MODE_SLOW)
+    */
+    MemIf_ModeType eDefaultMode;
+    /**
+    * @brief max number of bytes to read in one cycle of Fls_MainFunction (fast mode)
+    */
+    Fls_LengthType u32MaxReadFastMode;
+    /**
+    * @brief max number of bytes to read in one cycle of  Fls_MainFunction (normal mode)
+    */
+    Fls_LengthType u32MaxReadNormalMode;
+    /**
+    * @brief max number of bytes to write in one cycle of Fls_MainFunction (fast mode)
+    */
+    Fls_LengthType u32MaxWriteFastMode;
+    /**
+    * @brief max number of bytes to write in one cycle of  Fls_MainFunction (normal mode)
+    */
+    Fls_LengthType u32MaxWriteNormalMode;
+    /**
+    * @brief number of configured logical sectors
+    */
+    Fls_SectorCountType u32SectorCount;
+    /**
+    * @brief pointer to array containing last logical address of each configured sector
+    */
+    const Fls_AddressType (*paSectorEndAddr)[];
+    /**
+    * @brief pointer to array containing sector size of each configured sector
+    */
+    const Fls_LengthType (*paSectorSize)[];
+    /**
+    * @brief pointer to array containing physical sector ID of each configured sector
+    */
+    const Fls_Flash_InternalSectorInfoType * const (*pSectorList)[];
+    /**
+    * @brief pointer to array containing flags set of each configured sector
+    */
+    const uint8 (*paSectorFlags)[];
+    /**
+    * @brief pointer to array containing page size information of each configured sector
+    */
+    const Fls_LengthType (*paSectorPageSize)[];
+    /**
+    * @brief Pointer to array containing the hardware channel(internal, external_qspi, external_emmc) of each configured sector.
+    */
+    const Fls_HwChType (*paHwCh)[];
+    /**
+    * @brief Pointer to array containing the configured hardware start address of each external sector.
+    */
+    const uint32 (*paSectorHwAddress)[];
+
+    /** @brief  Pointer to configuration structure of QSPI. */
+    const Fls_QspiCfgConfigType *  pFlsQspiCfgConfig;
+    /**
+    * @brief Pointer to configuration structure internal flash.
+    */
+    const Fls_InternalConfigType * pFlsInternalCfgConfig;
+    /**
+     * @brief FLS Config Set CRC checksum
+     */
+    Fls_CrcType u16ConfigCrc;
+
+} Fls_ConfigType;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+
+#endif /* FLS_TYPES_H */

RTD/include/Ftfc_Fls_Ip.h

@@ -0,0 +1,326 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Ftfc_Fls_Ip.h
+*
+*   @addtogroup FTFC_FLS_IP FTFC IP Driver
+*   @{
+*/
+/*================================================================================================*/
+
+#ifndef FLS_FLASH_H
+#define FLS_FLASH_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Ftfc_Fls_Ip_Types.h"
+#include "Ftfc_Fls_Ip_Cfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_VENDOR_ID_H                       43
+#define FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H        4
+#define FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H        4
+#define FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H     0
+#define FTFC_FLS_IP_SW_MAJOR_VERSION_H                1
+#define FTFC_FLS_IP_SW_MINOR_VERSION_H                0
+#define FTFC_FLS_IP_SW_PATCH_VERSION_H                0
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same vendor */
+#if (FTFC_FLS_IP_TYPES_VENDOR_ID != FTFC_FLS_IP_VENDOR_ID_H)
+    #error "Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_TYPES_AR_RELEASE_REVISION_VERSION != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Types.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Software version */
+#if ((FTFC_FLS_IP_TYPES_SW_MAJOR_VERSION != FTFC_FLS_IP_SW_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_TYPES_SW_MINOR_VERSION != FTFC_FLS_IP_SW_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_TYPES_SW_PATCH_VERSION != FTFC_FLS_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Types.h are different"
+#endif
+
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same vendor */
+#if (FTFC_FLS_IP_VENDOR_ID_CFG != FTFC_FLS_IP_VENDOR_ID_H)
+    #error "Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same Software version */
+#if ((FTFC_FLS_IP_SW_MAJOR_VERSION_CFG != FTFC_FLS_IP_SW_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_SW_MINOR_VERSION_CFG != FTFC_FLS_IP_SW_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_SW_PATCH_VERSION_CFG != FTFC_FLS_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip.h and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+
+
+/*==================================================================================================
+                                       GLOBAL VARIABLES
+==================================================================================================*/
+#define FLS_START_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+extern uint32 Ftfc_Fls_Ip_u32ElapsedTicks;
+extern uint32 Ftfc_Fls_Ip_u32TimeoutTicks;
+extern uint32 Ftfc_Fls_Ip_u32CurrentTicks;
+#endif
+
+#define FLS_STOP_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* Base address for Flash Memory Module */
+extern FTFx_HARDWARE_TYPE * const FTFx_BaseAddress;
+
+#define FLS_STOP_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+*                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+/**
+ * @brief        Initializes the FTCF module
+ *
+ * @details      This function will initialize ftfc module and clear all error flags.
+ *
+ * @param[in]    Ftfc_Fls_Ip_pInitConfig   Pointer to the driver configuration structure.
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS            Initialization is success
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT      Errors Timeout because wait for the Done bit long time
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Init(const Ftfc_ConfigType * Ftfc_Fls_Ip_pInitConfig);
+
+/*!
+ * @brief        Abort a program or erase operation
+ *
+ * @details      This function will abort a program or erase operation in user
+ *               mode and clear all PGM, APGM, ERS, AERS, EHV, AEHV bits in MCR,AMCRS registers
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS : The operation is successful.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT: the operation error because wait for the Done bit long time
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Abort(void);
+
+/**
+ * @brief        This function fills data to pDestAddressPtr
+ *
+ * @details      This function fills data to pDestAddressPtr with data from the specified address
+ *
+ * @param[in]    u32SrcAddress       The start address of the area to be read.
+ * @param[in]    pDestAddressPtr     Pointer to the destination of the read.
+ * @param[in]    u32Length           Read size
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS             Read performed successfully.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM   Input parameters are invalid.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR               There was an error while reading.
+ *
+ * @pre          The module has to be initialized and not busy.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Read(Ftfc_Fls_Ip_AddressType u32SrcAddress,
+                                        uint8 *pDestAddressPtr,
+                                        Ftfc_Fls_Ip_LengthType u32Length
+                                       );
+/**
+ * @brief        Checks that there is the desired data at the specified address
+ *
+ * @details      Checks that there is the desired data at the specified address.
+ *               If the compare is intented to be a blank check, the pSourceAddressPtr should be NULL.
+ *
+ * @param[in]    u32SrcAddress        The start address of the area to be checked.
+ * @param[in]    pCompareAddressPtr   Pointer to the data expected to be read.
+ * @param[in]    u32Length            Check size
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS               Read performed successfully.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM     Input parameters are invalid.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR                 There was an error while reading.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY  The expected data was not found completely at the specified address
+ *
+ * @pre          The module has to be initialized and not busy.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Compare(Ftfc_Fls_Ip_AddressType u32SrcAddress,
+                                           const uint8 * pCompareAddressPtr,
+                                           Ftfc_Fls_Ip_LengthType u32Length
+                                          );
+
+/**
+ * @brief         Get block number from target address
+ *
+ * @details       Get block number from target address
+ *
+ * @param[in]    u32TargetAddress   target address
+ *
+ * @return       Ftfc_Fls_Ip_GetBlockNumberFromAddress
+ * @retval       The block number which contains the target address.
+ *
+ */
+Ftfc_Fls_Ip_FlashBlocksNumberType Ftfc_Fls_Ip_GetBlockNumberFromAddress(uint32 u32TargetAddress);
+
+/**
+ * @brief         Accepts and erases a selected program flash or data flash sector if possible
+ *
+ * @details       Accepts an erase job over one of the sectors if possible.
+ *                Starts the high voltage erase and then exits. The status of the hardware erase must
+ *                be verified by calling asynchronously the Ftfc_Fls_Ip_SectorEraseStatus function.
+ *                 The Ftfc_Fls_Ip_SectorErase function shall cover all the available sectors.
+ *
+ * @param[in]    u32SectorStartAddress   The start address of the sector to be erased.
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS             Hardware erase started successfully
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM   The selected sector is out of bound
+ * @retval       STATUS_FTFC_FLS_IP_ERROR               There is another job configured or in progress or
+ *                                                 @p The sector is locked by another core or couldn't be unlocked.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT       The erase operation exceeded the timeout - Status value available only if the timeout feature is enabled
+ *
+ * @pre          The module has to be initialized.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorErase(uint32 u32SectorStartAddress);
+
+/**
+ * @brief         Checks the status of the hardware erase started by the Ftfc_Fls_Ip_SectorErase function.
+ *
+ * @details       Checks the status of the hardware erase started by the Ftfc_Fls_Ip_SectorErase function.
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS             Erase performed successfully
+ * @retval       STATUS_Ftfc_Fls_Ip_BUSY                Hardware erase is still in progress
+ * @retval       STATUS_FTFC_FLS_IP_ERROR               There was an error during the hardware erase.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT       The erase operation exceeded the timeout - Status value available only if the timeout feature is enabled.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK   The sector was not erased correctly - Status value available only if the blank check feature is enabled
+ *
+ * @pre          The module has to be initialized.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorEraseStatus(void);
+
+/**
+ * @brief         Writes data into the memory array using the main interface. Initiates the hardware write and then exits.
+ *
+ * @details       Writes data into the memory array using the main interface. Initiates the hardware write and then exits.
+ *                the status of the hardware erase must be verified by calling asynchronously the Ftfc_Fls_Ip_WriteStatus function.
+ *
+ * @param[in]    u32DestAddress      The start address of the write, must be aligned with 8 bytes.
+ * @param[in]    pSourceAddressPtr   Source program buffer address.
+ * @param[in]    u32Length           Size in bytes of the flash region to be programed, must be aligned with 8 bytes and the maximum value is 128 bytes.
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS             Program performed successfully
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM   The input parameters are invaid.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR               There is another job configured or in progress or
+ *                                                 @p The sector is locked by another core or couldn't be unlocked.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT       The erase operation exceeded the timeout - Status value available only if the timeout feature is enabled
+ *
+ * @pre          The module has to be initialized.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Write(uint32 u32DestAddress,
+                                         const uint8 *pSourceAddressPtr,
+                                         uint32 u32Length
+                                        );
+
+/**
+ * @brief         Checks the status of the hardware program started by the FTFC_Ip_Write function.
+ *
+ * @details       Checks the status of the hardware program started by the FTFC_Ip_Write function.
+ *
+ * @return       Ftfc_Fls_Ip_StatusType
+ * @retval       STATUS_FTFC_FLS_IP_SUCCESS                Program performed successfully
+ * @retval       STATUS_Ftfc_Fls_Ip_BUSY                   Hardware program is still in progress
+ * @retval       STATUS_FTFC_FLS_IP_ERROR                  There was an error during the hardware program.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_TIMEOUT          The program operation exceeded the timeout - Status value available only if the timeout feature is enabled.
+ * @retval       STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY   The data was not written corectly into the memory - Status available only of program verify feature is enabled
+ *
+ * @pre          The module has to be initialized.
+ *
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WriteStatus(void);
+
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+    #if ( FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON )
+    Fls_CompHandlerReturnType Ftfc_Fls_Ip_DsiHandler(const Fls_ExceptionDetailsType  *pExceptionDetailsPtr);
+    #else
+    Fls_CompHandlerReturnType Ftfc_Fls_Ip_DsiHandler(void);
+    #endif
+#endif /* ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) ) */
+
+
+void Ftfc_Fls_Ip_SetAsyncMode(const boolean Async);
+
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FTFC_FLS_IP_H */

RTD/include/Ftfc_Fls_Ip_Ac.h

@@ -0,0 +1,80 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FTFC_FLS_IP_AC_H
+#define FTFC_FLS_IP_AC_H
+
+/**
+*   @file Ftfc_Fls_Ip_Ac.h
+*
+*   @addtogroup FTFC_FLS_IP FTFC IP Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_AC_VENDOR_ID_H                      43
+#define FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_H       4
+#define FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_H       4
+#define FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_H    0
+#define FTFC_FLS_IP_AC_SW_MAJOR_VERSION_H               1
+#define FTFC_FLS_IP_AC_SW_MINOR_VERSION_H               0
+#define FTFC_FLS_IP_AC_SW_PATCH_VERSION_H               0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+#define FLS_START_SEC_CODE_AC
+#include "Fls_MemMap.h"
+
+#ifdef _LINARO_C_S32K1XX_
+    void Ftfc_Fls_Ip_AccessCode(void (*CallBack)( void ) ) __attribute__ ((section (".acfls_code_rom")));
+#else
+    void Ftfc_Fls_Ip_AccessCode(void (*CallBack)( void ) );
+#endif
+
+#define FLS_STOP_SEC_CODE_AC
+#include "Fls_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FTFC_FLS_IP_AC_H */

RTD/include/Ftfc_Fls_Ip_Types.h

@@ -0,0 +1,204 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FTFC_FLS_IP_TYPES_H
+#define FTFC_FLS_IP_TYPES_H
+
+/**
+*   @file Ftfc_Fls_Ip_Types.h
+*
+*   @addtogroup FTFC_FLS_IP FTFC IP Driver
+*   @{
+*/
+
+/* implements Ftfc_Fls_Ip_Types.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "StandardTypes.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_TYPES_VENDOR_ID                    43
+#define FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION     4
+#define FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION     4
+#define FTFC_FLS_IP_TYPES_AR_RELEASE_REVISION_VERSION  0
+#define FTFC_FLS_IP_TYPES_SW_MAJOR_VERSION             1
+#define FTFC_FLS_IP_TYPES_SW_MINOR_VERSION             0
+#define FTFC_FLS_IP_TYPES_SW_PATCH_VERSION             0
+
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and StandardTypes.h file are of the same version */
+    #if ((FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION)\
+        )
+        #error "AutoSar Version Numbers of Ftfc_Fls_Ip_Types.h and StandardTypes.h are different"
+    #endif
+#endif
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/**
+ * @brief FCCOB commands IDs
+ */
+#define FLASH_CMD_PROGRAM_PHRASE                (0x07U)
+#define FLASH_CMD_ERASE_SECTOR                  (0x09U)
+
+/**
+ * @brief  Program allignment
+ */
+#define FTFC_WRITE_DOUBLE_WORD     8U
+
+/**
+* @brief the number of bytes uses to compare (1 byte).
+*
+*/
+#define FLS_SIZE_1BYTE      1U
+
+/**
+* @brief the number of bytes uses to compare (2 bytes).
+*
+*/
+#define FLS_SIZE_2BYTE      2U
+
+/**
+* @brief the number of bytes uses to compare (4 bytes).
+*
+*/
+#define FLS_SIZE_4BYTE      4U
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/**
+* @brief          Return value of Fls handler function.
+* @details        Fls_DsiHandler and Fls_MciHandler can return the following value:
+*                 - FLS_UNHANDLED    Fls driver is not responsable for this situation
+*                 - FLS_HANDLED_SKIP Fls driver is responsable for this exception and want to skip this job
+*                 .
+*/
+typedef uint8 Fls_CompHandlerReturnType;
+
+typedef const uint8 * Fls_InstructionAddressType;
+typedef const void * Fls_DataAddressType;
+typedef uint32 Ftfc_Fls_Ip_AddressType;
+typedef uint32 Ftfc_Fls_Ip_LengthType;
+
+/**
+* @brief          Detailed information on the exception.
+* @details        The following information will be checked by the driver:
+*                 - if there is a pending read, compare,
+*                 - data_pt matches address currently accessed by pending flash read or flash compare job,
+*                 - if the exception syndrome register indicates DSI or MCI reason,
+*                 .
+*
+*/
+typedef struct
+{
+    Fls_InstructionAddressType instruction_pt; /**< @brief pointer to the instruction that generated the ECC */
+    Fls_DataAddressType        data_pt;        /**< @brief data address that caused the ECC error */
+    uint32                     syndrome_u32;   /**< @brief details on the type of exception */
+} Fls_ExceptionDetailsType;
+
+
+typedef uint32 Fls_Flash_DataBusWidthType;
+
+/**
+    @brief Enumeration of Blocks of memory flash .
+*/
+typedef enum
+{
+    FLS_CODE_BLOCK_0  = 0x00U,  /*!< code block number 0 */
+    FLS_CODE_BLOCK_1  = 0x01U,  /*!< code block number 1 */
+    FLS_CODE_BLOCK_2  = 0x02U,  /*!< code block number 2 */
+    FLS_DATA_BLOCK    = 0x04U,  /*!< data block          */
+    FLS_BLOCK_INVALID = 0xFFU   /*!< invalid block       */
+} Ftfc_Fls_Ip_FlashBlocksNumberType;
+
+/**
+* @brief          Fls Start Flash Access Notification Pointer Type
+* @details        Pointer type of Ftfc_StartFlashAccessNotifPtrType function
+*
+*/
+typedef void (*Ftfc_StartFlashAccessNotifPtrType)(void);
+
+/**
+* @brief          Fls Finished Flash Access Notification Pointer Type
+* @details        Pointer type of Ftfc_FinishedFlashAccessNotifPtrType function
+*
+*/
+typedef void (*Ftfc_FinishedFlashAccessNotifPtrType)(void);
+
+/*!
+ * @brief Ftfc Configuration Structure
+ *
+ * Implements : Ftfc_ConfigType_Class
+ */
+typedef struct
+{
+    Ftfc_StartFlashAccessNotifPtrType       startFlashAccessNotifPtr;            /*!< Pointer to start flash access callout  */
+    Ftfc_FinishedFlashAccessNotifPtrType    finishedFlashAccessNotifPtr;         /*!< Pointer to finish flash access callout */
+} Ftfc_ConfigType;
+
+/**
+    @brief Enumeration of checking status errors or not.
+*/
+typedef enum
+{
+    STATUS_FTFC_FLS_IP_SUCCESS                   = 0x5AA5U,    /*!< Successful job */
+    STATUS_FTFC_FLS_IP_BUSY                      = 0xE742U,    /*!< IP is performing an operation */
+    STATUS_FTFC_FLS_IP_ERROR                     = 0x27E4U,    /*!< Error - general code */
+    STATUS_FTFC_FLS_IP_ERROR_TIMEOUT             = 0x2BD4U,    /*!< Error - exceeded timeout */
+    STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM         = 0x2DB4U,    /*!< Error - wrong input parameter */
+    STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK         = 0x2E74U,    /*!< Error - selected memory area is not erased */
+    STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY      = 0x33CCU,    /*!< Error - selected memory area doesn't contain desired value */
+    STATUS_FTFC_FLS_IP_ERROR_USER_TEST_BREAK_SBC = 0x35ACU,    /*!< Error - single bit correction */
+    STATUS_FTFC_FLS_IP_ERROR_USER_TEST_BREAK_DBD = 0x366CU,    /*!< Error - double bit detection */
+    STATUS_FTFC_FLS_IP_SECTOR_UNPROTECTED        = 0xFA22U,    /*!< Checked sector is unlocked */
+    STATUS_FTFC_FLS_IP_SECTOR_PROTECTED          = 0xE8B8U     /*!< Checked sector is locked */
+} Ftfc_Fls_Ip_StatusType;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+#endif /* FTFC_FLS_IP_TYPES_H */
+

RTD/include/Lpuart_Uart_Ip_HwAccess.h

@@ -640,6 +640,10 @@ static inline void Lpuart_Uart_Ip_ClearStatusFlag(LPUART_Type * Base, Lpuart_Uar
         case LPUART_UART_IP_PARITY_ERR:
             Base->STAT = (Base->STAT & (~LPUART_FEATURE_STAT_REG_FLAGS_MASK)) | LPUART_STAT_PF_MASK;
             break;
+
+        case LPUART_UART_IP_IDLE://Chenjie
+            Base->STAT = (Base->STAT & (~LPUART_FEATURE_STAT_REG_FLAGS_MASK)) | LPUART_STAT_IDLE_MASK;
+            break;
         default:
             /* Dummy code */
             break;

RTD/include/Os.h

@@ -0,0 +1,57 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_H
+#define OS_H
+
+/**
+*   @file Os.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#include    "Os_version.h"    /**< OS version info */
+#include    "Std_Types.h"     /**< Standard type header - from MCAL  */
+#include    "Os_types_public.h"   /**< Autosar OS public types  */
+#include    "Os_counter_api.h"
+#include    "Os_multicore.h"
+
+#include    "Os_cfg.h"    /* OS Configuration (generated by SysGen) */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_H */
+

RTD/include/Os_counter_api.h

@@ -0,0 +1,52 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_COUNTER_API_H
+#define OS_COUNTER_API_H
+
+/**
+*   @file Os_counter_api.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include "Os_counter_types.h"   /* for StatusType and counter specific types */
+
+extern StatusType GetCounterValue (CounterType ctrId, TickRefType tickRef);
+
+extern StatusType GetElapsedValue (CounterType ctrId, TickRefType valueRef, TickRefType tickRef);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_COUNTER_API_H */

RTD/include/Os_counter_types.h

@@ -0,0 +1,52 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_COUNTER_TYPES_H_
+#define OS_COUNTER_TYPES_H_
+
+/**
+*   @file Os_counter_types.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "Os_types_basic.h"     /* for OSDWORD  */
+#include "Os_types_common_public.h"     /* for OSObjectType */
+#include "Rte_Os_Type.h"     
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_COUNTER_TYPES_H_ */
+

RTD/include/Os_multicore.h

@@ -0,0 +1,75 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_MULTICORE_H
+#define OS_MULTICORE_H
+
+/**
+*   @file Os_multicore.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*
+* @page misra_violations MISRA-C:2012 violations
+*
+* @section [global]
+* Violates MISRA 2012 Advisory Rule 2.5, A project should not contain unused macro declarations.
+* This definition uses or not it is depended by configuring to select the sectors.
+*
+*/
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Os_types_basic.h"
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                   FUNCTION DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_MULTICORE_H */

RTD/include/Os_types_basic.h

@@ -0,0 +1,63 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_TYPES_BASIC_H
+#define OS_TYPES_BASIC_H
+
+/**
+*   @file Os_types_basic.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include    "Std_Types.h"        /**< Standard type header - from MCAL  */
+
+/*
+ * only the basic types
+ */
+
+typedef unsigned char OSBYTE;
+typedef unsigned char *OSBYTEPTR;
+
+typedef unsigned short OSWORD;
+typedef signed short OSSHORT;
+
+typedef unsigned short *OSWORDPTR;
+typedef unsigned int OSDWORD;
+
+typedef OSWORD CoreIdType;
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_TYPES_BASIC_H */

RTD/include/Os_types_common_public.h

@@ -0,0 +1,77 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_TYPES_COMMON_PUBLIC_H_
+#define OS_TYPES_COMMON_PUBLIC_H_
+
+/**
+*   @file Os_types_common_public.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "Os_types_basic.h"
+
+#define OSFALSE         (0U)
+#define OSTRUE          (1U)
+
+/*
+ *  types required by the Autosar API
+ */
+
+typedef OSBYTE OSAPPLICATIONTYPE;
+typedef OSBYTE OSAPPLICATIONMASKTYPE;
+
+/* avoid collision with MCAL */
+#ifndef STATUSTYPEDEFINED
+/* prescribed by OSEK/VDX */
+#define STATUSTYPEDEFINED       /* required by OSEK/VDX Binding Specification */
+
+#define E_OK                      ( (StatusType) 0 )   /* No error, successful completion  */
+typedef unsigned char StatusType;       /* OSEK: Status type             */
+
+#endif /* !defined(STATUSTYPEDEFINED) */
+
+
+typedef OSWORD OSObjectType;            /* bits [15] - Core Id, bits [14..11] - ObjType, bits [10..0] - ObjId, */
+
+typedef OSObjectType TaskType;          /* used in task, events api ... */
+
+typedef OSDWORD TickType;               /* Type for timers ticks - use by counter, alarm, schedule table alarm */
+typedef TickType  *TickRefType;         /* OSEK: Reference to counter value - use by counter and alarm */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_TYPES_COMMON_PUBLIC_H_ */

RTD/include/Os_types_public.h

@@ -0,0 +1,51 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_TYPES_PUBLIC_H_
+#define OS_TYPES_PUBLIC_H_
+
+/**
+*   @file Os_types_public.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include    "Os_types_common_public.h"
+
+#include    "Os_counter_types.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_TYPES_PUBLIC_H_ */

RTD/include/Os_version.h

@@ -0,0 +1,59 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef OS_VERSION_H
+#define OS_VERSION_H
+
+/**
+*   @file Os_version.h
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define OS_VENDOR_ID                    43    /* Freescale AUTOSAR Vendor ID  */
+#define OS_MODULE_ID                    0x01   /* OS Module ID                 */
+
+#define OS_AR_RELEASE_MAJOR_VERSION     4   /* Major version number of AUTOSAR specification       */
+#define OS_AR_RELEASE_MINOR_VERSION     4   /* Minor version number of AUTOSAR specification       */
+#define OS_AR_RELEASE_REVISION_VERSION  0   /* Patch level version number of AUTOSAR specification */
+
+#define OS_SW_MAJOR_VERSION             1   /* Major version number of the implementation   */
+#define OS_SW_MINOR_VERSION             0   /* Minor version number of the implementation   */
+#define OS_SW_PATCH_VERSION             0    /* Patch level version number of the implementation */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* OS_VERSION_H */

RTD/include/Qspi_Ip.h

@@ -0,0 +1,466 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QSPI_IP_H
+#define QSPI_IP_H
+
+/**
+*   @file Qspi_Ip.h
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "StandardTypes.h"
+#include "Qspi_Ip_Types.h"
+#include "Qspi_Ip_Features.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_H                       43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_H        4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_H        4
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_H     0
+#define QSPI_IP_SW_MAJOR_VERSION_H                1
+#define QSPI_IP_SW_MINOR_VERSION_H                0
+#define QSPI_IP_SW_PATCH_VERSION_H                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Qspi_Ip header file and StandardTypes.h header file are of the same Autosar version */
+    #if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_H != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (QSPI_IP_AR_RELEASE_MINOR_VERSION_H != STD_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "Autosar Version Numbers of Qspi_Ip.h and StandardTypes.h are different"
+    #endif
+#endif
+
+/* Check if current file and Qspi_Ip_Types header file are of the same vendor */
+#if (FLS_QSPI_TYPES_VENDOR_ID != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip.h and Qspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Autosar version */
+#if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.h and Qspi_Ip_Types.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Software version */
+#if ((FLS_QSPI_TYPES_SW_MAJOR_VERSION != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (FLS_QSPI_TYPES_SW_MINOR_VERSION != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (FLS_QSPI_TYPES_SW_PATCH_VERSION != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.h and Qspi_Ip_Types.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (QSPI_IP_FEATURES_VENDOR_ID_CFG != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip.h and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.h and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.h and Qspi_Ip_Features.h are different"
+#endif
+/*******************************************************************************
+ * Definitions.
+ ******************************************************************************/
+
+/*! Maximum number of bytes then can be read in one operation */
+#define     QSPI_IP_MAX_READ_SIZE       (FEATURE_QSPI_RX_BUF_SIZE)
+/*! Maximum number of bytes then can be written in one operation */
+#define     QSPI_IP_MAX_WRITE_SIZE      (FEATURE_QSPI_TX_BUF_SIZE)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+/*!
+ * @brief Initializes the serial flash memory driver
+ *
+ * This function initializes the external flash driver and prepares it for operation.
+ *
+ * @param instance     External flash instance number
+ * @param pConfig      Pointer to the driver configuration structure.
+ * @param pConnect     Pointer to the flash device connection structure.
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Init(uint32 instance,
+                                const Qspi_Ip_MemoryConfigType * pConfig,
+                                const Qspi_Ip_MemoryConnectionType * pConnect
+                               );
+
+
+/*!
+ * @brief De-initializes the serial flash memory driver
+ *
+ * This function de-initializes the qspi driver. The driver can't be used
+ * again until reinitialized. The state structure is no longer needed by the driver and
+ * may be freed after calling this function.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Deinit(uint32 instance);
+
+
+/*!
+ * @brief Erase a sector in the serial flash.
+ *
+ * This function performs one erase sector (block) operation on the external flash. The erase size must match one of
+ * the device's erase types.
+ *
+ * @param instance     External flash instance number
+ * @param address      Address of sector to be erased
+ * @param size         Size of the sector to be erase. The sector size must match one of the supported erase sizes of the device.
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_EraseBlock(uint32 instance,
+                                      uint32 address,
+                                      uint32 size
+                                     );
+
+/*!
+ * @brief Erase the entire serial flash
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_EraseChip(uint32 instance);
+
+/*!
+ * @brief Check the status of the flash device
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_GetMemoryStatus(uint32 instance);
+
+
+/*!
+ * @brief Sets the protection bits to the requested value.
+ *
+ * @param instance     External flash instance number
+ * @param value        New value for the protection bits
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_SetProtection(uint32 instance,
+                                         uint8 value
+                                        );
+
+
+/*!
+ * @brief Returns the current value of the protection bits
+ *
+ * @param instance     External flash instance number
+ * @param value        Current value of the protection bits
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_GetProtection(uint32 instance,
+                                         uint8 *value
+                                        );
+
+
+/*!
+ * @brief Resets the flash device
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Reset(uint32 instance);
+
+
+/*!
+ * @brief Enters 0-X-X (no command) mode. This mode assumes only reads are performed.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Enter0XX(uint32 instance);
+
+
+/*!
+ * @brief Exits 0-X-X (no command) mode. This allows operations other than reads to be performed.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Exit0XX(uint32 instance);
+
+
+/*!
+ * @brief Suspends a program operation.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ProgramSuspend(uint32 instance);
+
+
+/*!
+ * @brief Resumes a program operation.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ProgramResume(uint32 instance);
+
+
+/*!
+ * @brief Suspends an erase operation.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_EraseSuspend(uint32 instance);
+
+
+/*!
+ * @brief Resumes an erase operation.
+ *
+ * @param instance     External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_EraseResume(uint32 instance);
+
+
+/*!
+ * @brief Read data from serial flash
+ *
+ * @param instance     External flash instance number
+ * @param address      Start address for read operation
+ * @param data         Buffer where to store read data
+ * @param size         Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Read(uint32 instance,
+                                uint32 address,
+                                uint8 * data,
+                                uint32 size
+                               );
+
+
+/*!
+ * @brief Read manufacturer ID/device ID from serial flash
+ *
+ * @param instance     External flash instance number
+ * @param data         Buffer where to store read data. Buffer size must match ReadId initialization settings.
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ReadId(uint32 instance,
+                                  uint8 * data
+                                 );
+
+
+/*!
+ * @brief Verifies the correctness of the programmed data
+ *
+ * @param instance     External flash instance number
+ * @param address      Start address of area to be verified
+ * @param data         Data to be verified
+ * @param size         Size of area to be verified
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ProgramVerify(uint32 instance,
+                                         uint32 address,
+                                         const uint8 * data,
+                                         uint32 size
+                                        );
+
+
+/*!
+ * @brief Checks whether or not an area in the serial flash is erased
+ *
+ * @param instance     External flash instance number
+ * @param address      Start address of area to be verified
+ * @param size         Size of area to be verified
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_EraseVerify(uint32 instance,
+                                       uint32 address,
+                                       uint32 size
+                                      );
+
+/*!
+ * @brief Writes data in serial flash
+ *
+ * @param instance     External flash instance number
+ * @param address      Start address of area to be programmed
+ * @param data         Data to be programmed in flash
+ * @param size         Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_Program(uint32 instance,
+                                   uint32 address,
+                                   const uint8 * data,
+                                   uint32 size
+                                  );
+
+
+/*!
+ * @brief Launches a simple command for the serial flash.
+ *
+ * @param instance     External flash instance number
+ * @param lut          Index of command in virtual LUT
+ * @param addr         Address used in the command, or base address of the target serial flash
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_RunCommand(uint32 instance,
+                                      uint16 lut,
+                                      uint32 addr
+                                     );
+
+
+/*!
+ * @brief Launches a read command for the serial flash
+ *
+ * This function can launch a read command in 3 modes:
+ * - normal read (dataRead != NULL_PTR): Data is read from serial flash and placed in the buffer
+ * - verify (dataRead == NULL_PTR, dataCmp != NULL_PTR): Data is read from serial flash and compared to the reference buffer
+ * - blank check (dataRead == NULL_PTR, dataCmp == NULL_PTR): Data is read from serial flash and compared to 0xFF
+ * Only normal read mode can use DMA.
+ *
+ * @param instance       External flash instance number
+ * @param lut            Index of LUT register
+ * @param addr           Start address for read operation in serial flash
+ * @param dataRead       Buffer where to store read data
+ * @param dataCmp        Buffer to be compared to read data
+ * @param size           Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_RunReadCommand(uint32 instance,
+                                          uint16 lut,
+                                          uint32 addr,
+                                          uint8 * dataRead,
+                                          const uint8 * dataCmp,
+                                          uint32 size
+                                         );
+
+
+/*!
+ * @brief Launches a write command for the serial flash
+ *
+ * @param instance       External flash instance number
+ * @param lut            Index of LUT register
+ * @param addr           Start address for write operation in serial flash
+ * @param data           Data to be programmed in flash
+ * @param size           Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_RunWriteCommand(uint32 instance,
+                                           uint16 lut,
+                                           uint32 addr,
+                                           const uint8 * data,
+                                           uint32 size
+                                          );
+
+/*!
+ * @brief Sets up AHB reads to the serial flash
+ *
+ * @param instance   External flash instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_AhbReadEnable(uint32 instance);
+
+
+/*!
+ * @brief Check the status of the QSPI controller
+ *
+ * @param instance     QSPI peripheral instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ControllerGetStatus(uint32 instance);
+
+
+/*!
+ * @brief Initializes the qspi driver
+ *
+ * This function initializes the qspi driver and prepares it for operation.
+ *
+ * @param instance         QSPI peripheral instance number
+ * @param userConfigPtr    Pointer to the qspi configuration structure.
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ControllerInit(uint32 instance,
+                                          const Qspi_Ip_ControllerConfigType * userConfigPtr
+                                         );
+
+/*!
+ * @brief De-initialize the qspi driver
+ *
+ * This function de-initializes the qspi driver. The driver can't be used
+ * again until reinitialized. The context structure is no longer needed by the driver and
+ * can be freed after calling this function.
+ *
+ * @param instance     QSPI peripheral instance number
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ControllerDeinit(uint32 instance);
+
+/*!
+ * @brief Initializes the serial flash memory configuration from SFDP table
+ *
+ * This function uses the information in the SFDP table to auto-fill the memory configuration structure.
+ *
+ * @param pConfig      Pointer to the driver configuration structure.
+ * @param pConnect     Pointer to the flash device connection structure.
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_ReadSfdp(Qspi_Ip_MemoryConfigType * pConfig,
+                                    const Qspi_Ip_MemoryConnectionType * pConnect
+                                   );
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_H */

RTD/include/Qspi_Ip_Common.h

@@ -0,0 +1,154 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QSPI_IP_COMMON_H
+#define QSPI_IP_COMMON_H
+
+/**
+*   @file Qspi_Ip_Common.h
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_Common.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "Qspi_Ip_Features.h"
+#include "Qspi_Ip.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_COMMON_VENDOR_ID_H                       43
+#define QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H        4
+#define QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H        4
+#define QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H     0
+#define QSPI_IP_COMMON_SW_MAJOR_VERSION_H                1
+#define QSPI_IP_COMMON_SW_MINOR_VERSION_H                0
+#define QSPI_IP_COMMON_SW_PATCH_VERSION_H                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (QSPI_IP_COMMON_VENDOR_ID_H != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Qspi_Ip_Common.h and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Common.h and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((QSPI_IP_COMMON_SW_MAJOR_VERSION_H != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_COMMON_SW_MINOR_VERSION_H != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (QSPI_IP_COMMON_SW_PATCH_VERSION_H != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Common.h and Qspi_Ip_Features.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip header file are of the same vendor */
+#if (QSPI_IP_COMMON_VENDOR_ID_H != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip_Common.h and Qspi_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Autosar version */
+#if ((QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Common.h and Qspi_Ip.h are different"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Software version */
+#if ((QSPI_IP_COMMON_SW_MAJOR_VERSION_H != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_COMMON_SW_MINOR_VERSION_H != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_COMMON_SW_PATCH_VERSION_H != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Common.h and Qspi_Ip.h are different"
+#endif
+
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+/*******************************************************************************
+ * Enumerations.
+ ******************************************************************************/
+
+
+/*******************************************************************************
+ * External variable declarations.
+ ******************************************************************************/
+
+ /* Phisical LUT seq to use for all flash commands */
+#define QSPI_IP_COMMAND_LUT 0U
+ /* Phisical LUT seq to use for AHB reads */
+#define QSPI_IP_AHB_LUT 1U
+
+#define FLS_START_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* Table of AHB addresses for QuadSPI instances. */
+extern const uint32 Qspi_Ip_AhbAddress[QuadSPI_INSTANCE_COUNT];
+
+#define FLS_STOP_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+/*!
+ * @brief Driver configuration structure
+ *
+ * This structure is used to provide configuration parameters for the external flash driver
+ * at initialization time.
+ */
+typedef struct
+{
+    const Qspi_Ip_MemoryConfigType *configuration;      /*!< Serial flash device configuration                */
+    const Qspi_Ip_MemoryConnectionType *connection;     /*!< Connection to a QSPI device                      */
+    uint32 baseAddress;                                 /*!< Base address of serial flash device              */
+    uint32 lastCommand;                                 /*!< Last command sent to the flash device            */
+    uint16 activeReadLut;                               /*!< LUT number for currently active read mode        */
+} Qspi_Ip_StateType;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#endif /* QSPI_IP_MEM_INSTANCE_COUNT */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_COMMON_H */

RTD/include/Qspi_Ip_Controller.h

@@ -0,0 +1,258 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QSPI_IP_CONTROLLER_H
+#define QSPI_IP_CONTROLLER_H
+
+/**
+*   @file Qspi_Ip_Controller.h
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_Controller.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "Qspi_Ip_Features.h"
+#include "Qspi_Ip_Common.h"
+#include "Qspi_Ip.h"
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_CONTROLLER_VENDOR_ID_H                       43
+#define QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H        4
+#define QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H        4
+#define QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H     0
+#define QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H                1
+#define QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H                0
+#define QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_H != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Qspi_Ip_Controller.h and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip_Features.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Common header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_H != QSPI_IP_COMMON_VENDOR_ID_H)
+    #error "Qspi_Ip_Controller.h and Qspi_Ip_Common.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip_Common.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip_Common.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_H != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip_Controller.h and Qspi_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip.h are different"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.h and Qspi_Ip.h are different"
+#endif
+
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+/*******************************************************************************
+ * Enumerations.
+ ******************************************************************************/
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+#define FLS_START_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+extern QuadSPI_Type * const Qspi_Ip_BaseAddress[];
+
+#define FLS_STOP_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+/*!
+ * @name QuadSPI Driver
+ * @{
+ */
+
+
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+
+/*!
+ * @brief Configures LUT commands
+ *
+ * This function configures a pair of LUT commands in the specified LUT register.
+ * LUT sequences start at index multiple of 4 and can have up to 8 commands
+ *
+ * @param instance     QuadSPI peripheral instance number
+ * @param lut          Index in LUT table
+ * @param instr0       First instruction
+ * @param instr1       Second instruction
+ * Implements      Qspi_Ip_SetLut_Activity
+ */
+void Qspi_Ip_SetLut(uint32 instance,
+                    uint8 lut,
+                    Qspi_Ip_InstrOpType operation0,
+                    Qspi_Ip_InstrOpType operation1
+                   );
+
+/*!
+ * @brief Sets sequence ID for AHB operations
+ *
+ * @param instance     QuadSPI peripheral instance number
+ * @param seqID        Sequence ID in LUT for read operation
+ * Implements   Qspi_Ip_SetAhbSeqId_Activity
+ */
+void Qspi_Ip_SetAhbSeqId(uint32 instance,
+                         uint8 seqID
+                        );
+
+/*!
+ * @brief Returns the physical base address of a flash device
+ *
+ * This function returns the physical base address of a flash device, depending on the QSPI connection.
+ * The controller must be initialized prior to calling this function.
+ *
+ * @param instance        QuadSPI peripheral instance number
+ * @param connectionType  Connection of the flash device to QSPI
+ */
+uint32 Qspi_Ip_GetBaseAdress(uint32 instance,
+                             Qspi_Ip_ConnectionType connectionType
+                            );
+
+/*!
+ * @brief Launches a simple IP command
+ *
+ * @param instance     QuadSPI peripheral instance number
+ * @param lut          Index of LUT register
+ * @param addr         Address of the target serial flash
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_IpCommand(uint32 instance,
+                                     uint8 lut,
+                                     uint32 addr
+                                    );
+
+
+/*!
+ * @brief Launches an IP read command
+ *
+ * This function can launch a read command in 3 modes:
+ * - normal read (dataRead != NULL_PTR): Data is read from serial flash and placed in the buffer
+ * - verify (dataRead == NULL_PTR, dataCmp != NULL_PTR): Data is read from serial flash and compared to the reference buffer
+ * - blank check (dataRead == NULL_PTR, dataCmp == NULL_PTR): Data is read from serial flash and compared to 0xFF
+ * Only normal read mode can use DMA.
+ *
+ * @param instance       QuadSPI peripheral instance number
+ * @param lut            Index of LUT register
+ * @param addr           Start address for read operation in serial flash
+ * @param dataRead       Buffer where to store read data
+ * @param dataCmp        Buffer to be compared to read data
+ * @param size           Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_IpRead(uint32 instance,
+                                  uint8 lut,
+                                  uint32 addr,
+                                  uint8 * dataRead,
+                                  const uint8 * dataCmp,
+                                  uint32 size
+                                 );
+
+
+/*!
+ * @brief Launches an IP write command
+ *
+ * @param instance       QuadSPI peripheral instance number
+ * @param lut            Index of LUT register
+ * @param addr           Start address for write operation in serial flash
+ * @param data           Data to be programmed in flash
+ * @param size           Size of data buffer
+ * @return    Error or success status returned by API
+ */
+Qspi_Ip_StatusType Qspi_Ip_IpWrite(uint32 instance,
+                                   uint8 lut,
+                                   uint32 addr,
+                                   const uint8 * data,
+                                   uint32 size
+                                  );
+
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_CONTROLLER_H */

RTD/include/Qspi_Ip_HwAccess.h

@@ -0,0 +1,800 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QUADSPI_HW_ACCESS_H
+#define QUADSPI_HW_ACCESS_H
+
+/**
+*   @file Qspi_Ip_HwAccess.h
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_HwAccess.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+#include "Qspi_Ip.h"
+#include "Qspi_Ip_Common.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_HW_ACCESS_VENDOR_ID_H                       43
+#define QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H        4
+#define QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H        4
+#define QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H     0
+#define QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H                1
+#define QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H                0
+#define QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H                0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip header file are of the same vendor */
+#if (QSPI_IP_HW_ACCESS_VENDOR_ID_H != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip_HwAccess.h and Qspi_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Autosar version */
+#if ((QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip.h are different"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Software version */
+#if ((QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Common header file are of the same vendor */
+#if (QSPI_IP_HW_ACCESS_VENDOR_ID_H != QSPI_IP_COMMON_VENDOR_ID_H)
+    #error "Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Autosar version */
+#if ((QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H    != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H    != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Software version */
+#if ((QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h are different"
+#endif
+
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define QSPI_IP_RX_READOUT_IP   1U        /* RX Buffer content is read using the AHB Bus registers QSPI_ARDBn */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+
+/*
+ * Set all hardware registers to their reset value
+ */
+static inline void Qspi_Ip_ResetAllRegisters(QuadSPI_Type *baseAddr)
+{
+    uint8 cnt;
+
+    /* reset MCR register */
+    baseAddr->MCR     = (uint32)0x000F400CUL;
+    /* reset IPCR register */
+    baseAddr->IPCR    = (uint32)0x00000000UL;
+    /* reset FLSHCR register */
+    baseAddr->FLSHCR  = (uint32)0x00000303UL;
+    /* reset BUF0CR register */
+    baseAddr->BUF0CR  = (uint32)0x00000003UL;
+    /* reset BUF1CR register */
+    baseAddr->BUF1CR  = (uint32)0x00000002UL;
+    /* reset BUF2CR register */
+    baseAddr->BUF2CR  = (uint32)0x00000001UL;
+    /* reset BUF3CR register */
+    baseAddr->BUF3CR  = (uint32)0x80000000UL;
+    /* reset BFGENCR register */
+    baseAddr->BFGENCR = (uint32)0x00000000UL;
+    /* reset SOCCR register */
+    baseAddr->SOCCR   = (uint32)0x00000000UL;
+    /* reset BUF0IND register */
+    baseAddr->BUF0IND = (uint32)0x00000000UL;
+    /* reset BUF1IND register */
+    baseAddr->BUF1IND = (uint32)0x00000000UL;
+    /* reset BUF2IND register */
+    baseAddr->BUF2IND = (uint32)0x00000000UL;
+    /* reset SFAR register */
+    baseAddr->SFAR    = (uint32)0x00000000UL;
+    /* reset SFACR register */
+    baseAddr->SFACR   = (uint32)0x00000000UL;
+    /* reset SMPR register */
+    baseAddr->SMPR    = (uint32)0x00000000UL;
+    /* reset RBCT register */
+    baseAddr->RBCT    = (uint32)0x00000000UL;
+    /* reset TBDR register */
+    baseAddr->TBDR    = (uint32)0x00000000UL;
+    /* reset TBCT register */
+    baseAddr->TBCT    = (uint32)0x00000000UL;
+    /* reset FR register - Write 1 to clear */
+    baseAddr->FR      = (uint32)0x0C83F0C1UL;
+    /* reset RSER register */
+    baseAddr->RSER    = (uint32)0x00000000UL;
+    /* reset SPTRCLR register */
+    baseAddr->SPTRCLR = (uint32)0x00000000UL;
+    /* reset SFA1AD register */
+    baseAddr->SFA1AD  = (uint32)0x6C000000UL;
+    /* reset SFA2AD register */
+    baseAddr->SFA2AD  = (uint32)0x6C000000UL;
+    /* reset SFB1AD register */
+    baseAddr->SFB1AD  = (uint32)0x70000000UL;
+    /* reset SFB2AD register */
+    baseAddr->SFB2AD  = (uint32)0x70000000UL;
+    /* reset LUTKEY register */
+    baseAddr->LUTKEY  = (uint32)0x5AF05AF0UL;
+    /* reset LCKCR register */
+    baseAddr->LCKCR   = (uint32)0x00000002UL;
+    /* reset LUT0 register */
+    baseAddr->LUT[0]  = (uint32)0x08180403UL;
+    /* reset LUT1 register */
+    baseAddr->LUT[1]  = (uint32)0x24001C08UL;
+    for (cnt = 2U; cnt < QuadSPI_LUT_COUNT; cnt++)
+    {
+        baseAddr->LUT[cnt] = (uint32)0x00000000UL;
+    }
+}
+
+
+/*
+ * Triggers an IP transaction
+ */
+static inline void Qspi_Ip_IpTrigger(QuadSPI_Type *baseAddr,
+                                     uint8 seqID,
+                                     uint16 dataSize
+                                    )
+{
+    baseAddr->IPCR =  QuadSPI_IPCR_SEQID(seqID)
+                    | QuadSPI_IPCR_IDATSZ(dataSize);
+}
+
+
+/*
+ * Clear Rx buffer
+ */
+static inline void Qspi_Ip_ClearRxBuf(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR |= QuadSPI_MCR_CLR_RXF_MASK;
+
+}
+
+
+/*
+ * Clear Tx buffer
+ */
+static inline void Qspi_Ip_ClearTxBuf(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR |= QuadSPI_MCR_CLR_TXF_MASK;
+
+}
+
+
+/*
+ * Checks the Tx buffer clear flag
+ * Returns TRUE if the Tx buffer content is invalidated.
+ */
+static inline boolean Qspi_Ip_GetClrTxStatus(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->MCR;
+
+    regValue = (regValue & QuadSPI_MCR_CLR_TXF_MASK) >> QuadSPI_MCR_CLR_TXF_SHIFT;
+    return (0U == regValue)? TRUE : FALSE;
+}
+
+
+#ifdef QuadSPI_SPTRCLR_ABRT_CLR_MASK
+/*
+ * Clear AHB buffer
+ */
+static inline void Qspi_Ip_ClearAhbBuf(QuadSPI_Type *baseAddr)
+{
+    baseAddr->SPTRCLR |= QuadSPI_SPTRCLR_ABRT_CLR_MASK;
+}
+
+/*
+ * Checks the Ahb buffer clear flag
+ * Returns TRUE if the Ahb buffer content is invalidated.
+ */
+static inline boolean Qspi_Ip_GetClrAhbStatus(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->SPTRCLR;
+
+    regValue = (regValue & QuadSPI_SPTRCLR_ABRT_CLR_MASK) >> QuadSPI_SPTRCLR_ABRT_CLR_SHIFT;
+    return (0U == regValue)? TRUE : FALSE;
+}
+#endif
+
+
+/*
+ * Enable QuadSPI device
+ */
+static inline void Qspi_Ip_Enable(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR &= ~QuadSPI_MCR_MDIS_MASK;
+
+}
+
+
+/*
+ * Disable QuadSPI device
+ */
+static inline void Qspi_Ip_Disable(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR |= QuadSPI_MCR_MDIS_MASK;
+
+}
+
+/*
+ * Enable DDR mode
+ */
+static inline void QSPI_DDR_Enable(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR |= QuadSPI_MCR_DDR_EN_MASK;
+
+}
+
+
+/*
+ * Disable DDR mode
+ */
+static inline void QSPI_DDR_Disable(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
+
+}
+
+
+/*
+ * Enable or disable DQS Latency
+ */
+static inline void QSPI_DQS_LatEnable(QuadSPI_Type *baseAddr, boolean enable)
+{
+    uint32 regValue = (uint32)baseAddr->MCR;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_MCR_DQS_LAT_EN_MASK));
+    regValue |= QuadSPI_MCR_DQS_LAT_EN(enable? 1U : 0U);
+
+    baseAddr->MCR = (uint32)regValue;
+}
+
+
+/*
+ * Enable DQS
+ */
+static inline void QSPI_DQS_Enable(QuadSPI_Type *baseAddr)
+{
+    (void)baseAddr;
+#ifdef QuadSPI_MCR_DQS_EN_MASK
+    baseAddr->MCR |= QuadSPI_MCR_DQS_EN_MASK;
+#endif
+}
+
+/*
+ * Disable DQS
+ */
+static inline void QSPI_DQS_Disable(QuadSPI_Type *baseAddr)
+{
+    (void)baseAddr;
+#ifdef QuadSPI_MCR_DQS_EN_MASK
+    baseAddr->MCR &= ~QuadSPI_MCR_DQS_EN_MASK;
+#endif
+}
+
+
+/*
+ * Assert QuadSPI sw reset bits
+ */
+static inline void Qspi_Ip_SwResetOn(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK;
+
+}
+
+
+/*
+ * Deassert QuadSPI sw reset bits
+ */
+static inline void Qspi_Ip_SwResetOff(QuadSPI_Type *baseAddr)
+{
+    baseAddr->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
+
+}
+
+
+/*
+ * Configure idle values for data lines 2:3
+ */
+static inline void Qspi_Ip_SetIdleLineValues(QuadSPI_Type *baseAddr,
+                                             uint8 iofa2IdleValue,
+                                             uint8 iofa3IdleValue,
+                                             uint8 iofb2IdleValue,
+                                             uint8 iofb3IdleValue
+                                            )
+{
+    /* get value MCR register */
+    uint32 regValue = (uint32)baseAddr->MCR;
+
+    /* set mask for ISD3FA,ISD2FA,ISD2FB,ISD3FB */
+    regValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK | QuadSPI_MCR_ISD2FB_MASK | QuadSPI_MCR_ISD3FB_MASK));
+    regValue |= (QuadSPI_MCR_ISD2FA(iofa2IdleValue) |
+                 QuadSPI_MCR_ISD3FA(iofa3IdleValue) |
+                 QuadSPI_MCR_ISD2FB(iofb2IdleValue) |
+                 QuadSPI_MCR_ISD3FB(iofb3IdleValue));
+    /* set again the MCR register */
+    baseAddr->MCR = (uint32)regValue;
+}
+
+
+
+/*
+ * Configure external flash memory map size A
+ */
+static inline void Qspi_Ip_SetMemMapSizeA(uint32 instance, QuadSPI_Type *baseAddr, uint32 sizeA1, uint32 sizeA2)
+{
+    baseAddr->SFA1AD = Qspi_Ip_AhbAddress[instance] + sizeA1;
+    baseAddr->SFA2AD = Qspi_Ip_AhbAddress[instance] + sizeA1 + sizeA2;
+}
+
+/*
+ * Configure external flash memory map size B
+ */
+static inline void Qspi_Ip_SetMemMapSizeB(QuadSPI_Type *baseAddr, uint32 sizeB1, uint32 sizeB2)
+{
+    /* Get memory address of size A2 */
+    uint32 regValue = (uint32)baseAddr->SFA2AD;
+
+    baseAddr->SFB1AD = regValue + sizeB1;
+    baseAddr->SFB2AD = regValue + sizeB1 + sizeB2;
+}
+
+/*
+ * Set CS hold time in serial clock cycles
+ */
+static inline void Qspi_Ip_SetCsHoldTime(QuadSPI_Type *baseAddr, uint8 cycles)
+{
+    uint32 regValue = (uint32)baseAddr->FLSHCR;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSH_MASK));
+    regValue |= QuadSPI_FLSHCR_TCSH(cycles);
+    baseAddr->FLSHCR = (uint32)regValue;
+}
+
+
+/*
+ * Set CS setup time
+ */
+static inline void Qspi_Ip_SetCsSetupTime(QuadSPI_Type *baseAddr, uint8 cycles)
+{
+    uint32 regValue = (uint32)baseAddr->FLSHCR;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSS_MASK));
+    regValue |= QuadSPI_FLSHCR_TCSS(cycles);
+    baseAddr->FLSHCR = (uint32)regValue;
+}
+
+
+/*
+ * Set data in hold time
+ */
+static inline void Qspi_Ip_SetDataInHoldTime(QuadSPI_Type *baseAddr, Qspi_Ip_FlashDataAlignType enable)
+{
+    uint32 regValue = (uint32)baseAddr->FLSHCR;
+
+    regValue &= (uint32)(~(QuadSPI_FLSHCR_TDH_MASK));
+    regValue |= QuadSPI_FLSHCR_TDH(enable);
+    baseAddr->FLSHCR = (uint32)regValue;
+}
+
+
+/*
+ * Sets AHB buffer 0 configuration
+ */
+static inline void Qspi_Ip_SetAhbBuf0(QuadSPI_Type *baseAddr,
+                                      uint16 size,
+                                      uint8 master
+                                     )
+{
+    baseAddr->BUF0CR =  QuadSPI_BUF0CR_ADATSZ((uint32)size >> 3U)
+                      | QuadSPI_BUF0CR_MSTRID(master);
+}
+
+
+/*
+ * Sets AHB buffer 1 configuration
+ */
+static inline void Qspi_Ip_SetAhbBuf1(QuadSPI_Type *baseAddr,
+                                      uint16 size,
+                                      uint8 master
+                                     )
+{
+    baseAddr->BUF1CR =  QuadSPI_BUF1CR_ADATSZ((uint32)size >> 3U)
+                      | QuadSPI_BUF1CR_MSTRID(master);
+}
+
+
+/*
+ * Sets AHB buffer 2 configuration
+ */
+static inline void Qspi_Ip_SetAhbBuf2(QuadSPI_Type *baseAddr,
+                                      uint16 size,
+                                      uint8 master
+                                     )
+{
+    baseAddr->BUF2CR =  QuadSPI_BUF2CR_ADATSZ((uint32)size >> 3U)
+                      | QuadSPI_BUF2CR_MSTRID(master);
+}
+
+
+/*
+ * Sets AHB buffer 3 configuration
+ */
+static inline void Qspi_Ip_SetAhbBuf3(QuadSPI_Type *baseAddr,
+                                       uint16 size,
+                                       uint8 master,
+                                       boolean allMasters
+                                     )
+{
+    baseAddr->BUF3CR =  QuadSPI_BUF3CR_ADATSZ((uint32)size >> 3U)
+                      | QuadSPI_BUF3CR_MSTRID(master)
+                      | QuadSPI_BUF3CR_ALLMST(allMasters? 1U : 0U);
+}
+
+
+/*
+ * Sets AHB buffer 0 index. Parameter represents desired end index of the buffer.
+ */
+static inline void Qspi_Ip_SetAhbBuf0Ind(QuadSPI_Type *baseAddr,
+                                         uint32 index
+                                        )
+{
+    baseAddr->BUF0IND =  index;
+}
+
+
+/*
+ * Sets AHB buffer 1 index. Parameter represents desired end index of the buffer.
+ */
+static inline void Qspi_Ip_SetAhbBuf1Ind(QuadSPI_Type *baseAddr,
+                                         uint32 index
+                                        )
+{
+    baseAddr->BUF1IND =  index;
+}
+
+
+/*
+ * Sets AHB buffer 2 index. Parameter represents desired end index of the buffer.
+ */
+static inline void Qspi_Ip_SetAhbBuf2Ind(QuadSPI_Type *baseAddr,
+                                         uint32 index
+                                        )
+{
+    baseAddr->BUF2IND =  index;
+}
+
+
+/*
+ * Sets address for IP transactions
+ */
+static inline void Qspi_Ip_SetIpAddr(QuadSPI_Type *baseAddr,
+                                     uint32 addr
+                                    )
+{
+    baseAddr->SFAR = addr;
+}
+
+
+/*
+ * Sets flash address options
+ */
+static inline void Qspi_Ip_SetAddrOptions(QuadSPI_Type *baseAddr,
+                                          uint32 columnAddr,
+                                          boolean wordAdressable
+                                         )
+{
+    baseAddr->SFACR = QuadSPI_SFACR_CAS(columnAddr)
+                    | QuadSPI_SFACR_WA(wordAdressable? 1U : 0U);
+}
+
+
+/*
+ * Configures parameters related to sampling Rx data
+ */
+static inline void Qspi_Ip_SetRxCfg(QuadSPI_Type *baseAddr,
+                                    Qspi_Ip_SampleDelayType delay,
+                                    Qspi_Ip_SamplePhaseType clockPhase
+                                   )
+{
+    baseAddr->SMPR = QuadSPI_SMPR_FSPHS(clockPhase)
+                   | QuadSPI_SMPR_FSDLY(delay);
+}
+
+
+
+
+/*
+ * Checks if module is busy with a transaction
+ */
+static inline boolean Qspi_Ip_GetBusyStatus(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->SR;
+
+    regValue = (regValue & QuadSPI_SR_BUSY_MASK) >> QuadSPI_SR_BUSY_SHIFT;
+    return (regValue != 0U)? TRUE : FALSE;
+}
+
+
+/*
+ * Returns the current fill level of the Rx buffer
+ */
+static inline uint32 Qspi_Ip_GetRxBufFill(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->RBSR;
+
+    regValue = (regValue & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
+    return regValue;
+}
+
+
+/*
+ * Checks if enough Rx data is available, according to the watermark setting
+ */
+static inline boolean Qspi_Ip_GetRxDataEvent(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->SR;
+
+    regValue = (regValue & QuadSPI_SR_RXWE_MASK) >> QuadSPI_SR_RXWE_SHIFT;
+    return (regValue != 0U)? TRUE : FALSE;
+}
+
+
+/*
+ * Returns Tx buffer fill level expressed in 4-byte entries
+ */
+static inline uint32 Qspi_Ip_GetTxBufFill(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->TBSR;
+
+    regValue = (regValue & QuadSPI_TBSR_TRBFL_MASK) >> QuadSPI_TBSR_TRBFL_SHIFT;
+    return regValue;
+}
+
+
+/*
+ * Checks the Tx buffer watermark.
+ * Returns TRUE if number of buffer entries specified by the watermark is available.
+ */
+static inline boolean Qspi_Ip_GetTxWatermarkAvailable(const QuadSPI_Type *baseAddr)
+{
+    uint32 regValue = (uint32)baseAddr->SR;
+
+    regValue = (regValue & QuadSPI_SR_TXWA_MASK) >> QuadSPI_SR_TXWA_SHIFT;
+    return (regValue != 0U)? TRUE : FALSE;
+}
+
+
+/*
+ * Writes data in the Tx buffer
+ */
+static inline void Qspi_Ip_WriteTxData(QuadSPI_Type *baseAddr, uint32 data)
+{
+    baseAddr->TBDR = data;
+}
+
+
+/*
+ * Returns the address of the Tx data register
+ */
+static inline uint32 Qspi_Ip_GetTxDataAddr(const QuadSPI_Type *baseAddr)
+{
+    return (uint32)&(baseAddr->TBDR);
+}
+
+
+/*
+ * Returns the address of the first Rx data register
+ */
+static inline uint32 Qspi_Ip_GetRxDataAddr(const QuadSPI_Type *baseAddr)
+{
+    return (uint32)&(baseAddr->RBDR[0U]);
+}
+
+
+/*
+ * Enables Tx DMA request (when Tx buffer has room for more data)
+ */
+static inline void Qspi_Ip_EnableTxDmaReq(QuadSPI_Type *baseAddr)
+{
+    baseAddr->RSER |= QuadSPI_RSER_TBFDE_MASK;
+}
+
+
+/*
+ * Enables Rx DMA request (when Rx buffer has room for more data)
+ */
+static inline void Qspi_Ip_EnableRxDmaReq(QuadSPI_Type *baseAddr)
+{
+    baseAddr->RSER |= QuadSPI_RSER_RBDDE_MASK;
+}
+
+
+/*
+ * Disables both Rx and Tx DMA requests
+ */
+static inline void Qspi_Ip_DisableDmaReq(QuadSPI_Type *baseAddr)
+{
+    baseAddr->RSER &= ~(QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK);
+}
+
+
+/*
+ * Perform a POP operation on the Rx buffer, removing Rx_watermark entries
+ */
+static inline void Qspi_Ip_RxPop(QuadSPI_Type *baseAddr)
+{
+    baseAddr->FR = QuadSPI_FR_RBDF_MASK;
+}
+
+
+/*
+ * Configures the watermark for the Rx buffer, expressed in number of 4-byte entries
+ */
+static inline void Qspi_Ip_SetRxWatermark(QuadSPI_Type *baseAddr,
+                                          uint8 watermark
+                                         )
+{
+    uint32 regValue = (uint32)baseAddr->RBCT;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_RBCT_WMRK_MASK));
+    regValue |= QuadSPI_RBCT_WMRK((uint32)watermark - 1U);
+    baseAddr->RBCT = (uint32)regValue;
+}
+
+
+/*
+ * Configures the rx for the Rx buffer, expressed in number of 4-byte entries
+ */
+static inline void Qspi_Ip_SetRxBufReadout(QuadSPI_Type *baseAddr,
+                                           uint8 readout
+                                          )
+{
+    uint32 regValue = (uint32)baseAddr->RBCT;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_RBCT_RXBRD_MASK));
+    regValue |= QuadSPI_RBCT_RXBRD(readout);
+    baseAddr->RBCT = (uint32)regValue;
+}
+
+
+/*
+ * Configures the watermark for the Tx buffer, expressed in number of 4-byte entries
+ */
+static inline void Qspi_Ip_SetTxWatermark(QuadSPI_Type *baseAddr,
+                                          uint8 watermark
+                                         )
+{
+    uint32 regValue = (uint32)baseAddr->TBCT;
+
+    regValue &= (uint32)(~((uint32)QuadSPI_TBCT_WMRK_MASK));
+    regValue |= QuadSPI_TBCT_WMRK(watermark);
+    baseAddr->TBCT = (uint32)regValue;
+}
+
+
+/*
+ * Enables interrupts specified by the mask parameter
+ */
+static inline void Qspi_Ip_EnableInt(QuadSPI_Type *baseAddr,
+                                     uint32 mask
+                                    )
+{
+    baseAddr->RSER |= mask;
+}
+
+
+/*
+ * Disables interrupts specified by the mask parameter
+ */
+static inline void Qspi_Ip_DisableInt(QuadSPI_Type *baseAddr,
+                                      uint32 mask
+                                     )
+{
+    baseAddr->RSER &= ~mask;
+}
+
+
+/*
+ * Clears interrupt flags specified by the mask parameter
+ */
+static inline void Qspi_Ip_ClearIntFlag(QuadSPI_Type *baseAddr,
+                                        uint32 mask
+                                       )
+{
+    baseAddr->FR = mask;
+}
+
+
+
+
+
+
+
+
+#ifdef QuadSPI_MCR_SCLKCFG_MASK
+/*
+ * Configure chip-specific clock options
+ */
+static inline void Qspi_Ip_SetClockOptions(QuadSPI_Type *baseAddr, uint8 option)
+{
+    uint32 regValue = (uint32)baseAddr->MCR;
+
+    regValue &= (uint32)(~QuadSPI_MCR_SCLKCFG_MASK);
+    regValue |= QuadSPI_MCR_SCLKCFG(option);
+    baseAddr->MCR = (uint32)regValue;
+}
+#endif
+
+
+#ifdef QuadSPI_SOCCR_SOCCFG_MASK
+/*
+ * Configure chip-specific options
+ */
+static inline void Qspi_Ip_SetChipOptions(QuadSPI_Type *baseAddr, uint32 option)
+{
+    baseAddr->SOCCR = option;
+}
+#endif
+
+#endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QUADSPI_HW_ACCESS_H */

RTD/include/Qspi_Ip_Types.h

@@ -0,0 +1,512 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QSPI_IP_TYPES_H
+#define QSPI_IP_TYPES_H
+
+/**
+*   @file Qspi_Ip_Types.h
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_Types.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "StandardTypes.h"
+#include "Qspi_Ip_Features.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_QSPI_TYPES_VENDOR_ID                    43
+#define FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION     4
+#define FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION     4
+#define FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION  0
+#define FLS_QSPI_TYPES_SW_MAJOR_VERSION             1
+#define FLS_QSPI_TYPES_SW_MINOR_VERSION             0
+#define FLS_QSPI_TYPES_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Qspi_Ip_Types header file and StandardTypes.h header file are of the same Autosar version */
+    #if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "Autosar Version Numbers of Qspi_Ip_Types.h and StandardTypes.h are different"
+    #endif
+#endif
+
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (FLS_QSPI_TYPES_VENDOR_ID != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Qspi_Ip_Types.h and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((FLS_QSPI_TYPES_SW_MAJOR_VERSION != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_TYPES_SW_MINOR_VERSION != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_TYPES_SW_PATCH_VERSION != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Types.h and Qspi_Ip_Features.h are different"
+#endif
+
+
+/*******************************************************************************
+ * Enumerations.
+ ******************************************************************************/
+
+/*! Number of erase types that can be supported by a flash device */
+#define     QSPI_IP_ERASE_TYPES      4U
+
+/*! @brief Number of AHB buffers in the device */
+#define QSPI_IP_AHB_BUFFERS   4U
+
+/*! Invalid sequence number in virtual LUT, used for unsupported features */
+#define     QSPI_IP_LUT_INVALID     (uint16)0xFFFFU
+/*! End operation for a LUT sequence */
+#define     QSPI_IP_LUT_SEQ_END     (uint16)0x0U
+
+
+/*! @brief qspi return codes
+ */
+typedef enum
+{
+    STATUS_QSPI_IP_SUCCESS              = 0x00U,   /*!< Successful job */
+    STATUS_QSPI_IP_ERROR                = 0x01U,   /*!< IP is performing an operation */
+    STATUS_QSPI_IP_BUSY                 = 0x02U,   /*!< Error - general code */
+    STATUS_QSPI_IP_TIMEOUT              = 0x03U,   /*!< Error - exceeded timeout */
+    STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY = 0x04U,   /*!< Error - selected memory area doesn't contain desired value */
+} Qspi_Ip_StatusType;
+
+
+/*! @brief flash connection to the QSPI module
+ */
+typedef enum
+{
+    QSPI_IP_SIDE_A1    = 0x00U,  /*!< Serial flash connected on side A1    */
+    QSPI_IP_SIDE_A2    = 0x01U,  /*!< Serial flash connected on side A2    */
+    QSPI_IP_SIDE_B1    = 0x02U,  /*!< Serial flash connected on side B1    */
+    QSPI_IP_SIDE_B2    = 0x03U,  /*!< Serial flash connected on side B2    */
+} Qspi_Ip_ConnectionType;
+
+
+/*! @brief flash operation type
+ */
+typedef enum
+{
+    QSPI_IP_OP_TYPE_CMD          = 0x00U,  /*!< Simple command                              */
+    QSPI_IP_OP_TYPE_WRITE_REG    = 0x01U,  /*!< Write value in external flash register      */
+    QSPI_IP_OP_TYPE_RMW_REG      = 0x02U,  /*!< RMW command on external flash register      */
+    QSPI_IP_OP_TYPE_READ_REG     = 0x03U,  /*!< Read external flash register until expected value is read    */
+    QSPI_IP_OP_TYPE_QSPI_CFG     = 0x04U,  /*!< Re-configure QSPI controller                */
+} Qspi_Ip_OpType;
+
+/*! @brief Lut commands
+ */
+typedef enum
+{
+    QSPI_IP_LUT_INSTR_STOP            = (0U << 10U),    /*!<  End of sequence                           */
+    QSPI_IP_LUT_INSTR_CMD             = (1U << 10U),    /*!<  Command                                   */
+    QSPI_IP_LUT_INSTR_ADDR            = (2U << 10U),    /*!<  Address                                   */
+    QSPI_IP_LUT_INSTR_DUMMY           = (3U << 10U),    /*!<  Dummy cycles                              */
+    QSPI_IP_LUT_INSTR_MODE            = (4U << 10U),    /*!<  8-bit mode                                */
+    QSPI_IP_LUT_INSTR_MODE2           = (5U << 10U),    /*!<  2-bit mode                                */
+    QSPI_IP_LUT_INSTR_MODE4           = (6U << 10U),    /*!<  4-bit mode                                */
+    QSPI_IP_LUT_INSTR_READ            = (7U << 10U),    /*!<  Read data                                 */
+    QSPI_IP_LUT_INSTR_WRITE           = (8U << 10U),    /*!<  Write data                                */
+    QSPI_IP_LUT_INSTR_JMP_ON_CS       = (9U << 10U),    /*!<  Jump on chip select deassert and stop     */
+    QSPI_IP_LUT_INSTR_ADDR_DDR        = (10U << 10U),   /*!<  Address - DDR mode                        */
+    QSPI_IP_LUT_INSTR_MODE_DDR        = (11U << 10U),   /*!<  8-bit mode - DDR mode                     */
+    QSPI_IP_LUT_INSTR_MODE2_DDR       = (12U << 10U),   /*!<  2-bit mode - DDR mode                     */
+    QSPI_IP_LUT_INSTR_MODE4_DDR       = (13U << 10U),   /*!<  4-bit mode - DDR mode                     */
+    QSPI_IP_LUT_INSTR_READ_DDR        = (14U << 10U),   /*!<  Read data - DDR mode                      */
+    QSPI_IP_LUT_INSTR_WRITE_DDR       = (15U << 10U),   /*!<  Write data - DDR mode                     */
+    QSPI_IP_LUT_INSTR_DATA_LEARN      = (16U << 10U),   /*!<  Data learning pattern                     */
+    QSPI_IP_LUT_INSTR_CMD_DDR         = (17U << 10U),   /*!<  Command - DDR mode                        */
+    QSPI_IP_LUT_INSTR_CADDR           = (18U << 10U),   /*!<  Column address                            */
+    QSPI_IP_LUT_INSTR_CADDR_DDR       = (19U << 10U),   /*!<  Column address - DDR mode                 */
+    QSPI_IP_LUT_INSTR_JMP_TO_SEQ      = (20U << 10U),   /*!<  Jump on chip select deassert and continue */
+} Qspi_Ip_LutCommandsType;
+
+/*! @brief Lut pad options
+ */
+typedef enum
+{
+    QSPI_IP_LUT_PADS_1              = (0U << 8U),    /*!<  1 Pad      */
+    QSPI_IP_LUT_PADS_2              = (1U << 8U),    /*!<  2 Pads     */
+    QSPI_IP_LUT_PADS_4              = (2U << 8U),    /*!<  4 Pads     */
+    QSPI_IP_LUT_PADS_8              = (3U << 8U),    /*!<  8 Pads     */
+} Qspi_Ip_LutPadsType;
+
+/*!
+ * @brief Operation in a LUT sequence.
+ *
+ * This type describes one basic operation inside a LUT sequence. Each operation contains:
+ *  - instruction (6 bits)
+ *  - number of PADs (2 bits)
+ *  - operand (8 bits)
+ * Qspi_Ip_LutCommandsType and Qspi_Ip_LutPadsType types should be used to form operations
+ */
+typedef uint16 Qspi_Ip_InstrOpType;
+
+/*! @brief Read mode
+ */
+typedef enum
+{
+#if (FEATURE_QSPI_INTERNAL_DQS == 1)
+    QSPI_IP_READ_MODE_INTERNAL_DQS        = 0U,  /*!< Use internally generated strobe signal       */
+#endif
+#if (FEATURE_QSPI_LOOPBACK == 1)
+    QSPI_IP_READ_MODE_LOOPBACK            = 1U,  /*!< Use loopback clock from PAD as strobe signal */
+#endif
+#if (FEATURE_QSPI_LOOPBACK_DQS == 1)
+    QSPI_IP_READ_MODE_LOOPBACK_DQS        = 2U,  /*!< Use loopback clock from PAD as strobe signal */
+#endif
+    QSPI_IP_READ_MODE_EXTERNAL_DQS        = 3U,  /*!< Use external strobe signal                   */
+} Qspi_Ip_ReadModeType;
+
+
+/*! @brief Clock phase used for sampling Rx data
+ */
+typedef enum
+{
+    QSPI_IP_DATA_RATE_SDR         = 0U,    /*!<  Single data rate    */
+    QSPI_IP_DATA_RATE_DDR         = 1U,    /*!<  Double data rate    */
+} Qspi_Ip_DataRateType;
+
+
+/*! @brief Delay used for sampling Rx data
+ */
+typedef enum
+{
+    QSPI_IP_SAMPLE_DELAY_SAME_DQS              = 0U,    /*!<  Same DQS              */
+    QSPI_IP_SAMPLE_DELAY_HALFCYCLE_EARLY_DQS   = 1U,    /*!<  Half-cycle early DQS  */
+} Qspi_Ip_SampleDelayType;
+
+/*! @brief Clock phase used for sampling Rx data
+ */
+typedef enum
+{
+    QSPI_IP_SAMPLE_PHASE_NON_INVERTED    = 0U,    /*!<  Sampling at non-inverted clock  */
+    QSPI_IP_SAMPLE_PHASE_INVERTED        = 1U,    /*!<  Sampling at inverted clock      */
+} Qspi_Ip_SamplePhaseType;
+
+/*! @brief Alignment of outgoing data with serial clock
+ */
+typedef enum
+{
+    QSPI_IP_FLASH_DATA_ALIGN_REFCLK      = 0U,    /*!<  Data aligned with the posedge of Internal reference clock of QSPI  */
+    QSPI_IP_FLASH_DATA_ALIGN_2X_REFCLK   = 1U,    /*!<  Data aligned with 2x serial flash half clock                          */
+} Qspi_Ip_FlashDataAlignType;
+
+
+
+/*! @brief Init callout pointer type
+*/
+typedef Qspi_Ip_StatusType (*Qspi_Ip_InitCalloutPtrType)(uint32 instance);
+
+/*! @brief Reset callout pointer type
+*/
+typedef Qspi_Ip_StatusType (*Qspi_Ip_ResetCalloutPtrType)(uint32 instance);
+
+/*! @brief Error Check callout pointer type
+*/
+typedef Qspi_Ip_StatusType (*Qspi_Ip_ErrorCheckCalloutPtrType)(uint32 instance);
+
+/*! @brief Ecc Check callout pointer type
+*/
+typedef Qspi_Ip_StatusType (*Qspi_Ip_EccCheckCalloutPtrType)(uint32 instance, uint32 startAddress, uint32 dataLength);
+
+
+/*******************************************************************************
+* Definitions
+******************************************************************************/
+
+
+/*!
+ * @brief AHB configuration structure
+ *
+ * This structure is used to provide configuration parameters for AHB access
+ * to the external flash
+ */
+typedef struct
+{
+    uint8 masters[QSPI_IP_AHB_BUFFERS];    /*!< List of AHB masters assigned to each buffer          */
+    uint16 sizes[QSPI_IP_AHB_BUFFERS];     /*!< List of buffer sizes                                 */
+    boolean allMasters;                    /*!< Indicates that any master may access the last buffer */
+} Qspi_Ip_ControllerAhbConfigType;
+
+#if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148)
+/*! @brief Source of QuadSPI AHB read interface, module and bus interface clock
+ */
+typedef enum
+{
+    QSPI_IP_CLK_SRC_SYS_CLK = 0U,  /*!< FIRC_DIV1 is clock source of QuadSPI internal reference clock */
+    QSPI_IP_CLK_SRC_BUS_CLK = 1U,  /*!< PLL_DIV1 is clock source of QuadSPI internal reference clock  */
+} Qspi_Ip_ClockSourceType;
+
+/*! @brief Source of QuadSPI internal reference clock
+ */
+typedef enum
+{
+    QSPI_IP_CLK_REF_PLL_DIV1  = 0U,  /*!< PLL_DIV1 is clock source of QuadSPI internal reference clock  */
+    QSPI_IP_CLK_REF_FIRC_DIV1 = 1U,  /*!< FIRC_DIV1 is clock source of QuadSPI internal reference clock */
+} Qspi_Ip_ClockReferenceType;
+#endif
+
+/*!
+ * @brief Driver configuration structure
+ *
+ * This structure is used to provide configuration parameters for the qspi driver
+ * at initialization time.
+ */
+typedef struct
+{
+#if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148)
+    Qspi_Ip_ClockSourceType    clockSrc;    /*!< AHB read interface, module and bus interface clock      */
+    Qspi_Ip_ClockReferenceType clockRef;    /*!< Internal reference clock (async clock domain)           */
+    uint8   clockRefDiv;                    /*!< Divider value for internal reference clock              */
+    boolean dqsInvertA;                     /*!< Inverted reference clock selection for DQS Flash A      */
+    boolean dqsInvertB;                     /*!< Inverted reference clock selection for DQS Flash B      */
+    uint8   dqsDelayA;                      /*!< Fine delay chain configuration for Flash A              */
+    uint8   dqsDelayB;                      /*!< Fine delay chain configuration for Flash B              */
+#endif
+
+    Qspi_Ip_DataRateType dataRate;          /*!< Single/double data rate                                 */
+    uint32 memSizeA1;                       /*!< Size of serial flash A1                                 */
+    uint32 memSizeA2;                       /*!< Size of serial flash A2                                 */
+    uint32 memSizeB1;                       /*!< Size of serial flash B1                                 */
+    uint32 memSizeB2;                       /*!< Size of serial flash B2                                 */
+    uint8 csHoldTime;                       /*!< CS hold time, expressed in serial clock cycles          */
+    uint8 csSetupTime;                      /*!< CS setup time, expressed in serial clock cycles         */
+    uint8 columnAddr;                       /*!< Width of the column address, 0 if not used              */
+    boolean wordAddresable;                 /*!< True if serial flash is word addressable                */
+    Qspi_Ip_ReadModeType readModeA;         /*!< Read mode for incoming data from serial flash A         */
+    Qspi_Ip_ReadModeType readModeB;         /*!< Read mode for incoming data from serial flash B         */
+    Qspi_Ip_SampleDelayType sampleDelay;    /*!< Delay (in clock cycles) used for sampling Rx data       */
+    Qspi_Ip_SamplePhaseType samplePhase;    /*!< Clock phase used for sampling Rx data                   */
+
+
+    boolean dqsLatency;                     /*!< Enable DQS latency for reads (Hyperflash)               */
+    Qspi_Ip_FlashDataAlignType dataAlign;   /*!< Alignment of output data sent to serial flash           */
+    uint8 io2IdleValueA;                    /*!< (0 / 1) Logic level of IO[2] signal when not used on side A      */
+    uint8 io3IdleValueA;                    /*!< (0 / 1) Logic level of IO[3] signal when not used on side A      */
+    uint8 io2IdleValueB;                    /*!< (0 / 1) Logic level of IO[2] signal when not used on side B      */
+    uint8 io3IdleValueB;                    /*!< (0 / 1) Logic level of IO[3] signal when not used on side B      */
+    Qspi_Ip_ControllerAhbConfigType ahbConfig;  /*!< AHB buffers configuration                     */
+} Qspi_Ip_ControllerConfigType;
+
+ /*!
+ * @brief Status register configuration structure
+ *
+ * This structure contains information about the status registers of the external flash
+ */
+typedef struct
+{
+    uint16 statusRegInitReadLut;     /*!< Command used to read the status register during initialization                   */
+    uint16 statusRegReadLut;         /*!< Command used to read the status register                                         */
+    uint16 statusRegWriteLut;        /*!< Command used to write the status register                                        */
+    uint16 writeEnableSRLut;         /*!< Write enable command used before writing to status register                      */
+    uint16 writeEnableLut;           /*!< Write enable command used before write or erase operations                       */
+    uint8 regSize;                   /*!< Size in bytes of status register                                                 */
+    uint8 busyOffset;                /*!< Position of "busy" bit inside status register                                    */
+    uint8 busyValue;                 /*!< Value of "busy" bit which indicates that the device is busy; can be 0 or 1       */
+    uint8 writeEnableOffset;         /*!< Position of "write enable" bit inside status register                            */
+    uint8 blockProtectionOffset;     /*!< Offset of block protection bits inside status register                           */
+    uint8 blockProtectionWidth;      /*!< Width of block protection bitfield                                               */
+    uint8 blockProtectionValue;      /*!< Value of block protection bitfield, indicate the protected area                  */
+} Qspi_Ip_StatusConfigType;
+
+
+ /*!
+ * @brief Describes one type of erase
+ *
+ * This structure contains information about one type of erase supported by the external flash
+ */
+typedef struct
+{
+    uint16 eraseLut;              /*!< Lut index for erase command */
+    uint8 size;                   /*!< Size of the erased area: 2 ^ size; e.g. 0x0C means 4 Kbytes */
+} Qspi_Ip_EraseVarConfigType;
+
+
+ /*!
+ * @brief Erase capabilities configuration structure
+ *
+ * This structure contains information about the erase capabilities of the external flash
+ */
+typedef struct
+{
+    Qspi_Ip_EraseVarConfigType eraseTypes[QSPI_IP_ERASE_TYPES];      /*!< Erase types supported by the device  */
+    uint16 chipEraseLut;                                             /*!< Lut index for chip erase command */
+} Qspi_Ip_EraseConfigType;
+
+
+ /*!
+ * @brief Read Id capabilities configuration structure
+ *
+ * This structure contains information about the read manufacturer/device ID command
+ */
+typedef struct
+{
+    uint16 readIdLut;                               /*!< Read Id command                                  */
+    uint16 readIdSize;                              /*!< Size of data returned by Read Id command         */
+    uint32 readIdExpected;                          /*!< Device ID configured value (Memory density | Memory type | Manufacturer ID) */
+} Qspi_Ip_ReadIdConfigType;
+
+
+ /*!
+ * @brief Suspend capabilities configuration structure
+ *
+ * This structure contains information about the Program / Erase Suspend capabilities of the external flash
+ */
+typedef struct
+{
+    uint16 eraseSuspendLut;       /*!< Lut index for the erase suspend operation   */
+    uint16 eraseResumeLut;        /*!< Lut index for the erase resume operation    */
+    uint16 programSuspendLut;     /*!< Lut index for the program suspend operation */
+    uint16 programResumeLut;      /*!< Lut index for the program resume operation  */
+} Qspi_Ip_SuspendConfigType;
+
+
+/*!
+ * @brief Soft Reset capabilities configuration structure
+ *
+ * This structure contains information about the Soft Reset capabilities of the external flash
+ */
+typedef struct
+{
+    uint16 resetCmdLut;                   /*!< First command in reset sequence            */
+    uint8 resetCmdCount;                  /*!< Number of commands in reset sequence       */
+} Qspi_Ip_ResetConfigType;
+
+
+/*!
+ * @brief List of LUT sequences.
+ *
+ * List of LUT sequences. Each sequence describes a command to the external flash. Sequences are separated by a 0 operation
+ */
+typedef struct
+{
+    uint16 opCount;                    /*!< Number of operations in the LUT table    */
+    Qspi_Ip_InstrOpType *lutOps;       /*!< List of operations                       */
+} Qspi_Ip_LutConfigType;
+
+
+/*!
+ * @brief Initialization operation
+ *
+ * This structure describes one initialization operation.
+ */
+typedef struct
+{
+    Qspi_Ip_OpType opType;         /*!< Operation type                                 */
+    uint16 command1Lut;            /*!< Index of first command sequence in Lut; for RMW type this is the read command               */
+    uint16 command2Lut;            /*!< Index of second command sequence in Lut, only used for RMW type, this is the write command  */
+    uint16 weLut;                  /*!< Index of write enable sequence in Lut, only used for Write and RMW type                     */
+    uint32 addr;                   /*!< Address, if used in command.                                                                */
+    uint8 size;                    /*!< Size in bytes of configuration register                                                     */
+    uint8 shift;                   /*!< Position of configuration field inside the register                                         */
+    uint8 width;                   /*!< Width in bits of configuration field.                                                       */
+    uint32 value;                  /*!< Value to set in the field                                                                   */
+    const Qspi_Ip_ControllerConfigType * ctrlCfgPtr;  /*!< New controller configuration, valid only for QSPI_IP_OP_TYPE_QSPI_CFG type     */
+} Qspi_Ip_InitOperationType;
+
+
+/*!
+ * @brief Initialization sequence
+ *
+ * Describe sequence that will be performed only once during initialization to put the flash in the desired state for operation.
+ * This may include, for example, setting the QE bit, activating 4-byte addressing, activating XPI mode
+ */
+typedef struct
+{
+    uint8 opCount;                                     /*!< Number of operations  */
+    Qspi_Ip_InitOperationType * operations;            /*!< List of operations    */
+} Qspi_Ip_InitConfigType;
+
+
+
+/*!
+ * @brief Driver configuration structure
+ *
+ * This structure is used to provide configuration parameters for the external flash driver
+ * at initialization time.
+ */
+typedef struct
+{
+    uint32 memSize;                                       /*!< Memory size (in bytes)                           */
+    uint32 pageSize;                                      /*!< Page size (in bytes)                             */
+    uint16 readLut;                                       /*!< Command used to read data from flash             */
+    uint16 writeLut;                                      /*!< Command used to write data to flash              */
+    uint16 read0xxLut;                                    /*!< 0-x-x mode read command                          */
+    uint16 read0xxLutAHB;                                 /*!< 0-x-x mode AHB read command                      */
+    Qspi_Ip_ReadIdConfigType readIdSettings;              /*!< Erase settings of the external flash             */
+    Qspi_Ip_EraseConfigType eraseSettings;                /*!< Erase settings of the external flash             */
+    Qspi_Ip_StatusConfigType statusConfig;                /*!< Status register information                      */
+    Qspi_Ip_SuspendConfigType suspendSettings;            /*!< Program / Erase Suspend settings                 */
+    Qspi_Ip_ResetConfigType resetSettings;                /*!< Soft Reset settings, used at runtime             */
+    Qspi_Ip_ResetConfigType initResetSettings;            /*!< Soft Reset settings, used for first time reset   */
+    Qspi_Ip_InitConfigType initConfiguration;             /*!< Operations for initial flash configuration       */
+    Qspi_Ip_LutConfigType lutSequences;                   /*!< List of LUT sequences describing flash commands  */
+    Qspi_Ip_InitCalloutPtrType initCallout;               /*!< Pointer to init callout                          */
+    Qspi_Ip_ResetCalloutPtrType resetCallout;             /*!< Pointer to reset callout                         */
+    Qspi_Ip_ErrorCheckCalloutPtrType errorCheckCallout;   /*!< Pointer to error check callout                   */
+    Qspi_Ip_EccCheckCalloutPtrType eccCheckCallout;       /*!< Pointer to ecc check callout                     */
+    const Qspi_Ip_ControllerConfigType * ctrlAutoCfgPtr;  /*!< Initial controller configuration, if needed      */
+} Qspi_Ip_MemoryConfigType;
+
+
+/*!
+ * @brief Flash-controller conections configuration structure
+ *
+ * This structure specifies thte connecctions of each flash device to QSPI controllers
+ * at initialization time.
+ */
+typedef struct
+{
+    uint32 qspiInstance;                              /*!< QSPI Instance where this device is connected     */
+    Qspi_Ip_ConnectionType connectionType;            /*!< Device connection to QSPI module                 */
+} Qspi_Ip_MemoryConnectionType;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_TYPES_H */

RTD/src/Fls.c

@@ -0,0 +1,2861 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+/**
+*   @file Fls.c
+*
+*   @addtogroup FLS FLS Driver
+*   @{
+*/
+
+/* implements Fls.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+ /* Compiler warning fls_c_REF_CW_01: explicit cast discards volatile qualifier.
+   The cast is explicit, intended and the casted value is treated properly.
+   Sizes of the pointers and integral types for all the supported platforms/compilers are well known
+   and the volatile keyword is not needed when using the pointer value as a flash address counter,
+   as the pointer value is not updated in the DSI interrupt context or by other hardware means.
+ */
+
+
+/*==================================================================================================
+ *                                        INCLUDE FILES
+ * 1) system and project includes
+ * 2) needed interfaces from external units
+ * 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls.h"
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+#endif
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+#include "Qspi_Ip.h"
+#endif
+#if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+#if (STD_ON == FLS_CLEAN_CACHE_AFTER_LOAD_AC)
+#include "Cache_Ip.h"
+#endif /* FLS_CLEAN_CACHE_AFTER_LOAD_AC */
+#endif /* FLS_AC_LOAD_ON_JOB_START */
+#include "Det.h"
+#include "SchM_Fls.h"
+#include "StandardTypes.h"
+#include "Fls_IPW.h"
+
+
+/*==================================================================================================
+ *                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VENDOR_ID_C                      43
+#define FLS_AR_RELEASE_MAJOR_VERSION_C       4
+#define FLS_AR_RELEASE_MINOR_VERSION_C       4
+#define FLS_AR_RELEASE_REVISION_VERSION_C    0
+#define FLS_SW_MAJOR_VERSION_C               1
+#define FLS_SW_MINOR_VERSION_C               0
+#define FLS_SW_PATCH_VERSION_C               0
+
+
+/*==================================================================================================
+ *                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls header file are of the same vendor */
+#if (FLS_VENDOR_ID_C != FLS_VENDOR_ID)
+    #error "Fls.c and Fls.h have different vendor ids"
+#endif
+/* Check if current file and Fls header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_C    != FLS_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_C    != FLS_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_C != FLS_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls.c and Fls.h are different"
+#endif
+/* Check if current file and Fls header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_C != FLS_SW_MAJOR_VERSION) || \
+     (FLS_SW_MINOR_VERSION_C != FLS_SW_MINOR_VERSION) || \
+     (FLS_SW_PATCH_VERSION_C != FLS_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls.c and Fls.h are different"
+#endif
+
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+#endif /* STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    /* Check if current file and Qspi_Ip.h header file are of the same vendor */
+    #if (FLS_VENDOR_ID_C != QSPI_IP_VENDOR_ID_H)
+        #error "Fls.c and Qspi_Ip.h have different vendor ids"
+    #endif
+    /* Check if current file and Qspi_Ip.h header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+         (FLS_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+        )
+        #error "AutoSar Version Numbers of Fls.c and Qspi_Ip.h are different"
+    #endif
+    /* Check if current file and Qspi_Ip.h header file are of the same Software version */
+    #if ((FLS_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_H) || \
+         (FLS_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_H) || \
+         (FLS_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_H) \
+        )
+        #error "Software Version Numbers of Fls.c and Qspi_Ip.h are different"
+    #endif
+#endif /* STD_ON == FLS_QSPI_SECTORS_CONFIGURED */
+
+#if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+    #if (STD_ON == FLS_CLEAN_CACHE_AFTER_LOAD_AC )
+        #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+            /* Check if current file and Cache_Ip.h header file are of the same Autosar version */
+            #if ((FLS_AR_RELEASE_MAJOR_VERSION_C != CACHE_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+                 (FLS_AR_RELEASE_MINOR_VERSION_C != CACHE_IP_AR_RELEASE_MINOR_VERSION_H) \
+                )
+                #error "AutoSar Version Numbers of Fls.c and Cache_Ip.h are different"
+            #endif
+        #endif
+    #endif /* STD_ON == FLS_CLEAN_CACHE_AFTER_LOAD_AC  */
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Det header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_C != DET_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_C != DET_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls.c and Det.h are different"
+    #endif
+    /* Check if current file and SchM_Fls header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_C != SCHM_FLS_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_C != SCHM_FLS_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls.c and SchM_Fls.h are different"
+    #endif
+    /* Check if current file and StandardTypes header file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls.c and StandardTypes.h are different"
+    #endif
+#endif
+
+/* Check if current file and Fls_IPW.h header file are of the same vendor */
+#if (FLS_VENDOR_ID_C != FLS_IPW_VENDOR_ID_H)
+    #error "Fls.c and Fls_IPW.h have different vendor ids"
+#endif
+/* Check if current file and Dem header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_C    != FLS_IPW_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_C    != FLS_IPW_AR_RELEASE_MINOR_VERSION_H) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_C != FLS_IPW_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Fls.c and Fls_IPW.h are different"
+#endif
+/* Check if current file and Fls_IPW.h header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_C != FLS_IPW_SW_MAJOR_VERSION_H) || \
+     (FLS_SW_MINOR_VERSION_C != FLS_IPW_SW_MINOR_VERSION_H) || \
+     (FLS_SW_PATCH_VERSION_C != FLS_IPW_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Fls.c and Fls_IPW.h are different"
+#endif
+
+
+/*==================================================================================================
+ *                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+/**
+ * @brief Logical address of data block currently processed by Fls_MainFunction
+ */
+Fls_AddressType Fls_u32JobAddrIt;
+/**
+ * @brief Last logical address to be processed by a job
+ */
+Fls_AddressType Fls_u32JobAddrEnd;
+/**
+ * @brief Index of flash sector currently processed by a job
+ * @details Used by all types of job
+ */
+volatile Fls_SectorIndexType Fls_u32JobSectorIt;
+
+/**
+ * @brief Type of currently executed job (erase, write, read, or compare)
+ */
+static Fls_JobType Fls_eJob;                             /* implicit zero initialization: FLS_JOB_ERASE */
+/**
+ * @brief Index of last flash sector by current job
+ * @details Used to check status of all external flash chips before start jobs
+ * or is the last sector in Erease job
+ */
+Fls_SectorIndexType Fls_u32JobSectorEnd;
+/**
+    @brief Result of last flash hardware job
+ */
+volatile MemIf_JobResultType Fls_eLLDJobResult;          /* implicit zero initialization: MEMIF_JOB_OK */
+/**
+    @brief Type of current flash hardware job - used for asynchronous operating mode.
+ */
+Fls_LLDJobType Fls_eLLDJob;    /* implicit zero initialization: FLASH_JOB_NONE */
+/**
+ * @brief Pointer to current flash module configuration set
+ */
+const Fls_ConfigType * Fls_pConfigPtr;                   /* implicit zero initialization: NULL_PTR */
+
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+ *                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                        LOCAL MACROS
+==================================================================================================*/
+/**
+    @brief fill pattern used to clear write and erase access code in RAM
+ */
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+#define FLS_AC_UNLOAD_PATTERN 0xffffffffU
+
+
+#define FLS_START_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+/* @brief verify that AC loaded or not */
+boolean Fls_bACloaded;                                   /* implicit zero initialization: FALSE */
+
+#define FLS_STOP_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+#endif
+
+/**
+    @brief Calculate total flash size in bytes
+ */
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+#define FLS_TOTAL_SIZE ((*(Fls_pConfigPtr->paSectorEndAddr))[Fls_pConfigPtr->u32SectorCount - 1U] + 1U)
+#endif
+
+
+/*==================================================================================================
+                                       LOCAL VARIABLES
+==================================================================================================*/
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/**
+ * @brief Maximum number of bytes to read or compare in one cycle of Fls_MainFunction
+ */
+static Fls_LengthType Fls_u32MaxRead;
+/**
+ * @brief Maximum number of bytes to write in one cycle of Fls_MainFunction
+ */
+static Fls_LengthType Fls_u32MaxWrite;
+/**
+ * @brief Result of last flash module job
+ * @implements Fls_eJobResult_Object
+ */
+static MemIf_JobResultType Fls_eJobResult;
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+/**
+ * @brief Pointer to current position in source data buffer
+ * @details Used by both write and compare jobs
+ */
+static const uint8 * Fls_pJobDataSrcPtr;
+/**
+ * @brief Pointer to current position in target data buffer
+ * @details Used only by read job
+ */
+static uint8 * Fls_pJobDataDestPtr;
+/**
+ * @brief Indicates that new job has been accepted
+ * @details Used by all types of job
+ */
+static uint8 Fls_u8JobStart;
+
+
+#define FLS_STOP_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+/**
+ * @brief Pointer to current flash module configuration set
+ * @implements Fls_u32AccCRCremainder_Object
+ */
+static uint32 Fls_u32AccCRCremainder;
+
+#define FLS_STOP_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+/*==================================================================================================
+                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+#define FLS_START_SEC_CONST_32
+#include "Fls_MemMap.h"
+
+/* Start Position and Size of erase access code in flash */
+extern const uint32 Fls_ACEraseRomStart[];
+extern const uint32 Fls_ACEraseSize[];
+
+/* Start Position and Size of write access code in flash */
+extern const uint32 Fls_ACWriteRomStart[];
+extern const uint32 Fls_ACWriteSize[];
+
+#define FLS_STOP_SEC_CONST_32
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+
+/* Block of ACErase function address */
+static Fls_BlockNumberOfSectorType  FLs_u8blockAcErase;
+/* Block of ACWrite function address */
+static Fls_BlockNumberOfSectorType  FLs_u8blockAcWrite;
+
+#define FLS_STOP_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+
+
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+static Fls_SectorIndexType Fls_GetSectorIndexByAddr(const Fls_AddressType u32TargetAddress);
+static Fls_AddressType Fls_GetSectorStartAddr(const Fls_SectorIndexType u32SectorIndex );
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+static boolean Fls_IsAddrPageAligned( const Fls_AddressType u32TargetAddress );
+static boolean Fls_IsAddrPageStartAligned( const Fls_AddressType u32TargetAddress );
+static boolean Fls_IsAddrPageEndAligned( const Fls_AddressType u32TargetAddress );
+static boolean Fls_IsAddrSectorStartAligned( const Fls_AddressType u32TargetAddress );
+static boolean Fls_IsAddrSectorEndAligned( const Fls_AddressType u32TargetAddress );
+static Std_ReturnType CheckInputParamReadCompareJob( Fls_AddressType u32SourceAddress,
+                                                     const uint8 * pTargetAddressPtr,
+                                                     Fls_LengthType u32Length,
+                                                     uint8 ApiId
+                                                   );
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+static boolean Fls_IsAddrWordAligned( const Fls_AddressType u32TargetAddress );
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+#endif /* #if ( FLS_DEV_ERROR_DETECT == STD_ON ) */
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+static void Fls_LoadAc( const Fls_JobType eJob );
+static void Fls_UnloadAc( const Fls_JobType eJob );
+static inline void Fls_CheckLoadAc(Fls_BlockNumberOfSectorType blockAc);
+static inline void Fls_CheckUnLoadAc(void);
+#endif
+static void Fls_AccumulateCRC( uint32 u32InputData );
+static void Fls_ResetCRC( void );
+static uint32 Fls_FinalizeCRC( void );
+static void Fls_UpdateCRCreminder( Fls_CrcDataSizeType eDataSize );
+
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+static void Fls_AccumulateCRC_Qspi_paFlashCfg(void);
+static void Fls_AccumulateCRC_Qspi_paQspiUnitCfg(void);
+static void Fls_AccumulateCRC_Qspi_eraseSettings(const Qspi_Ip_EraseConfigType *eraseSettings);
+static void Fls_AccumulateCRC_Qspi_initConfiguration(const Qspi_Ip_InitConfigType *initConfiguration);
+#endif /*#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)*/
+
+static Fls_CrcType  Fls_CalcCfgCRC( void );
+static MemIf_JobResultType  Fls_DoJobErase( void );
+static Fls_AddressType Fls_CalcMaxTransferAddrEnd( const Fls_LengthType u32MaxTransfer );
+static Fls_AddressType Fls_CalcSectorTransferOffset( void );
+static Fls_AddressType Fls_CalcSectorTransferLength( const Fls_AddressType u32MaxTransferEndAddr );
+static Fls_LLDReturnType Fls_DoJobWrite(const Fls_AddressType u32SectorOffset,
+                                        const Fls_AddressType u32Length
+                                       );
+
+static Fls_LLDReturnType Fls_ProcessJobDataTransfer(const Fls_AddressType u32SectorOffset,
+                                                    const Fls_AddressType u32Length
+                                                   );
+static MemIf_JobResultType Fls_DoJobDataTransfer(const Fls_LengthType u32MaxTransfer);
+static MemIf_JobResultType Fls_ProcessRequestedJobs( void );
+
+
+static MemIf_JobResultType Fls_LLDGetJobResult( void );
+static void Fls_LLDClrJobResult( void );
+
+static inline void Fls_MainFunction_CheckJobResult(MemIf_JobResultType eWorkResult);
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+/**
+ * @brief        Maps u32TargetAddress to sector index
+ *
+ * @details      Calculate index of logical sector u32TargetAddress belongs to
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       Zero based index of logical sector
+ * @retval       0 .. (Fls_pConfigPtr->u32SectorCount - 1)
+ *
+ * @pre          The module must be initialized
+ * @pre          u32TargetAddress must be in configured flash boundary
+ *
+ */
+static Fls_SectorIndexType Fls_GetSectorIndexByAddr( const Fls_AddressType u32TargetAddress )
+{
+    Fls_SectorIndexType u32SectorIndex;
+
+    for ( u32SectorIndex = 0U; u32SectorIndex < Fls_pConfigPtr->u32SectorCount;
+         u32SectorIndex++
+        )
+    {
+        if ( u32TargetAddress <= (*(Fls_pConfigPtr->paSectorEndAddr))[u32SectorIndex] )
+        {
+            /* u32TargetAddress belongs to sector with index u32SectorIndex */
+            break;
+        }
+        else
+        {
+            /* Check next sector */
+        }
+    }
+
+    return u32SectorIndex;
+}
+
+/**
+ * @brief        Return start address of given sector
+ *
+ * @details      Calculate start address (in linear space) of logical sector
+ *               specified by the u32SectorIndex parameter
+ *
+ * @param[in]    u32SectorIndex Index of logical sector
+ *
+ * @return       Start address of u32SectorIndex sector
+ * @retval       0 .. (FLS_TOTAL_SIZE - 1)
+ *
+ * @pre          The module must be initialized
+ * @pre          u32SectorIndex must be in range 0 .. (Fls_pConfigPtr->u32SectorCount - 1)
+ *
+ */
+static Fls_AddressType Fls_GetSectorStartAddr( const Fls_SectorIndexType u32SectorIndex )
+{
+    Fls_AddressType u32TargetAddress = 0U;
+
+    if ( 0U != u32SectorIndex )
+    {
+        u32TargetAddress = (*(Fls_pConfigPtr->paSectorEndAddr))[u32SectorIndex - 1U] + 1U;
+    }
+    else
+    {
+        /* First sector starts with address 0 */
+    }
+
+    return u32TargetAddress;
+}
+
+/**
+ * @brief        Check whether u32TargetAddress is page aligned
+ *
+ * @details      Check whether u32TargetAddress is integer multiple of Flash Page Size
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is page aligned
+ * @retval       FALSE u32TargetAddress is not page aligned
+ *
+ */
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+static boolean Fls_IsAddrPageAligned(const Fls_AddressType u32TargetAddress)
+{
+    boolean bRetVal = (boolean)FALSE;
+
+    /* Aligned to Double Word or Word depending if CODE/DATA Flash or DFO */
+    if (0U == (u32TargetAddress % (*(Fls_pConfigPtr->paSectorPageSize))[Fls_GetSectorIndexByAddr(u32TargetAddress)]))
+    {
+        bRetVal = (boolean)TRUE;
+    }
+    else
+    {
+        /* u32TargetAddress is not page aligned */
+    }
+
+    return( bRetVal );
+}
+
+/**
+ * @brief        Check whether u32TargetAddress is page start aligned
+ *
+ * @details      Check whether u32TargetAddress is in range and aligned to first
+ *               byte of flash page
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is in range and aligned to start of the page
+ * @retval       FALSE u32TargetAddress is not in range or aligned to start of the page
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static boolean Fls_IsAddrPageStartAligned( const Fls_AddressType u32TargetAddress )
+{
+    boolean bRetVal = (boolean)FALSE;
+
+    if (( u32TargetAddress < (Fls_AddressType)FLS_TOTAL_SIZE ) &&
+        ( (boolean)TRUE == Fls_IsAddrPageAligned( u32TargetAddress ) ) \
+       )
+    {
+        bRetVal = (boolean)TRUE;
+    }
+    else
+    {
+        /* u32TargetAddress is not in range or aligned to start of the page */
+    }
+
+    return( bRetVal );
+}
+
+/**
+ * @brief        Check whether u32TargetAddress is page start aligned
+ *
+ * @details      Check whether u32Length is in range and aligned to
+ *               flash page
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ * @param[in]    u32Length size of current write
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is in range and aligned to end of the page
+ * @retval       FALSE u32TargetAddress is not in range or aligned to end of the page
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static boolean Fls_IsAddrPageEndAligned(const Fls_AddressType u32TargetAddress)
+{
+    boolean bRetVal = (boolean)FALSE;
+    Fls_LengthType u32SectorOffset;
+
+    /* Calculate offset in the last sector of current operation */
+    u32SectorOffset = u32TargetAddress - Fls_GetSectorStartAddr(Fls_GetSectorIndexByAddr(u32TargetAddress));
+
+    if (((u32TargetAddress - 1U) < (Fls_AddressType)FLS_TOTAL_SIZE ) &&
+       (0U == (u32SectorOffset % (*(Fls_pConfigPtr->paSectorPageSize))[Fls_GetSectorIndexByAddr(u32TargetAddress)]))
+       )
+    {
+        bRetVal = (boolean)TRUE;
+    }
+    else
+    {
+        /* u32TargetAddress is not in range or aligned to end of the page */
+    }
+
+    return( bRetVal );
+}
+
+
+/**
+ * @brief        Check whether u32TargetAddress is sector start aligned
+ *
+ * @details      Check whether u32TargetAddress is in range and aligned to first
+ *               byte of flash sector
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is in range and aligned to start of the sector
+ * @retval       FALSE u32TargetAddress is not in range or not aligned to
+ *               start of the sector
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static boolean Fls_IsAddrSectorStartAligned(const Fls_AddressType u32TargetAddress)
+{
+    boolean bRetVal = (boolean)FALSE;
+    Fls_SectorIndexType u32SectorIndex;
+    Fls_LengthType u32SectorSize;
+
+    if ( u32TargetAddress < FLS_TOTAL_SIZE )
+    {
+        u32SectorIndex = Fls_GetSectorIndexByAddr( u32TargetAddress );
+        u32SectorSize = (*(Fls_pConfigPtr->paSectorSize))[u32SectorIndex];
+        if ( ( 0U == ((u32TargetAddress - Fls_GetSectorStartAddr( u32SectorIndex)) % u32SectorSize)))
+        {
+            bRetVal = (boolean)TRUE;
+        }
+        else
+        {
+            /* u32TargetAddress is not in range or
+                not aligned to start of the sector */
+        }
+    }
+
+    return bRetVal;
+}
+
+
+/**
+ * @brief        Check whether u32TargetAddress is sector end aligned
+ *
+ * @details      Check whether u32TargetAddress is in range and aligned to last
+ *               byte of flash sector
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is in range and aligned to end of the sector
+ * @retval       FALSE u32TargetAddress is not in range or not aligned to
+ *               end of the sector
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static boolean Fls_IsAddrSectorEndAligned( const Fls_AddressType u32TargetAddress )
+{
+    boolean bRetVal = (boolean)FALSE;
+    Fls_SectorIndexType u32SectorIndex;
+    Fls_LengthType u32SectorSize;
+    Fls_AddressType u32EndAddress;
+
+    if ( u32TargetAddress < FLS_TOTAL_SIZE )
+    {
+        u32SectorIndex = Fls_GetSectorIndexByAddr( u32TargetAddress );
+        u32SectorSize = (*(Fls_pConfigPtr->paSectorSize))[u32SectorIndex];
+        u32EndAddress = (*(Fls_pConfigPtr->paSectorEndAddr))[u32SectorIndex];
+
+        if ( 0U == (( u32EndAddress - u32TargetAddress ) %  u32SectorSize ) )
+        {
+            bRetVal =  (boolean)TRUE;
+        }
+        else
+        {
+            /* u32TargetAddress is not aligned to end of the sector */
+        }
+    }
+
+    return bRetVal;
+}
+
+static Std_ReturnType CheckInputParamReadCompareJob( Fls_AddressType u32SourceAddress,
+                                                     const uint8 * pTargetAddressPtr,
+                                                     Fls_LengthType u32Length,
+                                                     uint8 ApiId
+                                                   )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    boolean CheckInputTemp = FALSE;
+
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        /* Report Error if Fls_pConfigPtr = NULL_PTR  */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_UNINIT );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( u32SourceAddress >= FLS_TOTAL_SIZE )
+    {
+        /* Report Error if u32SourceAddress is invalid */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_PARAM_ADDRESS );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (( 0U == u32Length ) || ((u32SourceAddress + u32Length) > FLS_TOTAL_SIZE ))
+    {
+        /* Report Error if u32Length is invalid */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_PARAM_LENGTH );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+        CheckInputTemp = TRUE;
+    }
+
+    if (TRUE == CheckInputTemp)
+    {
+        if ( NULL_PTR == pTargetAddressPtr )
+        {
+            /* Report Error if pTargetAddressPtr = NULL_PTR */
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_PARAM_DATA );
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+    #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+        else if ( (boolean)FALSE == Fls_IsAddrWordAligned(u32SourceAddress) )
+        {
+            /* Report Error if u32SourceAddress is not aligned */
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_PARAM_ADDRESS );
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+        else if ( (boolean)FALSE == Fls_IsAddrWordAligned(u32SourceAddress + u32Length) )
+        {
+            /* Report Error if u32SourceAddress + u32Length is not aligned */
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, ApiId, FLS_E_PARAM_LENGTH );
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /*fix misra*/
+        }
+    #endif /* #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+    }
+    else
+    {
+        /*fix misra*/
+    }
+
+    return (u8RetVal);
+}
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+/**
+ * @brief        Check whether u32TargetAddress is word aligned
+ *
+ * @details      If QSPI is available and QSPI sectors are configured and
+ *               if the WordAddresable option is set, check if the address
+ *               is word aligned. For hyperflash memories only even addresses
+ *               are allowed.
+ *
+ * @param[in]    u32TargetAddress Target address in flash memory
+ *
+ * @return       boolean
+ * @retval       TRUE u32TargetAddress is word aligned
+ * @retval       FALSE u32TargetAddress is not word aligned
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static boolean Fls_IsAddrWordAligned( const Fls_AddressType u32TargetAddress )
+{
+    boolean bRetVal = (boolean)TRUE;
+
+#if (FEATURE_QSPI_ADDR_CFG == 1)
+    Fls_SectorIndexType u32TmpJobSectorIt = 0UL;
+    const Qspi_Ip_ControllerConfigType *ctrlCfg;
+    uint32 flashInstance;
+    uint32 controllerNo;
+    uint32 ctrlCfgNo;
+
+    /* Check in case when a bad address is passed */
+    if (FLS_TOTAL_SIZE == u32TargetAddress)
+    {
+        u32TmpJobSectorIt = Fls_pConfigPtr->u32SectorCount - 1U;
+    }
+    else
+    {
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr( u32TargetAddress );
+    }
+
+    /* Get external flash instance */
+    flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[u32TmpJobSectorIt];
+    /* Only apply for external sectors */
+    if (FLS_DEVICE_INSTANCE_INVALID != flashInstance)
+    {
+        /* Get controller configuration */
+        controllerNo = ((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[flashInstance]).qspiInstance;
+        ctrlCfgNo = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiConfig))[controllerNo];
+        ctrlCfg = &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paQspiUnitCfg))[ctrlCfgNo]);
+
+        if ( ((boolean)TRUE == ctrlCfg->wordAddresable) && (0U != (u32TargetAddress % 2U)) )
+        {
+           /* The WordAddresable option is set but the address is not word aligned. */
+           bRetVal = (boolean)FALSE;
+        }
+    }
+#else
+    /*Fix warning: unused variable*/
+    (void)u32TargetAddress;
+#endif
+
+    return bRetVal;
+}
+#endif /* #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+#endif /* FLS_DEV_ERROR_DETECT == STD_ON */
+
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+/**
+ * @brief        Load access code to RAM
+ *
+ * @details      Load erase or write access code to statically
+ *               pre-configured location in RAM
+ *
+ * @param[in]    eJob Type of access code to load. Can be either
+ *               FLS_JOB_ERASE or FLS_JOB_WRITE
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static void Fls_LoadAc( const Fls_JobType eJob )
+{
+    const uint32 * pRomPtr = NULL_PTR;
+    const uint32 * pRomEndPtr = NULL_PTR;
+    uint32 * pRamPtr = NULL_PTR;
+
+    switch ( eJob )
+    {
+        case FLS_JOB_ERASE:
+            pRomPtr = Fls_ACEraseRomStart;
+            pRomEndPtr = &(pRomPtr[(uint32)(Fls_ACEraseSize)]);
+            pRamPtr = (uint32*)((uint32)(Fls_pConfigPtr->acErasePtr));
+            break;
+
+        case FLS_JOB_WRITE:
+            pRomPtr = Fls_ACWriteRomStart;
+            pRomEndPtr = &(pRomPtr[(uint32)(Fls_ACWriteSize)]);
+            pRamPtr = (uint32*)((uint32)(Fls_pConfigPtr->acWritePtr));
+            break;
+
+        default:
+            /* Do nothing - should not happen in Fully Trusted Environment;
+               'default' clause added to fulfil MISRA Rule 15.3 */
+            break;
+    }
+
+    /* Copy erase or write access code to RAM */
+    /* pRomEndPtr is dynamically calculated and might not be multiple of 4U */
+    if (pRamPtr != NULL_PTR)
+    {
+        for (; (uint32)pRomPtr < (uint32)pRomEndPtr; pRomPtr++)
+        {
+            *pRamPtr = *pRomPtr;
+            pRamPtr++;
+        }
+    }
+}
+
+
+/**
+ * @brief        Unload access code to RAM
+ *
+ * @details      Erase write or erase access code from statically
+ *               pre-configured location in RAM. Fills the RAM location
+ *               with FLS_AC_UNLOAD_PATTERN
+ *
+ * @param[in]    eJob Type of access code to unload. Can be either
+ *               FLS_JOB_ERASE or FLS_JOB_WRITE
+ *
+ * @pre          The module must be initialized
+ *
+ */
+static void Fls_UnloadAc( const Fls_JobType eJob )
+{
+    uint32 * pRamPtr = NULL_PTR;
+    const uint32 * pRamEndPtr = NULL_PTR;
+
+    switch ( eJob )
+    {
+        case FLS_JOB_ERASE:
+            pRamPtr = (uint32*)((uint32)(Fls_pConfigPtr->acErasePtr));
+            pRamEndPtr = &(pRamPtr[(uint32)(Fls_ACEraseSize)]);
+            break;
+
+        case FLS_JOB_WRITE:
+            pRamPtr = (uint32*)((uint32)(Fls_pConfigPtr->acWritePtr));
+            pRamEndPtr = &(pRamPtr[(uint32)(Fls_ACWriteSize)]);
+            break;
+
+        default:
+            /* Do nothing - should not happen in Fully Trusted Environment;
+               'default' clause added to fulfil MISRA Rule 15.3 */
+            break;
+    }
+
+    if (pRamPtr != NULL_PTR)
+    {
+        /* Unload (erase) write or erase access code from RAM */
+        for (; (uint32)pRamPtr < (uint32)pRamEndPtr; pRamPtr++)
+        {
+            *pRamPtr = FLS_AC_UNLOAD_PATTERN;
+        }
+    }
+}
+
+static inline void Fls_CheckLoadAc(Fls_BlockNumberOfSectorType blockAc)
+{
+    Fls_HwChType eHwCh;
+
+    /* Get channel type(INTERNAL, QSPI,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+    if (FLS_CH_INTERN == eHwCh)
+    {
+        /* Only load if not in Asynch mode and erare/write to the same block */
+        if ( (*((*(Fls_pConfigPtr->pSectorList))[Fls_u32JobSectorIt])).blockNumberOfSector == blockAc )
+        {
+            /* Load position independent access code to RAM */
+            Fls_LoadAc( Fls_eJob );
+            Fls_bACloaded = (boolean)TRUE;
+
+#if (STD_ON == FLS_CLEAN_CACHE_AFTER_LOAD_AC)
+            if (FLS_JOB_ERASE == Fls_eJob)
+            {
+                /* Clean cache after loading to sync with RAM for Erase job */
+                Cache_Ip_CleanByAddr(CACHE_IP_ALL, TRUE, (uint32)Fls_pConfigPtr->acErasePtr, ((uint32)Fls_ACEraseSize * 4U));
+            }
+            else
+            {
+                /* Clean cache after loading to sync with RAM for Write job */
+                Cache_Ip_CleanByAddr(CACHE_IP_ALL, TRUE, (uint32)Fls_pConfigPtr->acWritePtr, ((uint32)Fls_ACWriteSize * 4U));
+            }
+#endif /* FLS_SUPPORT_CACHE_FEATURE */
+        }
+    }
+}
+
+
+static inline void Fls_CheckUnLoadAc(void)
+{
+    /* If the access code was loaded */
+    if (TRUE == Fls_bACloaded)
+    {
+        /* Unload from RAM */
+        Fls_UnloadAc( Fls_eJob );
+        /* Mask the status as unloaded */
+        Fls_bACloaded = (boolean)FALSE;
+    }
+}
+#endif /* FLS_AC_LOAD_ON_JOB_START */
+
+/**
+ * @brief        Erase one complete flash sector
+ *
+ * @details      Call low level flash driver service
+ *               to erase one complete flash sector specified by the Fls_u32JobSectorIt
+ *               internal job variable
+ *
+ * @return       MemIf_JobResultType
+ * @retval       MEMIF_JOB_OK erase operation succeeded and there
+ *               is no more sectors to erase
+ * @retval       MEMIF_JOB_PENDING erase operation succeeded and there
+ *               is still one or more sectors to erase
+ * @retval       MEMIF_JOB_FAILED operation failed due to hardware error
+ *
+ * @param[in]    Job Type of access code to unload. Can be either
+ *               FLS_JOB_ERASE or FLS_JOB_WRITE
+ *
+ * @pre          The module must be initialized, the Fls_u32JobSectorIt internal
+ *               job variable must contain index of logical sector to be erased, and
+ *               Fls_u32JobSectorEnd must contain index of last logical sector to be erased
+ *
+ * @post         increments the Fls_u32JobSectorIt internal job variable
+ *
+ *
+ */
+static MemIf_JobResultType  Fls_DoJobErase( void )
+{
+    MemIf_JobResultType eRetVal = MEMIF_JOB_PENDING;
+    uint32 u32Datastore;
+    Fls_LengthType u32PhysicalSectorSize;
+    Fls_AddressType u32SectorTransferOffset;
+
+    if ( Fls_u32JobAddrIt > Fls_u32JobAddrEnd )
+    {
+        /* No more sectors to erase */
+        eRetVal = MEMIF_JOB_OK;
+    }
+    else
+    {
+        boolean bAsynch;
+        Fls_LLDReturnType eLldRetVal;
+
+        /* Get the Fls_IPW_SectorErase function operation mode */
+        if ( 0U != ((*(Fls_pConfigPtr->paSectorFlags))[Fls_u32JobSectorIt] &
+                   (FLS_SECTOR_ERASE_ASYNCH)
+                  )
+          )
+        {
+            /* The sector write is performed in an asynchronous manner, it is ASYNC mode. */
+            bAsynch = (boolean)TRUE;
+        }
+        else
+        {
+            /* The sector write is SYNC */
+            bAsynch = (boolean)FALSE;
+#if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+            Fls_CheckLoadAc(FLs_u8blockAcErase);
+#endif /* #if (STD_ON == FLS_AC_LOAD_ON_JOB_START) */
+        }
+
+        /* Get size of the physical sector */
+        u32PhysicalSectorSize = (*(Fls_pConfigPtr->paSectorSize))[Fls_u32JobSectorIt];
+        /* Calculate offset of the sector inside sector group */
+        u32SectorTransferOffset = Fls_CalcSectorTransferOffset();
+        /* Update the Fls_JobAddressIt iterator */
+        Fls_u32JobAddrIt += u32PhysicalSectorSize;
+
+        eLldRetVal = Fls_IPW_SectorErase( u32SectorTransferOffset , u32PhysicalSectorSize, bAsynch );
+
+        if (( Fls_u32JobAddrIt > Fls_u32JobAddrEnd ) && ( FLASH_E_OK == eLldRetVal ))
+        {
+            eRetVal = MEMIF_JOB_OK;
+        }
+        else if (FLASH_E_FAILED == eLldRetVal)
+        {
+            (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_ERASE_FAILED);
+            eRetVal = MEMIF_JOB_FAILED;
+        }
+        else
+        {
+            /* The erase operation is either:
+                1. For ASYNCHRONOUS operation: pending (FLASH_E_PENDING) in hardware, or
+                2. For SYNCHRONOUS operation: finished (FLASH_E_OK) and there are more sectors to erase.
+
+                1. If the operation is Async, than the sector is increased in
+                   Fls_IPW_LLDMainFunction()(for Async erase).
+                   when completing the job.
+                2. If the operation is Sync erase, than the sector is increased below because the job is complete.
+            */
+            u32Datastore = (*(Fls_pConfigPtr->paSectorFlags))[Fls_u32JobSectorIt];
+            if ( 0U == ( u32Datastore & FLS_SECTOR_ERASE_ASYNCH) )
+            {
+                if ((Fls_u32JobAddrIt > ((*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt])))
+                {
+                    Fls_u32JobSectorIt++;
+                }
+            }
+        }
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+        Fls_CheckUnLoadAc();
+#endif /* #if (STD_ON == FLS_AC_LOAD_ON_JOB_START) */
+    }
+
+    return( eRetVal );
+}
+
+/**
+ * @brief       Calculate last logical address to read, write, or compare
+ *              from in current cycle of Fls_MainFunction
+ *
+ * @details      Calculate last logical address of Fls_DoJobDataTransfer
+ *               loop to limit number of bytes transferred to/from flash memory
+ *               in one cycle of Fls_MainFunction
+ *
+ * @return       Fls_AddressType
+ * @retval       0 .. (FLS_TOTAL_SIZE - 1)
+ *
+ * @param[in]    u32MaxTransfer Maximum number of bytes to read, write, or compare
+ *               in current cycle of Fls_MainFunction
+ *
+ * @pre          Fls_u32JobAddrIt must contain current, and Fls_u32JobAddrEnd last
+ *               logical address of current job
+ *
+ */
+static Fls_AddressType Fls_CalcMaxTransferAddrEnd( const Fls_LengthType u32MaxTransfer )
+{
+    Fls_AddressType u32MaxTransferEndAddr = Fls_u32JobAddrEnd;
+
+    /* Adjust the u32MaxTransferEndAddr address to transfer only
+        the u32MaxTransfer bytes in one Fls_MainFunction() call */
+    if ( u32MaxTransferEndAddr >= (Fls_u32JobAddrIt + u32MaxTransfer) )
+    {
+        u32MaxTransferEndAddr = (Fls_u32JobAddrIt + u32MaxTransfer) - 1U;
+    }
+    else
+    {
+        /* No adjustment is necessary. Job will finish in this cycle
+            of Fls_MainFunction */
+    }
+
+    return( u32MaxTransferEndAddr );
+}
+
+/**
+ * @brief       Calculate sector offset to read, write, or compare
+ *              from current sector
+ *
+ * @details      Calculate sector offset in bytes for low-level driver
+ *               services
+ *
+ * @return       Fls_AddressType
+ * @retval      0 .. (FLS_SECTOR_SIZE - 1)
+ *
+ * @pre         The module must be initialized, Fls_u32JobSectorIt internal job
+ *              variable must contain index of current logical sector,
+ *              Fls_u32JobAddrIt must contain current logical address
+ *
+ */
+static Fls_AddressType Fls_CalcSectorTransferOffset( void )
+{
+    Fls_AddressType u32SectorAddrStart;
+
+    /* Get first address of Fls_u32JobSectorIt sector */
+    u32SectorAddrStart = Fls_GetSectorStartAddr( Fls_u32JobSectorIt );
+
+    /* Calculate the sector offset */
+    return( Fls_u32JobAddrIt - u32SectorAddrStart );
+}
+
+
+/**
+ * @brief       Calculate number of bytes to read, write, or compare
+ *              from current sector
+ *
+ * @details      Calculate sector transfer length for low-level driver
+ *               services
+ *
+ * @param[in]    u32MaxTransferEndAddr Last address to read, write,
+ *               or compare data from in this cycle of Fls_MainFunction
+ *
+ * @return      Fls_AddressType
+ * @retval      0 .. (FLS_SECTOR_SIZE - 1)
+ *
+ * @pre        The module must be initialized, Fls_u32JobSectorIt internal job
+ *             variable must contain index of current logical sector,
+ *             Fls_u32JobAddrIt must contain current logical address, and
+ *             u32MaxTransferEndAddr must be >= Fls_u32JobAddrIt and lie within
+ *             the specified lower and upper flash address boundaries
+ *
+ */
+static Fls_AddressType Fls_CalcSectorTransferLength( const Fls_AddressType u32MaxTransferEndAddr )
+{
+    Fls_AddressType u32SectorEndAddr;
+    Fls_AddressType u32MaxTransferAddr = u32MaxTransferEndAddr;
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    uint32 u32TransferSize = 0U;
+    uint32 u32InterfaceSize = 0U;
+#endif
+
+    /* Get last address of Fls_u32JobSectorIt sector */
+    u32SectorEndAddr = (*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt];
+
+    /* Adjust u32SectorEndAddr based on hardware implementation */
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    if ((FLS_CH_INTERN == (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt]) && (FLS_JOB_WRITE == Fls_eJob))
+    {
+        u32InterfaceSize = FLS_INTERNAL_WRITE_SIZE;
+
+        u32TransferSize = u32MaxTransferAddr - Fls_u32JobAddrIt + 1U;
+        if (u32TransferSize > (u32InterfaceSize - (Fls_u32JobAddrIt % u32InterfaceSize)))
+        {
+            u32MaxTransferAddr = (Fls_u32JobAddrIt + (u32InterfaceSize - (Fls_u32JobAddrIt % u32InterfaceSize))) - 1U;
+        }
+    }
+#endif
+    /* Adjust the u32SectorEndAddr according to max number of bytes to transfer
+        during one cycle of Fls_MainFunction */
+    if ( u32SectorEndAddr > u32MaxTransferAddr )
+    {
+        u32SectorEndAddr = u32MaxTransferAddr;
+    }
+    else
+    {
+        /* No adjustment is necessary. There is more sectors to transfer */
+    }
+
+    /* Calculate number of bytes to read from the sector */
+    return(( u32SectorEndAddr - Fls_u32JobAddrIt ) + 1U );
+}
+
+/**
+ * @brief        Write up to one physical flash sector
+ *
+ * @details      Call low level flash driver service to write given number of bytes
+ *               at given sector offset
+ *
+ * @param[in]    u32SectorOffset Flash sector offset to write data from
+ * @param[in]    Length Number of bytes to read
+ *
+ * @return       Fls_LLDReturnType
+ * @retval       FLASH_E_OK write operation succeeded
+ * @retval       FLASH_E_FAILED write operation failed due to a hardware error
+ *
+ * @pre          The module must be initialized, the Fls_u32JobSectorIt internal job
+ *               variable must contain valid index of logical sector to write,
+ *               u32SectorOffset and u32Length must be in physical sector boundary and page
+ *               aligned, Fls_pJobDataSrcPtr internal job variable must point to data
+ *               write buffer
+ *
+ */
+static Fls_LLDReturnType Fls_DoJobWrite(const Fls_AddressType u32SectorOffset,
+                                        const Fls_AddressType u32Length
+                                       )
+{
+    Fls_LLDReturnType eRetVal;
+    boolean bAsynch;
+
+    /* Get the Fls_IPW_SectorWrite function operation mode */
+    if ( 0U != ((*(Fls_pConfigPtr->paSectorFlags))[Fls_u32JobSectorIt] & \
+                (FLS_PAGE_WRITE_ASYNCH) \
+              )
+      )
+    {
+        /* The sector write is performed in an asynchronous manner, it is ASYNC */
+        bAsynch = (boolean)TRUE;
+    }
+    else
+    {
+        /* The sector write is SYNC*/
+        bAsynch = (boolean)FALSE;
+#if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+        Fls_CheckLoadAc(FLs_u8blockAcWrite);
+#endif /* #if (STD_ON == FLS_AC_LOAD_ON_JOB_START) */
+    }
+
+    eRetVal = Fls_IPW_SectorWrite( u32SectorOffset, u32Length, Fls_pJobDataSrcPtr, bAsynch );
+
+    if ( FLASH_E_FAILED == eRetVal )
+    {
+        /* An error will be reported */
+        (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_WRITE_FAILED);
+    }
+#if ( (FLS_ERASE_VERIFICATION_ENABLED == STD_ON) || (FLS_WRITE_VERIFICATION_ENABLED == STD_ON) )
+    /* A verification has been failed, convert to FLASH_E_FAILED */
+    else if (FLASH_E_BLOCK_INCONSISTENT == eRetVal)
+    {
+        eRetVal = FLASH_E_FAILED;
+    }
+    else
+    {
+        ; /* empty else at the end of an else-if structure */
+    }
+#endif /* (FLS_ERASE_VERIFICATION_ENABLED == STD_ON) || (FLS_WRITE_VERIFICATION_ENABLED == STD_ON) */
+
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+    Fls_CheckUnLoadAc();
+#endif /* #if (STD_ON == FLS_AC_LOAD_ON_JOB_START) */
+    return( eRetVal );
+}
+
+static Fls_LLDReturnType Fls_ProcessJobDataTransfer(const Fls_AddressType u32SectorOffset,
+                                                    const Fls_AddressType u32Length
+                                                   )
+{
+    Fls_LLDReturnType eTransferRetVal = FLASH_E_FAILED;
+
+    /* Call Low-level driver to transfer data to/from physical flash device */
+    switch ( Fls_eJob )
+    {
+        case FLS_JOB_WRITE:
+            eTransferRetVal =  Fls_DoJobWrite( u32SectorOffset, u32Length );
+            /* Update the source data pointer for next write */
+            Fls_pJobDataSrcPtr = &(Fls_pJobDataSrcPtr[u32Length]);
+            break;
+        case FLS_JOB_READ:
+            eTransferRetVal =  Fls_IPW_SectorRead(u32SectorOffset, u32Length, Fls_pJobDataDestPtr, NULL_PTR);
+            if ( FLASH_E_FAILED == eTransferRetVal )
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_READ_FAILED);
+            }
+            /* Update the destination data pointer for next read */
+            Fls_pJobDataDestPtr = &(Fls_pJobDataDestPtr[u32Length]);
+            break;
+#if ( FLS_COMPARE_API == STD_ON )
+        case FLS_JOB_COMPARE:
+            eTransferRetVal =  Fls_IPW_SectorRead(u32SectorOffset, u32Length, NULL_PTR, Fls_pJobDataSrcPtr);
+            if ((FLASH_E_BLOCK_INCONSISTENT == eTransferRetVal) || (FLASH_E_FAILED == eTransferRetVal))
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_COMPARE_FAILED);
+            }
+            /* Update the source data pointer for next compare */
+            Fls_pJobDataSrcPtr = &(Fls_pJobDataSrcPtr[u32Length]);
+            break;
+#endif /* FLS_COMPARE_API == STD_ON */
+#if ( FLS_BLANK_CHECK_API == STD_ON )
+        case FLS_JOB_BLANK_CHECK:
+            eTransferRetVal =  Fls_IPW_SectorRead(u32SectorOffset, u32Length, NULL_PTR, NULL_PTR);
+            if ( FLASH_E_FAILED == eTransferRetVal )
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_COMPARE_FAILED);
+            }
+            break;
+#endif /* FLS_BLANK_CHECK_API == STD_ON */
+        default:
+            ; /* Do nothing - should not happen in Fully Trusted Environment;
+            "default" clause added to fulfil MISRA Rule 15.3 */
+            break;
+    }
+    return eTransferRetVal;
+}
+/**
+    @brief Read, write, or compare flash data
+    @details Call Fls_ProcessJobDataTransfer function to read, write,
+        or compare flash data. The functions ensures that only pre-configured
+        maximum number of bytes is read, written, or compared during
+        one cycle of the Fls_MainFunction call
+
+    @return MemIf_JobResultType
+    @retval MEMIF_JOB_OK read, write, or compare operation succeeded and there
+        is no more data to read, write, or compare
+    @retval MEMIF_JOB_PENDING read, write, or compare operation succeeded
+        and there is still some data to read, write, or compare
+    @retval MEMIF_JOB_FAILED read, write, or compare operation failed due
+        to a hardware error
+    @retval MEMIF_BLOCK_INCONSISTENT Compared data from a flash compare
+        eJob are not equal
+
+    @pre The module must be initialized, the Fls_u32JobSectorIt internal
+        eJob variable must contain index of logical sector to read, write,
+        or compare, the Fls_u32JobAddrIt must contain logical address to read,
+        write or compare, and Fls_u32JobAddrEnd must contain last address to read,
+        write or compare.
+
+    @post Updates the Fls_u32JobSectorIt, Fls_pJobDataSrcPtr, Fls_pJobDataDestPtr,
+        and Fls_u32JobAddrIt internal eJob variables
+ */
+static MemIf_JobResultType Fls_DoJobDataTransfer(const Fls_LengthType u32MaxTransfer)
+{
+    MemIf_JobResultType eRetVal = MEMIF_JOB_PENDING;
+
+    /* No more data to write */
+    if ( Fls_u32JobAddrIt > Fls_u32JobAddrEnd )
+    {
+        eRetVal = MEMIF_JOB_OK;
+    }
+    else
+    {
+        Fls_AddressType u32MaxTransferAddrEnd;
+        Fls_LLDReturnType eTransferRetVal;
+
+        /* Last address to transfer data to/from in this call of the Fls_MainFunction() functions */
+        u32MaxTransferAddrEnd = Fls_CalcMaxTransferAddrEnd( u32MaxTransfer );
+
+        /* Transfer sector by sector until the u32MaxTransferAddrEnd address is reached or error is detected */
+        do
+        {
+            Fls_AddressType u32SectorTransferOffset;
+            Fls_AddressType u32SectorTransferLength;
+
+            /* Calculate offset and length of the sector data transfer */
+            u32SectorTransferOffset = Fls_CalcSectorTransferOffset();
+            u32SectorTransferLength = Fls_CalcSectorTransferLength( u32MaxTransferAddrEnd );
+
+            /* Update the Fls_JobAddressIt iterator.*/
+            Fls_u32JobAddrIt += u32SectorTransferLength;
+
+            /* Call Low-level driver to transfer data to/from physical flash device */
+            eTransferRetVal = Fls_ProcessJobDataTransfer(u32SectorTransferOffset, u32SectorTransferLength);
+
+            if ( FLASH_E_OK == eTransferRetVal ) /* If the previous(SYNC job) has finished successfully */
+            {
+                if ( (Fls_u32JobAddrIt > (*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt]))
+                {
+                    /* Move on to the next sector */
+                    Fls_u32JobSectorIt++;
+                }
+            }
+        }
+        while (( Fls_u32JobAddrIt <= u32MaxTransferAddrEnd ) &&
+               ( FLASH_E_OK == eTransferRetVal )
+              );
+
+
+        if ( FLASH_E_FAILED == eTransferRetVal )
+        {
+            eRetVal = MEMIF_JOB_FAILED;
+        }
+        else if ( FLASH_E_BLOCK_INCONSISTENT == eTransferRetVal )
+        {
+            /* compare job only */
+            eRetVal = MEMIF_BLOCK_INCONSISTENT;
+        }
+        else if (( Fls_u32JobAddrIt > Fls_u32JobAddrEnd ) &&
+                 ( FLASH_E_OK == eTransferRetVal )
+                )
+        {
+            /* All desired job data has been successfully transferred */
+            eRetVal = MEMIF_JOB_OK;
+        }
+        else
+        {
+            ; /* The write operation is either pending (FLASH_E_PENDING)
+            in hardware in case of asynchronous operation or
+            finished (FLASH_E_OK) in case of synchronous operation
+            and there is more pages to write */
+        }
+    }
+
+    return( eRetVal );
+}
+
+/**
+ * @brief        Function to handle cumulative CRC calculation over input data.
+ *
+ * @details      Handles cumulative CRC calculation over input 32-bit data, .
+ *
+ * @param[in]    inputData ... data to be CRC-ed
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Fls_ResetCRC() was executed before the first call of
+ *               Fls_AccumulateCRC().
+ *
+ *
+ */
+static void Fls_AccumulateCRC(uint32 u32InputData)
+{
+
+    if (0xFFFFU < u32InputData)
+    {
+        /* preparation for accumulation of higher 16 bits of the u32InputData */
+        Fls_u32AccCRCremainder = (Fls_u32AccCRCremainder << 16U) | (u32InputData >> 16U);
+        /* make 16-bit accumulated result (in lower 16-bits of Fls_u32AccCRCremainder) */
+        Fls_UpdateCRCreminder(FLS_CRC_16_BITS);
+    }
+
+    if (0xFFU < u32InputData)
+    {
+        /* preparation for accumulation of lower 16 bits of the u32InputData */
+        Fls_u32AccCRCremainder = (Fls_u32AccCRCremainder << 16U) | (u32InputData & 0x0000FFFFU);
+        /* make 16-bit accumulated result (in lower 16-bits of Fls_u32AccCRCremainder) */
+        Fls_UpdateCRCreminder(FLS_CRC_16_BITS);
+    }
+    else
+    {
+        /* optimization: only 8 LSB bits are processed */
+        /* preparation for accumulation of lower 8 bits of the u32InputData */
+        Fls_u32AccCRCremainder = (Fls_u32AccCRCremainder << 8U) | u32InputData;
+        /* make 16-bit accumulated result (in lower 16-bits of Fls_u32AccCRCremainder) */
+        Fls_UpdateCRCreminder(FLS_CRC_8_BITS);
+    }
+
+    return;
+}
+
+
+/**
+ * @brief        Function to reset CRC calculation.
+ *
+ * @details      Resets accumulated Fls_u32AccCRCremainder.
+ *
+ * @param[in]    void
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          None.
+ *
+ *
+ */
+static void Fls_ResetCRC ( void )
+{
+    Fls_u32AccCRCremainder = 0U;
+}
+
+/**
+ * @brief        Function to finalize CRC calculation.
+ *
+ * @details      Finalizes accumulated CRC computation and resturns the final
+ *               CRC checksum.
+ *
+ * @param[in]    void
+ *
+ * @return       uint32
+ * @retval       The final CRC checksum in the lower 16 bits.
+ *
+ * @pre          Fls_AccumulateCRC() was executed at least once before
+ *               calling Fls_FinalizeCRC().
+ *
+ */
+static uint32 Fls_FinalizeCRC ( void )
+{
+    /* add the final 0x0000 to the remainder */
+    Fls_u32AccCRCremainder = (Fls_u32AccCRCremainder << 16U);
+    /* make the final 16-bit CRC */
+    Fls_UpdateCRCreminder(FLS_CRC_16_BITS);
+
+    return (Fls_u32AccCRCremainder);
+}
+
+/**
+ * @brief        Function to perform CRC calculation over input 32-bit data.
+ *
+ * @details      Process 32-bit data to 16-bit reminder.
+ *
+ * @param[in]    accDataPtr ... ptr to data to be processed
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Can be called only from Fls_AccumulateCRC().
+ *
+ */
+
+static void Fls_UpdateCRCreminder(Fls_CrcDataSizeType eDataSize)
+{
+    uint32 u32CrcPolynomSft;
+    uint32 u32LeadingOne;
+    uint32 u32AccDataLoc;
+    uint32 u32LeadingOneInitial;
+
+    switch (eDataSize)
+    {
+        case FLS_CRC_8_BITS:
+            u32CrcPolynomSft = 0x11021U << 7U; /* shifted CRC-16-CCITT (x.25 protocol)*/
+            u32LeadingOneInitial = 0x10000U << 7U;
+            break;
+        case FLS_CRC_16_BITS:
+        default:
+            u32CrcPolynomSft = 0x11021U << 15U; /* shifted CRC-16-CCITT (x.25 protocol)*/
+            u32LeadingOneInitial = 0x10000U << 15U;
+            break;
+    }
+
+    /* copy static variable to auto (computation over static may be slow) */
+    u32AccDataLoc = Fls_u32AccCRCremainder;
+
+    /* CRC computation */
+    for (u32LeadingOne = u32LeadingOneInitial; u32LeadingOne >= 0x00010000U; u32LeadingOne >>= 1U)
+    {
+        if (0U != (u32AccDataLoc & u32LeadingOne))
+        {
+            u32AccDataLoc ^= u32CrcPolynomSft;
+        }
+        u32CrcPolynomSft >>= 1U;
+    }
+
+    /* copy back to static variable */
+    Fls_u32AccCRCremainder = u32AccDataLoc;
+
+    return;
+}
+
+/**
+ * @brief        Calculates CRC over Fls configuration.
+ *
+ * @details      Calculates CRC over selected items of Fls configuration set
+ *               pointed to by ConfigPtr.
+ *
+ * @param[in]    ConfigPtr        Pointer to flash driver configuration set.
+ *
+ * @return       uint32
+ * @retval       0 .. 0xFFFF (16-bit CRC using CRC-16-CCITT polynomial)
+ *
+ * @pre          Fls_pConfigPtr must not be properly initialized.
+ *
+ */
+
+static Fls_CrcType  Fls_CalcCfgCRC( void )
+{
+    Fls_SectorIndexType u32SectorIndex;
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+    uint8 u8IterUnits;
+#endif /*#ifdef (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)*/
+
+    /* Reset the accumulated CRC value */
+    Fls_ResetCRC();
+
+    /* Accumulate the rest of the params (common for all sectors within a config set) */
+    /* CRC - Accumulate eDefaultMode */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->eDefaultMode);
+    /* CRC - Accumulate u32MaxReadFastMode */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->u32MaxReadFastMode );
+    /* CRC - Accumulate u32MaxReadNormalMode */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->u32MaxReadNormalMode);
+    /* CRC - Accumulate u32MaxWriteFastMode */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->u32MaxWriteFastMode);
+    /* CRC - Accumulate u32MaxWriteNormalMode */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->u32MaxWriteNormalMode);
+    /* CRC - Accumulate u32SectorCount */
+    Fls_AccumulateCRC((uint32)Fls_pConfigPtr->u32SectorCount);
+
+    /* Iterate through the sector-dependent params */
+    for ( u32SectorIndex = 0U; u32SectorIndex < Fls_pConfigPtr->u32SectorCount; u32SectorIndex++ )
+    {
+        /* CRC - Accumulate paSectorEndAddr */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->paSectorEndAddr))[u32SectorIndex]);
+        /* CRC - Accumulate paSectorSize */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->paSectorSize))[u32SectorIndex]);
+        /* CRC - Accumulate pSectorList */
+        if (NULL_PTR != (*(Fls_pConfigPtr->pSectorList))[u32SectorIndex])
+        {   /* Accumulate Sector index for internal flash sectors */
+            Fls_AccumulateCRC((uint32)((*((*(Fls_pConfigPtr->pSectorList))[u32SectorIndex])).u32SectorId));
+            /* Accumulate Sector Start Address for internal flash sectors */
+            Fls_AccumulateCRC((uint32)(*((*(Fls_pConfigPtr->pSectorList))[u32SectorIndex])).pSectorStartAddressPtr);
+        }
+        /* CRC - Accumulate paSectorFlags */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->paSectorFlags))[u32SectorIndex]);
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+        /* CRC - Accumulate paHwCh */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->paHwCh))[u32SectorIndex]);
+        /* CRC - Accumulate paSectorHwAddress */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->paSectorHwAddress))[u32SectorIndex]);
+#endif /*#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)*/
+    }
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+    /* CRC - Accumulate u8FlashUnitsCount*/
+    Fls_AccumulateCRC((uint32)(Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashUnitsCount));
+    /* CRC - Accumulate (*paFlashConnectionCfg)[]  */
+    for (u8IterUnits = 0U; u8IterUnits < Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashUnitsCount; u8IterUnits++)
+    {
+        Fls_AccumulateCRC((uint32)((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[u8IterUnits]).qspiInstance);
+        Fls_AccumulateCRC((uint32)((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[u8IterUnits]).connectionType);
+    }
+    /* CRC - Accumulate (*u8FlashConfig)[] */
+    for (u8IterUnits = 0U; u8IterUnits < Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashUnitsCount; u8IterUnits++)
+    {
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashConfig))[u8IterUnits]);
+    }
+    /* CRC - Accumulate u8FlashConfigCount*/
+    Fls_AccumulateCRC((uint32)(Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashConfigCount));
+
+    /* CRC - Accumulate (*paFlashCfg)[] */
+    Fls_AccumulateCRC_Qspi_paFlashCfg();
+    /* CRC - Accumulate u8QspiUnitsCount*/
+    Fls_AccumulateCRC((uint32)(Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiUnitsCount));
+
+                    /* CRC - Accumulate (*u8QspiConfig)[] */
+    for (u8IterUnits = 0U; u8IterUnits < Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiUnitsCount; u8IterUnits++)
+    {
+        /* CRC - Accumulate memSize  */
+        Fls_AccumulateCRC((uint32)(*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiConfig))[u8IterUnits]);
+    }
+
+    /* CRC - Accumulate u8QspiConfigCount */
+    Fls_AccumulateCRC((uint32)(Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiConfigCount));
+    /* CRC - Accumulate (*paQspiUnitCfg)[] */
+    Fls_AccumulateCRC_Qspi_paQspiUnitCfg();
+#endif /*#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)*/
+    return ((Fls_CrcType)Fls_FinalizeCRC());
+}
+
+
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+/**
+ * @brief        Calculates CRC over QSPI paFlashCfg configuration.
+ *
+ * @details      Calculates CRC over paFlashCfg items of Fls QSPI configuration set
+ *               pointed to by ConfigPtr.
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Fls_pConfigPtr must be properly initialized.
+ *
+ */
+static void Fls_AccumulateCRC_Qspi_paFlashCfg(void)
+{
+    uint8 u8IterUnits;
+    const Qspi_Ip_MemoryConfigType * paFlashCfg;
+
+    /* CRC - Accumulate (*paFlashCfg)[] */
+    for (u8IterUnits = 0U; u8IterUnits < Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashConfigCount; u8IterUnits++)
+    {
+        paFlashCfg = &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashCfg))[u8IterUnits]);
+
+        /* CRC - Accumulate memSize  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->memSize );
+        /* CRC - Accumulate pageSize  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->pageSize );
+        /* CRC - Accumulate readLut  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->readLut );
+        /* CRC - Accumulate writeLut  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->writeLut );
+        /* CRC - Accumulate read0xxLut  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->read0xxLut );
+        /* CRC - Accumulate read0xxLutAHB  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->read0xxLutAHB );
+
+        /* CRC - Accumulate readIdSettings.readIdLut  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->readIdSettings.readIdLut );
+        /* CRC - Accumulate readIdSettings.readIdSize  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->readIdSettings.readIdSize );
+        /* CRC - Accumulate readIdSettings.readIdExpected  */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->readIdSettings.readIdExpected );
+
+        /* CRC - Accumulate eraseSettings  */
+        Fls_AccumulateCRC_Qspi_eraseSettings( &(paFlashCfg->eraseSettings) );
+
+                                            /* CRC - Accumulate statusConfig */
+        /* CRC - Accumulate statusRegReadLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.statusRegReadLut );
+        /* CRC - Accumulate statusRegWriteLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.statusRegWriteLut );
+        /* CRC - Accumulate writeEnableSRLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.writeEnableSRLut );
+        /* CRC - Accumulate writeEnableLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.writeEnableLut );
+        /* CRC - Accumulate regSize */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.regSize );
+        /* CRC - Accumulate busyOffset */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.busyOffset );
+        /* CRC - Accumulate busyValue */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.busyValue );
+        /* CRC - Accumulate writeEnableOffset */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.writeEnableOffset );
+        /* CRC - Accumulate blockProtectionOffset */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.blockProtectionOffset );
+        /* CRC - Accumulate blockProtectionWidth */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->statusConfig.blockProtectionWidth );
+
+                                        /* CRC - Accumulate suspendSettings */
+        /* CRC - Accumulate eraseSuspendLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->suspendSettings.eraseSuspendLut );
+        /* CRC - Accumulate eraseResumeLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->suspendSettings.eraseResumeLut );
+        /* CRC - Accumulate programSuspendLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->suspendSettings.programSuspendLut );
+        /* CRC - Accumulate programResumeLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->suspendSettings.programResumeLut );
+
+                                        /* CRC - Accumulate resetSettings */
+        /* CRC - Accumulate resetCmdLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->resetSettings.resetCmdLut );
+        /* CRC - Accumulate resetCmdCount */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->resetSettings.resetCmdCount );
+
+                                        /* CRC - Accumulate initResetSettings */
+        /* CRC - Accumulate resetCmdLut */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->initResetSettings.resetCmdLut );
+        /* CRC - Accumulate resetCmdCount */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->initResetSettings.resetCmdCount );
+
+        /* CRC - Accumulate initConfiguration */
+        Fls_AccumulateCRC_Qspi_initConfiguration( &(paFlashCfg->initConfiguration) );
+
+                                    /* CRC - Accumulate lutSequences */
+        /* CRC - Accumulate opCount */
+        Fls_AccumulateCRC( (uint32)paFlashCfg->lutSequences.opCount );
+    }
+}
+
+/**
+ * @brief        Calculates CRC over QSPI eraseSettings configuration.
+ *
+ * @details      Calculates CRC over eraseSettings items of Fls QSPI configuration set
+ *               pointed to by ConfigPtr.
+ *
+ * @param[in]    u8IterUnits The index of QSPI configuration
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Fls_pConfigPtr must be properly initialized.
+ *
+ */
+static void Fls_AccumulateCRC_Qspi_eraseSettings(const Qspi_Ip_EraseConfigType *eraseSettings)
+{
+    uint8 eraseTypes;
+
+    for (eraseTypes = 0U; eraseTypes < QSPI_IP_ERASE_TYPES; eraseTypes++)
+    {
+        /* CRC - Accumulate eraseLut  */
+        Fls_AccumulateCRC( (uint32)eraseSettings->eraseTypes[eraseTypes].eraseLut );
+        /* CRC - Accumulate Size of the erased area  */
+        Fls_AccumulateCRC( (uint32)eraseSettings->eraseTypes[eraseTypes].size );
+    }
+    /* CRC - Accumulate chipEraseLut  */
+    Fls_AccumulateCRC( (uint32)eraseSettings->chipEraseLut );
+}
+
+/**
+ * @brief        Calculates CRC over QSPI initConfiguration configuration.
+ *
+ * @details      Calculates CRC over eraseSettings items of Fls QSPI configuration set
+ *               pointed to by ConfigPtr.
+ *
+ * @param[in]    u8IterUnits The index of QSPI configuration
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Fls_pConfigPtr must be properly initialized.
+ *
+ */
+static void Fls_AccumulateCRC_Qspi_initConfiguration(const Qspi_Ip_InitConfigType *initConfiguration)
+{
+    uint8 u8IterInstrOpers;
+    const Qspi_Ip_InitOperationType * operation;
+
+    /* CRC - Accumulate opCount */
+    Fls_AccumulateCRC( (uint32)initConfiguration->opCount);
+
+    for (u8IterInstrOpers = 0U; u8IterInstrOpers < initConfiguration->opCount; u8IterInstrOpers++)
+    {
+        operation = &(initConfiguration->operations[u8IterInstrOpers]);
+
+        /* CRC - Accumulate opType */
+        Fls_AccumulateCRC( (uint32)operation->opType );
+        /* CRC - Accumulate command1Lut */
+        Fls_AccumulateCRC( (uint32)operation->command1Lut );
+        /* CRC - Accumulate command2Lut */
+        Fls_AccumulateCRC( (uint32)operation->command2Lut );
+        /* CRC - Accumulate weLut */
+        Fls_AccumulateCRC( (uint32)operation->weLut );
+        /* CRC - Accumulate addr */
+        Fls_AccumulateCRC( (uint32)operation->addr );
+        /* CRC - Accumulate size */
+        Fls_AccumulateCRC( (uint32)operation->size );
+        /* CRC - Accumulate shift */
+        Fls_AccumulateCRC( (uint32)operation->shift );
+        /* CRC - Accumulate width */
+        Fls_AccumulateCRC( (uint32)operation->width );
+        /* CRC - Accumulate value */
+        Fls_AccumulateCRC( (uint32)operation->value );
+    }
+}
+
+
+
+
+/**
+ * @brief        Calculates CRC over QSPI paQspiUnitCfg configuration.
+ *
+ * @details      Calculates CRC over paQspiUnitCfg items of Fls QSPI configuration set
+ *               pointed to by ConfigPtr.
+ *
+ * @param[in]    u8IterUnits The index of QSPI configuration
+ *
+ * @return       void
+ * @retval       None.
+ *
+ * @pre          Fls_pConfigPtr must be properly initialized.
+ *
+ */
+static void Fls_AccumulateCRC_Qspi_paQspiUnitCfg(void)
+{
+    uint8 u8IterUnits;
+    uint8 u8IterAhb;
+    const Qspi_Ip_ControllerConfigType *paQspiUnitCfg;
+
+    /* CRC - Accumulate (*paQspiUnitCfg)[] */
+    for (u8IterUnits = 0U; u8IterUnits < Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiConfigCount; u8IterUnits++)
+    {
+        paQspiUnitCfg = &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paQspiUnitCfg))[u8IterUnits]);
+
+        /* CRC - Accumulate dataRate */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->dataRate) );
+        /* CRC - Accumulate memSizeA1 */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->memSizeA1) );
+        /* CRC - Accumulate memSizeA2 */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->memSizeA2) );
+        /* CRC - Accumulate memSizeB1 */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->memSizeB1) );
+        /* CRC - Accumulate memSizeB2 */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->memSizeB2) );
+        /* CRC - Accumulate csHoldTime */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->csHoldTime) );
+        /* CRC - Accumulate csSetupTime */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->csSetupTime) );
+        /* CRC - Accumulate columnAddr */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->columnAddr) );
+        /* CRC - Accumulate wordAddresable */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->wordAddresable? 1U : 0U) );
+        /* CRC - Accumulate readModeA */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->readModeA) );
+        /* CRC - Accumulate readModeB */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->readModeB) );
+        /* CRC - Accumulate sampleDelay */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->sampleDelay) );
+        /* CRC - Accumulate samplePhase */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->samplePhase) );
+        /* CRC - Accumulate dqsLatency */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->dqsLatency? 1U : 0U) );
+        /* CRC - Accumulate dataAlign */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->dataAlign) );
+        /* CRC - Accumulate io2IdleValueA */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->io2IdleValueA) );
+        /* CRC - Accumulate io3IdleValueA */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->io3IdleValueA) );
+        /* CRC - Accumulate io2IdleValueB */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->io2IdleValueB) );
+        /* CRC - Accumulate io3IdleValueB */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->io3IdleValueB) );
+        for (u8IterAhb = 0U; u8IterAhb < QSPI_IP_AHB_BUFFERS; u8IterAhb++)
+        {
+            /* CRC - Accumulate masters */
+            Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->ahbConfig.masters[u8IterAhb]) );
+        }
+        for (u8IterAhb = 0U; u8IterAhb < QSPI_IP_AHB_BUFFERS; u8IterAhb++)
+        {
+            /* CRC - Accumulate sizes */
+            Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->ahbConfig.sizes[u8IterAhb]) );
+        }
+        /* CRC - Accumulate allMasters */
+        Fls_AccumulateCRC( (uint32)(paQspiUnitCfg->ahbConfig.allMasters? 1U : 0U) );
+    }
+}
+
+#endif /*#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)*/
+
+
+
+/**
+ * @brief   Decides which sub-function to call based on the job type: Modify (Write, Erase) or Read (Read, Compare).
+ **/
+static MemIf_JobResultType Fls_ProcessRequestedJobs( void )
+{
+    MemIf_JobResultType eWorkResult = MEMIF_JOB_OK;
+
+    if ( FLS_JOB_ERASE == Fls_eJob )
+    {
+        /**** MODIFY jobs ****/
+        /* Start current job or start a new batch of current job or verify status of current job. */
+        eWorkResult = Fls_DoJobErase();
+    }
+    else if ( FLS_JOB_WRITE == Fls_eJob )
+    {
+        eWorkResult = Fls_DoJobDataTransfer( Fls_u32MaxWrite );
+    }
+    else
+    {
+        /**** READ jobs ****/
+        /* FLS_JOB_READ, FLS_JOB_BLANK_CHECK and FLS_JOB_COMPARE jobs are always synchronous */
+        eWorkResult = Fls_DoJobDataTransfer( Fls_u32MaxRead );
+    }
+
+    return eWorkResult;
+}
+/*==================================================================================================
+                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+/**
+ * @brief        The function initializes Fls module.
+ * @details      The function sets the internal module variables according to given
+ *               configuration set.
+ *
+ * @param[in]    pConfigPtr        Pointer to flash driver configuration set.
+ *
+ * @api
+ *
+ * @pre          @p pConfigPtr must not be @p NULL_PTR and the module status must not
+ *               be @p MEMIF_BUSY.
+ *
+ * @implements     Fls_Init_Activity
+ *
+ */
+void Fls_Init(const Fls_ConfigType * pConfigPtr)
+{
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+#ifdef FLS_PRECOMPILE_SUPPORT
+    if (NULL_PTR != pConfigPtr)
+#else
+    if (NULL_PTR == pConfigPtr)
+#endif /* FLS_PRECOMPILE_SUPPORT */
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_INIT_ID, FLS_E_PARAM_CONFIG );
+    }
+    else if (MEMIF_JOB_PENDING == Fls_eJobResult)
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_INIT_ID, FLS_E_BUSY );
+    }
+    else
+    {
+#endif /* FLS_DEV_ERROR_DETECT == STD_ON */
+
+    #ifdef FLS_PRECOMPILE_SUPPORT
+       Fls_pConfigPtr = &Fls_Config;
+       (void)pConfigPtr;
+    #else
+       Fls_pConfigPtr = pConfigPtr;
+    #endif /* <DRIVER>_PRECOMPILE_SUPPORT */
+        if (Fls_pConfigPtr->u16ConfigCrc != Fls_CalcCfgCRC())
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_INIT_ID, FLS_E_PARAM_CONFIG );
+#endif /* FLS_DEV_ERROR_DETECT == STD_ON */
+            Fls_pConfigPtr = NULL_PTR;
+            Fls_eJobResult = MEMIF_JOB_FAILED;
+        }
+        else
+        {
+            /* Set the max number of bytes to read/write
+                during Fls_MainFunction call */
+            if (MEMIF_MODE_SLOW == Fls_pConfigPtr->eDefaultMode)
+            {
+                Fls_u32MaxRead = Fls_pConfigPtr->u32MaxReadNormalMode;
+                Fls_u32MaxWrite = Fls_pConfigPtr->u32MaxWriteNormalMode;
+            }
+            else
+            {
+                Fls_u32MaxRead = Fls_pConfigPtr->u32MaxReadFastMode;
+                Fls_u32MaxWrite = Fls_pConfigPtr->u32MaxWriteFastMode;
+            }
+                /* Initialize flash hardware
+                   NOTE: The variable 'Fls_eLLDJobResult' will be updated in the below function*/
+                Fls_IPW_Init();
+
+            if ( MEMIF_JOB_FAILED == Fls_LLDGetJobResult() )
+            {
+                Fls_eJobResult = MEMIF_JOB_FAILED;
+            #if ( FLS_DEV_ERROR_DETECT == STD_ON )
+                Fls_pConfigPtr = NULL_PTR;
+            #endif
+            }
+            else
+            {
+                Fls_eJobResult = MEMIF_JOB_OK;
+            #if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+                /* Get block number of ACWrite/Erase function address */
+                FLs_u8blockAcWrite = Fls_IPW_GetBlockNumberFromAddress((Fls_AddressType)Fls_ACWriteRomStart);
+                FLs_u8blockAcErase = Fls_IPW_GetBlockNumberFromAddress((Fls_AddressType)Fls_ACEraseRomStart);
+            #endif /* #if (STD_ON == FLS_AC_LOAD_ON_JOB_START) */
+            }
+        }
+    #if (FLS_DEV_ERROR_DETECT == STD_ON)
+    }
+    #endif
+}
+
+/**
+ * @brief            Erase one or more complete flash sectors.
+ * @details          Starts an erase job asynchronously. The actual job is performed
+ *                   by the @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress        Target address in flash memory.
+ * @param[in]        u32Length               Number of bytes to erase.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                    Erase command has been accepted.
+ * @retval           E_NOT_OK                Erase command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Erase changes module status and some internal variables
+ *                   (@p Fls_u32JobSectorIt, @p Fls_u32JobSectorEnd, @p Fls_Job,
+ *                   @p Fls_eJobResult).
+ *
+ * @implements       Fls_Erase_Activity
+ *
+ */
+Std_ReturnType Fls_Erase(Fls_AddressType u32TargetAddress,
+                         Fls_LengthType u32Length
+                        )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    Fls_SectorIndexType u32TmpJobSectorIt;
+    Fls_SectorIndexType u32TmpJobSectorEnd;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_ERASE_ID, FLS_E_UNINIT );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( (boolean)FALSE == (Fls_IsAddrSectorStartAligned( (Fls_AddressType)u32TargetAddress )) )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_ERASE_ID, FLS_E_PARAM_ADDRESS );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (( 0U == u32Length ) || ( (boolean)FALSE == (Fls_IsAddrSectorEndAligned(( (Fls_AddressType)u32TargetAddress + u32Length ) - 1U ))) )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_ERASE_ID, FLS_E_PARAM_LENGTH );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+
+        /* Perform calculations outside the critical section in order
+            to limit time spend in the CS */
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr( u32TargetAddress );
+        u32TmpJobSectorEnd = Fls_GetSectorIndexByAddr(( u32TargetAddress + u32Length ) - 1U );
+
+        SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_10();
+
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_ERASE_ID, FLS_E_BUSY );
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+
+            SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_10();
+        }
+        else
+        {
+            /* Configure the erase job */
+            Fls_u32JobSectorIt = u32TmpJobSectorIt;
+            Fls_u32JobSectorEnd = u32TmpJobSectorEnd;
+            Fls_u32JobAddrIt = u32TargetAddress;
+            Fls_u32JobAddrEnd = ( u32TargetAddress + u32Length ) - 1U ;
+            Fls_eJob = FLS_JOB_ERASE;
+            Fls_u8JobStart = 1U;
+            /* Execute the erase job */
+            Fls_eJobResult = MEMIF_JOB_PENDING;
+
+            SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_10();
+        }
+    }
+
+    return( u8RetVal );
+}
+
+
+/**
+ * @brief            Write one or more complete flash pages to the flash device.
+ * @details          Starts a write job asynchronously. The actual job is performed by
+ *                   @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress        Target address in flash memory.
+ * @param[in]        pSourceAddressPtr       Pointer to source data buffer.
+ * @param[in]        u32Length               Number of bytes to write.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                 Write command has been accepted.
+ * @retval           E_NOT_OK             Write command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Write changes module status and some internal variables
+ *                  (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                  @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ * @implements       Fls_Write_Activity
+ *
+ */
+Std_ReturnType Fls_Write(Fls_AddressType u32TargetAddress,
+                         const uint8 * pSourceAddressPtr,
+                         Fls_LengthType u32Length
+                        )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    Fls_SectorIndexType u32TmpJobSectorIt;
+    Fls_AddressType u32TmpJobAddrEnd;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        /* Report Error if Fls_pConfigPtr = NULL_PTR  */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_WRITE_ID, FLS_E_UNINIT );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( (boolean)FALSE == (Fls_IsAddrPageStartAligned( (Fls_AddressType)u32TargetAddress )))
+    {
+        /* Report Error if u32TargetAddress is not aligned */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_WRITE_ID, FLS_E_PARAM_ADDRESS );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (( 0U == u32Length ) || ( (boolean)FALSE == (Fls_IsAddrPageEndAligned( u32TargetAddress +  u32Length ) )))
+    {
+        /* Report Error if u32TargetAddress +  u32Length is not aligned */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_WRITE_ID, FLS_E_PARAM_LENGTH );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( NULL_PTR == pSourceAddressPtr )
+    {
+        /* Report Error if pSourceAddressPtr = NULL_PTR */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_WRITE_ID, FLS_E_PARAM_DATA );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+
+        /* Perform calculations outside the critical section in order
+            to limit time spend in the CS */
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr(u32TargetAddress);
+        u32TmpJobAddrEnd = ( u32TargetAddress + u32Length ) - 1U;
+        /* Start of exclusive area. Implementation depends on integrator. */
+        SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_11();
+
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_WRITE_ID, FLS_E_BUSY );
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+            /* End of exclusive area. Implementation depends on integrator. */
+            SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_11();
+        }
+        else
+        {
+            /* Configure the write job */
+            Fls_u32JobSectorIt = u32TmpJobSectorIt;
+            Fls_u32JobSectorEnd = Fls_GetSectorIndexByAddr(u32TmpJobAddrEnd);
+            Fls_u32JobAddrEnd = u32TmpJobAddrEnd;
+            Fls_u32JobAddrIt = u32TargetAddress;
+            Fls_pJobDataSrcPtr = pSourceAddressPtr;
+            Fls_eJob = FLS_JOB_WRITE;
+            Fls_u8JobStart = 1U;
+            /* Execute the write job */
+            Fls_eJobResult = MEMIF_JOB_PENDING;
+            /* End of exclusive area. Implementation depends on integrator. */
+            SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_11();
+        }
+    }
+
+    return( u8RetVal );
+}
+
+
+#if ( FLS_CANCEL_API == STD_ON ) || defined(__DOXYGEN__)
+/**
+ * @brief            Cancel an ongoing flash read, write, erase or compare job.
+ * @details          Abort a running job synchronously so that directly after returning
+ *                   from this function a new job can be started.
+ *
+ * @api
+ *
+ * @pre              The module must be initialized.
+ * @post             @p Fls_Cancel changes module status and @p Fls_eJobResult
+ *                   internal variable.
+ *
+ * @implements       Fls_Cancel_Activity
+ *
+ */
+void Fls_Cancel( void )
+{
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_CANCEL_ID, FLS_E_UNINIT );
+    }
+    else
+    {
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+            /* Cancel ongoing hardware job */
+            Fls_IPW_Cancel();
+        #if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+            if (TRUE == Fls_bACloaded)
+            {
+                Fls_UnloadAc( Fls_eJob );
+                Fls_bACloaded = FALSE;
+            }
+            else
+            {
+                /* The FLS_JOB_READ and FLS_JOB_COMPARE jobs don't use the access code */
+            }
+        #endif /* #if STD_ON == FLS_AC_LOAD_ON_JOB_START */
+            /* If underlying hardware job was successfully cancelled */
+            if ( MEMIF_JOB_CANCELED == Fls_LLDGetJobResult() )
+            {
+                /* Update global job result status */
+                Fls_eJobResult = MEMIF_JOB_CANCELED;
+            }
+
+            if ( NULL_PTR != Fls_pConfigPtr->jobErrorNotificationPtr )
+            {
+                /* Call FlsJobErrorNotification function if configured */
+                Fls_pConfigPtr->jobErrorNotificationPtr();
+            }
+            else
+            {
+                /* Callback notification configured as null pointer */
+            }
+        }
+        else
+        {
+            /* Leave the job result unchanged */
+        }
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    }
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+}
+#endif    /* FLS_CANCEL_API == STD_ON */
+
+
+#if (( FLS_GET_STATUS_API == STD_ON ) || defined (__DOXYGEN__))
+/**
+ * @brief            Returns the FLS module status.
+ * @details          Returns the FLS module status synchronously.
+ *
+ * @return           MemIf_StatusType
+ * @retval           MEMIF_UNINIT        Module has not been initialized (yet).
+ * @retval           MEMIF_IDLE          Module is currently idle.
+ * @retval           MEMIF_BUSY          Module is currently busy.
+ *
+ * @api
+ *
+ * @implements       Fls_GetStatus_Activity
+ *
+ */
+MemIf_StatusType Fls_GetStatus( void )
+{
+    MemIf_StatusType eRetVal = MEMIF_IDLE;
+
+    /* if the Fls_pConfigPtr = NULL_PTR */
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        eRetVal = MEMIF_UNINIT;
+    }
+    else if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+    {
+        /* return MEMIF_BUSY if the other job is in progress */
+        eRetVal = MEMIF_BUSY;
+    }
+    else
+    {
+        /* return MEMIF_IDLE if no job  */
+        eRetVal = MEMIF_IDLE;
+    }
+
+    return( eRetVal );
+}
+#endif    /* FLS_GET_STATUS_API == STD_ON */
+
+
+#if ( FLS_GET_JOB_RESULT_API == STD_ON )||  defined (__DOXYGEN__)
+/**
+ * @brief            Returns the result of the last job.
+ * @details          Returns synchronously the result of the last job.
+ *
+ * @return           MemIf_JobResultType
+ * @retval           MEMIF_JOB_OK              Successfully completed job.
+ * @retval           MEMIF_JOB_FAILED          Not successfully completed job.
+ * @retval           MEMIF_JOB_PENDING         Still pending job (not yet completed).
+ * @retval           MEMIF_JOB_CANCELED        Job has been cancelled.
+ * @retval           MEMIF_BLOCK_INCONSISTENT  Inconsistent block requested, it may
+ *                                             contains corrupted data.
+ * @retval           MEMIF_BLOCK_INVALID       Invalid block requested.
+ *
+ * @api
+ *
+ * @implements       Fls_GetJobResult_Activity
+ *
+ */
+MemIf_JobResultType Fls_GetJobResult( void )
+{
+    MemIf_JobResultType eRetVal = MEMIF_JOB_OK;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_GETJOBRESULT_ID, FLS_E_UNINIT );
+        eRetVal = MEMIF_JOB_FAILED;
+    }
+    else
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+        eRetVal = Fls_eJobResult;
+    }
+    return( eRetVal );
+}
+#endif    /* FLS_GET_JOB_RESULT_API == STD_ON */
+
+
+/**
+ * @brief            Reads from flash memory.
+ * @details          Starts a read job asynchronously. The actual job is performed by
+ *                   @p Fls_MainFunction.
+ *
+ * @param[in]        u32SourceAddress        Source address in flash memory.
+ * @param[in]        u32Length               Number of bytes to read.
+ * @param[out]       pTargetAddressPtr       Pointer to target data buffer.
+ *
+ * @return           MemIf_JobResultType
+ * @retval           MEMIF_JOB_OK              Successfully completed job.
+ * @retval           MEMIF_JOB_FAILED          Not successfully completed job.
+ * @retval           MEMIF_JOB_PENDING         Still pending job (not yet completed).
+ * @retval           MEMIF_JOB_CANCELED        Job has been canceled.
+ * @retval           MEMIF_BLOCK_INCONSISTENT  Inconsistent block requested, it may
+ *                                             contains corrupted data.
+ * @retval           MEMIF_BLOCK_INVALID       Invalid block requested.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_Read changes module status and some internal variables
+ *                 (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                 @p Fls_pJobDataDestPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ * @implements       Fls_Read_Activity
+ *
+ */
+Std_ReturnType Fls_Read(Fls_AddressType u32SourceAddress,
+                        uint8 * pTargetAddressPtr,
+                        Fls_LengthType u32Length
+                       )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    Fls_SectorIndexType u32TmpJobSectorIt = 0UL;
+    Fls_AddressType u32TmpJobAddrEnd = 0UL;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    u8RetVal = CheckInputParamReadCompareJob(u32SourceAddress, pTargetAddressPtr, u32Length, FLS_READ_ID);
+    if ((Std_ReturnType)E_OK == u8RetVal)
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+
+        /* Perform calculations outside the critical section in order
+            to limit time spend in the CS */
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr( u32SourceAddress );
+        u32TmpJobAddrEnd = ( u32SourceAddress + u32Length ) - 1U;
+        /* Start of exclusive area. Implementation depends on integrator. */
+        SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_12();
+
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_READ_ID, FLS_E_BUSY );
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* Configure the read job */
+            Fls_u32JobSectorIt = u32TmpJobSectorIt;
+            Fls_u32JobSectorEnd = Fls_GetSectorIndexByAddr(u32TmpJobAddrEnd);
+            Fls_u32JobAddrIt = u32SourceAddress;
+            Fls_u32JobAddrEnd = u32TmpJobAddrEnd;
+            Fls_pJobDataDestPtr = pTargetAddressPtr;
+            Fls_eJob = FLS_JOB_READ;
+
+            Fls_u8JobStart = 1U;
+
+            /* Execute the read job */
+            Fls_eJobResult = MEMIF_JOB_PENDING;
+
+        }
+        /* End of exclusive area. Implementation depends on integrator. */
+        SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_12();
+    }
+
+    return( u8RetVal );
+}
+
+#if ( FLS_COMPARE_API == STD_ON ) || defined(__DOXYGEN__)
+/**
+ * @brief           Compares a flash memory area with an application data buffer.
+ * @details         Starts a compare job asynchronously. The actual job is performed by
+ *                  @p Fls_MainFunction.
+ *
+ * @param[in]        u32SourceAddress          Source address in flash memory.
+ * @param[in]        pTargetAddressPtr        Pointer to source data buffer.
+ * @param[in]        u32Length                 Number of bytes to compare.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                      Compare command has been accepted.
+ * @retval           E_NOT_OK                   Compare command has not been accepted.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_Read changes module status and some internal variables
+ *                (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ * @implements       Fls_Compare_Activity
+ *
+ */
+Std_ReturnType Fls_Compare( Fls_AddressType u32SourceAddress,
+                            const uint8 * pTargetAddressPtr,
+                            Fls_LengthType u32Length
+                          )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    Fls_SectorIndexType u32TmpJobSectorIt = 0UL;
+    Fls_AddressType u32TmpJobAddrEnd = 0UL;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    u8RetVal = CheckInputParamReadCompareJob(u32SourceAddress, pTargetAddressPtr, u32Length, FLS_COMPARE_ID);
+    if ((Std_ReturnType)E_OK == u8RetVal)
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+
+        /* Perform calculations outside the critical section in order
+            to limit time spend in the CS */
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr( u32SourceAddress );
+        u32TmpJobAddrEnd = ( u32SourceAddress + u32Length ) - 1U;
+        /* Start of exclusive area. Implementation depends on integrator. */
+        SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_13();
+
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_COMPARE_ID, FLS_E_BUSY );
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            Fls_u32JobSectorIt = u32TmpJobSectorIt;
+            Fls_u32JobSectorEnd = Fls_GetSectorIndexByAddr(u32TmpJobAddrEnd);
+            Fls_u32JobAddrIt = u32SourceAddress;
+            Fls_u32JobAddrEnd = u32TmpJobAddrEnd;
+            Fls_pJobDataSrcPtr = pTargetAddressPtr;
+            Fls_eJob = FLS_JOB_COMPARE;
+            Fls_u8JobStart = 1U;
+
+            /* Execute the read job */
+            Fls_eJobResult = MEMIF_JOB_PENDING;
+
+        }
+        /* End of exclusive area. Implementation depends on integrator. */
+        SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_13();
+    }
+
+    return( u8RetVal );
+}
+#endif /* FLS_COMPARE_API == STD_ON */
+
+#if (FLS_BLANK_CHECK_API == STD_ON)
+/**
+ * @brief           Verify whether a given memory area has been erased but not (yet) programmed.
+ * @details         Starts a compare job asynchronously. The actual job is performed by
+ *                  @p Fls_MainFunction.
+ *
+ * @param[in]        u32TargetAddress          Address in flash memory from which the blank check should be started.
+ * @param[in]        u32Length                 Number of bytes to be checked for erase pattern.
+ *
+ * @return           Std_ReturnType
+ * @retval           E_OK                   Blank checking command has been accepted.
+ * @retval           E_NOT_OK               Blank checking command has not been accepted.
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized and not busy.
+ * @post             @p Fls_Read changes module status and some internal variables
+ *                   (@p Fls_u32JobSectorIt, @p Fls_u32JobAddrIt, @p Fls_u32JobAddrEnd,
+ *                   @p Fls_pJobDataSrcPtr, @p Fls_eJob, @p Fls_eJobResult).
+ *
+ * @implements       Fls_BlankCheck_Activity
+ *
+ */
+Std_ReturnType Fls_BlankCheck( Fls_AddressType u32TargetAddress,
+                               Fls_LengthType u32Length
+                             )
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    Fls_SectorIndexType u32TmpJobSectorIt = 0UL;
+    Fls_AddressType u32TmpJobAddrEnd = 0UL;
+
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        /* Report Error if Fls_pConfigPtr = NULL_PTR  */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_UNINIT );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( u32TargetAddress >= FLS_TOTAL_SIZE )
+    {
+        /* Report Error if u32TargetAddress is not aligned */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_PARAM_ADDRESS );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (( 0U == u32Length ) || ((u32TargetAddress + u32Length) > FLS_TOTAL_SIZE ))
+    {
+        /* Report Error if u32Length is invalid */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_PARAM_LENGTH );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    else if ( (boolean)FALSE == Fls_IsAddrWordAligned(u32TargetAddress) )
+    {
+        /* Report Error if u32TargetAddress is not aligned */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_PARAM_ADDRESS );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    else if ( (boolean)FALSE == Fls_IsAddrWordAligned(u32TargetAddress + u32Length) )
+    {
+        /* Report Error if u32TargetAddress + u32Length is not aligned */
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_PARAM_LENGTH );
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    #endif /* #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+    else
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+    {
+        /* Perform calculations outside the critical section in order
+            to limit time spend in the CS */
+        u32TmpJobSectorIt = Fls_GetSectorIndexByAddr( u32TargetAddress );
+        u32TmpJobAddrEnd = ( u32TargetAddress + u32Length ) - 1U;
+        /* Start of exclusive area. Implementation depends on integrator. */
+        SchM_Enter_Fls_FLS_EXCLUSIVE_AREA_14();
+
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+            (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_BLANK_CHECK_ID, FLS_E_BUSY );
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            Fls_u32JobSectorIt = u32TmpJobSectorIt;
+            Fls_u32JobAddrIt = u32TargetAddress;
+            Fls_u32JobAddrEnd = u32TmpJobAddrEnd;
+            Fls_eJob = FLS_JOB_BLANK_CHECK;
+            Fls_u8JobStart = 1U;
+
+            /* Execute the read job */
+            Fls_eJobResult = MEMIF_JOB_PENDING;
+        }
+        /* End of exclusive area. Implementation depends on integrator. */
+        SchM_Exit_Fls_FLS_EXCLUSIVE_AREA_14();
+    }
+
+    return( u8RetVal );
+}
+#endif /* FLS_BLANK_CHECK_API == STD_ON */
+
+#if ( FLS_SET_MODE_API == STD_ON )|| defined (__DOXYGEN__)
+/**
+ * @brief           Sets the FLS module's operation mode to the given Mode.
+ * @details         Every given mode determines maximum bytes for read-write
+ *                  operations. Every mode has a set of pre-configured values.
+ *
+ * @param[in]        eMode        MEMIF_MODE_FAST or MEMIF_MODE_SLOW.
+ *
+ * @api
+ *
+ * @pre            The module has to be initialized and not busy.
+ * @post           @p Fls_SetMode changes internal variables @p Fls_u32MaxRead and
+ *                 @p Fls_u32MaxWrite.
+ *
+ * @implements       Fls_SetMode_Activity
+ *
+ */
+void Fls_SetMode(MemIf_ModeType eMode)
+{
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_SETMODE_ID, FLS_E_UNINIT );
+    }
+    else if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_SETMODE_ID, FLS_E_BUSY );
+    }
+    else
+    {
+#endif  /* FLS_DEV_ERROR_DETECT == STD_ON */
+        /* Set the max number of bytes to read/write
+            during Fls_MainFunction call */
+        switch ( eMode )
+        {
+            case MEMIF_MODE_FAST:
+                Fls_u32MaxRead = Fls_pConfigPtr->u32MaxReadFastMode;
+                Fls_u32MaxWrite = Fls_pConfigPtr->u32MaxWriteFastMode;
+                break;
+
+            case MEMIF_MODE_SLOW:
+                Fls_u32MaxRead = Fls_pConfigPtr->u32MaxReadNormalMode;
+                Fls_u32MaxWrite = Fls_pConfigPtr->u32MaxWriteNormalMode;
+                break;
+
+            default:
+                ; /* Do nothing - should not happen in Fully Trusted Environment;
+                   'default' clause added to fulfil MISRA Rule 15.3 */
+                break;
+        }
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    }
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+}
+#endif /* FLS_SET_MODE_API == STD_ON */
+
+#if ( FLS_VERSION_INFO_API == STD_ON )|| defined(__DOXYGEN__)
+/**
+ * @brief        Returns version information about FLS module.
+ * @details      Version information includes:
+ *               - Module Id
+ *               - Vendor Id
+ *               - Vendor specific version numbers (BSW00407).
+ *
+ * @param[in,out] pVersionInfoPtr  Pointer to where to store the version information of this module.
+ *
+ * @api
+ *
+ * @implements       Fls_GetVersionInfo_Activity
+ *
+ */
+void Fls_GetVersionInfo(Std_VersionInfoType * pVersionInfoPtr)
+{
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == pVersionInfoPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_GETVERSIONINFO_ID, FLS_E_PARAM_POINTER );
+    }
+    else
+    {
+#endif /* FLS_DEV_ERROR_DETECT == STD_ON */
+        pVersionInfoPtr->moduleID = (uint16)FLS_MODULE_ID;
+        pVersionInfoPtr->vendorID = (uint16)FLS_VENDOR_ID;
+        pVersionInfoPtr->sw_major_version = (uint8)FLS_SW_MAJOR_VERSION;
+        pVersionInfoPtr->sw_minor_version = (uint8)FLS_SW_MINOR_VERSION;
+        pVersionInfoPtr->sw_patch_version = (uint8)FLS_SW_PATCH_VERSION;
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    }
+#endif /* FLS_DEV_ERROR_DETECT == STD_ON */
+}
+#endif /* FLS_VERSION_INFO_API == STD_ON */
+
+
+static inline void Fls_MainFunction_CheckJobResult(MemIf_JobResultType eWorkResult)
+{
+    Fls_eJobResult = eWorkResult;
+
+    if ( MEMIF_JOB_OK == eWorkResult )
+    {
+        if ( NULL_PTR != Fls_pConfigPtr->jobEndNotificationPtr )
+        {
+            /* Call FlsJobEndNotification function if configured */
+            Fls_pConfigPtr->jobEndNotificationPtr();
+        }
+        else
+        {
+            ; /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    else if (( MEMIF_JOB_FAILED == eWorkResult ) ||
+            ( MEMIF_JOB_CANCELED == eWorkResult ) ||
+            ( MEMIF_BLOCK_INCONSISTENT == eWorkResult )
+           )
+    {
+        if ( NULL_PTR != Fls_pConfigPtr->jobErrorNotificationPtr )
+        {
+            /* Call FlsJobErrorNotification function if configured */
+            Fls_pConfigPtr->jobErrorNotificationPtr();
+        }
+        else
+        {
+            ; /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    else
+    {
+        ; /* Empty clause added to fulfill MISRA. */
+    }
+}
+
+
+/**
+ * @brief            Performs actual flash read, write, erase and compare jobs.
+ * @details          Bytes number processed per cycle depends by job type (erase, write, read, compare)
+ *                   current FLS module's operating mode (normal, fast)
+ *                   and write, erase Mode of Execution (sync, async).
+ *
+ * @api
+ *
+ * @pre              The module has to be initialized.
+ *
+ *
+ * @note             This function have to be called cyclically by the Basic Software Module;
+ *                   it will do nothing if there aren't pending job.
+ *
+ * @implements       Fls_MainFunction_Activity
+ */
+void Fls_MainFunction( void )
+{
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    if ( NULL_PTR == Fls_pConfigPtr )
+    {
+        (void) Det_ReportError( (uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_UNINIT );
+    }
+    else
+    {
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+        if ( MEMIF_JOB_PENDING == Fls_eJobResult )
+        {
+            MemIf_JobResultType eWorkResult = MEMIF_JOB_OK;
+
+                if ( 1U == Fls_u8JobStart )
+                {
+                    Fls_u8JobStart = 0U;
+
+                    /* Clear result of hardware job */
+                    Fls_LLDClrJobResult();
+
+                    Fls_IPW_AbortSuspended();
+                }
+                /* Check the status of pending jobs. */
+                if ( FLASH_JOB_NONE != Fls_eLLDJob ) /* If there is any Async job scheduled. */
+                {
+                    /* Process ongoing erase or write asynchronous hardware job */
+                    Fls_IPW_LLDMainFunction();  /* Process the maximum defined length(configuration parameter), or until a sector boundary. */
+                }
+                eWorkResult = Fls_LLDGetJobResult();
+                if (MEMIF_JOB_OK == eWorkResult)
+                {
+                    /* Process the requested jobs : write, compare, erase, read */
+                    eWorkResult = Fls_ProcessRequestedJobs();
+                }
+
+            Fls_MainFunction_CheckJobResult(eWorkResult);
+        }
+        else
+        {
+            ; /* Nothing to do since no job is pending */
+        }
+#if ( FLS_DEV_ERROR_DETECT == STD_ON )
+    }
+#endif    /* FLS_DEV_ERROR_DETECT == STD_ON */
+}
+
+/**
+ * @brief          Returns the LLD JobResult
+ */
+static MemIf_JobResultType Fls_LLDGetJobResult( void )
+{
+    return( Fls_eLLDJobResult );
+}
+
+/**
+ * @brief          Clear status of erase or write hardware job result.
+ * @details        Set the internal status to  MEMIF_JOB_OK
+ */
+static void Fls_LLDClrJobResult( void )
+{
+    Fls_eLLDJobResult = MEMIF_JOB_OK;
+    Fls_eLLDJob = FLASH_JOB_NONE;
+}
+
+#if ( STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED )
+#if ( (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) )
+/**
+* @brief          Low level data storage exception handler.
+*
+* @return         Exc_CompHandlerReturnType
+* @retval         EXC_HANDLED_SKIP The data storage exception was
+*                 caused by currently pending flash read or compare job
+* @retval         EXC_UNHANDLED The data storage exception was
+*                 NOT caused by currently pending flash read or compare job
+*
+* @implements    Fls_DsiHandler_Activity
+*/
+Fls_CompHandlerReturnType Fls_DsiHandler( const Fls_ExceptionDetailsType * pExceptionDetailsPtr )
+{
+    return Fls_IPW_DsiHandler(pExceptionDetailsPtr);
+}
+#endif /* (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) */
+
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+/**
+ * @brief         In the FlsReadFunctionCallout, user can start a task and call this function to performs the actual copy operation.
+ *
+ * @implements    Fls_ReadEachBlock_Activity
+ */
+void Fls_ReadEachBlock(void)
+{
+    /* Perform the copy */
+    Fls_IPW_ReadEachBlock();
+}
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+
+#endif /* STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED */
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Fls_IPW.c

@@ -0,0 +1,1714 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+/**
+*   @file Fls_IPW.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Fls_IPW.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls.h"
+#include "Fls_IPW.h"
+#include "Det.h"
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+#include "Ftfc_Fls_Ip.h"
+#include "Ftfc_Fls_Ip_Ac.h"
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+#include "Qspi_Ip.h"
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_IPW_VENDOR_ID_C                           43
+#define FLS_IPW_AR_RELEASE_MAJOR_VERSION_C            4
+#define FLS_IPW_AR_RELEASE_MINOR_VERSION_C            4
+#define FLS_IPW_AR_RELEASE_REVISION_VERSION_C         0
+#define FLS_IPW_SW_MAJOR_VERSION_C                    1
+#define FLS_IPW_SW_MINOR_VERSION_C                    0
+#define FLS_IPW_SW_PATCH_VERSION_C                    0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls header file are of the same vendor */
+#if (FLS_IPW_VENDOR_ID_C != FLS_VENDOR_ID)
+    #error "Fls_IPW.c and Fls.h have different vendor ids"
+#endif
+/* Check if current file and Fls header file are of the same Autosar version */
+#if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C    != FLS_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_IPW_AR_RELEASE_MINOR_VERSION_C    != FLS_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_IPW_AR_RELEASE_REVISION_VERSION_C != FLS_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls_IPW.c and Fls.h are different"
+#endif
+/* Check if current file and Fls header file are of the same Software version */
+#if ((FLS_IPW_SW_MAJOR_VERSION_C != FLS_SW_MAJOR_VERSION) || \
+     (FLS_IPW_SW_MINOR_VERSION_C != FLS_SW_MINOR_VERSION) || \
+     (FLS_IPW_SW_PATCH_VERSION_C != FLS_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_IPW.c and Fls.h are different"
+#endif
+
+/* Check if current file and Fls_IPW.h header file have the same Vendor ID */
+#if (FLS_IPW_VENDOR_ID_C != FLS_IPW_VENDOR_ID_H)
+    #error "Fls_IPW.c and Fls_IPW.h have different vendor ids"
+#endif
+/* Check if current file and Fls_IPW.h header file are of the same Autosar version */
+#if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C    != FLS_IPW_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FLS_IPW_AR_RELEASE_MINOR_VERSION_C    != FLS_IPW_AR_RELEASE_MINOR_VERSION_H) || \
+     (FLS_IPW_AR_RELEASE_REVISION_VERSION_C != FLS_IPW_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Fls_IPW.c and Fls_IPW.h are different"
+#endif
+/* Check if current file and Fls_IPW.h header file are of the same Software version */
+#if ((FLS_IPW_SW_MAJOR_VERSION_C != FLS_IPW_SW_MAJOR_VERSION_H) || \
+     (FLS_IPW_SW_MINOR_VERSION_C != FLS_IPW_SW_MINOR_VERSION_H) || \
+     (FLS_IPW_SW_PATCH_VERSION_C != FLS_IPW_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Fls_IPW.c and Fls_IPW.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Det header file are of the same Autosar version */
+    #if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C != DET_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_IPW_AR_RELEASE_MINOR_VERSION_C != DET_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls_IPW.c and Det.h are different"
+    #endif
+#endif
+
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    /* Check if current file and Ftfc_Fls_Ip header file are of the same vendor */
+    #if (FLS_IPW_VENDOR_ID_C != FTFC_FLS_IP_VENDOR_ID_H)
+        #error "Fls_IPW.c and Ftfc_Fls_Ip.h have different vendor ids"
+    #endif
+    /* Check if current file and Ftfc_Fls_Ip header file are of the same Autosar version */
+    #if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+            (FLS_IPW_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H) || \
+            (FLS_IPW_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H) \
+        )
+        #error "AutoSar Version Numbers of Fls_IPW.c and Ftfc_Fls_Ip.h are different"
+    #endif
+    /* Check if current file and Ftfc_Fls_Ip header file are of the same Software version */
+    #if ((FLS_IPW_SW_MAJOR_VERSION_C != FTFC_FLS_IP_SW_MAJOR_VERSION_H) || \
+         (FLS_IPW_SW_MINOR_VERSION_C != FTFC_FLS_IP_SW_MINOR_VERSION_H) || \
+         (FLS_IPW_SW_PATCH_VERSION_C != FTFC_FLS_IP_SW_PATCH_VERSION_H) \
+        )
+        #error "Software Version Numbers of Fls_IPW.c and Ftfc_Fls_Ip.h are different"
+    #endif
+
+    /* Check if current file and Ftfc_Fls_Ip_Ac header file are of the same vendor */
+    #if (FLS_IPW_VENDOR_ID_C != FTFC_FLS_IP_AC_VENDOR_ID_H)
+        #error "Fls_IPW.c and Ftfc_Fls_Ip_Ac.h have different vendor ids"
+    #endif
+    /* Check if current file and Ftfc_Fls_Ip_Ac header file are of the same Autosar version */
+    #if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_H) || \
+            (FLS_IPW_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_H) || \
+            (FLS_IPW_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_H) \
+        )
+        #error "AutoSar Version Numbers of Fls_IPW.c and Ftfc_Fls_Ip_Ac.h are different"
+    #endif
+    /* Check if current file and Ftfc_Fls_Ip_Ac header file are of the same Software version */
+    #if ((FLS_IPW_SW_MAJOR_VERSION_C != FTFC_FLS_IP_AC_SW_MAJOR_VERSION_H) || \
+         (FLS_IPW_SW_MINOR_VERSION_C != FTFC_FLS_IP_AC_SW_MINOR_VERSION_H) || \
+         (FLS_IPW_SW_PATCH_VERSION_C != FTFC_FLS_IP_AC_SW_PATCH_VERSION_H) \
+        )
+        #error "Software Version Numbers of Fls_IPW.c and Ftfc_Fls_Ip_Ac.h are different"
+    #endif
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    /* Check if current file and Fls_Qspi header file are of the same vendor */
+    #if (FLS_IPW_VENDOR_ID_C != QSPI_IP_VENDOR_ID_H)
+        #error "Fls_IPW.c and Fls_Qspi.h have different vendor ids"
+    #endif
+    #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+        /* Check if current file and Fls_Qspi header file are of the same Autosar version */
+        #if ((FLS_IPW_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+             (FLS_IPW_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+             (FLS_IPW_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+            )
+            #error "AutoSar Version Numbers of Fls_IPW.c and Fls_Qspi.h are different"
+        #endif
+    #endif
+    /* Check if current file and Fls_Qspi header file are of the same Software version */
+    #if ((FLS_IPW_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_H) || \
+         (FLS_IPW_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_H) || \
+         (FLS_IPW_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_H) \
+        )
+        #error "Software Version Numbers of Fls_IPW.c and Fls_Qspi.h are different"
+    #endif
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+#if (STD_ON == FLS_AC_LOAD_ON_JOB_START)
+    #ifdef MCAL_PLATFORM_ARM
+        #define FLASH_ARM_FAR_CALL2THUMB_CODE_BIT0_U32 (0x00000001UL)
+        /* Macro for Access Code Call. On ARM/Thumb, BLX instruction used by the compiler for calling a function
+           pointed to by the pointer requires that LSB bit of the address is set to one if the called fcn is coded in Thumb. */
+        #define FLASH_AC_CALL(ptr2fcn, ptr2fcnType) ((ptr2fcnType)(((uint32)(ptr2fcn)) | FLASH_ARM_FAR_CALL2THUMB_CODE_BIT0_U32))
+    #else
+        #define FLASH_AC_CALL(ptr2fcn, ptr2fcnType) (ptr2fcn)
+    #endif /* MCAL_PLATFORM_ARM */
+#endif /* FLS_AC_LOAD_ON_JOB_START */
+
+
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+static Fls_LLDReturnType Fls_IPW_TranslateReturnCode(Ftfc_Fls_Ip_StatusType eReturnCode);
+static void Fls_IPW_LLDMainFunctionFtfcJobs(void);
+static inline void Fls_IPW_LLDMainFunctionFtfcJobs_CheckEraseStatus(Ftfc_Fls_Ip_StatusType status);
+static inline void Fls_IPW_LLDMainFunctionFtfcJobs_CheckWriteStatus(Ftfc_Fls_Ip_StatusType status);
+static inline Fls_LLDReturnType Fls_IPW_SectorEraseFtfcJobs(boolean bAsynch, Fls_AddressType u32SectorOffset);
+static inline Fls_LLDReturnType Fls_IPW_SectorWriteFtfcJobs(const Fls_AddressType u32SectorOffset, const Fls_AddressType u32Length, const uint8 *pJobDataSrcPtr, const boolean bAsynch);
+static inline void Fls_IPW_CallAccessCodeWrite(void);
+static inline void Fls_IPW_CallAccessCodeErase(void);
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+static Ftfc_Fls_Ip_StatusType Fls_IPW_CopyBlock(uint32 u32LogicalAddress, uint32 u32Length, uint8 *pDestAddressPtr, const uint8 *pSourceAddressPtr);
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+static Fls_AddressType  Fls_IPW_ComputeWriteChunkSize(Fls_AddressType jobSize, Fls_AddressType baseAddr, Fls_AddressType pageSize);
+static Fls_LLDReturnType Fls_IPW_SectorWriteChunk(const boolean bAsynch);
+static void Fls_IPW_LLDMainFunctionQspiErase(uint32 flashInstance);
+static void Fls_IPW_LLDMainFunctionQspiWrite(uint32 flashInstance);
+static void Fls_IPW_LLDMainFunctionQspiJobs(void);
+static inline Fls_LLDReturnType Fls_IPW_SectorEraseQspiJobs(boolean bAsynch, Fls_AddressType u32SectorOffset, const Fls_LengthType u32PhysicalSectorSize);
+static inline Fls_LLDReturnType Fls_IPW_SectorWriteQspiJobs(const Fls_AddressType u32SectorOffset, const Fls_AddressType u32Length, const uint8 *pJobDataSrcPtr, const boolean bAsynch);
+static Qspi_Ip_StatusType Fls_IPW_InitControllers(void);
+static Qspi_Ip_StatusType Fls_IPW_InitMemories(void);
+static boolean Fls_IPW_CheckDevicesId(void);
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+
+/*==================================================================================================
+                                 ENUM TYPEDEFS
+==================================================================================================*/
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+/**
+* @brief   Elements of read callout function
+*/
+typedef struct
+{
+    uint32             u32ReadStartAddress;    /**< @brief The start address of the memory area to be read/compare  */
+    uint32             u32Length;              /**< @brief Number of bytes to read/compare                          */
+    uint8              *pDataDest;             /**< @brief Pointer to target data buffer used to read to            */
+    const uint8        *pDataSource;           /**< @brief Pointer to source data buffer used to compare            */
+    Ftfc_Fls_Ip_StatusType  eStatus;           /**< @brief Status of the copy operation                             */
+} Fls_CopyDescrType;
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+/*==================================================================================================
+                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+
+/*==================================================================================================
+ *                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+#if (defined(FLS_DEVICES_USING_SFDP))
+#if (FLS_DEVICES_USING_SFDP > 0)
+
+#define FLS_QSPI_SFDP_LUT_SIZE               130U
+#define FLS_QSPI_SFDP_INIT_OP_SIZE           4U
+
+typedef struct
+{
+    Qspi_Ip_InstrOpType lutOps[FLS_QSPI_SFDP_LUT_SIZE];               /*!< Array for virtual LUT instructions       */
+    Qspi_Ip_InitOperationType initOps[FLS_QSPI_SFDP_INIT_OP_SIZE];    /*!< Array for initial operations             */
+    Qspi_Ip_MemoryConfigType sfdpCfg;                                 /*!< Flash device configuration structure     */
+} Fls_Qspi_SfdpConfigType;
+#endif
+#endif
+
+
+/*==================================================================================================
+                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL VARIABLES
+==================================================================================================*/
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* The external job start address */
+static Fls_AddressType Fls_Qspi_u32ExtJobStartAddr;
+/* The external job size */
+static Fls_AddressType Fls_Qspi_u32ExtJobSize;
+/* The external job current chunk size, for jobs which need to be split in chunks */
+static Fls_AddressType Fls_Qspi_u32ExtJobChunkSize;
+/* Source data buffer for the current write job. */
+static const uint8 * Fls_Qspi_u32ExtJobBuffAddr;
+
+#if (defined(FLS_DEVICES_USING_SFDP))
+#if (FLS_DEVICES_USING_SFDP > 0)
+/* Array of configurations for flash devices configured to use SFDP  */
+static Fls_Qspi_SfdpConfigType Fls_Qspi_SfdpConfigs[FLS_DEVICES_USING_SFDP];
+/* Configurations indexes for flash devices configured to use SFDP  */
+static uint8 Fls_Qspi_SfdpConfigsIndex[QSPI_IP_MEM_INSTANCE_COUNT];
+#endif
+#endif
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+/* Counters for timeout detection */
+static uint32  Fls_Qspi_u32ElapsedTicks;
+static uint32  Fls_Qspi_u32TimeoutTicks;
+static uint32  Fls_Qspi_u32CurrentTicks;
+
+#define FLS_STOP_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+/* The copy operation when read */
+static Fls_CopyDescrType Fls_CopyDescr;
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+/*
+    Computes the size of the next chunk of a write job.
+*/
+static Fls_AddressType  Fls_IPW_ComputeWriteChunkSize(Fls_AddressType jobSize, Fls_AddressType baseAddr, Fls_AddressType pageSize)
+{
+    Fls_AddressType chunkSize;
+
+    /* Check external device restrictions: chunkSize can not exceed the device page size */
+    /* If address is not aligned, max. chunkSize is the amount left in the current page */
+    chunkSize = pageSize - (baseAddr % pageSize);
+    /* Check if chunk does not exceed IP driver capabilities */
+    if (chunkSize > QSPI_IP_MAX_WRITE_SIZE)
+    {
+        chunkSize = QSPI_IP_MAX_WRITE_SIZE;
+    }
+    /* Check if entire job fits in current page */
+    if (chunkSize > jobSize)
+    {
+        chunkSize = jobSize;
+    }
+    return chunkSize;
+}
+
+/**
+* @brief          Writes a single data chunk.
+* @details        This function initiates a write for a data chunk - amount of data than can be written in a single operation.
+*/
+static Fls_LLDReturnType Fls_IPW_SectorWriteChunk(const boolean bAsynch)
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    uint32 flashInstance;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    /* Get external flash instance */
+    flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[Fls_u32JobSectorIt];
+
+#if (FLS_ERASE_VERIFICATION_ENABLED == STD_ON)
+    if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_EraseVerify(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobChunkSize))
+    {
+        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_ERASE_FAILED);
+        eLldRetVal = FLASH_E_FAILED;
+    }
+    else
+    {
+#endif /* (FLS_ERASE_VERIFICATION_ENABLED == STD_ON) */
+        /* Call IP write routine. */
+        if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_Program(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobBuffAddr, Fls_Qspi_u32ExtJobChunkSize))
+        {
+            eLldRetVal = FLASH_E_FAILED;
+        }
+        else
+        {
+            if ((boolean)FALSE == bAsynch) /*SYNC Mode*/
+            {
+                eLldRetVal = FLASH_E_OK;
+                /* Wait for the write to finish. */
+                do
+                {
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+                    Fls_Qspi_u32ElapsedTicks += OsIf_GetElapsed(&Fls_Qspi_u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+                    if (Fls_Qspi_u32ElapsedTicks >= Fls_Qspi_u32TimeoutTicks)
+                    {
+                        status = STATUS_QSPI_IP_TIMEOUT;
+                        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+                        break;
+                    }
+                    else
+                    {
+                        ; /* Empty clause added to fulfill MISRA. */
+                    }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+                    status = Qspi_Ip_GetMemoryStatus(flashInstance);
+                }
+                while (STATUS_QSPI_IP_BUSY == status);
+
+                if (STATUS_QSPI_IP_SUCCESS != status)
+                {
+                    eLldRetVal = FLASH_E_FAILED;
+                }
+#if (FLS_WRITE_VERIFICATION_ENABLED == STD_ON)
+                else if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_ProgramVerify(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobBuffAddr, Fls_Qspi_u32ExtJobChunkSize))
+                {
+                    (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_WRITE_FAILED);
+                    eLldRetVal = FLASH_E_FAILED;
+                }
+#endif /* (FLS_WRITE_VERIFICATION_ENABLED == STD_ON) */
+                else
+                {
+                    ; /* Empty clause added to fulfill MISRA. */
+                }
+            }
+            else
+            {
+                /* Schedule async write job. */
+                Fls_eLLDJobResult = MEMIF_JOB_PENDING;
+                Fls_eLLDJob = FLASH_JOB_WRITE;
+                eLldRetVal = FLASH_E_PENDING;
+            }
+        }
+#if (FLS_ERASE_VERIFICATION_ENABLED == STD_ON)
+    }
+#endif /* (FLS_ERASE_VERIFICATION_ENABLED == STD_ON) */
+
+    return eLldRetVal;
+}
+
+/*
+ * Function Name : Fls_IPW_LLDMainFunctionQspiErase
+ * Description   : Handles ASYNC QSPI erase
+*/
+static void Fls_IPW_LLDMainFunctionQspiErase(uint32 flashInstance)
+{
+#if (FLS_ERASE_VERIFICATION_ENABLED == STD_OFF)
+    (void)flashInstance;
+#else
+    Fls_AddressType u32ChunkSize = FLS_MAX_ERASE_BLANK_CHECK;
+
+    if (Fls_Qspi_u32ExtJobSize < FLS_MAX_ERASE_BLANK_CHECK)
+    {
+        u32ChunkSize = Fls_Qspi_u32ExtJobSize;
+    }
+    Fls_Qspi_u32ExtJobSize -= u32ChunkSize;
+    /* Verify that the sector was successfully erased. */
+    if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_EraseVerify(flashInstance, Fls_Qspi_u32ExtJobStartAddr, u32ChunkSize))
+    {
+        /* Error, the memory locations are not erased or there was an error when attempting to read it. */
+        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_ERASE_FAILED);
+        Fls_eLLDJob = FLASH_JOB_NONE;
+        Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+    }
+    if ((Fls_Qspi_u32ExtJobSize == 0U) && (Fls_eLLDJob != FLASH_JOB_NONE))
+#endif /* (FLS_ERASE_VERIFICATION_ENABLED == STD_ON) */
+    {
+        /* Erase operation succeeded */
+        Fls_eLLDJob = FLASH_JOB_NONE;
+        Fls_eLLDJobResult = MEMIF_JOB_OK;
+        if ((Fls_u32JobAddrIt > ((*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt])))
+        {
+            /* Move on to the next sector */
+            Fls_u32JobSectorIt++;
+        }
+    }
+}
+
+
+/*
+ * Function Name : Fls_IPW_GetExtFlashConfig
+ * Description   : Gets the external flash configuration
+*/
+static const Qspi_Ip_MemoryConfigType * Fls_IPW_GetExtFlashConfig(uint32 flashInstance)
+{
+    const Qspi_Ip_MemoryConfigType *flashConfig = NULL_PTR;
+    uint32 flashConfigNo;
+
+    /* Get external flash configuration */
+    flashConfigNo = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashConfig))[flashInstance];
+    if (flashConfigNo != FLS_IPW_CFG_INVALID)
+    {
+        flashConfig = &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashCfg))[flashConfigNo]);
+    }
+#if (defined(FLS_DEVICES_USING_SFDP))
+#if (FLS_DEVICES_USING_SFDP > 0)
+    else
+    {
+        /* SFDP auto-filled configuration */
+        flashConfigNo = Fls_Qspi_SfdpConfigsIndex[flashInstance];
+        flashConfig = &(Fls_Qspi_SfdpConfigs[flashConfigNo].sfdpCfg);
+    }
+#endif
+#endif
+    return flashConfig;
+}
+
+
+/*
+ * Function Name : Fls_IPW_LLDMainFunctionQspiWrite
+ * Description   : Handles ASYNC QSPI write
+*/
+static void Fls_IPW_LLDMainFunctionQspiWrite(uint32 flashInstance)
+{
+    const Qspi_Ip_MemoryConfigType *flashConfig;
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+
+#if (FLS_WRITE_VERIFICATION_ENABLED == STD_ON)
+    if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_ProgramVerify(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobBuffAddr, Fls_Qspi_u32ExtJobChunkSize))
+    {
+        /* Error, the memory location was not programmed with the desired data. */
+        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_WRITE_FAILED);
+        Fls_eLLDJob = FLASH_JOB_NONE;
+        Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+    }
+    else
+#endif /* (FLS_WRITE_VERIFICATION_ENABLED == STD_ON) */
+    {
+        /* Chunk write succeeded, check if there are more chunks */
+        if (Fls_Qspi_u32ExtJobSize == Fls_Qspi_u32ExtJobChunkSize)
+        {
+            /* This was the last chunk, operation is completed */
+            Fls_eLLDJob = FLASH_JOB_NONE;
+            Fls_eLLDJobResult = MEMIF_JOB_OK;
+            /* For a Write Job in ASYNC mode check if Fls_u32JobSectorIt should be increased */
+            if ((Fls_u32JobAddrIt > ((*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt])))
+            {
+                /* Move on to the next sector */
+                Fls_u32JobSectorIt++;
+            }
+        }
+        else
+        {
+            /* Get external flash configuration */
+            flashConfig = Fls_IPW_GetExtFlashConfig(flashInstance);
+            /* Update job parameters */
+            Fls_Qspi_u32ExtJobStartAddr += Fls_Qspi_u32ExtJobChunkSize;
+            Fls_Qspi_u32ExtJobBuffAddr = &(Fls_Qspi_u32ExtJobBuffAddr[Fls_Qspi_u32ExtJobChunkSize]);
+            Fls_Qspi_u32ExtJobSize -= Fls_Qspi_u32ExtJobChunkSize;
+            Fls_Qspi_u32ExtJobChunkSize = Fls_IPW_ComputeWriteChunkSize(Fls_Qspi_u32ExtJobSize, Fls_Qspi_u32ExtJobStartAddr, flashConfig->pageSize);
+            /* Launch async write of next chunk */
+            eLldRetVal = Fls_IPW_SectorWriteChunk((boolean)TRUE);
+            if (FLASH_E_FAILED == eLldRetVal)
+            {
+                /* Error, cannot launch write for next chunk */
+                Fls_eLLDJob = FLASH_JOB_NONE;
+                Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            }
+        }
+    }
+}
+
+/*
+ * Function Name : Fls_IPW_LLDMainFunctionQspiJobs
+ * Description   : Handles ASYNC QSPI jobs
+*/
+static void Fls_IPW_LLDMainFunctionQspiJobs(void)
+{
+    Qspi_Ip_StatusType status;
+    uint32 flashInstance;
+
+    /* Get external flash instance */
+    flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[Fls_u32JobSectorIt];
+
+    status = Qspi_Ip_GetMemoryStatus(flashInstance);
+    if (STATUS_QSPI_IP_BUSY != status)
+    {
+        if (STATUS_QSPI_IP_SUCCESS != status)
+        {
+            /* Error, unable to retrieve flash device status */
+            if (FLASH_JOB_ERASE == Fls_eLLDJob)
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_ERASE_FAILED);
+            }
+            else if (FLASH_JOB_WRITE == Fls_eLLDJob )
+            {
+
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_WRITE_FAILED);
+            }
+            else
+            {
+                ; /* Do nothing - should not happen in Fully Trusted Environment;
+                'else' clause added to fulfil MISRA Rule 14.10 */
+            }
+
+            Fls_eLLDJob = FLASH_JOB_NONE;
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+        }
+        else
+        {
+            if (FLASH_JOB_ERASE == Fls_eLLDJob)
+            {
+                Fls_IPW_LLDMainFunctionQspiErase(flashInstance);
+            }
+            else if (FLASH_JOB_WRITE == Fls_eLLDJob )
+            {
+                Fls_IPW_LLDMainFunctionQspiWrite(flashInstance);
+            }
+            else
+            {
+                ; /* Do nothing - should not happen in Fully Trusted Environment;
+                'else' clause added to fulfil MISRA Rule 14.10 */
+            }
+        }
+    }   /* if (STATUS_QSPI_IP_BUSY != status ) */
+    else
+    {
+        /* device busy, check timeout */
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+        Fls_Qspi_u32ElapsedTicks += OsIf_GetElapsed(&Fls_Qspi_u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (Fls_Qspi_u32ElapsedTicks >= Fls_Qspi_u32TimeoutTicks)
+        {
+            /* operation timed out */
+            (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+
+            if (FLASH_JOB_ERASE == Fls_eLLDJob)
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_ERASE_FAILED);
+            }
+            else if (FLASH_JOB_WRITE == Fls_eLLDJob )
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_WRITE_FAILED);
+            }
+            else
+            {
+                ; /* Do nothing - should not happen in Fully Trusted Environment;
+                'else' clause added to fulfil MISRA Rule 14.10 */
+            }
+
+            Fls_eLLDJob = FLASH_JOB_NONE;
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+        }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+    }   /* if (STATUS_QSPI_IP_BUSY != status ) */
+}
+
+
+static inline Fls_LLDReturnType Fls_IPW_SectorEraseQspiJobs(boolean bAsynch, Fls_AddressType u32SectorOffset, const Fls_LengthType u32PhysicalSectorSize)
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 flashInstance;
+
+    /* Get external flash instance */
+    flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[Fls_u32JobSectorIt];
+    /* Compute target address : sector start address */
+    Fls_Qspi_u32ExtJobStartAddr = (*(Fls_pConfigPtr->paSectorHwAddress))[Fls_u32JobSectorIt] + u32SectorOffset;
+    /* Record job size */
+    Fls_Qspi_u32ExtJobSize = u32PhysicalSectorSize;
+
+    /* Call IP routine to erase external sector. */
+    if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_EraseBlock(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobSize))
+    {
+        eLldRetVal = FLASH_E_FAILED;
+    }
+    else
+    {
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+        /* Prepare timeout counter */
+        Fls_Qspi_u32ElapsedTicks = 0U;
+        Fls_Qspi_u32TimeoutTicks = OsIf_MicrosToTicks(((boolean)FALSE == bAsynch)?FLS_QSPI_SYNC_ERASE_TIMEOUT:FLS_QSPI_ASYNC_ERASE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        Fls_Qspi_u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+        if ((boolean)FALSE == bAsynch) /*SYNC Mode*/
+        {
+            eLldRetVal = FLASH_E_OK;
+            /* Wait for the erase to finish. */
+            do
+            {
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+                Fls_Qspi_u32ElapsedTicks += OsIf_GetElapsed(&Fls_Qspi_u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+                if (Fls_Qspi_u32ElapsedTicks >= Fls_Qspi_u32TimeoutTicks)
+                {
+                    status = STATUS_QSPI_IP_TIMEOUT;
+                    (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+                    break;
+                }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+                status = Qspi_Ip_GetMemoryStatus(flashInstance);
+            }
+            while (STATUS_QSPI_IP_BUSY == status);
+
+            if (STATUS_QSPI_IP_SUCCESS != status)
+            {
+                eLldRetVal = FLASH_E_FAILED;
+            }
+#if (FLS_ERASE_VERIFICATION_ENABLED == STD_ON)
+            /* Verify that the sector was succesfully erased. */
+            else if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_EraseVerify(flashInstance, Fls_Qspi_u32ExtJobStartAddr, Fls_Qspi_u32ExtJobSize))
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_ERASE_FAILED);
+                eLldRetVal = FLASH_E_FAILED;
+            }
+#endif
+            else
+            {
+                ; /* Empty clause added to fulfill MISRA. */
+            }
+        }
+        else
+        {
+            /* Schedule async erase job. */
+            Fls_eLLDJobResult = MEMIF_JOB_PENDING;
+            Fls_eLLDJob = FLASH_JOB_ERASE;
+            eLldRetVal = FLASH_E_PENDING;
+        }
+    }
+
+    return eLldRetVal;
+}
+
+
+static inline Fls_LLDReturnType Fls_IPW_SectorWriteQspiJobs(const Fls_AddressType u32SectorOffset,
+                                                            const Fls_AddressType u32Length,
+                                                            const uint8 *pJobDataSrcPtr,
+                                                            const boolean bAsynch
+                                                           )
+{
+    Fls_LLDReturnType eLldRetVal;
+    const Qspi_Ip_MemoryConfigType *flashConfig;
+    uint32 flashInstance;
+
+    /* Get external flash instance */
+    flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[Fls_u32JobSectorIt];
+    /* Get external flash configuration */
+    flashConfig = Fls_IPW_GetExtFlashConfig(flashInstance);
+
+    /* Compute target address : sector address + offset */
+    Fls_Qspi_u32ExtJobStartAddr = (*(Fls_pConfigPtr->paSectorHwAddress))[Fls_u32JobSectorIt] + u32SectorOffset;
+    /* Record source pointer */
+    Fls_Qspi_u32ExtJobBuffAddr = pJobDataSrcPtr;
+    /* Record job size */
+    Fls_Qspi_u32ExtJobSize = u32Length;
+    /* Compute next chunk size - consider QSPI and external device restrictions */
+    Fls_Qspi_u32ExtJobChunkSize = Fls_IPW_ComputeWriteChunkSize(Fls_Qspi_u32ExtJobSize, Fls_Qspi_u32ExtJobStartAddr, flashConfig->pageSize);
+
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+    /* Prepare timeout counter */
+    Fls_Qspi_u32ElapsedTicks = 0U;
+    Fls_Qspi_u32TimeoutTicks = OsIf_MicrosToTicks(((boolean)FALSE == bAsynch)?FLS_QSPI_SYNC_WRITE_TIMEOUT:FLS_QSPI_ASYNC_WRITE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    Fls_Qspi_u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+
+    /* Write the first chunk */
+    eLldRetVal = Fls_IPW_SectorWriteChunk(bAsynch);
+    if ((boolean)FALSE == bAsynch)
+    {    /* SYNC Mode - complete operation */
+        while ((FLASH_E_OK == eLldRetVal) && (Fls_Qspi_u32ExtJobSize > Fls_Qspi_u32ExtJobChunkSize))
+        {
+            /* Update job parameters */
+            Fls_Qspi_u32ExtJobStartAddr += Fls_Qspi_u32ExtJobChunkSize;
+            Fls_Qspi_u32ExtJobBuffAddr = &(Fls_Qspi_u32ExtJobBuffAddr[Fls_Qspi_u32ExtJobChunkSize]);
+            Fls_Qspi_u32ExtJobSize -= Fls_Qspi_u32ExtJobChunkSize;
+            Fls_Qspi_u32ExtJobChunkSize = Fls_IPW_ComputeWriteChunkSize(Fls_Qspi_u32ExtJobSize, Fls_Qspi_u32ExtJobStartAddr, flashConfig->pageSize);
+            /* Write current chunk */
+            eLldRetVal = Fls_IPW_SectorWriteChunk(bAsynch);
+        }
+    }
+
+    return eLldRetVal;
+}
+
+
+/*
+ * Function Name : Fls_IPW_InitControllers
+ * Description   : Initialize QSPI controllers
+*/
+static Qspi_Ip_StatusType Fls_IPW_InitControllers(void)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint8 config = 0U;
+    uint8 cnt = 0U;
+
+    for (cnt = 0U; cnt < Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiUnitsCount; cnt++)
+    {
+        /* Get configuration for current QSPI device */
+        config = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8QspiConfig))[cnt];
+        if (config != FLS_IPW_CFG_INVALID)
+        {
+            /* Use configuration "config" to initialize QSPI controller "cnt" */
+            status = Qspi_Ip_ControllerInit(cnt, &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paQspiUnitCfg))[config]));
+            if (STATUS_QSPI_IP_SUCCESS != status)
+            {
+                break;
+            }
+        }
+    }
+
+    return status;
+}
+
+/*
+ * Function Name : Fls_IPW_InitMemories
+ * Description   : Initialize Qspi external flash devices
+*/
+static Qspi_Ip_StatusType Fls_IPW_InitMemories(void)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint8 config = 0U;
+    uint8 cnt = 0U;
+#if (defined(FLS_DEVICES_USING_SFDP))
+#if (FLS_DEVICES_USING_SFDP > 0)
+    Qspi_Ip_MemoryConfigType *flashCfg;
+    /* Current SFDP configuration  */
+    uint8 Fls_Qspi_SfdpConfigsCount = 0U;
+#endif
+#endif
+
+    for (cnt = 0U; cnt < Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashUnitsCount; cnt++)
+    {
+        /* Get configuration for current QSPI device */
+        config = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashConfig))[cnt];
+        if (config != FLS_IPW_CFG_INVALID)
+        {
+            /* Use configuration "config" to initialize flash device "cnt" */
+            status = Qspi_Ip_Init(cnt, &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashCfg))[config]), &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[cnt]));
+        }
+#if (defined(FLS_DEVICES_USING_SFDP))
+#if (FLS_DEVICES_USING_SFDP > 0)
+        else
+        {
+            /* This device must auto-configure using SFDP */
+            /* Prepare configuration structure, link lut and init operations arrays */
+            flashCfg = &(Fls_Qspi_SfdpConfigs[Fls_Qspi_SfdpConfigsCount].sfdpCfg);
+            flashCfg->lutSequences.opCount = FLS_QSPI_SFDP_LUT_SIZE;
+            flashCfg->lutSequences.lutOps = Fls_Qspi_SfdpConfigs[Fls_Qspi_SfdpConfigsCount].lutOps;
+            flashCfg->initConfiguration.opCount = FLS_QSPI_SFDP_INIT_OP_SIZE;
+            flashCfg->initConfiguration.operations = Fls_Qspi_SfdpConfigs[Fls_Qspi_SfdpConfigsCount].initOps;
+            status = Qspi_Ip_ReadSfdp(flashCfg, &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[cnt]));
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                /* Qspi_Ip_ReadSfdp auto-filled configuration, use it to initialize flash device */
+                status = Qspi_Ip_Init(cnt, flashCfg, &((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[cnt]));
+            }
+            /* Store index to allow configuration to be retrieved later */
+            Fls_Qspi_SfdpConfigsIndex[cnt] = Fls_Qspi_SfdpConfigsCount;
+            Fls_Qspi_SfdpConfigsCount++;
+        }
+#endif
+#endif
+
+        /* Configure the AHB reads for flash unit "cnt" */
+        if ( (STATUS_QSPI_IP_SUCCESS == status) && ((boolean)TRUE == (*(Fls_pConfigPtr->pFlsQspiCfgConfig->paAHBReadCfg))[cnt]) )
+        {
+            status = Qspi_Ip_AhbReadEnable( ((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[cnt]).qspiInstance );
+        }
+
+        if (STATUS_QSPI_IP_SUCCESS != status)
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
+/*
+ * Function Name : Fls_IPW_CheckDevicesId
+ * Description   : Check the identification of the external flash device against the configured one
+*/
+static boolean Fls_IPW_CheckDevicesId(void)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    boolean bRetVal = (boolean)TRUE;
+    const Qspi_Ip_MemoryConfigType * pConfig;
+    uint32 readId = 0U;
+    uint8 cnt;
+
+    for (cnt = 0U; cnt < Fls_pConfigPtr->pFlsQspiCfgConfig->u8FlashUnitsCount; cnt++)
+    {
+        /* Get configuration for current QSPI device */
+        pConfig = Fls_IPW_GetExtFlashConfig(cnt);
+
+        /* If enabled, check identification of the external flash device */
+        if (QSPI_IP_LUT_INVALID != pConfig->readIdSettings.readIdLut)
+        {
+            status = Qspi_Ip_ReadId(cnt, (uint8 *)&readId);
+            /* Compare current device's ID with the corresponding configuration */
+            if ( (STATUS_QSPI_IP_SUCCESS != status) || (readId != pConfig->readIdSettings.readIdExpected) )
+            {
+                (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_INIT_ID, FLS_E_UNEXPECTED_FLASH_ID);
+                bRetVal = (boolean)FALSE;
+                break;
+            }
+        }
+    }
+    return bRetVal;
+}
+
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+/*
+ * Function Name : Fls_IPW_Init
+ * Description   : Initialize Fls module
+ * @implements     Fls_IPW_Init_Activity
+*/
+void Fls_IPW_Init(void)
+{
+    Fls_eLLDJobResult = MEMIF_JOB_OK;
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+    Qspi_Ip_StatusType status;
+    boolean bCheckId = (boolean)FALSE;
+
+    /* Initialize QSPI controllers */
+    status = Fls_IPW_InitControllers();
+
+    /* Initialize external flash devices */
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        status = Fls_IPW_InitMemories();
+    }
+
+    /* Check the hardware ID of the external flash devices */
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        bCheckId = Fls_IPW_CheckDevicesId();
+    }
+
+    if ((boolean)TRUE == bCheckId)
+    {
+        Fls_eLLDJobResult = MEMIF_JOB_OK;
+    }
+    else
+    {
+        Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+    }
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    if (MEMIF_JOB_OK == Fls_eLLDJobResult)
+    {
+       if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_Init(Fls_pConfigPtr->pFlsInternalCfgConfig))
+        {
+            Fls_eLLDJobResult = MEMIF_JOB_OK;
+        }
+        else
+        {
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+        }
+    }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+    Fls_eLLDJob = FLASH_JOB_NONE;
+}
+
+/*
+ * Function Name : Fls_IPW_AbortSuspended
+ * Description   : Abort suspended Fls module
+ * @implements     Fls_IPW_AbortSuspended_Activity
+*/
+void Fls_IPW_AbortSuspended(void)
+{
+#if (FLS_QSPI_SECTORS_CONFIGURED == STD_ON)
+    Fls_HwChType eHwCh;
+    Fls_SectorIndexType u32SectorIndexIter;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 flashInstance;
+    uint32 controllerInstance;
+    uint32 lastFlashInstance = FLS_DEVICE_INSTANCE_INVALID;
+
+    for (u32SectorIndexIter = Fls_u32JobSectorIt; u32SectorIndexIter <= Fls_u32JobSectorEnd; u32SectorIndexIter++ )
+    {
+        /* Get channel type(INTERNAL, EXTERNAL_A1, A2,...) to determine the HW IP used(internal or external flash). */
+        eHwCh = (*(Fls_pConfigPtr->paHwCh))[u32SectorIndexIter];
+         /* Get external flash instance */
+        flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[u32SectorIndexIter];
+
+        /* Check if this channel already was checked before */
+        if ( (FLS_CH_QSPI == eHwCh) && (flashInstance != lastFlashInstance) )
+        {
+            lastFlashInstance = flashInstance;
+            /* Get controller instance */
+            controllerInstance = ((*(Fls_pConfigPtr->pFlsQspiCfgConfig->paFlashConnectionCfg))[flashInstance]).qspiInstance;
+
+            /* Prepare timeout counter */
+            Fls_Qspi_u32ElapsedTicks = 0U;
+            Fls_Qspi_u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_CMD_COMPLETE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+            Fls_Qspi_u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+            /* Wait for the controller to become idle */
+            do
+            {
+                /* Add Fault Injection point for FR_ILLINE flag */
+                MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_ABORTSUSPEND);
+
+                status = Qspi_Ip_ControllerGetStatus(controllerInstance);
+                Fls_Qspi_u32ElapsedTicks += OsIf_GetElapsed(&Fls_Qspi_u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+                if ((STATUS_QSPI_IP_BUSY == status) && (Fls_Qspi_u32ElapsedTicks >= Fls_Qspi_u32TimeoutTicks))
+                {
+                    status = STATUS_QSPI_IP_TIMEOUT;
+                }
+            }
+            while (STATUS_QSPI_IP_BUSY == status);
+
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                /* Check that external memory is idle */
+                if (STATUS_QSPI_IP_SUCCESS != Qspi_Ip_GetMemoryStatus(flashInstance))
+                {
+                    /* Reset external memory */
+                    status = Qspi_Ip_Reset(flashInstance);
+                }
+            }
+
+            if (STATUS_QSPI_IP_SUCCESS != status)
+            {
+                /*Exit for-loop*/
+                Fls_eLLDJob = FLASH_JOB_NONE;
+                Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+                break;
+            }
+        }
+    }
+
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+}
+
+void Fls_IPW_ClearHVJob(void)
+{
+    /* Hardware did not support this feature */
+}
+
+#if (FLS_CANCEL_API == STD_ON )
+
+/*
+ * Function Name : Fls_IPW_Cancel
+ * Description   : Cancel Fls module
+ * @implements     Fls_IPW_Cancel_Activity
+*/
+void Fls_IPW_Cancel(void)
+{
+    Fls_HwChType eHwCh;
+
+    /* Get channel type(INTERNAL, QSPI,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+
+    if (MEMIF_JOB_PENDING == Fls_eLLDJobResult )
+    {
+#if (FLS_INTERNAL_SECTORS_CONFIGURED == STD_ON)
+        if (FLS_CH_INTERN == eHwCh)
+        {
+            if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_Abort())
+            {
+                /* Mark the job as canceled.*/
+                Fls_eLLDJob = FLASH_JOB_NONE;
+                Fls_eLLDJobResult = MEMIF_JOB_CANCELED;
+            }
+        }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+        if (FLS_CH_QSPI == eHwCh)
+        {
+            /* Mark the job as canceled.*/
+            Fls_eLLDJob = FLASH_JOB_NONE;
+            Fls_eLLDJobResult = MEMIF_JOB_CANCELED;
+        }
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+    }
+    else
+    {
+        /* no hardware job (asynchronous) is pending, do nothing */
+
+        /* Mark the internal job as canceled.*/
+        Fls_eLLDJob = FLASH_JOB_NONE;
+        Fls_eLLDJobResult = MEMIF_JOB_CANCELED;
+    }
+}
+#endif
+
+
+/**
+* @brief          Process ongoing erase or write hardware job.
+* @details        In case Async Operation is ongoing this function will complete the following job:
+*                 - Erase
+*                 - Erase on Interleaved sectors
+*                 - Write
+*                 - Erase blank Check
+*
+* @note           Dem_ReportErrorStatus(Fls_pConfigPtr->Fls_E_EraseFailedCfg.id, DEM_EVENT_STATUS_FAILED)
+*                 when erase operation failed due to hardware error.
+*                 Dem_ReportErrorStatus(Fls_pConfigPtr->Fls_E_WriteFailedCfg.id, DEM_EVENT_STATUS_FAILED)
+*                 when write operation failed due to hardware error
+* @implements     Fls_IPW_LLDMainFunction_Activity
+*/
+void Fls_IPW_LLDMainFunction( void )
+{
+    Fls_HwChType eHwCh;
+
+    /* Get channel type(INTERNAL, EXTERNAL_A1, A2,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+
+    if (MEMIF_JOB_PENDING == Fls_eLLDJobResult)
+    {
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+        if (FLS_CH_INTERN == eHwCh)
+        {
+            Fls_IPW_LLDMainFunctionFtfcJobs();
+        }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+        if (FLS_CH_QSPI == eHwCh)
+        {
+            Fls_IPW_LLDMainFunctionQspiJobs();
+        }
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+    }   /* if (MEMIF_JOB_PENDING == Fls_eLLDJobResult) */
+    else
+    {
+        /* no hardware job (asynchronous) is pending, do nothing */
+    }
+}
+
+
+/**
+* @brief          IP wrapper sector read function.
+* @details        Route the read job to appropriate low level IP function.
+* @implements     Fls_IPW_SectorRead_Activity
+*/
+Fls_LLDReturnType Fls_IPW_SectorRead(const Fls_AddressType u32SectorOffset,
+                                     const Fls_AddressType u32Length,
+                                     uint8 * pJobDataDestPtr,
+                                     const uint8 *pJobDataSrcPtr
+                                    )
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    Fls_HwChType eHwCh;
+#if ( (FLS_COMPARE_API == STD_OFF) && (FLS_BLANK_CHECK_API == STD_OFF) )
+    (void)pJobDataSrcPtr;
+#endif  /* (( FLS_COMPARE_API == STD_ON ) || ( FLS_BLANK_CHECK_API == STD_ON )) */
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_ERROR;
+    uint32 u32ReadStartAddress = 0U;
+#endif /* #if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 flashInstance;
+    Fls_AddressType u32ReadAddr;
+#endif /* #if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+    /* Get channel type(INTERNAL, QSPI,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+
+    /* Decide the IP used: internal flash or external QSPI */
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    if (FLS_CH_INTERN == eHwCh)
+    {
+        /* Get the base address of the sector. */
+        u32ReadStartAddress = (uint32)(*((*(Fls_pConfigPtr->pSectorList))[Fls_u32JobSectorIt])).pSectorStartAddressPtr;
+        /* Add the offset */
+        u32ReadStartAddress += u32SectorOffset;
+
+        /* Decide whether the job is a Read, a compare, or a blank check. */
+        if (NULL_PTR != pJobDataDestPtr)
+        {
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+            if ( NULL_PTR != Fls_pConfigPtr->FlsReadFunctionCallout )
+            {
+                /* Users will have to define Callout function to call Fls_ReadEachBlock to read data from memory */
+                eReturnCode = Fls_IPW_CopyBlock(u32ReadStartAddress, u32Length, pJobDataDestPtr, NULL_PTR);
+            }
+            else
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+            {
+                eReturnCode = Ftfc_Fls_Ip_Read(u32ReadStartAddress, pJobDataDestPtr, u32Length);
+            }
+        }
+#if (( FLS_COMPARE_API == STD_ON ) || ( FLS_BLANK_CHECK_API == STD_ON ))
+        else
+        {
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+            if ( NULL_PTR != Fls_pConfigPtr->FlsReadFunctionCallout )
+            {
+                /* Users will have to define Callout function to call Fls_ReadEachBlock to read data from memory */
+                eReturnCode = Fls_IPW_CopyBlock(u32ReadStartAddress, u32Length, NULL_PTR, pJobDataSrcPtr);
+            }
+            else
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+            {
+                eReturnCode = Ftfc_Fls_Ip_Compare(u32ReadStartAddress, pJobDataSrcPtr, u32Length);
+            }
+        }
+#endif  /* (( FLS_COMPARE_API == STD_ON ) || ( FLS_BLANK_CHECK_API == STD_ON )) */
+
+        eLldRetVal = Fls_IPW_TranslateReturnCode(eReturnCode);
+    }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    if (FLS_CH_QSPI == eHwCh)
+    {
+        /* Get external flash instance */
+        flashInstance = (*(Fls_pConfigPtr->pFlsQspiCfgConfig->u8SectFlashUnit))[Fls_u32JobSectorIt];
+        /* Initialize job parameters */
+        /* Compute target address : sector address + offset */
+        u32ReadAddr = (*(Fls_pConfigPtr->paSectorHwAddress))[Fls_u32JobSectorIt] + u32SectorOffset;
+
+        /* Fault Injection point for testing when read data is executing */
+        MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_DATA_IPREAD);
+
+        /* Decide whether the job is a Read, a compare, or a blank check. */
+        if (NULL_PTR != pJobDataDestPtr)
+        {
+            status = Qspi_Ip_Read(flashInstance, u32ReadAddr, pJobDataDestPtr, u32Length);
+        }
+#if ( FLS_COMPARE_API == STD_ON )
+        else if (NULL_PTR != pJobDataSrcPtr)
+        {
+            status = Qspi_Ip_ProgramVerify(flashInstance, u32ReadAddr, pJobDataSrcPtr, u32Length);
+        }
+#endif /*#if ( FLS_COMPARE_API == STD_ON ) */
+#if ( FLS_BLANK_CHECK_API == STD_ON )
+        else
+        {
+            status = Qspi_Ip_EraseVerify(flashInstance, u32ReadAddr, u32Length);
+        }
+#endif /*#if ( FLS_BLANK_CHECK_API == STD_ON ) */
+        (void)pJobDataSrcPtr;
+
+        if (STATUS_QSPI_IP_SUCCESS != status)
+        {
+#if (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON)
+            /*check timeout after checking status fail*/
+            if (STATUS_QSPI_IP_TIMEOUT == status)
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+            }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+#if ( FLS_COMPARE_API == STD_ON )
+            if (STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY == status)
+            {
+                eLldRetVal = FLASH_E_BLOCK_INCONSISTENT;
+            }
+            else
+            {
+                eLldRetVal = FLASH_E_FAILED;
+            }
+#else
+            eLldRetVal = FLASH_E_FAILED;
+#endif /*#if ( FLS_COMPARE_API == STD_ON ) */
+        }
+        else
+        {
+            eLldRetVal = FLASH_E_OK;
+        }
+    } /* FLS_CH_QSPI == eHwCh */
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+    return eLldRetVal;
+}
+
+/**
+* @brief          IP wrapper sector erase function.
+* @details        Route the erase job to appropriate low level IP function.
+* @implements     Fls_IPW_SectorErase_Activity
+*/
+Fls_LLDReturnType Fls_IPW_SectorErase(const Fls_AddressType u32SectorOffset,
+                                      const Fls_LengthType u32PhysicalSectorSize,
+                                      const boolean bAsynch
+                                     )
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    Fls_HwChType eHwCh;
+
+    /* Get channel type(INTERNAL, QSPI,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+
+    /* Decide the IP used: internal flash or external QSPI */
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    if (FLS_CH_INTERN == eHwCh)
+    {
+        eLldRetVal = Fls_IPW_SectorEraseFtfcJobs(bAsynch, u32SectorOffset);
+    }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    if (FLS_CH_QSPI == eHwCh)
+    {
+        eLldRetVal = Fls_IPW_SectorEraseQspiJobs(bAsynch, u32SectorOffset, u32PhysicalSectorSize);
+    }
+#else
+    /*Fix warning: unused variable*/
+    (void)u32PhysicalSectorSize;
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+    return eLldRetVal;
+}
+
+/**
+* @brief          IP wrapper sector write function.
+* @details        Route the write job to appropriate low level IP function.
+* @implements     Fls_IPW_SectorWrite_Activity
+*/
+Fls_LLDReturnType Fls_IPW_SectorWrite(const Fls_AddressType u32SectorOffset,
+                                      const Fls_AddressType u32Length,
+                                      const uint8 *pJobDataSrcPtr,
+                                      const boolean bAsynch
+                                     )
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    Fls_HwChType eHwCh;
+
+    /* Get channel type(INTERNAL, QSPI,...) to determine the HW IP used(internal or external flash). */
+    eHwCh = (*(Fls_pConfigPtr->paHwCh))[Fls_u32JobSectorIt];
+
+    /* Decide the IP used: internal flash or external QSPI */
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+    if (FLS_CH_INTERN == eHwCh)
+    {
+        eLldRetVal = Fls_IPW_SectorWriteFtfcJobs(u32SectorOffset, u32Length, pJobDataSrcPtr, bAsynch);
+    }
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+
+#if (STD_ON == FLS_QSPI_SECTORS_CONFIGURED)
+    if (FLS_CH_QSPI == eHwCh)
+    {
+        eLldRetVal = Fls_IPW_SectorWriteQspiJobs(u32SectorOffset, u32Length, pJobDataSrcPtr, bAsynch);
+    }
+#endif /* (STD_ON == FLS_QSPI_SECTORS_CONFIGURED) */
+
+    return eLldRetVal;
+}
+
+#if (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED)
+static inline void Fls_IPW_LLDMainFunctionFtfcJobs_CheckEraseStatus(Ftfc_Fls_Ip_StatusType status)
+{
+    if (STATUS_FTFC_FLS_IP_BUSY != status)
+    {
+        /* Erase operation finished at IP level - successfully or with errors or timed out */
+        if (STATUS_FTFC_FLS_IP_SUCCESS != status)
+        {
+            /* Sector lock was ok, but IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_ERASE_FAILED);
+            /* Report Runtime error when comparing is incorrect */
+            if (STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK == status)
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_ERASE_FAILED);
+            }
+        #if (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON)
+            /*check timeout after checking status fail*/
+            else if (STATUS_FTFC_FLS_IP_ERROR_TIMEOUT == status)
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+            }
+            else
+            {
+                /* Do nothing - blank statement added to fulfil MISRA Rule 15.7 */
+            }
+        #endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+        }
+        else
+        {
+            /* Everything was ok */
+            Fls_eLLDJob = FLASH_JOB_NONE;
+            Fls_eLLDJobResult = MEMIF_JOB_OK;
+            if ((Fls_u32JobAddrIt > ((*(Fls_pConfigPtr->paSectorEndAddr))[Fls_u32JobSectorIt])))
+            {
+                /* Move on to the next sector */
+                Fls_u32JobSectorIt++;
+            }
+        }
+    }
+}
+
+
+static inline void Fls_IPW_LLDMainFunctionFtfcJobs_CheckWriteStatus(Ftfc_Fls_Ip_StatusType status)
+{
+    if (STATUS_FTFC_FLS_IP_BUSY != status)
+    {
+        /* Write operation finished at IP level - successfully or with errors or timed out */
+        if (STATUS_FTFC_FLS_IP_SUCCESS != status)
+        {
+            /* IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            /* An error will be reported */
+            (void)Det_ReportTransientFault((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_WRITE_FAILED);
+
+            /* Report errors due to incorrect verifying writing */
+            if (STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY == status)
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_WRITE_FAILED);
+            }
+        #if (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON)
+            /*check timeout after checking status fail*/
+            else if (STATUS_FTFC_FLS_IP_ERROR_TIMEOUT == status)
+            {
+                (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+            }
+            else
+            {
+                /* Do nothing - blank statement added to fulfil MISRA Rule 15.7 */
+            }
+        #endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+        }
+        else
+        {
+            /* Everything was ok */
+            Fls_eLLDJobResult = MEMIF_JOB_OK;
+        }
+    }
+}
+
+
+static void Fls_IPW_LLDMainFunctionFtfcJobs(void)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_ERROR;
+
+    /* some hardware job (asynchronous) is pending */
+    if (FLASH_JOB_ERASE == Fls_eLLDJob )
+    {
+        eReturnCode = Ftfc_Fls_Ip_SectorEraseStatus();
+
+        Fls_IPW_LLDMainFunctionFtfcJobs_CheckEraseStatus(eReturnCode);
+    }
+    /* Write hardware job (asynchronous) is pending */
+    else if (FLASH_JOB_WRITE == Fls_eLLDJob )
+    {
+        eReturnCode = Ftfc_Fls_Ip_WriteStatus();
+
+        Fls_IPW_LLDMainFunctionFtfcJobs_CheckWriteStatus(eReturnCode);
+    }
+    else
+    {
+        /* Do nothing - should not happen in Fully Trusted Environment;
+           'else' clause added to fulfil MISRA Rule 14.10 */
+    }
+}
+
+
+static inline Fls_LLDReturnType Fls_IPW_SectorEraseFtfcJobs(boolean bAsynch, Fls_AddressType u32SectorOffset)
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    uint32 u32SectorStartAddress;
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_ERROR;
+
+    /* Get the base address of the sector. */
+    u32SectorStartAddress = (uint32)(*((*(Fls_pConfigPtr->pSectorList))[Fls_u32JobSectorIt])).pSectorStartAddressPtr;
+
+    /* set synch/Asynch at IP layer base on bAynch */
+    Ftfc_Fls_Ip_SetAsyncMode(bAsynch);
+    eReturnCode = Ftfc_Fls_Ip_SectorErase(u32SectorStartAddress + u32SectorOffset);
+
+    if ((STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode) && (FALSE == bAsynch))
+    {
+        Fls_IPW_CallAccessCodeErase();
+
+        /* check status of erase hardware */
+        eReturnCode = Ftfc_Fls_Ip_SectorEraseStatus();
+        if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+        {
+            /* Sector lock was ok, but IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            eLldRetVal = Fls_IPW_TranslateReturnCode(eReturnCode);
+        }
+        else
+        {
+            /* Everything was ok */
+            Fls_eLLDJobResult = MEMIF_JOB_OK;
+            eLldRetVal = FLASH_E_OK;
+        }
+    }
+    else
+    {
+        if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+        {
+            /* IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            eLldRetVal = Fls_IPW_TranslateReturnCode(eReturnCode);
+        }
+        else
+        {
+            eLldRetVal = FLASH_E_PENDING;
+            Fls_eLLDJob = FLASH_JOB_ERASE;
+            Fls_eLLDJobResult = MEMIF_JOB_PENDING;
+        }
+    }
+
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+    /*check timeout after perform erase*/
+    if (STATUS_FTFC_FLS_IP_ERROR_TIMEOUT == eReturnCode)
+    {
+        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+    }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+
+    return eLldRetVal;
+}
+
+
+static inline Fls_LLDReturnType Fls_IPW_SectorWriteFtfcJobs(const Fls_AddressType u32SectorOffset,
+                                                            const Fls_AddressType u32Length,
+                                                            const uint8 *pJobDataSrcPtr,
+                                                            const boolean bAsynch
+                                                           )
+{
+    Fls_LLDReturnType eLldRetVal = FLASH_E_FAILED;
+    uint32 u32WriteStartAddress;
+    Ftfc_Fls_Ip_StatusType eReturnCode;
+
+    /* Get the base address of the sector. */
+    u32WriteStartAddress = (uint32)(*((*(Fls_pConfigPtr->pSectorList))[Fls_u32JobSectorIt])).pSectorStartAddressPtr;
+    /* Add the offset */
+    u32WriteStartAddress += u32SectorOffset;
+
+    /* set synch/Asynch at IP layer base on bAynch */
+    Ftfc_Fls_Ip_SetAsyncMode(bAsynch);
+    eReturnCode = Ftfc_Fls_Ip_Write(u32WriteStartAddress, pJobDataSrcPtr, u32Length);
+    /* On sync */
+    if ((STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode) && (FALSE == bAsynch))
+    {
+        Fls_IPW_CallAccessCodeWrite();
+
+        /* Check status of write hardware */
+        eReturnCode = Ftfc_Fls_Ip_WriteStatus();
+        if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+        {
+            /* IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            eLldRetVal = Fls_IPW_TranslateReturnCode(eReturnCode);
+        }
+        else
+        {
+            eLldRetVal = FLASH_E_OK;
+        }
+    }
+    else
+    {
+        if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+        {
+            /* IP operation failed */
+            Fls_eLLDJobResult = MEMIF_JOB_FAILED;
+            eLldRetVal = Fls_IPW_TranslateReturnCode(eReturnCode);
+        }
+        else
+        {
+            eLldRetVal = FLASH_E_PENDING;
+            Fls_eLLDJob = FLASH_JOB_WRITE;
+            Fls_eLLDJobResult = MEMIF_JOB_PENDING;
+        }
+    }
+#if ( (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON))
+    /*check timeout after performing write*/
+    if (STATUS_FTFC_FLS_IP_ERROR_TIMEOUT == eReturnCode)
+    {
+        (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_TIMEOUT);
+    }
+#endif /* (FLS_TIMEOUT_SUPERVISION_ENABLED == STD_ON) */
+
+    return eLldRetVal;
+}
+
+static inline void Fls_IPW_CallAccessCodeWrite(void)
+{
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+    if (TRUE == Fls_bACloaded)
+    {
+        /* Sync mode - wait for IP to finish */
+        FLASH_AC_CALL(Fls_pConfigPtr->acWritePtr, Fls_AcWritePtrType)(Fls_pConfigPtr->acCallBackPtr);
+    }
+    else
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+    {
+        Ftfc_Fls_Ip_AccessCode(Fls_pConfigPtr->acCallBackPtr);
+    }
+}
+
+
+static inline void Fls_IPW_CallAccessCodeErase(void)
+{
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+    if (TRUE == Fls_bACloaded)
+    {
+        /* Sync mode - wait for IP to finish */
+        FLASH_AC_CALL(Fls_pConfigPtr->acErasePtr, Fls_AcErasePtrType)(Fls_pConfigPtr->acCallBackPtr);
+    }
+    else
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+    {
+        Ftfc_Fls_Ip_AccessCode(Fls_pConfigPtr->acCallBackPtr);
+    }
+}
+
+
+static Fls_LLDReturnType Fls_IPW_TranslateReturnCode(Ftfc_Fls_Ip_StatusType eReturnCode)
+{
+    Fls_LLDReturnType eLldRetVal;
+
+    /* Translate the return code from IPV to HLD */
+    switch (eReturnCode)
+    {
+        case STATUS_FTFC_FLS_IP_SUCCESS:
+            /* Operation succeeded */
+            eLldRetVal = FLASH_E_OK;
+            break;
+
+        case STATUS_FTFC_FLS_IP_BUSY:
+            /* Operation is pending */
+            eLldRetVal = FLASH_E_PENDING;
+            break;
+
+        case STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK:
+            /* Content of flash memory doesn't match with erased value */
+            eLldRetVal = FLASH_E_BLOCK_INCONSISTENT;
+            (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_ERASE_FAILED);
+            break;
+
+        case STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY:
+            /* Content of flash memory doesn't match with data buffer */
+            eLldRetVal = FLASH_E_BLOCK_INCONSISTENT;
+            (void)Det_ReportRuntimeError((uint16)FLS_MODULE_ID, FLS_INSTANCE_ID, FLS_MAINFUNCTION_ID, FLS_E_VERIFY_WRITE_FAILED);
+            break;
+
+        default:
+            /* Operation failed due to hardware error */
+            eLldRetVal = FLASH_E_FAILED;
+            break;
+    }
+
+    return eLldRetVal;
+}
+
+#if ( (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) )
+Fls_CompHandlerReturnType Fls_IPW_DsiHandler(const Fls_ExceptionDetailsType  *pExceptionDetailsPtr)
+{
+    Fls_CompHandlerReturnType eLldRetVal;
+
+    #if ( FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON )
+    eLldRetVal = Ftfc_Fls_Ip_DsiHandler(pExceptionDetailsPtr);
+    #else
+    (void)pExceptionDetailsPtr;  /* Unused variable */
+    eLldRetVal = Ftfc_Fls_Ip_DsiHandler();
+    #endif
+
+    return eLldRetVal;
+}
+#endif /* (STD_ON == FLS_ECC_CHECK) || (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS) */
+
+#if (STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS)
+/**
+ * Function Name : Fls_IPW_CopyBlock
+ * Description   : Call the FlsReadFunctionCallout where user can schedule a task which performs the copy operation (Fls_ReadEachBlock)
+ *
+ */
+static Ftfc_Fls_Ip_StatusType Fls_IPW_CopyBlock(uint32 u32LogicalAddress, uint32 u32Length, uint8 *pDestAddressPtr, const uint8 *pSourceAddressPtr)
+{
+    /* Prepare for the copy operation */
+    Fls_CopyDescr.u32ReadStartAddress = u32LogicalAddress;
+    Fls_CopyDescr.u32Length           = u32Length;
+    Fls_CopyDescr.pDataDest           = pDestAddressPtr;
+    Fls_CopyDescr.pDataSource         = pSourceAddressPtr;
+    Fls_CopyDescr.eStatus             = STATUS_FTFC_FLS_IP_ERROR;
+
+    /* This callout can schedule a task which performs the copy operation. The amount of data to copy (u32Length) can be arbitrarily long.
+     * If the copy fails because of the expected exception, the task is forcibly terminated from the ProtectionHook().
+     */
+    Fls_pConfigPtr->FlsReadFunctionCallout();
+
+    return Fls_CopyDescr.eStatus;
+}
+
+/**
+ * Function Name : Fls_IPW_ReadEachBlock
+ * Description   : Performs the actual copy operation.
+ */
+void Fls_IPW_ReadEachBlock(void)
+{
+    if (NULL_PTR != Fls_CopyDescr.pDataDest)
+    {
+        /* Read operation */
+        Fls_CopyDescr.eStatus = Ftfc_Fls_Ip_Read(Fls_CopyDescr.u32ReadStartAddress, Fls_CopyDescr.pDataDest, Fls_CopyDescr.u32Length);
+    }
+    else
+    {
+        /* Compare operation */
+        Fls_CopyDescr.eStatus = Ftfc_Fls_Ip_Compare(Fls_CopyDescr.u32ReadStartAddress, Fls_CopyDescr.pDataSource, Fls_CopyDescr.u32Length);
+    }
+}
+#endif /* STD_ON == FLS_ECC_CHECK_BY_AUTOSAR_OS */
+
+#endif /* (STD_ON == FLS_INTERNAL_SECTORS_CONFIGURED) */
+
+#if ( STD_ON == FLS_AC_LOAD_ON_JOB_START )
+Fls_BlockNumberOfSectorType Fls_IPW_GetBlockNumberFromAddress(Fls_AddressType targetAddress)
+{
+    /* Get block number from address  */
+    return (Fls_BlockNumberOfSectorType)Ftfc_Fls_Ip_GetBlockNumberFromAddress((uint32)targetAddress);
+}
+#endif /* STD_ON == FLS_AC_LOAD_ON_JOB_START */
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Ftfc_Fls_Ip.c

@@ -0,0 +1,1939 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Ftfc_Fls_Ip.c
+*
+*   @addtogroup FTFC_FLS_IP FTFC IP Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Ftfc_Fls_Ip.h"
+#if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+#include "Cache_Ip.h"
+#endif /* FTFC_FLS_IP_SYNCRONIZE_CACHE */
+
+#if (STD_ON == FTFC_ENABLE_USER_MODE_SUPPORT)
+#define USER_MODE_REG_PROT_ENABLED      STD_ON
+#include "RegLockMacros.h"
+#endif /* #if (STD_ON == FTFC_ENABLE_USER_MODE_SUPPORT) */
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+#include "OsIf.h"
+#endif
+
+#include "Mcal.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_VENDOR_ID_C                    43
+#define FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C     4
+#define FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C     4
+#define FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_C  0
+#define FTFC_FLS_IP_SW_MAJOR_VERSION_C             1
+#define FTFC_FLS_IP_SW_MINOR_VERSION_C             0
+#define FTFC_FLS_IP_SW_PATCH_VERSION_C             0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Ftfc_Fls_Ip header file are of the same vendor */
+#if (FTFC_FLS_IP_VENDOR_ID_C != FTFC_FLS_IP_VENDOR_ID_H)
+    #error "Ftfc_Fls_Ip.c and Ftfc_Fls_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip.c and Ftfc_Fls_Ip.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip header file are of the same Software version */
+#if ((FTFC_FLS_IP_SW_MAJOR_VERSION_C != FTFC_FLS_IP_SW_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_SW_MINOR_VERSION_C != FTFC_FLS_IP_SW_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_SW_PATCH_VERSION_C != FTFC_FLS_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip.c and Ftfc_Fls_Ip.h are different"
+#endif
+
+#if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+    #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+        /* Check if current file and Cache_Ip header file are of the same Autosar version */
+        #if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C != CACHE_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+             (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C != CACHE_IP_AR_RELEASE_MINOR_VERSION_H) \
+            )
+            #error "Autosar Version Numbers of Ftfc_Fls_Ip.c and Cache_Ip.h are different"
+        #endif
+    #endif
+#endif /* FTFC_FLS_IP_SYNCRONIZE_CACHE */
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+    #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+        /* Check if current file and OsIf header file are of the same Autosar version */
+        #if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+             (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "AutoSar Version Numbers of Ftfc_Fls_Ip.c and OsIf.h are different"
+        #endif
+    #endif
+#endif
+
+#if (STD_ON == FTFC_ENABLE_USER_MODE_SUPPORT)
+    #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+        /* Check if current file and RegLockMacros.h header file are of the same Autosar version */
+        #if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
+             (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "Autosar Version Numbers of Ftfc_Fls_Ip.c and RegLockMacros.h are different"
+        #endif
+        /* Check if current file and Mcal.h header file are of the same Autosar version */
+        #if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+             (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "Autosar Version Numbers of Ftfc_Fls_Ip.c and Mcal.h are different"
+        #endif
+    #endif
+#endif /* #if (STD_ON == FTFC_ENABLE_USER_MODE_SUPPORT) */
+
+
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#if (FTFC_FLS_IP_INVALID_PREBUF_FROM_RAM == STD_ON)
+#define FLS_START_SEC_RAMCODE
+#else
+#define FLS_START_SEC_CODE
+#endif
+#include "Fls_MemMap.h"
+
+/* The Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram function should be placed and executed from RAM,
+   because it accesses the flash prefetch buffers, which should not be modified while reading code instructions.
+   In practice, this function still works normally from FLASH because it has already loaded to Cache and executed from there.
+   However, on platforms that do not support cache or cache is disabled, this functions must be placed on RAM.
+   For more information, please see the chapter Tips for FLS integration in the Integration Manual.
+ */
+static void Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram(void);
+
+#if (FTFC_FLS_IP_INVALID_PREBUF_FROM_RAM == STD_ON)
+#define FLS_STOP_SEC_RAMCODE
+#else
+#define FLS_STOP_SEC_CODE
+#endif
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+static boolean Ftfc_Fls_Ip_CheckValidRange(uint32 startAddress, uint32 length);
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ReadPreCheck(uint32 u32SrcAddress, const uint8 *pDestAddressPtr, uint32 u32Length);
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ComparePreCheck(uint32 u32SrcAddress, uint32 u32Length);
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorErasePreCheck(uint32 u32SectorStartAddress);
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WritePreCheck(uint32 u32DestAddress, const uint8 *pSourceAddressPtr, uint32 u32Length);
+
+static void Ftfc_Fls_Ip_InvalidPrefetchBuff(void);
+
+static void Ftfc_Fls_Ip_ClearErrorFlags(void);
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ControllerBusy(void);
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_CtrlStatus(void);
+
+static void Ftfc_Fls_Ip_LoadFCCOBParams(const uint32 u32PhysicAddr,
+                                        const uint8 * pDataAddr,
+                                        const uint8 u8FCCOBCmdId
+                                       );
+
+static uint32 Ftfc_Fls_Ip_ConvertSysToFTFEAddr(uint32 u32SystemAddress);
+static void Ftfc_Fls_Ip_FlashAccessCalloutStart(void);
+static void Ftfc_Fls_Ip_FlashAccessCalloutFinish(void);
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WaitForOperationFinish(void);
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_CheckFProtReg(uint32 u32SectStartAddr);
+
+static uint32 Ftfc_Fls_ComputeReadSize(uint32 srcAddress, uint32 desAddress, uint32 byteRemain);
+
+static void Ftfc_Fls_Ip_ProgramVerify(uint32 address, const uint8 * data, uint32 size);
+static void Ftfc_Fls_Ip_EraseVerify(uint32 address, uint32 size);
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ReadStatus(boolean compareStatus);
+
+static inline uint32 Ftfc_Fls_Ip_ReadData32(uint32 address);
+static inline uint16 Ftfc_Fls_Ip_ReadData16(uint32 address);
+static inline uint8 Ftfc_Fls_Ip_ReadData8(uint32 address);
+
+static void Ftfc_Fls_Ip_ReadData(uint32 readSize,
+                                 uint32 readAddress,
+                                 uint32 desAddress,
+                                 uint8 *desAddressPtr
+                                );
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Flash_AbortSuspended(void);
+
+static void Ftfc_Fls_Ip_CalculateDFlashBitSize(void);
+
+#if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+static void Ftfc_Fls_SynchronizeCache(uint32 address,
+                                      uint32 length
+                                     );
+#endif
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+                                       LOCAL VARIABLES
+==================================================================================================*/
+#define FLS_START_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+/* The amount of DFlash size which is covered by a bit in the Data Flash Protection Register (FDPROT),
+ * which is the total amount of DFlash divided by 8.
+ */
+static uint32 Ftfc_Fls_Ip_u32DFlashBitSizeProt;
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+uint32 Ftfc_Fls_Ip_u32ElapsedTicks;
+uint32 Ftfc_Fls_Ip_u32TimeoutTicks;
+uint32 Ftfc_Fls_Ip_u32CurrentTicks;
+#endif
+
+#if ((STD_ON == FTFC_PROGRAM_VERIFICATION_ENABLED) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+static uint32 Ftfc_Fls_Ip_u32ProgrammedAddress;
+static uint32 Ftfc_Fls_Ip_u32ProgrammedLength;
+#endif
+#if (STD_ON == FTFC_PROGRAM_VERIFICATION_ENABLED)
+static const uint8 *Ftfc_Fls_Ip_pProgrammedData;
+#endif
+
+#if ((STD_ON == FTFC_ERASE_VERIFICATION_ENABLED) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+static uint32 Ftfc_Fls_Ip_u32ErasedSectorAddress;
+#endif
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+#if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+/* Save the most recent memory access address for ECC handling */
+static volatile uint32 Ftfc_Fls_Ip_u32ReadAddressPtr;
+#endif
+#endif
+
+#define FLS_STOP_SEC_VAR_CLEARED_32
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_INIT_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+    /* Save the current read operation status for ECC handling */
+    static volatile Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR;
+#else
+    static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR;
+#endif
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_eWriteStatus = STATUS_FTFC_FLS_IP_ERROR;
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_eEraseStatus = STATUS_FTFC_FLS_IP_ERROR;
+
+#define FLS_STOP_SEC_VAR_INIT_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+/**
+ * @brief Pointer to current flash module configuration set
+ */
+static const Ftfc_ConfigType * Ftfc_Fls_Ip_pConfigPtr;
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_VAR_INIT_BOOLEAN
+#include "Fls_MemMap.h"
+
+static boolean Ftfc_Fls_Ip_Async = TRUE;
+
+#define FLS_STOP_SEC_VAR_INIT_BOOLEAN
+#include "Fls_MemMap.h"
+
+#define FLS_START_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* Base address for Flash Memory Module */
+FTFx_HARDWARE_TYPE * const FTFx_BaseAddress = FTFx_HARDWARE_UNIT;
+
+#define FLS_STOP_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_CalculateDFlashBitSize
+ * Description      Calculates the region size protected by each DPROT bit.
+ *                  The total amount of DFlash size is determined based on the DEPART value, which cannot change in runtime
+ */
+static void Ftfc_Fls_Ip_CalculateDFlashBitSize(void)
+{
+    uint32 u32DFlashSize;
+    uint32 u32RegSimFcfg1;
+    uint32 u32FlexNvmPartSize;
+
+    /* Determine the DFlash size. */
+    u32RegSimFcfg1 = IP_SIM->FCFG1;
+    /* Get the amount of flash allocated to FlexNVM/EEPROM partition, which has to be subtracted from the current Dflash size. */
+    u32FlexNvmPartSize = (uint32)( (u32RegSimFcfg1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT );
+
+    /* Special partition codes for 2048K device. */
+#if (0x80000UL == FTFC_D_FLASH_SIZE)
+/* 512K devices. */
+    if ( (FLASH_FLEXNVM_DFLASH_EEPROM_512_0_V1 == u32FlexNvmPartSize) ||
+         (FLASH_FLEXNVM_DFLASH_EEPROM_DEFAULT  == u32FlexNvmPartSize)
+       )
+    {
+         /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = FTFC_D_FLASH_SIZE;   /*0x80000, 512K*/
+    }
+    else if (FLASH_FLEXNVM_DFLASH_EEPROM_448_64_V1 == u32FlexNvmPartSize)
+    {
+         /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = 0x70000UL;  /* 448K */
+    }
+    else
+    {
+        u32DFlashSize = 0U;     /* Error case, should not be taken. */
+    }
+#elif (0x10000UL == FTFC_D_FLASH_SIZE)
+/* 64K devices. */
+    if ( (FLASH_FLEXNVM_DFLASH_EEPROM_64_0_V1 == u32FlexNvmPartSize) ||
+         (FLASH_FLEXNVM_DFLASH_EEPROM_64_0_V2 == u32FlexNvmPartSize) ||
+         (FLASH_FLEXNVM_DFLASH_EEPROM_DEFAULT == u32FlexNvmPartSize)
+       )
+    {
+        /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = FTFC_D_FLASH_SIZE;
+    }
+    else if ( (FLASH_FLEXNVM_DFLASH_EEPROM_32_32_V1 == u32FlexNvmPartSize) ||
+              (FLASH_FLEXNVM_DFLASH_EEPROM_32_32_V2 == u32FlexNvmPartSize)
+            )
+    {
+         /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = 0x8000UL;  /* 32K */
+    }
+    else if (FLASH_FLEXNVM_DFLASH_EEPROM_16_48_V1 == u32FlexNvmPartSize)
+    {
+         /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = 0x4000UL;  /* 16K */
+    }
+    else
+    {
+        /*FLASH_FLEXNVM_DFLASH_EEPROM_0_64_V1*/
+        /*FLASH_FLEXNVM_DFLASH_EEPROM_0_64_V2*/
+        u32DFlashSize = 0U;     /* No data flash configured. */
+    }
+#elif (0x8000UL == FTFC_D_FLASH_SIZE)
+/* 32K devices. */
+    if ( (FLASH_FLEXNVM_DFLASH_EEPROM_32_0_V1 == u32FlexNvmPartSize) ||
+         (FLASH_FLEXNVM_DFLASH_EEPROM_32_0_V2 == u32FlexNvmPartSize) ||
+         (FLASH_FLEXNVM_DFLASH_EEPROM_DEFAULT == u32FlexNvmPartSize)
+       )
+    {
+        /* FlexNvm configured for all Data Flash (no EEPROM partitioned) */
+        u32DFlashSize = FTFC_D_FLASH_SIZE;
+    }
+
+    else if (FLASH_FLEXNVM_DFLASH_EEPROM_8_24_V1 == u32FlexNvmPartSize)
+    {
+         /* FlexNvm configured 8K Data Flash (24K EEPROM partitioned) */
+        u32DFlashSize = 0x2000UL;  /* 8K */
+    }
+    else
+    {
+        /*FLASH_FLEXNVM_DFLASH_EEPROM_0_32_V1*/
+        /*FLASH_FLEXNVM_DFLASH_EEPROM_0_32_V2*/
+        u32DFlashSize = 0U;     /* No data flash configured. */
+    }
+#endif
+
+    /* Each bit in the FDPROT register protects an 8th of the available DFlash. */
+    Ftfc_Fls_Ip_u32DFlashBitSizeProt = u32DFlashSize >> 3UL;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_CheckFProtReg
+ * Description      Checks if the input address is protected or not, before executing the write or erase operation.
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_CheckFProtReg(uint32 u32SectStartAddr)
+{
+    uint32 u32PFlashBitSize;     /* The amount of Pflash size which is covered by a bit in a protection register, which is the total amount of Pflash divided by 32. */
+    uint32 u32PFlashRegSize;     /* The amount of Pflash size which is covered by a protection register, which is the total amount of Pflash divided by 4. */
+    uint8  u8SecRegProtBitPos;
+    uint8  u8RegProtNo;
+    Ftfc_Fls_Ip_StatusType eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+
+    /* Determine if it is a Pflash or Dflash data sector. */
+    if ( u32SectStartAddr >= (FTFC_P_FLASH_BASE_ADDR + FTFC_P_FLASH_SIZE))                /* if NOT a P-FLASH addr... */
+    {
+        if ( (u32SectStartAddr < FTFC_D_FLASH_BASE_ADDR) ||
+             (u32SectStartAddr >= (FTFC_D_FLASH_BASE_ADDR + FTFC_D_FLASH_SIZE))           /* ...and also NOT a D-FLASH addr... */
+           )
+        {
+            /* invalid flash address */
+            eRetVal = STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM;
+        }
+        else
+        {
+            /* DATA flash sector */
+            if (0U != Ftfc_Fls_Ip_u32DFlashBitSizeProt)
+            {
+                /* A prot register has 8 bits, determine the bit which the current address resides in */
+                u8SecRegProtBitPos = (uint8)( (u32SectStartAddr - FTFC_D_FLASH_BASE_ADDR) / Ftfc_Fls_Ip_u32DFlashBitSizeProt );
+                if (0U == (FTFx_BaseAddress->FDPROT & (1UL << u8SecRegProtBitPos)))
+                {
+                    /* Data Flash region is protected */
+                    eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+                }
+            }
+            else
+            {
+                /* No Dflash configured, although this sector is supposed to be a DFlash one. */
+                eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+            }
+        }
+    }
+    else
+    {
+        /* PROGRAM flash sector */
+
+        /* Determine the Pflash size which is protected by a register. */
+#if (0x180000UL == FTFC_P_FLASH_SIZE ) /* 2048K device */
+        /* For 2048K device, the PFlash size, which is 1.5K has to be rounded to 2K. */
+        u32PFlashRegSize = 0x200000UL >> 2UL;
+#else
+        u32PFlashRegSize = FTFC_P_FLASH_SIZE >> 2UL;
+#endif
+
+        /* Compute the protection region size depending on the P-FLASH size. */
+#if (0x20000UL == FTFC_P_FLASH_SIZE)
+        u32PFlashBitSize = 4096UL;      /* Each bit protects 4KB regions */
+#endif
+#if (0x40000UL == FTFC_P_FLASH_SIZE)
+        u32PFlashBitSize = 8192UL;      /* Each bit protects 8KB regions */
+#endif
+#if (0x80000UL == FTFC_P_FLASH_SIZE)
+        u32PFlashBitSize = 16384UL;     /* Each bit protects 16KB regions */
+#endif
+#if (0x100000UL == FTFC_P_FLASH_SIZE)
+        u32PFlashBitSize = 32768UL;     /* Each bit protects 32KB regions */
+#endif
+#if (0x180000UL == FTFC_P_FLASH_SIZE)
+        u32PFlashBitSize = 65536UL;     /* Each bit protects 64KB regions */
+#endif
+
+        /* There are four prot registers for PROGRAM flash sectors, the right one has to be determined. Find in which reg prot register this sector belongs. */
+        u8RegProtNo = (uint8)(u32SectStartAddr / u32PFlashRegSize);  /* Determine in which of the four protection regions the current address resides. */
+
+        /* A prot register has 8 bits, determine the bit which the current address resides in */
+        u8SecRegProtBitPos = (uint8)((u32SectStartAddr % u32PFlashRegSize) / u32PFlashBitSize);
+
+        if (u8RegProtNo < FTFx_FPROT_COUNT)
+        {
+            /* Check if the sector is protected */
+            if (0U == (FTFx_BaseAddress->FPROT[u8RegProtNo] & (1UL << u8SecRegProtBitPos)))
+            {
+                /* Program Flash region is protected */
+                eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+    return eRetVal;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_Init
+ * Description      This function will initialize Ftfc module and clear all error flags.
+ * @implements      Ftfc_Fls_Ip_Init_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Init(const Ftfc_ConfigType * Ftfc_Fls_Ip_pInitConfig)
+{
+    DEV_ASSERT_FTFC(Ftfc_Fls_Ip_pInitConfig != NULL_PTR);
+    Ftfc_Fls_Ip_pConfigPtr = Ftfc_Fls_Ip_pInitConfig;
+
+    /* Precalculate the DFlash region protect size each bit to increase performance in runtime */
+    Ftfc_Fls_Ip_CalculateDFlashBitSize();
+
+    return STATUS_FTFC_FLS_IP_SUCCESS;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_Abort
+ * Description      Abort a program or erase operation
+ * @implements      Ftfc_Fls_Ip_Abort_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Abort(void)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal;
+
+    /* Wait for current pending operation to finish, as there is no hardware way to abort it */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_WaitForOperationFinish())
+    {
+        /* memory idle, no operation is pending */
+        eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+    else
+    {
+        eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+    }
+    return eRetVal;
+}
+
+
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WaitForOperationFinish(void)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal;
+
+    #if ( FTFC_TIMEOUT_SUPERVISION_ENABLED == STD_ON )
+    uint32 u32ElapsedAbortTicks = 0UL;
+    uint32 u32TimeoutAbortTicks = OsIf_MicrosToTicks(FTFC_ABORT_TIMEOUT, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+    uint32 u32CurrentAbortTicks = OsIf_GetCounter((OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+
+    /* wait until done */
+    while ((0U == ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK)) && (u32ElapsedAbortTicks < u32TimeoutAbortTicks))
+    {
+        u32ElapsedAbortTicks += OsIf_GetElapsed(&u32CurrentAbortTicks, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+    }
+    #else
+    /* wait until done */
+    while (0U == ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK))
+    {
+
+    }
+    #endif /* FTFC_TIMEOUT_SUPERVISION_ENABLED == STD_ON */
+
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_HARDWARE_BUSY_IN_ABORT);
+    /* return true if DONE */
+    if (0U != ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK))
+    {
+        /* OK, memory idle */
+        eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+    else
+    {
+        /* error, memory controller not idle */
+        eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+    }
+
+    return eRetVal;
+}
+
+
+#if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+static void Ftfc_Fls_SynchronizeCache(uint32 address,
+                                      uint32 length
+                                     )
+{
+    /* Expand the memory area to align with multiple of a cache line size (16 bytes) */
+    const uint32 mask = ~0x0FU;
+    uint32 cacheStartAddr = address & mask;
+    uint32 cacheEndAddr   = ((address + length + 0x0FU) & mask);
+    uint32 cacheLength    = cacheEndAddr - cacheStartAddr;
+    uint32 prefetchBufferSize;
+    uint32 i;
+
+    #if (STD_ON == FTFC_FLS_D_FLASH_CACHEABLE)
+        /* Both code and data flash are cacheable */
+        if ( (boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_P_FLASH(address) )
+        {
+            prefetchBufferSize = 16U;  /* 128-bit prefetch speculation buffer for Program Flash */
+        }
+        else
+        {
+            prefetchBufferSize = 8U;  /* 64-bit prefetch speculation buffer for Data Flash */
+        }
+
+        /* Invalidate each size of the prefetch buffer at a time */
+        for (i = 0; i < cacheLength; i += prefetchBufferSize)
+        {
+            (void)Cache_Ip_InvalidateByAddr(CACHE_IP_ALL, cacheStartAddr, prefetchBufferSize);
+            cacheStartAddr += prefetchBufferSize;
+        }
+
+    #else
+        /* The data flash is non-cacheable, skip it, only invalidate cache for program flash */
+        if ( (boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_P_FLASH(address) )
+        {
+            prefetchBufferSize = 16U;  /* 128-bit prefetch speculation buffer for Program Flash */
+
+            /* Invalidate each size of the prefetch buffer at a time */
+            for (i = 0; i < cacheLength; i += prefetchBufferSize)
+            {
+                (void)Cache_Ip_InvalidateByAddr(CACHE_IP_ALL, cacheStartAddr, prefetchBufferSize);
+                cacheStartAddr += prefetchBufferSize;
+            }
+        }
+    #endif
+}
+#endif
+
+
+/**
+ * @brief Compute the data size, considering the addresses alignment and the remaining bytes.
+ *
+ * @param[in]  srcAddress the internal flash address
+ * @param[in]  desAddress the user's buffer address
+ * @param[in]  byteRemain how many bytes are left to process
+ *
+ * @return the data size that flash memory will accept given the address/buffer alignments
+ * @retval FLS_SIZE_1BYTE     unaligned operations
+ * @retval FLS_SIZE_2BYTE     16-bit aligned operations
+ * @retval FLS_SIZE_4BYTE     32-bit aligned operations
+ */
+static uint32 Ftfc_Fls_ComputeReadSize(uint32 srcAddress,
+                                       uint32 desAddress,
+                                       uint32 byteRemain
+                                      )
+{
+    uint32 readSize = FLS_SIZE_1BYTE;
+    /* Combine two addresses for faster alignment checking */
+    uint32 combinedAddress = srcAddress | desAddress;
+
+    /* Both the lowest two bits are zero: 4 bytes aligned */
+    if (0UL == (combinedAddress & 0x03UL))
+    {
+        if (byteRemain >= FLS_SIZE_4BYTE)
+        {
+            /* 4 bytes operation */
+            readSize = FLS_SIZE_4BYTE;
+        }
+        else if (byteRemain >= FLS_SIZE_2BYTE)
+        {
+            /* 2 bytes operation */
+            readSize = FLS_SIZE_2BYTE;
+        }
+        else
+        {
+            /* 1 byte operation */
+        }
+    }
+    /* Both the lowest one bit are zero: 2 bytes aligned */
+    else if (0UL == (combinedAddress & 0x01UL))
+    {
+        if (byteRemain >= FLS_SIZE_2BYTE)
+        {
+            /* 2 bytes operation */
+            readSize = FLS_SIZE_2BYTE;
+        }
+        else
+        {
+            /* 1 byte operation */
+        }
+    }
+    else
+    {
+        /* 1 byte operation */
+    }
+
+    return readSize;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ReadData32
+ * Description      Reads 4 bytes from the specified address
+ */
+static inline uint32 Ftfc_Fls_Ip_ReadData32(uint32 address)
+{
+    return (*((uint32 *)address));
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ReadData16
+ * Description      Reads 2 bytes from the specified address
+ */
+static inline uint16 Ftfc_Fls_Ip_ReadData16(uint32 address)
+{
+    return (*((uint16 *)address));
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ReadData8
+ * Description      Reads 1 byte from the specified address
+ */
+static inline uint8 Ftfc_Fls_Ip_ReadData8(uint32 address)
+{
+    return (*((uint8 *)address));
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ReadData
+ * Description      Accesses the flash to read data to user buffer
+ */
+static void Ftfc_Fls_Ip_ReadData(uint32 readSize,
+                                 uint32 readAddress,
+                                 uint32 desAddress,
+                                 uint8 *desAddressPtr
+                                )
+{
+    switch (readSize)
+    {
+        case FLS_SIZE_4BYTE:
+            *((uint32 *)desAddress) = Ftfc_Fls_Ip_ReadData32(readAddress);
+            break;
+
+        case FLS_SIZE_2BYTE:
+            *((uint16 *)desAddress) = Ftfc_Fls_Ip_ReadData16(readAddress);
+            break;
+
+        case FLS_SIZE_1BYTE:
+            *desAddressPtr = Ftfc_Fls_Ip_ReadData8(readAddress);  /* Using uint8 directly to avoid pointer casting */
+            break;
+
+        default:
+            /* Do nothing */
+            break;
+    }
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_CheckValidRange
+ * Description      Checks both start and end address are within the Program or Data flash address space, using before Read/Compare/Write operations
+ */
+static boolean Ftfc_Fls_Ip_CheckValidRange(uint32 startAddress, uint32 length)
+{
+    boolean bRetVal = (boolean)FALSE;
+    uint32 endAddress = startAddress + length - 1UL;
+
+    /* The start and end address must be within the program flash or data flash address space */
+     if ( (((boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_P_FLASH(startAddress)) &&
+           ((boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_P_FLASH(endAddress)))
+        ||
+          (((boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_D_FLASH(startAddress)) &&
+           ((boolean)TRUE == (boolean)FTFC_ADDRESS_VALID_D_FLASH(endAddress)))
+        )
+    {
+        /* The memory range is valid */
+        bRetVal = (boolean)TRUE;
+    }
+
+    return bRetVal;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ReadPreCheck
+ * Description      Prepare before starting a new read operation
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ReadPreCheck(uint32 u32SrcAddress, const uint8 *pDestAddressPtr, uint32 u32Length)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM;
+
+    /* Check 1: The user buffer pointer cannot be a null pointer */
+    if (NULL_PTR == pDestAddressPtr)
+    {
+        /* Wrong input parameters */
+    }
+    /* Check 2: The read length must be greater than zero */
+    else if (0UL == u32Length)
+    {
+        /* Wrong input parameters */
+    }
+    /* Check 3: The start and end address must be within the program flash or data flash address space */
+    else if ( (boolean)FALSE == Ftfc_Fls_Ip_CheckValidRange(u32SrcAddress, u32Length) )
+    {
+        /* Wrong input parameters */
+    }
+    else
+    {
+        /* Reaching here means that everything is ok */
+        eReturnCode = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+
+    return eReturnCode;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_Read
+ * Description      This function fills data to pDestAddressPtr with data from the specified address
+ * @implements      Ftfc_Fls_Ip_Read_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Read(Ftfc_Fls_Ip_AddressType u32SrcAddress,
+                                        uint8 *pDestAddressPtr,
+                                        Ftfc_Fls_Ip_LengthType u32Length
+                                       )
+{
+    uint32 readAddress = (uint32)u32SrcAddress;
+    uint32 desAddress  = (uint32)pDestAddressPtr;
+    uint8 *desAddressPtr = pDestAddressPtr;
+    uint32 bytesRemain = u32Length;
+    uint32 readSize;
+    Ftfc_Fls_Ip_StatusType readStatus;
+
+    DEV_ASSERT_FTFC(u32Length > 0UL);
+    DEV_ASSERT_FTFC(pDestAddressPtr != NULL_PTR);
+    DEV_ASSERT_FTFC( Ftfc_Fls_Ip_CheckValidRange(u32SrcAddress, u32Length) );
+
+    /* Checking before reading */
+    Ftfc_Fls_Ip_eReadStatus = Ftfc_Fls_Ip_ReadPreCheck(u32SrcAddress, pDestAddressPtr, u32Length);
+
+    /* Everything is ready for a new read operation */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_eReadStatus)
+    {
+        /* Change to busy state */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_BUSY;
+
+        /* Invalidate cache */
+        #if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+        Ftfc_Fls_SynchronizeCache(readAddress, bytesRemain);
+        #endif
+
+        /* Start read operation */
+        do
+        {
+            /* Invalidate prefetch buffer before reading to make sure that the driver always reads the new data from flash */
+            Ftfc_Fls_Ip_InvalidPrefetchBuff();
+
+            #if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+            #if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+            /* Save the current memory access address for ECC handling */
+            Ftfc_Fls_Ip_u32ReadAddressPtr = readAddress;
+            #endif
+            /* Clear ECC flag */
+            FTFx_BaseAddress->FERSTAT = FTFx_FERSTAT_DFDIF_MASK;
+            #endif
+
+            /* Compute the maximum read size */
+            readSize = Ftfc_Fls_ComputeReadSize(readAddress, desAddress, bytesRemain);
+
+            /* Start flash access */
+            Ftfc_Fls_Ip_FlashAccessCalloutStart();
+
+            /* Access the flash to read data to user buffer */
+            Ftfc_Fls_Ip_ReadData(readSize, readAddress, desAddress, desAddressPtr);
+
+            /* Finish flash access */
+            Ftfc_Fls_Ip_FlashAccessCalloutFinish();
+
+            /* Check for hardware errors or ECC happend */
+            readStatus = Ftfc_Fls_Ip_ReadStatus((boolean)TRUE);
+            if (STATUS_FTFC_FLS_IP_SUCCESS != readStatus)
+            {
+                break;
+            }
+
+            /* Move to the next data */
+            readAddress  += readSize;
+            desAddress   += readSize;
+            desAddressPtr = &desAddressPtr[readSize];
+            bytesRemain  -= readSize;
+        }
+        while (0UL < bytesRemain);
+
+        /* Checking if working was successful: the requested bytes were copied and no errors happend */
+        if (0UL == bytesRemain)
+        {
+            /* Mark as success */
+            Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_SUCCESS;
+        }
+    }
+
+    return Ftfc_Fls_Ip_eReadStatus;
+}
+
+
+/**
+ * @brief Check status after memory accessing of Read/Compare operations
+ *
+ * @return the status of the most recent memory access
+ * @retval STATUS_FTFC_FLS_IP_ERROR     Hardware errors or ECC happend or there was a compare error
+ * @retval STATUS_FTFC_FLS_IP_SUCCESS   Everything was ok
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ReadStatus(boolean compareStatus)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+    uint8 errorFlags;
+
+    /* Check everything in order of priority: hardware > ECC > compare */
+
+    /* Step 1: Check for hardware errors */
+    errorFlags = FTFx_BaseAddress->FSTAT & (FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK);
+    if (0U != errorFlags)
+    {
+        /* Clear all error flags: write 1 to clear */
+        FTFx_BaseAddress->FSTAT = errorFlags;
+        /* Hardware errors: change read status to error state */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR;
+    }
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+    /* Step 2: Check for ECC */
+    else if (STATUS_FTFC_FLS_IP_ERROR == Ftfc_Fls_Ip_eReadStatus)
+    {
+        /* ECC happened in the DsiHandler: keep the current status */
+    }
+#endif
+
+    /* Step 3: Check for compare error */
+    else if ((boolean)TRUE != compareStatus)
+    {
+        /* Compare error: update read status */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY;
+    }
+    else
+    {
+        /* Everything was ok */
+        eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+
+    return eRetVal;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ComparePreCheck
+ * Description      Prepare before starting a new cpmpare operation
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ComparePreCheck(uint32 u32SrcAddress, uint32 u32Length)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM;
+
+    /* Check 1: The read length must be greater than zero */
+    if (0UL == u32Length)
+    {
+        /* Wrong input parameters */
+    }
+    /* Check 2: The start and end address must be within the program flash or data flash address space */
+    else if ( (boolean)FALSE == Ftfc_Fls_Ip_CheckValidRange(u32SrcAddress, u32Length) )
+    {
+        /* Wrong input parameters */
+    }
+    else
+    {
+        /* Reaching here means that everything is ok */
+        eReturnCode = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+
+    return eReturnCode;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_Compare
+ * Description      Checks that there is the desired data at the specified address
+ * @implements      Ftfc_Fls_Ip_Compare_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Compare(Ftfc_Fls_Ip_AddressType u32SrcAddress,
+                                           const uint8 * pCompareAddressPtr,
+                                           Ftfc_Fls_Ip_LengthType u32Length
+                                          )
+{
+    uint32 srcAddress = (uint32)u32SrcAddress;
+
+    DEV_ASSERT_FTFC(u32Length > 0UL);
+    DEV_ASSERT_FTFC( Ftfc_Fls_Ip_CheckValidRange(u32SrcAddress, u32Length) );
+
+    /* Checking before comparing */
+    Ftfc_Fls_Ip_eReadStatus = Ftfc_Fls_Ip_ComparePreCheck(u32SrcAddress, u32Length);
+
+    /* Everything is ready for a new compare operation */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_eReadStatus)
+    {
+        /* Change to busy state */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_BUSY;
+
+        /* Invalidate cache before reading memory */
+        #if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+        Ftfc_Fls_SynchronizeCache(srcAddress, u32Length);
+        #endif
+
+        /* Choose the type of comparison */
+        if (NULL_PTR != pCompareAddressPtr)
+        {
+            /* Verify the written data */
+            Ftfc_Fls_Ip_ProgramVerify(srcAddress, pCompareAddressPtr, u32Length);
+        }
+        else
+        {
+            /* Blank check */
+            Ftfc_Fls_Ip_EraseVerify(srcAddress, u32Length);
+        }
+
+    }
+
+    return Ftfc_Fls_Ip_eReadStatus;
+}
+
+
+/**
+ * @brief Verifies data written in serial flash
+ */
+static void Ftfc_Fls_Ip_ProgramVerify(uint32 address, const uint8 * data, uint32 size)
+{
+    uint32 verifyAddress = address;
+    uint32 verifyData    = (uint32)data;
+    uint32 verifySize    = size;
+    uint32 readSize;
+    Ftfc_Fls_Ip_StatusType status;
+    boolean compareStatus = (boolean)TRUE;
+
+    /* Start compare operation */
+    do
+    {
+        /* Invalidate prefetch buffer before reading to make sure that the driver always reads the new data from flash */
+        Ftfc_Fls_Ip_InvalidPrefetchBuff();
+
+        #if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+        #if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+        /* Save the current memory access address for ECC handling */
+        Ftfc_Fls_Ip_u32ReadAddressPtr = verifyAddress;
+        #endif
+        /* Clear ECC flag */
+        FTFx_BaseAddress->FERSTAT = FTFx_FERSTAT_DFDIF_MASK;
+        #endif
+
+        /* Compute the maximum read size */
+        readSize = Ftfc_Fls_ComputeReadSize(verifyAddress, verifyData, verifySize);
+
+        /* Start flash access */
+        Ftfc_Fls_Ip_FlashAccessCalloutStart();
+
+        switch (readSize)
+        {
+            case FLS_SIZE_4BYTE:
+                if (Ftfc_Fls_Ip_ReadData32(verifyData) != Ftfc_Fls_Ip_ReadData32(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            case FLS_SIZE_2BYTE:
+                if (Ftfc_Fls_Ip_ReadData16(verifyData) != Ftfc_Fls_Ip_ReadData16(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            case FLS_SIZE_1BYTE:
+                if (Ftfc_Fls_Ip_ReadData8(verifyData) != Ftfc_Fls_Ip_ReadData8(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            default:
+                /* Do nothing */
+                break;
+        }
+
+        /* Finish flash access */
+        Ftfc_Fls_Ip_FlashAccessCalloutFinish();
+
+        /* Check for hardware errors or ECC happend or compare error */
+        status = Ftfc_Fls_Ip_ReadStatus(compareStatus);
+        if (STATUS_FTFC_FLS_IP_SUCCESS != status)
+        {
+            break;
+        }
+
+        /* Move to next data */
+        verifyAddress += readSize;
+        verifyData    += readSize;
+        verifySize    -= readSize;
+    }
+    while (0UL < verifySize);
+
+    /* Checking if working is successful: the requested bytes were copied and no errors happend */
+    if (0UL == verifySize)
+    {
+        /* Mark as success */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+}
+
+
+/**
+ * @brief Verifies that an area in memory flash is in erased state
+ */
+static void Ftfc_Fls_Ip_EraseVerify(uint32 address, uint32 size)
+{
+    uint32 verifyAddress = address;
+    uint32 verifySize = size;
+    uint32 readSize;
+    Ftfc_Fls_Ip_StatusType status;
+    boolean compareStatus = (boolean)TRUE;
+
+    /* Start compare operation */
+    do
+    {
+        /* Invalidate prefetch buffer before reading to make sure that the driver always reads the new data from flash */
+        Ftfc_Fls_Ip_InvalidPrefetchBuff();
+
+        #if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+        #if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+        /* Save the current memory access address for ECC handling */
+        Ftfc_Fls_Ip_u32ReadAddressPtr = verifyAddress;
+        #endif
+        /* Clear ECC flag */
+        FTFx_BaseAddress->FERSTAT = FTFx_FERSTAT_DFDIF_MASK;
+        #endif
+
+        /* Compute the maximum read size */
+        readSize = Ftfc_Fls_ComputeReadSize(verifyAddress, 0UL, verifySize);
+
+        /* Start flash access */
+        Ftfc_Fls_Ip_FlashAccessCalloutStart();
+
+        switch (readSize)
+        {
+            case FLS_SIZE_4BYTE:
+                if ((uint32)FTFC_ERASED_VALUE != Ftfc_Fls_Ip_ReadData32(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            case FLS_SIZE_2BYTE:
+                if ((uint16)FTFC_ERASED_VALUE != Ftfc_Fls_Ip_ReadData16(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            case FLS_SIZE_1BYTE:
+                if ((uint8)FTFC_ERASED_VALUE != Ftfc_Fls_Ip_ReadData8(verifyAddress))
+                {
+                    compareStatus = (boolean)FALSE;
+                }
+                break;
+
+            default:
+                /* Do nothing */
+                break;
+        }
+
+        /* Finish flash access */
+        Ftfc_Fls_Ip_FlashAccessCalloutFinish();
+
+        /* Check for hardware errors or ECC happend or compare error */
+        status = Ftfc_Fls_Ip_ReadStatus(compareStatus);
+        if (STATUS_FTFC_FLS_IP_SUCCESS != status)
+        {
+            break;
+        }
+
+        /* Move to next data */
+        verifyAddress += readSize;
+        verifySize    -= readSize;
+    }
+    while (0UL < verifySize);
+
+    /* Checking if working is successful: the requested bytes were copied and no errors happend */
+    if (0UL == verifySize)
+    {
+        /* Mark as success */
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_SectorErasePreCheck
+ * Description      Prepare before starting a new erase operation: input params, memory protection and hardware status
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorErasePreCheck(uint32 u32SectorStartAddress)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_SUCCESS;
+
+    /* Step 1: Check address is in the valid range and align with the size of a program or data sector */
+    if ( ((boolean)FALSE == ((boolean)FTFC_ADDRESS_VALID(u32SectorStartAddress)))  ||
+         ((boolean)FALSE == ((boolean)FTFC_SECTOR_ALIGNED(u32SectorStartAddress)))
+       )
+    {
+        /* Wrong input parameters*/
+        eReturnCode = STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM;
+    }
+
+    /* Step 2: Check if the memory area is protected or not */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        eReturnCode = Ftfc_Fls_Ip_CheckFProtReg(u32SectorStartAddress);
+    }
+
+    /* Step 3: Check if hardware is busy or not */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        eReturnCode = Ftfc_Fls_Ip_ControllerBusy();
+    }
+
+    return eReturnCode;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_SectorErase
+ * Description      Accepts and erases a selected program flash or data flash sector if possible
+ * @implements      Ftfc_Fls_Ip_SectorErase_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorErase(uint32 u32SectorStartAddress)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal;
+    boolean bAddressValid  = FTFC_ADDRESS_VALID(u32SectorStartAddress);
+    boolean bSectorAligned = FTFC_SECTOR_ALIGNED(u32SectorStartAddress);
+
+    DEV_ASSERT_FTFC(bAddressValid);
+    DEV_ASSERT_FTFC(bSectorAligned);
+    /* Unused variables */
+    (void)bAddressValid;
+    (void)bSectorAligned;
+
+    /* Check(if erase suspended is possible) if any ongoing erase suspended and abort it */
+    eRetVal = Ftfc_Fls_Flash_AbortSuspended();
+
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eRetVal)
+    {
+        /* Pre-check before starting erase operation */
+        eRetVal = Ftfc_Fls_Ip_SectorErasePreCheck(u32SectorStartAddress);
+    }
+
+    /* Verify that there is no other job in progress */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eRetVal)
+    {
+#if ((FTFC_ERASE_VERIFICATION_ENABLED == STD_ON) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+        /* Prepare address for the blank check */
+        Ftfc_Fls_Ip_u32ErasedSectorAddress = u32SectorStartAddress;
+#endif
+        /* Setup erase operation */
+        Ftfc_Fls_Ip_LoadFCCOBParams(u32SectorStartAddress, NULL_PTR, FLASH_CMD_ERASE_SECTOR);
+
+        /* Clear all error flags, otherwise CCIF cannot be cleared to launch command */
+        Ftfc_Fls_Ip_ClearErrorFlags();
+
+        /* if Async is true */
+        if (TRUE == Ftfc_Fls_Ip_Async)
+        {
+            /* Start flash access */
+            Ftfc_Fls_Ip_FlashAccessCalloutStart();
+            /* start internal erase/program sequence */
+            FTFx_BaseAddress->FSTAT = FTFx_FSTAT_CCIF_MASK;
+        /* if Sync mode */
+        }
+        else
+        {
+            ; /* do no-thing*/
+        }
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+        /* Prepare timeout counter */
+        Ftfc_Fls_Ip_u32ElapsedTicks = 0UL;
+        Ftfc_Fls_Ip_u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        if ((boolean)FALSE == Ftfc_Fls_Ip_Async)
+        {
+            Ftfc_Fls_Ip_u32TimeoutTicks = OsIf_MicrosToTicks(FTFC_SYNC_ERASE_TIMEOUT, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        }
+        else
+        {
+            Ftfc_Fls_Ip_u32TimeoutTicks = OsIf_MicrosToTicks(FTFC_ASYNC_ERASE_TIMEOUT, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        }
+#endif
+    }
+
+    /* Save the erase job's status */
+    Ftfc_Fls_Ip_eEraseStatus = eRetVal;
+    return eRetVal;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_SectorEraseStatus
+ * Description      Checks the status of the hardware erase started by the Ftfc_Fls_Ip_SectorErase function.
+ * @implements      Ftfc_Fls_Ip_SectorEraseStatus_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_SectorEraseStatus(void)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode;
+#if ((FTFC_ERASE_VERIFICATION_ENABLED == STD_ON) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+    uint32 u32Length = 0;
+#endif
+
+    /* Check if the erase job started successfully */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_eEraseStatus)
+    {
+        /* The job started successfully, polling the controller status */
+        eReturnCode = Ftfc_Fls_Ip_CtrlStatus();
+
+#if ((FTFC_ERASE_VERIFICATION_ENABLED == STD_ON) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+        /* The job has done, perform the verification */
+        if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+        {
+            /* Check the sector size */
+            if (Ftfc_Fls_Ip_u32ErasedSectorAddress >= FTFC_D_FLASH_BASE_ADDR)
+            {
+                u32Length = FTFC_D_FLASH_SECTOR_SIZE;
+            }
+            else
+            {
+                u32Length = FTFC_P_FLASH_SECTOR_SIZE;
+            }
+
+            #if ( FTFC_ERASE_VERIFICATION_ENABLED == STD_ON )
+            /* Verify blank check after erasing the data */
+            eReturnCode = Ftfc_Fls_Ip_Compare(Ftfc_Fls_Ip_u32ErasedSectorAddress, NULL_PTR, u32Length);
+            if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+            {
+                eReturnCode = STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK;
+            }
+            #else
+            /* Invalidate cache: this will be done inside the function Ftfc_Fls_Ip_Compare if erase verifivation is enabled */
+            Ftfc_Fls_SynchronizeCache(Ftfc_Fls_Ip_u32ErasedSectorAddress, u32Length);
+            #endif
+        }
+#endif
+    }
+    else
+    {
+        /* The erase job did not start successfully, return error immediately */
+        eReturnCode = STATUS_FTFC_FLS_IP_ERROR;
+    }
+
+    return eReturnCode;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_WritePreCheck
+ * Description      Prepare before starting a new write operation: input params, memory protection and hardware status
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WritePreCheck(uint32 u32DestAddress, const uint8 *pSourceAddressPtr, uint32 u32Length)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode = STATUS_FTFC_FLS_IP_SUCCESS;
+
+    /* Step 1: Check length and address should align with FTFC_WRITE_DOUBLE_WORD, the start and end address must be a valid range */
+    if ( ((u32DestAddress % (uint8)FTFC_WRITE_DOUBLE_WORD) != 0U )                 ||
+          (u32Length != FTFC_WRITE_DOUBLE_WORD)                                    ||
+          (NULL_PTR == pSourceAddressPtr)                                          ||
+         ((boolean)FALSE == Ftfc_Fls_Ip_CheckValidRange(u32DestAddress, u32Length))
+       )
+    {
+        /* Wrong input parameters*/
+        eReturnCode = STATUS_FTFC_FLS_IP_ERROR_INPUT_PARAM;
+    }
+
+    /* Step 2: Check if the memory area is protected or not */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        eReturnCode = Ftfc_Fls_Ip_CheckFProtReg(u32DestAddress);
+    }
+
+    /* Step 3: Check if hardware is busy or not */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        eReturnCode = Ftfc_Fls_Ip_ControllerBusy();
+    }
+
+    return eReturnCode;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_Write
+ * Description      Writes data into the memory array using the main interface. Initiates the hardware write and then exits.
+ * @implements      Ftfc_Fls_Ip_Write_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_Write(uint32 u32DestAddress,
+                                         const uint8 *pSourceAddressPtr,
+                                         uint32 u32Length
+                                        )
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode;
+
+    DEV_ASSERT_FTFC( Ftfc_Fls_Ip_CheckValidRange(u32DestAddress, u32Length) );
+    DEV_ASSERT_FTFC(0U == (u32DestAddress % (uint8)FTFC_WRITE_DOUBLE_WORD));
+    DEV_ASSERT_FTFC(FTFC_WRITE_DOUBLE_WORD == u32Length);
+    DEV_ASSERT_FTFC(pSourceAddressPtr != NULL_PTR);
+
+    /* Check(if erase suspended is possible) if any ongoing erase suspended and abort it */
+    eReturnCode = Ftfc_Fls_Flash_AbortSuspended();
+    
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        /* Pre-check before starting write operation */
+        eReturnCode = Ftfc_Fls_Ip_WritePreCheck(u32DestAddress, pSourceAddressPtr, u32Length);
+    }
+
+    /* Verify blank check before writing the data */
+#if ( FTFC_ERASE_VERIFICATION_ENABLED == STD_ON )
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+        eReturnCode = Ftfc_Fls_Ip_Compare(u32DestAddress, NULL_PTR, u32Length);
+        if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+        {
+            eReturnCode = STATUS_FTFC_FLS_IP_ERROR_BLANK_CHECK;
+        }
+    }
+#endif
+
+    /* Everything is ready for a new write operation */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+    {
+#if ((STD_ON == FTFC_PROGRAM_VERIFICATION_ENABLED) || (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE))
+        Ftfc_Fls_Ip_u32ProgrammedAddress = u32DestAddress;
+        Ftfc_Fls_Ip_u32ProgrammedLength = u32Length;
+#endif
+
+#if (STD_ON == FTFC_PROGRAM_VERIFICATION_ENABLED)
+        Ftfc_Fls_Ip_pProgrammedData = pSourceAddressPtr;
+#endif
+        /* setup write operation */
+        Ftfc_Fls_Ip_LoadFCCOBParams(u32DestAddress, pSourceAddressPtr, FLASH_CMD_PROGRAM_PHRASE);
+
+        MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_WRITE_PREPARED_DATA_TO_SENT);
+
+        /* Clear all error flags, otherwise CCIF cannot be cleared to launch command */
+        Ftfc_Fls_Ip_ClearErrorFlags();
+
+        /* if Async is true */
+        if (TRUE == Ftfc_Fls_Ip_Async)
+        {
+            /* Start flash access */
+            Ftfc_Fls_Ip_FlashAccessCalloutStart();
+            /* start internal erase/program sequence */
+            FTFx_BaseAddress->FSTAT = FTFx_FSTAT_CCIF_MASK;
+        }
+        
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+        /* Prepare timeout counter */
+        Ftfc_Fls_Ip_u32ElapsedTicks = 0UL;
+        Ftfc_Fls_Ip_u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        if ((boolean)FALSE == Ftfc_Fls_Ip_Async)
+        {
+            Ftfc_Fls_Ip_u32TimeoutTicks = OsIf_MicrosToTicks(FTFC_SYNC_WRITE_TIMEOUT, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        }
+        else
+        {
+            Ftfc_Fls_Ip_u32TimeoutTicks = OsIf_MicrosToTicks(FTFC_ASYNC_WRITE_TIMEOUT, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        }
+#endif
+    }
+
+    /* Save the write's job result */
+    Ftfc_Fls_Ip_eWriteStatus = eReturnCode;
+    return eReturnCode;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_WriteStatus
+ * Description      Checks the status of the hardware program started by the FTFC_FLS_IP_MainInterfaceWrite function.
+ * @implements      Ftfc_Fls_Ip_WriteStatus_Activity
+ */
+Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_WriteStatus(void)
+{
+    Ftfc_Fls_Ip_StatusType eReturnCode;
+
+    /* Check if the write job started successfully */
+    if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_eWriteStatus)
+    {
+        /* The job started successfully, polling the controller status */
+        eReturnCode = Ftfc_Fls_Ip_CtrlStatus();
+
+        /* The job has done, perform the verification */
+        if (STATUS_FTFC_FLS_IP_SUCCESS == eReturnCode)
+        {
+#if ( FTFC_PROGRAM_VERIFICATION_ENABLED == STD_ON )
+            /* Fault Injection point: write data to programmed sector to make the Compare failed */
+            MCAL_FAULT_INJECTION_POINT(FLS_FIP_FTFC_FAILED_VERIFICATION_WRITE);
+
+            /* Verify written data */
+            eReturnCode = Ftfc_Fls_Ip_Compare(Ftfc_Fls_Ip_u32ProgrammedAddress, Ftfc_Fls_Ip_pProgrammedData, Ftfc_Fls_Ip_u32ProgrammedLength);
+            if (STATUS_FTFC_FLS_IP_SUCCESS != eReturnCode)
+            {
+                eReturnCode = STATUS_FTFC_FLS_IP_ERROR_PROGRAM_VERIFY;
+            }
+#else
+        #if ( STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE )
+        /* Invalidate cache: this will be done inside the function Ftfc_Fls_Ip_Compare if program verifivation is enabled */
+        Ftfc_Fls_SynchronizeCache(Ftfc_Fls_Ip_u32ProgrammedAddress, Ftfc_Fls_Ip_u32ProgrammedLength);
+        #endif
+#endif
+        }
+
+    }
+    else
+    {
+        /* The write job did not start successfully, return error immediately */
+        eReturnCode = STATUS_FTFC_FLS_IP_ERROR;
+    }
+
+    return eReturnCode;
+}
+
+/**
+ * Function Name    Ftfc_Fls_Flash_AbortSuspended
+ * Description      Managing Abort Erase suspend. If there is a pending erase suspended, abort it.
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Flash_AbortSuspended(void)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+    uint8 tempValueFCNFG_Flags;
+
+    /* Ff there is a suspended operation in progress */
+    if (0U != ((FTFx_BaseAddress->FCNFG) & FTFx_FCNFG_ERSSUSP_MASK))
+    {
+        /* if the memory controller is ready to receive new commands */
+        if (0U != ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK))
+        {
+            /* abort the suspended erase */
+            tempValueFCNFG_Flags = FTFx_BaseAddress->FCNFG;
+            FTFx_BaseAddress->FCNFG = tempValueFCNFG_Flags & ((uint8)(~FTFx_FCNFG_ERSSUSP_MASK));
+        }
+        else    /* memory controller busy */
+        {
+            /* wait for memory controller to finish current operation */
+            if (STATUS_FTFC_FLS_IP_SUCCESS == Ftfc_Fls_Ip_WaitForOperationFinish())
+            {
+                /* abort the suspended erase */
+                tempValueFCNFG_Flags = FTFx_BaseAddress->FCNFG;
+                FTFx_BaseAddress->FCNFG = tempValueFCNFG_Flags & ((uint8)(~FTFx_FCNFG_ERSSUSP_MASK));
+            }
+            else /* operation not finished, aborted on timeout */
+            {
+                eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+            }
+        }
+    }
+    else
+    {
+        ;/* No suspended erase operation */
+    }
+
+    return eRetVal;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_CtrlStatus
+ * Description      Get the status of job with main interface.
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_CtrlStatus(void)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal;
+    uint8 errorFlags;
+
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FTFC_ERROR_READ_FSTAT_FLAG);
+
+    /* Check if the flash controller is idle, by polling the CCIF status bit. */
+    if (0U != (FTFx_BaseAddress->FSTAT & FTFx_FSTAT_CCIF_MASK))
+    {
+        /* OK, memory controller is idle */
+
+        /* Check if any hardware errors happened */
+        errorFlags = FTFx_BaseAddress->FSTAT & (FTFx_ERR_FLAGS_MASK);
+        if (0U == errorFlags)
+        {
+            eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+        }
+        else
+        {
+            /* clear the error flags */
+            FTFx_BaseAddress->FSTAT = errorFlags;
+            eRetVal = STATUS_FTFC_FLS_IP_ERROR;
+        }
+    }
+    else
+    {
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+        Ftfc_Fls_Ip_u32ElapsedTicks += OsIf_GetElapsed(&Ftfc_Fls_Ip_u32CurrentTicks, (OsIf_CounterType)FTFC_TIMEOUT_TYPE);
+        if (Ftfc_Fls_Ip_u32ElapsedTicks >= Ftfc_Fls_Ip_u32TimeoutTicks)
+        {
+            /*Errors Timeout because wait for the Done bit long time*/
+            eRetVal = STATUS_FTFC_FLS_IP_ERROR_TIMEOUT;
+        }
+        else
+#endif
+        {
+            eRetVal = STATUS_FTFC_FLS_IP_BUSY;
+        }
+    }
+
+    return eRetVal;
+}
+
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ControllerBusy
+ * Description      Check if the flash controller is busy or not
+ */
+static Ftfc_Fls_Ip_StatusType Ftfc_Fls_Ip_ControllerBusy(void)
+{
+    Ftfc_Fls_Ip_StatusType eRetVal;
+
+    /* Check if the flash controller is idle, by polling the CCIF status bit. */
+    if (0U != (FTFx_BaseAddress->FSTAT & FTFx_FSTAT_CCIF_MASK))
+    {
+        /* CCIF = 1, memory controller is idle */
+        eRetVal = STATUS_FTFC_FLS_IP_SUCCESS;
+    }
+    else
+    {
+        /* Controller is busy */
+        eRetVal = STATUS_FTFC_FLS_IP_BUSY;
+    }
+
+    return eRetVal;
+}
+
+/**
+ *
+ * Function Name    Ftfc_Fls_Ip_ClearErrorFlags
+ * Description      Clear all error flags before lauching a new command
+ */
+static void Ftfc_Fls_Ip_ClearErrorFlags(void)
+{
+    FTFx_BaseAddress->FSTAT = (uint8)(FTFx_FSTAT_FPVIOL_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_RDCOLERR_MASK);
+}
+
+
+
+static void Ftfc_Fls_Ip_LoadFCCOBParams(const uint32 u32PhysicAddr,
+                                        const uint8 * pDataAddr,
+                                        const uint8 u8FCCOBCmdId
+                                       )
+{
+    uint32 u32FTFEAddr = 0UL;
+
+    /* convert system memory map address to FTFE module address */
+    u32FTFEAddr = Ftfc_Fls_Ip_ConvertSysToFTFEAddr(u32PhysicAddr);
+
+    FTFx_BaseAddress->FCCOB[3] = u8FCCOBCmdId;                      /* Erase Flash Sector */
+    FTFx_BaseAddress->FCCOB[2] = (uint8)(u32FTFEAddr >> 16UL);      /* Flash address [23:16] */
+    FTFx_BaseAddress->FCCOB[1] = (uint8)(u32FTFEAddr >> 8UL);       /* Flash address [15:8] */
+    FTFx_BaseAddress->FCCOB[0] = (uint8)(u32FTFEAddr >> 0UL);       /* Flash address [7:0] */
+
+    if (NULL_PTR != pDataAddr)
+    {
+        /* load the first word */
+        FTFx_BaseAddress->FCCOB[7] = pDataAddr[3];
+        FTFx_BaseAddress->FCCOB[6] = pDataAddr[2];
+        FTFx_BaseAddress->FCCOB[5] = pDataAddr[1];
+        FTFx_BaseAddress->FCCOB[4] = pDataAddr[0];
+
+        /* load the second word */
+        FTFx_BaseAddress->FCCOB[11] = pDataAddr[7];
+        FTFx_BaseAddress->FCCOB[10] = pDataAddr[6];
+        FTFx_BaseAddress->FCCOB[9]  = pDataAddr[5];
+        FTFx_BaseAddress->FCCOB[8]  = pDataAddr[4];
+    }
+}
+
+/**
+* @brief            Convert system memory map address to FTFE internal memory address
+*
+* @details          FTFE module requires flash address in 24bit format. Address passed to FTFE module
+*                   via FCCOB command object is composed of sector offset(reported to D-FLASH or P-FLASH
+*                   base address) plus the MSB bit set for DATA flash sectors and cleared for
+*                   PROGRAM flash sectors.
+*
+* @param[in]        u32SystemAddress Physical flash address in system memory map
+*
+* @return           u32FTFEAddr    FTFE internal memory address
+*/
+static uint32 Ftfc_Fls_Ip_ConvertSysToFTFEAddr(uint32 u32SystemAddress)
+{
+    uint32 u32FTFEAddr = 0x0UL;
+
+    /* check if address is a valid flash address and calculate FTFE internal memory addr */
+    if (u32SystemAddress < (FTFC_P_FLASH_BASE_ADDR + FTFC_P_FLASH_SIZE))
+    {
+        /* In P_FLASH range, valid P_FLASH addr */
+        u32FTFEAddr = u32SystemAddress - FTFC_P_FLASH_BASE_ADDR;
+    }
+    else if ( (u32SystemAddress >= FTFC_D_FLASH_BASE_ADDR) && (u32SystemAddress < (FTFC_D_FLASH_BASE_ADDR + FTFC_D_FLASH_SIZE)) )
+    {
+        /* In D_FLASH range, valid D_FLASH addr */
+        /* set the MSB of 24-bit address to distinguish between P_FLASH and D_FLASH */
+        u32FTFEAddr = (u32SystemAddress - FTFC_D_FLASH_BASE_ADDR) + 0x800000UL;
+    }
+    else
+    {
+        /* invalid flash address */
+    }
+
+    return u32FTFEAddr;
+}
+
+
+ /*
+ * Function Name    Ftfc_Fls_Ip_GetBlockNumberFromAddress
+ * Description      Get block number from address.
+ */
+Ftfc_Fls_Ip_FlashBlocksNumberType Ftfc_Fls_Ip_GetBlockNumberFromAddress(uint32 u32TargetAddress)
+{
+    Ftfc_Fls_Ip_FlashBlocksNumberType blockNumber;
+
+    if (u32TargetAddress < (uint32)FLS_P_BLOCK_SIZE)
+    {
+        /* The address is in the code block 0 */
+        blockNumber = FLS_CODE_BLOCK_0;
+    }
+    else if (u32TargetAddress < (uint32)(FLS_P_BLOCK_SIZE * 2U))
+    {
+        /* The address is in the code block 1 */
+        blockNumber = FLS_CODE_BLOCK_1;
+    }
+    else if (u32TargetAddress < (uint32)(FLS_P_BLOCK_SIZE * 3U))
+    {
+        /* The address is in the code block 2 */
+        blockNumber = FLS_CODE_BLOCK_2;
+    }
+    else if ((u32TargetAddress >= (uint32)(FTFC_D_FLASH_BASE_ADDR )) && (u32TargetAddress < (uint32)(FTFC_D_FLASH_BASE_ADDR + FTFC_D_FLASH_SIZE)))
+    {
+        /* The address is in the data */
+        blockNumber = FLS_DATA_BLOCK;
+    }
+    else
+    {
+        /* Out of bounds address */
+        blockNumber = FLS_BLOCK_INVALID;
+    }
+
+    return blockNumber;
+}
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+/**
+* @brief          Low level data storage exception handler.
+*
+* @return         Exc_CompHandlerReturnType
+* @retval         EXC_HANDLED_SKIP The data storage exception was
+*                 caused by currently pending flash read or compare job
+* @retval         EXC_UNHANDLED The data storage exception was
+*                 NOT caused by currently pending flash read or compare job
+*
+*/
+#if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+Fls_CompHandlerReturnType Ftfc_Fls_Ip_DsiHandler(const Fls_ExceptionDetailsType *pExceptionDetailsPtr)
+{
+    Fls_CompHandlerReturnType u8RetVal = FLS_UNHANDLED;
+    Ftfc_Fls_Ip_StatusType readStatus = Ftfc_Fls_Ip_eReadStatus;
+    uint32 readAddress = Ftfc_Fls_Ip_u32ReadAddressPtr;
+
+    /*  Check whether there is
+        [1] pending read, compare, erase or write job,
+        [2] exception syndrome register indicates DSI reason, and
+        [3] data_pt matches address currently accessed by pending flash read or flash compare job */
+    if ( ( STATUS_FTFC_FLS_IP_BUSY == readStatus )
+        &&
+        (FTFC_DSI_EXC_SYNDROME == (pExceptionDetailsPtr->syndrome_u32 & FTFC_DSI_EXC_SYNDROME))
+        &&
+        ( (uint32)(pExceptionDetailsPtr->data_pt) == readAddress )
+      )
+    {
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR;
+        u8RetVal = FLS_HANDLED_SKIP;
+    }
+    else
+    {
+        /* FLS_UNHANDLED */
+    }
+
+    return u8RetVal;
+}
+#else
+Fls_CompHandlerReturnType Ftfc_Fls_Ip_DsiHandler(void)
+{
+    Fls_CompHandlerReturnType u8RetVal = FLS_UNHANDLED;
+
+    /* Check whether there is a pending read, compare, erase or write job */
+    if (STATUS_FTFC_FLS_IP_BUSY == Ftfc_Fls_Ip_eReadStatus)
+    {
+        Ftfc_Fls_Ip_eReadStatus = STATUS_FTFC_FLS_IP_ERROR;
+        u8RetVal = FLS_HANDLED_SKIP;
+    }
+    else
+    {
+        /* FLS_UNHANDLED */
+    }
+
+    return u8RetVal;
+}
+#endif /* (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON) */
+
+#endif /* (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) */
+
+
+/**
+ *
+ * Function Name : Ftfc_Fls_Ip_InvalidPrefetchBuff
+ * Description   : invalidate prefect buff to make sure that the driver always reads the new data from flash
+ */
+static void Ftfc_Fls_Ip_InvalidPrefetchBuff(void)
+{
+    /* start critical section: implementation depends on integrator */
+    Ftfc_Fls_Ip_FlashAccessCalloutStart();
+
+    /* Call the function allocated on RAM */
+    #if (STD_ON == FTFC_ENABLE_USER_MODE_SUPPORT)
+    OsIf_Trusted_Call(Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram);
+    #else
+    Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram();
+    #endif
+
+    /* end flash access section: implementation depends on integrator */
+    Ftfc_Fls_Ip_FlashAccessCalloutFinish();
+}
+
+
+/**
+ *
+ * Function Name : Ftfc_Fls_Ip_GetAsyncMode
+ * Description   : set synch/Asynch at IP layer base on the bAynch of HLD
+ *
+ */
+void Ftfc_Fls_Ip_SetAsyncMode(const boolean Async)
+{
+    Ftfc_Fls_Ip_Async = Async;
+}
+
+
+/**
+ *
+ * Function Name : Ftfc_Fls_Ip_FlashAccessCalloutStart
+ * Description   : Call the callout function if it was configured
+ *
+ */
+static void Ftfc_Fls_Ip_FlashAccessCalloutStart(void)
+{
+    if (NULL_PTR != Ftfc_Fls_Ip_pConfigPtr->startFlashAccessNotifPtr)
+    {
+        Ftfc_Fls_Ip_pConfigPtr->startFlashAccessNotifPtr();
+    }
+}
+
+
+/**
+ *
+ * Function Name : Ftfc_Fls_Ip_FlashAccessCalloutFinish
+ * Description   : Call the callout function if it was configured
+ *
+ */
+static void Ftfc_Fls_Ip_FlashAccessCalloutFinish(void)
+{
+    if (NULL_PTR != Ftfc_Fls_Ip_pConfigPtr->finishedFlashAccessNotifPtr)
+    {
+        Ftfc_Fls_Ip_pConfigPtr->finishedFlashAccessNotifPtr();
+    }
+}
+
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+#if (FTFC_FLS_IP_INVALID_PREBUF_FROM_RAM == STD_ON)
+#define FLS_START_SEC_RAMCODE
+#else
+#define FLS_START_SEC_CODE
+#endif
+#include "Fls_MemMap.h"
+
+/**
+ *
+ * Function Name : Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram
+ * Description   : Invalidate prefectch buffer to make sure that the driver always reads the new data from flash
+ */
+static void Ftfc_Fls_Ip_InvalidPrefetchBuff_Ram(void)
+{
+    uint32 u32RegMscmOcmdr;
+    /* Check the status of the prefecth buffers, and invalidate them only if they are enabled.*/
+    u32RegMscmOcmdr = IP_MSCM->OCMDR[0];
+    if ( 0U == (u32RegMscmOcmdr & MSCM_OCMDR_OCM1(2)))    /* If prefetch is enabled for program flash, OCMDR0[5] == 0 */
+    {
+        IP_MSCM->OCMDR[0] = u32RegMscmOcmdr | MSCM_OCMDR_OCM1(2);  /* Set OCMDR0[5]. Disable PF for program flash */
+
+        IP_MSCM->OCMDR[0] = u32RegMscmOcmdr;                       /* Clear OCMDR0[5]. Enable PF for program flash */
+    }
+
+    u32RegMscmOcmdr = IP_MSCM->OCMDR[1];
+    if ( 0U == (u32RegMscmOcmdr & MSCM_OCMDR_OCM1(2)) )    /* If prefetch is enabled for data flash, OCMDR1[5] == 0 */
+    {
+        IP_MSCM->OCMDR[1] = u32RegMscmOcmdr | MSCM_OCMDR_OCM1(2);  /* Set OCMDR0[5]. Disable PF for data flash */
+
+        IP_MSCM->OCMDR[1] = u32RegMscmOcmdr;                       /* Clear OCMDR0[5]. Enable PF for data flash */
+    }
+}
+
+#if (FTFC_FLS_IP_INVALID_PREBUF_FROM_RAM == STD_ON)
+#define FLS_STOP_SEC_RAMCODE
+#else
+#define FLS_STOP_SEC_CODE
+#endif
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Ftfc_Fls_Ip_Ac.c

@@ -0,0 +1,188 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Ftfc_Fls_Ip_Ac.c
+*
+*   @addtogroup FTFC_FLS_IP FTFC IP Driver
+*   @{
+*/
+
+/* implements Ftfc_Fls_Ip_Ac.c_Artifact */
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Ftfc_Fls_Ip.h"
+#include "Ftfc_Fls_Ip_Cfg.h"
+#include "Ftfc_Fls_Ip_Ac.h"
+
+
+/*==================================================================================================
+ *                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_AC_VENDOR_ID_C                      43
+#define FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_C       4
+#define FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_C       4
+#define FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_C    0
+#define FTFC_FLS_IP_AC_SW_MAJOR_VERSION_C               1
+#define FTFC_FLS_IP_AC_SW_MINOR_VERSION_C               0
+#define FTFC_FLS_IP_AC_SW_PATCH_VERSION_C               0
+
+
+/*==================================================================================================
+ *                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Ftfc_Fls_Ip header file are of the same vendor */
+#if (FTFC_FLS_IP_AC_VENDOR_ID_C != FTFC_FLS_IP_VENDOR_ID_H)
+    #error "Fls_Ac.c and Ftfc_Fls_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip header file are of the same Software version */
+#if ((FTFC_FLS_IP_AC_SW_MAJOR_VERSION_C != FTFC_FLS_IP_SW_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_SW_MINOR_VERSION_C != FTFC_FLS_IP_SW_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_SW_PATCH_VERSION_C != FTFC_FLS_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip.h are different"
+#endif
+
+/* Check if current file and Ftfc_Fls_Ip_Ac.h header file have the same Vendor ID */
+#if (FTFC_FLS_IP_AC_VENDOR_ID_C != FTFC_FLS_IP_AC_VENDOR_ID_H)
+    #error "Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Ac.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Ac.h  header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Ac.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Ac.h  header file are of the same Software version */
+#if ((FTFC_FLS_IP_AC_SW_MAJOR_VERSION_C != FTFC_FLS_IP_AC_SW_MAJOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_SW_MINOR_VERSION_C != FTFC_FLS_IP_AC_SW_MINOR_VERSION_H) || \
+     (FTFC_FLS_IP_AC_SW_PATCH_VERSION_C != FTFC_FLS_IP_AC_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Ac.h are different"
+#endif
+
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file have the same Vendor ID */
+#if (FTFC_FLS_IP_AC_VENDOR_ID_C != FTFC_FLS_IP_VENDOR_ID_CFG)
+    #error "Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg.h  header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AC_AR_RELEASE_MAJOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_MINOR_VERSION_C    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FTFC_FLS_IP_AC_AR_RELEASE_REVISION_VERSION_C != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg.h  header file are of the same Software version */
+#if ((FTFC_FLS_IP_AC_SW_MAJOR_VERSION_C != FTFC_FLS_IP_SW_MAJOR_VERSION_CFG) || \
+     (FTFC_FLS_IP_AC_SW_MINOR_VERSION_C != FTFC_FLS_IP_SW_MINOR_VERSION_CFG) || \
+     (FTFC_FLS_IP_AC_SW_PATCH_VERSION_C != FTFC_FLS_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip_Ac.c and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+
+
+/*==================================================================================================
+                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+#define FLS_START_SEC_CODE_AC
+#include "Fls_MemMap.h"
+
+/* Position independent erase access code */
+#if (FTFC_TIMEOUT_SUPERVISION_ENABLED == STD_ON)
+void Ftfc_Fls_Ip_AccessCode(void (*CallBack)( void ) )
+{
+    uint32 u32ValueTimeOut = Ftfc_Fls_Ip_u32TimeoutTicks;
+    uint32 u32WaitedTicks;
+
+    FTFx_BaseAddress->FSTAT = FTFx_FSTAT_CCIF_MASK;
+    /* wait until operation finishes or write/erase timeout is reached */
+    while ((0U == ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK)) && (0U < u32ValueTimeOut))
+    {
+        u32ValueTimeOut--;
+        if (NULL_PTR != CallBack)
+        {
+            CallBack();
+        }
+    }
+
+    /* Update the timeout counter */
+    u32WaitedTicks = Ftfc_Fls_Ip_u32TimeoutTicks - u32ValueTimeOut;
+    Ftfc_Fls_Ip_u32ElapsedTicks += u32WaitedTicks;
+    Ftfc_Fls_Ip_u32CurrentTicks += u32WaitedTicks;
+}
+#else
+
+void Ftfc_Fls_Ip_AccessCode(void (*CallBack)( void ) )
+{
+    /* start internal erase/program sequence */
+    FTFx_BaseAddress->FSTAT = FTFx_FSTAT_CCIF_MASK;
+    /* wait until operation finishes or write/erase timeout is reached */
+    while (0U == ((FTFx_BaseAddress->FSTAT) & FTFx_FSTAT_CCIF_MASK))
+    {
+        if (NULL_PTR != CallBack)
+        {
+            CallBack();
+        }
+    }
+}
+#endif /* FTFC_TIMEOUT_SUPERVISION_ENABLED == STD_ON */
+
+/**
+ * @brief    Stop of Fls section CODE_AC
+ *
+ */
+#define FLS_STOP_SEC_CODE_AC
+#include "Fls_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Lpuart_Uart_Ip.c

@@ -1128,25 +1128,23 @@ static void Lpuart_Uart_Ip_RxIdleIrqHandler(uint32 Instance)
     const Lpuart_Uart_Ip_UserConfigType *UartUserCfg;
 
     LPUART_Type * Base;
-
     Base = Lpuart_Uart_Ip_apBases[Instance];
 
     UartState = (Lpuart_Uart_Ip_StateStructureType *)Lpuart_Uart_Ip_apStateStructuresArray[Instance];
     UartUserCfg = (Lpuart_Uart_Ip_UserConfigType*) Lpuart_Uart_Ip_apUserConfig[Instance];
 
-    /* Disable receive idle interrupt. */
-    Lpuart_Uart_Ip_SetIntMode(Base, (uint32)LPUART_CTRL_ILIE_SHIFT, FALSE);
-    /* Clear idle flag*/
-    Base->STAT |= LPUART_STAT_IDLE(0);
-
+//    /* Disable receive idle interrupt. */
+//    Lpuart_Uart_Ip_SetIntMode(Base, (uint32)LPUART_CTRL_ILIE_SHIFT, FALSE);
+    
     /* Invoke callback if there is one */
-
+	/* Clear idle flag*/
+	Lpuart_Uart_Ip_ClearStatusFlag(Base, LPUART_UART_IP_IDLE);
     if (UartUserCfg->Callback != NULL_PTR)
     {
     	UartUserCfg->Callback(Instance, LPUART_UART_IP_EVENT_RECV_IDLE,UartUserCfg->CallbackParam);
     }
     UartState->ReceiveStatus = LPUART_UART_IP_STATUS_SUCCESS;
-    //Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2,STD_ON);
+    Lpuart_Uart_Ip_CompleteReceiveUsingDma(Instance);
 }
 
 /*FUNCTION**********************************************************************
@@ -1225,14 +1223,11 @@ void Lpuart_Uart_Ip_IrqHandler(const uint8 Instance)
         }
 
         /*Handle receiving data idle interrupt*///zhengchao
-		if (Lpuart_Uart_Ip_GetStatusFlag(Base, (uint32)LPUART_UART_IP_IDLE) && (FALSE == IsReturn))
+		if (Lpuart_Uart_Ip_GetStatusFlag(Base, LPUART_UART_IP_IDLE) && (FALSE == IsReturn))
 		{
-			if (Lpuart_Uart_Ip_GetIntMode(Base, (uint32)LPUART_UART_IP_IDLE))
+			if (Lpuart_Uart_Ip_GetIntMode(Base, LPUART_UART_IP_IDLE))
 			{
-//				Dio_WriteChannel(DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1,STD_OFF);
 				Lpuart_Uart_Ip_RxIdleIrqHandler(Instance);
-//				Dio_WriteChannel(DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1,STD_ON);
-				//return;
 			}
 			else
 			{
@@ -1878,7 +1873,7 @@ static void Lpuart_Uart_Ip_CompleteReceiveDataUsingInt(const uint8 Instance)
     /* In Abort case, the transmission need to stop instantly */
     if (UartState->ReceiveStatus == LPUART_UART_IP_STATUS_ABORTED)
     {
-        Lpuart_Uart_Ip_StartTimeout(&StartTime, &TimeoutTicks, LPUART_UART_IP_TIMEOUT_VALUE_US, LPUART_UART_IP_TIMEOUT_TYPE);
+        Lpuart_Uart_Ip_StartTimeout(&StartTime, &TimeoutTicks, LPUART_UART_IP_TIMEOUT_VALUE_US/10, LPUART_UART_IP_TIMEOUT_TYPE);
         /* Wait until the data is completely received */
         while (!Lpuart_Uart_Ip_GetStatusFlag(Base, LPUART_UART_IP_DATA_REG_FULL) && \
                !Lpuart_Uart_Ip_CheckTimeout(&StartTime, &ElapsedTicks, TimeoutTicks, LPUART_UART_IP_TIMEOUT_TYPE))
@@ -1990,7 +1985,7 @@ void Lpuart_Uart_Ip_CompleteReceiveUsingDma(uint8 Instance)
         if (UartState->ReceiveStatus == LPUART_UART_IP_STATUS_ABORTED)
         {
             /* Wait until the last transmission complete */
-            Lpuart_Uart_Ip_StartTimeout(&StartTime, &TimeoutTicks, LPUART_UART_IP_TIMEOUT_VALUE_US, LPUART_UART_IP_TIMEOUT_TYPE);
+            Lpuart_Uart_Ip_StartTimeout(&StartTime, &TimeoutTicks, LPUART_UART_IP_TIMEOUT_VALUE_US/10, LPUART_UART_IP_TIMEOUT_TYPE);
             while (!Lpuart_Uart_Ip_GetStatusFlag(Base, LPUART_UART_IP_DATA_REG_FULL) && \
                !Lpuart_Uart_Ip_CheckTimeout(&StartTime, &ElapsedTicks, TimeoutTicks, LPUART_UART_IP_TIMEOUT_TYPE))
             {}
@@ -2038,7 +2033,7 @@ static void Lpuart_Uart_Ip_SetupIntDmaMode(const uint8 Instance, boolean Enable)
       Base = Lpuart_Uart_Ip_apBases[Instance];
 
       /* Setup error interrupts */
-      Lpuart_Uart_Ip_SetIntMode(Base, LPUART_UART_IP_INT_RX_OVERRUN, Enable);
+      Lpuart_Uart_Ip_SetIntMode(Base, LPUART_UART_IP_INT_RX_OVERRUN, 0);
       Lpuart_Uart_Ip_SetIntMode(Base, LPUART_UART_IP_INT_PARITY_ERR_FLAG, Enable);
       Lpuart_Uart_Ip_SetIntMode(Base, LPUART_UART_IP_INT_NOISE_ERR_FLAG, Enable);
       Lpuart_Uart_Ip_SetIntMode(Base, LPUART_UART_IP_INT_FRAME_ERR_FLAG, Enable);

RTD/src/Os_counter_api.c

@@ -0,0 +1,78 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Os_counter_api.c
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Os.h"
+
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+StatusType GetCounterValue (CounterType ctrId, TickRefType tickRef)
+{
+    (void)ctrId;
+    (void)tickRef;
+    return (StatusType)E_OK;
+}
+
+StatusType GetElapsedValue (CounterType ctrId, TickRefType valueRef, TickRefType tickRef)
+{
+    (void)ctrId;
+    (void)valueRef;
+    (void)tickRef;
+    return (StatusType)E_OK;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

RTD/src/Os_multicore.c

@@ -0,0 +1,71 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : generic
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Os_multicore.c
+*
+*   @addtogroup [OS]
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Os.h"
+#include "Os_multicore.h"
+#include "Mcal.h"
+
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                        LOCAL FUNCTION DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

RTD/src/Qspi_Ip.c

@@ -0,0 +1,1549 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Qspi_Ip.c
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "Qspi_Ip_Cfg.h"
+#include "Qspi_Ip_Controller.h"
+#include "Qspi_Ip_Common.h"
+#include "Qspi_Ip.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_C                    43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_C     4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_C     4
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_C  0
+#define QSPI_IP_SW_MAJOR_VERSION_C             1
+#define QSPI_IP_SW_MINOR_VERSION_C             0
+#define QSPI_IP_SW_PATCH_VERSION_C             0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Cfg header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_VENDOR_ID_CFG)
+    #error "Qspi_Ip.c and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.c and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.c and Qspi_Ip_Cfg.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Controller header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_CONTROLLER_VENDOR_ID_H)
+    #error "Qspi_Ip.c and Qspi_Ip_Controller.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.c and Qspi_Ip_Controller.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.c and Qspi_Ip_Controller.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Common header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_COMMON_VENDOR_ID_H)
+    #error "Qspi_Ip.c and Qspi_Ip_Common.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.c and Qspi_Ip_Common.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.c and Qspi_Ip_Common.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip.c and Qspi_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip.c and Qspi_Ip.h are different"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip.c and Qspi_Ip.h are different"
+#endif
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+ /* Last command sent to the flash device */
+#define QSPI_IP_LAST_COMMAND_NONE     0U
+#define QSPI_IP_LAST_COMMAND_WRITE    1U
+#define QSPI_IP_LAST_COMMAND_ERASE    2U
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* Pointer to runtime state structures */
+static Qspi_Ip_StateType Qspi_Ip_MemoryStateStructure[QSPI_IP_MEM_INSTANCE_COUNT];
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+static Qspi_Ip_StatusType Qspi_Ip_WriteEnable(uint32 instance);
+static Qspi_Ip_StatusType Qspi_Ip_InitReset(uint32 instance, uint16 resetCmdLut, uint8 resetCmdCount, const Qspi_Ip_StateType * state);
+static Qspi_Ip_StatusType Qspi_Ip_InitWriteReg(uint32 instance, const Qspi_Ip_InitOperationType * operation);
+static Qspi_Ip_StatusType Qspi_Ip_InitRMWReg(uint32 instance, const Qspi_Ip_InitOperationType * operation);
+static Qspi_Ip_StatusType Qspi_Ip_InitReadReg(uint32 instance, const Qspi_Ip_InitOperationType * operation);
+static Qspi_Ip_StatusType Qspi_Ip_InitProtection(uint32 instance, const Qspi_Ip_StateType * state);
+static Qspi_Ip_StatusType Qspi_Ip_InitOperation(uint32 instance, const Qspi_Ip_StateType * state, uint8 initOp);
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitLutSeq
+ * Description   : Initializes one sequence in the LUT table from a virtual table sequence. Returns start index of next sequence.
+* @implements      Qspi_Ip_InitLutSeq_Activity */
+static uint16 Qspi_Ip_InitLutSeq(uint32 instance, uint16 virtualLutIdx, uint8 lutIndex)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_InstrOpType *virtualLutTable = state->configuration->lutSequences.lutOps;
+    Qspi_Ip_InstrOpType operation1, operation2;
+    uint16 vLutIdx = virtualLutIdx;         /* Index in virtual LUT  */
+    uint8 lutIdx = 0U;                      /* Index in phisical LUT */
+
+    do
+    {
+        DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount);
+        operation1 = virtualLutTable[vLutIdx];
+        vLutIdx++;
+        operation2 = QSPI_IP_LUT_SEQ_END;
+        if (operation1 != QSPI_IP_LUT_SEQ_END)
+        {
+            DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount);
+            operation2 = virtualLutTable[vLutIdx];
+            vLutIdx++;
+        }
+        /* Add two operations to lut sequence */
+        DEV_ASSERT_QSPI(lutIdx < FEATURE_QSPI_LUT_SEQUENCE_SIZE);
+        Qspi_Ip_SetLut(instance, (FEATURE_QSPI_LUT_SEQUENCE_SIZE * lutIndex) + lutIdx, operation1, operation2);
+        lutIdx++;
+    }
+    while (operation2 != QSPI_IP_LUT_SEQ_END);
+
+    return vLutIdx;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetValue
+ * Description   : Converts a long value in data to be sent to flash
+* @implements      Qspi_Ip_SetValue_Activity */
+static inline void Qspi_Ip_SetValue(uint8 *data, uint8 size, uint32 value)
+{
+    uint8 cnt;
+    uint32 temp = value;
+
+    /* Put value in the data buffer */
+    for (cnt = 0U; cnt < size; cnt++)
+    {
+        data[cnt] = (uint8)(temp & 0xFFU);
+        temp >>= 8U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetBitfield
+ * Description   : Sets a new value in a register bitfield
+* @implements      Qspi_Ip_SetBitfield_Activity */
+static void Qspi_Ip_SetBitfield(uint8 *data, uint8 size, uint8 shift, uint8 width, uint32 value)
+{
+    uint8 cnt;
+    uint32 longData = 0UL;
+    uint32 mask;
+
+    /* Pack data in a long value */
+    for (cnt = 0U; cnt < size; cnt++)
+    {
+        longData = (longData << 8U) + data[cnt];
+    }
+    /* Apply change */
+    mask = ((1UL << (uint32)width) - 1UL) << (uint32)shift;
+    longData &= ~mask;
+    longData |= (value << shift) & mask;
+    /* Put data back in the data buffer */
+    for (cnt = 0U; cnt < size; cnt++)
+    {
+        data[cnt] = (uint8)(longData & 0xFFU);
+        longData >>= 8U;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_GetBitfield
+ * Description   : Extracts the value of a register bitfield
+ * @implements     Qspi_Ip_GetBitfield_Activity */
+static uint32 Qspi_Ip_GetBitfield(const uint8 *data, uint8 size, uint8 shift, uint8 width)
+{
+    uint8 cnt;
+    uint32 longData = 0U;
+    uint32 mask;
+    uint32 value;
+
+    /* Pack data in a long value */
+    for (cnt = 0U; cnt < size; cnt++)
+    {
+        longData = (longData << 8U) + data[cnt];
+    }
+    /* Extract field */
+    mask = (1UL << (uint32)width) - 1UL;
+    value = (longData >> shift) & mask;
+    return value;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_UpdateStatusReg
+ * Description   : Updates a bitfield in the status register
+* @implements      Qspi_Ip_UpdateStatusReg_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_UpdateStatusReg(uint32 instance, uint8 offset, uint8 width, uint8 value)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+    uint8 data[4U];
+    Qspi_Ip_StatusType status;
+
+    /* Read status register */
+    status = Qspi_Ip_RunReadCommand(instance, statusConfig->statusRegReadLut, 0U, data, NULL_PTR, statusConfig->regSize);
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Check existing value, write status register only if needed */
+        if (value != Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width))
+        {
+            Qspi_Ip_SetBitfield(data, statusConfig->regSize, offset, width, value);
+        }
+        /* send WREN command for status register */
+        if (statusConfig->writeEnableSRLut != QSPI_IP_LUT_INVALID)
+        {
+            status = Qspi_Ip_RunCommand(instance, statusConfig->writeEnableSRLut, 0U);
+        }
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* send write status register command */
+            status = Qspi_Ip_RunWriteCommand(instance, statusConfig->statusRegWriteLut, 0U, data, statusConfig->regSize);
+        }
+    }
+
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_CheckStatusReg
+ * Description   : Checks a bitfield in the status register
+* @implements      Qspi_Ip_CheckStatusReg_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_CheckStatusReg(uint32 instance, uint8 offset, uint8 width, uint8 *value)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+    uint8 data[4];
+    Qspi_Ip_StatusType status;
+
+    /* Read status register */
+    status = Qspi_Ip_RunReadCommand(instance, statusConfig->statusRegReadLut, 0U, data, NULL_PTR, statusConfig->regSize);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Extract bit-field */
+        *value = (uint8)Qspi_Ip_GetBitfield(data, statusConfig->regSize, offset, width);
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_WriteEnable
+ * Description   : Enables the serial flash memory for a program or erase operation
+* @implements      Qspi_Ip_WriteEnable_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_WriteEnable(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+
+    uint32 retries = QSPI_IP_MAX_RETRY + 1U;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_TIMEOUT;
+    Qspi_Ip_StatusType cmdStatus;
+    uint8 welValue = 0U;
+
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPCOMMAND_WAIT_IN_WREN);
+
+    while (retries > 0UL)
+    {
+        /* send WREN command */
+        cmdStatus = Qspi_Ip_RunCommand(instance, statusConfig->writeEnableLut, 0U);
+        if (cmdStatus != STATUS_QSPI_IP_SUCCESS)
+        {
+            status = cmdStatus;
+        }
+        /* check WEL bit */
+        cmdStatus = Qspi_Ip_CheckStatusReg(instance, statusConfig->writeEnableOffset, 1U, &welValue);
+        if (STATUS_QSPI_IP_SUCCESS == cmdStatus)
+        {
+            /* 1 == check WEL */
+            if (1U == welValue)
+            {
+                status = STATUS_QSPI_IP_SUCCESS;
+                break;
+            }
+        }
+        else
+        {
+            /* record error */
+            status = cmdStatus;
+        }
+        retries--;
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_BasicErase
+ * Description   : Perform one of the supported erase types in the serial flash.
+ * @implements      Qspi_Ip_BasicErase_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_BasicErase(uint32 instance, uint32 address, uint16 eraseLut)
+{
+    Qspi_Ip_StatusType status;
+
+    /* enable write before erasing */
+    status = Qspi_Ip_WriteEnable(instance);
+
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPCOMMAND_WAIT_IN_BASICERS);
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* launch erase command and return */
+        status = Qspi_Ip_RunCommand(instance, eraseLut, address);
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_CheckMemoryStatus
+ * Description   : Check that the memory is idle. Used internally by the driver during initialization
+ */
+static Qspi_Ip_StatusType Qspi_Ip_CheckMemoryStatus(uint32 instance, uint16 lut)
+{
+    Qspi_Ip_StatusType status;
+    uint8 busyValue;
+    uint8 data[4];
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+
+    /* Check if the QuadSPI controller is idle */
+    status = Qspi_Ip_ControllerGetStatus(state->connection->qspiInstance);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Check if the operation has finished in the serial flash */
+        /* Read status register */
+        status = Qspi_Ip_RunReadCommand(instance, lut, 0U, data, NULL_PTR, statusConfig->regSize);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* Extract bit-field */
+            busyValue = (uint8)Qspi_Ip_GetBitfield(data, statusConfig->regSize, statusConfig->busyOffset, 1U);
+            if (busyValue == statusConfig->busyValue)
+            {
+                /* Flash device is busy */
+                status = STATUS_QSPI_IP_BUSY;
+            }
+        }
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_CheckCommandComplete
+ * Description   : Wait until external memory is not busy
+* @implements      Qspi_Ip_CheckCommandComplete_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_CheckCommandComplete(uint32 instance, uint16 lut)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_FLS_INIT_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    /* Wait for the command to complete */
+    do
+    {
+        /* Get memory status */
+        status = Qspi_Ip_CheckMemoryStatus(instance, lut);
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        /* Check timeout */
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+    }
+    while (STATUS_QSPI_IP_BUSY == status);
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_CheckResetComplete
+ * Description   : Wait until external memory is available for operation after a reset
+* @implements      Qspi_Ip_CheckResetComplete_Activity */
+static void Qspi_Ip_CheckResetComplete(void)
+{
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_RESET_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    /* Wait for the specified time */
+    do
+    {
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    }
+    while (u32ElapsedTicks < u32TimeoutTicks);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitWriteReg
+ * Description   : Write the configured value into a register of external flash device
+* @implements      Qspi_Ip_InitWriteReg_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitWriteReg(uint32 instance, const Qspi_Ip_InitOperationType * operation)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint8 value[4U];
+
+    /* write a value in a register */
+    if (QSPI_IP_LUT_INVALID != operation->weLut)
+    {
+        /* send WREN command */
+        status = Qspi_Ip_RunCommand(instance, operation->weLut, operation->addr);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            Qspi_Ip_SetValue(value, operation->size, operation->value);
+            status = Qspi_Ip_RunWriteCommand(instance, operation->command1Lut, operation->addr, value, operation->size);
+        }
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitRMWReg
+ * Description   : Change a bitfield in a register of external flash device
+* @implements      Qspi_Ip_InitRMWReg_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitRMWReg(uint32 instance, const Qspi_Ip_InitOperationType * operation)
+{
+    Qspi_Ip_StatusType status;
+    uint32 fieldVal;
+    uint8 value[4U];
+
+    /* Read current register value */
+    status = Qspi_Ip_RunReadCommand(instance, operation->command1Lut, operation->addr, value, NULL_PTR, operation->size);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Retrieve target bitfield */
+        fieldVal = Qspi_Ip_GetBitfield(value, operation->size, operation->shift, operation->width);
+        if (fieldVal != operation->value)
+        {
+            /* Modify target bitfield */
+            Qspi_Ip_SetBitfield(value, operation->size, operation->shift, operation->width, operation->value);
+            if (QSPI_IP_LUT_INVALID != operation->weLut)
+            {
+                /* Send WREN command */
+                status = Qspi_Ip_RunCommand(instance, operation->weLut, operation->addr);
+            }
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                /* Write back register value; use second LUT command */
+                status = Qspi_Ip_RunWriteCommand(instance, operation->command2Lut, operation->addr, (uint8 *)&value, operation->size);
+            }
+        }
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitReadReg
+ * Description   : Read the register's value of external flash device and loop until matching the configured one
+* @implements      Qspi_Ip_InitReadReg_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitReadReg(uint32 instance, const Qspi_Ip_InitOperationType * operation)
+{
+    Qspi_Ip_StatusType status;
+    uint32 fieldVal = 0UL;
+    uint8 value[4U];
+    uint32 u32ElapsedTicks = 0UL;
+    uint32 u32TimeoutTicks;
+    uint32 u32CurrentTicks;
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_FLS_INIT_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    do
+    {
+        /* read current register value */
+        status = Qspi_Ip_RunReadCommand(instance, operation->command1Lut, operation->addr, value, NULL_PTR, operation->size);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* retrieve target bitfield */
+            fieldVal = Qspi_Ip_GetBitfield(value, operation->size, operation->shift, operation->width);
+        }
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+    }
+    while (fieldVal != operation->value);
+
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitOperation
+ * Description   : Execute initialization sequence to get the serial flash memory in the target state for operation */
+static Qspi_Ip_StatusType Qspi_Ip_InitOperation (uint32 instance, const Qspi_Ip_StateType * state, uint8 initOp)
+{
+    const Qspi_Ip_InitOperationType *initOperations;
+    Qspi_Ip_StatusType status;
+
+    status = STATUS_QSPI_IP_SUCCESS;
+    initOperations = state->configuration->initConfiguration.operations;
+
+    switch (initOperations[initOp].opType)
+    {
+        case QSPI_IP_OP_TYPE_CMD:
+            /* Execute a simple command */
+            status = Qspi_Ip_RunCommand(instance, initOperations[initOp].command1Lut, initOperations[initOp].addr);
+            break;
+
+        case QSPI_IP_OP_TYPE_WRITE_REG:
+            /* Write value into the register */
+            status = Qspi_Ip_InitWriteReg(instance, &initOperations[initOp]);
+            break;
+
+        case QSPI_IP_OP_TYPE_RMW_REG:
+            /* Change a bitfield in the register */
+            status = Qspi_Ip_InitRMWReg(instance, &initOperations[initOp]);
+            break;
+
+        case QSPI_IP_OP_TYPE_READ_REG:
+            /* Check a bitfield in the register */
+            status = Qspi_Ip_InitReadReg(instance, &initOperations[initOp]);
+            break;
+
+        case QSPI_IP_OP_TYPE_QSPI_CFG:
+            /* Re-initialize QSPI controller with the given configuration */
+            (void)Qspi_Ip_ControllerDeinit(state->connection->qspiInstance);
+            status = Qspi_Ip_ControllerInit(state->connection->qspiInstance, initOperations[initOp].ctrlCfgPtr);
+            break;
+
+        default:
+            ; /* unknown operation */
+            break;
+    }   /* switch */
+
+    return status;
+
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitDevice
+ * Description   : Execute initialization sequence to get the serial flash memory in the target state for operation
+* @implements      Qspi_Ip_InitDevice_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitDevice(uint32 instance, const Qspi_Ip_StateType * state)
+{
+    Qspi_Ip_StatusType status;
+    uint8 initConfigOpCount;
+    uint8 initOp;
+
+    status = STATUS_QSPI_IP_SUCCESS;
+
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPCOMMAND_INITDEVICE);
+
+    /* Perform operations in initialization list */
+    initConfigOpCount = state->configuration->initConfiguration.opCount;
+    if (initConfigOpCount > 0U)
+    {
+        for (initOp = 0; initOp < initConfigOpCount; initOp++)
+        {
+            /* Ensure the previous command is completed */
+            status = Qspi_Ip_CheckCommandComplete(instance, state->configuration->statusConfig.statusRegInitReadLut);
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                status = Qspi_Ip_InitOperation(instance, state, initOp);
+            }
+
+            if (STATUS_QSPI_IP_SUCCESS != status)
+            {
+                break;
+            }
+        }   /* for */
+    }  /* if (initConfigOpCount > 0U) */
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitProtection
+ * Description   : Update the protection configuration value if needed
+* @implements      Qspi_Ip_InitProtection_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitProtection(uint32 instance, const Qspi_Ip_StateType * state)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint8 configProtection = state->configuration->statusConfig.blockProtectionValue;
+    uint8 getProtection = 0U;
+
+    if (state->configuration->statusConfig.blockProtectionWidth != 0U)
+    {
+        /* Ensure the previous command is completed */
+        status = Qspi_Ip_CheckCommandComplete(instance, state->configuration->statusConfig.statusRegReadLut);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* Read and check the current setting */
+            status = Qspi_Ip_GetProtection(instance, &getProtection);
+            if ((STATUS_QSPI_IP_SUCCESS == status) && (getProtection != configProtection))
+            {
+                /* Set new setting */
+                status = Qspi_Ip_SetProtection(instance, configProtection);
+                if (STATUS_QSPI_IP_SUCCESS == status)
+                {
+                    /* Ensure the write is completed  */
+                    status = Qspi_Ip_CheckCommandComplete(instance, state->configuration->statusConfig.statusRegReadLut);
+                }
+            }
+        }
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InitReset
+ * Description   : Perform the software reset sequence
+* @implements      Qspi_Ip_InitReset_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_InitReset(uint32 instance, uint16 resetCmdLut, uint8 resetCmdCount, const Qspi_Ip_StateType * state)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint16 crtLut = resetCmdLut;
+    uint8 cnt;
+
+    if (QSPI_IP_LUT_INVALID != resetCmdLut)
+    {
+        for (cnt = 0U; cnt < resetCmdCount; cnt++)
+        {
+            /* Copy sequence in LUT registers */
+            crtLut = Qspi_Ip_InitLutSeq(instance, crtLut, QSPI_IP_COMMAND_LUT);
+
+            /* Run QSPI command */
+            status = Qspi_Ip_IpCommand(state->connection->qspiInstance, QSPI_IP_COMMAND_LUT, state->baseAddress);
+            if (status != STATUS_QSPI_IP_SUCCESS)
+            {
+                break;
+            }
+        }
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* Ensure flash is ready after reset */
+            Qspi_Ip_CheckResetComplete();
+        }
+    }
+
+    return status;
+}
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_RunCommand
+ * Description   : Launches a simple command for the serial flash
+* @implements      Qspi_Ip_RunCommand_Activity */
+Qspi_Ip_StatusType Qspi_Ip_RunCommand(uint32 instance,
+                                      uint16 lut,
+                                      uint32 addr
+                                     )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID);
+    DEV_ASSERT_QSPI(addr < state->configuration->memSize);
+    if (QSPI_IP_LUT_INVALID == lut)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    else
+    {
+        /* Copy sequence in LUT registers */
+        (void)Qspi_Ip_InitLutSeq(instance, lut, QSPI_IP_COMMAND_LUT);
+
+        /* Run QSPI command */
+        status = Qspi_Ip_IpCommand(state->connection->qspiInstance, QSPI_IP_COMMAND_LUT, state->baseAddress + addr);
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_RunReadCommand
+ * Description   : Launches a read command for the serial flash
+* @implements      Qspi_Ip_RunReadCommand_Activity */
+Qspi_Ip_StatusType Qspi_Ip_RunReadCommand(uint32 instance,
+                                          uint16 lut,
+                                          uint32 addr,
+                                          uint8 * dataRead,
+                                          const uint8 * dataCmp,
+                                          uint32 size
+                                         )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID);
+    DEV_ASSERT_QSPI(addr < state->configuration->memSize);
+    DEV_ASSERT_QSPI((size > 0UL) && ((addr + size) <= state->configuration->memSize));
+
+    if (QSPI_IP_LUT_INVALID == lut)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    else
+    {
+        /* Copy sequence in LUT registers */
+        (void)Qspi_Ip_InitLutSeq(instance, lut, QSPI_IP_COMMAND_LUT);
+
+        /* Run QSPI command */
+        status = Qspi_Ip_IpRead(state->connection->qspiInstance, QSPI_IP_COMMAND_LUT, state->baseAddress + addr, dataRead, dataCmp, size);
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_RunWriteCommand
+ * Description   : Launches a write command for the serial flash
+ * @implements     Qspi_Ip_RunWriteCommand_Activity */
+Qspi_Ip_StatusType Qspi_Ip_RunWriteCommand(uint32 instance,
+                                           uint16 lut,
+                                           uint32 addr,
+                                           const uint8 * data,
+                                           uint32 size
+                                          )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID);
+    DEV_ASSERT_QSPI(addr < state->configuration->memSize);
+    DEV_ASSERT_QSPI((size > 0UL) && ((addr + size) <= state->configuration->memSize));
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+
+    if (QSPI_IP_LUT_INVALID == lut)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    else
+    {
+        /* Copy sequence in LUT registers */
+        (void)Qspi_Ip_InitLutSeq(instance, lut, QSPI_IP_COMMAND_LUT);
+
+        /* Run QSPI command */
+        status = Qspi_Ip_IpWrite(state->connection->qspiInstance, QSPI_IP_COMMAND_LUT, state->baseAddress + addr, data, size);
+    }
+
+    return status;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_EraseBlock
+ * Description   : Erase a sector in the serial flash.
+ *                 The size must match one of the device's erase types.
+ * @implements     Qspi_Ip_EraseBlock_Activity */
+Qspi_Ip_StatusType Qspi_Ip_EraseBlock(uint32 instance,
+                                      uint32 address,
+                                      uint32 size
+                                     )
+{
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+    uint8 eraseType;
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(address < state->configuration->memSize);
+    DEV_ASSERT_QSPI((size > 0UL) && ((address + size) <= state->configuration->memSize));
+    /* Check address range */
+    if (address < state->configuration->memSize)
+    {
+        /* find the suited erase type */
+        for (eraseType = 0U; eraseType < QSPI_IP_ERASE_TYPES; eraseType++)
+        {
+            if ((state->configuration->eraseSettings.eraseTypes[eraseType].eraseLut != QSPI_IP_LUT_INVALID) &&
+                (size == (uint32)((uint32)1U << (state->configuration->eraseSettings.eraseTypes[eraseType].size))))
+            {
+                break;
+            }
+            else
+            {
+                /* Empty clause added to fulfill MISRA. */
+            }
+        }
+        /* if erase type was found, launch the erase */
+        if (eraseType < QSPI_IP_ERASE_TYPES)
+        {
+            status = Qspi_Ip_BasicErase(instance, address, state->configuration->eraseSettings.eraseTypes[eraseType].eraseLut);
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                state->lastCommand = QSPI_IP_LAST_COMMAND_ERASE;
+            }
+        }
+        else
+        {
+            /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_EraseChip
+ * Description   : Erase the entire serial flash
+ * @implements     Qspi_Ip_EraseChip_Activity */
+Qspi_Ip_StatusType Qspi_Ip_EraseChip(uint32 instance)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    if (state->configuration->eraseSettings.chipEraseLut != QSPI_IP_LUT_INVALID)
+    {
+        /* enable write before erasing */
+        status = Qspi_Ip_WriteEnable(instance);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* launch erase command */
+            status = Qspi_Ip_RunCommand(instance, state->configuration->eraseSettings.chipEraseLut, 0U);
+        }
+        else
+        {
+            /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProgramSuspend
+ * Description   : Suspends a program operation
+ * @implements     Qspi_Ip_ProgramSuspend_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ProgramSuspend(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    return Qspi_Ip_RunCommand(instance, state->configuration->suspendSettings.programSuspendLut, 0U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProgramResume
+ * Description   : Resumes a program operation
+ * @implements     Qspi_Ip_ProgramResume_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ProgramResume(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    return Qspi_Ip_RunCommand(instance, state->configuration->suspendSettings.programResumeLut, 0U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_EraseSuspend
+ * Description   : Suspends an erase operation
+ * @implements     Qspi_Ip_EraseSuspend_Activity */
+Qspi_Ip_StatusType Qspi_Ip_EraseSuspend(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    return Qspi_Ip_RunCommand(instance, state->configuration->suspendSettings.eraseSuspendLut, 0U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_EraseResume
+ * Description   : Resumes an erase operation
+ * @implements     Qspi_Ip_EraseResume_Activity */
+Qspi_Ip_StatusType Qspi_Ip_EraseResume(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    return Qspi_Ip_RunCommand(instance, state->configuration->suspendSettings.eraseResumeLut, 0U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Reset
+ * Description   : Issues a software reset command
+ * @implements     Qspi_Ip_Reset_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Reset(uint32 instance)
+{
+    uint16 resetCmdLut;        /*!< First command in reset sequence            */
+    uint8 resetCmdCount;       /*!< Number of commands in reset sequence       */
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    resetCmdLut = state->configuration->resetSettings.resetCmdLut;
+    if (QSPI_IP_LUT_INVALID != resetCmdLut)
+    {
+        resetCmdCount = state->configuration->resetSettings.resetCmdCount;
+        /* Perform reset */
+        status = Qspi_Ip_InitReset(instance, resetCmdLut, resetCmdCount, state);
+        /* Bring corresponding controller to initial configuration if required */
+        if ((STATUS_QSPI_IP_SUCCESS == status) && (state->configuration->ctrlAutoCfgPtr != NULL_PTR))
+        {
+            status = Qspi_Ip_ControllerInit(state->connection->qspiInstance, state->configuration->ctrlAutoCfgPtr);
+        }
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* Execute initial setup of external device */
+            status = Qspi_Ip_InitDevice(instance, state);
+        }
+    }
+
+    /* If enabled, call the reset callout. */
+    if (NULL_PTR != state->configuration->resetCallout)
+    {
+        status = state->configuration->resetCallout(instance);
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_GetMemoryStatus
+ * Description   : Get the status of the last operation
+ * @implements     Qspi_Ip_GetMemoryStatus_Activity */
+Qspi_Ip_StatusType Qspi_Ip_GetMemoryStatus(uint32 instance)
+{
+    Qspi_Ip_StatusType status;
+    uint8 busyValue;
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    /* Check if the QuadSPI command is complete */
+    status = Qspi_Ip_ControllerGetStatus(state->connection->qspiInstance);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Check if the operation has finished in the serial flash */
+        status = Qspi_Ip_CheckStatusReg(instance, statusConfig->busyOffset, 1U, &busyValue);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            /* Check BUSY value */
+            if (busyValue == statusConfig->busyValue)
+            {
+                /* Write/erase in progress */
+                status = STATUS_QSPI_IP_BUSY;
+            }
+            else
+            {
+                /* Call user callout, if available, to check operation result */
+                if ((state->lastCommand != QSPI_IP_LAST_COMMAND_NONE) && (NULL_PTR != state->configuration->errorCheckCallout))
+                {
+                    status = state->configuration->errorCheckCallout(instance);
+                }
+                state->lastCommand = QSPI_IP_LAST_COMMAND_NONE;
+            }
+        }
+        else
+        {
+            /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+
+    return status;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Read
+ * Description   : Read data from serial flash
+ * @implements     Qspi_Ip_Read_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Read(uint32 instance,
+                                uint32 address,
+                                uint8 * data,
+                                uint32 size
+                               )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    uint32 crtAddress = address;
+    uint8 * crtData = data;
+    uint32 crtSize = size;
+    uint32 chunkSize = QSPI_IP_MAX_READ_SIZE;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    DEV_ASSERT_QSPI(crtAddress < state->configuration->memSize);
+    DEV_ASSERT_QSPI((crtSize > 0UL) && ((crtAddress + crtSize) <= state->configuration->memSize));
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_READ_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    while ((crtSize > 0UL) && (STATUS_QSPI_IP_SUCCESS == status))
+    {
+        if (chunkSize > crtSize)
+        {
+            /* Adjust size for last chunk */
+            chunkSize = crtSize;
+        }
+        /* Check timeout */
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+        status = Qspi_Ip_RunReadCommand(instance, state->activeReadLut, crtAddress, crtData, NULL_PTR, chunkSize);
+        /* Move to next chunk */
+        crtSize -= chunkSize;
+        crtAddress += chunkSize;
+        crtData = &(crtData[chunkSize]);
+
+        /* Call user callout, if available, to check ecc status */
+        if ( (STATUS_QSPI_IP_SUCCESS == status) && (NULL_PTR != state->configuration->errorCheckCallout) )
+        {
+            status = state->configuration->eccCheckCallout(instance, crtAddress, chunkSize);
+        }
+    }
+    return status;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ReadId
+ * Description   : Read manufacturer ID from serial flash
+ * @implements     Qspi_Ip_ReadId_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ReadId(uint32 instance,
+                                  uint8 * data
+                                 )
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+
+    return Qspi_Ip_RunReadCommand(instance,
+                                  state->configuration->readIdSettings.readIdLut,
+                                  0U,
+                                  data,
+                                  NULL_PTR,
+                                  state->configuration->readIdSettings.readIdSize);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProgramVerify
+ * Description   : Verifies data written in serial flash
+ * @implements     Qspi_Ip_ProgramVerify_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ProgramVerify(uint32 instance,
+                                         uint32 address,
+                                         const uint8 * data,
+                                         uint32 size
+                                        )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    uint32 crtAddress = address;
+    const uint8 * crtData = data;
+    uint32 crtSize = size;
+    uint32 chunkSize = QSPI_IP_MAX_READ_SIZE;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    DEV_ASSERT_QSPI(crtAddress < state->configuration->memSize);
+    DEV_ASSERT_QSPI((crtSize > 0UL) && ((crtAddress + crtSize) <= state->configuration->memSize));
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_READ_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    while ((crtSize > 0U) && (STATUS_QSPI_IP_SUCCESS == status))
+    {
+        if (chunkSize > crtSize)
+        {
+            /* Adjust size for last chunk */
+            chunkSize = crtSize;
+        }
+        /* Check timeout */
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+        status = Qspi_Ip_RunReadCommand(instance, state->activeReadLut, crtAddress, NULL_PTR, crtData, chunkSize);
+        /* Move to next chunk */
+        crtSize -= chunkSize;
+        crtAddress += chunkSize;
+        crtData = &(crtData[chunkSize]);
+    }
+    return status;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_EraseVerify
+ * Description   : Verifies that an area in serial flash is in erased state
+ * @implements     Qspi_Ip_EraseVerify_Activity */
+Qspi_Ip_StatusType Qspi_Ip_EraseVerify(uint32 instance,
+                                       uint32 address,
+                                       uint32 size
+                                      )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    uint32 crtAddress = address;
+    uint32 crtSize = size;
+    uint32 chunkSize = QSPI_IP_MAX_READ_SIZE;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    DEV_ASSERT_QSPI(crtAddress < state->configuration->memSize);
+    DEV_ASSERT_QSPI((crtSize > 0UL) && ((crtAddress + crtSize) <= state->configuration->memSize));
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_READ_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    while ((crtSize > 0UL) && (STATUS_QSPI_IP_SUCCESS == status))
+    {
+        if (chunkSize > crtSize)
+        {
+            /* Adjust size for last chunk */
+            chunkSize = crtSize;
+        }
+        /* Check timeout */
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+        status = Qspi_Ip_RunReadCommand(instance, state->activeReadLut, crtAddress, NULL_PTR, NULL_PTR, chunkSize);
+        /* Move to next chunk */
+        crtSize -= chunkSize;
+        crtAddress += chunkSize;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Program
+ * Description   : Writes data in serial flash
+ * @implements     Qspi_Ip_Program_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Program(uint32 instance,
+                                   uint32 address,
+                                   const uint8 * data,
+                                   uint32 size
+                                  )
+{
+    Qspi_Ip_StatusType status;
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(address < state->configuration->memSize);
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+    DEV_ASSERT_QSPI((size > 0UL) && ((address + size) <= state->configuration->memSize));
+
+    /* Check address range and page size */
+    if ((address >= state->configuration->memSize) || ((size > state->configuration->pageSize)))
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    else
+    {
+        /* enable write before programming */
+        status = Qspi_Ip_WriteEnable(instance);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            status = Qspi_Ip_RunWriteCommand(instance, state->configuration->writeLut, address, data, size);
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                state->lastCommand = QSPI_IP_LAST_COMMAND_WRITE;
+            }
+        }
+        else
+        {
+            /* Empty clause added to fulfill MISRA. */
+        }
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Enter0XX
+ * Description   : Enters 0-X-X mode (no command for read instructions)
+ * @implements     Qspi_Ip_Enter0XX_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Enter0XX(uint32 instance)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    uint8 dummyData;
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    if (state->configuration->read0xxLut != QSPI_IP_LUT_INVALID)
+    {
+        state->activeReadLut = state->configuration->read0xxLut;
+        /* Perform a dummy read to activate 0-X-X mode */
+        status = Qspi_Ip_RunReadCommand(instance, state->activeReadLut, 0U, &dummyData, NULL_PTR, 1U);
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Exit0XX
+ * Description   : Exits 0-X-X mode (no command for read instructions)
+ * @implements     Qspi_Ip_Exit0XX_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Exit0XX(uint32 instance)
+{
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+    uint8 dummyData;
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    if (state->configuration->read0xxLut != QSPI_IP_LUT_INVALID)
+    {
+        state->activeReadLut = state->configuration->readLut;
+        /* Perform a dummy read to disable 0-X-X mode */
+        status = Qspi_Ip_RunReadCommand(instance, state->activeReadLut, 0U, &dummyData, NULL_PTR, 1U);
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetProtection
+ * Description   : Sets the protection bits of the device
+ * @implements     Qspi_Ip_SetProtection_Activity */
+Qspi_Ip_StatusType Qspi_Ip_SetProtection(uint32 instance,
+                                         uint8 value
+                                        )
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+
+    return Qspi_Ip_UpdateStatusReg(instance, statusConfig->blockProtectionOffset, statusConfig->blockProtectionWidth, value);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_GetProtection
+ * Description   : Returns the current protection bits of the device
+ * @implements     Qspi_Ip_GetProtection_Activity */
+Qspi_Ip_StatusType Qspi_Ip_GetProtection(uint32 instance,
+                                         uint8 *value
+                                        )
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    const Qspi_Ip_StatusConfigType *statusConfig = &(state->configuration->statusConfig);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(value != NULL_PTR);
+
+    return Qspi_Ip_CheckStatusReg(instance, statusConfig->blockProtectionOffset, statusConfig->blockProtectionWidth, value);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_AhbReadEnable
+ * Description   : Enables AHB reads for the current flash device
+ * @implements     Qspi_Ip_AhbReadEnable_Activity */
+Qspi_Ip_StatusType Qspi_Ip_AhbReadEnable(uint32 instance)
+{
+    const Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_ERROR;
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    if (state->activeReadLut != QSPI_IP_LUT_INVALID)
+    {
+        /* Copy sequence in LUT registers */
+        (void)Qspi_Ip_InitLutSeq(instance, state->activeReadLut, QSPI_IP_AHB_LUT);
+        /* Set sequence number */
+        Qspi_Ip_SetAhbSeqId(instance, QSPI_IP_AHB_LUT);
+        status = STATUS_QSPI_IP_SUCCESS;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Init
+ * Description   : Initialize the serial flash memory driver
+ *
+ * @implements     Qspi_Ip_Init_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Init(uint32 instance,
+                                const Qspi_Ip_MemoryConfigType * pConfig,
+                                const Qspi_Ip_MemoryConnectionType * pConnect
+                               )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(pConfig != NULL_PTR);
+    DEV_ASSERT_QSPI(pConnect != NULL_PTR);
+
+    /* Copy configuration information to state structure */
+    DEV_ASSERT_QSPI(NULL_PTR == state->configuration);
+    state->configuration = pConfig;
+    state->connection = pConnect;
+    state->activeReadLut = pConfig->readLut;    /* 0-X-X mode disabled by default */
+    state->lastCommand = QSPI_IP_LAST_COMMAND_NONE;
+    state->baseAddress = Qspi_Ip_GetBaseAdress(pConnect->qspiInstance, pConnect->connectionType);
+
+    /* Initialize corresponding controller if required */
+    if (pConfig->ctrlAutoCfgPtr != NULL_PTR)
+    {
+        status = Qspi_Ip_ControllerInit(pConnect->qspiInstance, pConfig->ctrlAutoCfgPtr);
+    }
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+       /* Perform initial reset */
+        status = Qspi_Ip_InitReset(instance, pConfig->initResetSettings.resetCmdLut, pConfig->initResetSettings.resetCmdCount, state);
+    }
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Execute initial setup of external device */
+        status = Qspi_Ip_InitDevice(instance, state);
+    }
+
+    /* If enabled, call the init callout, for additional QSPI IP or external memory settings. */
+    if ((STATUS_QSPI_IP_SUCCESS == status) && (NULL_PTR != pConfig->initCallout))
+    {
+        status = pConfig->initCallout(instance);
+    }
+
+    /* Perform protection configuration */
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        status = Qspi_Ip_InitProtection(instance, state);
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Deinit
+ * Description   : De-initialize the serial flash memory driver
+ * @implements     Qspi_Ip_Deinit_Activity */
+Qspi_Ip_StatusType Qspi_Ip_Deinit(uint32 instance)
+{
+    Qspi_Ip_StateType * state = &(Qspi_Ip_MemoryStateStructure[instance]);
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(state->configuration != NULL_PTR);
+    state->configuration = NULL_PTR;
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Qspi_Ip_Controller.c

@@ -0,0 +1,1122 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Qspi_Ip_Controller.c
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_Controller.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+#include "Qspi_Ip_Cfg.h"
+#include "Qspi_Ip_Controller.h"
+#include "Qspi_Ip_HwAccess.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_CONTROLLER_VENDOR_ID_C                       43
+#define QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_C        4
+#define QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_C        4
+#define QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_C     0
+#define QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_C                1
+#define QSPI_IP_CONTROLLER_SW_MINOR_VERSION_C                0
+#define QSPI_IP_CONTROLLER_SW_PATCH_VERSION_C                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Cfg header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_C != QSPI_IP_VENDOR_ID_CFG)
+    #error "Qspi_Ip_Controller.c and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_Cfg.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Controller header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_C != QSPI_IP_CONTROLLER_VENDOR_ID_H)
+    #error "Qspi_Ip_Controller.c and Qspi_Ip_Controller.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_Controller.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_C != QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_Controller.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_HwAccess header file are of the same vendor */
+#if (QSPI_IP_CONTROLLER_VENDOR_ID_C != QSPI_IP_HW_ACCESS_VENDOR_ID_H)
+    #error "Qspi_Ip_Controller.c and Qspi_Ip_HwAccess.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_HwAccess header file are of the same Autosar version */
+#if ((QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_HwAccess.h are different"
+#endif
+/* Check if current file and Qspi_Ip_HwAccess header file are of the same Software version */
+#if ((QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_C != QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_MINOR_VERSION_C != QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_CONTROLLER_SW_PATCH_VERSION_C != QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Controller.c and Qspi_Ip_HwAccess.h are different"
+#endif
+
+
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148)
+    /* Bit-fields of chip-specific MCR[SCLKCFG] field */
+    #define QSPI_MCR_SCLKCFG_INPUT_EN             0x80U    /* Enable input buffer of QSPI pads */
+    #define QSPI_MCR_SCLKCFG_CLK_MOD              0x40U    /* Quadspi Clocking mode selection  */
+    #define QSPI_MCR_SCLKCFG_EXT_DQS              0x20U    /* Use external DQS (HyperRAM mode) */
+    #define QSPI_MCR_SCLKCFG_CLK_SRC              0x10U    /* QuadSPI source clock selection   */
+    #define QSPI_MCR_SCLKCFG_DQS_INV_B            0x08U    /* B-side DQS invert                */
+    #define QSPI_MCR_SCLKCFG_DQS_SEL_B            0x04U    /* B-side DQS select                */
+    #define QSPI_MCR_SCLKCFG_DQS_INV_A            0x02U    /* A-side DQS invert                */
+    #define QSPI_MCR_SCLKCFG_DQS_SEL_A            0x01U    /* A-side DQS select                */
+
+    /* Bit-fields of chip-specific SOCCR[SOCCFG] field */
+    /* Programmable Divider Selection */
+    #define QuadSPI_SOCCR_PD_MASK                 0xE0000000u
+    #define QuadSPI_SOCCR_PD_SHIFT                29u
+    #define QuadSPI_SOCCR_PD(x)                   (((uint32)(((uint32)(x))<<QuadSPI_SOCCR_PD_SHIFT))&QuadSPI_SOCCR_PD_MASK)
+    /* Programmable Divider Disable */
+    #define QuadSPI_SOCCR_PDD_MASK                0x10000000u
+
+    #define QuadSPI_SOCCR_DSQ_DEL_B               8u
+    #define QuadSPI_SOCCR_DSQ_DEL_A               0u
+#endif /* (FEATURE_QSPI_CHIP_OPTIONS_S32K148) */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @cond DRIVER_INTERNAL_USE_ONLY */
+
+/* Mask of QuadSPI IP-related error flags */
+#define QSPI_ERR_FLAGS_MASK    (QuadSPI_FR_TBUF_MASK | \
+                                QuadSPI_FR_ILLINE_MASK | \
+                                QuadSPI_FR_RBOF_MASK | \
+                                QuadSPI_FR_IPAEF_MASK | \
+                                QuadSPI_FR_IPIEF_MASK)
+
+
+#define FLS_START_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* Table of base addresses for QuadSPI instances. */
+QuadSPI_Type * const Qspi_Ip_BaseAddress[QuadSPI_INSTANCE_COUNT] = IP_QuadSPI_BASE_PTRS;
+/* Table of AHB addresses for QuadSPI instances. */
+const uint32 Qspi_Ip_AhbAddress[QuadSPI_INSTANCE_COUNT] = QuadSPI_AHB_PTRS;
+
+#define FLS_STOP_SEC_CONST_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+static Qspi_Ip_StatusType Qspi_Ip_WaitTransactionComplete(const QuadSPI_Type *baseAddr);
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProcessDataRead
+ * Description   : Processes read data
+ * @implements     Qspi_Ip_ProcessDataRead_Activity */
+static inline Qspi_Ip_StatusType Qspi_Ip_ProcessDataRead(uint8 * dataRead, uint32 size, const QuadSPI_Type *baseAddr)
+{
+    uint8 * data = dataRead;
+    uint32 cnt = 0U;
+    uint32 recvData;
+    uint32 sizeRemaining;
+    uint32 wordSize;
+    uint8 byteCnt;
+
+    sizeRemaining = size;
+    /* Check user buffer alignment */
+    if (((uint32)dataRead & 0x3U) == 0U)
+    {
+        /* Process 4 bytes at a time to speed up read */
+        for (cnt = 0U; cnt < (sizeRemaining >> 2U); cnt++)
+        {
+            *((uint32 *)((uint32)data)) = baseAddr->RBDR[cnt];  /* Casting through uint32 to avoid Misra 11.3 */
+            data = &(data[4U]);
+        }
+        sizeRemaining -= cnt * 4U;
+    }
+    /* Process remaining bytes one by one */
+    while (sizeRemaining > 0U)
+    {
+        /* Get next received word */
+        recvData = baseAddr->RBDR[cnt];
+        /* get wordSize for the loop */
+        wordSize = (sizeRemaining > 4U)?4U:sizeRemaining;
+        for (byteCnt = 0U; byteCnt < wordSize; byteCnt++)
+        {
+#if (defined(CORE_BIG_ENDIAN))
+            *data = (uint8)(recvData >> 24U);
+            recvData <<= 8U;
+#else
+            *data = (uint8)(recvData & 0xFFU);
+            recvData >>= 8U;
+#endif
+            data++;
+            sizeRemaining--;
+        }
+        cnt++;
+    }
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProcessDataVerify
+ * Description   : Processes program verify data
+ * @implements     Qspi_Ip_ProcessDataVerify_Activity */
+static inline Qspi_Ip_StatusType Qspi_Ip_ProcessDataVerify(const uint8 * dataCmp, uint32 size, const QuadSPI_Type *baseAddr)
+{
+    const uint8 * roData = dataCmp;
+    uint32 cnt = 0U;
+    uint32 recvData;
+    uint8 recvByte;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 byteCnt;
+    uint32 wordSize;
+    uint32 sizeRemaining;
+
+    sizeRemaining = size;
+    /* Check user buffer alignment */
+    if (((uint32)dataCmp & 0x3U) == 0U)
+    {
+        for (cnt = 0U; cnt < (size >> 2U); cnt++)
+        {
+            /* Process 4 bytes at a time to speed up read */
+            if (*((const uint32 *)((uint32)roData)) != baseAddr->RBDR[cnt])
+            {
+                /* return STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY if the data is not match */
+                status = STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY;
+                break;
+            }
+            /* update the roData */
+            roData = &(roData[4U]);
+        }
+        /* update the sizeRemaining */
+        sizeRemaining -= cnt * 4U;
+    }
+    /* Process remaining bytes one by one */
+    while ((STATUS_QSPI_IP_SUCCESS == status) && (sizeRemaining > 0U))
+    {
+        /* Get next received word */
+        recvData = baseAddr->RBDR[cnt];
+        /* get wordSize for the loop */
+        wordSize = (sizeRemaining > 4U)?4U:sizeRemaining;
+        for (byteCnt = 0U; byteCnt < wordSize; byteCnt++)
+        {
+#if (defined(CORE_BIG_ENDIAN))
+            recvByte = (uint8)(recvData >> 24U);
+            recvData <<= 8U;
+#else
+            recvByte = (uint8)(recvData & 0xFFU);
+            recvData >>= 8U;
+#endif
+            /* return STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY if the data is not match */
+            if (*roData != recvByte)
+            {
+                status = STATUS_QSPI_IP_ERROR_PROGRAM_VERIFY;
+                break;
+            }
+            /* update the roData, sizeRemaining */
+            roData++;
+            sizeRemaining--;
+        }
+        cnt++;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ProcessDataBlankCheck
+ * Description   : Processes blank check data
+ * @implements     Qspi_Ip_ProcessDataBlankCheck_Activity */
+static inline Qspi_Ip_StatusType Qspi_Ip_ProcessDataBlankCheck(uint32 size, const QuadSPI_Type *baseAddr)
+{
+    uint32 cnt = 0U;
+    uint32 recvData = 0U;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 dataSize;
+
+    /* Blank check */
+    for (cnt = 0U; cnt < (size >> 2U); cnt++)
+    {
+        if (baseAddr->RBDR[cnt] != 0xFFFFFFFFU)
+        {
+            status = STATUS_QSPI_IP_ERROR;
+            break;
+        }
+    }
+    dataSize = size & 3U;
+    if ((STATUS_QSPI_IP_SUCCESS == status) && (dataSize != 0U))
+    {
+        /* Process last few bytes */
+        recvData = baseAddr->RBDR[size >> 2U];
+#if (defined(CORE_BIG_ENDIAN))
+        if ((~recvData & ~(((uint32)1U << (((uint32)4U - dataSize) * 8U)) - 1U)) != 0U)
+#else
+        if ((~recvData & (((uint32)1U << (dataSize * 8U)) - 1U)) != 0U)
+#endif
+        {
+            status = STATUS_QSPI_IP_ERROR;
+        }
+    }
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_FillTxBuf
+ * Description   : Fill Tx buffer with the specified number of 4-byte entries
+* @implements      Qspi_Ip_FillTxBuf_Activity */
+static void Qspi_Ip_FillTxBuf(QuadSPI_Type *baseAddr, const uint8 * roData, uint32 size)
+{
+    uint32 sizeLeft = size;
+    uint32 wordSize;
+    uint32 data;
+    uint8 byteCnt;
+    const uint8 * roDataPtr = roData;
+
+    /* Check user buffer alignment */
+    if (((uint32)roData & 0x3U) == 0U)
+    {
+        /* Process 4 bytes at a time to speed things up */
+        while (sizeLeft >= 4U)
+        {
+            data = *(const uint32 *)((uint32)roDataPtr);  /* Casting through uint32 to avoid Misra 11.3 */
+            sizeLeft -= 4U;
+            roDataPtr = &(roDataPtr[4U]);
+            Qspi_Ip_WriteTxData(baseAddr, data);
+        }
+    }
+    /* Process remaining bytes one by one */
+    while (sizeLeft > 0U)
+    {
+        /* Processes last few data bytes (less than 4) */
+        data = 0U;
+        wordSize = (sizeLeft > 4U)?4U:sizeLeft;
+        for (byteCnt = 0U; byteCnt < wordSize; byteCnt++)
+        {
+#if (defined(CORE_BIG_ENDIAN))
+            data += ((uint32)(*roDataPtr) << (8U * (3U - byteCnt)));
+#else
+            data += ((uint32)(*roDataPtr) << (8U * byteCnt));
+#endif
+            roDataPtr++;
+        }
+        Qspi_Ip_WriteTxData(baseAddr, data);
+        sizeLeft -= wordSize;
+    }
+
+    return;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ErrorCheck
+ * Description   : Checks if there were errors during IP command execution
+* @implements      Qspi_Ip_ErrorCheck_Activity */
+static inline Qspi_Ip_StatusType Qspi_Ip_ErrorCheck(QuadSPI_Type *baseAddr)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    if ((baseAddr->FR & QSPI_ERR_FLAGS_MASK) != 0U)
+    {
+        /* clear error flags */
+        baseAddr->FR = QSPI_ERR_FLAGS_MASK;
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    else
+    {
+        /* Empty clause added to fulfill MISRA. */
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SwResetDelay
+ * Description   : Insert waiting loops after changing the value of the software reset bits
+ */
+static inline void Qspi_Ip_SwResetDelay(void)
+{
+    volatile uint32 u32CurrentTicks;
+    /* Prepare timeout counter */
+    u32CurrentTicks = QSPI_IP_SOFTWARE_RESET_DELAY;
+    /* Insert delay after changing the value of the software reset bits. */
+    while (u32CurrentTicks > 0U)
+    {
+        u32CurrentTicks--;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SwReset
+ * Description   : Resets the QuadSPI device
+* @implements      Qspi_Ip_SwReset_Activity */
+static void Qspi_Ip_SwReset(QuadSPI_Type *baseAddr)
+{
+    /* Software reset AHB domain and Serial Flash domain at the same time. */
+    Qspi_Ip_SwResetOn(baseAddr);
+    /* Insert delay after changing the value of the reset bits. */
+    Qspi_Ip_SwResetDelay();
+    /* Disable QuadSPI module before de-asserting the reset bits. */
+    Qspi_Ip_Disable(baseAddr);
+    /* De-asset Software reset AHB domain and Serial Flash domain bits. */
+    Qspi_Ip_SwResetOff(baseAddr);
+    /* Re-enable QuadSPI module after reset. */
+    Qspi_Ip_Enable(baseAddr);
+    /* Insert delay after changing the value of the reset bits. */
+    Qspi_Ip_SwResetDelay();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_AhbFlush
+ * Description   : Reset AHB buffers
+ */
+static void Qspi_Ip_AhbFlush(QuadSPI_Type *baseAddr)
+{
+#ifdef QuadSPI_SPTRCLR_ABRT_CLR_MASK
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    /* Use the AHB buffer clear bit to avoid losing the DLL lock */
+    Qspi_Ip_ClearAhbBuf(baseAddr);
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_CMD_COMPLETE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+
+    /* Wait for clearing the AHB buffer pointers */
+    while (!Qspi_Ip_GetClrAhbStatus(baseAddr))
+    {
+        /* An exit point for safety purpose only, because this loop is not expected to happen in practice */
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if ( u32ElapsedTicks >= u32TimeoutTicks )
+        {
+            break;
+        }
+    }
+
+#else
+    /* Otherwise use the software reset */
+    Qspi_Ip_SwReset(baseAddr);
+#endif
+}
+
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureChipOptions
+ * Description   : Configures chip-specific settings, e.g. SOCCR
+ ***********************************************************************/
+#if defined(FEATURE_QSPI_CHIP_OPTIONS_S32K148)
+static void Qspi_Ip_ConfigureChipOptions(QuadSPI_Type *baseAddr, const Qspi_Ip_ControllerConfigType * userConfigPtr)
+{
+    /* always enable pads input buffers */
+    uint8 clkOption = QSPI_MCR_SCLKCFG_INPUT_EN;
+    uint32 chipOption = 0U;
+
+    /* Configure MCR_SCLKCFG options */
+    /* Configure module clock selection */
+    if (QSPI_IP_CLK_SRC_BUS_CLK == userConfigPtr->clockSrc)
+    {
+        clkOption |= QSPI_MCR_SCLKCFG_CLK_MOD;
+    }
+    /* Configure internal reference clock selection */
+    if (QSPI_IP_CLK_REF_FIRC_DIV1 == userConfigPtr->clockRef)
+    {
+        clkOption |= QSPI_MCR_SCLKCFG_CLK_SRC;
+    }
+    /* Configure external DQS mode for Flash B (HyperRAM Enabled) */
+    if (QSPI_IP_READ_MODE_EXTERNAL_DQS == userConfigPtr->readModeB)
+    {
+        clkOption |= QSPI_MCR_SCLKCFG_EXT_DQS;
+    }
+    /* Select reference clock for DQS for each side */
+    if (QSPI_IP_READ_MODE_LOOPBACK == userConfigPtr->readModeA)
+    {
+        clkOption |= (uint8)(QSPI_MCR_SCLKCFG_DQS_SEL_A);
+    }
+    if (QSPI_IP_READ_MODE_LOOPBACK == userConfigPtr->readModeB)
+    {
+        clkOption |= (uint8)(QSPI_MCR_SCLKCFG_DQS_SEL_B);
+    }
+    /* Configure inverted DQS: 0-Inverted / 1-Not Inverted */
+    if ((boolean)FALSE == userConfigPtr->dqsInvertA)
+    {
+        clkOption |= (uint8)(QSPI_MCR_SCLKCFG_DQS_INV_A);
+    }
+    if ((boolean)FALSE == userConfigPtr->dqsInvertB)
+    {
+        clkOption |= (uint8)(QSPI_MCR_SCLKCFG_DQS_INV_B);
+    }
+    Qspi_Ip_SetClockOptions(baseAddr, clkOption);
+
+    /* Configure SOCCR options */
+    /* Disable divider before configuring it */
+    Qspi_Ip_SetChipOptions(baseAddr, QuadSPI_SOCCR_PDD_MASK);
+    chipOption |= QuadSPI_SOCCR_PD((uint32)userConfigPtr->clockRefDiv - 1U);
+    chipOption |= ((uint32)userConfigPtr->dqsDelayA << QuadSPI_SOCCR_DSQ_DEL_A) +
+                  ((uint32)userConfigPtr->dqsDelayB << QuadSPI_SOCCR_DSQ_DEL_B);
+    /* Write configuration, keep divider disabled */
+    Qspi_Ip_SetChipOptions(baseAddr, chipOption | QuadSPI_SOCCR_PDD_MASK);
+    /* Enable divider */
+    Qspi_Ip_SetChipOptions(baseAddr, chipOption);
+}
+
+#elif defined(FEATURE_QSPI_CHIP_OPTIONS_S32K3)
+static void Qspi_Ip_ConfigureChipOptions(QuadSPI_Type *baseAddr, const Qspi_Ip_ControllerConfigType * userConfigPtr)
+{
+    (void)userConfigPtr;
+    Qspi_Ip_SetChipOptions(baseAddr, 0x0000000E);  /* set ibe=1, obe=1, dse=1 and sre=0 */
+}
+
+#else
+static void Qspi_Ip_ConfigureChipOptions(const QuadSPI_Type *baseAddr, const Qspi_Ip_ControllerConfigType * userConfigPtr)
+{
+    (void)userConfigPtr;
+    (void)baseAddr;
+}
+#endif
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureReadOptions
+ * Description   : Configures data read settings
+* @implements      Qspi_Ip_ConfigureReadOptions_Activity */
+static void Qspi_Ip_ConfigureReadOptions(QuadSPI_Type *baseAddr, const Qspi_Ip_ControllerConfigType * userConfigPtr)
+{
+    /* Always enable DQS */
+    QSPI_DQS_Enable(baseAddr);
+    QSPI_DQS_LatEnable(baseAddr, userConfigPtr->dqsLatency);
+    if (QSPI_IP_DATA_RATE_SDR == userConfigPtr->dataRate)
+    {
+        QSPI_DDR_Disable(baseAddr);
+        /* Ignore output data align setting in SDR mode */
+        Qspi_Ip_SetDataInHoldTime(baseAddr, QSPI_IP_FLASH_DATA_ALIGN_REFCLK);
+    }
+    else  /* QSPI_IP_DATA_RATE_DDR */
+    {
+        QSPI_DDR_Enable(baseAddr);
+        Qspi_Ip_SetDataInHoldTime(baseAddr, userConfigPtr->dataAlign);
+    }
+
+
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_AhbSetup
+ * Description   : Sets up AHB accesses to the serial flash
+* @implements      Qspi_Ip_AhbSetup_Activity */
+static Qspi_Ip_StatusType Qspi_Ip_AhbSetup(uint32 instance, const Qspi_Ip_ControllerAhbConfigType *config)
+{
+    QuadSPI_Type *baseAddr;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(0U == (config->sizes[0U] & 7U));
+    DEV_ASSERT_QSPI(((uint32)config->sizes[0U] +
+               (uint32)config->sizes[1U] +
+               (uint32)config->sizes[2U] +
+               (uint32)config->sizes[3U]) <= FEATURE_QSPI_AHB_BUF_SIZE);
+    /* Get base address of instance */
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* configure AHB transfer sizes to match the buffer sizes */
+    /* Set AHB buffer 0 */
+    Qspi_Ip_SetAhbBuf0(baseAddr, config->sizes[0U], config->masters[0U]);
+    /* Set AHB buffer 1 */
+    Qspi_Ip_SetAhbBuf1(baseAddr, config->sizes[1U], config->masters[1U]);
+    /* Set AHB buffer 2 */
+    Qspi_Ip_SetAhbBuf2(baseAddr, config->sizes[2U], config->masters[2U]);
+    /* Set AHB buffer 3 */
+    Qspi_Ip_SetAhbBuf3(baseAddr, config->sizes[3U], config->masters[3U], config->allMasters);
+    /* Set AHB buffer index 0 */
+    Qspi_Ip_SetAhbBuf0Ind(baseAddr, (uint32)config->sizes[0U]);
+    /* Set AHB buffer index 1 */
+    Qspi_Ip_SetAhbBuf1Ind(baseAddr, (uint32)config->sizes[0U] + (uint32)config->sizes[1U]);
+    /* Set AHB buffer index 2 */
+    Qspi_Ip_SetAhbBuf2Ind(baseAddr, (uint32)config->sizes[0U] + (uint32)config->sizes[1U] + (uint32)config->sizes[2U]);
+
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*! @endcond */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetLut
+ * Description   : Configures a pair of LUT commands in the specified LUT register
+ *
+ *END**************************************************************************/
+void Qspi_Ip_SetLut(uint32 instance,
+                    uint8 lut,
+                    Qspi_Ip_InstrOpType operation0,
+                    Qspi_Ip_InstrOpType operation1
+                   )
+{
+    QuadSPI_Type *baseAddr;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut < QuadSPI_LUT_COUNT);
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+    baseAddr->LUT[lut] = (uint32)operation0 + ((uint32)operation1 << 16U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetAhbSeqId
+ * Description   : Sets sequence ID for AHB operations
+ *
+ *END**************************************************************************/
+void Qspi_Ip_SetAhbSeqId(uint32 instance,
+                         uint8 seqID
+                        )
+{
+    QuadSPI_Type *baseAddr;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+    baseAddr->BFGENCR =  QuadSPI_BFGENCR_SEQID(seqID);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SetMemMap
+ * Description   : Configure the memory mapping
+ *
+ *END**************************************************************************/
+static inline void Qspi_Ip_SetMemMap(uint32 instance,
+                                     QuadSPI_Type *baseAddr,
+                                     const Qspi_Ip_ControllerConfigType * userConfigPtr
+                                    )
+{
+    /* Configure external flash memory map Size A */
+    Qspi_Ip_SetMemMapSizeA(instance, baseAddr, userConfigPtr->memSizeA1, userConfigPtr->memSizeA2);
+    /* Configure external flash memory map Size B */
+    Qspi_Ip_SetMemMapSizeB(baseAddr, userConfigPtr->memSizeB1, userConfigPtr->memSizeB2);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureBuffers
+ * Description   : Configure the Rx and Rx buffer
+ *
+ *END**************************************************************************/
+static inline void Qspi_Ip_ConfigureBuffers(QuadSPI_Type *baseAddr)
+{
+    /* Read Rx buffer through RBDR registers */
+    Qspi_Ip_SetRxBufReadout(baseAddr, QSPI_IP_RX_READOUT_IP);
+    /* Set watermarks */
+    Qspi_Ip_SetTxWatermark(baseAddr, 1U);
+    Qspi_Ip_SetRxWatermark(baseAddr, 1U);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureController
+ * Description   : Configure the controller register following user configurations
+ *
+ *END**************************************************************************/
+static inline void Qspi_Ip_ConfigureController(uint32 instance,
+                                               const Qspi_Ip_ControllerConfigType * userConfigPtr
+                                              )
+{
+    QuadSPI_Type *baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Configure external flash memory map Size A */
+    Qspi_Ip_SetMemMap(instance, baseAddr, userConfigPtr);
+
+    Qspi_Ip_SetAddrOptions(baseAddr, userConfigPtr->columnAddr, userConfigPtr->wordAddresable);
+    Qspi_Ip_SetRxCfg(baseAddr, userConfigPtr->sampleDelay, userConfigPtr->samplePhase);
+    Qspi_Ip_SetCsHoldTime(baseAddr, userConfigPtr->csHoldTime);
+    Qspi_Ip_SetCsSetupTime(baseAddr, userConfigPtr->csSetupTime);
+    /* Unused side lines are "no matter" so just repeat idle settings on both sides */
+    Qspi_Ip_SetIdleLineValues(baseAddr, userConfigPtr->io2IdleValueA, userConfigPtr->io3IdleValueA,
+                                         userConfigPtr->io2IdleValueB, userConfigPtr->io3IdleValueB);
+    /* Configure buffers */
+    Qspi_Ip_ConfigureBuffers(baseAddr);
+
+
+    /* Configure read options */
+    Qspi_Ip_ConfigureReadOptions(baseAddr, userConfigPtr);
+    /* Configure chip-specific options */
+    Qspi_Ip_ConfigureChipOptions(baseAddr, userConfigPtr);
+    /* Configure AHB settings */
+    (void)Qspi_Ip_AhbSetup(instance, &(userConfigPtr->ahbConfig));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ControllerInit
+ * Description   : Initializes the qspi controller
+ * @implements     Qspi_Ip_ControllerInit_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ControllerInit(uint32 instance,
+                                          const Qspi_Ip_ControllerConfigType * userConfigPtr
+                                         )
+{
+    QuadSPI_Type *baseAddr;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(userConfigPtr != NULL_PTR);
+    /* Initialize driver status structure */
+
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Ensure module is disabled */
+    Qspi_Ip_Disable(baseAddr);
+
+    /* Ensure all registers contain their reset value */
+    Qspi_Ip_ResetAllRegisters(baseAddr);
+
+    /* Configure the controller following the user configurations */
+    Qspi_Ip_ConfigureController(instance, userConfigPtr);
+
+    /* Enable QuadSPI module */
+    Qspi_Ip_Enable(baseAddr);
+
+    /* Reset serial flash and AHB domains */
+    Qspi_Ip_SwReset(baseAddr);
+
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ControllerDeinit
+ * Description   : De-initialize the qspi driver
+ * @implements     Qspi_Ip_ControllerDeinit_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ControllerDeinit(uint32 instance)
+{
+    QuadSPI_Type *baseAddr;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Disable QuadSPI module */
+    Qspi_Ip_Disable(baseAddr);
+
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_GetBaseAdress
+ * Description   : Returns the physical base address of a flash device on the AHB bus.
+ *                 The controller must be initialized prior to calling this function.
+ * @implements     Qspi_Ip_GetBaseAdress_Activity */
+uint32 Qspi_Ip_GetBaseAdress(uint32 instance,
+                             Qspi_Ip_ConnectionType connectionType
+                            )
+{
+    const QuadSPI_Type *baseAddr;
+    uint32 address = 0U;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    /* get the base address base on the instance */
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    switch (connectionType)
+    {
+        case QSPI_IP_SIDE_A1:
+            /* get base address of side A1 */
+            address = Qspi_Ip_AhbAddress[instance];
+            break;
+        case QSPI_IP_SIDE_A2:
+            /* get base address of side A2 */
+            address = baseAddr->SFA1AD;
+            break;
+        case QSPI_IP_SIDE_B1:
+            /* get base address of side B1 */
+            address = baseAddr->SFA2AD;
+            break;
+        case QSPI_IP_SIDE_B2:
+            /* get base address of side B2 */
+            address = baseAddr->SFB1AD;
+            break;
+        default:
+            ; /* Not possible */
+            break;
+    }
+
+    return address;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_IpCommand
+ * Description   : Launches a simple IP command
+ * @implements     Qspi_Ip_IpCommand_Activity */
+Qspi_Ip_StatusType Qspi_Ip_IpCommand(uint32 instance,
+                                     uint8 lut,
+                                     uint32 addr
+                                    )
+{
+    QuadSPI_Type *baseAddr;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut < QuadSPI_LUT_COUNT);
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Reset AHB buffers to force re-read from memory after erase operation */
+    Qspi_Ip_AhbFlush(baseAddr);
+
+    /* Set address */
+    Qspi_Ip_SetIpAddr(baseAddr, addr);
+    /* Trigger IP command with specified sequence and dummy size */
+    Qspi_Ip_IpTrigger(baseAddr, lut, 1U);
+
+    /* Add Fault Injection point for FR_ILLINE flag */
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPCOMMAND);
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_CMD_COMPLETE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    do
+    {
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        status = Qspi_Ip_ControllerGetStatus(instance);
+    }
+    while ((u32ElapsedTicks < u32TimeoutTicks) && (STATUS_QSPI_IP_BUSY == status));
+    if (STATUS_QSPI_IP_BUSY == status)
+    {
+        status = STATUS_QSPI_IP_TIMEOUT;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_WaitTransactionComplete
+ * Description   : Wait until Qspi controller is not busy or timeout
+ */
+static Qspi_Ip_StatusType Qspi_Ip_WaitTransactionComplete(const QuadSPI_Type *baseAddr)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32  u32ElapsedTicks = 0UL;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_CMD_COMPLETE_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    /* Wait for command to be completed */
+    while (Qspi_Ip_GetBusyStatus(baseAddr))
+    {
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+        if (u32ElapsedTicks >= u32TimeoutTicks)
+        {
+            status = STATUS_QSPI_IP_TIMEOUT;
+            break;
+        }
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_IpRead
+ * Description   : Launches an IP read command
+ * @implements     Qspi_Ip_IpRead_Activity */
+Qspi_Ip_StatusType Qspi_Ip_IpRead(uint32 instance,
+                                  uint8 lut,
+                                  uint32 addr,
+                                  uint8 * dataRead,
+                                  const uint8 * dataCmp,
+                                  uint32 size
+                                 )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    QuadSPI_Type *baseAddr;
+
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(lut < QuadSPI_LUT_COUNT);
+    DEV_ASSERT_QSPI(size <= FEATURE_QSPI_RX_BUF_SIZE);
+
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Make sure there is no garbage in Rx fifo */
+    Qspi_Ip_ClearRxBuf(baseAddr);
+    /* Set read address */
+    Qspi_Ip_SetIpAddr(baseAddr, addr);
+    /* Trigger IP command with specified sequence and size */
+    /* If size is odd, round up to even size; this is needed in octal DDR mode */
+    Qspi_Ip_IpTrigger(baseAddr, lut, (uint16)((size + 1U) & (~1U)));
+
+    /* Add Fault Injection point for FR_ILLINE flag */
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPREAD);
+
+    /* Wait until the command is sent */
+    status = Qspi_Ip_WaitTransactionComplete(baseAddr);
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Check for errors reported by the QuadSPI */
+        status = Qspi_Ip_ErrorCheck(baseAddr);
+    }
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Process received data */
+        if (dataRead != NULL_PTR)
+        {
+            /* Normal read */
+            status = Qspi_Ip_ProcessDataRead(dataRead, size, baseAddr);
+        }
+        else if (dataCmp != NULL_PTR)
+        {
+            /* Verify */
+            status = Qspi_Ip_ProcessDataVerify(dataCmp, size, baseAddr);
+        }
+        else
+        {
+            /* Blank check */
+            status = Qspi_Ip_ProcessDataBlankCheck(size, baseAddr);
+        }
+    }   /* (status = STATUS_QSPI_IP_SUCCESS) */
+
+    /* Reset Rx fifo */
+    Qspi_Ip_ClearRxBuf(baseAddr);
+
+    return status;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_InvalidateTxBuf
+ * Description   : Invalidates the TX buffer content and wait until it is completed or timed out
+ * @implements     Qspi_Ip_InvalidateTxBuf_Activity */
+static inline void Qspi_Ip_InvalidateTxBuf(uint32 instance)
+{
+    QuadSPI_Type *baseAddr;
+    volatile uint32  u32CurrentTicks = FEATURE_QSPI_TX_RESET_DELAY;
+
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    Qspi_Ip_ClearTxBuf(baseAddr);
+
+    /* Prepare timeout counter */
+    u32CurrentTicks = FEATURE_QSPI_TX_RESET_DELAY;
+    /* Insert delay to ensure TX FIFO reset is complete */
+    while (u32CurrentTicks > 0U)
+    {
+        u32CurrentTicks--;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_PadTxBuf
+ * Description   : Pad Tx buffer up to a minimum number of entries required
+ *                 by the device for transmission to start
+ *
+ *END**************************************************************************/
+static void Qspi_Ip_PadTxBuf(QuadSPI_Type *baseAddr)
+{
+#if (FEATURE_QSPI_TX_MIN_BUF_FILL > 1)
+    uint32 bufFill = Qspi_Ip_GetTxBufFill(baseAddr);
+    while ((bufFill < FEATURE_QSPI_TX_MIN_BUF_FILL) || ((bufFill & 3U) != 0U))
+    {
+        Qspi_Ip_WriteTxData(baseAddr, 0xFFFFFFFFU);
+        bufFill++;
+    }
+#else
+    (void)baseAddr;
+#endif
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_IpWrite
+ * Description   : Launches an IP write command
+ * @implements     Qspi_Ip_IpWrite_Activity */
+Qspi_Ip_StatusType Qspi_Ip_IpWrite(uint32 instance,
+                                   uint8 lut,
+                                   uint32 addr,
+                                   const uint8 * data,
+                                   uint32 size
+                                  )
+{
+    QuadSPI_Type *baseAddr;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    Qspi_Ip_StatusType errors = STATUS_QSPI_IP_SUCCESS;
+
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+    DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT);
+    DEV_ASSERT_QSPI(size <= (uint16)FEATURE_QSPI_TX_BUF_SIZE);
+    DEV_ASSERT_QSPI(lut < QuadSPI_LUT_COUNT);
+    DEV_ASSERT_QSPI(data != NULL_PTR);
+
+    /* Reset AHB buffers to force re-read from memory after write operation */
+    Qspi_Ip_AhbFlush(baseAddr);
+
+    /* Set write address */
+    Qspi_Ip_SetIpAddr(baseAddr, addr);
+
+    /* Ensure there is no garbage in Tx FIFO */
+    Qspi_Ip_InvalidateTxBuf(instance);
+    /* Fill Tx buffer */
+    Qspi_Ip_FillTxBuf(baseAddr, data, size);
+    /* Pad Tx buffer up to the minimum number of entries required by the device */
+    Qspi_Ip_PadTxBuf(baseAddr);
+
+    /* Trigger IP command with specified sequence and size */
+    Qspi_Ip_IpTrigger(baseAddr, lut, (uint16)size);
+
+    /* Add Fault Injection point for FR_TBUF flag */
+    MCAL_FAULT_INJECTION_POINT(FLS_FIP_FR_ERROR_IPWRITE);
+
+    /* Wait until the command is sent */
+    status = Qspi_Ip_WaitTransactionComplete(baseAddr);
+
+    /* Check for errors reported by the QuadSPI */
+    errors = Qspi_Ip_ErrorCheck(baseAddr);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        status = errors;
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ControllerGetStatus
+ * Description   : Checks the status of the currently running IP command
+ * @implements     Qspi_Ip_ControllerGetStatus_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ControllerGetStatus(uint32 instance)
+{
+    QuadSPI_Type *baseAddr;
+    Qspi_Ip_StatusType status;
+
+    DEV_ASSERT_QSPI((instance < QuadSPI_INSTANCE_COUNT));
+    baseAddr = Qspi_Ip_BaseAddress[instance];
+
+    /* Check device for busy status */
+    if (Qspi_Ip_GetBusyStatus(baseAddr))
+    {
+        status = STATUS_QSPI_IP_BUSY;
+    }
+    else
+    {
+        /* Check for errors reported by the QuadSPI */
+        status = Qspi_Ip_ErrorCheck(baseAddr);
+    }
+    return status;
+}
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Qspi_Ip_Sfdp.c

@@ -0,0 +1,3327 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Qspi_Ip_Sfdp.c
+*
+*   @addtogroup IPV_QSPI QSPI IPV Driver
+*   @{
+*/
+
+/* implements Qspi_Ip_Sfdp.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include "Qspi_Ip_Cfg.h"
+#include "Qspi_Ip_Controller.h"
+#include "Qspi_Ip_Common.h"
+#include "Qspi_Ip.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_C                    43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_C     4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_C     4
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_C  0
+#define QSPI_IP_SW_MAJOR_VERSION_C             1
+#define QSPI_IP_SW_MINOR_VERSION_C             0
+#define QSPI_IP_SW_PATCH_VERSION_C             0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Cfg header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_VENDOR_ID_CFG)
+    #error "Qspi_Ip_Sfdp.c and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Cfg.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Controller header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_CONTROLLER_VENDOR_ID_H)
+    #error "Qspi_Ip_Sfdp.c and Qspi_Ip_Controller.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_CONTROLLER_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_CONTROLLER_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Controller.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Controller header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_CONTROLLER_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_CONTROLLER_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Controller.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Common header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_COMMON_VENDOR_ID_H)
+    #error "Qspi_Ip_Sfdp.c and Qspi_Ip_Common.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Common.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Common header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip_Common.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_C != QSPI_IP_VENDOR_ID_H)
+    #error "Qspi_Ip_Sfdp.c and Qspi_Ip.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip.h are different"
+#endif
+/* Check if current file and Qspi_Ip header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_C != QSPI_IP_SW_MAJOR_VERSION_H) || \
+     (QSPI_IP_SW_MINOR_VERSION_C != QSPI_IP_SW_MINOR_VERSION_H) || \
+     (QSPI_IP_SW_PATCH_VERSION_C != QSPI_IP_SW_PATCH_VERSION_H) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Sfdp.c and Qspi_Ip.h are different"
+#endif
+
+/*******************************************************************************
+ * Definitions.
+ ******************************************************************************/
+
+#define QSPI_IP_CMD_SFDP_READ            0x5AU    /* Instruction for Read SFDP command */
+#define QSPI_IP_CMD_BASIC_READ           0x03U    /* Basic read instruction  */
+#define QSPI_IP_CMD_BASIC_READ_4B        0x13U    /* Basic read instruction - 4 bytes address */
+#define QSPI_IP_CMD_BASIC_WRITE          0x02U    /* Basic write (page program) instruction  */
+#define QSPI_IP_CMD_BASIC_READ_SR        0x05U    /* Basic instruction for read status reg. command */
+#define QSPI_IP_CMD_BASIC_WRITE_SR       0x01U    /* Basic instruction for write status reg. command */
+#define QSPI_IP_CMD_BASIC_WRITE_ENABLE   0x06U    /* Basic instruction for write enable command */
+#define QSPI_IP_CMD_BASIC_CHIP_ERASE     0x60U    /* Basic instruction for chip erase command */
+#define QSPI_IP_CMD_XSPI_WRITE           0x12U    /* XSPI profile 1.0 Instruction for Program command */
+#define QSPI_IP_CMD_XSPI_CHIP_ERASE      0xC7U    /* XSPI profile 1.0 Instruction for Chip Erase command */
+#define QSPI_IP_CMD_XSPI_READ_SR         0x05U    /* XSPI profile 1.0 Instruction for read status reg. command */
+#define QSPI_IP_CMD_XSPI_WRITE_SR        0x01U    /* XSPI profile 1.0 Instruction for write status reg. command */
+#define QSPI_IP_CMD_XSPI_WRITE_ENABLE    0x06U    /* XSPI profile 1.0 Instruction for write enable command */
+#define QSPI_IP_CMD_XSPI_RESET           0xF0U    /* XSPI profile 1.0 Instruction for soft reset command */
+#define QSPI_IP_CMD_XSPI_RESET_ENABLE    0x66U    /* XSPI profile 1.0 Instruction for reset enable command */
+#define QSPI_IP_CMD_XSPI_RESET_DEF       0x99U    /* XSPI profile 1.0 Instruction for soft reset and enter default protocol mode command */
+
+#define QSPI_IP_TABLE_SIZE_BASIC     20U     /* Max basic flash parameter table length                      */
+#define QSPI_IP_TABLE_SIZE_4BADD     2U      /* Max 4-byte address instruction table length                 */
+#define QSPI_IP_TABLE_SIZE_XSPI1     5U      /* Max extended serial peripheral interface table length       */
+#define QSPI_IP_TABLE_SIZE_SRMAP     28U     /* Max status, control and configuration register map length   */
+#define QSPI_IP_TABLE_SIZE_2DOPI     8U      /* Max command sequence to change to octal ddr length          */
+
+#define QSPI_IP_SFDP_MAJOR_REVISION              1U
+#define QSPI_IP_SFDP_MINOR_REVISION_REV_0        0U
+#define QSPI_IP_SFDP_MINOR_REVISION_REV_A        5U
+
+    /**** Constants for retrieving SFDP parameters - Basic flash parameters table *****/
+
+    /* Flash Size */
+#define QSPI_IP_SFDP_BASIC_MEM_SIZE_DWORD         2U
+#define QSPI_IP_SFDP_BASIC_MEM_SIZE_SHIFT         0U
+#define QSPI_IP_SFDP_BASIC_MEM_SIZE_WIDTH         32U
+    /* Page Size */
+#define QSPI_IP_SFDP_BASIC_PAGE_SIZE_DWORD        11U
+#define QSPI_IP_SFDP_BASIC_PAGE_SIZE_SHIFT        4U
+#define QSPI_IP_SFDP_BASIC_PAGE_SIZE_WIDTH        4U
+    /* Octal DTR (8D-8D-8D) Command and Command Extension */
+#define QSPI_IP_SFDP_BASIC_CMD_EXT_DWORD          18U
+#define QSPI_IP_SFDP_BASIC_CMD_EXT_SHIFT          29U
+#define QSPI_IP_SFDP_BASIC_CMD_EXT_WIDTH          2U
+    /* Erase type 1 - instruction and size */
+#define QSPI_IP_SFDP_BASIC_ERASE1_INST_DWORD          8U
+#define QSPI_IP_SFDP_BASIC_ERASE1_INST_SHIFT          8U
+#define QSPI_IP_SFDP_BASIC_ERASE1_INST_WIDTH          8U
+#define QSPI_IP_SFDP_BASIC_ERASE1_SIZE_DWORD          8U
+#define QSPI_IP_SFDP_BASIC_ERASE1_SIZE_SHIFT          0U
+#define QSPI_IP_SFDP_BASIC_ERASE1_SIZE_WIDTH          8U
+    /* Erase type 2 - instruction and size */
+#define QSPI_IP_SFDP_BASIC_ERASE2_INST_DWORD          8U
+#define QSPI_IP_SFDP_BASIC_ERASE2_INST_SHIFT          24U
+#define QSPI_IP_SFDP_BASIC_ERASE2_INST_WIDTH          8U
+#define QSPI_IP_SFDP_BASIC_ERASE2_SIZE_DWORD          8U
+#define QSPI_IP_SFDP_BASIC_ERASE2_SIZE_SHIFT          16U
+#define QSPI_IP_SFDP_BASIC_ERASE2_SIZE_WIDTH          8U
+    /* Erase type 3 - instruction and size */
+#define QSPI_IP_SFDP_BASIC_ERASE3_INST_DWORD          9U
+#define QSPI_IP_SFDP_BASIC_ERASE3_INST_SHIFT          8U
+#define QSPI_IP_SFDP_BASIC_ERASE3_INST_WIDTH          8U
+#define QSPI_IP_SFDP_BASIC_ERASE3_SIZE_DWORD          9U
+#define QSPI_IP_SFDP_BASIC_ERASE3_SIZE_SHIFT          0U
+#define QSPI_IP_SFDP_BASIC_ERASE3_SIZE_WIDTH          8U
+    /* Erase type 4 - instruction and size */
+#define QSPI_IP_SFDP_BASIC_ERASE4_INST_DWORD          9U
+#define QSPI_IP_SFDP_BASIC_ERASE4_INST_SHIFT          24U
+#define QSPI_IP_SFDP_BASIC_ERASE4_INST_WIDTH          8U
+#define QSPI_IP_SFDP_BASIC_ERASE4_SIZE_DWORD          9U
+#define QSPI_IP_SFDP_BASIC_ERASE4_SIZE_SHIFT          16U
+#define QSPI_IP_SFDP_BASIC_ERASE4_SIZE_WIDTH          8U
+    /* Erase suspend instruction */
+#define QSPI_IP_SFDP_BASIC_ESUS_INSTR_DWORD          13U
+#define QSPI_IP_SFDP_BASIC_ESUS_INSTR_SHIFT          24U
+#define QSPI_IP_SFDP_BASIC_ESUS_INSTR_WIDTH          8U
+    /* Erase resume instruction */
+#define QSPI_IP_SFDP_BASIC_ERES_INSTR_DWORD          13U
+#define QSPI_IP_SFDP_BASIC_ERES_INSTR_SHIFT          16U
+#define QSPI_IP_SFDP_BASIC_ERES_INSTR_WIDTH          8U
+    /* Program suspend instruction */
+#define QSPI_IP_SFDP_BASIC_PSUS_INSTR_DWORD          13U
+#define QSPI_IP_SFDP_BASIC_PSUS_INSTR_SHIFT          8U
+#define QSPI_IP_SFDP_BASIC_PSUS_INSTR_WIDTH          8U
+    /* Program resume instruction */
+#define QSPI_IP_SFDP_BASIC_PRES_INSTR_DWORD          13U
+#define QSPI_IP_SFDP_BASIC_PRES_INSTR_SHIFT          0U
+#define QSPI_IP_SFDP_BASIC_PRES_INSTR_WIDTH          8U
+    /* Quad Enable Requirements */
+#define QSPI_IP_SFDP_BASIC_QE_REQ_DWORD              15U
+#define QSPI_IP_SFDP_BASIC_QE_REQ_SHIFT              20U
+#define QSPI_IP_SFDP_BASIC_QE_REQ_WIDTH              3U
+    /* Soft Reset */
+#define QSPI_IP_SFDP_BASIC_SW_RESET_DWORD            16U
+#define QSPI_IP_SFDP_BASIC_SW_RESET_SHIFT            8U
+#define QSPI_IP_SFDP_BASIC_SW_RESET_WIDTH            6U
+    /* Write Enable Instruction Select for Writing to Volatile Status Register */
+#define QSPI_IP_SFDP_BASIC_WREN_SR_DWORD             1U
+#define QSPI_IP_SFDP_BASIC_WREN_SR_SHIFT             3U
+#define QSPI_IP_SFDP_BASIC_WREN_SR_WIDTH             2U
+    /* 4-4-4 mode enable sequences */
+#define QSPI_IP_SFDP_BASIC_444_SWITCH_DWORD          15U
+#define QSPI_IP_SFDP_BASIC_444_SWITCH_SHIFT          4U
+#define QSPI_IP_SFDP_BASIC_444_SWITCH_WIDTH          5U
+
+    /* Fast read instructions/mode bits/dummy bits */
+#define  QSPI_IP_SFDP_BASIC_READ112_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_BASIC_READ122_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_BASIC_READ114_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_BASIC_READ144_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_BASIC_READ444_SUP_DWORD           5U
+#define  QSPI_IP_SFDP_BASIC_READ118_SUP_DWORD           17U
+#define  QSPI_IP_SFDP_BASIC_READ188_SUP_DWORD           17U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_SUP_SHIFT           16U
+#define  QSPI_IP_SFDP_BASIC_READ122_SUP_SHIFT           20U
+#define  QSPI_IP_SFDP_BASIC_READ114_SUP_SHIFT           22U
+#define  QSPI_IP_SFDP_BASIC_READ144_SUP_SHIFT           21U
+#define  QSPI_IP_SFDP_BASIC_READ444_SUP_SHIFT           4U
+#define  QSPI_IP_SFDP_BASIC_READ118_SUP_SHIFT           24U
+#define  QSPI_IP_SFDP_BASIC_READ188_SUP_SHIFT           8U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_SUP_WIDTH           1U
+#define  QSPI_IP_SFDP_BASIC_READ122_SUP_WIDTH           1U
+#define  QSPI_IP_SFDP_BASIC_READ114_SUP_WIDTH           1U
+#define  QSPI_IP_SFDP_BASIC_READ144_SUP_WIDTH           1U
+#define  QSPI_IP_SFDP_BASIC_READ444_SUP_WIDTH           1U
+#define  QSPI_IP_SFDP_BASIC_READ118_SUP_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ188_SUP_WIDTH           8U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_INST_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ122_INST_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ114_INST_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ144_INST_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ444_INST_DWORD           7U
+#define  QSPI_IP_SFDP_BASIC_READ118_INST_DWORD           17U
+#define  QSPI_IP_SFDP_BASIC_READ188_INST_DWORD           17U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_INST_SHIFT           8U
+#define  QSPI_IP_SFDP_BASIC_READ122_INST_SHIFT           24U
+#define  QSPI_IP_SFDP_BASIC_READ114_INST_SHIFT           24U
+#define  QSPI_IP_SFDP_BASIC_READ144_INST_SHIFT           8U
+#define  QSPI_IP_SFDP_BASIC_READ444_INST_SHIFT           24U
+#define  QSPI_IP_SFDP_BASIC_READ118_INST_SHIFT           24U
+#define  QSPI_IP_SFDP_BASIC_READ188_INST_SHIFT           8U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ122_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ114_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ144_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ444_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ118_INST_WIDTH           8U
+#define  QSPI_IP_SFDP_BASIC_READ188_INST_WIDTH           8U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_MODE_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ122_MODE_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ114_MODE_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ144_MODE_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ444_MODE_DWORD           7U
+#define  QSPI_IP_SFDP_BASIC_READ118_MODE_DWORD           17U
+#define  QSPI_IP_SFDP_BASIC_READ188_MODE_DWORD           17U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_MODE_SHIFT           5U
+#define  QSPI_IP_SFDP_BASIC_READ122_MODE_SHIFT           21U
+#define  QSPI_IP_SFDP_BASIC_READ114_MODE_SHIFT           21U
+#define  QSPI_IP_SFDP_BASIC_READ144_MODE_SHIFT           5U
+#define  QSPI_IP_SFDP_BASIC_READ444_MODE_SHIFT           21U
+#define  QSPI_IP_SFDP_BASIC_READ118_MODE_SHIFT           21U
+#define  QSPI_IP_SFDP_BASIC_READ188_MODE_SHIFT           5U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ122_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ114_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ144_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ444_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ118_MODE_WIDTH           3U
+#define  QSPI_IP_SFDP_BASIC_READ188_MODE_WIDTH           3U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_DUMMY_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ122_DUMMY_DWORD           4U
+#define  QSPI_IP_SFDP_BASIC_READ114_DUMMY_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ144_DUMMY_DWORD           3U
+#define  QSPI_IP_SFDP_BASIC_READ444_DUMMY_DWORD           7U
+#define  QSPI_IP_SFDP_BASIC_READ118_DUMMY_DWORD           17U
+#define  QSPI_IP_SFDP_BASIC_READ188_DUMMY_DWORD           17U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_DUMMY_SHIFT           0U
+#define  QSPI_IP_SFDP_BASIC_READ122_DUMMY_SHIFT           16U
+#define  QSPI_IP_SFDP_BASIC_READ114_DUMMY_SHIFT           16U
+#define  QSPI_IP_SFDP_BASIC_READ144_DUMMY_SHIFT           0U
+#define  QSPI_IP_SFDP_BASIC_READ444_DUMMY_SHIFT           16U
+#define  QSPI_IP_SFDP_BASIC_READ118_DUMMY_SHIFT           16U
+#define  QSPI_IP_SFDP_BASIC_READ188_DUMMY_SHIFT           0U
+
+#define  QSPI_IP_SFDP_BASIC_READ112_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ122_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ114_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ144_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ444_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ118_DUMMY_WIDTH           5U
+#define  QSPI_IP_SFDP_BASIC_READ188_DUMMY_WIDTH           5U
+
+#define  QSPI_IP_SFDP_BASIC_ADDR_BYTES_DWORD           1U
+#define  QSPI_IP_SFDP_BASIC_ADDR_BYTES_SHIFT           17U
+#define  QSPI_IP_SFDP_BASIC_ADDR_BYTES_WIDTH           2U
+
+#define  QSPI_IP_SFDP_BASIC_ADDR_SWITCH_DWORD          16U
+#define  QSPI_IP_SFDP_BASIC_ADDR_SWITCH_SHIFT          24U
+#define  QSPI_IP_SFDP_BASIC_ADDR_SWITCH_WIDTH          8U
+
+
+    /**** Constants for retrieving SFDP parameters - xSPI 1.0 table *****/
+
+    /* Read fast command */
+#define QSPI_IP_SFDP_XSPI1_READ_FAST_DWORD          1U
+#define QSPI_IP_SFDP_XSPI1_READ_FAST_SHIFT          8U
+#define QSPI_IP_SFDP_XSPI1_READ_FAST_WIDTH          8U
+    /* Max. number of dummy cycles */
+#define QSPI_IP_SFDP_XSPI1_DUMMY_DWORD              4U
+#define QSPI_IP_SFDP_XSPI1_DUMMY_SHIFT              7U
+#define QSPI_IP_SFDP_XSPI1_DUMMY_WIDTH              5U
+    /* Chip erase support */
+#define QSPI_IP_SFDP_XSPI1_CHIP_ERASE_DWORD         3U
+#define QSPI_IP_SFDP_XSPI1_CHIP_ERASE_SHIFT         26U
+#define QSPI_IP_SFDP_XSPI1_CHIP_ERASE_WIDTH         1U
+    /* Soft Reset support */
+#define QSPI_IP_SFDP_XSPI1_RESET_DWORD              3U
+#define QSPI_IP_SFDP_XSPI1_RESET_SHIFT              13U
+#define QSPI_IP_SFDP_XSPI1_RESET_WIDTH              1U
+    /* Reset Enable support */
+#define QSPI_IP_SFDP_XSPI1_RESET_EN_DWORD           3U
+#define QSPI_IP_SFDP_XSPI1_RESET_EN_SHIFT           12U
+#define QSPI_IP_SFDP_XSPI1_RESET_EN_WIDTH           1U
+    /* Soft Reset and Enter default protocol mode support */
+#define QSPI_IP_SFDP_XSPI1_RESET_DEF_DWORD          3U
+#define QSPI_IP_SFDP_XSPI1_RESET_DEF_SHIFT          11U
+#define QSPI_IP_SFDP_XSPI1_RESET_DEF_WIDTH          1U
+
+    /**** Constants for retrieving SFDP parameters - Status, Control and Configuration Register Map *****/
+
+    /* Busy (WIP) flag offset */
+#define QSPI_IP_SFDP_SRMAP_WIP_OFFSET_DWORD          5U
+#define QSPI_IP_SFDP_SRMAP_WIP_OFFSET_SHIFT          24U
+#define QSPI_IP_SFDP_SRMAP_WIP_OFFSET_WIDTH          3U
+    /* Busy (WIP) flag value */
+#define QSPI_IP_SFDP_SRMAP_WIP_VALUE_DWORD          5U
+#define QSPI_IP_SFDP_SRMAP_WIP_VALUE_SHIFT          30U
+#define QSPI_IP_SFDP_SRMAP_WIP_VALUE_WIDTH          1U
+    /* Write Enable (WEL) flag offset */
+#define QSPI_IP_SFDP_SRMAP_WEL_OFFSET_DWORD          6U
+#define QSPI_IP_SFDP_SRMAP_WEL_OFFSET_SHIFT          24U
+#define QSPI_IP_SFDP_SRMAP_WEL_OFFSET_WIDTH          3U
+    /* Dummy cycles in 8D-8D-8D mode */
+#define QSPI_IP_SFDP_SRMAP_DUMMY_8D_DWORD          3U
+#define QSPI_IP_SFDP_SRMAP_DUMMY_8D_SHIFT          6U
+#define QSPI_IP_SFDP_SRMAP_DUMMY_8D_WIDTH          4U
+    /* SR read is direct command (not using address) */
+#define QSPI_IP_SFDP_SRMAP_USE_ADDR_DWORD          5U
+#define QSPI_IP_SFDP_SRMAP_USE_ADDR_SHIFT          28U
+#define QSPI_IP_SFDP_SRMAP_USE_ADDR_WIDTH          1U
+    /* Address offset for volatile registers */
+#define QSPI_IP_SFDP_SRMAP_OFFSET_DWORD          1U
+#define QSPI_IP_SFDP_SRMAP_OFFSET_SHIFT          0U
+#define QSPI_IP_SFDP_SRMAP_OFFSET_WIDTH          32U
+    /* Number of address bytes used for Generic Addressable Read/Write Status/Control register commands for volatile registers */
+#define QSPI_IP_SFDP_SRMAP_NBYTES_DWORD          3U
+#define QSPI_IP_SFDP_SRMAP_NBYTES_SHIFT          28U
+#define QSPI_IP_SFDP_SRMAP_NBYTES_WIDTH          2U
+    /* SR local address */
+#define QSPI_IP_SFDP_SRMAP_SR_ADDR_DWORD          5U
+#define QSPI_IP_SFDP_SRMAP_SR_ADDR_SHIFT          16U
+#define QSPI_IP_SFDP_SRMAP_SR_ADDR_WIDTH          8U
+    /* SR address shift (before adding to the offset) */
+#define QSPI_IP_SFDP_SRMAP_SR_SHIFT_DWORD          5U
+#define QSPI_IP_SFDP_SRMAP_SR_SHIFT_SHIFT          27U
+#define QSPI_IP_SFDP_SRMAP_SR_SHIFT_WIDTH          1U
+
+    /**** Constants for retrieving SFDP parameters - Command Sequences to Change to Octal DDR (8D-8D-8D) mode *****/
+
+    /* Length of command sequence */
+#define QSPI_IP_SFDP_2DOPI_CMD_LEN_SHIFT          24U
+#define QSPI_IP_SFDP_2DOPI_CMD_LEN_WIDTH          8U
+    /* Bytes of command sequence */
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE1_SHIFT          16U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE2_SHIFT          8U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE3_SHIFT          0U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE4_SHIFT          24U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE5_SHIFT          16U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE6_SHIFT          8U
+#define QSPI_IP_SFDP_2DOPI_CMD_BYTE7_SHIFT          0U
+
+    /**** Constants for retrieving SFDP parameters - 4-byte Address Instructions *****/
+
+#define QSPI_IP_SFDP_4BADD_INSTR_SUP_DWORD           1U
+#define QSPI_IP_SFDP_4BADD_INSTR_SUP_WIDTH           1U
+#define QSPI_IP_SFDP_4BADD_ERASE_INST_DWORD          2U
+#define QSPI_IP_SFDP_4BADD_ERASE_INST_WIDTH          8U
+#define QSPI_IP_SFDP_4BADD_ERASE1_SUP_SHIFT          9U
+#define QSPI_IP_SFDP_4BADD_ERASE2_SUP_SHIFT          10U
+#define QSPI_IP_SFDP_4BADD_ERASE3_SUP_SHIFT          11U
+#define QSPI_IP_SFDP_4BADD_ERASE4_SUP_SHIFT          12U
+#define QSPI_IP_SFDP_4BADD_ERASE1_INST_SHIFT         0U
+#define QSPI_IP_SFDP_4BADD_ERASE2_INST_SHIFT         8U
+#define QSPI_IP_SFDP_4BADD_ERASE3_INST_SHIFT         16U
+#define QSPI_IP_SFDP_4BADD_ERASE4_INST_SHIFT         24U
+
+#define  QSPI_IP_SFDP_4BADD_READ112_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_READ122_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_READ114_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_READ144_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_READ444_SUP_DWORD           0xFFU     /* invalid */
+#define  QSPI_IP_SFDP_4BADD_READ118_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_READ188_SUP_DWORD           1U
+
+#define  QSPI_IP_SFDP_4BADD_READ111_SUP_SHIFT           0U
+#define  QSPI_IP_SFDP_4BADD_READ112_SUP_SHIFT           2U
+#define  QSPI_IP_SFDP_4BADD_READ122_SUP_SHIFT           3U
+#define  QSPI_IP_SFDP_4BADD_READ114_SUP_SHIFT           4U
+#define  QSPI_IP_SFDP_4BADD_READ144_SUP_SHIFT           5U
+#define  QSPI_IP_SFDP_4BADD_READ444_SUP_SHIFT           1U       /* use 1-1-1 fast read */
+#define  QSPI_IP_SFDP_4BADD_READ118_SUP_SHIFT           20U
+#define  QSPI_IP_SFDP_4BADD_READ188_SUP_SHIFT           21U
+
+
+#define  QSPI_IP_SFDP_4BADD_WRITE112_SUP_DWORD           0xFFU     /* invalid */
+#define  QSPI_IP_SFDP_4BADD_WRITE122_SUP_DWORD           0xFFU     /* invalid */
+#define  QSPI_IP_SFDP_4BADD_WRITE114_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_WRITE144_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_WRITE444_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_WRITE118_SUP_DWORD           1U
+#define  QSPI_IP_SFDP_4BADD_WRITE188_SUP_DWORD           1U
+
+#define  QSPI_IP_SFDP_4BADD_WRITE112_SUP_SHIFT           0U
+#define  QSPI_IP_SFDP_4BADD_WRITE122_SUP_SHIFT           0U
+#define  QSPI_IP_SFDP_4BADD_WRITE114_SUP_SHIFT           7U
+#define  QSPI_IP_SFDP_4BADD_WRITE144_SUP_SHIFT           8U
+#define  QSPI_IP_SFDP_4BADD_WRITE444_SUP_SHIFT           6U      /* use 1-1-1 write */
+#define  QSPI_IP_SFDP_4BADD_WRITE118_SUP_SHIFT           23U
+#define  QSPI_IP_SFDP_4BADD_WRITE188_SUP_SHIFT           24U
+
+
+/*******************************************************************************
+ * Enumerations.
+ ******************************************************************************/
+
+#if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
+
+/* sfdp modes */
+typedef enum
+{
+    QSPI_IP_SFDP_1S_1S_1S  = 0x00U,   /*!< 1S-1S-1S mode */
+    QSPI_IP_SFDP_2S_2S_2S  = 0x01U,   /*!< 2S-2S-2S mode */
+    QSPI_IP_SFDP_4S_4S_4S  = 0x02U,   /*!< 4S-4S-4S mode */
+    QSPI_IP_SFDP_4S_4D_4D  = 0x03U,   /*!< 4S-4D-4D mode */
+    QSPI_IP_SFDP_8D_8D_8D  = 0x04U,   /*!< 8D-8D-8D mode */
+} Qspi_Ip_SfdpModes;
+
+/* sfdp table types */
+typedef enum
+{
+    QSPI_IP_SFDP_TABLE_BASIC   = 0x00U,   /*!< Basic flash parameter table                               */
+    QSPI_IP_SFDP_TABLE_4BADD   = 0x84U,   /*!< 4-byte Address Instruction Table                          */
+    QSPI_IP_SFDP_TABLE_XSPI1   = 0x05U,   /*!< eXtended Serial Peripheral Interface (xSPI) Profile 1.0   */
+    QSPI_IP_SFDP_TABLE_SRMAP   = 0x87U,   /*!< Status, Control and Configuration Register Map            */
+    QSPI_IP_SFDP_TABLE_2DOPI   = 0x0AU,   /*!< Command Sequences to change to DOPI (8D-8D-8D) mode       */
+} Qspi_Ip_SfdpTables;
+
+/* fast read modes - basic parameters table */
+typedef enum
+{
+    QSPI_IP_SFDP_READ_MODE_112    = 0x00U,  /*!< 1-1-2 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_122    = 0x01U,  /*!< 1-2-2 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_114    = 0x02U,  /*!< 1-1-4 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_144    = 0x03U,  /*!< 1-4-4 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_444    = 0x04U,  /*!< 4-4-4 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_118    = 0x05U,  /*!< 1-1-8 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_188    = 0x06U,  /*!< 1-8-8 fast read mode            */
+    QSPI_IP_SFDP_READ_MODE_MAX    = 0x07U,  /*!< Number of read modes            */
+} flash_external_fast_read_modes_t;
+
+/* structure containing sfdp tables */
+typedef struct
+{
+    uint32 paramTable_basic[QSPI_IP_TABLE_SIZE_BASIC];
+    uint32 paramTable_4badd[QSPI_IP_TABLE_SIZE_4BADD];
+    uint32 paramTable_xspi1[QSPI_IP_TABLE_SIZE_XSPI1];
+    uint32 paramTable_srmap[QSPI_IP_TABLE_SIZE_SRMAP];
+    uint32 paramTable_2dopi[QSPI_IP_TABLE_SIZE_2DOPI];
+    uint8 paramTableLength_basic;
+    uint8 paramTableLength_4badd;
+    uint8 paramTableLength_xspi1;
+    uint8 paramTableLength_srmap;
+    uint8 paramTableLength_2dopi;
+} Qspi_Ip_SfdpTablesContainer;
+
+/*******************************************************************************
+ * Local Variables
+ ******************************************************************************/
+
+#define FLS_START_SEC_VAR_CLEARED_16
+#include "Fls_MemMap.h"
+
+static uint16 lutCount;                     /* Current number of operations in the LUT table                               */
+
+#define FLS_STOP_SEC_VAR_CLEARED_16
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+
+static uint8 initOpCount;                  /* Current number of operations in the initial operations list                 */
+static uint8 basicAddrBits;                /* Current number of operations in the initial operations list                 */
+static uint8 modeIndex;                    /* Index of the selected read mode                                             */
+
+#define FLS_STOP_SEC_VAR_CLEARED_8
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+static Qspi_Ip_LutPadsType cmdPads;         /* Pads to use for commands (e.g. 4 if the selected operation mode is 4-4-4)   */
+static Qspi_Ip_LutPadsType cmdPadsInit;     /* Number of pads used for commands in the initial state                       */
+
+#define FLS_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+
+static boolean overflow;                    /* Either LUT or initial operations list was not big enough                    */
+static boolean quadAvailable;               /* Quad mode can be used                                                       */
+
+#define FLS_STOP_SEC_VAR_CLEARED_BOOLEAN
+#include "Fls_MemMap.h"
+
+
+
+/* tables for extracting parameters from SFDP table */
+
+#define FLS_START_SEC_VAR_INIT_8
+#include "Fls_MemMap.h"
+
+static uint8 eraseInstDword[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE2_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE3_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE4_INST_DWORD
+};
+static uint8 eraseInstShift[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE2_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE3_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE4_INST_SHIFT
+};
+static uint8 eraseInstWidth[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE2_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE3_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE4_INST_WIDTH
+};
+static uint8 eraseSizeDword[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_SIZE_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE2_SIZE_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE3_SIZE_DWORD,
+    QSPI_IP_SFDP_BASIC_ERASE4_SIZE_DWORD
+};
+static uint8 eraseSizeShift[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_SIZE_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE2_SIZE_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE3_SIZE_SHIFT,
+    QSPI_IP_SFDP_BASIC_ERASE4_SIZE_SHIFT
+};
+static uint8 eraseSizeWidth[4U] = {
+    QSPI_IP_SFDP_BASIC_ERASE1_SIZE_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE2_SIZE_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE3_SIZE_WIDTH,
+    QSPI_IP_SFDP_BASIC_ERASE4_SIZE_WIDTH
+};
+
+static uint8 erase4ByteSupShift[4U] = {
+    QSPI_IP_SFDP_4BADD_ERASE1_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE2_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE3_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE4_SUP_SHIFT
+};
+
+static uint8 erase4ByteInstShift[4U] = {
+    QSPI_IP_SFDP_4BADD_ERASE1_INST_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE2_INST_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE3_INST_SHIFT,
+    QSPI_IP_SFDP_4BADD_ERASE4_INST_SHIFT
+};
+
+static uint8 dopiSwitchShift[7U] = {
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE1_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE2_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE3_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE4_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE5_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE6_SHIFT,
+    QSPI_IP_SFDP_2DOPI_CMD_BYTE7_SHIFT,
+};
+static uint8 dopiSwitchWord[7U] = {
+    0U,
+    0U,
+    0U,
+    1U,
+    1U,
+    1U,
+    1U,
+};
+
+static uint8 readSupDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ122_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ114_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ144_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ444_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ118_SUP_DWORD,
+    QSPI_IP_SFDP_BASIC_READ188_SUP_DWORD
+};
+
+static uint8 readSupShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ122_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ114_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ144_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ444_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ118_SUP_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ188_SUP_SHIFT
+};
+
+static uint8 readSupWitdh[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ122_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ114_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ144_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ444_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ118_SUP_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ188_SUP_WIDTH
+};
+
+static uint8 read4ByteSupDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_4BADD_READ112_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ122_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ114_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ144_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ444_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ118_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_READ188_SUP_DWORD
+};
+
+static uint8 read4ByteSupShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_4BADD_READ112_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ122_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ114_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ144_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ444_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ118_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_READ188_SUP_SHIFT
+};
+
+static uint8 write4ByteSupDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_4BADD_WRITE112_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE122_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE114_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE144_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE444_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE118_SUP_DWORD,
+    QSPI_IP_SFDP_4BADD_WRITE188_SUP_DWORD
+};
+
+static uint8 write4ByteSupShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_4BADD_WRITE112_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE122_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE114_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE144_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE444_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE118_SUP_SHIFT,
+    QSPI_IP_SFDP_4BADD_WRITE188_SUP_SHIFT
+};
+
+static uint8 read4ByteInst[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    0x3CU,
+    0xBCU,
+    0x6CU,
+    0xECU,
+    0x13U,
+    0x7CU,
+    0xCCU
+};
+
+static uint8 write4ByteInst[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    0x00U,
+    0x00U,
+    0x34U,
+    0x3EU,
+    0x12U,
+    0x84U,
+    0x8EU
+};
+
+static uint8 readInstDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ122_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ114_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ144_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ444_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ118_INST_DWORD,
+    QSPI_IP_SFDP_BASIC_READ188_INST_DWORD
+};
+
+static uint8 readInstShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ122_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ114_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ144_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ444_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ118_INST_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ188_INST_SHIFT
+};
+
+static uint8 readInstWidth[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ122_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ114_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ144_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ444_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ118_INST_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ188_INST_WIDTH
+};
+
+static uint8 readModeDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ122_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ114_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ144_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ444_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ118_MODE_DWORD,
+    QSPI_IP_SFDP_BASIC_READ188_MODE_DWORD
+};
+
+static uint8 readModeShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ122_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ114_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ144_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ444_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ118_MODE_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ188_MODE_SHIFT
+};
+
+static uint8 readModeWidth[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ122_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ114_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ144_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ444_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ118_MODE_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ188_MODE_WIDTH
+};
+
+static uint8 readDummyDword[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ122_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ114_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ144_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ444_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ118_DUMMY_DWORD,
+    QSPI_IP_SFDP_BASIC_READ188_DUMMY_DWORD
+};
+
+static uint8 readDummyShift[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ122_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ114_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ144_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ444_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ118_DUMMY_SHIFT,
+    QSPI_IP_SFDP_BASIC_READ188_DUMMY_SHIFT
+};
+
+static uint8 readDummyWidth[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_SFDP_BASIC_READ112_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ122_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ114_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ144_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ444_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ118_DUMMY_WIDTH,
+    QSPI_IP_SFDP_BASIC_READ188_DUMMY_WIDTH
+};
+
+#define FLS_STOP_SEC_VAR_INIT_8
+#include "Fls_MemMap.h"
+
+
+#define FLS_START_SEC_VAR_INIT_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+static Qspi_Ip_LutPadsType readModeInstPads[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_1
+};
+
+static Qspi_Ip_LutPadsType readModeAddrPads[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_2,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_1,
+    QSPI_IP_LUT_PADS_8
+};
+
+static Qspi_Ip_LutPadsType readModeDataPads[QSPI_IP_SFDP_READ_MODE_MAX] = {
+    QSPI_IP_LUT_PADS_2,
+    QSPI_IP_LUT_PADS_2,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_4,
+    QSPI_IP_LUT_PADS_8,
+    QSPI_IP_LUT_PADS_8
+};
+
+#define FLS_STOP_SEC_VAR_INIT_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+/*==================================================================================================
+ *LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+static inline Qspi_Ip_InstrOpType Qspi_Ip_PackLut(Qspi_Ip_LutCommandsType cmd, Qspi_Ip_LutPadsType pad, uint8 op);
+static inline void Qspi_Ip_SfdpLutInit(void);
+static inline void Qspi_Ip_SfdpLutAdd(const Qspi_Ip_LutConfigType *lutSequences, Qspi_Ip_InstrOpType instr);
+
+static inline uint32 Qspi_Ip_SfdpGetBasicParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue);
+static inline uint32 Qspi_Ip_SfdpGet4BAddParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue);
+static inline uint32 Qspi_Ip_SfdpGetXspi1Param(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue);
+static inline uint32 Qspi_Ip_SfdpGetSRMapParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue);
+static inline uint32 Qspi_Ip_SfdpGet2DopiParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue);
+
+static void Qspi_Ip_SfdpLutAddSrAddr(const Qspi_Ip_LutConfigType *lutSequences, const Qspi_Ip_SfdpTablesContainer *sfdpTables);
+static inline boolean Qspi_Ip_SfdpSignatureCheck(const uint8 *data);
+static inline void Qspi_Ip_SfdpInitLut(uint32 instance, Qspi_Ip_SfdpModes mode);
+static void Qspi_Ip_WaitAfterReset(void);
+static void Qspi_Ip_SfdpInitReset(uint32 instance, uint32 baseAddress);
+static Qspi_Ip_StatusType Qspi_Ip_SfdpCheck(uint32 instance, uint32 baseAddress);
+static inline boolean Qspi_Ip_SfdpCheckMinorRevision(uint8 minorRevision);
+static inline uint8 Qspi_Ip_SfdpGetCmdExt(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 instruction);
+
+static inline boolean Qspi_Ip_SfdpCheckNewerRevision(uint8 paramIdLSB,
+                                                     uint8 tableType,
+                                                     uint8 majorRevision,
+                                                     uint8 minorRevision,
+                                                     sint16 minorRevisionMax
+                                                    );
+
+static Qspi_Ip_StatusType Qspi_Ip_SfdpFindTable(uint32 instance, uint32 baseAddress, Qspi_Ip_SfdpTables tableType, uint32 * paramTable, uint8 * paramTableLength);
+static Qspi_Ip_StatusType Qspi_Ip_SfdpReadTables(uint32 instance, uint32 baseAddress, Qspi_Ip_SfdpTablesContainer *sfdpTables);
+
+static void Qspi_Ip_SfdpInitSimpleCmd(uint8 cmd, const Qspi_Ip_MemoryConfigType * pConfig);
+static uint8 Qspi_Ip_SfdpGetWeSrInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables);
+static void Qspi_Ip_SfdpInitWriteReg(uint8 cmd, uint8 wrenCmd, uint8 size, uint32 value, const Qspi_Ip_MemoryConfigType * pConfig);
+
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_01(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_02(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_08(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_16(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpGetBasicAddrBits(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpConfigureQE(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_LutCommandsType Qspi_Ip_SfdpGetModeInstr(uint8 modeClocks, Qspi_Ip_LutPadsType addrPads);
+static void Qspi_Ip_SfdpGetSpiReadInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt, uint8 *instruction, uint8 *addrBits);
+static void Qspi_Ip_SfdpConfigBasicRead(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig);
+
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_01(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_04(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_08(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_16(const Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch(const Qspi_Ip_SfdpTablesContainer * sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpGetBasicReadInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetBasicWriteInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpGetXspi1ReadInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetXspi1WriteInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static uint8 Qspi_Ip_SfdpGetBasicEraseInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt, uint8 *addrbits);
+static uint8 Qspi_Ip_SfdpGetXspi1EraseInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt);
+static void Qspi_Ip_SfdpGetBasicEraseInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetXspi1EraseInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetBasicStatusInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetXspi1StatusInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpConfigReset1(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads);
+static void Qspi_Ip_SfdpConfigReset2(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads);
+static void Qspi_Ip_SfdpConfigReset4(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads);
+static void Qspi_Ip_SfdpConfigReset8(const Qspi_Ip_MemoryConfigType * pConfig, Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads);
+static void Qspi_Ip_SfdpConfigReset16(const Qspi_Ip_MemoryConfigType * pConfig, Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads);
+
+static void Qspi_Ip_SfdpGetBasicResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig,
+                                          Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads
+                                         );
+
+static void Qspi_Ip_SfdpGetXspi1ResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetXspi1InitResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpGetBasicSuspendInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetXspi1SuspendInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpAdd2dopiOperation(const Qspi_Ip_MemoryConfigType * pConfig, uint8 seqSize,const uint32 *words);
+static void Qspi_Ip_SfdpGetXspi1InitOpInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetBasicInitOpInfo(Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGet0xxInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static void Qspi_Ip_SfdpConfigureOther(Qspi_Ip_MemoryConfigType * pConfig);
+static void Qspi_Ip_SfdpGetSize(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static Qspi_Ip_StatusType Qspi_Ip_ConfigureBasic(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+static Qspi_Ip_StatusType Qspi_Ip_ConfigureXspi1(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig);
+
+static inline void Qspi_Ip_SfdpGetBasicInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                            Qspi_Ip_MemoryConfigType * pConfig
+                                           );
+
+static inline void Qspi_Ip_SfdpGetXspi1Info(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                            Qspi_Ip_MemoryConfigType * pConfig
+                                           );
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+/*******************************************************************************
+ * Private Functions
+ ******************************************************************************/
+
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_PackLut
+ * Description   : Packs command, pads count and operand in a LUT entry
+ */
+static inline Qspi_Ip_InstrOpType Qspi_Ip_PackLut(Qspi_Ip_LutCommandsType cmd, Qspi_Ip_LutPadsType pad, uint8 op)
+{
+    return (Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)cmd | (Qspi_Ip_InstrOpType)pad | (Qspi_Ip_InstrOpType)op);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpLutInit
+ * Description   : Initializes LUT and init operations counters
+ */
+static inline void Qspi_Ip_SfdpLutInit(void)
+{
+    lutCount = 0U;
+    initOpCount = 0U;
+    overflow = FALSE;
+    quadAvailable = TRUE;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpLutAdd
+ * Description   : Initializes LUT and init operations counters
+ */
+static inline void Qspi_Ip_SfdpLutAdd(const Qspi_Ip_LutConfigType *lutSequences, Qspi_Ip_InstrOpType instr)
+{
+    if (lutCount < lutSequences->opCount)
+    {
+        lutSequences->lutOps[lutCount] = instr;
+        lutCount++;
+    }
+    else
+    {
+        overflow = TRUE;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicParam
+ * Description   : Returns a bitfield from the SFDP tables
+ */
+static inline uint32 Qspi_Ip_SfdpGetBasicParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue)
+{
+    const uint32* tablePtr  = NULL_PTR;
+    uint8 tableSize         = 0U;
+    volatile uint32 mask    = 0UL;
+    volatile uint32 result  = 0UL;
+
+    tablePtr  = sfdpTables->paramTable_basic;
+    tableSize = sfdpTables->paramTableLength_basic;
+
+    if ((NULL_PTR != tablePtr) && (dword <= tableSize) )
+    {
+        /* get required field */
+        mask   = (1UL << (uint32)(width)) - 1UL;
+        result = ((uint32)(tablePtr[dword - 1U] >> shift)) & mask;
+    }
+    else
+    {
+        /* table too short, use default */
+        result = defaultValue;
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGet4BAddParam
+ * Description   : Returns a bitfield from the SFDP tables
+ */
+static inline uint32 Qspi_Ip_SfdpGet4BAddParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue)
+{
+    const uint32* tablePtr  = NULL_PTR;
+    uint8 tableSize         = 0U;
+    volatile uint32 mask    = 0UL;
+    volatile uint32 result  = 0UL;
+
+    tablePtr  = sfdpTables->paramTable_4badd;
+    tableSize = sfdpTables->paramTableLength_4badd;
+
+    if ((NULL_PTR != tablePtr) && (dword <= tableSize) )
+    {
+        /* get required field */
+        mask   = (1UL << (uint32)(width)) - 1UL;
+        result = ((uint32)(tablePtr[dword - 1U] >> shift)) & mask;
+    }
+    else
+    {
+        /* table too short, use default */
+        result = defaultValue;
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1Param
+ * Description   : Returns a bitfield from the SFDP tables
+ */
+static inline uint32 Qspi_Ip_SfdpGetXspi1Param(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue)
+{
+    const uint32* tablePtr  = NULL_PTR;
+    uint8 tableSize         = 0U;
+    volatile uint32 mask    = 0UL;
+    volatile uint32 result  = 0UL;
+
+    tablePtr  = sfdpTables->paramTable_xspi1;
+    tableSize = sfdpTables->paramTableLength_xspi1;
+
+    if ((NULL_PTR != tablePtr) && (dword <= tableSize) )
+    {
+        /* get required field */
+        mask   = (1UL << (uint32)(width)) - 1UL;
+        result = ((uint32)(tablePtr[dword - 1U] >> shift)) & mask;
+    }
+    else
+    {
+        /* table too short, use default */
+        result = defaultValue;
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetSRMapParam
+ * Description   : Returns a bitfield from the SFDP tables
+ */
+static inline uint32 Qspi_Ip_SfdpGetSRMapParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue)
+{
+    const uint32* tablePtr  = NULL_PTR;
+    uint8 tableSize         = 0U;
+    volatile uint32 mask    = 0UL;
+    volatile uint32 result  = 0UL;
+
+    tablePtr  = sfdpTables->paramTable_srmap;
+    tableSize = sfdpTables->paramTableLength_srmap;
+
+    if ((NULL_PTR != tablePtr) && (dword <= tableSize) )
+    {
+        /* get required field */
+        mask   = (1UL << (uint32)(width)) - 1UL;
+        result = ((uint32)(tablePtr[dword - 1U] >> shift)) & mask;
+    }
+    else
+    {
+        /* table too short, use default */
+        result = defaultValue;
+    }
+
+    return result;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGet2DopiParam
+ * Description   : Returns a bitfield from the SFDP tables
+ */
+static inline uint32 Qspi_Ip_SfdpGet2DopiParam(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                               uint8 dword, uint8 shift, uint8 width, uint32 defaultValue)
+{
+    const uint32* tablePtr  = NULL_PTR;
+    uint8 tableSize         = 0U;
+    volatile uint32 mask    = 0UL;
+    volatile uint32 result  = 0UL;
+
+    tablePtr  = sfdpTables->paramTable_2dopi;
+    tableSize = sfdpTables->paramTableLength_2dopi;
+
+    if ((NULL_PTR != tablePtr) && (dword <= tableSize) )
+    {
+        /* get required field */
+        mask   = (1UL << (uint32)(width)) - 1UL;
+        result = ((uint32)(tablePtr[dword - 1U] >> shift)) & mask;
+    }
+    else
+    {
+        /* table too short, use default */
+        result = defaultValue;
+    }
+
+    return result;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpLutAddSrAddr
+ * Description   : Initializes LUT and init operations counters
+ */
+static void Qspi_Ip_SfdpLutAddSrAddr(const Qspi_Ip_LutConfigType *lutSequences, const Qspi_Ip_SfdpTablesContainer *sfdpTables)
+{
+    uint32 addrOffset;
+    uint8 srAddr;
+    uint8 srShift;
+    uint8 nBytes;
+    sint8 cnt;
+    uint8 directCmd;
+
+    /* SR read is direct command (not using address */
+    directCmd = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_USE_ADDR_DWORD,
+                                                 QSPI_IP_SFDP_SRMAP_USE_ADDR_SHIFT, QSPI_IP_SFDP_SRMAP_USE_ADDR_WIDTH, 0x0U);
+    if (directCmd == 0U)
+    {
+        /* direct command - nothing to do */
+    }
+    else
+    {
+        /* Address offset for volatile registers */
+        addrOffset = (uint32)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_OFFSET_DWORD,
+                                                       QSPI_IP_SFDP_SRMAP_OFFSET_SHIFT, QSPI_IP_SFDP_SRMAP_OFFSET_WIDTH, 0x0U);
+        /* Number of address bytes used for Generic Addressable Read/Write Status/Control register commands for volatile registers */
+        nBytes = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_NBYTES_DWORD,
+                                                  QSPI_IP_SFDP_SRMAP_NBYTES_SHIFT, QSPI_IP_SFDP_SRMAP_NBYTES_WIDTH, 0x0U);
+        /* SR local address */
+        srAddr = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_SR_ADDR_DWORD,
+                                                  QSPI_IP_SFDP_SRMAP_SR_ADDR_SHIFT, QSPI_IP_SFDP_SRMAP_SR_ADDR_WIDTH, 0x0U);
+        /* SR address shift (before adding to the offset) */
+        srShift = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_SR_SHIFT_DWORD,
+                                                   QSPI_IP_SFDP_SRMAP_SR_SHIFT_SHIFT, QSPI_IP_SFDP_SRMAP_SR_SHIFT_WIDTH, 0x0U);
+
+        /* compute SR address */
+        addrOffset = addrOffset + ((uint32)srAddr << (srShift * 8U));
+        /* add address to LUT sequence. Use CMD in case addr is out of range */
+        for (cnt = (sint8)nBytes; cnt >= 0; cnt--)
+        {
+            srAddr = (uint8)((addrOffset >> ((uint8)cnt * 8U)) & 0xFFU);
+            Qspi_Ip_SfdpLutAdd(lutSequences, Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, srAddr));
+        }
+    }
+
+    return;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpSignatureCheck
+ * Description   : Checks SFDP signature
+ */
+static inline boolean Qspi_Ip_SfdpSignatureCheck(const uint8 *data)
+{
+    boolean retCode = FALSE;
+
+    if ((data[0] == 0x53U) && (data[1] == 0x46U) && (data[2] == 0x44U) && (data[3] == 0x50U))
+    {
+        retCode = TRUE;
+    }
+
+    return retCode;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpInitLut
+ * Description   : Initializes LUT table for reading SFDP information, using the specified format
+ */
+static inline void Qspi_Ip_SfdpInitLut(uint32 instance, Qspi_Ip_SfdpModes mode)
+{
+    Qspi_Ip_LutCommandsType instCmd;
+    Qspi_Ip_LutCommandsType addrCmd;
+    Qspi_Ip_LutCommandsType dataCmd;
+    Qspi_Ip_LutPadsType pads;
+
+    /* Set command parameters according to mode */
+    instCmd = QSPI_IP_LUT_INSTR_CMD;
+    addrCmd = QSPI_IP_LUT_INSTR_ADDR;
+    dataCmd = QSPI_IP_LUT_INSTR_READ;
+    if (QSPI_IP_SFDP_8D_8D_8D == mode)
+    {
+        pads = QSPI_IP_LUT_PADS_8;
+        instCmd = QSPI_IP_LUT_INSTR_CMD_DDR;
+        addrCmd = QSPI_IP_LUT_INSTR_ADDR_DDR;
+        dataCmd = QSPI_IP_LUT_INSTR_READ_DDR;
+    }
+    else if (QSPI_IP_SFDP_4S_4D_4D == mode)
+    {
+        pads = QSPI_IP_LUT_PADS_4;
+        addrCmd = QSPI_IP_LUT_INSTR_ADDR_DDR;
+        dataCmd = QSPI_IP_LUT_INSTR_READ_DDR;
+    }
+    else if (QSPI_IP_SFDP_4S_4S_4S == mode)
+    {
+        pads = QSPI_IP_LUT_PADS_4;
+    }
+    else if (QSPI_IP_SFDP_2S_2S_2S == mode)
+    {
+        pads = QSPI_IP_LUT_PADS_2;
+    }
+    else
+    {
+        pads = QSPI_IP_LUT_PADS_1;
+    }
+
+/* Build SFDP Read Sequence */
+    Qspi_Ip_SetLut(instance, (uint8)(FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT),
+                    Qspi_Ip_PackLut(instCmd, pads, (uint8)QSPI_IP_CMD_SFDP_READ),         /* READ SFDP command on 1 data line */
+                    Qspi_Ip_PackLut(addrCmd, pads, 24U));                                   /* 24-bit address on 1 data line */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 1U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_DUMMY, pads, 8U),                          /* 8 Dummy cycles */
+                    Qspi_Ip_PackLut(dataCmd, pads, 0x10U));                                 /* Read data on 1 data line */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 2U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),                           /* End of sequence */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U));                          /* End of sequence */
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_WaitAfterReset
+ * Description   : Wait until external memory is available for operation after a reset
+ */
+static void Qspi_Ip_WaitAfterReset(void)
+{
+    uint32  u32ElapsedTicks = 0U;
+    uint32  u32TimeoutTicks;
+    uint32  u32CurrentTicks;
+
+    /* Prepare timeout counter */
+    u32TimeoutTicks = OsIf_MicrosToTicks(QSPI_IP_RESET_TIMEOUT, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    u32CurrentTicks = OsIf_GetCounter((OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    /* Wait for the specified time */
+    do
+    {
+        u32ElapsedTicks += OsIf_GetElapsed(&u32CurrentTicks, (OsIf_CounterType)QSPI_IP_TIMEOUT_TYPE);
+    }
+    while (u32ElapsedTicks < u32TimeoutTicks);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpInitReset
+ * Description   : Sends 8D-8D-8D reset commands to force device to enter SPI mode.
+ */
+static void Qspi_Ip_SfdpInitReset(uint32 instance, uint32 baseAddress)
+{
+    /* As we don't know yet the command extension convention of the device, try both ways */
+    /* 1. Command Extension is the inverse of the Command */
+    /* Send Reset Enable Command */
+    Qspi_Ip_SetLut(instance, (uint8)(FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_ENABLE),         /* Reset Enable command in DOPI Mode */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)~QSPI_IP_CMD_XSPI_RESET_ENABLE));       /* command extension */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 1U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),                           /* End of sequence */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U));                          /* End of sequence */
+    (void)Qspi_Ip_IpCommand(instance, QSPI_IP_COMMAND_LUT, baseAddress);
+    /* Send Reset Command */
+    Qspi_Ip_SetLut(instance, (uint8)(FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_DEF),         /* Reset command in DOPI Mode */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)~QSPI_IP_CMD_XSPI_RESET_DEF));       /* command extension */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 1U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),                           /* End of sequence */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U));                          /* End of sequence */
+    (void)Qspi_Ip_IpCommand(instance, QSPI_IP_COMMAND_LUT, baseAddress);
+
+    /* 2. Command Extension is the same as the Command */
+    /* Send Reset Enable Command */
+    Qspi_Ip_SetLut(instance, (uint8)(FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_ENABLE),         /* Reset Enable command in DOPI Mode */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_ENABLE));        /* command extension */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 1U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),                           /* End of sequence */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U));                          /* End of sequence */
+    (void)Qspi_Ip_IpCommand(instance, QSPI_IP_COMMAND_LUT, baseAddress);
+    /* Send Reset Command */
+    Qspi_Ip_SetLut(instance, (uint8)(FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_DEF),         /* Reset command in DOPI Mode */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, (uint8)QSPI_IP_CMD_XSPI_RESET_DEF));        /* command extension */
+    Qspi_Ip_SetLut(instance, (uint8)((FEATURE_QSPI_LUT_SEQUENCE_SIZE * QSPI_IP_COMMAND_LUT) + 1U),
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),                           /* End of sequence */
+                    Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U));                          /* End of sequence */
+    (void)Qspi_Ip_IpCommand(instance, QSPI_IP_COMMAND_LUT, baseAddress);
+
+    /* Wait for reset to complete */
+    Qspi_Ip_WaitAfterReset();
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpCheck
+ * Description   : Checks the existence of SFDP support.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_SfdpCheck(uint32 instance, uint32 baseAddress)
+{
+    /* List of sfdp modes attempt to read and the corresponding pad return values */
+    const Qspi_Ip_SfdpModes  modes[4U] = {QSPI_IP_SFDP_4S_4D_4D, QSPI_IP_SFDP_4S_4S_4S, QSPI_IP_SFDP_2S_2S_2S, QSPI_IP_SFDP_1S_1S_1S};
+    const Qspi_Ip_LutPadsType pads[4U] = {QSPI_IP_LUT_PADS_4,    QSPI_IP_LUT_PADS_4,    QSPI_IP_LUT_PADS_2,    QSPI_IP_LUT_PADS_1   };
+    const uint32 maxAttempts = 4U;
+    Qspi_Ip_StatusType status;
+    uint8 data[4U];
+    uint32 i;
+
+    /* Attempt to read SFDP in 8D-8D-8D mode  */
+    /* Workaround: send 8D-8D-8D reset commands as specified by xSPI Profile 1.0 */
+    Qspi_Ip_SfdpInitReset(instance, baseAddress);
+
+    /* Attempt to read SFDP modes */
+    for (i = 0U; i < maxAttempts; i++)
+    {
+        Qspi_Ip_SfdpInitLut(instance, modes[i]);
+        status = Qspi_Ip_IpRead(instance, QSPI_IP_COMMAND_LUT, baseAddress, data, NULL_PTR, 4U);
+        if ((STATUS_QSPI_IP_SUCCESS == status) && Qspi_Ip_SfdpSignatureCheck(data))
+        {
+            /* Found a supported mode */
+            cmdPadsInit = pads[i];
+            break;
+        }
+    }
+
+    /* All read attempts failed, device does not support SFDP */
+    if (i >= maxAttempts)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpCheckMinorRevision
+ * Description   : Verifies validity of sfdp minor revision
+ *
+ *END**************************************************************************/
+static inline boolean Qspi_Ip_SfdpCheckMinorRevision(uint8 minorRevision)
+{
+    /* Revision and size must match the specifications of JESD216, JESD216A or JESD216B; also accept newer revisions */
+    return ((QSPI_IP_SFDP_MINOR_REVISION_REV_0 == minorRevision) ||
+            (minorRevision >= QSPI_IP_SFDP_MINOR_REVISION_REV_A));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetCmdExt
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static inline uint8 Qspi_Ip_SfdpGetCmdExt(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 instruction)
+{
+    uint8 cmdExt;
+
+    /* Get Command Extension */
+    cmdExt = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_CMD_EXT_DWORD,
+                                              QSPI_IP_SFDP_BASIC_CMD_EXT_SHIFT, QSPI_IP_SFDP_BASIC_CMD_EXT_WIDTH, 0x1U);
+    if (cmdExt == 0U)
+    {
+        cmdExt = instruction;
+    }
+    else
+    {
+        cmdExt = ~instruction;
+    }
+    return cmdExt;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpClearTable
+ * Description   : Clears parameter table before reading it. This is to avoid MISRA non-initialized value errors.
+ */
+static void Qspi_Ip_SfdpClearTable(uint32 * paramTable, uint8 paramTableLength)
+{
+    uint8 count;
+    for (count = 0U; count < paramTableLength; count++)
+    {
+        paramTable[count] = 0U;
+    }
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpCheckNewerRevision
+ * Description   : Check SFDP Parameter Table revision is newer or not
+ */
+static inline boolean Qspi_Ip_SfdpCheckNewerRevision(uint8 paramIdLSB,
+                                                     uint8 tableType,
+                                                     uint8 majorRevision,
+                                                     uint8 minorRevision,
+                                                     sint16 minorRevisionMax
+                                                    )
+{
+    boolean retVal;
+
+    if ((paramIdLSB == (uint8)tableType) &&
+        (QSPI_IP_SFDP_MAJOR_REVISION == majorRevision) &&
+        ((sint16)minorRevision > minorRevisionMax))
+    {
+        retVal = TRUE;
+    }
+    else
+    {
+        retVal = FALSE;
+    }
+
+    return retVal;
+}
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpFindTable
+ * Description   : Finds requested parameters table in SFDP table, if it exists.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_SfdpFindTable(uint32 instance, uint32 baseAddress, Qspi_Ip_SfdpTables tableType, uint32 * paramTable, uint8 * paramTableLength)
+{
+    Qspi_Ip_StatusType status;
+    uint8 data[8U];
+    uint8 paramHeaders = 0U;
+    uint8 majorRevision;
+    uint8 minorRevision;
+    sint16 minorRevisionMax = -1;
+    uint8 paramIdLSB;
+    uint32 currAddr;
+    uint32 paramTableBaseAddr = 0U;
+    uint8 tableLength;
+    uint8 tableLengthMax = 0U;
+    boolean minorVerFlag = FALSE;
+
+    Qspi_Ip_SfdpClearTable(paramTable, *paramTableLength);
+    /* read second part of SFDP header to check version and get number of parameter headers */
+    status = Qspi_Ip_IpRead(instance, QSPI_IP_COMMAND_LUT, baseAddress + 4U, data, NULL_PTR, 4U);
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* check SFDP revision; minor revision can be greater than expected, because backward compatibility is guaranteed */
+        majorRevision = data[1];
+        minorRevision = data[0];
+        paramHeaders = (uint8)(data[2] + 1U);
+        minorVerFlag = Qspi_Ip_SfdpCheckMinorRevision(minorRevision);
+        if ( (QSPI_IP_SFDP_MAJOR_REVISION != majorRevision) || (TRUE != minorVerFlag) )
+        {
+            paramHeaders = 0U;
+            status = STATUS_QSPI_IP_ERROR;
+        }
+    }
+
+    /* If paramHeaders is greater than zero means the SFDP revision is correct */
+    /* iterate through parameter headers */
+    currAddr = 8U;
+    for (; paramHeaders > (uint8)0U; paramHeaders--)
+    {
+        /* read current parameter header */
+        status = Qspi_Ip_IpRead(instance, QSPI_IP_COMMAND_LUT, baseAddress + currAddr, data, NULL_PTR, 8U);
+        if (status != STATUS_QSPI_IP_SUCCESS)
+        {
+            break;
+        }
+        majorRevision = data[2];
+        minorRevision = data[1];
+        paramIdLSB = data[0];
+        tableLength = data[3];
+        if (TRUE == Qspi_Ip_SfdpCheckNewerRevision(paramIdLSB, (uint8)tableType, majorRevision, minorRevision, minorRevisionMax))
+        {
+            /* Found SFDP Basic Parameter Table with newer revision */
+            paramTableBaseAddr = baseAddress + (((uint32)data[6U] << 16U) | ((uint32)data[5U] << 8U) | ((uint8)data[4U]));
+            minorRevisionMax = (sint16)minorRevision;
+            tableLengthMax = tableLength;
+        }
+        currAddr += 8U;
+    }
+
+    /* If minorRevisionMax is not negative, it means that a SFDP table was found */
+    if (minorRevisionMax >= 0)
+    {
+        /* Adjust table length in case of newer revisions */
+        if (tableLengthMax > *paramTableLength)
+        {
+            tableLengthMax = *paramTableLength;
+        }
+        /* Read parameter table */
+        status = Qspi_Ip_IpRead(instance, QSPI_IP_COMMAND_LUT, paramTableBaseAddr, (uint8 *)paramTable, NULL_PTR, (uint32)tableLengthMax * 4U);
+        if (STATUS_QSPI_IP_SUCCESS == status)
+        {
+            *paramTableLength = tableLengthMax;
+        }
+    }
+    else
+    {
+        /* Could not find a table of the requested kind */
+        *paramTableLength = 0U;
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpReadTables
+ * Description   : Finds requested parameters table in SFDP table, if it exists.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_SfdpReadTables(uint32 instance, uint32 baseAddress, Qspi_Ip_SfdpTablesContainer *sfdpTables)
+{
+    Qspi_Ip_StatusType status;
+
+    /* Initialize each table length to max specified by JESD216 rev. D */
+    sfdpTables->paramTableLength_basic = QSPI_IP_TABLE_SIZE_BASIC;
+    sfdpTables->paramTableLength_4badd = QSPI_IP_TABLE_SIZE_4BADD;
+    sfdpTables->paramTableLength_xspi1 = QSPI_IP_TABLE_SIZE_XSPI1;
+    sfdpTables->paramTableLength_srmap = QSPI_IP_TABLE_SIZE_SRMAP;
+    sfdpTables->paramTableLength_2dopi = QSPI_IP_TABLE_SIZE_2DOPI;
+
+    /* Search Basic Flash Parameter Table */
+    status = Qspi_Ip_SfdpFindTable(instance, baseAddress, QSPI_IP_SFDP_TABLE_BASIC,
+                                   sfdpTables->paramTable_basic, &(sfdpTables->paramTableLength_basic));
+    if ((status != STATUS_QSPI_IP_SUCCESS) || (sfdpTables->paramTableLength_basic == 0U))
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Search 4-byte Address Instruction Table */
+        status = Qspi_Ip_SfdpFindTable(instance, baseAddress, QSPI_IP_SFDP_TABLE_4BADD,
+                                       sfdpTables->paramTable_4badd, &(sfdpTables->paramTableLength_4badd));
+    }
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Search eXtended Serial Peripheral Interface (xSPI) Profile 1.0 Table */
+        status = Qspi_Ip_SfdpFindTable(instance, baseAddress, QSPI_IP_SFDP_TABLE_XSPI1,
+                                       sfdpTables->paramTable_xspi1, &(sfdpTables->paramTableLength_xspi1));
+    }
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Search Status, Control and Configuration Register Map Table */
+        status = Qspi_Ip_SfdpFindTable(instance, baseAddress, QSPI_IP_SFDP_TABLE_SRMAP,
+                                       sfdpTables->paramTable_srmap, &(sfdpTables->paramTableLength_srmap));
+    }
+
+    if (STATUS_QSPI_IP_SUCCESS == status)
+    {
+        /* Command Sequences to change to DOPI (8D-8D-8D) mode */
+        status = Qspi_Ip_SfdpFindTable(instance, baseAddress, QSPI_IP_SFDP_TABLE_2DOPI,
+                                       sfdpTables->paramTable_2dopi, &(sfdpTables->paramTableLength_2dopi));
+    }
+
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpInitSimpleCmd
+ * Description   : Builds an initial operation containing a simple command.
+ */
+static void Qspi_Ip_SfdpInitSimpleCmd(uint8 cmd, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    Qspi_Ip_InitOperationType *operation;
+
+    if (initOpCount >= pConfig->initConfiguration.opCount)
+    {
+        /* operations list not big enough */
+        overflow = TRUE;
+    }
+    else
+    {
+        operation = &(pConfig->initConfiguration.operations[initOpCount]);
+        initOpCount++;
+        /* Build operation */
+        operation->opType = QSPI_IP_OP_TYPE_CMD;
+        operation->command1Lut = lutCount;
+        operation->addr = 0U;
+        /* Build LUT sequence */
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, cmd));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        /* Other operation fields are unused */
+        operation->command2Lut = QSPI_IP_LUT_INVALID;
+        operation->weLut = QSPI_IP_LUT_INVALID;
+        operation->size  = 0U;
+        operation->shift = 0U;
+        operation->width = 0U;
+        operation->value = 0U;
+        operation->ctrlCfgPtr = NULL_PTR;
+    }
+
+    return;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetWeSrInstr
+ * Description   : Returns instruction for write enable on SR register.
+ */
+static uint8 Qspi_Ip_SfdpGetWeSrInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables)
+{
+    uint8 wrEnSr;
+
+    /* Check "Write Enable Instruction Select for Writing to Volatile Status Register" bitfield */
+    wrEnSr = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_WREN_SR_DWORD,
+                                              QSPI_IP_SFDP_BASIC_WREN_SR_SHIFT, QSPI_IP_SFDP_BASIC_WREN_SR_WIDTH, 0x1U);
+    if (wrEnSr == 1U)
+    {
+        wrEnSr = 0x50U;
+    }
+    else
+    {
+        wrEnSr = 0x06U;
+    }
+    return wrEnSr;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpInitWriteReg
+ * Description   : Builds an initial operation containing a register write command.
+ */
+static void Qspi_Ip_SfdpInitWriteReg(uint8 cmd, uint8 wrenCmd, uint8 size, uint32 value, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    Qspi_Ip_InitOperationType *operation;
+
+    if (initOpCount >= pConfig->initConfiguration.opCount)
+    {
+        /* operations list not big enough */
+        overflow = TRUE;
+    }
+    else
+    {
+        operation = &(pConfig->initConfiguration.operations[initOpCount]);
+        initOpCount++;
+        /* Build operation */
+        operation->opType = QSPI_IP_OP_TYPE_WRITE_REG;
+        operation->addr = 0U;
+        operation->weLut = lutCount;
+        operation->size = size;
+        operation->value = value;
+        /* Build WE LUT sequence */
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, wrenCmd));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        operation->command1Lut = lutCount;
+        /* Build write SR LUT sequence */
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, cmd));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_1, 0x1U));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+        /* Other operation fields are unused */
+        operation->command2Lut = QSPI_IP_LUT_INVALID;
+        operation->shift = 0U;
+        operation->width = 0U;
+        operation->ctrlCfgPtr = NULL_PTR;
+    }
+
+    return;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp4byteAddrSwitch_01
+ * Description   : Switch to 4-byte addressing mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_01(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* issue instruction B7h (preceding write enable not required) */
+    Qspi_Ip_SfdpInitSimpleCmd(0xB7U, pConfig);
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp4byteAddrSwitch_02
+ * Description   : Switch to 4-byte addressing mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_02(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* issue write enable instruction 06h, then issue instruction B7h */
+    Qspi_Ip_SfdpInitSimpleCmd(0x06U, pConfig);
+    Qspi_Ip_SfdpInitSimpleCmd(0xB7U, pConfig);
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp4byteAddrSwitch_08
+ * Description   : Switch to 4-byte addressing mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_08(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is used to enable/disable 4-byte address mode.
+       When MSB is set to ‘1’, 4-byte address mode is active and A[30:24] bits are don’t care. Read with instruction 16h.
+       Write instruction is 17h with 1 byte of data. When MSB is cleared to ‘0’, select the active 128 Mbit segment by setting
+       the appropriate A[30:24] bits and use 3-Byte addressing */
+    /* Not implemented */
+    (void)pConfig;
+    return STATUS_QSPI_IP_ERROR;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp4byteAddrSwitch_16
+ * Description   : Switch to 4-byte addressing mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch_16(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* A 16-bit nonvolatile configuration register controls 3-Byte/4-Byte address mode. Read instruction is B5h.
+       Bit[0] controls address mode [0=3-Byte; 1=4-Byte]. Write configuration register instruction is B1h, data length is 2 bytes */
+    /* Not implemented */
+    (void)pConfig;
+    return STATUS_QSPI_IP_ERROR;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp4byteAddrSwitch
+ * Description   : Switch to 4-byte addressing mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp4byteAddrSwitch(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint8 addrSwitch;
+
+    /* Check 4-byte addr enable mode */
+    addrSwitch = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_ADDR_SWITCH_DWORD,
+                                                  QSPI_IP_SFDP_BASIC_ADDR_SWITCH_SHIFT, QSPI_IP_SFDP_BASIC_ADDR_SWITCH_WIDTH, 0x0U);
+    if ((addrSwitch & 0x01U) != 0U)
+    {
+        /* issue instruction B7h (preceding write enable not required) */
+        status = Qspi_Ip_Sfdp4byteAddrSwitch_01(pConfig);
+    }
+    else if ((addrSwitch & 0x02U) != 0U)
+    {
+        /* issue write enable instruction 06h, then issue instruction B7h */
+        status = Qspi_Ip_Sfdp4byteAddrSwitch_02(pConfig);
+    }
+    else if ((addrSwitch & 0x08U) != 0U)
+    {
+        /* 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is used to enable/disable 4-byte address mode */
+        status = Qspi_Ip_Sfdp4byteAddrSwitch_08(pConfig);
+    }
+    else if ((addrSwitch & 0x16U) != 0U)
+    {
+        /* A 16-bit nonvolatile configuration register controls 3-Byte/4-Byte address mode. */
+        status = Qspi_Ip_Sfdp4byteAddrSwitch_16(pConfig);
+    }
+    else
+    {
+        /* Can't switch to 4-byte addr. mode */
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicAddrBits
+ * Description   : Returns number of address bits.
+ */
+static void Qspi_Ip_SfdpGetBasicAddrBits(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 addrBytes;
+    Qspi_Ip_StatusType status;
+
+    /* Check number of address bytes */
+    addrBytes = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_ADDR_BYTES_DWORD,
+                                                 QSPI_IP_SFDP_BASIC_ADDR_BYTES_SHIFT, QSPI_IP_SFDP_BASIC_ADDR_BYTES_WIDTH, 0x0U);
+    switch (addrBytes)
+    {
+        case 0U:
+            /* 3-Byte only addressing */
+            basicAddrBits = 24U;
+            break;
+        case 1U:
+            /* 3 or 4 byte addressing, try to switch to 4 */
+            status = Qspi_Ip_Sfdp4byteAddrSwitch(sfdpTables, pConfig);
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                basicAddrBits = 32U;
+            }
+            else
+            {
+                basicAddrBits = 24U;
+            }
+            break;
+        case 2U:
+            /* 4-Byte only addressing */
+            basicAddrBits = 32U;
+            break;
+        default:
+            /* reseved, should not happen, default to 3-byte */
+            basicAddrBits = 24U;
+            break;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigureQE
+ * Description   : Adds initial operation to set QE bit, if required.
+ */
+static void Qspi_Ip_SfdpConfigureQE(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 qeReq;
+    uint8 wrenCmd;
+
+    /* Check "Quad Enable Requirements (QER)" field */
+    qeReq = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_QE_REQ_DWORD,
+                                             QSPI_IP_SFDP_BASIC_QE_REQ_SHIFT, QSPI_IP_SFDP_BASIC_QE_REQ_WIDTH, 0x7U);
+    wrenCmd = Qspi_Ip_SfdpGetWeSrInstr(sfdpTables);
+    switch (qeReq)
+    {
+        case 0U:
+            /* Device does not have a QE bit. */
+            break;
+        case 1U:
+            /* QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via
+               Write Status with two data bytes where bit 1 of the second byte is zero. Writing only one byte to the status register has the side-effect
+               of clearing status register 2, including the QE bit */
+            Qspi_Ip_SfdpInitWriteReg(0x01U, wrenCmd, 2U, 0x0002U, pConfig);
+            break;
+        case 2U:
+            /* QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is one.
+               It is cleared via Write Status with one data byte where bit 6 is zero. */
+            Qspi_Ip_SfdpInitWriteReg(0x01U, wrenCmd, 1U, 0x40U, pConfig);
+            break;
+        case 3U:
+            /* QE is bit 7 of status register 2. It is set via Write status register 2 instruction 3Eh with one data byte where bit 7 is one.
+               It is cleared via Write status register 2 instruction 3Eh with one data byte where bit 7 is zero. The status register 2 is read using instruction 3Fh. */
+            Qspi_Ip_SfdpInitWriteReg(0x3EU, wrenCmd, 1U, 0x80U, pConfig);
+            break;
+        case 4U:
+            /* QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via
+               Write Status with two data bytes where bit 1 of the second byte is zero. In contrast to the 001b code, writing one byte to the status
+               register does not modify status register 2. */
+            Qspi_Ip_SfdpInitWriteReg(0x01U, wrenCmd, 2U, 0x0002U, pConfig);
+            break;
+        case 5U:
+            /* QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h.
+               QE is set via Write Status instruction 01h with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with
+               two data bytes where bit 1 of the second byte is zero. */
+            Qspi_Ip_SfdpInitWriteReg(0x01U, wrenCmd, 2U, 0x0002U, pConfig);
+            break;
+        case 6U:
+            /* QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction
+               35h, and status register 3 is read using instruction 15h. QE is set via Write Status Register instruction 31h with one data byte where
+               bit 1 is one. It is cleared via Write Status Register instruction 31h with one data byte where bit 1 is zero. */
+            Qspi_Ip_SfdpInitWriteReg(0x31U, wrenCmd, 1U, 0x02U, pConfig);
+            break;
+        default:
+            /* Unknown QE bit setting procedure or table too short, disable quad commands */
+            quadAvailable = FALSE;
+            break;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetModeInstr
+ * Description   : Returns MODE instructions to use for read commands.
+ */
+static Qspi_Ip_LutCommandsType Qspi_Ip_SfdpGetModeInstr(uint8 modeClocks, Qspi_Ip_LutPadsType addrPads)
+{
+    uint8 modeBits;
+    Qspi_Ip_LutCommandsType mode = QSPI_IP_LUT_INSTR_MODE;
+
+    /* compute the number of mode bits from pads and mode clocks */
+    modeBits = modeClocks * (1U << (uint8)((uint32)addrPads >> 8U));
+    switch (modeBits)
+    {
+        case 2U:
+            mode = QSPI_IP_LUT_INSTR_MODE2;
+            break;
+        case 4U:
+            mode = QSPI_IP_LUT_INSTR_MODE4;
+            break;
+        case 8U:
+            mode = QSPI_IP_LUT_INSTR_MODE;
+            break;
+        default:
+            /* unsupported mode */
+            break;
+    }
+    return mode;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetSpiReadInstr
+ * Description   : Returns instructions for read type <cnt>.
+ */
+static void Qspi_Ip_SfdpGetSpiReadInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt, uint8 *instruction, uint8 *addrBits)
+{
+    uint8 sup4badd;
+
+    /* Check 4-byte instr. support */
+    sup4badd = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, read4ByteSupDword[cnt],
+                                                read4ByteSupShift[cnt], QSPI_IP_SFDP_4BADD_INSTR_SUP_WIDTH, 0x0U);
+    if (sup4badd == 1U)
+    {
+        /* Use 4-byte address instruction specified in SFDP standard */
+        *instruction = read4ByteInst[cnt];
+        *addrBits = 32U;
+    }
+    else
+    {
+        /* Get instruction from basic parameters table */
+        *instruction = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, readInstDword[cnt],
+                                                        readInstShift[cnt], readInstWidth[cnt], 0x0U);
+        *addrBits = basicAddrBits;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigBasicRead
+ * Description   : Configures basic 1-1-1 read.
+ */
+static void Qspi_Ip_SfdpConfigBasicRead(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 addrBits;
+    uint8 instruction;
+
+    /* Check 4-byte instr. support */
+    addrBits = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, QSPI_IP_SFDP_4BADD_INSTR_SUP_DWORD,
+                                                QSPI_IP_SFDP_4BADD_READ111_SUP_SHIFT, QSPI_IP_SFDP_4BADD_INSTR_SUP_WIDTH, 0x0U);
+    if (addrBits == 0U)
+    {
+        instruction = QSPI_IP_CMD_BASIC_READ;
+        addrBits = basicAddrBits;
+    }
+    else
+    {
+        instruction = QSPI_IP_CMD_BASIC_READ_4B;
+        addrBits = 32U;
+    }
+    /* Build LUT */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, addrBits));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 0x10U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp444Switch
+ * Description   : Add commands to switch to 4-4-4 mode in operations list
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_01(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+        /* 01: set QE per QER description above, then issue instruction 38h */
+        /* 02: issue instruction 38h */
+    Qspi_Ip_SfdpInitSimpleCmd(0x38U, pConfig);
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp444Switch
+ * Description   : Add commands to switch to 4-4-4 mode in operations list
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_04(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+        /* issue instruction 35h */
+    Qspi_Ip_SfdpInitSimpleCmd(0x35U, pConfig);
+    return STATUS_QSPI_IP_SUCCESS;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp444Switch
+ * Description   : Add commands to switch to 4-4-4 mode in operations list
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_08(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+        /* device uses a read-modify-write sequence of operations: read configuration using instruction 65h followed by address 800003h, set bit 6,
+           write configuration using instruction 71h followed by address 800003h. This configuration is volatile. */
+    /* Not implemented */
+    (void)pConfig;
+    return STATUS_QSPI_IP_ERROR;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp444Switch
+ * Description   : Add commands to switch to 4-4-4 mode in operations list
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch_16(const Qspi_Ip_MemoryConfigType * pConfig)
+{
+        /* Device uses a read-modify-write sequence of operations: Read Volatile Enhanced Configuration Register using instruction 65h,
+           no address is required, reset bit 7 to 0. Write Volatile Enhanced Configuration Register using instruction 61h,
+           no address is required. This configuration is volatile. */
+    /* Not implemented */
+    (void)pConfig;
+    return STATUS_QSPI_IP_ERROR;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_Sfdp444Switch
+ * Description   : Add commands to switch to 4-4-4 mode in operations list
+ */
+static Qspi_Ip_StatusType Qspi_Ip_Sfdp444Switch(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 quadSwitch;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    /* Check 4-4-4 mode enable sequences */
+    quadSwitch = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_444_SWITCH_DWORD,
+                                                  QSPI_IP_SFDP_BASIC_444_SWITCH_SHIFT, QSPI_IP_SFDP_BASIC_444_SWITCH_WIDTH, 0x0U);
+    if ((quadSwitch & 0x3U) != 0U)
+    {
+        /* 01: set QE per QER description above, then issue instruction 38h */
+        /* 02: issue instruction 38h */
+        status = Qspi_Ip_Sfdp444Switch_01(pConfig);
+    }
+    else if ((quadSwitch & 0x4U) != 0U)
+    {
+        /* issue instruction 35h */
+        status = Qspi_Ip_Sfdp444Switch_04(pConfig);
+    }
+    else if ((quadSwitch & 0x8U) != 0U)
+    {   /* device uses a read-modify-write sequence of operations */
+        status = Qspi_Ip_Sfdp444Switch_08(pConfig);
+    }
+    else if ((quadSwitch & 0x16U) != 0U)
+    {   /* device uses a read-modify-write sequence of operations */
+        status = Qspi_Ip_Sfdp444Switch_16(pConfig);
+    }
+    else
+    {
+        /* can't do the switch to 4-4-4 mode */
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicReadInfo
+ * Description   : Builds configuration for basic (SPI) read.
+ */
+static void Qspi_Ip_SfdpGetBasicReadInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 supported = 0U;
+    uint8 crtMode;
+    uint8 modeClocks;
+    uint8 dummyClocks;
+    Qspi_Ip_LutPadsType instPads;
+    Qspi_Ip_LutPadsType addrPads;
+    Qspi_Ip_LutPadsType dataPads;
+    uint8 addrBits;
+    uint8 instruction;
+    Qspi_Ip_LutCommandsType modeInstr;
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    /* Find the best supported fast read mode */
+    /* Check if read mode is supported */
+    for (crtMode = (uint8)QSPI_IP_SFDP_READ_MODE_MAX; crtMode > 0U; crtMode-- )
+    {
+        modeIndex = (uint8)(crtMode - 1U);
+        if ((QSPI_IP_LUT_PADS_4 == readModeDataPads[modeIndex]) && (FALSE == quadAvailable))
+        {
+            /* Quad mode not available ignore quad commands */
+            continue;
+        }
+        supported = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, readSupDword[modeIndex],
+                                                     readSupShift[modeIndex], readSupWitdh[modeIndex], 0x0U);
+        if (supported != 0U)
+        {
+            if ((uint8)QSPI_IP_SFDP_READ_MODE_444 == modeIndex)
+            {
+                /* 4-4-4 read mode, add commands to switch to this mode in operation list */
+                status = Qspi_Ip_Sfdp444Switch(sfdpTables, pConfig);
+                /* Will use 4 cmd pads for all commands */
+                cmdPads = QSPI_IP_LUT_PADS_4;
+            }
+            else
+            {
+                status = STATUS_QSPI_IP_SUCCESS;
+                cmdPads = QSPI_IP_LUT_PADS_1;
+            }
+            if (STATUS_QSPI_IP_SUCCESS == status)
+            {
+                /* Get read instruction */
+                Qspi_Ip_SfdpGetSpiReadInstr(sfdpTables, modeIndex, &instruction, &addrBits);
+                /* Get mode and dummy clocks */
+                modeClocks = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, readModeDword[modeIndex],
+                                                              readModeShift[modeIndex], readModeWidth[modeIndex], 0x0U);
+                dummyClocks = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, readDummyDword[modeIndex],
+                                                               readDummyShift[modeIndex], readDummyWidth[modeIndex], 0x0U);
+                /* Get other command parameters */
+                instPads = readModeInstPads[modeIndex];
+                addrPads = readModeAddrPads[modeIndex];
+                dataPads = readModeDataPads[modeIndex];
+                /* Build LUT */
+                pConfig->readLut = lutCount;
+                Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, instPads, instruction));
+                Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR, addrPads, addrBits));
+                if (modeClocks > 0U)
+                {
+                    modeInstr = Qspi_Ip_SfdpGetModeInstr(modeClocks, addrPads);
+                    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(modeInstr, addrPads, 0x0U));
+                }
+                if (dummyClocks > 0U)
+                {
+                    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_DUMMY, addrPads, dummyClocks));
+                }
+                Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ, dataPads, 0x10U));
+                Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+                /* Found read command, exit loop */
+                break;
+            }
+        }
+    }
+
+    if (supported == 0U)
+    {
+        /* No supported fast read mode found, use default */
+        Qspi_Ip_SfdpConfigBasicRead(sfdpTables, pConfig);
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicWriteInfo
+ * Description   : Builds configuration for basic (SPI) write
+ */
+static void Qspi_Ip_SfdpGetBasicWriteInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 supported;
+    Qspi_Ip_LutPadsType instPads;
+    Qspi_Ip_LutPadsType addrPads;
+    Qspi_Ip_LutPadsType dataPads;
+    uint8 addrBits;
+    uint8 instruction;
+
+    /* check if 4-byte write corresponding to the current read mode is supported */
+    supported = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, write4ByteSupDword[modeIndex],
+                                                 write4ByteSupShift[modeIndex], QSPI_IP_SFDP_4BADD_INSTR_SUP_DWORD, 0x0);
+    if (supported == 1U)
+    {
+        addrBits = 32U;
+        instruction = write4ByteInst[modeIndex];
+        instPads = readModeInstPads[modeIndex];
+        addrPads = readModeAddrPads[modeIndex];
+        dataPads = readModeDataPads[modeIndex];
+    }
+    else
+    {
+        /* No 4-byte write support, use basic write since SFDP does not specify other write modes */
+        addrBits = basicAddrBits;
+        instruction = QSPI_IP_CMD_BASIC_WRITE;
+        instPads = cmdPads;
+        addrPads = cmdPads;
+        dataPads = cmdPads;
+    }
+    /* Get LUT index */
+    pConfig->writeLut = lutCount;
+    /* Build LUT */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, instPads, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR, addrPads, addrBits));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_WRITE, dataPads, 0x10U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1ReadInfo
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static void Qspi_Ip_SfdpGetXspi1ReadInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 readInst;
+    uint8 cmdExt;
+    uint8 dummy;
+
+    /* Get fast read instruction */
+    readInst = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_READ_FAST_DWORD,
+                                                QSPI_IP_SFDP_XSPI1_READ_FAST_SHIFT, QSPI_IP_SFDP_XSPI1_READ_FAST_WIDTH, 0xEEU);
+    /* Get Command Extension */
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, readInst);
+    /* Get Dummy cycles */
+    dummy = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_DUMMY_DWORD,
+                                             QSPI_IP_SFDP_XSPI1_DUMMY_SHIFT, QSPI_IP_SFDP_XSPI1_DUMMY_WIDTH, 20U);
+
+    /* Get LUT index */
+    pConfig->readLut = lutCount;
+    /* Build LUT command */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, readInst));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR_DDR, QSPI_IP_LUT_PADS_8, (uint8)32U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_8, dummy));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ_DDR, QSPI_IP_LUT_PADS_8, 0x10U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1WriteInfo
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static void Qspi_Ip_SfdpGetXspi1WriteInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 writeInst;
+    uint8 cmdExt;
+
+    /* Page program instruction - not in SFDP table */
+    writeInst = QSPI_IP_CMD_XSPI_WRITE;
+    /* Get Command Extension */
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, writeInst);
+
+    /* Get LUT index */
+    pConfig->writeLut = lutCount;
+    /* Build LUT command */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, writeInst));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR_DDR, QSPI_IP_LUT_PADS_8, (uint8)32U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_WRITE_DDR, QSPI_IP_LUT_PADS_8, 0x10U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicEraseInstr
+ * Description   : Returns instructions for erase type <cnt>.
+ */
+static uint8 Qspi_Ip_SfdpGetBasicEraseInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt, uint8 *addrbits)
+{
+    uint8 addr4;
+    uint8 eraseInst;
+
+    /* Check 4-byte instr. support */
+    addr4 = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, QSPI_IP_SFDP_4BADD_INSTR_SUP_DWORD,
+                                             erase4ByteSupShift[cnt], QSPI_IP_SFDP_4BADD_INSTR_SUP_WIDTH, 0x0U);
+    if (addr4 == 1U)
+    {
+        /* Get erase instruction from 4-byte address instructions table */
+        eraseInst = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, QSPI_IP_SFDP_4BADD_ERASE_INST_DWORD,
+                                                     erase4ByteInstShift[cnt], QSPI_IP_SFDP_4BADD_ERASE_INST_WIDTH, 0x0U);
+        *addrbits = 32U;
+    }
+    else
+    {
+        /* Get erase instruction from basic parameters table */
+        eraseInst = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, eraseInstDword[cnt],
+                                                     eraseInstShift[cnt], eraseInstWidth[cnt], 0x0U);
+        *addrbits = basicAddrBits;
+    }
+    return eraseInst;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1EraseInstr
+ * Description   : Returns instructions for erase type <cnt>.
+ */
+static uint8 Qspi_Ip_SfdpGetXspi1EraseInstr(const Qspi_Ip_SfdpTablesContainer *sfdpTables, uint8 cnt)
+{
+    uint8 addr4;
+    uint8 eraseInst;
+
+    /* Check 4-byte instr. support */
+    addr4 = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, QSPI_IP_SFDP_4BADD_INSTR_SUP_DWORD,
+                                             erase4ByteSupShift[cnt], QSPI_IP_SFDP_4BADD_INSTR_SUP_WIDTH, 0x0U);
+    if (addr4 == 1U)
+    {
+        /* Get erase instruction from 4-byte address instructions table */
+        eraseInst = (uint8)Qspi_Ip_SfdpGet4BAddParam(sfdpTables, QSPI_IP_SFDP_4BADD_ERASE_INST_DWORD,
+                                                     erase4ByteInstShift[cnt], QSPI_IP_SFDP_4BADD_ERASE_INST_WIDTH, 0x0U);
+    }
+    else
+    {
+        /* Get erase instruction from basic parameters table */
+        eraseInst = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, eraseInstDword[cnt],
+                                                     eraseInstShift[cnt], eraseInstWidth[cnt], 0x0U);
+    }
+    return eraseInst;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicEraseInfo
+ * Description   : Builds configuration for SPI mode.
+ */
+static void Qspi_Ip_SfdpGetBasicEraseInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 eraseInst;
+    uint8 eraseSize;
+    uint8 addrbits;
+    uint8 cnt;
+
+    /* Loop through the 4 possible erase types */
+    for (cnt = 0U; cnt < 4U; cnt++)
+    {
+        /* Get erase size */
+        eraseSize = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, eraseSizeDword[cnt],
+                                                     eraseSizeShift[cnt], eraseSizeWidth[cnt], 0x0U);
+        pConfig->eraseSettings.eraseTypes[cnt].size = eraseSize;
+        if (eraseSize > 0U)
+        {
+            /* Get erase instruction */
+            eraseInst = Qspi_Ip_SfdpGetBasicEraseInstr(sfdpTables, cnt, &addrbits);
+            /* Get LUT index */
+            pConfig->eraseSettings.eraseTypes[cnt].eraseLut = lutCount;
+            /* Build LUT command */
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, eraseInst));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR, cmdPads, (uint8)addrbits));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        }
+        else
+        {
+            /* Erase type not supported */
+            pConfig->eraseSettings.eraseTypes[cnt].eraseLut = QSPI_IP_LUT_INVALID;
+        }
+    }
+
+    /* Chip erase */
+    eraseInst = QSPI_IP_CMD_BASIC_CHIP_ERASE;
+    pConfig->eraseSettings.chipEraseLut = lutCount;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, eraseInst));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1EraseInfo
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static void Qspi_Ip_SfdpGetXspi1EraseInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 eraseInst;
+    uint8 eraseSize;
+    uint8 eraseExt;
+    uint8 cnt;
+
+    /* Loop through the 4 possible erase types */
+    for (cnt = 0U; cnt < 4U; cnt++)
+    {
+        /* Get erase size */
+        eraseSize = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, eraseSizeDword[cnt],
+                                                     eraseSizeShift[cnt], eraseSizeWidth[cnt], 0x0U);
+        pConfig->eraseSettings.eraseTypes[cnt].size = eraseSize;
+        if (eraseSize > 0U)
+        {
+            /* Get erase instruction */
+            eraseInst = Qspi_Ip_SfdpGetXspi1EraseInstr(sfdpTables, cnt);
+            eraseExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, eraseInst);
+            /* Get LUT index */
+            pConfig->eraseSettings.eraseTypes[cnt].eraseLut = lutCount;
+            /* Build LUT command */
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, eraseInst));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, eraseExt));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_ADDR_DDR, QSPI_IP_LUT_PADS_8, (uint8)32U));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        }
+        else
+        {
+            /* Erase type not supported */
+            pConfig->eraseSettings.eraseTypes[cnt].eraseLut = QSPI_IP_LUT_INVALID;
+        }
+    }
+
+    /* Check chip erase support */
+    eraseInst = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_CHIP_ERASE_DWORD,
+                                                 QSPI_IP_SFDP_XSPI1_CHIP_ERASE_SHIFT, QSPI_IP_SFDP_XSPI1_CHIP_ERASE_WIDTH, 0x0U);
+    if (eraseInst == 0U)
+    {
+        pConfig->eraseSettings.chipEraseLut = QSPI_IP_LUT_INVALID;
+    }
+    else
+    {
+        pConfig->eraseSettings.chipEraseLut = lutCount;
+        /* Build LUT command */
+        eraseInst = QSPI_IP_CMD_XSPI_CHIP_ERASE;
+        eraseExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, eraseInst);
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, eraseInst));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, eraseExt));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicStatusInfo
+ * Description   : Builds configuration for SPI mode.
+ */
+static void Qspi_Ip_SfdpGetBasicStatusInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 instruction;
+    Qspi_Ip_StatusConfigType *statusConfig;
+
+    statusConfig = &(pConfig->statusConfig);
+
+    statusConfig->regSize = 1U;
+    statusConfig->blockProtectionOffset = 0U;
+    statusConfig->blockProtectionWidth = 0U;
+    statusConfig->blockProtectionValue = 0U;
+    statusConfig->busyOffset = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WIP_OFFSET_DWORD,
+                                                                QSPI_IP_SFDP_SRMAP_WIP_OFFSET_SHIFT, QSPI_IP_SFDP_SRMAP_WIP_OFFSET_WIDTH, 0x0U);
+    /* Busy bit meaning is reversed (0: Positive (WIP=1 means write is in progress); 1: Inverted (WIP=0 means write is in progress) */
+    statusConfig->busyValue = (uint8)(1U - Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WIP_VALUE_DWORD,
+                                                                     QSPI_IP_SFDP_SRMAP_WIP_VALUE_SHIFT, QSPI_IP_SFDP_SRMAP_WIP_VALUE_WIDTH, 0x0U));
+    statusConfig->writeEnableOffset = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WEL_OFFSET_DWORD,
+                                                                       QSPI_IP_SFDP_SRMAP_WEL_OFFSET_SHIFT, QSPI_IP_SFDP_SRMAP_WEL_OFFSET_WIDTH, 0x1U);
+    /* Build LUT sequence for initial read status reg. */
+    statusConfig->statusRegInitReadLut = lutCount;
+    instruction = QSPI_IP_CMD_BASIC_READ_SR;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 0x1U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Build LUT sequence for read status reg. */
+    if (QSPI_IP_LUT_PADS_1 == cmdPads)
+    {
+        /* Use same sequence */
+        statusConfig->statusRegReadLut = statusConfig->statusRegInitReadLut;
+    }
+    else
+    {
+        statusConfig->statusRegReadLut = lutCount;
+        instruction = QSPI_IP_CMD_BASIC_READ_SR;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ, cmdPads, 0x10));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+
+    /* Build LUT sequence for write status reg. */
+    statusConfig->statusRegWriteLut = lutCount;
+    instruction = QSPI_IP_CMD_BASIC_WRITE_SR;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_WRITE, cmdPads, 0x1U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+    /* Build LUT sequence for write enable */
+    statusConfig->writeEnableLut = lutCount;
+    instruction = QSPI_IP_CMD_BASIC_WRITE_ENABLE;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+    /* Build LUT sequence for SR write enable */
+    instruction = Qspi_Ip_SfdpGetWeSrInstr(sfdpTables);
+    if (QSPI_IP_CMD_BASIC_WRITE_ENABLE == instruction)
+    {
+        statusConfig->writeEnableSRLut = statusConfig->writeEnableLut;
+    }
+    else
+    {
+        statusConfig->writeEnableSRLut = lutCount;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1StatusInfo
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static void Qspi_Ip_SfdpGetXspi1StatusInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 instruction;
+    uint8 cmdExt;
+    uint8 dummy;
+    Qspi_Ip_StatusConfigType *statusConfig;
+
+    statusConfig = &(pConfig->statusConfig);
+
+    statusConfig->regSize = 1U;
+    statusConfig->blockProtectionOffset = 0U;
+    statusConfig->blockProtectionWidth = 0U;
+    statusConfig->blockProtectionValue = 0U;
+    statusConfig->busyOffset = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WIP_OFFSET_DWORD,
+                                                                QSPI_IP_SFDP_SRMAP_WIP_OFFSET_SHIFT, QSPI_IP_SFDP_SRMAP_WIP_OFFSET_WIDTH, 0x0U);
+    /* Busy bit meaning is reversed (0: Positive (WIP=1 means write is in progress); 1: Inverted (WIP=0 means write is in progress) */
+    statusConfig->busyValue = (uint8)(1U - Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WIP_VALUE_DWORD,
+                                                                     QSPI_IP_SFDP_SRMAP_WIP_VALUE_SHIFT, QSPI_IP_SFDP_SRMAP_WIP_VALUE_WIDTH, 0x0U));
+    statusConfig->writeEnableOffset = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_WEL_OFFSET_DWORD,
+                                                                       QSPI_IP_SFDP_SRMAP_WEL_OFFSET_SHIFT, QSPI_IP_SFDP_SRMAP_WEL_OFFSET_WIDTH, 0x1U);
+    /* Build LUT sequence for initial read status reg. */
+    statusConfig->statusRegInitReadLut = lutCount;
+    instruction = QSPI_IP_CMD_XSPI_READ_SR;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 0x1U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Build LUT sequence for read status reg. */
+    statusConfig->statusRegReadLut = lutCount;
+    instruction = QSPI_IP_CMD_XSPI_READ_SR;
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+    dummy = (uint8)Qspi_Ip_SfdpGetSRMapParam(sfdpTables, QSPI_IP_SFDP_SRMAP_DUMMY_8D_DWORD,
+                                             QSPI_IP_SFDP_SRMAP_DUMMY_8D_SHIFT, QSPI_IP_SFDP_SRMAP_DUMMY_8D_WIDTH, 0x0U);
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAddSrAddr(&(pConfig->lutSequences), sfdpTables);
+    if (dummy != 0U)
+    {
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_8, dummy));
+    }
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_READ_DDR, QSPI_IP_LUT_PADS_8, 0x10));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+    /* Build LUT sequence for write status reg. */
+    statusConfig->statusRegWriteLut = lutCount;
+    instruction = QSPI_IP_CMD_XSPI_WRITE_SR;
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAddSrAddr(&(pConfig->lutSequences), sfdpTables);
+    /* Use SDR write because reg. size is 1 */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_8, 0x2U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+    /* Build LUT sequence for write enable */
+    statusConfig->writeEnableSRLut = lutCount;
+    statusConfig->writeEnableLut = lutCount;
+    instruction = QSPI_IP_CMD_XSPI_WRITE_ENABLE;
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigReset1
+ * Description   : Configure reset settings - option 1.
+ */
+static void Qspi_Ip_SfdpConfigReset1(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    /* drive Fh on all 4 data wires for 8 clocks */
+    /* Not implemented */
+    (void)pConfig;
+    (void)resetSettings;
+    (void)pads;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigReset2
+ * Description   : Configure reset settings - option 2.
+ */
+static void Qspi_Ip_SfdpConfigReset2(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    /* drive Fh on all 4 data wires for 10 clocks if device is operating in 4-byte address mode */
+    /* Not implemented */
+    (void)pConfig;
+    (void)resetSettings;
+    (void)pads;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigReset4
+ * Description   : Configure reset settings - option 4.
+ */
+static void Qspi_Ip_SfdpConfigReset4(const Qspi_Ip_MemoryConfigType * pConfig, const Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    /* drive Fh on all 4 data wires for 16 clocks */
+    /* Not implemented */
+    (void)pConfig;
+    (void)resetSettings;
+    (void)pads;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigReset8
+ * Description   : Configure reset settings - option 8.
+ */
+static void Qspi_Ip_SfdpConfigReset8(const Qspi_Ip_MemoryConfigType * pConfig, Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    /* issue instruction F0h */
+    resetSettings->resetCmdLut = lutCount;
+    resetSettings->resetCmdCount = 1U;
+    /* Build LUT sequence */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, pads, 0xF0U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigReset16
+ * Description   : Configure reset settings - option 16.
+ */
+static void Qspi_Ip_SfdpConfigReset16(const Qspi_Ip_MemoryConfigType * pConfig, Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    /* issue reset enable instruction 66h, then issue reset instruction 99h.
+       The reset enable, reset sequence may be issued on 1, 2, 4, or 8 wires depending on the device operating mode. */
+    resetSettings->resetCmdLut = lutCount;
+    resetSettings->resetCmdCount = 2U;
+    /* 1st LUT sequence - 0x66 */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, pads, 0x66U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* 2nd LUT sequence - 0x99 */
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, pads, 0x99U));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicResetInfo
+ * Description   : Configure reset settings - XPI mode.
+ */
+static void Qspi_Ip_SfdpGetBasicResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, const Qspi_Ip_MemoryConfigType * pConfig,
+                                                        Qspi_Ip_ResetConfigType *resetSettings, Qspi_Ip_LutPadsType pads)
+{
+    uint8 resetOption;
+
+    resetOption = (uint8)Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_SW_RESET_DWORD,
+                                                   QSPI_IP_SFDP_BASIC_SW_RESET_SHIFT, QSPI_IP_SFDP_BASIC_SW_RESET_WIDTH, 0x0U);
+    if ((resetOption & 0x10U) != 0U)
+    {
+        /* issue reset enable instruction 66h, then issue reset instruction 99h.
+           The reset enable, reset sequence may be issued on 1, 2, 4, or 8 wires depending on the device operating mode. */
+        Qspi_Ip_SfdpConfigReset16(pConfig, resetSettings, pads);
+    }
+    else if ((resetOption & 0x8U) != 0U)
+    {
+        Qspi_Ip_SfdpConfigReset8(pConfig, resetSettings, pads);
+        /* issue instruction F0h */
+    }
+    else if ((resetOption & 0x1U) != 0U)
+    {
+        Qspi_Ip_SfdpConfigReset1(pConfig, resetSettings, pads);
+        /* drive Fh on all 4 data wires for 8 clocks */
+    }
+    else if ((resetOption & 0x2U) != 0U)
+    {
+        Qspi_Ip_SfdpConfigReset2(pConfig, resetSettings, pads);
+        /* drive Fh on all 4 data wires for 10 clocks if device is operating in 4-byte address mode */
+    }
+    else if ((resetOption & 0x4U) != 0U)
+    {
+        Qspi_Ip_SfdpConfigReset4(pConfig, resetSettings, pads);
+        /* drive Fh on all 4 data wires for 16 clocks */
+    }
+    else
+    {
+        /* unknown reset sequence */
+        resetSettings->resetCmdLut = QSPI_IP_LUT_INVALID;
+        resetSettings->resetCmdCount = 0U;
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1ResetInfo
+ * Description   : Configure reset settings - XPI mode.
+ */
+static void Qspi_Ip_SfdpGetXspi1ResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 rSup;
+    uint8 rEnSup;
+    uint8 instruction;
+    uint8 cmdExt;
+
+    pConfig->resetSettings.resetCmdLut = QSPI_IP_LUT_INVALID;
+    pConfig->resetSettings.resetCmdCount = 0U;
+
+    rEnSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_EN_DWORD,
+                                              QSPI_IP_SFDP_XSPI1_RESET_EN_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_EN_WIDTH, 0x0U);
+    rSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_DEF_DWORD,
+                                            QSPI_IP_SFDP_XSPI1_RESET_DEF_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_DEF_WIDTH, 0x0U);
+    if ((rEnSup == 1U) && (rSup == 1U))
+    {
+        /* 0x66, 0x99 reset sequence */
+        pConfig->resetSettings.resetCmdLut = lutCount;
+        pConfig->resetSettings.resetCmdCount = 2U;
+        instruction = QSPI_IP_CMD_XSPI_RESET_ENABLE;
+        cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+
+        instruction = QSPI_IP_CMD_XSPI_RESET_DEF;
+        cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+    else
+    {
+        rSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_DWORD,
+                                                QSPI_IP_SFDP_XSPI1_RESET_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_WIDTH, 0x0U);
+        if (rSup == 1U)
+        {
+            /* 0xF0 reset command */
+            pConfig->resetSettings.resetCmdLut = lutCount;
+            pConfig->resetSettings.resetCmdCount = 1U;
+            instruction = QSPI_IP_CMD_XSPI_RESET;
+            cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, instruction);
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, instruction));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        }
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1InitResetInfo
+ * Description   : Configure initial reset settings - XPI mode
+ */
+static void Qspi_Ip_SfdpGetXspi1InitResetInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 rSup;
+    uint8 rEnSup;
+    uint8 instruction;
+
+    pConfig->initResetSettings.resetCmdLut = QSPI_IP_LUT_INVALID;
+    pConfig->initResetSettings.resetCmdCount = 0U;
+
+    rEnSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_EN_DWORD,
+                                              QSPI_IP_SFDP_XSPI1_RESET_EN_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_EN_WIDTH, 0x0U);
+    rSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_DEF_DWORD,
+                                            QSPI_IP_SFDP_XSPI1_RESET_DEF_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_DEF_WIDTH, 0x0U);
+    if ((rEnSup == 1U) && (rSup == 1U))
+    {
+        /* 0x66, 0x99 reset sequence */
+        pConfig->initResetSettings.resetCmdLut = lutCount;
+        pConfig->initResetSettings.resetCmdCount = 2U;
+        instruction = QSPI_IP_CMD_XSPI_RESET_ENABLE;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPadsInit, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, cmdPadsInit, 0x0U));
+
+        instruction = QSPI_IP_CMD_XSPI_RESET_DEF;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPadsInit, instruction));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, cmdPadsInit, 0x0U));
+    }
+    else
+    {
+        rSup = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_XSPI1_RESET_DWORD,
+                                                QSPI_IP_SFDP_XSPI1_RESET_SHIFT, QSPI_IP_SFDP_XSPI1_RESET_WIDTH, 0x0U);
+        if (rSup == 1U)
+        {
+            /* 0xF0 reset command */
+            pConfig->initResetSettings.resetCmdLut = lutCount;
+            pConfig->initResetSettings.resetCmdCount = 1U;
+            instruction = QSPI_IP_CMD_XSPI_RESET;
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPadsInit, instruction));
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, cmdPadsInit, 0x0U));
+        }
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicSuspendInfo
+ * Description   : Configure  suspend settings - SPI mode
+ */
+static void Qspi_Ip_SfdpGetBasicSuspendInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 esus;
+    uint8 eres;
+    uint8 psus;
+    uint8 pres;
+
+    esus = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_ESUS_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_ESUS_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_ESUS_INSTR_WIDTH, 0xB0U);
+    eres = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_ERES_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_ERES_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_ERES_INSTR_WIDTH, 0x30U);
+    psus = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_PSUS_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_PSUS_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_PSUS_INSTR_WIDTH, 0xB0U);
+    pres = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_PRES_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_PRES_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_PRES_INSTR_WIDTH, 0x30U);
+
+    /* Erase suspend sequence */
+    pConfig->suspendSettings.eraseSuspendLut = lutCount;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, esus));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Erase resume sequence */
+    pConfig->suspendSettings.eraseResumeLut = lutCount;
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, eres));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Program suspend sequence */
+    if (esus == psus)
+    {
+        pConfig->suspendSettings.programSuspendLut = pConfig->suspendSettings.eraseSuspendLut;
+    }
+    else
+    {
+        pConfig->suspendSettings.programSuspendLut = lutCount;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, psus));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+    /* Program resume sequence */
+    if (eres == pres)
+    {
+        pConfig->suspendSettings.programResumeLut = pConfig->suspendSettings.eraseResumeLut;
+    }
+    else
+    {
+        pConfig->suspendSettings.programResumeLut = lutCount;
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, cmdPads, pres));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1SuspendInfo
+ * Description   : Configure  suspend settings - XPI mode
+ */
+static void Qspi_Ip_SfdpGetXspi1SuspendInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 esus;
+    uint8 eres;
+    uint8 psus;
+    uint8 pres;
+    uint8 cmdExt;
+
+    esus = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_ESUS_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_ESUS_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_ESUS_INSTR_WIDTH, 0xB0U);
+    eres = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_ERES_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_ERES_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_ERES_INSTR_WIDTH, 0x30U);
+    psus = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_PSUS_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_PSUS_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_PSUS_INSTR_WIDTH, 0xB0U);
+    pres = (uint8)Qspi_Ip_SfdpGetXspi1Param(sfdpTables, QSPI_IP_SFDP_BASIC_PRES_INSTR_DWORD,
+                                            QSPI_IP_SFDP_BASIC_PRES_INSTR_SHIFT, QSPI_IP_SFDP_BASIC_PRES_INSTR_WIDTH, 0x30U);
+
+    /* Erase suspend sequence */
+    pConfig->suspendSettings.eraseSuspendLut = lutCount;
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, esus);
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, esus));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Erase resume sequence */
+    pConfig->suspendSettings.eraseResumeLut = lutCount;
+    cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, eres);
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, eres));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+    Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    /* Program suspend sequence */
+    if (esus == psus)
+    {
+        pConfig->suspendSettings.programSuspendLut = pConfig->suspendSettings.eraseSuspendLut;
+    }
+    else
+    {
+        pConfig->suspendSettings.programSuspendLut = lutCount;
+        cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, psus);
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, psus));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+    /* Program resume sequence */
+    if (eres == pres)
+    {
+        pConfig->suspendSettings.programResumeLut = pConfig->suspendSettings.eraseResumeLut;
+    }
+    else
+    {
+        pConfig->suspendSettings.programResumeLut = lutCount;
+        cmdExt = Qspi_Ip_SfdpGetCmdExt(sfdpTables, pres);
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, pres));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD_DDR, QSPI_IP_LUT_PADS_8, cmdExt));
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+    }
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpAdd2dopiOperation
+ * Description   : Add a DOPI switch command to the operation list
+ */
+static void Qspi_Ip_SfdpAdd2dopiOperation(const Qspi_Ip_MemoryConfigType * pConfig, uint8 seqSize, const uint32 *words)
+{
+    Qspi_Ip_InitOperationType *operation;
+    uint8 nextByte;
+    uint8 cnt;
+
+    if (initOpCount >= pConfig->initConfiguration.opCount)
+    {
+        /* operations list not big enough */
+        overflow = TRUE;
+    }
+    else
+    {
+        operation = &(pConfig->initConfiguration.operations[initOpCount]);
+        initOpCount++;
+        operation->opType = QSPI_IP_OP_TYPE_CMD;
+        operation->command1Lut = lutCount;
+        operation->addr = 0U;
+        /* Build LUT sequence for this command */
+        for (cnt = 0U; cnt < seqSize; cnt++)
+        {
+            nextByte = (uint8)((words[dopiSwitchWord[cnt]] >> dopiSwitchShift[cnt]) & 0xFFU);
+            Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, nextByte));
+        }
+        /* Add STOP instruction */
+        Qspi_Ip_SfdpLutAdd(&(pConfig->lutSequences), Qspi_Ip_PackLut(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0x0U));
+        /* Other operation fields are unused */
+        operation->command2Lut = QSPI_IP_LUT_INVALID;
+        operation->weLut = QSPI_IP_LUT_INVALID;
+        operation->size  = 0U;
+        operation->shift = 0U;
+        operation->width = 0U;
+        operation->value = 0U;
+        operation->ctrlCfgPtr = NULL_PTR;
+    }
+
+    return;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1InitOpInfo
+ * Description   : Configure initial operations list - XPI mode
+ */
+static void Qspi_Ip_SfdpGetXspi1InitOpInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint8 cnt;
+    uint8 seqSize;
+
+    if (sfdpTables->paramTableLength_2dopi > 0U)
+    {
+        for (cnt = 0U; cnt < (sfdpTables->paramTableLength_2dopi - 1U); cnt += 2U)
+        {
+            seqSize = (uint8)Qspi_Ip_SfdpGet2DopiParam(sfdpTables, cnt + 1U,
+                                                       QSPI_IP_SFDP_2DOPI_CMD_LEN_SHIFT, QSPI_IP_SFDP_2DOPI_CMD_LEN_WIDTH, 0x0U);
+            if (seqSize == 0U)
+            {
+                /* No more commands */
+                break;
+            }
+            Qspi_Ip_SfdpAdd2dopiOperation(pConfig, seqSize, &sfdpTables->paramTable_2dopi[cnt]);
+        }
+    }
+    /* Update operations count */
+    pConfig->initConfiguration.opCount = initOpCount;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetBasicInitOpInfo
+ * Description   : Configure initial operations list - XPI mode
+ */
+static void Qspi_Ip_SfdpGetBasicInitOpInfo(Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* Init operations already added, update operations count */
+    pConfig->initConfiguration.opCount = initOpCount;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGet0xxInfo
+ * Description   : Configure 0xx capabilities - XPI mode
+ */
+static void Qspi_Ip_SfdpGet0xxInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    /* Not implemented */
+    (void)sfdpTables;
+    pConfig->read0xxLut = QSPI_IP_LUT_INVALID;
+    pConfig->read0xxLutAHB = QSPI_IP_LUT_INVALID;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpConfigureOther
+ * Description   : Configure unsupported features
+ */
+static void Qspi_Ip_SfdpConfigureOther(Qspi_Ip_MemoryConfigType * pConfig)
+{
+    pConfig->readIdSettings.readIdLut = QSPI_IP_LUT_INVALID;
+    pConfig->initCallout = NULL_PTR;
+    pConfig->resetCallout = NULL_PTR;
+    pConfig->errorCheckCallout = NULL_PTR;
+    pConfig->ctrlAutoCfgPtr = NULL_PTR;
+}
+
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetSize
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static void Qspi_Ip_SfdpGetSize(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    uint32 size;
+
+    /* Dword 2 of parameter table: Flash Memory Density */
+    size = Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_MEM_SIZE_DWORD,
+                                     QSPI_IP_SFDP_BASIC_MEM_SIZE_SHIFT, QSPI_IP_SFDP_BASIC_MEM_SIZE_WIDTH, 0xFFFFFU);
+    /* check MSB */
+    if ((size & 0x80000000U) == 0U)
+    {
+        pConfig->memSize = (size + 1U) >> 3U;
+    }
+    else
+    {
+        pConfig->memSize = ((uint32)1U << ((size & (~(uint32)0x80000000U)) - (uint32)3U));
+    }
+
+    /* Dword 11 of parameter table: Page Size */
+    size = Qspi_Ip_SfdpGetBasicParam(sfdpTables, QSPI_IP_SFDP_BASIC_PAGE_SIZE_DWORD,
+                                     QSPI_IP_SFDP_BASIC_PAGE_SIZE_SHIFT, QSPI_IP_SFDP_BASIC_PAGE_SIZE_WIDTH, 8U);
+    pConfig->pageSize = ((uint32)1U << size);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_GetBasicInfo
+ * Description   : Builds basic configurations
+ */
+static inline void Qspi_Ip_SfdpGetBasicInfo(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                            Qspi_Ip_MemoryConfigType * pConfig
+                                           )
+{
+    /* Configure read command */
+    Qspi_Ip_SfdpGetBasicReadInfo(sfdpTables, pConfig);
+    /* Configure write command */
+    Qspi_Ip_SfdpGetBasicWriteInfo(sfdpTables, pConfig);
+    /* Configure erase commands */
+    Qspi_Ip_SfdpGetBasicEraseInfo(sfdpTables, pConfig);
+    /* Configure status register */
+    Qspi_Ip_SfdpGetBasicStatusInfo(sfdpTables, pConfig);
+
+    /* Configure reset settings */
+    Qspi_Ip_SfdpGetBasicResetInfo(sfdpTables, pConfig, &(pConfig->resetSettings), cmdPads);
+    /* Configure initial reset settings */
+    Qspi_Ip_SfdpGetBasicResetInfo(sfdpTables, pConfig, &(pConfig->initResetSettings), cmdPadsInit);
+    /* Configure suspend settings */
+    Qspi_Ip_SfdpGetBasicSuspendInfo(sfdpTables, pConfig);
+    /* Configure initial operations list */
+    Qspi_Ip_SfdpGetBasicInitOpInfo(pConfig);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureBasic
+ * Description   : Builds configuration for octal DDR (DOPI) mode.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_ConfigureBasic(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    /* Get size, page size */
+    Qspi_Ip_SfdpGetSize(sfdpTables, pConfig);
+    /* Get addres size for read/write commands */
+    Qspi_Ip_SfdpGetBasicAddrBits(sfdpTables, pConfig);
+    /* Check QE bit */
+    Qspi_Ip_SfdpConfigureQE(sfdpTables, pConfig);
+
+    /* Get basic info: read, write, erase, reset, suspend */
+    Qspi_Ip_SfdpGetBasicInfo(sfdpTables, pConfig);
+
+    /* Configure 0xx capabilities */
+    Qspi_Ip_SfdpGet0xxInfo(sfdpTables, pConfig);
+    /* Configure unsupported features */
+    Qspi_Ip_SfdpConfigureOther(pConfig);
+
+    /* Check for LUT or Init operations overflow */
+    if (overflow == TRUE)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    return status;
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_SfdpGetXspi1Info
+ * Description   : Builds Xspi1 configurations.
+ */
+static inline void Qspi_Ip_SfdpGetXspi1Info(const Qspi_Ip_SfdpTablesContainer *sfdpTables,
+                                            Qspi_Ip_MemoryConfigType * pConfig
+                                           )
+{
+    /* Configure read command */
+    Qspi_Ip_SfdpGetXspi1ReadInfo(sfdpTables, pConfig);
+    /* Configure write command */
+    Qspi_Ip_SfdpGetXspi1WriteInfo(sfdpTables, pConfig);
+    /* Configure erase commands */
+    Qspi_Ip_SfdpGetXspi1EraseInfo(sfdpTables, pConfig);
+    /* Configure status register */
+    Qspi_Ip_SfdpGetXspi1StatusInfo(sfdpTables, pConfig);
+
+    /* Configure reset settings */
+    Qspi_Ip_SfdpGetXspi1ResetInfo(sfdpTables, pConfig);
+    /* Configure initial reset settings */
+    Qspi_Ip_SfdpGetXspi1InitResetInfo(sfdpTables, pConfig);
+    /* Configure suspend settings */
+    Qspi_Ip_SfdpGetXspi1SuspendInfo(sfdpTables, pConfig);
+    /* Configure initial operations list */
+    Qspi_Ip_SfdpGetXspi1InitOpInfo(sfdpTables, pConfig);
+}
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ConfigureXspi1
+ * Description   : Builds octal DDR (DOPI) configuration for xSPI 1.0 devices.
+ */
+static Qspi_Ip_StatusType Qspi_Ip_ConfigureXspi1(const Qspi_Ip_SfdpTablesContainer *sfdpTables, Qspi_Ip_MemoryConfigType * pConfig)
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+
+    /* Get size, page size */
+    Qspi_Ip_SfdpGetSize(sfdpTables, pConfig);
+
+    /* Get Xspi1 info: read, write, erase, reset, suspend */
+    Qspi_Ip_SfdpGetXspi1Info(sfdpTables, pConfig);
+
+    /* Configure 0xx capabilities */
+    Qspi_Ip_SfdpGet0xxInfo(sfdpTables, pConfig);
+    /* Configure unsupported features */
+    Qspi_Ip_SfdpConfigureOther(pConfig);
+
+    /* Check for LUT or Init operations overflow */
+    if (overflow == TRUE)
+    {
+        status = STATUS_QSPI_IP_ERROR;
+    }
+    return status;
+}
+
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : Qspi_Ip_ReadSfdp
+ * Description   : Auto-fills configuration from SFDP information
+* @implements      Qspi_Ip_ReadSfdp_Activity */
+Qspi_Ip_StatusType Qspi_Ip_ReadSfdp(Qspi_Ip_MemoryConfigType * pConfig,
+                                    const Qspi_Ip_MemoryConnectionType * pConnect
+                                   )
+{
+    Qspi_Ip_StatusType status = STATUS_QSPI_IP_SUCCESS;
+    uint32 baseAddress;
+    /* SFDP Tables */
+    Qspi_Ip_SfdpTablesContainer sfdpTables;
+
+    /* Check for valid parameters */
+    DEV_ASSERT_QSPI(pConnect != NULL_PTR);
+    DEV_ASSERT_QSPI(pConfig != NULL_PTR);
+    DEV_ASSERT_QSPI((pConfig->lutSequences.lutOps != NULL_PTR) && (pConfig->lutSequences.opCount > 0U));
+    /* Get device base address */
+    baseAddress = Qspi_Ip_GetBaseAdress(pConnect->qspiInstance, pConnect->connectionType);
+    /* Initiate communication with flash, check SFDP support */
+    status = Qspi_Ip_SfdpCheck(pConnect->qspiInstance, baseAddress);
+    if (status != STATUS_QSPI_IP_SUCCESS)
+    {
+        /* direct command - nothing to do */
+    }
+    else
+    {
+        /* Read SFDP tables of interest */
+        status = Qspi_Ip_SfdpReadTables(pConnect->qspiInstance, baseAddress, &sfdpTables);
+        if (status != STATUS_QSPI_IP_SUCCESS)
+        {
+            /* direct command - nothing to do */
+        }
+        else
+        {
+            /* Initialize LUT and init operations count */
+            Qspi_Ip_SfdpLutInit();
+            /* Check xSPI 1.0 support */
+            if (sfdpTables.paramTableLength_xspi1 > 0U)
+            {
+                status = Qspi_Ip_ConfigureXspi1(&sfdpTables, pConfig);
+            }
+            else
+            {
+                status = Qspi_Ip_ConfigureBasic(&sfdpTables, pConfig);
+            }
+        }
+
+    }
+
+    return status;
+}
+
+
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+
+#endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

generate/include/FlexCAN_Ip_Cfg.h

@@ -147,7 +147,7 @@ extern "C"{
 #define FLEXCAN_IP_TIMEOUT_DURATION    (1000000U)
 
 /* This this will set the timer source for osif that will be used for timeout */
-#define FLEXCAN_IP_SERVICE_TIMEOUT_TYPE    (OSIF_COUNTER_DUMMY)
+#define FLEXCAN_IP_SERVICE_TIMEOUT_TYPE    (OSIF_COUNTER_SYSTEM)
 
 
 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */

generate/include/Flexio_Uart_Ip_Defines.h

@@ -92,7 +92,7 @@ extern "C"{
 #define FLEXIO_UART_IP_TIMEOUT_TYPE                     (OSIF_COUNTER_SYSTEM)
 
 /* @brief Number of loops before returning FLEXIO_STATUS_TIMEOUT.*/
-#define FLEXIO_UART_IP_TIMEOUT_VALUE_US                 (500000U)
+#define FLEXIO_UART_IP_TIMEOUT_VALUE_US                 (100000U)
 
 /* @brief Support for User mode. If this parameter has been configured to TRUE, the Uart driver can be executed from both supervisor and user mode. */
 #define FLEXIO_UART_IP_ENABLE_USER_MODE_SUPPORT         (STD_OFF)

generate/include/Fls_Cfg.h

@@ -0,0 +1,272 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLS_CFG_H
+#define FLS_CFG_H
+
+/**
+*   @file Fls_Cfg.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Fls_Cfg.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls_Types.h"
+#include "Mcal.h"
+#include "MemIf_Types.h"
+#include "Ftfc_Fls_Ip_Cfg.h"
+
+#include "Qspi_Ip_Cfg.h"
+
+#include "Fls_VS_0_PBcfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VENDOR_ID_CFG                    43
+#define FLS_AR_RELEASE_MAJOR_VERSION_CFG     4
+#define FLS_AR_RELEASE_MINOR_VERSION_CFG     4
+#define FLS_AR_RELEASE_REVISION_VERSION_CFG  0
+#define FLS_SW_MAJOR_VERSION_CFG             1
+#define FLS_SW_MINOR_VERSION_CFG             0
+#define FLS_SW_PATCH_VERSION_CFG             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls configuration header file are of the same vendor */
+#if (FLS_TYPES_VENDOR_ID != FLS_VENDOR_ID_CFG)
+    #error "Fls_Types.h and Fls_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Fls configuration header file are of the same Autosar version */
+#if ((FLS_TYPES_AR_RELEASE_MAJOR_VERSION    != FLS_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_TYPES_AR_RELEASE_MINOR_VERSION    != FLS_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_TYPES_AR_RELEASE_REVISION_VERSION != FLS_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_Types.h and Fls_Cfg.h are different"
+#endif
+/* Check if current file and Fls configuration header file are of the same software version */
+#if ((FLS_TYPES_SW_MAJOR_VERSION != FLS_SW_MAJOR_VERSION_CFG) || \
+     (FLS_TYPES_SW_MINOR_VERSION != FLS_SW_MINOR_VERSION_CFG) || \
+     (FLS_TYPES_SW_PATCH_VERSION != FLS_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_Types.h and Fls_Cfg.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Std_Types header file are of the same version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_CFG != MCAL_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls_Types.h and Mcal.h are different"
+    #endif
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and MemIf_Types.h file are of the same Autosar version */
+    #if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG != MEMIF_AR_RELEASE_MAJOR_VERSION) || \
+         (FLS_AR_RELEASE_MINOR_VERSION_CFG != MEMIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Fls_Cfg.h and MemIf_Types.h are different"
+    #endif
+#endif
+
+
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG != FTFC_FLS_IP_VENDOR_ID_CFG)
+    #error "Fls_Cfg.h and Ftfc_Fls_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG    != FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG    != FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG != FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_Cfg.h and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Cfg header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG != FTFC_FLS_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLS_SW_MINOR_VERSION_CFG != FTFC_FLS_IP_SW_MINOR_VERSION_CFG) || \
+     (FLS_SW_PATCH_VERSION_CFG != FTFC_FLS_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_Cfg.h and Ftfc_Fls_Ip_Cfg.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Cfg header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG != QSPI_IP_VENDOR_ID_CFG)
+    #error "Fls_Cfg.h and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG    != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+#error "AutoSar Version Numbers of Fls_Cfg.h and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG != QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLS_SW_MINOR_VERSION_CFG != QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLS_SW_PATCH_VERSION_CFG != QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_Cfg.h and Qspi_Ip_Cfg.h are different"
+#endif
+
+/* Check if current file and Fls_VS_0_PBcfg header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG != FLS_VS_0_PBCFG_VENDOR_ID)
+    #error "Fls_Cfg.h and Fls_VS_0_PBcfg.h have different vendor ids"
+#endif
+/* Check if current file and Fls_VS_0_PBcfg header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG    != FLS_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG    != FLS_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG != FLS_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Fls_Cfg.h and Fls_VS_0_PBcfg.h are different"
+#endif
+/* Check if current file and Fls_VS_0_PBcfg header file are of the same software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG != FLS_VS_0_PBCFG_SW_MAJOR_VERSION) || \
+     (FLS_SW_MINOR_VERSION_CFG != FLS_VS_0_PBCFG_SW_MINOR_VERSION) || \
+     (FLS_SW_PATCH_VERSION_CFG != FLS_VS_0_PBCFG_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_Cfg.h and Fls_VS_0_PBcfg.h are different"
+#endif
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+#define FLS_CONFIG_EXT \
+    FLS_CONFIG_VS_0_PB \
+
+/* STD_ON: Flash access code loaded on job start / unloaded on job end or error */
+#define FLS_AC_LOAD_ON_JOB_START             (STD_ON)
+
+#if (FLS_AC_LOAD_ON_JOB_START == STD_ON)
+    /* Cleaning cache after loading access code to RAM */
+    #define FLS_CLEAN_CACHE_AFTER_LOAD_AC    (STD_OFF)
+#endif
+
+/* Compile switch to enable and disable the Fls_Cancel function */
+#define FLS_CANCEL_API                       (STD_ON)
+
+/* Compile switch to enable and disable the Fls_Compare function */
+#define FLS_COMPARE_API                      (STD_ON)
+
+/* Compile switch to enable and disable the Fls_BlankCheck function */
+#define FLS_BLANK_CHECK_API                  (STD_OFF)
+
+/* Pre-processor switch to enable and disable development error detection */
+#define FLS_DEV_ERROR_DETECT                 (STD_ON)
+
+/* Compile switch to enable and disable the Fls_GetJobResult function */
+#define FLS_GET_JOB_RESULT_API               (STD_ON)
+
+/* Compile switch to enable and disable the Fls_GetStatus function */
+#define FLS_GET_STATUS_API                   (STD_ON)
+
+/* Compile switch to enable and disable the Fls_SetMode function */
+#define FLS_SET_MODE_API                     (STD_ON)
+
+/* Pre-processor switch to enable / disable the API to read out the modules version information */
+#define FLS_VERSION_INFO_API                 (STD_ON)
+
+/* Pre-processor switch to enable / disable the API to report data storage (ECC) errors to the flash driver */
+#define FLS_ECC_CHECK                        (STD_OFF)
+#define FLS_ECC_CHECK_BY_AUTOSAR_OS          (STD_OFF)
+
+/* Pre-processor switch to enable / disable the erase blank check */
+#define FLS_ERASE_VERIFICATION_ENABLED       (STD_OFF)
+
+/* Pre-processor switch to enable / disable the write verify check */
+#define FLS_WRITE_VERIFICATION_ENABLED       (STD_OFF)
+
+#if (FLS_ERASE_VERIFICATION_ENABLED == STD_ON)
+    /* The maximum number of bytes to blank check in one cycle of the flash driver job processing function */
+    #define FLS_MAX_ERASE_BLANK_CHECK        (256U)
+#endif
+
+/* Timeout handling enabled */
+#define FLS_TIMEOUT_SUPERVISION_ENABLED      (STD_OFF)
+
+
+/* Internal sectors are present or not in the current configuration. */
+#define FLS_INTERNAL_SECTORS_CONFIGURED      (STD_ON)
+
+/* Base address of code flash */
+#define FLS_PROGRAM_FLASH_BASE_ADDR          (0x00000000UL)
+/* Base address of data flash */
+#define FLS_DATA_FLASH_BASE_ADDR             (0x10000000UL)
+
+/* Internal flash write register size */
+#define FLS_INTERNAL_WRITE_SIZE              (8UL)
+
+
+/* External QSPI sectors are present or not in the current configuration. */
+#define FLS_QSPI_SECTORS_CONFIGURED          (STD_OFF)
+
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+                                 GLOBAL CONSTANT DECLARATIONS
+==================================================================================================*/
+#define FLS_PRECOMPILE_SUPPORT
+
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+/* Declaration of pre-compile configuration set structure */
+#define Fls_Config Fls_Config_VS_0
+extern const Fls_ConfigType Fls_Config;
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FLS_CFG_H */

generate/include/Fls_VS_0_PBcfg.h

@@ -0,0 +1,105 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef FLS_VS_0_PBCFG_H
+#define FLS_VS_0_PBCFG_H
+
+/**
+*   @file Fls_VS_0_PBcfg.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Fls_PBcfg.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VS_0_PBCFG_VENDOR_ID                    43
+
+#define FLS_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION     4
+#define FLS_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION     4
+#define FLS_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION  0
+
+#define FLS_VS_0_PBCFG_SW_MAJOR_VERSION             1
+#define FLS_VS_0_PBCFG_SW_MINOR_VERSION             0
+#define FLS_VS_0_PBCFG_SW_PATCH_VERSION             0
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+
+
+#define FLS_CONFIG_VS_0_PB \
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                             ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif    /* #ifndef FLS_VS_0_PBCFG_H */

generate/include/Ftfc_Eep_Ip_Cfg.h

@@ -112,7 +112,7 @@ extern "C"{
 #define FTFC_EEP_IP_FLEXRAM_ADDRESS         0x14000000U
 
 /** Total size of EEP */
-#define FTFC_EEP_IP_EEP_SIZE                2048U
+#define FTFC_EEP_IP_EEP_SIZE                4096U
 
 /** If this is a HT chip derivative the FTFM registers will be used - instead of FTFC. */
 #define FTFC_EEP_IP_HIGH_TEMP_CHIP          STD_OFF

generate/include/Ftfc_Fls_Ip_Cfg.h

@@ -0,0 +1,260 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FTFC_FLS_IP_CFG_H
+#define FTFC_FLS_IP_CFG_H
+
+/**
+*   @file Ftfc_Fls_Ip_Cfg.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Ftfc_Fls_Ip_Cfg.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "OsIf.h"
+
+#include "S32K146_FTFC.h"
+#include "S32K146_MSCM.h"
+#include "S32K146_SIM.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_VENDOR_ID_CFG                          43
+#define FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG           4
+#define FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG           4
+#define FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG        0
+#define FTFC_FLS_IP_SW_MAJOR_VERSION_CFG                   1
+#define FTFC_FLS_IP_SW_MINOR_VERSION_CFG                   0
+#define FTFC_FLS_IP_SW_PATCH_VERSION_CFG                   0
+
+
+/*==================================================================================================
+*                                 FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and OsIf.h header file are of the same Autosar version */
+    #if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG != OSIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Ftfc_Fls_Ip_Cfg.h and OsIf.h are different"
+    #endif
+#endif
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+#define FTFx_HARDWARE_TYPE                   FTFC_Type
+#define FTFx_HARDWARE_UNIT                   IP_FTFC
+
+#define FTFx_FPROT_COUNT                     FTFC_FPROT_COUNT
+#define FTFx_FSTAT_CCIF_MASK                 FTFC_FSTAT_CCIF_MASK
+#define FTFx_FSTAT_ACCERR_MASK               FTFC_FSTAT_ACCERR_MASK
+#define FTFx_FSTAT_FPVIOL_MASK               FTFC_FSTAT_FPVIOL_MASK
+#define FTFx_FSTAT_MGSTAT0_MASK              FTFC_FSTAT_MGSTAT0_MASK
+#define FTFx_FSTAT_RDCOLERR_MASK             FTFC_FSTAT_RDCOLERR_MASK
+#define FTFx_FERSTAT_DFDIF_MASK              FTFC_FERSTAT_DFDIF_MASK
+#define FTFx_FCNFG_ERSSUSP_MASK              FTFC_FCNFG_ERSSUSP_MASK
+
+#define FTFx_FSTAT_MGSTAT3_MASK              (0x00U)
+#define FTFx_FSTAT_MGSTAT2_MASK              (0x00U)
+#define FTFx_FSTAT_MGSTAT1_MASK              (0x00U)
+
+/* Mask of FTFx IP-related error flags */
+#define FTFx_ERR_FLAGS_MASK                  (FTFx_FSTAT_RDCOLERR_MASK | \
+                                              FTFx_FSTAT_ACCERR_MASK   | \
+                                              FTFx_FSTAT_FPVIOL_MASK   | \
+                                              FTFx_FSTAT_MGSTAT3_MASK  | \
+                                              FTFx_FSTAT_MGSTAT2_MASK  | \
+                                              FTFx_FSTAT_MGSTAT1_MASK  | \
+                                              FTFx_FSTAT_MGSTAT0_MASK)
+
+
+#define FTFC_FLS_IP_INVALID_PREBUF_FROM_RAM  (STD_ON)
+
+#define FTFC_FLS_IP_SYNCRONIZE_CACHE         (STD_ON)
+
+#if (STD_ON == FTFC_FLS_IP_SYNCRONIZE_CACHE)
+    #define FTFC_FLS_D_FLASH_CACHEABLE       (STD_ON)
+#endif
+
+#define FTFC_ENABLE_USER_MODE_SUPPORT        (STD_OFF)
+
+#define FTFC_TIMEOUT_SUPERVISION_ENABLED     (STD_OFF)
+
+#define FTFC_ERASE_VERIFICATION_ENABLED      (STD_OFF)
+
+#define FTFC_PROGRAM_VERIFICATION_ENABLED    (STD_OFF)
+
+#define FTFC_ERASED_VALUE                    (0xFFFFFFFFU)
+
+#define FTFC_ECC_CHECK                       (STD_OFF)
+
+#define FTFC_ECC_CHECK_BY_AUTOSAR_OS         (STD_OFF)
+
+#if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) )
+
+/* Support for all the derivatives excepting the M0++ core missing some registers related to read syndrome(CFSR) and data address(BFAR) */
+#define FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK    (STD_ON)
+
+#if (FTFC_ECC_SYNDROME_AND_DATA_ADDRESS_CHECK == STD_ON)
+    #define FTFC_DSI_EXC_SYNDROME                   (0x00008200U)
+#endif
+
+/*Return value for Fls_DsiHandler and Fls_MciHandler*/
+/**
+*   Return value for Fls_DsiHandler and Fls_MciHandler.
+*   module does not feel responsible (e.g. address does not belong to its current job,
+*   there is no current pending read/compare job, the syndrome is different).
+*
+*/
+#define FLS_UNHANDLED       (0U)
+/**
+*   Return value for Fls_DsiHandler and Fls_MciHandler.
+*   module feels responsible, but wants to repeat the  causing instruction.
+*   Maybe: it still uses information in MCM or ECSM module, but they are outdated
+*   (e.g. due to an erroneous DMA transfer in the meantime)
+*
+*/
+#define FLS_HANDLED_RETRY   (1U)
+/**
+*   Return value for Fls_DsiHandler and Fls_MciHandler.
+*   module feels responsible, the current job is marked as failed,
+*   processing may continue, skipping the causing instruction.
+*
+*/
+#define FLS_HANDLED_SKIP    (2U)
+/**
+*   Return value for Fls_DsiHandler and Fls_MciHandler.
+*   module  feels responsible, but the only reaction is to stop the system
+*   (e.g.: try to shut-down in a quite safe way)
+*
+*/
+#define FLS_HANDLED_STOP    (3U)
+#endif  /* #if ( (FTFC_ECC_CHECK == STD_ON) || (FTFC_ECC_CHECK_BY_AUTOSAR_OS == STD_ON) ) */
+
+/*! Enable development error check */
+#define DEV_ASSERT_FTFC(x)
+
+#define FTFC_TIMEOUT_TYPE                    (OSIF_COUNTER_DUMMY)
+
+#if (STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)
+
+#define FTFC_ASYNC_WRITE_TIMEOUT             (2147483647U)
+
+#define FTFC_ASYNC_ERASE_TIMEOUT             (2147483647U)
+
+#define FTFC_SYNC_WRITE_TIMEOUT              (2147483647U)
+
+#define FTFC_SYNC_ERASE_TIMEOUT              (2147483647U)
+
+#define FTFC_ABORT_TIMEOUT                   (32767U)
+
+#endif  /*(STD_ON == FTFC_TIMEOUT_SUPERVISION_ENABLED)*/
+
+/* Flash memory characteristics */
+#define FTFC_P_FLASH_BASE_ADDR               (0x00000000UL)
+#define FTFC_P_FLASH_SIZE                    (0x100000UL)
+#define FTFC_P_FLASH_SECTOR_SIZE             (0x1000UL)
+
+#define FTFC_D_FLASH_BASE_ADDR               (0x10000000UL)
+#define FTFC_D_FLASH_SIZE                    (0x10000UL)
+#define FTFC_D_FLASH_SECTOR_SIZE             (0x800UL)
+
+/* Valid P_FLASH address */
+#define FTFC_ADDRESS_VALID_P_FLASH(addr)     ( (addr) < (FTFC_P_FLASH_BASE_ADDR + FTFC_P_FLASH_SIZE) )
+
+/* Valid D_FLASH address */
+#define FTFC_ADDRESS_VALID_D_FLASH(addr)     ( (FTFC_D_FLASH_BASE_ADDR <= (addr)) && ((addr) < (FTFC_D_FLASH_BASE_ADDR + FTFC_D_FLASH_SIZE)) )
+
+/* Valid P_FLASH or D_FLASH address */
+#define FTFC_ADDRESS_VALID(addr)             ( FTFC_ADDRESS_VALID_P_FLASH(addr) || FTFC_ADDRESS_VALID_D_FLASH(addr) )
+
+
+/* Check if the address is sector alignment or not */
+#define FTFC_SECTOR_ALIGNED(addr)            ( ( ((addr) & (FTFC_P_FLASH_SECTOR_SIZE - 1UL)) == 0UL ) || ( ((addr) & (FTFC_D_FLASH_SECTOR_SIZE - 1UL)) == 0UL ) )
+
+
+/* FlexNVM Partition Code Ratios (DFLASH_EEPROM sizes in KB) - used for Program Partition Command */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_DEFAULT     (0x0FU)   /* Bit value:1111   Data flash (KByte):default*/
+#if (0x8000UL == FTFC_D_FLASH_SIZE)
+#define FLASH_FLEXNVM_DFLASH_EEPROM_32_0_V1     (0x00U)   /* Bit value:0000   Data flash (KByte):32 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_0_32_V1     (0x03U)   /* Bit value:0011   Data flash (KByte):0  EEPROM backup (KByte):32 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_0_32_V2     (0x08U)   /* Bit value:1000   Data flash (KByte):0  EEPROM backup (KByte):32 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_8_24_V1     (0x09U)   /* Bit value:1001   Data flash (KByte):8  EEPROM backup (KByte):24 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_32_0_V2     (0x0BU)   /* Bit value:1011   Data flash (KByte):32 EEPROM backup (KByte):0 */
+
+#elif (0x10000UL == FTFC_D_FLASH_SIZE)
+#define FLASH_FLEXNVM_DFLASH_EEPROM_64_0_V1     (0x00U)   /* Bit value:0000   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_32_32_V1    (0x03U)   /* Bit value:0011   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_0_64_V1     (0x04U)   /* Bit value:0100   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_0_64_V2     (0x08U)   /* Bit value:1000   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_16_48_V1    (0x0AU)   /* Bit value:1010   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_32_32_V2    (0x0BU)   /* Bit value:1011   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_64_0_V2     (0x0CU)   /* Bit value:1100   Data flash (KByte):64 EEPROM backup (KByte):0 */
+
+#elif (0x80000UL == FTFC_D_FLASH_SIZE)
+#define FLASH_FLEXNVM_DFLASH_EEPROM_512_0_V1    (0x00U)   /* Bit value:0000   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_448_64_V1   (0x04U)   /* Bit value:0100   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#define FLASH_FLEXNVM_DFLASH_EEPROM_512_0_V2    (0x0FU)   /* Bit value:1111   Data flash (KByte):64 EEPROM backup (KByte):0 */
+#endif
+
+/* Code block size (flash read partition size) */
+#define FLS_P_BLOCK_SIZE                     (0x80000U)
+
+
+/*==================================================================================================
+                                 GLOBAL CONSTANT DECLARATIONS
+==================================================================================================*/
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+extern const Ftfc_ConfigType FlsConfigSet_VS_0_InitCfg;
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* FTFC_FLS_IP_CFG_H */

generate/include/Mcal.h

@@ -0,0 +1,624 @@
+/*==================================================================================================
+* Project : RTD AUTOSAR 4.4
+* Platform : CORTEXM
+* Peripheral : S32K14X
+* Dependencies : none
+*
+* Autosar Version : 4.4.0
+* Autosar Revision : ASR_REL_4_4_REV_0000
+* Autosar Conf.Variant :
+* SW Version : 1.0.0
+* Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+* (c) Copyright 2020-2021 NXP Semiconductors
+* All Rights Reserved.
+*
+* NXP Confidential. This software is owned or controlled by NXP and may only be
+* used strictly in accordance with the applicable license terms. By expressly
+* accepting such terms or by downloading, installing, activating and/or otherwise
+* using the software, you are agreeing that you have read, and that you agree to
+* comply with and are bound by, such license terms. If you do not agree to be
+* bound by the applicable license terms, then you may not retain, install,
+* activate or otherwise use the software.
+==================================================================================================*/
+/**
+*   @file           Mcal.h
+*   @implements     Mcal.h_Artifact
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Base - SWS Compiler abstraction specific for MCAL.
+*   @details The file Mcal.h provides MCAL specific macros used for compiler abstraction.
+*
+*
+*   @addtogroup BASE_COMPONENT
+*   @{
+*/
+
+
+#ifndef MCAL_H
+#define MCAL_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+/*
+* @file        Mcal.h
+* @brief Include compiler abstraction
+*/
+#include "Compiler.h"
+/*
+* @file        Mcal.h
+* @brief Include standard types
+*/
+#include "StandardTypes.h"
+
+#include "Soc_Ips.h"
+
+#include "Reg_eSys.h"
+
+#include "OsIf_Internal.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define MCAL_VENDOR_ID                    43
+/** @violates @ref Mcal_h_REF_2 unused macro. */
+#define MCAL_MODULE_ID                    0
+#define MCAL_AR_RELEASE_MAJOR_VERSION     4
+#define MCAL_AR_RELEASE_MINOR_VERSION     4
+#define MCAL_AR_RELEASE_REVISION_VERSION  0
+#define MCAL_SW_MAJOR_VERSION             1
+#define MCAL_SW_MINOR_VERSION             0
+#define MCAL_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if source file and Compiler.h header file are of the same Autosar version */
+    #if ((MCAL_AR_RELEASE_MAJOR_VERSION != COMPILER_AR_RELEASE_MAJOR_VERSION) || \
+         (MCAL_AR_RELEASE_MINOR_VERSION != COMPILER_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Mcal.h and Compiler.h are different"
+    #endif
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if source file and StandardTypes.h header file are of the same Autosar version */
+    #if ((MCAL_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (MCAL_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Mcal.h and StandardTypes.h are different"
+    #endif
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if source file and StandardTypes.h header file are of the same Autosar version */
+    #if ((MCAL_AR_RELEASE_MAJOR_VERSION != REG_ESYS_AR_RELEASE_MAJOR_VERSION) || \
+         (MCAL_AR_RELEASE_MINOR_VERSION != REG_ESYS_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Mcal.h and Reg_eSys.h are different"
+    #endif
+#endif
+
+/* Check if source file and Soc_Ips.h header file have same versions */
+#if (MCAL_VENDOR_ID  != SOC_IPS_VENDOR_ID)
+#error "Soc_Ips.h and Mcal.h have different vendor IDs"
+#endif
+
+/* Check if source file and Soc_Ips.h header file are of the same Autosar version */
+#if ((MCAL_AR_RELEASE_MAJOR_VERSION != SOC_IPS_AR_RELEASE_MAJOR_VERSION) || \
+     (MCAL_AR_RELEASE_MINOR_VERSION != SOC_IPS_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Mcal.h and Soc_Ips.h are different"
+#endif
+
+#if ((MCAL_SW_MAJOR_VERSION != SOC_IPS_SW_MAJOR_VERSION) || \
+     (MCAL_SW_MINOR_VERSION != SOC_IPS_SW_MINOR_VERSION) || \
+     (MCAL_SW_PATCH_VERSION != SOC_IPS_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Soc_Ips.h and Mcal.h are different"
+#endif
+/*==================================================================================================
+*                                         CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/   
+
+/**************************************** Green Hills *********************************************/
+#ifdef _GREENHILLS_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */    
+    #define ASM_KEYWORD  __asm
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();  \
+                    ASM_KEYWORD("  wfi");   \
+                    OsIf_SuspendAllInterrupts(); \
+                } while (0)
+
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) __attribute__(( aligned(size) )) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+    
+   /**
+    * @brief Compiler abstraction for the packed qualifier
+    */
+    #define PACKED __packed 
+
+    /**
+     * @brief Compiler abstraction for MCAL Fault Injection tests 
+    */
+    #ifdef MCAL_ENABLE_FAULT_INJECTION
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_PUT_IN_QUOTES(x) #x
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label) ASM_KEYWORD(MCAL_PUT_IN_QUOTES(label::))
+    #else
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)
+    #endif
+        
+#endif /* #ifdef _GREENHILLS_C_S32K1XX_ */
+
+/**************************************** Wind River Diab *****************************************/
+#ifdef _DIABDATA_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */
+    #define ASM_KEYWORD  __asm volatile
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();              \
+                    ASM_KEYWORD(" wfi");  \
+                    OsIf_SuspendAllInterrupts();             \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) __attribute__(( aligned(size) )) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+    
+    /**
+     * @brief Compiler abstraction for the packed qualifier
+     */
+    #define PACKED __attribute__((packed)) 
+    
+    /**
+     * @brief Compiler abstraction for MCAL Fault Injection tests 
+    */
+    #ifdef MCAL_ENABLE_FAULT_INJECTION
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_PUT_IN_QUOTES(x) #x
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label) ASM_KEYWORD(MCAL_PUT_IN_QUOTES(label:))
+    #else
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)
+    #endif
+
+#endif /* #ifdef _DIABDATA_C_S32K1XX_ */
+
+/*************************************** CodeWarrior **********************************************/
+#ifdef _CODEWARRIOR_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */
+    #define ASM_KEYWORD  asm
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD (" opword 0x7C00007C");     \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) v __attribute__(( aligned(size) ));
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+    
+    /**
+    * @brief Compiler abstraction for the packed qualifier
+    */
+    #define PACKED __packed 
+
+#endif /* #ifdef _CODEWARRIOR_C_S32K1XX_ */
+
+/*************************************** Cosmic ***************************************************/
+#ifdef _COSMIC_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */
+    #define ASM_KEYWORD  _asm
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ASM_PUBLIC_LABEL(label)  _asm("\txdef\t" #label "\n" #label ":")
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD (" dc.l 0x7C00007C");       \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    #define ALIGNED_VARS_START(sec_name, align) \#pragma section [sec_name ## align]
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    #define VAR_ALIGN(v, size) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    #define ALIGNED_VARS_STOP() \#pragma section []
+#endif /* #ifdef _COSMIC_C_S32K1XX_ */
+
+/*************************************** HighTec **********************************************/
+#ifdef _HITECH_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */
+    #define ASM_KEYWORD  __asm
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD("  wait");                  \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) __attribute__(( aligned(size) )) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+#endif /* #ifdef _HITECH_C_S32K1XX_ */
+/**************************************** Linaro *********************************************/
+#ifdef _LINARO_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */    
+    #define ASM_KEYWORD  __asm
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD("  wfi");                   \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) __attribute__(( aligned(size) )) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+    
+    /**
+     * @brief Compiler abstraction for the packed qualifier
+     */
+    #define PACKED __attribute__((__packed__))
+    
+    /**
+     * @brief Compiler abstraction for MCAL Fault Injection tests 
+    */
+    #ifdef MCAL_ENABLE_FAULT_INJECTION
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_PUT_IN_QUOTES(x) #x
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label) ASM_KEYWORD(MCAL_PUT_IN_QUOTES(label:))
+    #else
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)
+    #endif
+  
+#endif /* #ifdef _LINARO_C_S32K1XX_ */
+
+/**************************************** DS5 *********************************************/
+#ifdef _ARM_DS5_C_S32K1XX_
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */    
+    #define ASM_KEYWORD  __asm
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD("  wfi");                   \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_START(sec_name, align)
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define VAR_ALIGN(v, size) __align(size) v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define ALIGNED_VARS_STOP()
+    /**
+     * @brief Compiler abstraction for the packed qualifier
+     */
+    #define PACKED __packed 
+    
+    /**
+     * @brief Compiler abstraction for MCAL Fault Injection tests 
+    */
+    #ifdef MCAL_ENABLE_FAULT_INJECTION
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_PUT_IN_QUOTES(x) #x
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label) ASM_KEYWORD(MCAL_PUT_IN_QUOTES(label:))
+    #else
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)
+    #endif
+    
+#endif /* #ifdef _ARM_DS5_C_S32K1XX_ */
+/**************************************** IAR *********************************************/
+#ifdef _IAR_C_S32K1XX_
+    
+    /**
+    * @brief Compiler abstraction for the "Put in Quotes".
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define MCAL_PUT_IN_QUOTES(x) #x
+    /**
+    * @brief Compiler abstraction for the "Double Put in Quotes" - Used by VAL_ALIGN.
+    */
+    /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+    #define MCAL_PUT_IN_QUOTES1(x) MCAL_PUT_IN_QUOTES(x)
+
+    /**
+    * @brief Compiler abstraction for the asm keyword.
+    */    
+    #define ASM_KEYWORD  __asm
+
+    /**
+    * @brief Compiler abstraction for the intrinsic wait instruction.
+    */
+    /*
+    * @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+    */
+    #define EXECUTE_WAIT()  \
+                do  \
+                {   \
+                    OsIf_ResumeAllInterrupts();                  \
+                    ASM_KEYWORD("  wfi");                   \
+                    OsIf_SuspendAllInterrupts();                 \
+                } while (0)
+
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /*
+    * @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+    */
+    #define ALIGNED_VARS_START(sec_name, align) 
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /*
+    * @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+    */
+    #define VAR_ALIGN(v, size)  _Pragma(MCAL_PUT_IN_QUOTES1(data_alignment=size)) \
+                                v;
+    /**
+    * @brief Compiler abstraction for the data alignment
+    */
+    /*
+    * @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+    */
+    #define ALIGNED_VARS_STOP() 
+    
+   /**
+    * @brief Compiler abstraction for the packed qualifier
+    */
+    /*
+    * @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+    */
+    #define PACKED __packed 
+        
+    /**
+     * @brief Compiler abstraction for MCAL Fault Injection tests 
+    */
+    #ifdef MCAL_ENABLE_FAULT_INJECTION
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)   ASM_KEYWORD(MCAL_PUT_IN_QUOTES(label:))
+    #else
+        /**  @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro. */
+        #define MCAL_FAULT_INJECTION_POINT(label)
+    #endif
+        
+#endif /* #ifdef _IAR_C_S32K1XX_ */
+
+/* check that the compiler used is supported (otherwise some defines might not exist) */
+#ifndef _GREENHILLS_C_S32K1XX_
+    #ifndef _DIABDATA_C_S32K1XX_
+        #ifndef _CODEWARRIOR_C_S32K1XX_
+            #ifndef _COSMIC_C_S32K1XX_
+                #ifndef _HITECH_C_S32K1XX_
+                    #ifndef _LINARO_C_S32K1XX_
+                        #ifndef _ARM_DS5_C_S32K1XX_
+                            #ifndef _IAR_C_S32K1XX_
+                                #error "Unsupported compiler. Compiler abstraction needs to be updated to use this compiler."
+                            #endif    
+                        #endif
+                    #endif
+                #endif
+            #endif
+        #endif
+    #endif
+#endif
+#if (MCAL_PLATFORM_ARM  == MCAL_ARM_AARCH64)
+/**
+* @brief Data Synchronization Barrier (DSB) completes when all instructions before this instruction complete
+*/
+/*
+* @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+*/
+#define MCAL_DATA_SYNC_BARRIER()  ASM_KEYWORD("dsb sy":::"memory")
+/**
+* @brief  flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the ISB has been completed.
+*/
+/*
+* @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+*/
+#define MCAL_INSTRUCTION_SYNC_BARRIER()  ASM_KEYWORD("isb":::"memory")
+#else
+/**
+* @brief Data Synchronization Barrier (DSB) completes when all instructions before this instruction complete
+*/
+/*
+* @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+*/
+#define MCAL_DATA_SYNC_BARRIER()  ASM_KEYWORD(" DSB")
+
+/**
+* @brief  flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the ISB has been completed.
+*/
+/*
+* @violates @ref Mcal_h_REF_1 A function should be used in preference to a function-like macro.
+*/
+#define MCAL_INSTRUCTION_SYNC_BARRIER()  ASM_KEYWORD(" ISB")
+#endif
+
+#if defined(MCAL_PLATFORM_ARM_M4) || defined(MCAL_PLATFORM_ARM_M4F)
+    #if !defined(USING_OS_AUTOSAROS)
+        #define EXIT_INTERRUPT()  MCAL_DATA_SYNC_BARRIER()   /* DSB sy full system */
+    #else
+        #define EXIT_INTERRUPT()
+    #endif /* !defined(USING_OS_AUTOSAROS) */
+#else
+    #define EXIT_INTERRUPT()
+#endif
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/**
+* @brief Typedef for DEM error management implemented by MCAL drivers
+*/
+typedef struct
+{
+    uint32 state;   /**< enabling/disabling the DEM error: Active=STD_ON/ Inactive=STD_OFF */
+    uint32 id ;     /**< ID of DEM error (0 if STD_OFF)*/
+}Mcal_DemErrorType; 
+/*==================================================================================================
+*                                 GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef MCAL_H */
+
+/** @} */

generate/include/Power_Ip_Cfg_Defines.h

@@ -94,7 +94,7 @@ extern "C"{
 /**
 * @brief
 */
-#define MCU_PERFORM_RESET_API   (STD_OFF)
+#define MCU_PERFORM_RESET_API   (STD_ON)
 
 
 /**

generate/include/Qspi_Ip_Cfg.h

@@ -0,0 +1,170 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef QSPI_IP_CFG_H
+#define QSPI_IP_CFG_H
+
+/**
+*   @file Qspi_Ip_Cfg.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Qspi_Ip_Cfg.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Mcal.h"
+#include "StandardTypes.h"
+#include "OsIf.h"
+#include "Qspi_Ip_Types.h"
+#include "Qspi_Ip_VS_0_PBcfg.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VENDOR_ID_CFG                    43
+#define QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG     4
+#define QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG     4
+#define QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG  0
+#define QSPI_IP_SW_MAJOR_VERSION_CFG             1
+#define QSPI_IP_SW_MINOR_VERSION_CFG             0
+#define QSPI_IP_SW_PATCH_VERSION_CFG             0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Qspi_Ip_Cfg header file and Mcal.h header file are of the same Autosar version */
+    #if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != MCAL_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "Autosar Version Numbers of Qspi_Ip_Cfg.h and Mcal.h are different"
+    #endif
+    /* Check if Qspi_Ip_Cfg header file and StandardTypes.h header file are of the same Autosar version */
+    #if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != STD_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "Autosar Version Numbers of Qspi_Ip_Cfg.h and StandardTypes.h are different"
+    #endif
+    /* Check if Qspi_Ip_Cfg header file and OsIf.h header file are of the same Autosar version */
+    #if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != OSIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "Autosar Version Numbers of Qspi_Ip_Cfg.h and OsIf.h are different"
+    #endif
+#endif
+
+/* Check if current file and Qspi_Ip_Types header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_CFG != FLS_QSPI_TYPES_VENDOR_ID)
+    #error "Qspi_Ip_Cfg.h and Qspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG    != FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG    != FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG != FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_Cfg.h and Qspi_Ip_Types.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_CFG != FLS_QSPI_TYPES_SW_MAJOR_VERSION) || \
+     (QSPI_IP_SW_MINOR_VERSION_CFG != FLS_QSPI_TYPES_SW_MINOR_VERSION) || \
+     (QSPI_IP_SW_PATCH_VERSION_CFG != FLS_QSPI_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Cfg.h and Qspi_Ip_Types.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_VS_0_PBcfg header file are of the same vendor */
+#if (QSPI_IP_VENDOR_ID_CFG != QSPI_IP_VS_0_PBCFG_VENDOR_ID)
+    #error "Qspi_Ip_Cfg.h and Qspi_Ip_VS_0_PBcfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_VS_0_PBcfg header file are of the same Autosar version */
+#if ((QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG    != QSPI_IP_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION) || \
+     (QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG    != QSPI_IP_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION) || \
+     (QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG != QSPI_IP_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION) \
+    )
+#error "AutoSar Version Numbers of Qspi_Ip_Cfg.h and Qspi_Ip_VS_0_PBcfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_VS_0_PBcfg header file are of the same software version */
+#if ((QSPI_IP_SW_MAJOR_VERSION_CFG != QSPI_IP_VS_0_PBCFG_SW_MAJOR_VERSION) || \
+     (QSPI_IP_SW_MINOR_VERSION_CFG != QSPI_IP_VS_0_PBCFG_SW_MINOR_VERSION) || \
+     (QSPI_IP_SW_PATCH_VERSION_CFG != QSPI_IP_VS_0_PBCFG_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_Cfg.h and Qspi_Ip_VS_0_PBcfg.h are different"
+#endif
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/* Maximum number of retries for Write Enable command */
+#define QSPI_IP_MAX_RETRY                 (3U)
+
+/* Pre-processor switch to enable/disable development error detection for QSPI Ip API */
+#define DEV_ASSERT_QSPI(x)
+
+/* Number of serial flash devices */
+#define QSPI_IP_MEM_INSTANCE_COUNT        (0U)
+
+
+/* Timeout for QSPI command completion */
+#define QSPI_IP_CMD_COMPLETE_TIMEOUT      (1U)
+
+/* Timeout for external flash software reset completion */
+#define QSPI_IP_RESET_TIMEOUT             (1U)
+
+/* Timeout for external flash startup initialization sequence completion */
+#define QSPI_IP_FLS_INIT_TIMEOUT          (1U)
+
+/* Timeout for a complete read operation */
+#define QSPI_IP_READ_TIMEOUT              (2147483647U)
+
+/* OsIf counter type used in timeout detection for QSPI IP operations  */
+#define QSPI_IP_TIMEOUT_TYPE              (OSIF_COUNTER_DUMMY)
+
+/* Delay after changing the value of the QSPI software reset bits */
+#define QSPI_IP_SOFTWARE_RESET_DELAY      (0U)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_CFG_H */
+

generate/include/Qspi_Ip_Features.h

@@ -0,0 +1,128 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#if !defined(QSPI_IP_FEATURES_H)
+#define QSPI_IP_FEATURES_H
+
+/**
+*   @file Qspi_Ip_Features.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Qspi_Ip_Features.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_FEATURES_VENDOR_ID_CFG                      43
+#define QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG       4
+#define QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG       4
+#define QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG    0
+#define QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG               1
+#define QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG               0
+#define QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG               0
+
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/* QuadSPI module features */
+
+/*! @brief First address of the serial flash device on the AHB bus. */
+#define FEATURE_QSPI_AMBA_BASE                        0x68000000U
+/*! @brief Size of AHB buffer. */
+#define FEATURE_QSPI_AHB_BUF_SIZE                     1024U
+/*! @brief Size of Tx FIFO. */
+#define FEATURE_QSPI_TX_BUF_SIZE                      128U
+/*! @brief Size of Rx FIFO. */
+#define FEATURE_QSPI_RX_BUF_SIZE                      128U
+/*! @brief Number of LUT registers that make up a LUT sequence */
+#define FEATURE_QSPI_LUT_SEQUENCE_SIZE                4U
+/*! @brief Minimum delay in CPU cycles between Tx FIFO reset and Tx FIFO push */
+#define FEATURE_QSPI_TX_RESET_DELAY                   (0U)
+/* Minimum entries of 4 bytes fill needed to allow Tx operation to start */
+#define FEATURE_QSPI_TX_MIN_BUF_FILL                  4U
+
+/*! @brief Supports Double Data Rate operation */
+#define FEATURE_QSPI_DDR                              1
+/*! @brief QSPI side B is available */
+#define FEATURE_QSPI_HAS_SIDE_B                       1
+/*! @brief Configurable Idle Signal Drive */
+#define FEATURE_QSPI_CONFIGURABLE_ISD                 1
+
+/*! @brief Supports addr. config options (column address, word addressable) */
+#define FEATURE_QSPI_ADDR_CFG                         1
+/*! @brief Supports byte swap */
+#define FEATURE_QSPI_BYTES_SWAP_ADDR                  0
+
+/*! @brief Supports center-aligned read strobe */
+#define FEATURE_QSPI_CENTER_ALIGNED_READ_STROBE       0
+/*! @brief Supports differential clock */
+#define FEATURE_QSPI_DIFFERENTIAL_CLOCK               0
+
+/*! @brief Supports internal DQS sampling mode */
+#define FEATURE_QSPI_INTERNAL_DQS                     1
+/*! @brief Supports loopback sampling mode */
+#define FEATURE_QSPI_LOOPBACK                         1
+/*! @brief Supports DQS loopback sampling mode */
+#define FEATURE_QSPI_LOOPBACK_DQS                     1
+/*! @brief Supports external DQS sampling mode */
+#define FEATURE_QSPI_EXTERNAL_DQS                     1
+/*! @brief Supports DQS_FA_SEL/DQS_FB_SEL field in MCR register for DQS selection */
+#define FEATURE_QSPI_SELECT_DQS                       0
+
+/*! @brief Supports Dll feature */
+#define FEATURE_QSPI_HAS_DLL                          0
+/*! @brief Supports full DLL features (as opposed to bypass mode only) */
+#define FEATURE_QSPI_EXTERNAL_DLL_FULL                0
+/*! @brief Supports DLL reference counter and DLL resolution*/
+#define FEATURE_QSPI_DLL_LOOPCONTROL                  0
+
+
+/*! @brief AHB base pointers initializer for all QSPI units */
+#define QuadSPI_AHB_PTRS    { FEATURE_QSPI_AMBA_BASE }
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* QSPI_IP_FEATURES_H */

generate/include/Qspi_Ip_VS_0_PBcfg.h

@@ -0,0 +1,112 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+#ifndef QSPI_IP_VS_0_PBCFG_H
+#define QSPI_IP_VS_0_PBCFG_H
+
+/**
+*   @file Qspi_Ip_VS_0_PBcfg.h
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Qspi_Ip_PBcfg.h_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+                                         INCLUDE FILES
+ 1) system and project includes
+ 2) needed interfaces from external units
+ 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define QSPI_IP_VS_0_PBCFG_VENDOR_ID                    43
+
+#define QSPI_IP_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION     4
+#define QSPI_IP_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION     4
+#define QSPI_IP_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION  0
+
+#define QSPI_IP_VS_0_PBCFG_SW_MAJOR_VERSION             1
+#define QSPI_IP_VS_0_PBCFG_SW_MINOR_VERSION             0
+#define QSPI_IP_VS_0_PBCFG_SW_PATCH_VERSION             0
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/* Defines for direct access to the virtual LUT table */
+
+
+/*==================================================================================================
+                                             ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/**@}*/
+
+#endif    /* #ifndef QSPI_IP_VS_0_PBCFG_H */

generate/include/Uart_Defines.h

@@ -92,7 +92,7 @@ extern "C"
 #define UART_TIMEOUT_TYPE               (OSIF_COUNTER_SYSTEM)
 
 /* @brief Number of loops before returning Timeout status */
-#define UART_TIMEOUT_VALUE_US           (500000U)
+#define UART_TIMEOUT_VALUE_US           (100000U)
 
 /* @brief Switches the Uart_GetVersionInfo() API ON or OFF. Support for version info API. */
 #define UART_VERSION_INFO_API           (STD_ON)

generate/include/modules.h

@@ -168,7 +168,7 @@ extern "C" {
 * @brief This constant used for other modules to check if FLS is present in the project.  
 * @violates @ref modules_h_REF_1 MISRA 2012 Advisory Rule 2.5, unused macro. 
 */
-#define USE_FLS_MODULE              (STD_OFF)
+#define USE_FLS_MODULE              (STD_ON)
 
 /** 
 * @brief This constant used for other modules to check if Fr is present in the project.  

generate/src/Fls_Cfg.c

@@ -0,0 +1,102 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+/*==================================================================================================
+==================================================================================================*/
+
+/**
+*   @file Fls_Cfg.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Fls_Cfg.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls.h"
+#ifdef FLS_PRECOMPILE_SUPPORT
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VENDOR_ID_PCFG_C                      43
+#define FLS_AR_RELEASE_MAJOR_VERSION_PCFG_C       4
+#define FLS_AR_RELEASE_MINOR_VERSION_PCFG_C       4
+#define FLS_AR_RELEASE_REVISION_VERSION_PCFG_C    0
+#define FLS_SW_MAJOR_VERSION_PCFG_C               1
+#define FLS_SW_MINOR_VERSION_PCFG_C               0
+#define FLS_SW_PATCH_VERSION_PCFG_C               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls header file are of the same vendor */
+#if (FLS_VENDOR_ID_PCFG_C != FLS_VENDOR_ID)
+    #error "Fls_Cfg.c and Fls.h have different vendor ids"
+#endif
+/* Check if current file and Fls header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_PCFG_C    != FLS_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_PCFG_C    != FLS_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_PCFG_C != FLS_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls_Cfg.c and Fls.h are different"
+#endif
+/* Check if current file and Fls header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_PCFG_C != FLS_SW_MAJOR_VERSION) || \
+     (FLS_SW_MINOR_VERSION_PCFG_C != FLS_SW_MINOR_VERSION) || \
+     (FLS_SW_PATCH_VERSION_PCFG_C != FLS_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_Cfg.c and Fls.h are different"
+#endif
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+
+
+
+
+
+#endif /* FLS_PRECOMPILE_SUPPORT */
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/

generate/src/Fls_VS_0_PBcfg.c

@@ -0,0 +1,2148 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Fls_VS_0_PBcfg.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Fls_PBcfg.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Fls.h"
+#include "Qspi_Ip_Features.h"
+#include "Qspi_Ip_Cfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_VENDOR_ID_CFG_C                      43
+#define FLS_AR_RELEASE_MAJOR_VERSION_CFG_C       4
+#define FLS_AR_RELEASE_MINOR_VERSION_CFG_C       4
+#define FLS_AR_RELEASE_REVISION_VERSION_CFG_C    0
+#define FLS_SW_MAJOR_VERSION_CFG_C               1
+#define FLS_SW_MINOR_VERSION_CFG_C               0
+#define FLS_SW_PATCH_VERSION_CFG_C               0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Fls header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG_C != FLS_VENDOR_ID)
+    #error "Fls_PBcfg.c and Fls.h have different vendor ids"
+#endif
+/* Check if current file and Fls header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG_C    != FLS_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG_C    != FLS_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG_C != FLS_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Fls_PBcfg.c and Fls.h are different"
+#endif
+/* Check if current file and Fls header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG_C != FLS_SW_MAJOR_VERSION) || \
+     (FLS_SW_MINOR_VERSION_CFG_C != FLS_SW_MINOR_VERSION) || \
+     (FLS_SW_PATCH_VERSION_CFG_C != FLS_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Fls_PBcfg.c and Fls.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG_C != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Fls_PBcfg.c and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG_C    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG_C    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG_C != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_PBcfg.c and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG_C != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (FLS_SW_MINOR_VERSION_CFG_C != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (FLS_SW_PATCH_VERSION_CFG_C != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_PBcfg.c and Qspi_Ip_Features.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Cfg header file are of the same vendor */
+#if (FLS_VENDOR_ID_CFG_C != QSPI_IP_VENDOR_ID_CFG)
+    #error "Fls_PBcfg.c and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Autosar version */
+#if ((FLS_AR_RELEASE_MAJOR_VERSION_CFG_C    != QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_MINOR_VERSION_CFG_C    != QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_AR_RELEASE_REVISION_VERSION_CFG_C != QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Fls_PBcfg.c and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg header file are of the same Software version */
+#if ((FLS_SW_MAJOR_VERSION_CFG_C != QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLS_SW_MINOR_VERSION_CFG_C != QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLS_SW_PATCH_VERSION_CFG_C != QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Fls_PBcfg.c and Qspi_Ip_Cfg.h are different"
+#endif
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+#define FLS_START_SEC_CODE
+#include "Fls_MemMap.h"
+
+/* Declaration of Fls Access Code Pointer (_ERASE_FUNC_ADDRESS_)*/
+extern void _ERASE_FUNC_ADDRESS_(void);
+
+/* Declaration of Fls Access Code Pointer (_WRITE_FUNC_ADDRESS_)*/
+extern void _WRITE_FUNC_ADDRESS_(void);
+
+#define FLS_STOP_SEC_CODE
+#include "Fls_MemMap.h"
+#define FLS_START_SEC_CONFIG_DATA_8
+#include "Fls_MemMap.h"
+
+/* aFlsSectorFlags */
+static const uint8 FlsConfigSet_VS_0_aFlsSectorFlags[128U] =
+{
+    0U,  /* FlsSector_0 */
+    0U,  /* FlsSector_1 */
+    0U,  /* FlsSector_2 */
+    0U,  /* FlsSector_3 */
+    0U,  /* FlsSector_4 */
+    0U,  /* FlsSector_5 */
+    0U,  /* FlsSector_6 */
+    0U,  /* FlsSector_7 */
+    0U,  /* FlsSector_8 */
+    0U,  /* FlsSector_9 */
+    0U,  /* FlsSector_10 */
+    0U,  /* FlsSector_11 */
+    0U,  /* FlsSector_12 */
+    0U,  /* FlsSector_13 */
+    0U,  /* FlsSector_14 */
+    0U,  /* FlsSector_15 */
+    0U,  /* FlsSector_16 */
+    0U,  /* FlsSector_17 */
+    0U,  /* FlsSector_18 */
+    0U,  /* FlsSector_19 */
+    0U,  /* FlsSector_20 */
+    0U,  /* FlsSector_21 */
+    0U,  /* FlsSector_22 */
+    0U,  /* FlsSector_23 */
+    0U,  /* FlsSector_24 */
+    0U,  /* FlsSector_25 */
+    0U,  /* FlsSector_26 */
+    0U,  /* FlsSector_27 */
+    0U,  /* FlsSector_28 */
+    0U,  /* FlsSector_29 */
+    0U,  /* FlsSector_30 */
+    0U,  /* FlsSector_31 */
+    0U,  /* FlsSector_32 */
+    0U,  /* FlsSector_33 */
+    0U,  /* FlsSector_34 */
+    0U,  /* FlsSector_35 */
+    0U,  /* FlsSector_36 */
+    0U,  /* FlsSector_37 */
+    0U,  /* FlsSector_38 */
+    0U,  /* FlsSector_39 */
+    0U,  /* FlsSector_40 */
+    0U,  /* FlsSector_41 */
+    0U,  /* FlsSector_42 */
+    0U,  /* FlsSector_43 */
+    0U,  /* FlsSector_44 */
+    0U,  /* FlsSector_45 */
+    0U,  /* FlsSector_46 */
+    0U,  /* FlsSector_47 */
+    0U,  /* FlsSector_48 */
+    0U,  /* FlsSector_49 */
+    0U,  /* FlsSector_50 */
+    0U,  /* FlsSector_51 */
+    0U,  /* FlsSector_52 */
+    0U,  /* FlsSector_53 */
+    0U,  /* FlsSector_54 */
+    0U,  /* FlsSector_55 */
+    0U,  /* FlsSector_56 */
+    0U,  /* FlsSector_57 */
+    0U,  /* FlsSector_58 */
+    0U,  /* FlsSector_59 */
+    0U,  /* FlsSector_60 */
+    0U,  /* FlsSector_61 */
+    0U,  /* FlsSector_62 */
+    0U,  /* FlsSector_63 */
+    0U,  /* FlsSector_64 */
+    0U,  /* FlsSector_65 */
+    0U,  /* FlsSector_66 */
+    0U,  /* FlsSector_67 */
+    0U,  /* FlsSector_68 */
+    0U,  /* FlsSector_69 */
+    0U,  /* FlsSector_70 */
+    0U,  /* FlsSector_71 */
+    0U,  /* FlsSector_72 */
+    0U,  /* FlsSector_73 */
+    0U,  /* FlsSector_74 */
+    0U,  /* FlsSector_75 */
+    0U,  /* FlsSector_76 */
+    0U,  /* FlsSector_77 */
+    0U,  /* FlsSector_78 */
+    0U,  /* FlsSector_79 */
+    0U,  /* FlsSector_80 */
+    0U,  /* FlsSector_81 */
+    0U,  /* FlsSector_82 */
+    0U,  /* FlsSector_83 */
+    0U,  /* FlsSector_84 */
+    0U,  /* FlsSector_85 */
+    0U,  /* FlsSector_86 */
+    0U,  /* FlsSector_87 */
+    0U,  /* FlsSector_88 */
+    0U,  /* FlsSector_89 */
+    0U,  /* FlsSector_90 */
+    0U,  /* FlsSector_91 */
+    0U,  /* FlsSector_92 */
+    0U,  /* FlsSector_93 */
+    0U,  /* FlsSector_94 */
+    0U,  /* FlsSector_95 */
+    0U,  /* FlsSector_96 */
+    0U,  /* FlsSector_97 */
+    0U,  /* FlsSector_98 */
+    0U,  /* FlsSector_99 */
+    0U,  /* FlsSector_100 */
+    0U,  /* FlsSector_101 */
+    0U,  /* FlsSector_102 */
+    0U,  /* FlsSector_103 */
+    0U,  /* FlsSector_104 */
+    0U,  /* FlsSector_105 */
+    0U,  /* FlsSector_106 */
+    0U,  /* FlsSector_107 */
+    0U,  /* FlsSector_108 */
+    0U,  /* FlsSector_109 */
+    0U,  /* FlsSector_110 */
+    0U,  /* FlsSector_111 */
+    0U,  /* FlsSector_112 */
+    0U,  /* FlsSector_113 */
+    0U,  /* FlsSector_114 */
+    0U,  /* FlsSector_115 */
+    0U,  /* FlsSector_116 */
+    0U,  /* FlsSector_117 */
+    0U,  /* FlsSector_118 */
+    0U,  /* FlsSector_119 */
+    0U,  /* FlsSector_120 */
+    0U,  /* FlsSector_121 */
+    0U,  /* FlsSector_122 */
+    0U,  /* FlsSector_123 */
+    0U,  /* FlsSector_124 */
+    0U,  /* FlsSector_125 */
+    0U,  /* FlsSector_126 */
+    0U   /* FlsSector_127 */
+};
+
+#define FLS_STOP_SEC_CONFIG_DATA_8
+#include "Fls_MemMap.h"
+
+
+
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* aFlsSectorEndAddr */
+static const Fls_AddressType FlsConfigSet_VS_0_aFlsSectorEndAddr[128U] =
+{
+    (Fls_AddressType)4095U,  /* FlsSector_0 */
+    (Fls_AddressType)8191U,  /* FlsSector_1 */
+    (Fls_AddressType)12287U,  /* FlsSector_2 */
+    (Fls_AddressType)16383U,  /* FlsSector_3 */
+    (Fls_AddressType)20479U,  /* FlsSector_4 */
+    (Fls_AddressType)24575U,  /* FlsSector_5 */
+    (Fls_AddressType)28671U,  /* FlsSector_6 */
+    (Fls_AddressType)32767U,  /* FlsSector_7 */
+    (Fls_AddressType)36863U,  /* FlsSector_8 */
+    (Fls_AddressType)40959U,  /* FlsSector_9 */
+    (Fls_AddressType)45055U,  /* FlsSector_10 */
+    (Fls_AddressType)49151U,  /* FlsSector_11 */
+    (Fls_AddressType)53247U,  /* FlsSector_12 */
+    (Fls_AddressType)57343U,  /* FlsSector_13 */
+    (Fls_AddressType)61439U,  /* FlsSector_14 */
+    (Fls_AddressType)65535U,  /* FlsSector_15 */
+    (Fls_AddressType)69631U,  /* FlsSector_16 */
+    (Fls_AddressType)73727U,  /* FlsSector_17 */
+    (Fls_AddressType)77823U,  /* FlsSector_18 */
+    (Fls_AddressType)81919U,  /* FlsSector_19 */
+    (Fls_AddressType)86015U,  /* FlsSector_20 */
+    (Fls_AddressType)90111U,  /* FlsSector_21 */
+    (Fls_AddressType)94207U,  /* FlsSector_22 */
+    (Fls_AddressType)98303U,  /* FlsSector_23 */
+    (Fls_AddressType)102399U,  /* FlsSector_24 */
+    (Fls_AddressType)106495U,  /* FlsSector_25 */
+    (Fls_AddressType)110591U,  /* FlsSector_26 */
+    (Fls_AddressType)114687U,  /* FlsSector_27 */
+    (Fls_AddressType)118783U,  /* FlsSector_28 */
+    (Fls_AddressType)122879U,  /* FlsSector_29 */
+    (Fls_AddressType)126975U,  /* FlsSector_30 */
+    (Fls_AddressType)131071U,  /* FlsSector_31 */
+    (Fls_AddressType)135167U,  /* FlsSector_32 */
+    (Fls_AddressType)139263U,  /* FlsSector_33 */
+    (Fls_AddressType)143359U,  /* FlsSector_34 */
+    (Fls_AddressType)147455U,  /* FlsSector_35 */
+    (Fls_AddressType)151551U,  /* FlsSector_36 */
+    (Fls_AddressType)155647U,  /* FlsSector_37 */
+    (Fls_AddressType)159743U,  /* FlsSector_38 */
+    (Fls_AddressType)163839U,  /* FlsSector_39 */
+    (Fls_AddressType)167935U,  /* FlsSector_40 */
+    (Fls_AddressType)172031U,  /* FlsSector_41 */
+    (Fls_AddressType)176127U,  /* FlsSector_42 */
+    (Fls_AddressType)180223U,  /* FlsSector_43 */
+    (Fls_AddressType)184319U,  /* FlsSector_44 */
+    (Fls_AddressType)188415U,  /* FlsSector_45 */
+    (Fls_AddressType)192511U,  /* FlsSector_46 */
+    (Fls_AddressType)196607U,  /* FlsSector_47 */
+    (Fls_AddressType)200703U,  /* FlsSector_48 */
+    (Fls_AddressType)204799U,  /* FlsSector_49 */
+    (Fls_AddressType)208895U,  /* FlsSector_50 */
+    (Fls_AddressType)212991U,  /* FlsSector_51 */
+    (Fls_AddressType)217087U,  /* FlsSector_52 */
+    (Fls_AddressType)221183U,  /* FlsSector_53 */
+    (Fls_AddressType)225279U,  /* FlsSector_54 */
+    (Fls_AddressType)229375U,  /* FlsSector_55 */
+    (Fls_AddressType)233471U,  /* FlsSector_56 */
+    (Fls_AddressType)237567U,  /* FlsSector_57 */
+    (Fls_AddressType)241663U,  /* FlsSector_58 */
+    (Fls_AddressType)245759U,  /* FlsSector_59 */
+    (Fls_AddressType)249855U,  /* FlsSector_60 */
+    (Fls_AddressType)253951U,  /* FlsSector_61 */
+    (Fls_AddressType)258047U,  /* FlsSector_62 */
+    (Fls_AddressType)262143U,  /* FlsSector_63 */
+    (Fls_AddressType)266239U,  /* FlsSector_64 */
+    (Fls_AddressType)270335U,  /* FlsSector_65 */
+    (Fls_AddressType)274431U,  /* FlsSector_66 */
+    (Fls_AddressType)278527U,  /* FlsSector_67 */
+    (Fls_AddressType)282623U,  /* FlsSector_68 */
+    (Fls_AddressType)286719U,  /* FlsSector_69 */
+    (Fls_AddressType)290815U,  /* FlsSector_70 */
+    (Fls_AddressType)294911U,  /* FlsSector_71 */
+    (Fls_AddressType)299007U,  /* FlsSector_72 */
+    (Fls_AddressType)303103U,  /* FlsSector_73 */
+    (Fls_AddressType)307199U,  /* FlsSector_74 */
+    (Fls_AddressType)311295U,  /* FlsSector_75 */
+    (Fls_AddressType)315391U,  /* FlsSector_76 */
+    (Fls_AddressType)319487U,  /* FlsSector_77 */
+    (Fls_AddressType)323583U,  /* FlsSector_78 */
+    (Fls_AddressType)327679U,  /* FlsSector_79 */
+    (Fls_AddressType)331775U,  /* FlsSector_80 */
+    (Fls_AddressType)335871U,  /* FlsSector_81 */
+    (Fls_AddressType)339967U,  /* FlsSector_82 */
+    (Fls_AddressType)344063U,  /* FlsSector_83 */
+    (Fls_AddressType)348159U,  /* FlsSector_84 */
+    (Fls_AddressType)352255U,  /* FlsSector_85 */
+    (Fls_AddressType)356351U,  /* FlsSector_86 */
+    (Fls_AddressType)360447U,  /* FlsSector_87 */
+    (Fls_AddressType)364543U,  /* FlsSector_88 */
+    (Fls_AddressType)368639U,  /* FlsSector_89 */
+    (Fls_AddressType)372735U,  /* FlsSector_90 */
+    (Fls_AddressType)376831U,  /* FlsSector_91 */
+    (Fls_AddressType)380927U,  /* FlsSector_92 */
+    (Fls_AddressType)385023U,  /* FlsSector_93 */
+    (Fls_AddressType)389119U,  /* FlsSector_94 */
+    (Fls_AddressType)393215U,  /* FlsSector_95 */
+    (Fls_AddressType)397311U,  /* FlsSector_96 */
+    (Fls_AddressType)401407U,  /* FlsSector_97 */
+    (Fls_AddressType)405503U,  /* FlsSector_98 */
+    (Fls_AddressType)409599U,  /* FlsSector_99 */
+    (Fls_AddressType)413695U,  /* FlsSector_100 */
+    (Fls_AddressType)417791U,  /* FlsSector_101 */
+    (Fls_AddressType)421887U,  /* FlsSector_102 */
+    (Fls_AddressType)425983U,  /* FlsSector_103 */
+    (Fls_AddressType)430079U,  /* FlsSector_104 */
+    (Fls_AddressType)434175U,  /* FlsSector_105 */
+    (Fls_AddressType)438271U,  /* FlsSector_106 */
+    (Fls_AddressType)442367U,  /* FlsSector_107 */
+    (Fls_AddressType)446463U,  /* FlsSector_108 */
+    (Fls_AddressType)450559U,  /* FlsSector_109 */
+    (Fls_AddressType)454655U,  /* FlsSector_110 */
+    (Fls_AddressType)458751U,  /* FlsSector_111 */
+    (Fls_AddressType)462847U,  /* FlsSector_112 */
+    (Fls_AddressType)466943U,  /* FlsSector_113 */
+    (Fls_AddressType)471039U,  /* FlsSector_114 */
+    (Fls_AddressType)475135U,  /* FlsSector_115 */
+    (Fls_AddressType)479231U,  /* FlsSector_116 */
+    (Fls_AddressType)483327U,  /* FlsSector_117 */
+    (Fls_AddressType)487423U,  /* FlsSector_118 */
+    (Fls_AddressType)491519U,  /* FlsSector_119 */
+    (Fls_AddressType)495615U,  /* FlsSector_120 */
+    (Fls_AddressType)499711U,  /* FlsSector_121 */
+    (Fls_AddressType)503807U,  /* FlsSector_122 */
+    (Fls_AddressType)507903U,  /* FlsSector_123 */
+    (Fls_AddressType)511999U,  /* FlsSector_124 */
+    (Fls_AddressType)516095U,  /* FlsSector_125 */
+    (Fls_AddressType)520191U,  /* FlsSector_126 */
+    (Fls_AddressType)524287U   /* FlsSector_127 */
+};
+
+/* paSectorSize */
+static const Fls_LengthType FlsConfigSet_VS_0_aFlsSectorSize[128U] =
+{
+    (Fls_LengthType)4096U,  /* FlsSector_0 */
+    (Fls_LengthType)4096U,  /* FlsSector_1 */
+    (Fls_LengthType)4096U,  /* FlsSector_2 */
+    (Fls_LengthType)4096U,  /* FlsSector_3 */
+    (Fls_LengthType)4096U,  /* FlsSector_4 */
+    (Fls_LengthType)4096U,  /* FlsSector_5 */
+    (Fls_LengthType)4096U,  /* FlsSector_6 */
+    (Fls_LengthType)4096U,  /* FlsSector_7 */
+    (Fls_LengthType)4096U,  /* FlsSector_8 */
+    (Fls_LengthType)4096U,  /* FlsSector_9 */
+    (Fls_LengthType)4096U,  /* FlsSector_10 */
+    (Fls_LengthType)4096U,  /* FlsSector_11 */
+    (Fls_LengthType)4096U,  /* FlsSector_12 */
+    (Fls_LengthType)4096U,  /* FlsSector_13 */
+    (Fls_LengthType)4096U,  /* FlsSector_14 */
+    (Fls_LengthType)4096U,  /* FlsSector_15 */
+    (Fls_LengthType)4096U,  /* FlsSector_16 */
+    (Fls_LengthType)4096U,  /* FlsSector_17 */
+    (Fls_LengthType)4096U,  /* FlsSector_18 */
+    (Fls_LengthType)4096U,  /* FlsSector_19 */
+    (Fls_LengthType)4096U,  /* FlsSector_20 */
+    (Fls_LengthType)4096U,  /* FlsSector_21 */
+    (Fls_LengthType)4096U,  /* FlsSector_22 */
+    (Fls_LengthType)4096U,  /* FlsSector_23 */
+    (Fls_LengthType)4096U,  /* FlsSector_24 */
+    (Fls_LengthType)4096U,  /* FlsSector_25 */
+    (Fls_LengthType)4096U,  /* FlsSector_26 */
+    (Fls_LengthType)4096U,  /* FlsSector_27 */
+    (Fls_LengthType)4096U,  /* FlsSector_28 */
+    (Fls_LengthType)4096U,  /* FlsSector_29 */
+    (Fls_LengthType)4096U,  /* FlsSector_30 */
+    (Fls_LengthType)4096U,  /* FlsSector_31 */
+    (Fls_LengthType)4096U,  /* FlsSector_32 */
+    (Fls_LengthType)4096U,  /* FlsSector_33 */
+    (Fls_LengthType)4096U,  /* FlsSector_34 */
+    (Fls_LengthType)4096U,  /* FlsSector_35 */
+    (Fls_LengthType)4096U,  /* FlsSector_36 */
+    (Fls_LengthType)4096U,  /* FlsSector_37 */
+    (Fls_LengthType)4096U,  /* FlsSector_38 */
+    (Fls_LengthType)4096U,  /* FlsSector_39 */
+    (Fls_LengthType)4096U,  /* FlsSector_40 */
+    (Fls_LengthType)4096U,  /* FlsSector_41 */
+    (Fls_LengthType)4096U,  /* FlsSector_42 */
+    (Fls_LengthType)4096U,  /* FlsSector_43 */
+    (Fls_LengthType)4096U,  /* FlsSector_44 */
+    (Fls_LengthType)4096U,  /* FlsSector_45 */
+    (Fls_LengthType)4096U,  /* FlsSector_46 */
+    (Fls_LengthType)4096U,  /* FlsSector_47 */
+    (Fls_LengthType)4096U,  /* FlsSector_48 */
+    (Fls_LengthType)4096U,  /* FlsSector_49 */
+    (Fls_LengthType)4096U,  /* FlsSector_50 */
+    (Fls_LengthType)4096U,  /* FlsSector_51 */
+    (Fls_LengthType)4096U,  /* FlsSector_52 */
+    (Fls_LengthType)4096U,  /* FlsSector_53 */
+    (Fls_LengthType)4096U,  /* FlsSector_54 */
+    (Fls_LengthType)4096U,  /* FlsSector_55 */
+    (Fls_LengthType)4096U,  /* FlsSector_56 */
+    (Fls_LengthType)4096U,  /* FlsSector_57 */
+    (Fls_LengthType)4096U,  /* FlsSector_58 */
+    (Fls_LengthType)4096U,  /* FlsSector_59 */
+    (Fls_LengthType)4096U,  /* FlsSector_60 */
+    (Fls_LengthType)4096U,  /* FlsSector_61 */
+    (Fls_LengthType)4096U,  /* FlsSector_62 */
+    (Fls_LengthType)4096U,  /* FlsSector_63 */
+    (Fls_LengthType)4096U,  /* FlsSector_64 */
+    (Fls_LengthType)4096U,  /* FlsSector_65 */
+    (Fls_LengthType)4096U,  /* FlsSector_66 */
+    (Fls_LengthType)4096U,  /* FlsSector_67 */
+    (Fls_LengthType)4096U,  /* FlsSector_68 */
+    (Fls_LengthType)4096U,  /* FlsSector_69 */
+    (Fls_LengthType)4096U,  /* FlsSector_70 */
+    (Fls_LengthType)4096U,  /* FlsSector_71 */
+    (Fls_LengthType)4096U,  /* FlsSector_72 */
+    (Fls_LengthType)4096U,  /* FlsSector_73 */
+    (Fls_LengthType)4096U,  /* FlsSector_74 */
+    (Fls_LengthType)4096U,  /* FlsSector_75 */
+    (Fls_LengthType)4096U,  /* FlsSector_76 */
+    (Fls_LengthType)4096U,  /* FlsSector_77 */
+    (Fls_LengthType)4096U,  /* FlsSector_78 */
+    (Fls_LengthType)4096U,  /* FlsSector_79 */
+    (Fls_LengthType)4096U,  /* FlsSector_80 */
+    (Fls_LengthType)4096U,  /* FlsSector_81 */
+    (Fls_LengthType)4096U,  /* FlsSector_82 */
+    (Fls_LengthType)4096U,  /* FlsSector_83 */
+    (Fls_LengthType)4096U,  /* FlsSector_84 */
+    (Fls_LengthType)4096U,  /* FlsSector_85 */
+    (Fls_LengthType)4096U,  /* FlsSector_86 */
+    (Fls_LengthType)4096U,  /* FlsSector_87 */
+    (Fls_LengthType)4096U,  /* FlsSector_88 */
+    (Fls_LengthType)4096U,  /* FlsSector_89 */
+    (Fls_LengthType)4096U,  /* FlsSector_90 */
+    (Fls_LengthType)4096U,  /* FlsSector_91 */
+    (Fls_LengthType)4096U,  /* FlsSector_92 */
+    (Fls_LengthType)4096U,  /* FlsSector_93 */
+    (Fls_LengthType)4096U,  /* FlsSector_94 */
+    (Fls_LengthType)4096U,  /* FlsSector_95 */
+    (Fls_LengthType)4096U,  /* FlsSector_96 */
+    (Fls_LengthType)4096U,  /* FlsSector_97 */
+    (Fls_LengthType)4096U,  /* FlsSector_98 */
+    (Fls_LengthType)4096U,  /* FlsSector_99 */
+    (Fls_LengthType)4096U,  /* FlsSector_100 */
+    (Fls_LengthType)4096U,  /* FlsSector_101 */
+    (Fls_LengthType)4096U,  /* FlsSector_102 */
+    (Fls_LengthType)4096U,  /* FlsSector_103 */
+    (Fls_LengthType)4096U,  /* FlsSector_104 */
+    (Fls_LengthType)4096U,  /* FlsSector_105 */
+    (Fls_LengthType)4096U,  /* FlsSector_106 */
+    (Fls_LengthType)4096U,  /* FlsSector_107 */
+    (Fls_LengthType)4096U,  /* FlsSector_108 */
+    (Fls_LengthType)4096U,  /* FlsSector_109 */
+    (Fls_LengthType)4096U,  /* FlsSector_110 */
+    (Fls_LengthType)4096U,  /* FlsSector_111 */
+    (Fls_LengthType)4096U,  /* FlsSector_112 */
+    (Fls_LengthType)4096U,  /* FlsSector_113 */
+    (Fls_LengthType)4096U,  /* FlsSector_114 */
+    (Fls_LengthType)4096U,  /* FlsSector_115 */
+    (Fls_LengthType)4096U,  /* FlsSector_116 */
+    (Fls_LengthType)4096U,  /* FlsSector_117 */
+    (Fls_LengthType)4096U,  /* FlsSector_118 */
+    (Fls_LengthType)4096U,  /* FlsSector_119 */
+    (Fls_LengthType)4096U,  /* FlsSector_120 */
+    (Fls_LengthType)4096U,  /* FlsSector_121 */
+    (Fls_LengthType)4096U,  /* FlsSector_122 */
+    (Fls_LengthType)4096U,  /* FlsSector_123 */
+    (Fls_LengthType)4096U,  /* FlsSector_124 */
+    (Fls_LengthType)4096U,  /* FlsSector_125 */
+    (Fls_LengthType)4096U,  /* FlsSector_126 */
+    (Fls_LengthType)4096U   /* FlsSector_127 */
+};
+
+/* paSectorPageSize */
+static const Fls_LengthType FlsConfigSet_VS_0_aFlsSectorPageSize[128U] =
+{
+    (Fls_LengthType)8U,  /* FlsSector_0 */
+    (Fls_LengthType)8U,  /* FlsSector_1 */
+    (Fls_LengthType)8U,  /* FlsSector_2 */
+    (Fls_LengthType)8U,  /* FlsSector_3 */
+    (Fls_LengthType)8U,  /* FlsSector_4 */
+    (Fls_LengthType)8U,  /* FlsSector_5 */
+    (Fls_LengthType)8U,  /* FlsSector_6 */
+    (Fls_LengthType)8U,  /* FlsSector_7 */
+    (Fls_LengthType)8U,  /* FlsSector_8 */
+    (Fls_LengthType)8U,  /* FlsSector_9 */
+    (Fls_LengthType)8U,  /* FlsSector_10 */
+    (Fls_LengthType)8U,  /* FlsSector_11 */
+    (Fls_LengthType)8U,  /* FlsSector_12 */
+    (Fls_LengthType)8U,  /* FlsSector_13 */
+    (Fls_LengthType)8U,  /* FlsSector_14 */
+    (Fls_LengthType)8U,  /* FlsSector_15 */
+    (Fls_LengthType)8U,  /* FlsSector_16 */
+    (Fls_LengthType)8U,  /* FlsSector_17 */
+    (Fls_LengthType)8U,  /* FlsSector_18 */
+    (Fls_LengthType)8U,  /* FlsSector_19 */
+    (Fls_LengthType)8U,  /* FlsSector_20 */
+    (Fls_LengthType)8U,  /* FlsSector_21 */
+    (Fls_LengthType)8U,  /* FlsSector_22 */
+    (Fls_LengthType)8U,  /* FlsSector_23 */
+    (Fls_LengthType)8U,  /* FlsSector_24 */
+    (Fls_LengthType)8U,  /* FlsSector_25 */
+    (Fls_LengthType)8U,  /* FlsSector_26 */
+    (Fls_LengthType)8U,  /* FlsSector_27 */
+    (Fls_LengthType)8U,  /* FlsSector_28 */
+    (Fls_LengthType)8U,  /* FlsSector_29 */
+    (Fls_LengthType)8U,  /* FlsSector_30 */
+    (Fls_LengthType)8U,  /* FlsSector_31 */
+    (Fls_LengthType)8U,  /* FlsSector_32 */
+    (Fls_LengthType)8U,  /* FlsSector_33 */
+    (Fls_LengthType)8U,  /* FlsSector_34 */
+    (Fls_LengthType)8U,  /* FlsSector_35 */
+    (Fls_LengthType)8U,  /* FlsSector_36 */
+    (Fls_LengthType)8U,  /* FlsSector_37 */
+    (Fls_LengthType)8U,  /* FlsSector_38 */
+    (Fls_LengthType)8U,  /* FlsSector_39 */
+    (Fls_LengthType)8U,  /* FlsSector_40 */
+    (Fls_LengthType)8U,  /* FlsSector_41 */
+    (Fls_LengthType)8U,  /* FlsSector_42 */
+    (Fls_LengthType)8U,  /* FlsSector_43 */
+    (Fls_LengthType)8U,  /* FlsSector_44 */
+    (Fls_LengthType)8U,  /* FlsSector_45 */
+    (Fls_LengthType)8U,  /* FlsSector_46 */
+    (Fls_LengthType)8U,  /* FlsSector_47 */
+    (Fls_LengthType)8U,  /* FlsSector_48 */
+    (Fls_LengthType)8U,  /* FlsSector_49 */
+    (Fls_LengthType)8U,  /* FlsSector_50 */
+    (Fls_LengthType)8U,  /* FlsSector_51 */
+    (Fls_LengthType)8U,  /* FlsSector_52 */
+    (Fls_LengthType)8U,  /* FlsSector_53 */
+    (Fls_LengthType)8U,  /* FlsSector_54 */
+    (Fls_LengthType)8U,  /* FlsSector_55 */
+    (Fls_LengthType)8U,  /* FlsSector_56 */
+    (Fls_LengthType)8U,  /* FlsSector_57 */
+    (Fls_LengthType)8U,  /* FlsSector_58 */
+    (Fls_LengthType)8U,  /* FlsSector_59 */
+    (Fls_LengthType)8U,  /* FlsSector_60 */
+    (Fls_LengthType)8U,  /* FlsSector_61 */
+    (Fls_LengthType)8U,  /* FlsSector_62 */
+    (Fls_LengthType)8U,  /* FlsSector_63 */
+    (Fls_LengthType)8U,  /* FlsSector_64 */
+    (Fls_LengthType)8U,  /* FlsSector_65 */
+    (Fls_LengthType)8U,  /* FlsSector_66 */
+    (Fls_LengthType)8U,  /* FlsSector_67 */
+    (Fls_LengthType)8U,  /* FlsSector_68 */
+    (Fls_LengthType)8U,  /* FlsSector_69 */
+    (Fls_LengthType)8U,  /* FlsSector_70 */
+    (Fls_LengthType)8U,  /* FlsSector_71 */
+    (Fls_LengthType)8U,  /* FlsSector_72 */
+    (Fls_LengthType)8U,  /* FlsSector_73 */
+    (Fls_LengthType)8U,  /* FlsSector_74 */
+    (Fls_LengthType)8U,  /* FlsSector_75 */
+    (Fls_LengthType)8U,  /* FlsSector_76 */
+    (Fls_LengthType)8U,  /* FlsSector_77 */
+    (Fls_LengthType)8U,  /* FlsSector_78 */
+    (Fls_LengthType)8U,  /* FlsSector_79 */
+    (Fls_LengthType)8U,  /* FlsSector_80 */
+    (Fls_LengthType)8U,  /* FlsSector_81 */
+    (Fls_LengthType)8U,  /* FlsSector_82 */
+    (Fls_LengthType)8U,  /* FlsSector_83 */
+    (Fls_LengthType)8U,  /* FlsSector_84 */
+    (Fls_LengthType)8U,  /* FlsSector_85 */
+    (Fls_LengthType)8U,  /* FlsSector_86 */
+    (Fls_LengthType)8U,  /* FlsSector_87 */
+    (Fls_LengthType)8U,  /* FlsSector_88 */
+    (Fls_LengthType)8U,  /* FlsSector_89 */
+    (Fls_LengthType)8U,  /* FlsSector_90 */
+    (Fls_LengthType)8U,  /* FlsSector_91 */
+    (Fls_LengthType)8U,  /* FlsSector_92 */
+    (Fls_LengthType)8U,  /* FlsSector_93 */
+    (Fls_LengthType)8U,  /* FlsSector_94 */
+    (Fls_LengthType)8U,  /* FlsSector_95 */
+    (Fls_LengthType)8U,  /* FlsSector_96 */
+    (Fls_LengthType)8U,  /* FlsSector_97 */
+    (Fls_LengthType)8U,  /* FlsSector_98 */
+    (Fls_LengthType)8U,  /* FlsSector_99 */
+    (Fls_LengthType)8U,  /* FlsSector_100 */
+    (Fls_LengthType)8U,  /* FlsSector_101 */
+    (Fls_LengthType)8U,  /* FlsSector_102 */
+    (Fls_LengthType)8U,  /* FlsSector_103 */
+    (Fls_LengthType)8U,  /* FlsSector_104 */
+    (Fls_LengthType)8U,  /* FlsSector_105 */
+    (Fls_LengthType)8U,  /* FlsSector_106 */
+    (Fls_LengthType)8U,  /* FlsSector_107 */
+    (Fls_LengthType)8U,  /* FlsSector_108 */
+    (Fls_LengthType)8U,  /* FlsSector_109 */
+    (Fls_LengthType)8U,  /* FlsSector_110 */
+    (Fls_LengthType)8U,  /* FlsSector_111 */
+    (Fls_LengthType)8U,  /* FlsSector_112 */
+    (Fls_LengthType)8U,  /* FlsSector_113 */
+    (Fls_LengthType)8U,  /* FlsSector_114 */
+    (Fls_LengthType)8U,  /* FlsSector_115 */
+    (Fls_LengthType)8U,  /* FlsSector_116 */
+    (Fls_LengthType)8U,  /* FlsSector_117 */
+    (Fls_LengthType)8U,  /* FlsSector_118 */
+    (Fls_LengthType)8U,  /* FlsSector_119 */
+    (Fls_LengthType)8U,  /* FlsSector_120 */
+    (Fls_LengthType)8U,  /* FlsSector_121 */
+    (Fls_LengthType)8U,  /* FlsSector_122 */
+    (Fls_LengthType)8U,  /* FlsSector_123 */
+    (Fls_LengthType)8U,  /* FlsSector_124 */
+    (Fls_LengthType)8U,  /* FlsSector_125 */
+    (Fls_LengthType)8U,  /* FlsSector_126 */
+    (Fls_LengthType)8U   /* FlsSector_127 */
+};
+
+/* Info structure (reg prot, ecc trigger, etc) for each internal flash sector. */
+static const Fls_Flash_InternalSectorInfoType FlsSector_0_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x080000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    160U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_1_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x081000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    161U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_2_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x082000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    162U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_3_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x083000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    163U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_4_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x084000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    164U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_5_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x085000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    165U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_6_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x086000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    166U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_7_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x087000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    167U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_8_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x088000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    168U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_9_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x089000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    169U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_10_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08A000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    170U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_11_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08B000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    171U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_12_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08C000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    172U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_13_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08D000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    173U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_14_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08E000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    174U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_15_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x08F000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    175U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_16_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x090000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    176U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_17_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x091000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    177U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_18_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x092000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    178U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_19_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x093000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    179U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_20_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x094000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    180U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_21_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x095000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    181U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_22_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x096000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    182U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_23_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x097000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    183U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_24_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x098000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    184U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_25_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x099000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    185U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_26_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09A000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    186U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_27_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09B000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    187U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_28_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09C000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    188U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_29_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09D000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    189U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_30_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09E000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    190U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_31_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x09F000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    191U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_32_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    192U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_33_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    193U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_34_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    194U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_35_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    195U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_36_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    196U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_37_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    197U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_38_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    198U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_39_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    199U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_40_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A8000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    200U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_41_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0A9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    201U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_42_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    202U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_43_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    203U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_44_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    204U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_45_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AD000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    205U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_46_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    206U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_47_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0AF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    207U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_48_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    208U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_49_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    209U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_50_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    210U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_51_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    211U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_52_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    212U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_53_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    213U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_54_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    214U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_55_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    215U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_56_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B8000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    216U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_57_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0B9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    217U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_58_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    218U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_59_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    219U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_60_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    220U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_61_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BD000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    221U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_62_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    222U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_63_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0BF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    223U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_64_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    224U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_65_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    225U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_66_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    226U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_67_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    227U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_68_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    228U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_69_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    229U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_70_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    230U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_71_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    231U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_72_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C8000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    232U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_73_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0C9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    233U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_74_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    234U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_75_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    235U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_76_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    236U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_77_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CD000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    237U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_78_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    238U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_79_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0CF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    239U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_80_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    240U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_81_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    241U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_82_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    242U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_83_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    243U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_84_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    244U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_85_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    245U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_86_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    246U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_87_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    247U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_88_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x038000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_0), /* code block 0 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    88U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_89_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0D9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    249U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_90_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    250U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_91_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    251U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_92_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    252U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_93_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DD000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    253U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_94_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    254U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_95_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0DF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    255U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_96_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    256U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_97_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    257U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_98_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    258U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_99_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    259U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_100_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    260U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_101_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    261U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_102_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    262U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_103_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    263U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_104_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E8000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    264U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_105_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0E9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    265U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_106_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0EA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    266U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_107_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0EB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    267U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_108_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0EC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    268U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_109_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0ED000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    269U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_110_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0EE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    270U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_111_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0EF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    271U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_112_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F0000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    272U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_113_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F1000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    273U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_114_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F2000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    274U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_115_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F3000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    275U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_116_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F4000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    276U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_117_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F5000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    277U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_118_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F6000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    278U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_119_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F7000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    279U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_120_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F8000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    280U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_121_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0F9000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    281U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_122_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FA000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    282U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_123_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FB000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    283U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_124_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FC000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    284U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_125_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FD000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    285U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_126_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FE000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    286U  /* Sector location to calculate cfgCRC */
+};
+
+static const Fls_Flash_InternalSectorInfoType FlsSector_127_FlsConfigSet_VS_0_sInternalSectorInfo =
+{
+    (FLS_PROGRAM_FLASH_BASE_ADDR + 0x0FF000UL),  /* pSectorStartAddressPtr */
+    (Fls_BlockNumberOfSectorType)(FLS_CODE_BLOCK_1), /* code block 1 */
+    (boolean)TRUE,  /* bEccTriggersExc */
+    287U  /* Sector location to calculate cfgCRC */
+};
+
+
+/* FLASH physical sectorization description */
+static const Fls_Flash_InternalSectorInfoType * const FlsConfigSet_VS_0_aSectorList[128U] =
+{
+    &FlsSector_0_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S128 */
+    &FlsSector_1_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S129 */
+    &FlsSector_2_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S130 */
+    &FlsSector_3_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S131 */
+    &FlsSector_4_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S132 */
+    &FlsSector_5_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S133 */
+    &FlsSector_6_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S134 */
+    &FlsSector_7_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S135 */
+    &FlsSector_8_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S136 */
+    &FlsSector_9_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S137 */
+    &FlsSector_10_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S138 */
+    &FlsSector_11_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S139 */
+    &FlsSector_12_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S140 */
+    &FlsSector_13_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S141 */
+    &FlsSector_14_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S142 */
+    &FlsSector_15_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S143 */
+    &FlsSector_16_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S144 */
+    &FlsSector_17_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S145 */
+    &FlsSector_18_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S146 */
+    &FlsSector_19_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S147 */
+    &FlsSector_20_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S148 */
+    &FlsSector_21_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S149 */
+    &FlsSector_22_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S150 */
+    &FlsSector_23_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S151 */
+    &FlsSector_24_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S152 */
+    &FlsSector_25_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S153 */
+    &FlsSector_26_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S154 */
+    &FlsSector_27_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S155 */
+    &FlsSector_28_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S156 */
+    &FlsSector_29_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S157 */
+    &FlsSector_30_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S158 */
+    &FlsSector_31_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S159 */
+    &FlsSector_32_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S160 */
+    &FlsSector_33_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S161 */
+    &FlsSector_34_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S162 */
+    &FlsSector_35_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S163 */
+    &FlsSector_36_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S164 */
+    &FlsSector_37_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S165 */
+    &FlsSector_38_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S166 */
+    &FlsSector_39_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S167 */
+    &FlsSector_40_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S168 */
+    &FlsSector_41_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S169 */
+    &FlsSector_42_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S170 */
+    &FlsSector_43_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S171 */
+    &FlsSector_44_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S172 */
+    &FlsSector_45_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S173 */
+    &FlsSector_46_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S174 */
+    &FlsSector_47_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S175 */
+    &FlsSector_48_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S176 */
+    &FlsSector_49_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S177 */
+    &FlsSector_50_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S178 */
+    &FlsSector_51_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S179 */
+    &FlsSector_52_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S180 */
+    &FlsSector_53_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S181 */
+    &FlsSector_54_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S182 */
+    &FlsSector_55_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S183 */
+    &FlsSector_56_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S184 */
+    &FlsSector_57_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S185 */
+    &FlsSector_58_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S186 */
+    &FlsSector_59_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S187 */
+    &FlsSector_60_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S188 */
+    &FlsSector_61_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S189 */
+    &FlsSector_62_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S190 */
+    &FlsSector_63_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S191 */
+    &FlsSector_64_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S192 */
+    &FlsSector_65_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S193 */
+    &FlsSector_66_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S194 */
+    &FlsSector_67_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S195 */
+    &FlsSector_68_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S196 */
+    &FlsSector_69_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S197 */
+    &FlsSector_70_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S198 */
+    &FlsSector_71_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S199 */
+    &FlsSector_72_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S200 */
+    &FlsSector_73_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S201 */
+    &FlsSector_74_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S202 */
+    &FlsSector_75_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S203 */
+    &FlsSector_76_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S204 */
+    &FlsSector_77_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S205 */
+    &FlsSector_78_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S206 */
+    &FlsSector_79_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S207 */
+    &FlsSector_80_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S208 */
+    &FlsSector_81_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S209 */
+    &FlsSector_82_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S210 */
+    &FlsSector_83_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S211 */
+    &FlsSector_84_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S212 */
+    &FlsSector_85_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S213 */
+    &FlsSector_86_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S214 */
+    &FlsSector_87_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S215 */
+    &FlsSector_88_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_0_S056 */
+    &FlsSector_89_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S217 */
+    &FlsSector_90_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S218 */
+    &FlsSector_91_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S219 */
+    &FlsSector_92_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S220 */
+    &FlsSector_93_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S221 */
+    &FlsSector_94_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S222 */
+    &FlsSector_95_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S223 */
+    &FlsSector_96_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S224 */
+    &FlsSector_97_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S225 */
+    &FlsSector_98_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S226 */
+    &FlsSector_99_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S227 */
+    &FlsSector_100_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S228 */
+    &FlsSector_101_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S229 */
+    &FlsSector_102_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S230 */
+    &FlsSector_103_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S231 */
+    &FlsSector_104_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S232 */
+    &FlsSector_105_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S233 */
+    &FlsSector_106_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S234 */
+    &FlsSector_107_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S235 */
+    &FlsSector_108_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S236 */
+    &FlsSector_109_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S237 */
+    &FlsSector_110_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S238 */
+    &FlsSector_111_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S239 */
+    &FlsSector_112_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S240 */
+    &FlsSector_113_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S241 */
+    &FlsSector_114_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S242 */
+    &FlsSector_115_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S243 */
+    &FlsSector_116_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S244 */
+    &FlsSector_117_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S245 */
+    &FlsSector_118_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S246 */
+    &FlsSector_119_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S247 */
+    &FlsSector_120_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S248 */
+    &FlsSector_121_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S249 */
+    &FlsSector_122_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S250 */
+    &FlsSector_123_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S251 */
+    &FlsSector_124_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S252 */
+    &FlsSector_125_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S253 */
+    &FlsSector_126_FlsConfigSet_VS_0_sInternalSectorInfo,  /* FLS_CODE_ARRAY_0_BLOCK_1_S254 */
+    &FlsSector_127_FlsConfigSet_VS_0_sInternalSectorInfo   /* FLS_CODE_ARRAY_0_BLOCK_1_S255 */
+};
+
+/* paHwCh */
+static const Fls_HwChType FlsConfigSet_VS_0_paHwCh[128U] =
+{
+    FLS_CH_INTERN,  /* FlsSector_0 */
+    FLS_CH_INTERN,  /* FlsSector_1 */
+    FLS_CH_INTERN,  /* FlsSector_2 */
+    FLS_CH_INTERN,  /* FlsSector_3 */
+    FLS_CH_INTERN,  /* FlsSector_4 */
+    FLS_CH_INTERN,  /* FlsSector_5 */
+    FLS_CH_INTERN,  /* FlsSector_6 */
+    FLS_CH_INTERN,  /* FlsSector_7 */
+    FLS_CH_INTERN,  /* FlsSector_8 */
+    FLS_CH_INTERN,  /* FlsSector_9 */
+    FLS_CH_INTERN,  /* FlsSector_10 */
+    FLS_CH_INTERN,  /* FlsSector_11 */
+    FLS_CH_INTERN,  /* FlsSector_12 */
+    FLS_CH_INTERN,  /* FlsSector_13 */
+    FLS_CH_INTERN,  /* FlsSector_14 */
+    FLS_CH_INTERN,  /* FlsSector_15 */
+    FLS_CH_INTERN,  /* FlsSector_16 */
+    FLS_CH_INTERN,  /* FlsSector_17 */
+    FLS_CH_INTERN,  /* FlsSector_18 */
+    FLS_CH_INTERN,  /* FlsSector_19 */
+    FLS_CH_INTERN,  /* FlsSector_20 */
+    FLS_CH_INTERN,  /* FlsSector_21 */
+    FLS_CH_INTERN,  /* FlsSector_22 */
+    FLS_CH_INTERN,  /* FlsSector_23 */
+    FLS_CH_INTERN,  /* FlsSector_24 */
+    FLS_CH_INTERN,  /* FlsSector_25 */
+    FLS_CH_INTERN,  /* FlsSector_26 */
+    FLS_CH_INTERN,  /* FlsSector_27 */
+    FLS_CH_INTERN,  /* FlsSector_28 */
+    FLS_CH_INTERN,  /* FlsSector_29 */
+    FLS_CH_INTERN,  /* FlsSector_30 */
+    FLS_CH_INTERN,  /* FlsSector_31 */
+    FLS_CH_INTERN,  /* FlsSector_32 */
+    FLS_CH_INTERN,  /* FlsSector_33 */
+    FLS_CH_INTERN,  /* FlsSector_34 */
+    FLS_CH_INTERN,  /* FlsSector_35 */
+    FLS_CH_INTERN,  /* FlsSector_36 */
+    FLS_CH_INTERN,  /* FlsSector_37 */
+    FLS_CH_INTERN,  /* FlsSector_38 */
+    FLS_CH_INTERN,  /* FlsSector_39 */
+    FLS_CH_INTERN,  /* FlsSector_40 */
+    FLS_CH_INTERN,  /* FlsSector_41 */
+    FLS_CH_INTERN,  /* FlsSector_42 */
+    FLS_CH_INTERN,  /* FlsSector_43 */
+    FLS_CH_INTERN,  /* FlsSector_44 */
+    FLS_CH_INTERN,  /* FlsSector_45 */
+    FLS_CH_INTERN,  /* FlsSector_46 */
+    FLS_CH_INTERN,  /* FlsSector_47 */
+    FLS_CH_INTERN,  /* FlsSector_48 */
+    FLS_CH_INTERN,  /* FlsSector_49 */
+    FLS_CH_INTERN,  /* FlsSector_50 */
+    FLS_CH_INTERN,  /* FlsSector_51 */
+    FLS_CH_INTERN,  /* FlsSector_52 */
+    FLS_CH_INTERN,  /* FlsSector_53 */
+    FLS_CH_INTERN,  /* FlsSector_54 */
+    FLS_CH_INTERN,  /* FlsSector_55 */
+    FLS_CH_INTERN,  /* FlsSector_56 */
+    FLS_CH_INTERN,  /* FlsSector_57 */
+    FLS_CH_INTERN,  /* FlsSector_58 */
+    FLS_CH_INTERN,  /* FlsSector_59 */
+    FLS_CH_INTERN,  /* FlsSector_60 */
+    FLS_CH_INTERN,  /* FlsSector_61 */
+    FLS_CH_INTERN,  /* FlsSector_62 */
+    FLS_CH_INTERN,  /* FlsSector_63 */
+    FLS_CH_INTERN,  /* FlsSector_64 */
+    FLS_CH_INTERN,  /* FlsSector_65 */
+    FLS_CH_INTERN,  /* FlsSector_66 */
+    FLS_CH_INTERN,  /* FlsSector_67 */
+    FLS_CH_INTERN,  /* FlsSector_68 */
+    FLS_CH_INTERN,  /* FlsSector_69 */
+    FLS_CH_INTERN,  /* FlsSector_70 */
+    FLS_CH_INTERN,  /* FlsSector_71 */
+    FLS_CH_INTERN,  /* FlsSector_72 */
+    FLS_CH_INTERN,  /* FlsSector_73 */
+    FLS_CH_INTERN,  /* FlsSector_74 */
+    FLS_CH_INTERN,  /* FlsSector_75 */
+    FLS_CH_INTERN,  /* FlsSector_76 */
+    FLS_CH_INTERN,  /* FlsSector_77 */
+    FLS_CH_INTERN,  /* FlsSector_78 */
+    FLS_CH_INTERN,  /* FlsSector_79 */
+    FLS_CH_INTERN,  /* FlsSector_80 */
+    FLS_CH_INTERN,  /* FlsSector_81 */
+    FLS_CH_INTERN,  /* FlsSector_82 */
+    FLS_CH_INTERN,  /* FlsSector_83 */
+    FLS_CH_INTERN,  /* FlsSector_84 */
+    FLS_CH_INTERN,  /* FlsSector_85 */
+    FLS_CH_INTERN,  /* FlsSector_86 */
+    FLS_CH_INTERN,  /* FlsSector_87 */
+    FLS_CH_INTERN,  /* FlsSector_88 */
+    FLS_CH_INTERN,  /* FlsSector_89 */
+    FLS_CH_INTERN,  /* FlsSector_90 */
+    FLS_CH_INTERN,  /* FlsSector_91 */
+    FLS_CH_INTERN,  /* FlsSector_92 */
+    FLS_CH_INTERN,  /* FlsSector_93 */
+    FLS_CH_INTERN,  /* FlsSector_94 */
+    FLS_CH_INTERN,  /* FlsSector_95 */
+    FLS_CH_INTERN,  /* FlsSector_96 */
+    FLS_CH_INTERN,  /* FlsSector_97 */
+    FLS_CH_INTERN,  /* FlsSector_98 */
+    FLS_CH_INTERN,  /* FlsSector_99 */
+    FLS_CH_INTERN,  /* FlsSector_100 */
+    FLS_CH_INTERN,  /* FlsSector_101 */
+    FLS_CH_INTERN,  /* FlsSector_102 */
+    FLS_CH_INTERN,  /* FlsSector_103 */
+    FLS_CH_INTERN,  /* FlsSector_104 */
+    FLS_CH_INTERN,  /* FlsSector_105 */
+    FLS_CH_INTERN,  /* FlsSector_106 */
+    FLS_CH_INTERN,  /* FlsSector_107 */
+    FLS_CH_INTERN,  /* FlsSector_108 */
+    FLS_CH_INTERN,  /* FlsSector_109 */
+    FLS_CH_INTERN,  /* FlsSector_110 */
+    FLS_CH_INTERN,  /* FlsSector_111 */
+    FLS_CH_INTERN,  /* FlsSector_112 */
+    FLS_CH_INTERN,  /* FlsSector_113 */
+    FLS_CH_INTERN,  /* FlsSector_114 */
+    FLS_CH_INTERN,  /* FlsSector_115 */
+    FLS_CH_INTERN,  /* FlsSector_116 */
+    FLS_CH_INTERN,  /* FlsSector_117 */
+    FLS_CH_INTERN,  /* FlsSector_118 */
+    FLS_CH_INTERN,  /* FlsSector_119 */
+    FLS_CH_INTERN,  /* FlsSector_120 */
+    FLS_CH_INTERN,  /* FlsSector_121 */
+    FLS_CH_INTERN,  /* FlsSector_122 */
+    FLS_CH_INTERN,  /* FlsSector_123 */
+    FLS_CH_INTERN,  /* FlsSector_124 */
+    FLS_CH_INTERN,  /* FlsSector_125 */
+    FLS_CH_INTERN,  /* FlsSector_126 */
+    FLS_CH_INTERN   /* FlsSector_127 */
+};
+
+/* paSectorHwAddress */
+static const Fls_AddressType FlsConfigSet_VS_0_paSectorHwAddress[128U] =
+{
+    (Fls_AddressType)0U,  /* FlsSector_0 */
+    (Fls_AddressType)0U,  /* FlsSector_1 */
+    (Fls_AddressType)0U,  /* FlsSector_2 */
+    (Fls_AddressType)0U,  /* FlsSector_3 */
+    (Fls_AddressType)0U,  /* FlsSector_4 */
+    (Fls_AddressType)0U,  /* FlsSector_5 */
+    (Fls_AddressType)0U,  /* FlsSector_6 */
+    (Fls_AddressType)0U,  /* FlsSector_7 */
+    (Fls_AddressType)0U,  /* FlsSector_8 */
+    (Fls_AddressType)0U,  /* FlsSector_9 */
+    (Fls_AddressType)0U,  /* FlsSector_10 */
+    (Fls_AddressType)0U,  /* FlsSector_11 */
+    (Fls_AddressType)0U,  /* FlsSector_12 */
+    (Fls_AddressType)0U,  /* FlsSector_13 */
+    (Fls_AddressType)0U,  /* FlsSector_14 */
+    (Fls_AddressType)0U,  /* FlsSector_15 */
+    (Fls_AddressType)0U,  /* FlsSector_16 */
+    (Fls_AddressType)0U,  /* FlsSector_17 */
+    (Fls_AddressType)0U,  /* FlsSector_18 */
+    (Fls_AddressType)0U,  /* FlsSector_19 */
+    (Fls_AddressType)0U,  /* FlsSector_20 */
+    (Fls_AddressType)0U,  /* FlsSector_21 */
+    (Fls_AddressType)0U,  /* FlsSector_22 */
+    (Fls_AddressType)0U,  /* FlsSector_23 */
+    (Fls_AddressType)0U,  /* FlsSector_24 */
+    (Fls_AddressType)0U,  /* FlsSector_25 */
+    (Fls_AddressType)0U,  /* FlsSector_26 */
+    (Fls_AddressType)0U,  /* FlsSector_27 */
+    (Fls_AddressType)0U,  /* FlsSector_28 */
+    (Fls_AddressType)0U,  /* FlsSector_29 */
+    (Fls_AddressType)0U,  /* FlsSector_30 */
+    (Fls_AddressType)0U,  /* FlsSector_31 */
+    (Fls_AddressType)0U,  /* FlsSector_32 */
+    (Fls_AddressType)0U,  /* FlsSector_33 */
+    (Fls_AddressType)0U,  /* FlsSector_34 */
+    (Fls_AddressType)0U,  /* FlsSector_35 */
+    (Fls_AddressType)0U,  /* FlsSector_36 */
+    (Fls_AddressType)0U,  /* FlsSector_37 */
+    (Fls_AddressType)0U,  /* FlsSector_38 */
+    (Fls_AddressType)0U,  /* FlsSector_39 */
+    (Fls_AddressType)0U,  /* FlsSector_40 */
+    (Fls_AddressType)0U,  /* FlsSector_41 */
+    (Fls_AddressType)0U,  /* FlsSector_42 */
+    (Fls_AddressType)0U,  /* FlsSector_43 */
+    (Fls_AddressType)0U,  /* FlsSector_44 */
+    (Fls_AddressType)0U,  /* FlsSector_45 */
+    (Fls_AddressType)0U,  /* FlsSector_46 */
+    (Fls_AddressType)0U,  /* FlsSector_47 */
+    (Fls_AddressType)0U,  /* FlsSector_48 */
+    (Fls_AddressType)0U,  /* FlsSector_49 */
+    (Fls_AddressType)0U,  /* FlsSector_50 */
+    (Fls_AddressType)0U,  /* FlsSector_51 */
+    (Fls_AddressType)0U,  /* FlsSector_52 */
+    (Fls_AddressType)0U,  /* FlsSector_53 */
+    (Fls_AddressType)0U,  /* FlsSector_54 */
+    (Fls_AddressType)0U,  /* FlsSector_55 */
+    (Fls_AddressType)0U,  /* FlsSector_56 */
+    (Fls_AddressType)0U,  /* FlsSector_57 */
+    (Fls_AddressType)0U,  /* FlsSector_58 */
+    (Fls_AddressType)0U,  /* FlsSector_59 */
+    (Fls_AddressType)0U,  /* FlsSector_60 */
+    (Fls_AddressType)0U,  /* FlsSector_61 */
+    (Fls_AddressType)0U,  /* FlsSector_62 */
+    (Fls_AddressType)0U,  /* FlsSector_63 */
+    (Fls_AddressType)0U,  /* FlsSector_64 */
+    (Fls_AddressType)0U,  /* FlsSector_65 */
+    (Fls_AddressType)0U,  /* FlsSector_66 */
+    (Fls_AddressType)0U,  /* FlsSector_67 */
+    (Fls_AddressType)0U,  /* FlsSector_68 */
+    (Fls_AddressType)0U,  /* FlsSector_69 */
+    (Fls_AddressType)0U,  /* FlsSector_70 */
+    (Fls_AddressType)0U,  /* FlsSector_71 */
+    (Fls_AddressType)0U,  /* FlsSector_72 */
+    (Fls_AddressType)0U,  /* FlsSector_73 */
+    (Fls_AddressType)0U,  /* FlsSector_74 */
+    (Fls_AddressType)0U,  /* FlsSector_75 */
+    (Fls_AddressType)0U,  /* FlsSector_76 */
+    (Fls_AddressType)0U,  /* FlsSector_77 */
+    (Fls_AddressType)0U,  /* FlsSector_78 */
+    (Fls_AddressType)0U,  /* FlsSector_79 */
+    (Fls_AddressType)0U,  /* FlsSector_80 */
+    (Fls_AddressType)0U,  /* FlsSector_81 */
+    (Fls_AddressType)0U,  /* FlsSector_82 */
+    (Fls_AddressType)0U,  /* FlsSector_83 */
+    (Fls_AddressType)0U,  /* FlsSector_84 */
+    (Fls_AddressType)0U,  /* FlsSector_85 */
+    (Fls_AddressType)0U,  /* FlsSector_86 */
+    (Fls_AddressType)0U,  /* FlsSector_87 */
+    (Fls_AddressType)0U,  /* FlsSector_88 */
+    (Fls_AddressType)0U,  /* FlsSector_89 */
+    (Fls_AddressType)0U,  /* FlsSector_90 */
+    (Fls_AddressType)0U,  /* FlsSector_91 */
+    (Fls_AddressType)0U,  /* FlsSector_92 */
+    (Fls_AddressType)0U,  /* FlsSector_93 */
+    (Fls_AddressType)0U,  /* FlsSector_94 */
+    (Fls_AddressType)0U,  /* FlsSector_95 */
+    (Fls_AddressType)0U,  /* FlsSector_96 */
+    (Fls_AddressType)0U,  /* FlsSector_97 */
+    (Fls_AddressType)0U,  /* FlsSector_98 */
+    (Fls_AddressType)0U,  /* FlsSector_99 */
+    (Fls_AddressType)0U,  /* FlsSector_100 */
+    (Fls_AddressType)0U,  /* FlsSector_101 */
+    (Fls_AddressType)0U,  /* FlsSector_102 */
+    (Fls_AddressType)0U,  /* FlsSector_103 */
+    (Fls_AddressType)0U,  /* FlsSector_104 */
+    (Fls_AddressType)0U,  /* FlsSector_105 */
+    (Fls_AddressType)0U,  /* FlsSector_106 */
+    (Fls_AddressType)0U,  /* FlsSector_107 */
+    (Fls_AddressType)0U,  /* FlsSector_108 */
+    (Fls_AddressType)0U,  /* FlsSector_109 */
+    (Fls_AddressType)0U,  /* FlsSector_110 */
+    (Fls_AddressType)0U,  /* FlsSector_111 */
+    (Fls_AddressType)0U,  /* FlsSector_112 */
+    (Fls_AddressType)0U,  /* FlsSector_113 */
+    (Fls_AddressType)0U,  /* FlsSector_114 */
+    (Fls_AddressType)0U,  /* FlsSector_115 */
+    (Fls_AddressType)0U,  /* FlsSector_116 */
+    (Fls_AddressType)0U,  /* FlsSector_117 */
+    (Fls_AddressType)0U,  /* FlsSector_118 */
+    (Fls_AddressType)0U,  /* FlsSector_119 */
+    (Fls_AddressType)0U,  /* FlsSector_120 */
+    (Fls_AddressType)0U,  /* FlsSector_121 */
+    (Fls_AddressType)0U,  /* FlsSector_122 */
+    (Fls_AddressType)0U,  /* FlsSector_123 */
+    (Fls_AddressType)0U,  /* FlsSector_124 */
+    (Fls_AddressType)0U,  /* FlsSector_125 */
+    (Fls_AddressType)0U,  /* FlsSector_126 */
+    (Fls_AddressType)0U   /* FlsSector_127 */
+};
+
+
+
+/**
+* @brief        Structure used to set function pointers notification, working mode
+*/
+/* Fls module initialization data (FlsConfigSet)*/
+const Fls_ConfigType Fls_Config_VS_0 =
+{
+    (Fls_AcErasePtrType)&_ERASE_FUNC_ADDRESS_,                        /* FlsAcErase */
+    (Fls_AcWritePtrType)&_WRITE_FUNC_ADDRESS_,                        /* FlsAcWrite */
+    NULL_PTR,                                                         /* FlsACCallback */
+    NULL_PTR,                                                         /* FlsJobEndNotification */
+    NULL_PTR,                                                         /* FlsJobErrorNotification */
+    NULL_PTR,                                                         /* FlsReadFunctionCallout */
+    MEMIF_MODE_SLOW,                                                  /* FlsDefaultMode */
+    1048576U,                                                         /* FlsMaxReadFastMode */
+    1024U,                                                            /* FlsMaxReadNormalMode */
+    256U,                                                             /* FlsMaxWriteFastMode */
+    8U,                                                               /* FlsMaxWriteNormalMode */
+    128U,                                                             /* FlsSectorCount */
+    &FlsConfigSet_VS_0_aFlsSectorEndAddr,                             /* (*paSectorEndAddr)[] */
+    &FlsConfigSet_VS_0_aFlsSectorSize,                                /* (*paSectorSize)[] */
+    &FlsConfigSet_VS_0_aSectorList,                                   /* (*pSectorList)[] */
+    &FlsConfigSet_VS_0_aFlsSectorFlags,                               /* (*paSectorFlags)[] */
+    &FlsConfigSet_VS_0_aFlsSectorPageSize,                            /* (*paSectorPageSize)[] */
+    &FlsConfigSet_VS_0_paHwCh,                                        /* (*paHwCh)[] */
+    &FlsConfigSet_VS_0_paSectorHwAddress,                             /* (*paSectorHwAddress)[] */
+    NULL_PTR,                                                         /* FlsQspiConfig */
+    &FlsConfigSet_VS_0_InitCfg,                                       /* FlsInternalConfig */
+    27560U                                                            /* configCrc */
+};
+
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/
+

generate/src/Ftfc_Fls_Ip_PBcfg.c

@@ -0,0 +1,108 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Ftfc_Fls_Ip_PBcfg.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Ftfc_Fls_Ip_PBcfg.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Ftfc_Fls_Ip_Types.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_VENDOR_ID_CFG_C                          43
+#define FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG_C           4
+#define FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG_C           4
+#define FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG_C        0
+#define FTFC_FLS_IP_SW_MAJOR_VERSION_CFG_C                   1
+#define FTFC_FLS_IP_SW_MINOR_VERSION_CFG_C                   0
+#define FTFC_FLS_IP_SW_PATCH_VERSION_CFG_C                   0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same vendor */
+#if (FTFC_FLS_IP_VENDOR_ID_CFG_C != FTFC_FLS_IP_TYPES_VENDOR_ID)
+    #error "Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG_C    != FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG_C    != FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG_C != FTFC_FLS_IP_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Software version */
+#if ((FTFC_FLS_IP_SW_MAJOR_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_MAJOR_VERSION) || \
+     (FTFC_FLS_IP_SW_MINOR_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_MINOR_VERSION) || \
+     (FTFC_FLS_IP_SW_PATCH_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h are different"
+#endif
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+const Ftfc_ConfigType FlsConfigSet_VS_0_InitCfg =
+{
+    NULL_PTR,  /* FlsStartFlashAccessNotif */
+    NULL_PTR  /* FlsFinishedFlashAccessNotif */
+};
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/

generate/src/Ftfc_Fls_Ip_VS_0_PBcfg.c

@@ -0,0 +1,108 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Ftfc_Fls_Ip_PBcfg.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Ftfc_Fls_Ip_PBcfg.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Ftfc_Fls_Ip_Types.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FTFC_FLS_IP_VENDOR_ID_CFG_C                          43
+#define FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG_C           4
+#define FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG_C           4
+#define FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG_C        0
+#define FTFC_FLS_IP_SW_MAJOR_VERSION_CFG_C                   1
+#define FTFC_FLS_IP_SW_MINOR_VERSION_CFG_C                   0
+#define FTFC_FLS_IP_SW_PATCH_VERSION_CFG_C                   0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same vendor */
+#if (FTFC_FLS_IP_VENDOR_ID_CFG_C != FTFC_FLS_IP_TYPES_VENDOR_ID)
+    #error "Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Autosar version */
+#if ((FTFC_FLS_IP_AR_RELEASE_MAJOR_VERSION_CFG_C    != FTFC_FLS_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FTFC_FLS_IP_AR_RELEASE_MINOR_VERSION_CFG_C    != FTFC_FLS_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FTFC_FLS_IP_AR_RELEASE_REVISION_VERSION_CFG_C != FTFC_FLS_IP_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h are different"
+#endif
+/* Check if current file and Ftfc_Fls_Ip_Types header file are of the same Software version */
+#if ((FTFC_FLS_IP_SW_MAJOR_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_MAJOR_VERSION) || \
+     (FTFC_FLS_IP_SW_MINOR_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_MINOR_VERSION) || \
+     (FTFC_FLS_IP_SW_PATCH_VERSION_CFG_C != FTFC_FLS_IP_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Ftfc_Fls_Ip_PBCfg.c and Ftfc_Fls_Ip_Types.h are different"
+#endif
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+//const Ftfc_ConfigType FlsConfigSet_VS_0_InitCfg =
+//{
+//    NULL_PTR,  /* FlsStartFlashAccessNotif */
+//    NULL_PTR  /* FlsFinishedFlashAccessNotif */
+//};
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/

generate/src/Lpuart_Uart_Ip_VS_0_PBcfg.c

@@ -47,6 +47,8 @@ extern "C"{
 #if (LPUART_UART_IP_HAS_DMA_ENABLED == STD_ON)
 #include "Dma_Ip.h"
 #endif
+
+#include "USER_CONFIG.h"
 /*==================================================================================================
 *                              SOURCE FILE VERSION INFORMATION
 ==================================================================================================*/
@@ -154,13 +156,35 @@ extern Lpuart_Uart_Ip_StateStructureType Lpuart_Uart_Ip_apStateStructure[3U];
 */
 const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_0_VS_0 =
 {
-
+#if (defined UART0_BAUDRATE)
+#if (UART0_BAUDRATE == UART_BAUDRATE_9600)
     /*!< Baud rate in hertz */
     9615U,
     /* Baud clock divisor*/
     8U,
     /* Over sampling ratio*/
     26U,
+#elif (UART0_BAUDRATE == UART_BAUDRATE_19200)
+	/*!< Baud rate in hertz */
+    19230U,
+    /* Baud clock divisor*/
+    4U,
+    /* Over sampling ratio*/
+    26U,
+#elif (UART0_BAUDRATE == UART_BAUDRATE_115200)
+	/*!< Baud rate in hertz */
+    117647U,
+    /* Baud clock divisor*/
+    1U,
+    /* Over sampling ratio*/
+    17U,
+#else
+#error "please select the right uart baudrate of uart0
+#endif
+#else
+#error "please define the UART0_BAUDRATE"
+#endif
+
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */
@@ -191,13 +215,34 @@ const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_0_VS_0 =
 */
 const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_1_VS_0 =
 {
-
+#if (defined UART1_BAUDRATE)
+#if (UART1_BAUDRATE == UART_BAUDRATE_9600)
     /*!< Baud rate in hertz */
+    9615U,
+    /* Baud clock divisor*/
+    8U,
+    /* Over sampling ratio*/
+    26U,
+#elif (UART1_BAUDRATE == UART_BAUDRATE_19200)
+	/*!< Baud rate in hertz */
+    19230U,
+    /* Baud clock divisor*/
+    4U,
+    /* Over sampling ratio*/
+    26U,
+#elif (UART1_BAUDRATE == UART_BAUDRATE_115200)
+	/*!< Baud rate in hertz */
     117647U,
     /* Baud clock divisor*/
     1U,
     /* Over sampling ratio*/
     17U,
+#else
+#error "please select the right uart baudrate of uart0
+#endif
+#else
+#error "please define the UART0_BAUDRATE"
+#endif
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */
@@ -228,13 +273,34 @@ const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_1_VS_0 =
 */
 const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_2_VS_0 =
 {
-
+#if (defined UART2_BAUDRATE)
+#if (UART2_BAUDRATE == UART_BAUDRATE_9600)
     /*!< Baud rate in hertz */
     9615U,
     /* Baud clock divisor*/
     8U,
     /* Over sampling ratio*/
     26U,
+#elif (UART2_BAUDRATE == UART_BAUDRATE_19200)
+	/*!< Baud rate in hertz */
+    19230U,
+    /* Baud clock divisor*/
+    4U,
+    /* Over sampling ratio*/
+    26U,
+#elif (UART2_BAUDRATE == UART_BAUDRATE_115200)
+	/*!< Baud rate in hertz */
+    117647U,
+    /* Baud clock divisor*/
+    1U,
+    /* Over sampling ratio*/
+    17U,
+#else
+#error "please select the right uart baudrate of uart0
+#endif
+#else
+#error "please define the UART0_BAUDRATE"
+#endif
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */

generate/src/Qspi_Ip_VS_0_PBcfg.c

@@ -0,0 +1,150 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : FTFC_FLS_IP IPV_QSPI
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file Qspi_Ip_PBcfg.c
+*
+*   @addtogroup FLS
+*   @{
+*/
+
+/* implements Qspi_Ip_PBcfg.c_Artifact */
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Qspi_Ip_Types.h"
+#include "Qspi_Ip_Features.h"
+#include "Qspi_Ip_Cfg.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLS_QSPI_IP_VENDOR_ID_CFG_C                      43
+#define FLS_QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_C       4
+#define FLS_QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_C       4
+#define FLS_QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_C    0
+#define FLS_QSPI_IP_SW_MAJOR_VERSION_CFG_C               1
+#define FLS_QSPI_IP_SW_MINOR_VERSION_CFG_C               0
+#define FLS_QSPI_IP_SW_PATCH_VERSION_CFG_C               0
+
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and Qspi_Ip_Types header file are of the same vendor */
+#if (FLS_QSPI_IP_VENDOR_ID_CFG_C != FLS_QSPI_TYPES_VENDOR_ID)
+    #error "Qspi_Ip_PBcfg.c and Qspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Autosar version */
+#if ((FLS_QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_C    != FLS_QSPI_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FLS_QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_C    != FLS_QSPI_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FLS_QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_C != FLS_QSPI_TYPES_AR_RELEASE_REVISION_VERSION) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Types.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Types header file are of the same Software version */
+#if ((FLS_QSPI_IP_SW_MAJOR_VERSION_CFG_C != FLS_QSPI_TYPES_SW_MAJOR_VERSION) || \
+     (FLS_QSPI_IP_SW_MINOR_VERSION_CFG_C != FLS_QSPI_TYPES_SW_MINOR_VERSION) || \
+     (FLS_QSPI_IP_SW_PATCH_VERSION_CFG_C != FLS_QSPI_TYPES_SW_PATCH_VERSION) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Types.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Features header file are of the same vendor */
+#if (FLS_QSPI_IP_VENDOR_ID_CFG_C != QSPI_IP_FEATURES_VENDOR_ID_CFG)
+    #error "Qspi_Ip_PBcfg.c and Qspi_Ip_Features.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Autosar version */
+#if ((FLS_QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_C    != QSPI_IP_FEATURES_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_C    != QSPI_IP_FEATURES_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_C != QSPI_IP_FEATURES_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Features.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Features header file are of the same Software version */
+#if ((FLS_QSPI_IP_SW_MAJOR_VERSION_CFG_C != QSPI_IP_FEATURES_SW_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_SW_MINOR_VERSION_CFG_C != QSPI_IP_FEATURES_SW_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_SW_PATCH_VERSION_CFG_C != QSPI_IP_FEATURES_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Features.h are different"
+#endif
+
+/* Check if current file and Qspi_Ip_Cfg.h header file are of the same vendor */
+#if (FLS_QSPI_IP_VENDOR_ID_CFG_C !=  QSPI_IP_VENDOR_ID_CFG)
+    #error "Qspi_Ip_PBcfg.c and Qspi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if current file and Qspi_Ip_Cfg.h header file are of the same Autosar version */
+#if ((FLS_QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG_C    !=  QSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG_C    !=  QSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG_C !=  QSPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Cfg.h are different"
+#endif
+/* Check if current file and Qspi_Ip_Cfg.h header file are of the same Software version */
+#if ((FLS_QSPI_IP_SW_MAJOR_VERSION_CFG_C !=  QSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_SW_MINOR_VERSION_CFG_C !=  QSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLS_QSPI_IP_SW_PATCH_VERSION_CFG_C !=  QSPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Qspi_Ip_PBcfg.c and Qspi_Ip_Cfg.h are different"
+#endif
+
+
+/*==================================================================================================
+                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                           CONSTANTS
+==================================================================================================*/
+
+
+
+#define FLS_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+/* External QSPI flash parameters. */
+
+
+
+
+
+#define FLS_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Fls_MemMap.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @}*/

src/AppFuncLib.c

@@ -15,6 +15,9 @@
  */
 
 #include "AppFuncLib.h"
+#include "AppGlobalVar.h"
+#include "Hal_Fls.h"
+#include "AppTaskUart1.h"
 /**
  * @brief : 获取故障码函数，从故障数组中获取故障码，并将之前的故障码向前移动
  * @param {UINT16} *ErrorArray

src/AppGlobalVar.c

@@ -17,9 +17,11 @@
 #include "AppGlobalVar.h"
 //测试
 
-//*全局变量*//
-uint8 VIN[17] = {0};
+//*????*//
+uint8 TcpbattSN[17] = {0x31}; //???SN??
+
 volatile uint32 TimerCounter = 0; // ms单位
+uint8 Fota_update_flag = 0;
 /*GPS*/
 QueueHandle_t GpsDataQueueHandle;
 sint16 xyzData[3] = {0};
@@ -31,15 +33,17 @@ boolean CanIf_bRxFlag = false;
 QueueHandle_t CanRecvQueueHandle;
 
 /*TCP相关变量*/
-uint8 TcpbattSN[17] = {0x00}; //上传的SN编号
 char ImeiNum[15] = {0};
 char IccidNum[20] = {0};
 uint8 CSQValue = 0;
 sint8 SocketId = -1;//联网状态
 sint8 RegChkRet = 0;//驻网状态
 char WebSiteIp[20] = {0};
+uint8 TcpWorkState = 0;
 const char WebSiteName[] = "\"iotp.fast-fun.cn\"";
 const uint16 WebSitePort = 8712;
+//const char WebSiteName[] = "\"nas.fast-fun.cn\"";
+//const uint16 WebSitePort = 8812;
 
 #define EEP_START_SEC_VAR_INIT_8_NO_CACHEABLE
 #include "Eep_MemMap.h"
@@ -80,9 +84,12 @@ uint8 battFanState = 0;
 uint8 battRelayState = 0;
 uint8 battConverState = 0;
 uint8 battSeparateEnable = 0;
-uint8 battSeparateEnableState = 0;
+uint8 battSeparateCtlState = 0;
+uint8 battSeparateState = 0;
 uint16 ErrorArray[5] = {0};
-
+uint32 meterAllPwr[2] = {0};
+uint32 meterPosPwr[2] = {0};
+uint32 meterNegPwr[2] = {0};
 //test
 uint32 BattTempR[4] = {0xFF};
 #endif

src/AppGlobalVar.h

@@ -22,7 +22,7 @@
 #include "hal_adapter.h"
 
 #define defaultSn "SPFPFL264S226D001"
-
+#define BATT_SN_LEN 17
 #define HWVERSION 0x0001
 #define BLSWVERSION 0x00000001
 #define DRVSWVERSION 0x00000001
@@ -35,6 +35,7 @@
 extern uint8 TcpbattSN[17];
 extern uint8 VIN[17];
 extern volatile uint32 TimerCounter;
+extern uint8 Fota_update_flag;
 typedef struct
 {
     uint8 RealLen;
@@ -59,7 +60,7 @@ extern const char WebSiteName[];
 extern const uint16 WebSitePort;
 extern char ImeiNum[15];
 extern char IccidNum[20];
-
+extern uint8 TcpWorkState;
 typedef struct _AppConfigType
 {
 	bool appSaveFlg;
@@ -109,9 +110,11 @@ extern uint8 battFanState ;
 extern uint8 battRelayState ;
 extern uint8 battConverState ;
 extern uint8 battSeparateEnable ;
-extern uint8 battSeparateEnableState ;
+extern uint8 battSeparateCtlState ;
+extern uint8 battSeparateState ;
 extern uint16 ErrorArray[5];
-
-
+extern uint32 meterAllPwr[2];
+extern uint32 meterPosPwr[2];
+extern uint32 meterNegPwr[2];
 extern uint32 BattTempR[4];
 #endif /* APPGLOBALVAR_H_ */

src/AppTaskCan.c

@@ -32,7 +32,6 @@ void CanTask(void *pvParameters)
 	GsensorInit();
 	while(1)
 	{
-
 		do
 		{
 			memset(&CanRxMsg, 0, sizeof(CanRxMsg));

src/AppTaskGps.c

@@ -14,14 +14,19 @@ void GpsTask(void *pvParameters)
 	GpsDataQueueHandle = xQueueCreate(1, sizeof(GPSInfo));//长度为1才可以允许覆写
 	Dio_WriteChannel(DioConf_DioChannel_PTD1_GPIO_OUT_MCU_GPS_POW_EN, STD_ON);//GPS开机
 	uint16 pReadLen = 0;
+	uint8 *UartRecvPtr=NULL;
 	while(1)
 	{
 		vTaskDelay(pdMS_TO_TICKS(10));
-		memset(RX_Buffer[UART_LPUART2],0x00,sizeof(RX_Buffer[UART_LPUART2]));
-		UART_Receive_Data(UART_LPUART2,RX_Buffer[UART_LPUART2],&pReadLen,1000);
+		UART_Receive_Data(UART_LPUART2,&UartRecvPtr,&pReadLen,1000);
 		if(pReadLen>0)
 		{
-			GpsDataDecode(RX_Buffer[UART_LPUART2]);
+			GpsDataDecode(UartRecvPtr);
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
 		}
 	}
 }

src/AppTaskMain.c

@@ -37,6 +37,13 @@ void MainTask(void *pvParameters)
 			AppConfigInfo.appSaveFlg = false;
 			HAL_EEP_Write(0,(uint8 *)&AppConfigInfo,sizeof(AppConfigInfo));
 		}
+		if(Fota_update_flag)//升级指令发出，进行重启
+		{
+			//重启前保存数据
+			AppConfigInfo.appSaveFlg = false;
+			HAL_EEP_Write(0,(uint8 *)&AppConfigInfo,sizeof(AppConfigInfo));
+			SystemSoftwareReset();
+		}
 	}
 }
 static void vTimerCallback(TimerHandle_t pxTimer)

src/AppTaskUart0.c

@@ -41,6 +41,7 @@ void Uart0Task(void *pvParameters)
 		case PROCESS_UART_STATE_READ:
 		{
 			/*电压电流数据读取（第一次读取）*/
+			uint8 *UartDataRecv = NULL;
 			pReadLen = 0;
 			Dio_FlipChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2);
 			RegAddrBegin = 0x00;
@@ -55,19 +56,18 @@ void Uart0Task(void *pvParameters)
 			Uart0AskMsg.CRC_L = CRC_chk_buffer;
 			Uart0AskMsg.CRC_H = CRC_chk_buffer >> 8;
 			/*RS485查询命令需要使能*/
-			Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_ON);
 			UART_Send_Data(UART_LPUART0, (uint8 *)&Uart0AskMsg, sizeof(Uart0AskMsg), 1000);
-			Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_OFF);
-			memset(RX_Buffer[UART_LPUART0], 0x00, sizeof(RX_Buffer[UART_LPUART0]));
 			uint16 ReadLen1 = 0;
 			uint16 ReadLenTar = 0;
 			uint8 ReadDelayCounter = 0;
 			ReadLenTar = (Reg_Num)*2+5;
+			memset((uint8 *)&UartAnsData,0x00,sizeof(UartAnsData));
 			while(1)
 			{
-				UART_Receive_Data(UART_LPUART0, &RX_Buffer[UART_LPUART0][ReadLen1], &pReadLen, 1000);
-				if(pReadLen>0)
+				UART_Receive_Data(UART_LPUART0, &UartDataRecv, &pReadLen, 100);
+				if(pReadLen>2)
 				{
+					memcpy((uint8 *)&UartAnsData+ReadLen1,UartDataRecv,pReadLen);
 					ReadLen1 = ReadLen1 + pReadLen;
 				}
 				else
@@ -88,18 +88,21 @@ void Uart0Task(void *pvParameters)
 					ReadLen1 = 0;
 					break;
 				}
+				if(UartDataRecv!=NULL)
+				{
+					free(UartDataRecv);
+				}
+				UartDataRecv=NULL;
 			}
 			if (pReadLen > 0)
 			{
 				uint16 CrcChkGet = 0xffff;
 				uint16 CrcChkCal = 0x0000;
-				memcpy((uint8 *)(&UartAnsData),RX_Buffer[UART_LPUART0],0x03);
-				UartAnsData.DataPtr = (uint8 *)(&RX_Buffer[UART_LPUART0][3]);
-				CrcChkCal = crc_chk(RX_Buffer[UART_LPUART0], pReadLen-2);
-				CrcChkGet = (uint16)((RX_Buffer[UART_LPUART0][pReadLen-1]<<8)|(RX_Buffer[UART_LPUART0][pReadLen-2]));
+				CrcChkCal = crc_chk((uint8 *)&UartAnsData, pReadLen-2);
+				CrcChkGet = ((uint16)(UartAnsData.Data[pReadLen-1-3])<<8) | ((uint16)(UartAnsData.Data[pReadLen-2-3]));
 				if(CrcChkCal==CrcChkGet)
 				{
-					bmsCellInfoDecode(UartAnsData.DataPtr);
+					bmsCellInfoDecode(UartAnsData.Data);
 					UartNoDataReadCounter = 0;
 				}
 			}
@@ -118,16 +121,15 @@ void Uart0Task(void *pvParameters)
 			Uart0AskMsg.CRC_L = CRC_chk_buffer;
 			Uart0AskMsg.CRC_H = CRC_chk_buffer >> 8;
 			/*RS485查询命令需要使能*/
-			Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_ON);
 			UART_Send_Data(UART_LPUART0, (uint8 *)&Uart0AskMsg, sizeof(Uart0AskMsg), 1000);
-			Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_OFF);
-			memset(RX_Buffer[UART_LPUART0], 0x00, sizeof(RX_Buffer[UART_LPUART0]));
+			memset((uint8 *)&UartAnsData,0x00,sizeof(UartAnsData));
 			ReadLenTar = (Reg_Num)*2+5;
 			while(1)
 			{
-				UART_Receive_Data(UART_LPUART0, &RX_Buffer[UART_LPUART0][ReadLen1], &pReadLen, 1000);
-				if(pReadLen>0)
+				UART_Receive_Data(UART_LPUART0, &UartDataRecv, &pReadLen, 100);
+				if(pReadLen>2)
 				{
+					memcpy((uint8 *)&UartAnsData+ReadLen1,UartDataRecv,pReadLen);
 					ReadLen1 = ReadLen1 + pReadLen;
 				}
 				else
@@ -148,37 +150,108 @@ void Uart0Task(void *pvParameters)
 					ReadLen1 = 0;
 					break;
 				}
+				if(UartDataRecv!=NULL)
+				{
+					free(UartDataRecv);
+				}
+				UartDataRecv=NULL;
 			}
-			Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_ON);
-
-			/*TTL直连可以直接查询*/
-			//memset(RX_Buffer[UART_LPUART0],0x00,sizeof(RX_Buffer[UART_LPUART0]));
-			//UART_Query_Data(UART_LPUART0,UART_LPUART0,(uint8 *)&Uart0AskMsg,sizeof(Uart0AskMsg),RX_Buffer[UART_LPUART0], &pReadLen,500);
 			if (pReadLen > 0)
 			{
 				uint16 CrcChkGet = 0xffff;
 				uint16 CrcChkCal = 0x0000;
-				memcpy((uint8 *)(&UartAnsData),RX_Buffer[UART_LPUART0],0x03);
-				UartAnsData.DataPtr = (uint8 *)(&RX_Buffer[UART_LPUART0][3]);
-				CrcChkCal = crc_chk(RX_Buffer[UART_LPUART0], pReadLen-2);
-				CrcChkGet = (uint16)((RX_Buffer[UART_LPUART0][pReadLen-1]<<8)|(RX_Buffer[UART_LPUART0][pReadLen-2]));
+				CrcChkCal = crc_chk((uint8 *)&UartAnsData, pReadLen-2);
+				CrcChkGet =  ((uint16)(UartAnsData.Data[pReadLen-1-3])<<8) | ((uint16)(UartAnsData.Data[pReadLen-2-3]));
 				if(CrcChkCal==CrcChkGet)
 				{
-					bmsOtherInfoDecode(UartAnsData.DataPtr);
+					bmsOtherInfoDecode(UartAnsData.Data);
 					UartNoDataReadCounter = 0;
 				}
 			}
 			UartNoDataReadCounter++;
 			//没有读到数据时的默认值
-			if(UartNoDataReadCounter>20)
+			if(UartNoDataReadCounter>10)
 			{
-				memset(RX_Buffer[UART_LPUART0],0x00,sizeof(RX_Buffer[UART_LPUART0]));
-				memcpy((uint8 *)(&UartAnsData),RX_Buffer[UART_LPUART0],0x03);
-				UartAnsData.DataPtr = (uint8 *)(&RX_Buffer[UART_LPUART0][3]);
-				bmsCellInfoDecode(UartAnsData.DataPtr);
-				bmsOtherInfoDecode(UartAnsData.DataPtr);
+				memset((uint8 *)&UartAnsData,0x00,sizeof(UartAnsData));
+				bmsCellInfoDecode(UartAnsData.Data);
+				bmsOtherInfoDecode(UartAnsData.Data);
 				PutErrorNum(ErrorArray, sizeof(ErrorArray)/2, 1);
 			}
+
+			/**电表数据读取*/
+			for(uint8 i=0;i<2;i++)
+			{
+				/*电表参数读取*/
+				static uint16 pt[2] = {0};
+				static uint16 ct[2] = {0};
+				pReadLen = 0;
+				uint8 *UartRecvPtr=NULL;
+				RegAddrBegin = 0x0FA1;
+				Reg_Num = 0x02;
+				Uart0AskMsg.Bms_Address = METER1_ADDRESS_CODE+i;//第一次读02，第二次读03
+				Uart0AskMsg.Bms_Funcode = UART_READ_CODE;
+				Uart0AskMsg.Reg_Begin_H = RegAddrBegin>>8;
+				Uart0AskMsg.Reg_Begin_L = RegAddrBegin;
+				Uart0AskMsg.Reg_Num_H = Reg_Num >> 8;
+				Uart0AskMsg.Reg_Num_L = Reg_Num;
+				CRC_chk_buffer = crc_chk((uint8 *)&Uart0AskMsg, 6);
+				Uart0AskMsg.CRC_L = CRC_chk_buffer;
+				Uart0AskMsg.CRC_H = CRC_chk_buffer >> 8;
+				UART_Send_Data(UART_LPUART0, (uint8 *)&Uart0AskMsg, sizeof(Uart0AskMsg), 100);
+				UART_Receive_Data(UART_LPUART0, &UartRecvPtr, &pReadLen, 1000);
+				//电表数据解析
+				if (pReadLen > 0)
+				{
+					uint16 CrcChkGet = 0xffff;
+					uint16 CrcChkCal = 0x0000;
+					CrcChkCal = crc_chk(UartRecvPtr, pReadLen-2);
+					CrcChkGet =  ((uint16)(*(UartRecvPtr+pReadLen-1))<<8) | ((uint16)(*(UartRecvPtr+pReadLen-2)));
+					if(CrcChkCal==CrcChkGet)
+					{
+						pt[i] = ((uint16)(*(UartRecvPtr+3))<<8) | ((uint16)(*(UartRecvPtr+4)));
+						ct[i] = ((uint16)(*(UartRecvPtr+5))<<8) | ((uint16)(*(UartRecvPtr+6)));
+					}
+				}
+				if(UartRecvPtr!=NULL)
+				{
+					free(UartRecvPtr);
+				}
+				UartRecvPtr=NULL;
+				/*电表电量数据读取*/
+				pReadLen = 0;
+				RegAddrBegin = 0x1B58;
+				Reg_Num = 0x08;
+				Uart0AskMsg.Bms_Address = METER1_ADDRESS_CODE+i;//第一次读02，第二次读03
+				Uart0AskMsg.Bms_Funcode = UART_READ_CODE;
+				Uart0AskMsg.Reg_Begin_H = RegAddrBegin>>8;
+				Uart0AskMsg.Reg_Begin_L = RegAddrBegin;
+				Uart0AskMsg.Reg_Num_H = Reg_Num >> 8;
+				Uart0AskMsg.Reg_Num_L = Reg_Num;
+				CRC_chk_buffer = crc_chk((uint8 *)&Uart0AskMsg, 6);
+				Uart0AskMsg.CRC_L = CRC_chk_buffer;
+				Uart0AskMsg.CRC_H = CRC_chk_buffer >> 8;
+				UART_Send_Data(UART_LPUART0, (uint8 *)&Uart0AskMsg, sizeof(Uart0AskMsg), 100);
+				UART_Receive_Data(UART_LPUART0, &UartRecvPtr, &pReadLen, 1000);
+				//电表数据解析
+				if (pReadLen > 0)
+				{
+					uint16 CrcChkGet = 0xffff;
+					uint16 CrcChkCal = 0x0000;
+					CrcChkCal = crc_chk(UartRecvPtr, pReadLen-2);
+					CrcChkGet =  ((uint16)(*(UartRecvPtr+pReadLen-1))<<8) | ((uint16)(*(UartRecvPtr+pReadLen-2)));
+					if(CrcChkCal==CrcChkGet)
+					{
+						meterAllPwr[i] = pt[i]*ct[i]*(((uint32)(*(UartRecvPtr+3))<<24)|((uint32)(*(UartRecvPtr+4))<<16)|((uint32)(*(UartRecvPtr+5))<<8) | ((uint32)(*(UartRecvPtr+6))));
+						meterPosPwr[i] = pt[i]*ct[i]*((uint32)(*(UartRecvPtr+11))<<24)|((uint32)(*(UartRecvPtr+12))<<16)|((uint32)(*(UartRecvPtr+13))<<8) | ((uint32)(*(UartRecvPtr+14)));
+						meterNegPwr[i] = pt[i]*ct[i]*((uint32)(*(UartRecvPtr+15))<<24)|((uint32)(*(UartRecvPtr+16))<<16)|((uint32)(*(UartRecvPtr+17))<<8) | ((uint32)(*(UartRecvPtr+18)));
+					}
+				}
+				if(UartRecvPtr!=NULL)
+				{
+					free(UartRecvPtr);
+				}
+				UartRecvPtr=NULL;
+			}
 			PROC_UART0_STATE_SWITCH(PROCESS_UART_STATE_IDLE);
 			break;
 		}
@@ -189,13 +262,13 @@ void Uart0Task(void *pvParameters)
 				uint16 RegAddress = 0;
 				uint16 CRC_chk_buffer = 0;
 				uint8 WriteData[2] = {0x00,0x00};
-				if(battSeparateEnableState)
+				if(!battSeparateCtlState)
 				{
-					setbit(WriteData[1],7);
+					setbit(WriteData[0],7);
 				}
 				else
 				{
-					clrbit(WriteData[1],7);
+					clrbit(WriteData[0],7);
 				}
 				RegAddress = 0x1B + AppDataInfo.BattCellCount + AppDataInfo.BattTempCount;
 				UartWriteMsgType Uart_Write_Msg;
@@ -210,13 +283,19 @@ void Uart0Task(void *pvParameters)
 				CRC_chk_buffer = crc_chk((uint8 *)&Uart_Write_Msg, sizeof(Uart_Write_Msg) - 2);
 				Uart_Write_Msg.CRC_L = CRC_chk_buffer;
 				Uart_Write_Msg.CRC_H = CRC_chk_buffer >> 8;
-				UART_Query_Data(UART_LPUART0,UART_LPUART0,(uint8 *)&Uart_Write_Msg,sizeof(Uart_Write_Msg),RX_Buffer[UART_LPUART0], &pReadLen,500);
-				if (pReadLen>0&&RX_Buffer[UART_LPUART0][1] == 0x10)
+				uint8 *UartRecvPtr = NULL;
+				UART_Query_Data(UART_LPUART0,UART_LPUART0,(uint8 *)&Uart_Write_Msg,sizeof(Uart_Write_Msg),&UartRecvPtr, &pReadLen,500);
+				if (pReadLen>0&&*(UartRecvPtr+1) == 0x10)
 				{
 					writecounter = 0;
 					battSeparateEnable = 0;
 				}
 				writecounter++;
+				if(UartRecvPtr != NULL)
+				{
+					free(UartRecvPtr);
+				}
+				UartRecvPtr = NULL;
 			}
 			if(writecounter>=5)
 			{
@@ -293,6 +372,7 @@ bool bmsCellInfoDecode(uint8 *dataPtr) //
 		Battsumvoltage = Battsumvoltage + battCellU[i];
 	}
 	avrgCellVol = Battsumvoltage / BATT_CELL_VOL_NUM;
+	battPackVol = Battsumvoltage/100;
 	return true;
 }
 bool bmsOtherInfoDecode(uint8 *dataPtr)//其他数据解析
@@ -306,18 +386,10 @@ bool bmsOtherInfoDecode(uint8 *dataPtr)//
 
 	temp = ((dataPtr[(0x09 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1]) >> 1) & 0x03;
 	battMOSSwitchState = ((temp & 0x01) << 1) | ((temp & 0x02) >> 1);
-	if (battSeparateEnableState==1)
-	{
-		battMOSSwitchState = battMOSSwitchState | (0x01 << 2);
-	}
-	else
-	{
-		battMOSSwitchState = battMOSSwitchState | (0x00 << 2);
-	}
 	battSOC = dataPtr[(0x0B + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1];
 	battSOH = dataPtr[(0x0C + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1];
 	Battdesigncap = (dataPtr[(0x0E + OtherInfoAddrOffset + TEMP_NUM) * 2]) << 24 | (dataPtr[(0x0E + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1]) << 16 | (dataPtr[(0x0F + OtherInfoAddrOffset + TEMP_NUM) * 2]) << 8 | (dataPtr[(0x0F + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1]);
-	battPackVol = ((dataPtr[(0x18 + OtherInfoAddrOffset + TEMP_NUM) * 2]) << 8 | (dataPtr[(0x18 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1])) / 10; // uint 100mV
+//	battPackVol = ((dataPtr[(0x18 + OtherInfoAddrOffset + TEMP_NUM) * 2]) << 8 | (dataPtr[(0x18 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1])) / 10; // uint 100mV
 	maxCellVol = (dataPtr[(0x19 + OtherInfoAddrOffset + TEMP_NUM) * 2] << 8) | dataPtr[(0x19 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1];
 	minCellVol = (dataPtr[(0x1A + OtherInfoAddrOffset + TEMP_NUM) * 2] << 8) | dataPtr[(0x1A + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1];
 	for (uint8 i = 0; i < AppDataInfo.BattTempCount; i++)
@@ -330,7 +402,15 @@ bool bmsOtherInfoDecode(uint8 *dataPtr)//
 	battFanState = getbit(dataPtr[(0x09 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1],3);
 	battRelayState = getbit(dataPtr[(0x09 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1],4);
 	battConverState = getbit(dataPtr[(0x09 + OtherInfoAddrOffset + TEMP_NUM) * 2 + 1],6);
-	battSeparateEnableState = getbit(dataPtr[(0x1B + OtherInfoAddrOffset + TEMP_NUM) * 2],7);
+	battSeparateState = getbit(dataPtr[(0x1B + OtherInfoAddrOffset + TEMP_NUM) * 2],7);
+	if (battSeparateState==0)
+	{
+		battMOSSwitchState = battMOSSwitchState | (0x01 << 2);
+	}
+	else
+	{
+		battMOSSwitchState = battMOSSwitchState | (0x00 << 2);
+	}
 	//故障状态映关系(先完成告警状态简单上传)
 	uint8 ErrorArrayTemp[32] ={0};
 	uint8 ErrorArrayNumTemp[32]={81,87,83,89,97,99,132,131,134,84,90,82,88,135,136,98,100};

src/AppTaskUart0.h

@@ -12,6 +12,7 @@
 #include "AppGlobalVar.h"
 #ifdef APP_UART0_ENABLE
 #define BMS_ADDRESS_CODE 0x01
+#define METER1_ADDRESS_CODE 0x05
 #define UART_READ_CODE 0x03
 #define UART_WRITE_CODE 0x10
 #define UART_ENCRYPT_CODE 0x05
@@ -23,7 +24,7 @@ typedef struct _UartAnsType
 	uint8 BmsAdd;
 	uint8 FunCode;
 	uint8 Datalen;
-    uint8 *DataPtr;
+    uint8 Data[300];
 }UartAnsType;
 typedef enum
 {

src/AppTaskUart1.c

@@ -14,8 +14,11 @@
  *      Author: QiXiang_CHENJIE
  */
 #include "AppTaskUart1.h"
+#include "hal_fls.h"
+
 const ATCmdFunc Atcmdfunc[] = {
 	{AT_CMD_TEST, "AT\r\n", at_callbackFunc},
+	{AT_ATE0, "ATE0\r\n", at_callbackFunc},
 	{AT_SIMREADY, "AT+CPIN?\r\n", at_callbackFunc},
 	{AT_GETICCID, "AT+CICCID\r\n", at_callbackFunc},
 	{AT_CGREG, "AT+CGREG?\r\n", at_callbackFunc},
@@ -38,10 +41,10 @@ sint8 TcpDataSendFunc(sint8 ConnectId);
 sint8 TcpRegisterChkFunc(void);
 void TcpDataEncode(uint32 *PtrSendAddr, uint16 *SendLen);
 void GetUtc8Time(UTC8TimeType *UTC8TimeTcp);
-static void AtcmdTransmit(sint8 CmdIdx, uint8 *SetValuePtr, uint16 SetValueLen, sint8 *retFunc);
-static sint8 tcpipConnectionSend(uint8 TcpConnectId,uint8 * SendDataPtr,uint16 SendDataLen);
-static void TcpDataInfoRecvHandle(uint8 *DataRecv,uint16 DataRecvLen);
+static void AtcmdTransmit(sint8 CmdIdx, uint8 *SetValuePtr, uint16 SetValueLen, sint8 *retFunc,uint16 timeout);
+static void TcpDataInfoRecvHandle(uint8 *DataRecv, uint16 DataRecvLen);
 static void GetCSQValue(uint8 *out);
+void Fota_Ftp(void);
 void Uart_4G_Task(void *pvParameters)
 {
 	(void)pvParameters;
@@ -53,36 +56,42 @@ void Uart_4G_Task(void *pvParameters)
 	// LED测试
 	Dio_WriteChannel(DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1, STD_OFF);
 	vTaskDelay(pdMS_TO_TICKS(1000));
-	uint8 pReadLen = 0;
+	uint16 pReadLen = 0;
 	InitFunc(); // 4G模块初始化,注：AT同步不通过，没有进行次数判定及跳转
 	uint32 SendTimerCounter = 0;
+	uint32 RecvTimerDelay = 0;
+	uint8 *UartRecvPtr=NULL;
 	for (;;)
 	{
 		switch (gProcess_Tcp_Task)
 		{
 		case PROCESS_TCP_IDLE: //空闲状态
 		{
-			vTaskDelay(pdMS_TO_TICKS(10));
+			UART_Receive_Data(UART_LPUART1, &UartRecvPtr, &pReadLen, 10);//100ms检测
 			if (SocketId < 0)
 			{
 				PROC_TCP_STATE_SWITCH(PROCESS_TCP_REGCHK);
 			}
-			else if ((TimerCounter -SendTimerCounter)>1000 && AppConfigInfo.eolFlg==1)
+			else if (pReadLen>0)
+			{
+				PROC_TCP_STATE_SWITCH(PROCESS_TCP_RECV);
+				RecvTimerDelay = TimerCounter;
+			}
+			else if (AppConfigInfo.eolFlg == 1 && (TimerCounter - SendTimerCounter) >= 1000 && TcpWorkState==0)
 			{
 				SendTimerCounter = TimerCounter;
 				PROC_TCP_STATE_SWITCH(PROCESS_TCP_SEND);
-				//Dio_FlipChannel(DioConf_DioChannel_PTE7_GPIO_OUT_MCU_LED3);
 			}
-			else if (TimerCounter % 100 == 0)
+			if((TimerCounter-RecvTimerDelay)>=10000 && TcpWorkState==1)//10s内没有命令下发，进行正常发送任务
 			{
-				PROC_TCP_STATE_SWITCH(PROCESS_TCP_RECV);
+				TcpWorkState = 0;
 			}
 			break;
 		}
 		case PROCESS_TCP_ATSYS:
 		{
 			sint8 ATRet = -1;
-			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet,100);
 			if (ATRet == 0)
 			{
 				PROC_TCP_STATE_SWITCH(PROCESS_TCP_IDLE);
@@ -140,11 +149,17 @@ void Uart_4G_Task(void *pvParameters)
 		}
 		case PROCESS_TCP_RECV: //网络数据接收,100ms空闲状态下即可接收
 		{
-			memset(RX_Buffer[UART_LPUART1],0x00,sizeof(RX_Buffer[UART_LPUART1]));
-			UART_Receive_Data(UART_LPUART1,RX_Buffer[UART_LPUART1],&pReadLen,100);
-			if(pReadLen>0&&SocketId>=0)
+			Dio_FlipChannel(DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1);
+
+			if (pReadLen > 0 && SocketId >= 0)
 			{
-				TcpDataInfoRecvHandle(RX_Buffer[UART_LPUART1],pReadLen);
+				TcpDataInfoRecvHandle(UartRecvPtr, pReadLen);
+
+				if(UartRecvPtr != NULL)
+				{
+					free(UartRecvPtr);
+				}
+				UartRecvPtr = NULL;
 			}
 			PROC_TCP_STATE_SWITCH(PROCESS_TCP_IDLE);
 			break;
@@ -179,7 +194,7 @@ sint8 TcpDataSendFunc(sint8 ConnectId)
 	{
 		return 0; //暂时无数据可以发
 	}
-	outValue = tcpipConnectionSend(ConnectId,(uint8 *)pSendDataAddr,DataSendLen);//发送函数
+	outValue = tcpipConnectionSend(ConnectId, (uint8 *)pSendDataAddr, DataSendLen); //发送函数
 	if (pSendDataAddr != 0)
 	{
 		free((uint8 *)(pSendDataAddr));
@@ -201,12 +216,19 @@ sint8 TcpConnectFunc(sint8 *ConnectId)
 			char *ATCmdSend = (char *)("ATE0\r\n");
 			uint8 ATCmdSendLen = mstrlen(ATCmdSend);
 			uint8 ReadLen = 0;
-			memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
+			uint8 *UartRecvPtr = NULL;
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen,&UartRecvPtr, &ReadLen, pdMS_TO_TICKS(1000));
 			uint8 *retptr = NULL;
 			if (ReadLen > 0)
 			{
-				retptr = (uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("OK"));
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+
+				if(UartRecvPtr != NULL)
+				{
+					free(UartRecvPtr);
+				}
+				UartRecvPtr = NULL;
+
 				if (retptr)
 				{
 					ConnectStep++;
@@ -226,7 +248,7 @@ sint8 TcpConnectFunc(sint8 *ConnectId)
 		}
 		case 1: // Netopen
 		{
-			AtcmdTransmit(AT_NETOPEN, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_NETOPEN, NULL, 0, &ATRet,100);
 			if (ATRet == 0)
 			{
 				ConnectStep++;
@@ -240,7 +262,7 @@ sint8 TcpConnectFunc(sint8 *ConnectId)
 		}
 		case 2: //连接检查
 		{
-			AtcmdTransmit(AT_CONNECTCHK, NULL, 0, &ATRet); // ATret返回的值是连接id，如果未连接返回-1
+			AtcmdTransmit(AT_CONNECTCHK, NULL, 0, &ATRet,1000); // ATret返回的值是连接id，如果未连接返回-1
 			if (ATRet >= 0)
 			{
 				*ConnectId = ATRet;
@@ -260,7 +282,7 @@ sint8 TcpConnectFunc(sint8 *ConnectId)
 			memcpy(AtCmdSend, WebSiteName, AtCmdSendLen);
 			memcpy(AtCmdSend + AtCmdSendLen, (char *)CRLF, sizeof(CRLF));
 			AtCmdSendLen = AtCmdSendLen + 2;
-			AtcmdTransmit(AT_CGIP, AtCmdSend, AtCmdSendLen, &ATRet);
+			AtcmdTransmit(AT_CGIP, AtCmdSend, AtCmdSendLen, &ATRet,5000);
 			if (ATRet == 0)
 			{
 				ConnectStep++;
@@ -279,7 +301,7 @@ sint8 TcpConnectFunc(sint8 *ConnectId)
 			*ConnectId = 0;
 			sprintf(AtCmdSend, "%d,\"TCP\",%s,%d\r\n", *ConnectId, WebSiteIp, WebSitePort); //此处需要优化
 			AtCmdSendTotalLen = mstrlen(AtCmdSend);
-			AtcmdTransmit(AT_CONNECT, AtCmdSend, AtCmdSendTotalLen, &ATRet);
+			AtcmdTransmit(AT_CONNECT, AtCmdSend, AtCmdSendTotalLen, &ATRet,10000);
 			if (ATRet == 0)
 			{
 				ConnectStep++;
@@ -309,7 +331,7 @@ sint8 TcpRegisterChkFunc(void)
 		{
 		case 0: // AT指令同步
 		{
-			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet,100);
 			if (ATRet == 0)
 			{
 				RegChkStep++;
@@ -323,7 +345,7 @@ sint8 TcpRegisterChkFunc(void)
 		}
 		case 1: // CPIN检查
 		{
-			AtcmdTransmit(AT_SIMREADY, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_SIMREADY, NULL, 0, &ATRet,100);
 			if (ATRet == 0)
 			{
 				RegChkStep++;
@@ -337,7 +359,7 @@ sint8 TcpRegisterChkFunc(void)
 		}
 		case 2:
 		{
-			AtcmdTransmit(AT_CGREG, NULL, 0, &ATRet); //驻网检查，返回值1和5是驻网成功
+			AtcmdTransmit(AT_CGREG, NULL, 0, &ATRet,1000); //驻网检查，返回值1和5是驻网成功
 			if (ATRet == 1 || ATRet == 5)
 			{
 				RegChkStep++;
@@ -364,20 +386,21 @@ void InitFunc(void)
 	uint8 ReadLen = 0;
 	char *ATCmdSend = NULL;
 	uint8 ATCmdSendLen = 0;
+	uint8 *UartRecvPtr = NULL;
 	while (1)
 	{
 		switch (_4G_InitStep)
 		{
 		case 0: // AT指令同步
 		{
-			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_CMD_TEST, NULL, 0, &ATRet,100);
 			if (ATRet == 0)
 			{
 				_4G_InitStep++;
 			}
 			else
 			{
-				_4G_InitStep = 0;
+				vTaskDelay(pdMS_TO_TICKS(100));
 			}
 			break;
 		}
@@ -385,37 +408,41 @@ void InitFunc(void)
 		{
 			ATCmdSend = (char *)("ATE0\r\n");
 			ATCmdSendLen = mstrlen(ATCmdSend);
-			memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(10000));
 			uint8 *retptr = NULL;
 			if (ReadLen > 0)
 			{
-				retptr = (uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("OK"));
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
 				if (retptr)
 				{
 					_4G_InitStep++;
 				}
 				else
 				{
-					_4G_InitStep = 0;
+					_4G_InitStep=0;
 				}
 			}
 			else
 			{
-				_4G_InitStep = 0;
+				_4G_InitStep=0;
 			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
 			break;
 		}
 		case 2: // IMEI获取
 		{
 			ATCmdSend = (char *)("AT+SIMEI?\r\n");
 			ATCmdSendLen = mstrlen(ATCmdSend);
-			memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+
 			uint8 *retptr = NULL;
 			if (ReadLen > 0)
 			{
-				retptr = (uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("+SIMEI"));
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("+SIMEI"));
 				if (retptr)
 				{
 					memcpy(ImeiNum, retptr + 8, 15);
@@ -423,65 +450,81 @@ void InitFunc(void)
 				}
 				else
 				{
-					_4G_InitStep = 0;
+					_4G_InitStep=0;
 				}
 			}
 			else
 			{
 				_4G_InitStep = 0;
 			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
 			break;
 		}
 		case 3: // 打开时间自动更新
 		{
 			ATCmdSend = (char *)("AT+CTZU=1\r\n");
 			ATCmdSendLen = mstrlen(ATCmdSend);
-			memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
 			uint8 *retptr = NULL;
 			if (ReadLen > 0)
 			{
-				retptr = (uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("OK"));
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
 				if (retptr)
 				{
 					_4G_InitStep++;
 				}
-				else
-				{
-					_4G_InitStep = 0;
-				}
 			}
 			else
 			{
 				_4G_InitStep = 0;
 			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
 			break;
 		}
 		case 4: // ICCID获取
 		{
-			AtcmdTransmit(AT_GETICCID, NULL, 0, &ATRet);
+			AtcmdTransmit(AT_GETICCID, NULL, 0, &ATRet,1000);
 			if (ATRet == 0)
 			{
 				_4G_InitStep++;
 			}
 			else
 			{
-				_4G_InitStep++;
+				_4G_InitStep=0;
 			}
 			break;
 		}
-		case 0xFF://GNSS开启
+		case 5:
 		{
-			AtcmdTransmit(AT_CGNSSPWR, NULL, 0, &ATRet);
-			if (ATRet == 0)
+			ATCmdSend = (char *)("AT+CIPSENDMODE=0\r\n");
+			ATCmdSendLen = mstrlen(ATCmdSend);
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, ATCmdSendLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+			uint8 *retptr = NULL;
+			if (ReadLen > 0)
 			{
-				_4G_InitStep++;
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+				if (retptr)
+				{
+					_4G_InitStep++;
+				}
 			}
 			else
 			{
 				_4G_InitStep = 0;
 			}
-			break;
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
 		}
 		default:
 		{
@@ -491,12 +534,13 @@ void InitFunc(void)
 		}
 	}
 }
-static void AtcmdTransmit(sint8 CmdIdx, uint8 *SetValuePtr, uint16 SetValueLen, sint8 *retFunc)
+static void AtcmdTransmit(sint8 CmdIdx, uint8 *SetValuePtr, uint16 SetValueLen, sint8 *retFunc,uint16 timeout)
 {
 	uint16 ReadLen = 0;
 	uint8 *PtrATCmdSend = NULL;
 	uint8 ATCmdFixedLen = 0;
 	uint16 ATCmdTotalLen = 0;
+	uint8 *UartRecvPtr=NULL;
 	ATCmdFixedLen = mstrlen(Atcmdfunc[CmdIdx].str);
 	ATCmdTotalLen = ATCmdFixedLen + SetValueLen;
 	PtrATCmdSend = malloc(ATCmdTotalLen + 1);
@@ -506,17 +550,29 @@ static void AtcmdTransmit(sint8 CmdIdx, uint8 *SetValuePtr, uint16 SetValueLen,
 	{
 		memcpy(PtrATCmdSend + ATCmdFixedLen, SetValuePtr, SetValueLen);
 	}
-	memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
 
-	UART_Query_Data(UART_LPUART1, UART_LPUART1, PtrATCmdSend, ATCmdTotalLen, RX_Buffer[UART_LPUART1], &ReadLen, 1000);
-
-	*retFunc = Atcmdfunc[CmdIdx].cb(PtrATCmdSend, RX_Buffer[UART_LPUART1], CmdIdx, ReadLen);
+	UART_Query_Data(UART_LPUART1, UART_LPUART1, PtrATCmdSend, ATCmdTotalLen, &UartRecvPtr, &ReadLen, timeout);
+	if(ReadLen>0)
+	{
+		*retFunc = Atcmdfunc[CmdIdx].cb(PtrATCmdSend, UartRecvPtr, CmdIdx, ReadLen);
+	}
+	else
+	{
+		*retFunc = -1;
+	}
 	if (PtrATCmdSend != NULL)
 	{
 		memset(PtrATCmdSend, 0x00, ATCmdTotalLen + 1);
 		free(PtrATCmdSend);
 	}
 	PtrATCmdSend = NULL;
+
+	if(UartRecvPtr != NULL)
+	{
+		free(UartRecvPtr);
+	}
+	UartRecvPtr = NULL;
+
 	return;
 }
 sint8 at_callbackFunc(char *PSendStr, char *pReadStr, uint8 CmdIdx, uint16 pReadLen)
@@ -608,6 +664,7 @@ sint8 at_callbackFunc(char *PSendStr, char *pReadStr, uint8 CmdIdx, uint16 pRead
 	{
 		if (retptr)
 		{
+			memset(WebSiteIp,0x00,sizeof(WebSiteIp));
 			for (uint8 i = 0; i < 30; i++)
 			{
 				if (*(retptr - i) == ',')
@@ -640,13 +697,9 @@ sint8 at_callbackFunc(char *PSendStr, char *pReadStr, uint8 CmdIdx, uint16 pRead
 		{
 			OutValue = 0;
 		}
-		break;
-	}
-	case AT_CGNSSPWR:
-	{
-		if (retptr)
+		else
 		{
-			OutValue = 0;
+			OutValue = -1;
 		}
 		break;
 	}
@@ -673,10 +726,14 @@ void TcpDataEncode(uint32 *PtrSendAddr, uint16 *SendLen)
 	{
 		DataIdx = 0x83; //储能开关信息发送
 	}
-	else if (TcpSendTimeCounter % 240 == 0)
+	else if ((TcpSendTimeCounter+2) % 240 == 0)
 	{
 		DataIdx = GpsMsg; //定位信息发送
 	}
+	else if ((TcpSendTimeCounter+3) % 240 == 0)
+	{
+		DataIdx = 0x93; //储能电量信息发送
+	}
 	else
 	{
 		*SendLen = 0;
@@ -825,6 +882,7 @@ void TcpDataEncode(uint32 *PtrSendAddr, uint16 *SendLen)
 		uint16 DataLen;
 		*SendLen = ProtocolFixedLen + ProtocolFluctedLen;
 		SendBuffer = malloc(*SendLen);
+		GetCSQValue(&CSQValue);
 		if (SendBuffer == NULL)
 		{
 			return;
@@ -926,6 +984,45 @@ void TcpDataEncode(uint32 *PtrSendAddr, uint16 *SendLen)
 		*PtrSendAddr = (uint32)SendBuffer;
 		break;
 	}
+	case 0x93://储能场景的电量信息
+	{
+		StorageInfoToTcp2 StorageInfo2;
+		*SendLen = sizeof(StorageInfo);
+		SendBuffer = malloc(*SendLen);
+		uint16 DataLen = 0;
+		DataLen = (uint16)sizeof(StorageInfo2.StorageMsg2);
+		StorageInfo2.startSymbol[0] = TCP_START_SYM1;
+		StorageInfo2.startSymbol[1] = TCP_START_SYM2;
+		StorageInfo2.cmdSymbol = TCP_CMD_SYM;
+		StorageInfo2.ansSymbol = TCP_ANS_SYM;
+		memcpy(StorageInfo2.SN, TcpbattSN, BATT_SN_LEN);
+		StorageInfo2.encryptMethod = TCP_ENCPT_DISABLE; // not encrypt
+		StorageInfo2.dataLength[0] = (DataLen >> 8) & 0xFF;
+		StorageInfo2.dataLength[1] = DataLen & 0xFF;
+		StorageInfo2.StorageMsg2.sendTimeUTC[0] = (UTC8TimeTcp.year) & 0xFF; // year
+		StorageInfo2.StorageMsg2.sendTimeUTC[1] = UTC8TimeTcp.month & 0xFF;	// month
+		StorageInfo2.StorageMsg2.sendTimeUTC[2] = UTC8TimeTcp.day & 0xFF;	// day
+		StorageInfo2.StorageMsg2.sendTimeUTC[3] = UTC8TimeTcp.hour & 0xFF;	// hour
+		StorageInfo2.StorageMsg2.sendTimeUTC[4] = UTC8TimeTcp.minute & 0xFF; // mins
+		StorageInfo2.StorageMsg2.sendTimeUTC[5] = UTC8TimeTcp.second & 0xFF; // sec
+		StorageInfo2.StorageMsg2.msgMark = DataIdx;
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[0] = (UTC8TimeTcp.year) & 0xFF; // year
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[1] = UTC8TimeTcp.month & 0xFF;	 // month
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[2] = UTC8TimeTcp.day & 0xFF;	 // day
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[3] = UTC8TimeTcp.hour & 0xFF;	 // hour
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[4] = UTC8TimeTcp.minute & 0xFF; // mins
+		StorageInfo2.StorageMsg2.msgCollectionTimeUTC[5] = UTC8TimeTcp.second & 0xFF;
+		StorageInfo2.StorageMsg2.meter1AllPwr = meterAllPwr[0];
+		StorageInfo2.StorageMsg2.meter1PosPwr = meterPosPwr[0];
+		StorageInfo2.StorageMsg2.meter1NegPwr = meterNegPwr[0];
+		StorageInfo2.StorageMsg2.meter2AllPwr = meterAllPwr[1];
+		StorageInfo2.StorageMsg2.meter2PosPwr = meterPosPwr[1];
+		StorageInfo2.StorageMsg2.meter2NegPwr = meterNegPwr[1];
+		StorageInfo2.CRC = bcc_chk((uint8 *)&StorageInfo2, sizeof(StorageInfo2) - 1);
+		memcpy(SendBuffer, &StorageInfo2, sizeof(StorageInfo2));
+		*PtrSendAddr = (uint32)SendBuffer;
+		break;
+	}
 	default:
 		break;
 	}
@@ -936,13 +1033,13 @@ void GetUtc8Time(UTC8TimeType *UTC8TimeTcp)
 	uint8 AtCmdLen = mstrlen(AtCmdAsk);
 	uint8 ReadLen = 0;
 	uint8 *retptr = NULL;
-	memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-	UART_Query_Data(UART_LPUART1, UART_LPUART1, AtCmdAsk, AtCmdLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
+	uint8 *UartRecvPtr=NULL;
+	UART_Query_Data(UART_LPUART1, UART_LPUART1, AtCmdAsk, AtCmdLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
 	if (ReadLen > 0)
 	{
-		if ((uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("OK")))
+		if ((uint8 *)strstr((char *)UartRecvPtr, (char *)("OK")))
 		{
-			retptr = (uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("+CCLK:"));
+			retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("+CCLK:"));
 			UTC8TimeTcp->year = CharToHex(*(retptr + 8)) * 10 + CharToHex(*(retptr + 9));
 			UTC8TimeTcp->month = CharToHex(*(retptr + 11)) * 10 + CharToHex(*(retptr + 12));
 			UTC8TimeTcp->day = CharToHex(*(retptr + 14)) * 10 + CharToHex(*(retptr + 15));
@@ -950,48 +1047,95 @@ void GetUtc8Time(UTC8TimeType *UTC8TimeTcp)
 			UTC8TimeTcp->minute = CharToHex(*(retptr + 20)) * 10 + CharToHex(*(retptr + 21));
 			UTC8TimeTcp->second = CharToHex(*(retptr + 23)) * 10 + CharToHex(*(retptr + 24));
 		}
+
+		if(UartRecvPtr != NULL)
+		{
+			free(UartRecvPtr);
+		}
+		UartRecvPtr = NULL;
 	}
 }
-static void TcpDataInfoRecvHandle(uint8 *DataRecv,uint16 DataRecvLen)
+static void GetCSQValue(uint8 *out)
 {
-    uint8 Tcp_Cmd;
-    uint8 *Ptr=NULL,*retptr=NULL;
-    uint8 TcpCmdAnswer[31];
-    uint16 TcpDataLen = 0;
-    uint16 NumCalTemp = 1;
-    retptr = (uint8 *)strstr((char *)DataRecv, (char *)("\r\n##"));
-    if(retptr==NULL)return;
-    for(uint8 i=0;i<5;i++)
-    {
-    	if(*(retptr - i - 1)=='D')
+	char *AtCmdAsk = (char *)("AT+CSQ\r\n");
+	uint8 AtCmdLen = mstrlen(AtCmdAsk);
+	uint8 ReadLen = 0;
+	uint8 *retptr = NULL;
+	uint8 *UartRecvPtr=NULL;
+	UART_Query_Data(UART_LPUART1, UART_LPUART1, AtCmdAsk, AtCmdLen, &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+	*out = 99;
+	if (ReadLen > 0)
+	{
+		if ((uint8 *)strstr((char *)UartRecvPtr, (char *)("OK")))
+		{
+			*out = 0;
+			retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("+CSQ:"));
+			char CsqStr[5];
+			for (uint8 i = 0; i < 5; i++)
+			{
+				if (*(retptr+i+6) == ',')
+				{
+					break;
+				}
+				memcpy((CsqStr+i),(retptr+i+6),1);
+			}
+			*out = atoi(CsqStr);
+		}
+
+		if(UartRecvPtr != NULL)
+		{
+			free(UartRecvPtr);
+		}
+		UartRecvPtr = NULL;
+	}
+	return;
+}
+static void TcpDataInfoRecvHandle(uint8 *DataRecv, uint16 DataRecvLen)
+{
+	uint8 Tcp_Cmd;
+	uint8 *Ptr = NULL, *retptr = NULL;
+	uint8 TcpCmdAnswer[31];
+	uint16 TcpDataLen = 0;
+	uint16 NumCalTemp = 1;
+	retptr = (uint8 *)strstr((char *)DataRecv, (char *)("\r\n##"));
+	if (retptr == NULL)
+		return;
+	for (uint8 i = 0; i < 5; i++)
+	{
+		if (*(retptr - i - 1) == 'D')
 		{
 			break;
 		}
-    	TcpDataLen = TcpDataLen + CharToHex(*(retptr - i - 1))*NumCalTemp;
-    	NumCalTemp = NumCalTemp*10;
-    }
-    if (TcpDataLen>0)
-    {
-        Ptr = retptr + 2;
-        if ((*(Ptr + 0) == TCP_START_SYM1) && (*(Ptr + 1) == TCP_START_SYM2)) //服务器起始信息
-        {
-            Tcp_Cmd = *(Ptr + 2); //命令标志
-//            if (*(Ptr + 3) == 0xFE)
-//            {
-//                TCPWorkState = 0x01;//需要暂停发送，进行命令应答的标志
-//            }
-            switch (Tcp_Cmd)
-            {
-            case TCP_QUERY_SYM:
-                break;
-            case TCP_SETCMD_SYM:
-                break;
-            case TCP_CONCMD_SYM:
-            {
-                TcpCmdAnswer[0] = TCP_START_SYM1;
-                TcpCmdAnswer[1] = TCP_START_SYM1;
-                TcpCmdAnswer[2] = TCP_CONCMD_SYM;
-                if (*(Ptr + 30) == 0x80) //远程锁定命令
+		TcpDataLen = TcpDataLen + CharToHex(*(retptr - i - 1)) * NumCalTemp;
+		NumCalTemp = NumCalTemp * 10;
+	}
+	if (TcpDataLen > 0)
+	{
+		Ptr = retptr + 2;
+		if ((*(Ptr + 0) == TCP_START_SYM1) && (*(Ptr + 1) == TCP_START_SYM2)) //服务器起始信息
+		{
+			Tcp_Cmd = *(Ptr + 2); //命令标志
+			if (*(Ptr + 3) == 0xFE)
+			{
+				TcpWorkState = 0x01;//需要暂停发送，进行命令应答的标志
+			}
+			switch (Tcp_Cmd)
+			{
+			case TCP_QUERY_SYM:
+				break;
+			case TCP_SETCMD_SYM:
+				break;
+			case TCP_CONCMD_SYM:
+			{
+				TcpCmdAnswer[0] = TCP_START_SYM1;
+				TcpCmdAnswer[1] = TCP_START_SYM1;
+				TcpCmdAnswer[2] = TCP_CONCMD_SYM;
+				if (*(Ptr + 30) == 0x01) //远程升级指令
+				{
+					//Fota_Func(Ptr, SocketId);
+					//Fota_Ftp();
+				}
+                else if (*(Ptr + 30) == 0x80) //远程锁定命令
                 {
                     TcpCmdAnswer[3] = 0x01;
                     memcpy(&TcpCmdAnswer[4], (Ptr + 4), BATT_SN_LEN);
@@ -1003,17 +1147,36 @@ static void TcpDataInfoRecvHandle(uint8 *DataRecv,uint16 DataRecvLen)
                     if (*(Ptr + 31) == 0x01) // 0x01代表锁定
                     {
                     	battSeparateEnable = 1;
-                    	battSeparateEnableState = 1;
+                    	battSeparateCtlState = 1;
                         tcpipConnectionSend(SocketId, TcpCmdAnswer, 31 );
                     }
                     else if (*(Ptr + 31) == 0x02) // 0x02代表解锁
                     {
                     	battSeparateEnable = 1;
-                    	battSeparateEnableState = 0;
+                    	battSeparateCtlState = 0;
                         tcpipConnectionSend(SocketId, TcpCmdAnswer, 31);
                     }
                 }
+				else
+				{
+					TcpCmdAnswer[3] = 0x0f;
+					memcpy(&TcpCmdAnswer[4], (Ptr + 4), BATT_SN_LEN);
+					TcpCmdAnswer[21] = TCP_ENCPT_DISABLE;
+					TcpCmdAnswer[22] = 0x00;
+					TcpCmdAnswer[23] = 0x06;
+					memcpy(&TcpCmdAnswer[24], (Ptr + 24), 6);
+					TcpCmdAnswer[30] = bcc_chk(TcpCmdAnswer, 30);
+					tcpipConnectionSend(SocketId, TcpCmdAnswer, 31);
+				}
+				break;
             }
+			case TCP_UDSCMD_SYM:
+			{
+				TcpCmdAnswer[0] = TCP_START_SYM1;
+				TcpCmdAnswer[1] = TCP_START_SYM1;
+				TcpCmdAnswer[2] = TCP_UDSCMD_SYM;
+				break;
+			}
             default:
             {
                 break;
@@ -1022,24 +1185,269 @@ static void TcpDataInfoRecvHandle(uint8 *DataRecv,uint16 DataRecvLen)
         }
     }
 }
-static sint8 tcpipConnectionSend(uint8 TcpConnectId,uint8 * SendDataPtr,uint16 SendDataLen)
+sint8 tcpipConnectionSend(uint8 TcpConnectId, uint8 *SendDataPtr, uint16 SendDataLen)
 {
 	sint8 outValue = -1;
-	sint8 ATRet = -1;
+	uint8  sendErrConuter= 0;
 	uint8 ReadLen = 0;
-	char AtCmdSend[10] = {0};
+	char AtCmdSend[20] = {0};
 	uint8 AtCmdSendTotalLen = 0;
-	sprintf(AtCmdSend, "%d,%d\r\n", TcpConnectId, SendDataLen);
+	uint8 *UartRecvPtr1 =NULL;
+	uint8 *UartRecvPtr =NULL;
+	uint8 ret = 0;
+	sprintf(AtCmdSend, "AT+CIPSEND=%d,%d\r\n", TcpConnectId, SendDataLen);
 	AtCmdSendTotalLen = mstrlen(AtCmdSend);
-	AtcmdTransmit(AT_SEND, AtCmdSend, AtCmdSendTotalLen, &ATRet);
-	if (ATRet == 0)
+	while(outValue!=0&&sendErrConuter<10)
 	{
-		memset(RX_Buffer[UART_LPUART1], 0x00, sizeof(RX_Buffer[UART_LPUART1]));
-		UART_Query_Data(UART_LPUART1, UART_LPUART1, (uint8 *)SendDataPtr, SendDataLen, RX_Buffer[UART_LPUART1], &ReadLen, 100);
-		if ((uint8 *)strstr((char *)RX_Buffer[UART_LPUART1], (char *)("OK")))
+		ret = UART_Query_Data(UART_LPUART1, UART_LPUART1, (uint8 *)AtCmdSend, AtCmdSendTotalLen, &UartRecvPtr1, &ReadLen, 2000);
+		if (ret==0&&ReadLen>0&&(uint8 *)strstr((char *)UartRecvPtr1, (char *)(">"))||0)//一个字节收不到的问题，IDE中断间隔过大不行
 		{
-			outValue = 0;
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, (uint8 *)SendDataPtr, SendDataLen, &UartRecvPtr, &ReadLen, 2000);
+			if (ReadLen>0&&(uint8 *)strstr((char *)UartRecvPtr, (char *)("\r\nOK\r\n\r\n+CIPSEND")))
+			{
+				outValue = 0;
+			}
+			else
+			{
+				outValue = -2;
+				sendErrConuter++;
+			}
 		}
+		else
+		{
+			outValue = -1;
+			sendErrConuter++;
+		}
+	}
+	if(UartRecvPtr != NULL)
+	{
+		free(UartRecvPtr);
+	}
+	UartRecvPtr = NULL;
+	if(UartRecvPtr1 != NULL)
+	{
+		free(UartRecvPtr1);
 	}
+	UartRecvPtr1 = NULL;
 	return outValue;
 }
+void Fota_Ftp(void)
+{
+	uint8 ftp_process = 0;
+	uint8 ftp_EndFlg = 0;
+	uint8 ftp_ErrCnt = 0;
+	char *ATCmdSend = NULL;
+	uint8 ATCmdSendLen = 0;
+	uint8 *UartRecvPtr = NULL;
+	uint16 ReadLen = 0;
+	uint8 *retptr = NULL;
+	while(!ftp_EndFlg)
+	{
+		vTaskDelay(pdMS_TO_TICKS(100));
+		if(ftp_ErrCnt>5)
+		{
+			ftp_ErrCnt = 0;
+			ftp_EndFlg = 1;
+		}
+		switch(ftp_process)
+		{
+		case 0://start
+		{
+			ATCmdSend = (char *)("AT+CFTPSSTART\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+			if (ReadLen > 0)
+			{
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+				if (retptr)
+				{
+					ftp_ErrCnt = 0;
+					ftp_process++;
+				}
+			}
+			else
+			{
+				ftp_ErrCnt++;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		case 1://login
+		{
+			uint8 *UartData = NULL;
+			ATCmdSend = (char *)("AT+CFTPSLOGIN=\"nas.fast-fun.cn\",21,\"qx\",\"qx900\",0\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(1000));
+			while (1)
+			{
+				UART_Receive_Data(UART_LPUART1,&UartData, &ReadLen,10000);
+				retptr = (uint8 *)strstr((char *)UartData, (char *)("+CFTPSLOGIN: 0"));
+				if (retptr)
+				{
+					ftp_ErrCnt = 0;
+					ftp_process++;
+					break;
+				}
+				else
+				{
+					ftp_ErrCnt++;
+				}
+				if(ftp_ErrCnt>5)
+				{
+					ftp_ErrCnt = 0;
+					ftp_process = 0;
+					ftp_EndFlg = 1;
+					break;
+				}
+				if(UartData != NULL)
+				{
+					free(UartData);
+				}
+				UartData = NULL;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		case 2://transmit server to module
+		{
+			uint8 *UartData = NULL;
+			ATCmdSend = (char *)("AT+CFTPSGETFILE=\"V0.0.1.5.bin\"\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(1000));
+			while (1)
+			{
+				UART_Receive_Data(UART_LPUART1,&UartData, &ReadLen,10000);
+				retptr = (uint8 *)strstr((char *)UartData, (char *)("+CFTPSGETFILE: 0"));
+				if (retptr)
+				{
+					ftp_ErrCnt = 0;
+					ftp_process++;
+					break;
+				}
+				else
+				{
+					ftp_ErrCnt++;
+				}
+				if(ftp_ErrCnt>5)
+				{
+					ftp_ErrCnt = 0;
+					ftp_process++;
+					break;
+				}
+				if(UartData != NULL)
+				{
+					free(UartData);
+				}
+				UartData = NULL;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		case 3://get data from module
+		{
+			uint8 *UartData = NULL;
+			uint32 currentAddr = 0;
+			uint16 readLen = 128;
+			uint32 fileLen = 65535;
+			ATCmdSend = (char *)("AT+FSATTRI=V0.0.1.5.bin\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+			if (ReadLen > 0)
+			{
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+				if (retptr)
+				{
+					while(readLen!=0)
+					{
+						sprintf(ATCmdSend, "AT+CFTRANTX=\"c:/V0.0.1.5.bin\",%d,%d\r\n\r\n", currentAddr, readLen);
+						UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartData, &ReadLen, pdMS_TO_TICKS(100));
+						if (ReadLen > 0)
+						{
+							retptr = (uint8 *)strstr((char *)UartData, (char *)("+CFTRANTX: DATA"));
+							if (retptr)
+							{
+								//数据处理区域
+								currentAddr = currentAddr + readLen;
+								readLen = min(fileLen-currentAddr,readLen);
+							}
+						}
+						if(UartData != NULL)
+						{
+							free(UartData);
+						}
+						UartData = NULL;
+					}
+				}
+			}
+			else
+			{
+				ftp_ErrCnt++;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		case 4://logout
+		{
+			ATCmdSend = (char *)("AT+CFTPSLOGOUT\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+			if (ReadLen > 0)
+			{
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+				if (retptr)
+				{
+					ftp_process++;
+					ftp_ErrCnt = 0;
+				}
+			}
+			else
+			{
+				ftp_ErrCnt++;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		case 5://stop
+		{
+			ATCmdSend = (char *)("AT+CFTPSSTOP\r\n");
+			UART_Query_Data(UART_LPUART1, UART_LPUART1, ATCmdSend, mstrlen(ATCmdSend), &UartRecvPtr, &ReadLen, pdMS_TO_TICKS(100));
+			if (ReadLen > 0)
+			{
+				retptr = (uint8 *)strstr((char *)UartRecvPtr, (char *)("OK"));
+				if (retptr)
+				{
+					ftp_process++;
+				}
+			}
+			else
+			{
+				ftp_ErrCnt++;
+			}
+			if(UartRecvPtr != NULL)
+			{
+				free(UartRecvPtr);
+			}
+			UartRecvPtr = NULL;
+			break;
+		}
+		default:
+			ftp_EndFlg = 1;
+			break;
+		}
+	}
+}

src/AppTaskUart1.h

@@ -3,7 +3,7 @@
  * @Date         : 2022-02-10 11:44:08
  * @Version      : V3.0
  * @LastEditors  : ChenJie
- * @LastEditTime : 2022-02-14 15:48:07
+ * @LastEditTime : 2022-05-17 16:22:56
  * @Description  : file content
  * @FilePath     : \S32K146_4G\src\AppTaskUart1.h
  */
@@ -38,6 +38,7 @@
 #define TCP_QUERY_SYM 0x80
 #define TCP_SETCMD_SYM 0x81
 #define TCP_CONCMD_SYM 0x82
+#define TCP_UDSCMD_SYM 0x83
 typedef struct _GPSInfoType
 {
 	uint8 sendTimeUTC[6];
@@ -63,98 +64,122 @@ typedef struct GPSMsgtoTcpType
 } GPSMsgtoTcpType;
 typedef struct _VerInfoType
 {
-	uint8	sendTimeUTC[6];
-	uint8	msgMark;
-	uint8	msgCollectionTimeUTC[6];
-	uint8	ICCID[20];
-	uint8	IMEI[15];
-	uint8	BMSHwVersion[2];
-	uint8	BMSSwVersion[4];
-	uint8	HwVersion[2];
-	uint8	BLVersion[4];
-	uint8	DRVVersion[4];
-	uint8	APPVersion[4];
-	uint8	BmsType;
-	uint8	BmsInfo;
-	uint8   DataModuleType;
-}VerInfoType;
+	uint8 sendTimeUTC[6];
+	uint8 msgMark;
+	uint8 msgCollectionTimeUTC[6];
+	uint8 ICCID[20];
+	uint8 IMEI[15];
+	uint8 BMSHwVersion[2];
+	uint8 BMSSwVersion[4];
+	uint8 HwVersion[2];
+	uint8 BLVersion[4];
+	uint8 DRVVersion[4];
+	uint8 APPVersion[4];
+	uint8 BmsType;
+	uint8 BmsInfo;
+	uint8 DataModuleType;
+} VerInfoType;
 typedef struct VersionMsgtoTcpType
 {
-	uint8 	startSymbol[2];
-	uint8	cmdSymbol;
-	uint8	ansSymbol;
-	uint8	SN[BATT_SN_LEN];
-	uint8	encryptMethod;
-	uint8	dataLength[2];
+	uint8 startSymbol[2];
+	uint8 cmdSymbol;
+	uint8 ansSymbol;
+	uint8 SN[BATT_SN_LEN];
+	uint8 encryptMethod;
+	uint8 dataLength[2];
 	VerInfoType VerInfo;
-	uint8	CRC;
-}VersionMsgtoTcpType;
+	uint8 CRC;
+} VersionMsgtoTcpType;
 typedef struct StorageInfoType
 {
-	uint8	sendTimeUTC[6];
-	uint8	msgMark;
-	uint8	msgCollectionTimeUTC[6];
-	uint8 	RelayState;
-	uint8   FanState;
-	uint8	HeatState;
-	uint8 	ConvertState;
-}StorageInfo;
+	uint8 sendTimeUTC[6];
+	uint8 msgMark;
+	uint8 msgCollectionTimeUTC[6];
+	uint8 RelayState;
+	uint8 FanState;
+	uint8 HeatState;
+	uint8 ConvertState;
+} StorageInfo;
 typedef struct StorageInfoToTcpType
 {
-	uint8 	startSymbol[2];
-	uint8	cmdSymbol;
-	uint8	ansSymbol;
-	uint8	SN[BATT_SN_LEN];
-	uint8	encryptMethod;
-	uint8	dataLength[2];
+	uint8 startSymbol[2];
+	uint8 cmdSymbol;
+	uint8 ansSymbol;
+	uint8 SN[BATT_SN_LEN];
+	uint8 encryptMethod;
+	uint8 dataLength[2];
 	StorageInfo StorageMsg;
-	uint8	CRC;
-}StorageInfoToTcp;
+	uint8 CRC;
+} StorageInfoToTcp;
+typedef struct StorageInfoType2
+{
+	uint8 sendTimeUTC[6];
+	uint8 msgMark;
+	uint8 msgCollectionTimeUTC[6];
+	uint32 meter1AllPwr;
+	uint32 meter1PosPwr;
+	uint32 meter1NegPwr;
+	uint32 meter2AllPwr;
+	uint32 meter2PosPwr;
+	uint32 meter2NegPwr;
+} StorageInfo2;
+typedef struct StorageInfoToTcpType2
+{
+	uint8 startSymbol[2];
+	uint8 cmdSymbol;
+	uint8 ansSymbol;
+	uint8 SN[BATT_SN_LEN];
+	uint8 encryptMethod;
+	uint8 dataLength[2];
+	StorageInfo2 StorageMsg2;
+	uint8 CRC;
+} StorageInfoToTcp2;
 typedef struct UTC8Time_Type
 {
-    uint8 year;
-    uint8 month;
-    uint8 day;
-    uint8 hour;
-    uint8 minute;
-    uint8 second;
+	uint8 year;
+	uint8 month;
+	uint8 day;
+	uint8 hour;
+	uint8 minute;
+	uint8 second;
 } UTC8TimeType;
 typedef enum
 {
-    AT_CMD_TEST = 0,
-    AT_SIMREADY,
-    AT_GETICCID,
-    AT_CGREG,
-    AT_CSQ,
-    AT_NETOPEN,
-    AT_CGIP,
-    AT_CONNECT,
-    AT_CONNECTCHK,
-    AT_SEND,
-    AT_DISCON,
-    AT_NETCLOSE,
+	AT_CMD_TEST = 0,
+	AT_ATE0,
+	AT_SIMREADY,
+	AT_GETICCID,
+	AT_CGREG,
+	AT_CSQ,
+	AT_NETOPEN,
+	AT_CGIP,
+	AT_CONNECT,
+	AT_CONNECTCHK,
+	AT_SEND,
+	AT_DISCON,
+	AT_NETCLOSE,
 	AT_CGNSSPWR
 } ATCmd;
 typedef sint8 (*pFunc)(char *PSendStr, char *pReadStr, uint8 CmdIdx, uint16 pReadLen);
 sint8 at_callbackFunc(char *PSendStr, char *pReadStr, uint8 CmdIdx, uint16 pReadLen);
 typedef struct
 {
-    ATCmd cmd; /*指令序号*/
-    char *str; /*指令内容*/
-    pFunc cb;  /*对应的执行*/
+	ATCmd cmd; /*指令序号*/
+	char *str; /*指令内容*/
+	pFunc cb;  /*对应的执行*/
 } ATCmdFunc;
 typedef enum
 {
-    PROCESS_TCP_IDLE = 0,
-    PROCESS_TCP_ATSYS,
-    PROCESS_TCP_REGCHK,
-    PROCESS_TCP_CONNECT,
-    PROCESS_TCP_SEND,
-    PROCESS_TCP_RECV,
-    PROCESS_TCP_HEART,
-    PROCESS_TCP_SLEEP,
-    PROCESS_TCP_ERROR
+	PROCESS_TCP_IDLE = 0,
+	PROCESS_TCP_ATSYS,
+	PROCESS_TCP_REGCHK,
+	PROCESS_TCP_CONNECT,
+	PROCESS_TCP_SEND,
+	PROCESS_TCP_RECV,
+	PROCESS_TCP_HEART,
+	PROCESS_TCP_SLEEP,
+	PROCESS_TCP_ERROR
 } process_Tcp;
 void Uart_4G_Task(void *pvParameters);
-
+sint8 tcpipConnectionSend(uint8 TcpConnectId, uint8 *SendDataPtr, uint16 SendDataLen);
 #endif /* APPTASKUART1_H_ */

src/Hal_Fls.c

@@ -0,0 +1,324 @@
+/*
+ * Hal_Fls.c
+ *
+ *  Created on: 2022Äê4ÔÂ6ÈÕ
+ *      Author: Zhengchao
+ */
+#include "Hal_Fls.h"
+#include "math.h"
+/* Application can used space */
+const BlockInfo_t gs_astBlockNumB[] =
+{
+    {APP_B_START_ADDR, APP_B_END_ADDR},    /* Block logical B */
+};
+
+/* Application flash status, this status info should be saved into flash */
+static tAppFlashStatus gs_stAppFlashStatus;
+
+#define GetAppStatusPtr() (&gs_stAppFlashStatus)
+
+static tAppDownloadType gs_stAppDownloadInfo = {APP_VECTOR_TABLE_OFFSET,0,0};
+
+#define SetFlashEreaseStatus(bIsFlashEraseSuccessful) \
+    do{\
+        gs_stAppFlashStatus.isFlashErasedSuccessfull = bIsFlashEraseSuccessful;\
+    }while(0u)
+
+#define SetFlashProgramStatus(bIsFlashProgramSuccessful) \
+    do{\
+        gs_stAppFlashStatus.isFlashProgramSuccessfull = bIsFlashProgramSuccessful;\
+    }while(0u)
+
+#define SetAppUpdateControllerName(bControolerName) \
+    do{\
+        gs_stAppFlashStatus.controllerName = bControolerName;\
+    }while(0u)
+
+#define SaveAppResetHandlerAddr(resetHandlerAddr, resetHnadlerAddrLen) \
+    do{\
+        gs_stAppFlashStatus.appStartAddr = resetHandlerAddr;\
+        gs_stAppFlashStatus.appStartAddrLen = resetHnadlerAddrLen;\
+    }while(0u)
+
+
+#define SaveAppStatusCrc(xCrc)\
+    do{\
+        gs_stAppFlashStatus.crc = xCrc;\
+    }while(0u)
+
+/* Create APP status CRC and save */
+#define CreateAndSaveAppStatusCrc(o_pCrc) \
+    do{\
+        CreateAppStatusCrc(o_pCrc);\
+        SaveAppStatusCrc(*o_pCrc);\
+    }while(0u)
+
+#define CreateAppStatusCrc(o_pCrc) CRC_HAL_CreatSoftwareCrc((uint8 *)&gs_stAppFlashStatus, sizeof(gs_stAppFlashStatus) - 4u, o_pCrc)
+
+#define IsFlashEraseSuccessful() (gs_stAppFlashStatus.isFlashErasedSuccessfull)
+#define IsFlashProgramSuccessful() (gs_stAppFlashStatus.isFlashProgramSuccessfull)
+
+
+static void Hal_FlsSaveFingerPrint(const uint8 *i_pFingerPrint, const uint8 i_FingerPrintLen);
+
+
+#define SetFlashStructStatus(bIsAppFlashStructValid) \
+    do{\
+        gs_stAppFlashStatus.isFlashStructValid = bIsAppFlashStructValid;\
+    }while(0u)
+
+#define SetDownloadAppLength(bAppLength) \
+    do{\
+    	gs_stAppDownloadInfo.appLength = bAppLength;\
+    	gs_stAppFlashStatus.appLength = bAppLength;\
+    }while(0u)
+
+#define SetDownloadAppPackCRC(bAppReceivedCRC) \
+    do{\
+    	gs_stAppDownloadInfo.receivedCRC = bAppReceivedCRC;\
+    }while(0u)
+
+
+
+//#define SetAPPStatus(bIsFlashEraseSuccessful, bIsFlashProgramSuccessful, bIsAppFlashStructValid) \
+//    do{\
+//        SetFlashEreaseStatus(bIsFlashEraseSuccessful);\
+//        SetFlashProgramStatus(bIsFlashProgramSuccessful);\
+//        SetFlashStructStatus(bIsAppFlashStructValid);\
+//    }while(0u)
+
+
+MemIf_JobResultType Hal_FlsWrite(Fls_AddressType u32TargetAddress, uint8 * pSourceAddressPtr, Fls_LengthType u32Length, uint32 timeOutMs)
+{
+	MemIf_JobResultType ret = MEMIF_JOB_FAILED;
+	if(TRUE == IsFlashEraseSuccessful())
+	{
+		Fls_Write(u32TargetAddress,pSourceAddressPtr,u32Length);
+		do
+		{
+			Fls_MainFunction();
+			vTaskDelay(pdMS_TO_TICKS(1));
+			timeOutMs--;
+		}while(MEMIF_IDLE != Fls_GetStatus() && timeOutMs>0);
+		ret = Fls_GetJobResult();
+	}
+	return ret;
+}
+
+MemIf_JobResultType Hal_FlsRead(Fls_AddressType u32TargetAddress, uint8 * pSourceAddressPtr, Fls_LengthType u32Length, uint32 timeOutMs)
+{
+	MemIf_JobResultType ret = MEMIF_JOB_FAILED;
+	Fls_Read(u32TargetAddress,pSourceAddressPtr,u32Length);
+	while(MEMIF_IDLE != Fls_GetStatus() && timeOutMs>0)
+	{
+		Fls_MainFunction();
+		vTaskDelay(pdMS_TO_TICKS(1));
+		timeOutMs--;
+	}
+	ret = Fls_GetJobResult();
+	return ret;
+}
+
+MemIf_JobResultType Hal_FlsErase(Fls_AddressType u32TargetAddress, uint32 eraseInternalLength, uint32 timeOutMs)
+{
+	MemIf_JobResultType ret = MEMIF_JOB_FAILED;
+	Fls_LengthType u32Length = 0;
+	if(eraseInternalLength > NUMBER_OF_INTERNAL_SECTOR * INTERNAL_SECTOR_SIZE)
+	{
+		u32Length = NUMBER_OF_INTERNAL_SECTOR * INTERNAL_SECTOR_SIZE;
+	}
+	else
+	{
+		u32Length = ceil((double)(eraseInternalLength/(double)(INTERNAL_SECTOR_SIZE))) * INTERNAL_SECTOR_SIZE;
+	}
+
+	Fls_Erase(u32TargetAddress,u32Length);
+	do
+	{
+		Fls_MainFunction();
+		vTaskDelay(pdMS_TO_TICKS(1));
+		timeOutMs--;
+	}while(MEMIF_IDLE != Fls_GetStatus() && timeOutMs>0);
+	ret = Fls_GetJobResult();
+	if(ret == MEMIF_JOB_OK)
+	{
+		SetFlashEreaseStatus(TRUE);
+	}
+	else
+	{
+		SetFlashEreaseStatus(FALSE);
+	}
+	return ret;
+}
+
+
+void Hal_SetAppInfo(uint32 appLength, uint32 appReceviedCRC,ControllerType controllerName)
+{
+	SetDownloadAppLength(appLength);
+	SetDownloadAppPackCRC(appReceviedCRC);
+	SetAppUpdateControllerName(controllerName);
+	uint32 fingerPrint = 0x5555;
+	Hal_FlsSaveFingerPrint(&fingerPrint, 2); //save finger print
+}
+
+
+/* Save FingerPrint */
+static void Hal_FlsSaveFingerPrint(const uint8 *i_pFingerPrint, const uint8 i_FingerPrintLen)
+{
+    uint8 FingerPrintLen = 0u;
+//    tCrc crc = 0u;
+//    ASSERT(NULL_PTR == i_pFingerPrint);
+
+    if (i_FingerPrintLen > FL_FINGER_PRINT_LENGTH)
+    {
+        FingerPrintLen = FL_FINGER_PRINT_LENGTH;
+    }
+    else
+    {
+        FingerPrintLen = (uint8)i_FingerPrintLen;
+    }
+
+    memcpy((void *) gs_stAppFlashStatus.aFingerPrint, (const void *) i_pFingerPrint,
+               FingerPrintLen);
+//    CreateAndSaveAppStatusCrc(&crc);
+}
+
+/* Get storage reset handler information */
+static uint32 Hal_FlsGetStorageRestHandlerAddr(void)
+{
+    return APP_VECTOR_TABLE_OFFSET + RESET_HANDLER_OFFSET;
+}
+
+/* Get reset handler addr length */
+static uint32 Hal_FlsGetResetHandlerLen(void)
+{
+    return RESET_HANDLER_ADDR_LEN;
+}
+
+static boolean Hal_GetAPPFlsInfo(uint32 *o_pAppInfoStartAddr, uint32 *o_pBlockSize)
+{
+    boolean result = FALSE;
+
+	*o_pAppInfoStartAddr = gs_astBlockNumB[0u].xBlockStartLogicalAddr;
+	*o_pBlockSize = gs_astBlockNumB[0u].xBlockEndLogicalAddr - gs_astBlockNumB[0u].xBlockStartLogicalAddr;
+	result = TRUE;
+
+    return result;
+}
+
+
+
+/* Flash check sum */
+static uint8 FlashChecksum(void)
+{
+    uint32 xCountCrc = 0u;
+    CRC_HAL_CreatSoftwareCrc((const uint8 *)(gs_stAppDownloadInfo.appVectoTableStartAddr + APP_FLAST_START_PHY_ADDR), gs_stAppDownloadInfo.appLength, &xCountCrc);
+
+    if(gs_stAppDownloadInfo.receivedCRC == xCountCrc)
+    {
+    	return TRUE;
+    }
+    else
+    {
+    	return FALSE;
+    }
+}
+
+static void Hal_FlsGetResetHandlerInfo(uint32 *o_pResetHandlerOffset, uint32 *o_pResetHandlerLength)
+{
+    if(NULL_PTR != o_pResetHandlerOffset && NULL_PTR != o_pResetHandlerLength)
+    {
+    	*o_pResetHandlerOffset = Hal_FlsGetStorageRestHandlerAddr();
+    	*o_pResetHandlerLength = Hal_FlsGetResetHandlerLen();
+    }
+}
+
+
+void Hal_FlsGetAppVectorTableStartAddr(uint32 *appVectorTableStartAddr)
+{
+	*appVectorTableStartAddr = gs_stAppDownloadInfo.appVectoTableStartAddr;
+}
+
+
+
+static uint8 Hal_FlsWriteFlashAppInfo(void)
+{
+
+	uint8 result = FALSE;
+	MemIf_JobResultType flsRet = MEMIF_JOB_FAILED;
+
+	tAppFlashStatus *pAppStatusPtr = NULL_PTR;
+	uint32 appInfoStartAddr = 0u;
+	uint32 appInfoLen = 0u;
+
+	uint32 resetHandlerOffset = 0u;
+	uint32 resetHandlerLength = 0u;
+
+	uint32 resetHandleLogicalAddr = 0u;
+	uint8 resetHandleAddrTemp[RESET_HANDLER_ADDR_LEN];
+	uint32 resetHandlePhyAddr = 0u;
+
+	uint32 crc = 0u;
+
+	/* Write data information in flash */
+	pAppStatusPtr = GetAppStatusPtr();
+
+	Hal_GetAPPFlsInfo(&appInfoStartAddr, &appInfoLen);
+
+	Hal_FlsGetResetHandlerInfo(&resetHandlerOffset,&resetHandlerLength);
+
+	resetHandleLogicalAddr = appInfoStartAddr + resetHandlerOffset;
+
+	Hal_FlsRead(resetHandleLogicalAddr,resetHandleAddrTemp,RESET_HANDLER_ADDR_LEN,500);
+
+	for(uint8 i=0; i<RESET_HANDLER_ADDR_LEN;i++)
+	{
+		resetHandlePhyAddr |= (resetHandleAddrTemp[i]<<(8*i));
+	}
+
+
+	SaveAppResetHandlerAddr(resetHandlePhyAddr, resetHandlerLength);
+
+
+	CreateAndSaveAppStatusCrc(&crc);
+
+	if(pAppStatusPtr != NULL_PTR)
+	{
+		 flsRet = Hal_FlsWrite(appInfoStartAddr,(uint8 *)pAppStatusPtr,sizeof(tAppFlashStatus),500);
+	}
+	if(flsRet == MEMIF_JOB_OK)
+	{
+		result = TRUE;
+	}
+	else
+	{
+		result = FALSE;
+	}
+	return result;
+
+}
+
+uint8 Hal_FlsCheckIsTransferSucceed(void)
+{
+	uint8 ret = FALSE;
+	if(TRUE == FlashChecksum())
+	{
+		SetFlashProgramStatus(TRUE);
+		ret = TRUE;
+	}
+	else
+	{
+		SetFlashProgramStatus(FALSE);
+		ret = FALSE;
+	}
+
+	SetFlashStructStatus(TRUE);
+	Hal_FlsWriteFlashAppInfo();
+
+	Hal_SetAppInfo(0,0xFFFFFFFF,CONTROLLER_SELF);
+	SetFlashEreaseStatus(FALSE);
+
+	return ret;
+}
+
+

src/Hal_Fls.h

@@ -0,0 +1,121 @@
+/*
+ * Hal_Fls.h
+ *
+ *  Created on: 2022Äê4ÔÂ6ÈÕ
+ *      Author: Zhengchao
+ */
+
+#ifndef HAL_FLS_H_
+#define HAL_FLS_H_
+
+#include "hal_adapter.h"
+#include "AppFunclib.h"
+#include "AppGlobalVar.h"
+#include "Hal_Wdg.h"
+#define EN_SUPPORT_APP_B
+
+typedef uint32 tLogicalAddr;
+
+typedef struct
+{
+    tLogicalAddr xBlockStartLogicalAddr; /* block start logical addr */
+    tLogicalAddr xBlockEndLogicalAddr;   /* block end logical addr */
+} BlockInfo_t;
+
+#define LOGICAL_START_ADDR           0U
+
+#define NUMBER_OF_INTERNAL_SECTOR    128U
+#define INTERNAL_SECTOR_SIZE         0x1000U
+
+
+#define APP_B_START_ADDR             0U
+#define APP_B_END_ADDR               NUMBER_OF_INTERNAL_SECTOR*INTERNAL_SECTOR_SIZE
+
+#define APP_FLAST_START_PHY_ADDR    (0x80000u)
+#define APP_VECTOR_TABLE_OFFSET (0x200u) /* Vector table offset from gs_astBlockNumA/B */
+#define RESET_HANDLER_OFFSET    (4u)     /* From top vector table to reset handle */
+#define RESET_HANDLER_ADDR_LEN  (4u)     /* Pointer length or reset handler length */
+/* Flash finger print length */
+#define FL_FINGER_PRINT_LENGTH  (17u)
+
+/* Program data buffer max length */
+#define MAX_FLASH_DATA_LEN (512u)
+
+#if (defined EN_SUPPORT_APP_B)
+
+
+typedef enum
+{
+    CONTROLLER_SELF = 1,
+	CONTROLLER_BLE,
+	CONTROLLER_B,
+	CONTROLLER_C,
+	CONTROLLER_D,
+	CONTROLLER_E,
+	CONTROLLER_F,
+}ControllerType;
+
+typedef struct
+{
+    /* Flash programming successful? If programming successful, the value set TRUE, else set FALSE */
+    uint8 isFlashProgramSuccessfull;
+
+    /* Is erase flash successful? If erased flash successful, set the TRUE, else set the FALSE. */
+    uint8 isFlashErasedSuccessfull;
+
+    /* Is Flash struct data valid? If written set the value is TRUE, else set the valid FALSE */
+    uint8 isFlashStructValid;
+
+    /* Indicate APP Counter. Before download. */
+    uint8 appCnt;
+
+    /* Is the App self update? If selfUpdate set the value is TRUE, else set the value FALSE*/
+    ControllerType controllerName;
+
+    /* Flag if finger print buffer */
+    uint8 aFingerPrint[FL_FINGER_PRINT_LENGTH];
+
+    /* Reset handler length */
+    uint32 appStartAddrLen;
+
+    /* APP Start address - reset handler */
+    uint32 appStartAddr;
+
+    /* APP Length - reset handler */
+    uint32 appLength;
+
+    /* Count CRC */
+    uint32 crc;
+}tAppFlashStatus;
+
+typedef struct
+{
+    /* Current process start address */
+    uint32 appVectoTableStartAddr;
+
+    /* Current process length */
+    uint32 appLength;
+
+    /* Received CRC value */
+    uint32 receivedCRC;
+
+} tAppDownloadType;
+
+#endif
+
+MemIf_JobResultType Hal_FlsWrite(Fls_AddressType u32TargetAddress, uint8 * pSourceAddressPtr, Fls_LengthType u32Length, uint32 timeOutMs);
+
+MemIf_JobResultType Hal_FlsRead(Fls_AddressType u32TargetAddress, uint8 * pSourceAddressPtr, Fls_LengthType u32Length, uint32 timeOutMs);
+
+MemIf_JobResultType Hal_FlsErase(Fls_AddressType u32TargetAddress, uint32 eraseInternalSectorNum, uint32 timeOutMs);
+
+void Hal_FlsGetAppVectorTableStartAddr(uint32 *appVectorTableStartAddr);
+
+void Hal_SetAppInfo(uint32 appLength, uint32 appReceviedCRC,ControllerType controllerName);
+
+uint8 Hal_FlsCheckIsTransferSucceed(void);
+
+extern void CRC_HAL_CreatSoftwareCrc(const uint8_t *i_pucDataBuf, const uint32_t i_ulDataLen, uint32_t *m_pCurCrc);
+
+//extern void CreatSoftwareCrc16(const uint8 *i_pDataBuf, const uint32 i_dataLen, uint32 *m_pCurCrc);
+#endif /* HAL_FLS_H_ */

src/Hal_Wdg.c

@@ -100,11 +100,18 @@ uint32 HAL_GetTimerTickCnt(void)
 
 void WATCHDOG_HAL_Feed(void)
 {
-	Wdg_43_Instance0_SetTriggerCondition(5000);
+	Wdg_43_Instance0_SetTriggerCondition(500);
 }
 
+typedef void (*AppAddr)(void);
 void DoResetECU(void)
 {
 	IsFeedWdg = FALSE;
 	Wdg_43_Instance0_SetTriggerCondition(0);
+	while(1)
+	{
+//		AppAddr resetHandle = (AppAddr)(0x00);
+//		    (resetHandle)();
+		;
+	}
 }

src/UDSTask.c

@@ -68,7 +68,7 @@ static const uint16 g_dnpCrcTable[256u] =
 /* Set information CRC */
 #define SetInforCRC(xCrc) ((*(uint16 *)(gs_stBootInfo.infoStartAddr + 14)) = (uint16)(xCrc))
 
-static void CreatSoftwareCrc16(const uint8 *i_pDataBuf, const uint32 i_dataLen, uint32 *m_pCurCrc)
+void CreatSoftwareCrc16(const uint8 *i_pDataBuf, const uint32 i_dataLen, uint32 *m_pCurCrc)
 {
     uint16 crc = 0u;
     uint32 index = 0u;

src/UDSTask.h

@@ -13,6 +13,7 @@
 
 #include "PlatformTypes.h"
 #include "hal_adapter.h"
+#include "USER_CONFIG.h"
 
 #define INFO_START_ADDR                 0x2000EFF0u
 #define REQUEST_ENTER_BOOTLOADER_ADDR   0x2000EFF1u
@@ -21,19 +22,22 @@
 #define EN_CRC_SOFTWARE /* Enable CRC module with software */
 
 
-#define USE_CAN_EXT_ID
-
 /* TODO Bootloader: #01 CAN RX and TX message ID Configuration */
-#if defined (USE_CAN_STD_ID)
-#define RX_FUN_ADDR_ID       (0x7DFu)    /* FuncReq  - CAN TP RX function ID */
-#define RX_PHY_ADDR_ID       (0x74Cu)    /* PhysReq  - CAN TP RX physical ID */
-#define TX_RESP_ADDR_ID      (0x75Cu)    /* PhysResp - CAN TP TX physical ID */
-#elif defined (USE_CAN_EXT_ID)
-#define RX_FUN_ADDR_ID       (0x18DA5536u)    /* FuncReq  - CAN TP RX function ID */
-#define RX_PHY_ADDR_ID       (0x18DA5535u)    /* PhysReq  - CAN TP RX physical ID */
-#define TX_RESP_ADDR_ID      (0x18DA3555u)    /* PhysResp - CAN TP TX physical ID */
+#if defined (CAN1_MSG_TYPE)
+	#if (CAN1_MSG_TYPE == CAN_MSG_STANDARD)
+		#define RX_FUN_ADDR_ID       (0x7BFu)    /* FuncReq  - CAN TP RX function ID */
+		#define RX_PHY_ADDR_ID       (0x7A0u)    /* PhysReq  - CAN TP RX physical ID */
+		#define TX_RESP_ADDR_ID      (0x7A8u)    /* PhysResp - CAN TP TX physical ID */
+	#elif (CAN1_MSG_TYPE == CAN_MSG_EXTENDED)
+		#define RX_FUN_ADDR_ID       (0x18DA55FFu)    /* FuncReq  - CAN TP RX function ID */
+		#define RX_PHY_ADDR_ID       (0x18DA5535u)    /* PhysReq  - CAN TP RX physical ID */
+		#define TX_RESP_ADDR_ID      (0x18DA3555u)    /* PhysResp - CAN TP TX physical ID */
+	#endif
+#else
+	#error "please define the CAN MSG Type of can1"
 #endif
 
+
 void RequestEnterBootloader(void);
 boolean IsJumptoBootloader(uint32 CanID, uint8 Data[]);
 void DoRoutinePositiveAnswer(void);

src/USER_CONFIG.h

@@ -0,0 +1,43 @@
+/*
+ * USER_CONFIG.h
+ *
+ *  Created on: 2022Äę4ÔÂ27ČŐ
+ *      Author: Zhengchao
+ */
+
+#ifndef USER_CONFIG_H_
+#define USER_CONFIG_H_
+
+#endif /* USER_CONFIG_H_ */
+
+
+/*define the CAN information */
+
+#define CAN_BAUDRATE_250K 	(0)
+#define CAN_BAUDRATE_500K 	(1)
+
+#define CAN_MSG_STANDARD 	(0)
+#define CAN_MSG_EXTENDED 	(1)
+
+
+#define CAN0_BAUDRATE CAN_BAUDRATE_250K
+#define CAN0_MSG_TYPE CAN_MSG_STANDARD
+
+//the Default Configuration of CAN1 is Extended 250k for Bootloader, while CAN1 standard 250k only for WuLing project
+#define CAN1_BAUDRATE CAN_BAUDRATE_250K
+#define CAN1_MSG_TYPE CAN_MSG_EXTENDED
+
+#define CAN2_BAUDRATE CAN_BAUDRATE_500K
+#define CAN2_MSG_TYPE CAN_MSG_STANDARD
+
+
+/*define the uart0 information */
+#define UART_BAUDRATE_9600 		(0)
+#define UART_BAUDRATE_19200 	(1)
+#define UART_BAUDRATE_115200 	(2)
+
+#define UART0_BAUDRATE UART_BAUDRATE_9600
+#define UART1_BAUDRATE UART_BAUDRATE_115200
+#define UART2_BAUDRATE UART_BAUDRATE_115200
+
+

src/hal_adapter.c

@@ -6,29 +6,116 @@
  */
 #include "hal_adapter.h"
 #include "AppGlobalVar.h"
- uint8_t __attribute__((section(".non_cacheable_data"))) RX_Buffer[3][BUFFER_SIZE];
- uint32_t bufferIdx[3] = {0};
- volatile uint32 VarNotification_0 = 0;
- volatile uint32 VarNotification_1 = 0;
- TP_Value_Type    ConvertedBuffer[NUM_RESULTS];
- Adc_ValueGroupType    ResultBuffer[NUM_RESULTS];
- Std_ReturnType  ADC_Converter(Adc_ValueGroupType* Buffer, TP_Value_Type* ConvertedValueR);
- Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen,uint32 T_timeout)
+#include "stdio.h"
+#include "stdarg.h"
+uint8_t __attribute__((section(".non_cacheable_data"))) RX_Buffer[3][BUFFER_SIZE];
+uint32_t bufferIdx[3] = {0};
+volatile uint32 VarNotification_0 = 0;
+volatile uint32 VarNotification_1 = 0;
+TP_Value_Type ConvertedBuffer[NUM_RESULTS];
+Adc_ValueGroupType ResultBuffer[NUM_RESULTS];
+ volatile Uart_StatusType Uart_TransmitStatus[3] = {UART_STATUS_TIMEOUT,UART_STATUS_TIMEOUT,UART_STATUS_TIMEOUT};
+ QueueHandle_t UartRecvQueue[3];
+ QueueHandle_t UartSendQueue[3];
+ QueueHandle_t UartHalQueueHandle;
+ void Uart_Hal_RecvTask(void *pvParameters);
+ void Uart_Hal_SendTask(void *pvParameters);
+ Std_ReturnType UartStartRecvFunc(uint8 channel);
+Std_ReturnType ADC_Converter(Adc_ValueGroupType *Buffer, TP_Value_Type *ConvertedValueR);
+static char sprint_buf[1024];
+uint16 myPrintf(const char *fmt, ...)
+{
+    va_list args;
+    int n;
+    va_start(args, fmt);
+    n = vsprintf(sprint_buf, fmt, args);
+    va_end(args);
+    Uart_AsyncSend(UART_LPUART0, sprint_buf, n);
+//    UART_Send_Data(UART_LPUART0, sprint_buf,n, 10);
+    return n;
+}
+
+Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 **rxBuffer, uint16 *rxlen, uint32 T_timeout)
+{
+	UartMsg_t UartRecvMsg;
+	UartMsg_t UartSendMsg;
+	BaseType_t Sendret = pdFALSE;
+	BaseType_t Recvret = pdFALSE;
+	uint32 retVal = E_NOT_OK;
+	UartSendMsg.DataLen = sendLength;
+	UartSendMsg.dataPrt = txBuffer;
+	*rxlen = 0;
+	Sendret = xQueueSend(UartSendQueue[transChannel],&UartSendMsg,50);
+	memset(&UartRecvMsg,0,sizeof(UartMsg_t));
+	if(Sendret == pdTRUE)
+	{
+		Recvret = xQueueReceive(UartRecvQueue[recvChannel],&UartRecvMsg,T_timeout);
+		if(Recvret == pdTRUE)
+		{
+			*rxlen = UartRecvMsg.DataLen;
+			*rxBuffer = UartRecvMsg.dataPrt;
+			retVal = E_OK;
+		}
+		else
+		{
+			retVal = 3;
+		}
+	}
+	else
+	{
+		retVal = 2;
+	}
+	return retVal;
+}
+Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 **rxBuffer, uint16 *rxlen, sint32 T_timeout)
+{
+	UartMsg_t UartRecvMsg;
+	BaseType_t ret = pdFALSE;
+	uint32 retVal = E_NOT_OK;
+	*rxlen = 0;
+	ret = xQueueReceive(UartRecvQueue[recvChannel],&UartRecvMsg,T_timeout);
+	if(ret == pdTRUE)
+	{
+		*rxlen = UartRecvMsg.DataLen;
+		*rxBuffer = UartRecvMsg.dataPrt;
+		retVal = E_OK;
+	}
+	return retVal;
+}
+Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout)
+{
+	UartMsg_t UartSendMsg;
+	BaseType_t ret = pdFALSE;
+	uint32 retVal = E_NOT_OK;
+	UartSendMsg.DataLen = sendLength;
+	UartSendMsg.dataPrt = txBuffer;
+	ret = xQueueSend(UartSendQueue[transChannel],&UartSendMsg,T_timeout);
+	if(ret == pdTRUE)
+	{
+		retVal = E_OK;
+	}
+	return retVal;
+}
+ void UartInit(void)
  {
-     volatile Std_ReturnType R_Uart_Status;
-     volatile Std_ReturnType T_Uart_Status;
-     volatile Uart_StatusType Uart_ReceiveStatus = UART_STATUS_TIMEOUT;
-     volatile Uart_StatusType Uart_TransmitStatus = UART_STATUS_TIMEOUT;
-     uint32 T_bytesRemaining;
-     uint32 R_bytesRemaining;
-     uint32 timeout = T_timeout;
-     uint32 retVal = E_NOT_OK;
-     //    uint8 Rx_Buffer[MSG_LEN];
-
-     /* Uart_AsyncReceive transmit data */
- //    IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(0);
-     bufferIdx[recvChannel]=0;
-	 switch(recvChannel)
+	 UartRecvQueue[0] = xQueueCreate(6, sizeof(UartMsg_t));
+	 UartRecvQueue[1] = xQueueCreate(3, sizeof(UartMsg_t));
+	 UartRecvQueue[2] = xQueueCreate(3, sizeof(UartMsg_t));
+	 UartSendQueue[0] = xQueueCreate(1, sizeof(UartMsg_t));
+	 UartSendQueue[1] = xQueueCreate(1, sizeof(UartMsg_t));
+	 UartSendQueue[2] = xQueueCreate(1, sizeof(UartMsg_t));
+	 UartHalQueueHandle = xQueueCreate(9, sizeof(UartHalMsg_t));
+
+	 xTaskCreate(Uart_Hal_RecvTask, (const char *const)"UartRecv", 1024, (void *)0, main_TASK_PRIORITY + 5, NULL);
+	 xTaskCreate(Uart_Hal_SendTask, (const char *const)"UartSend", 1024, (void *)0, main_TASK_PRIORITY + 4, NULL);
+ }
+ Std_ReturnType UartStartRecvFunc(uint8 channel)
+ {
+	 sint8 out = 0;
+	 volatile Std_ReturnType R_Uart_Status=E_NOT_OK;
+	 bufferIdx[channel]=0;
+	 memset(RX_Buffer[channel],0x00,BUFFER_SIZE);
+	 switch(channel)
 	 {
 		case 0:
 			IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(1);
@@ -42,592 +129,724 @@
 		default:
 			break;
 	 }
-	 if (txBuffer == NULL || rxBuffer == NULL)
-	 {
-		 return retVal;
-	 }
-
-	 /* Uart_AsyncSend transmit data */
-	 Uart_SetBuffer(transChannel, txBuffer, sendLength, UART_SEND);
-	 T_Uart_Status = Uart_AsyncSend(transChannel, txBuffer, sendLength);
-	 if (E_OK != T_Uart_Status)
-	 {
-		 Uart_Abort(transChannel, UART_SEND);
-		 return E_NOT_OK;
-	 }
-	 Uart_SetBuffer(recvChannel, &RX_Buffer[recvChannel][0], DMA_SIZE, UART_RECEIVE);
-	 R_Uart_Status = Uart_AsyncReceive(recvChannel, rxBuffer, DMA_SIZE);
-	 if (E_OK != R_Uart_Status)
-	 {
-		 Uart_Abort(recvChannel, UART_RECEIVE);
-		 return E_NOT_OK;
-	 }
-	 /* Check for no on-going transmission */
-//	 Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2, STD_ON);
-	 do
+	 Uart_SetBuffer(channel, RX_Buffer[channel], DMA_SIZE, UART_RECEIVE);
+	 R_Uart_Status = Uart_AsyncReceive(channel, RX_Buffer[channel], DMA_SIZE);
+	  if (E_OK != R_Uart_Status)
+	  {
+		  Uart_Abort(channel, UART_RECEIVE);
+		  out = E_NOT_OK;
+	  }
+	 return out;
+ }
+ void Uart_Hal_RecvTask(void *pvParameters)
+ {
+	 UartMsg_t UartMsg;
+	 UartHalMsg_t UartHalMsgRecv;
+	 BaseType_t ret = pdFALSE;
+	 uint32 T_bytesRemaining[3] = {0};
+	 uint16 T_timeout[3] = {0};
+	 volatile Uart_StatusType Uart_ReceiveStatus[3] = {UART_STATUS_TIMEOUT,UART_STATUS_TIMEOUT,UART_STATUS_TIMEOUT};
+	 uint8 UartIdx = UART_LPUART0;
+	 uint8 UartState[3] = {UartAbortRecv,UartAbortRecv,UartAbortRecv};
+	 while(1)
 	 {
-//		 Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2, STD_ON);
-		 if(Uart_TransmitStatus != UART_STATUS_NO_ERROR)
+		 if((T_timeout[UartIdx]>1000) && (Uart_ReceiveStatus[UartIdx] != UART_STATUS_NO_ERROR) )//判定UART停止，超时停止，不是接收状态则停止
 		 {
-			 Uart_TransmitStatus = Uart_GetStatus(transChannel, &T_bytesRemaining, UART_SEND);
+			  Uart_Abort(UartIdx, UART_RECEIVE);
+			  UartState[UartIdx] = UartAbortRecv;
+			  T_timeout[UartIdx] = 0;
 		 }
-		 if(Uart_ReceiveStatus != UART_STATUS_NO_ERROR)
+		 else if(Uart_ReceiveStatus[UartIdx] == UART_STATUS_NO_ERROR)
 		 {
-			 Uart_ReceiveStatus = Uart_GetStatus(recvChannel, &R_bytesRemaining, UART_RECEIVE);
+			 UartState[UartIdx] = UartRecvComplete;
 		 }
 
-		 vTaskDelay(pdMS_TO_TICKS(1));
-//		 Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2, STD_OFF);
-
-	 } while (((UART_STATUS_NO_ERROR != Uart_TransmitStatus || UART_STATUS_NO_ERROR != Uart_ReceiveStatus) && 0 < --timeout));
-//	 Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2, STD_OFF);
-	 if ((UART_STATUS_NO_ERROR != Uart_TransmitStatus))
-	 {
-		 Uart_Abort(transChannel, UART_SEND);
-		 retVal = E_NOT_OK;
-	 }
-	 else
-	 {
-		 retVal = E_OK;
-	 }
-	 if ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus))
-	 {
-		 Uart_Abort(recvChannel, UART_RECEIVE);
-		 *rxlen = bufferIdx[recvChannel];
-		 //IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(1);
-		 retVal = E_NOT_OK;
-	 }
-	 else
-	 {
-		 *rxlen = bufferIdx[recvChannel];
-		 retVal = E_OK;
-	 }
-	 return retVal;
- }
-
- Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout)
- {
-
-     volatile Std_ReturnType T_Uart_Status;
-     volatile Uart_StatusType Uart_TransmitStatus = UART_STATUS_TIMEOUT;
-     uint32 T_bytesRemaining;
-     uint32 timeout = T_timeout;
-     uint32 retVal = E_NOT_OK;
-     //    uint8 Rx_Buffer[MSG_LEN];
-
-     if (txBuffer == NULL)
-     {
-         return retVal;
-     }
-
-     /* Uart_AsyncSend transmit data */
-//     Uart_SetBuffer(transChannel, txBuffer, sendLength, UART_SEND);
-     T_Uart_Status = Uart_AsyncSend(transChannel, txBuffer, sendLength);
-     if (E_OK != T_Uart_Status)
-     {
-         Uart_Abort(transChannel, UART_SEND);
-         return E_NOT_OK;
-     }
-
-     /* Check for no on-going transmission */
-     do
-     {
-         Uart_TransmitStatus = Uart_GetStatus(transChannel, &T_bytesRemaining, UART_SEND);
-         vTaskDelay(pdMS_TO_TICKS(1));
-     } while ((UART_STATUS_NO_ERROR != Uart_TransmitStatus && 0 < --timeout));
-
-     if ((UART_STATUS_NO_ERROR != Uart_TransmitStatus))
-     {
-         //Uart_Abort(transChannel, UART_SEND);
-         retVal = E_NOT_OK;
-     }
-     else
-     {
-         retVal = E_OK;
-     }
-     return retVal;
- }
-
- Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer, uint16 *rxlen,sint32 T_timeout)
- {
-     volatile Std_ReturnType R_Uart_Status=E_NOT_OK;
-     volatile Uart_StatusType Uart_ReceiveStatus = UART_STATUS_TIMEOUT;
-     uint32 T_bytesRemaining = 0;
-     uint32 retVal = E_NOT_OK;
-     //    uint8 Rx_Buffer[MSG_LEN];
-     bufferIdx[recvChannel]=0;
-     *rxlen = 0;
-     if (rxBuffer == NULL)
-     {
-         return retVal;
-     }
-     /* Uart_AsyncReceive transmit data */
-	switch(recvChannel)
-	{
-		case 0:
-			IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(1);
-			break;
-		case 1:
-			IP_LPUART1->CTRL |= LPUART_CTRL_ILIE(1);
-			break;
-		case 2:
-			IP_LPUART2->CTRL |= LPUART_CTRL_ILIE(1);
-			break;
-		default:
-			break;
-	}
-     Uart_SetBuffer(recvChannel, rxBuffer, DMA_SIZE, UART_RECEIVE);
-     R_Uart_Status = Uart_AsyncReceive(recvChannel, rxBuffer, DMA_SIZE);
-     if (E_OK != R_Uart_Status)
-     {
-         Uart_Abort(recvChannel, UART_RECEIVE);
-         return E_NOT_OK;
-     }
-     /* Check for no on-going transmission */
-     do
-     {
-         Uart_ReceiveStatus = Uart_GetStatus(recvChannel, &T_bytesRemaining, UART_RECEIVE);
-         vTaskDelay(pdMS_TO_TICKS(1));
-
-     } while ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus)&& 0<T_timeout--);
-     if ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus))
-     {
-         Uart_Abort(recvChannel, UART_RECEIVE);
-         *rxlen = bufferIdx[recvChannel];
-         retVal = E_NOT_OK;
-     }
-     else
-     {
-    	 *rxlen = bufferIdx[recvChannel];
-         retVal = E_OK;
-     }
-     return retVal;
- }
- extern Lpuart_Uart_Ip_StateStructureType * Lpuart_Uart_Ip_apStateStructuresArray[LPUART_UART_IP_NUMBER_OF_INSTANCES];
- void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event )
- {
- //    (void)userData;
-     uint32_t temp;
-     /* Check the event type */
-     if (event == LPUART_UART_IP_EVENT_RX_FULL)
-     {
-         /* The reception stops when receiving idle is detected or the buffer is full */
-		 if (bufferIdx[hwInstance] <= (BUFFER_SIZE - DMA_SIZE))
+		 if((UartState[UartIdx] == UartAbortRecv) || (UartState[UartIdx] == UartRecvComplete)) //判定UART开始接收：UART停止后开始接收
 		 {
-			 /* Update the buffer index and the rx buffer */
-			 bufferIdx[hwInstance] += DMA_SIZE;
-			Uart_SetBuffer(hwInstance,&RX_Buffer[hwInstance][bufferIdx[hwInstance]],DMA_SIZE,UART_RECEIVE);
-			 //Lpuart_Uart_Ip_SetRxBuffer(hwInstance, &RX_Buffer[bufferIdx], DMA_SIZE);
+			 if(E_OK == UartStartRecvFunc(UartIdx))
+			 {
+				 UartState[UartIdx] = UartStartRecv;
+			 }
 		 }
-     }
-     if (event == LPUART_UART_IP_EVENT_ERROR)
-     {
-//     	/*Get the transfered data size. DMA Channel 1 is used for LPUART DMA receiving, please modify accordingly.*/
-//     	temp = DMA_SIZE - (uint32_t)IP_DMA->TCD->CITER.ELINKNO;
-//     	/*Add the remaining data size to the sum of the received size*/
-//     	bufferIdx[hwInstance] += temp;
-         /*Abort the receiving after detecting IDLE receiving*/
-     	Lpuart_Uart_Ip_AbortReceivingData(hwInstance);
-     	Lpuart_Uart_Ip_AbortSendingData(hwInstance);
- //    	bufferIdx = 0;
-     }
-     if( event == LPUART_UART_IP_EVENT_RECV_IDLE)
-     {
-     	/*Get the transfered data size. DMA Channel 1 is used for LPUART DMA receiving, please modify accordingly.*/
- 		temp = DMA_SIZE - (uint32_t)IP_DMA->TCD[hwInstance].CITER.ELINKNO;
- 		/*Add the remaining data size to the sum of the received size*/
- 		bufferIdx[hwInstance] += temp;
- 		/*Abort the receiving after detecting IDLE receiving*/
-
- 		Lpuart_Uart_Ip_StateStructureType * UartState;
- 		UartState = (Lpuart_Uart_Ip_StateStructureType *)Lpuart_Uart_Ip_apStateStructuresArray[hwInstance];
- 		UartState->IsRxBusy = FALSE;
- 		UartState->ReceiveStatus = LPUART_UART_IP_STATUS_SUCCESS;
- 		Lpuart_Uart_Ip_CompleteReceiveUsingDma(hwInstance);
- //		rxSuccess = true;
-     }
- }
-
- /*CAN*/
- Can_PduType Can_CreatePduInfo(Can_IdType id, CAN_IdFrameType idFrame, PduIdType swPduHandle, uint8 length, uint8 *sdu)
- {
-     Can_PduType PduInfo;
-     switch (idFrame)
-     {
-     case CAN_STANDARD_ID_TYPE:
-         id = id & 0x7FF;
-         break;
-     case CANFD_STANDARD_ID_TYPE:
-         id = (id & 0x7FF) | 0x40000000;
-         break;
-     case CAN_EXTENDED_ID_TYPE:
-         id = id | 0x80000000;
-         break;
-     case CANFD_EXTENDED_ID_TYPE:
-         id = id | 0xC0000000;
-         break;
-     default:
-         id = id & 0x7FF;
-         break;
-     }
-     PduInfo.id = id;
-     PduInfo.swPduHandle = swPduHandle;
-     PduInfo.length = length;
-     PduInfo.sdu = sdu;
-
-     return PduInfo;
- }
- Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg)
- {
-     volatile Can_PduType Can_PduInfo;
-     volatile Std_ReturnType CAN_Write_Status;
-     Std_ReturnType retVal = E_NOT_OK;
-     uint32 u8TimeOut = 100*100;
-     Can_HwHandleType Hth = Can0HardwareObject_TX + (Can_HwHandleType)ControllerId; // controller 0 --> Can0HardwareObject_TX
-
-     Can_PduInfo = Can_CreatePduInfo(CanMsg.id, CanMsg.idFrame, 0, CanMsg.length, CanMsg.sdu);
-
-     CAN_Write_Status = Can_Write(Hth, &Can_PduInfo);
-
-     CanIf_bTxFlag = FALSE;
-     if (CAN_Write_Status == E_OK)
-     {
-         while ((!CanIf_bTxFlag) && (u8TimeOut != 0U))
-         {
-             Can_MainFunction_Write();
-             u8TimeOut--;
-         }
-     }
-
-     if (CanIf_bTxFlag == TRUE)
-     {
-         retVal = E_OK;
-     }
-     else
-     {
-         retVal = E_NOT_OK;
-     }
-     return retVal;
- }
- Can_Msg_Type Can_GetMsgInfo(Can_IdType id, uint8 length, uint8 *sdu)
- {
-     Can_Msg_Type CanMsgInfo;
-
-     CanMsgInfo.idFrame = (CAN_IdFrameType)((id >> 30) & 0x03);
-     if (CanMsgInfo.idFrame & 0x01)
-     {
-         CanMsgInfo.id = id & 0x7FF;
-     }
-     else
-     {
-         CanMsgInfo.id = id & 0x1FFFFFFF;
-     }
-     CanMsgInfo.length = length;
-     CanMsgInfo.sdu = sdu;
-
-     return CanMsgInfo;
- }
-
- void CanIf_ControllerBusOff(uint8 ControllerId)
- {
-     (void)ControllerId;
- }
-
- void CanIf_ControllerModeIndication(uint8 ControllerId, Can_ControllerStateType ControllerMode)
- {
-     (void)ControllerId;
-     (void)ControllerMode;
- }
- void CanIf_TxConfirmation(PduIdType CanTxPduId)
- {
-     CanIf_u8TxConfirmCnt++;
-     CanIf_bTxFlag = TRUE;
-     (void)CanTxPduId;
- }
- void CanIf_RxIndication(const Can_HwType *Mailbox, const PduInfoType *PduInfoPtr)
- {
-	 Can_Msg_Type canRxMsg_Buff;
-	 Can_Msg_Type_Data canRxMsgQueueData;
-     CanIf_bRxFlag = TRUE; // should not be delete
-     // should put the msg into message queue
-     canRxMsg_Buff = Can_GetMsgInfo(Mailbox->CanId, PduInfoPtr->SduLength, PduInfoPtr->SduDataPtr);
-     canRxMsgQueueData.id = canRxMsg_Buff.id;
-     canRxMsgQueueData.length = canRxMsg_Buff.length;
-     memcpy(canRxMsgQueueData.data,canRxMsg_Buff.sdu,canRxMsgQueueData.length);
-     xQueueSend(CanRecvQueueHandle,&canRxMsgQueueData,0);
- }
-
- void CanIf_CurrentIcomConfiguration(uint8 ControllerId, IcomConfigIdType ConfigurationId, IcomSwitch_ErrorType Error)
- {
-     (void)ControllerId;
-     (void)ConfigurationId;
-     (void)Error;
- }
-
-
- void Notification_0(void)
- {
-	 ADC_Converter(ResultBuffer,ConvertedBuffer);
-	 memcpy(BattTempR,&ConvertedBuffer[3],4*sizeof(uint32));
-//     VarNotification_0++;
- }
-
- void Notification_1(void)
- {
-     VarNotification_1++;
- }
-
-
-
- Std_ReturnType  ADC_Converter(Adc_ValueGroupType* Buffer, TP_Value_Type* ConvertedValueR)
- {
-	 Adc_ValueGroupType REFH,REFL;
-	 REFH = Buffer[0];
-	 REFL = Buffer[2];
-	 for(int i = 3; i < NUM_RESULTS; i++)
-	 {
-//		 ConvertedValueR[i] = (TP_Value_Type)((float)(10000 * Buffer[i]/(float)(REFH - REFL))/(1-(float)(Buffer[i]/(float)(REFH - REFL))));
-		if(Buffer[i] >= REFH)
-		{
-		 ConvertedValueR[i] = 40930000;
-		}
-		else if(Buffer[i] <=REFL)
-		{
-			ConvertedValueR[i] = 0x00;
-		}
-		else
-		{
-		 ConvertedValueR[i] = (TP_Value_Type)((float)(10000 * (Buffer[i] - REFL)/(float)(REFH - REFL))/(1-(float)((Buffer[i]- REFL)/(float)(REFH - REFL))));
-		}
+		 Uart_ReceiveStatus[UartIdx] = Uart_GetStatus(UartIdx, &T_bytesRemaining[UartIdx], UART_RECEIVE);
+		 T_timeout[UartIdx]++;
+		 UartIdx = (UartIdx + 1) > 2 ? 0 : (UartIdx + 1);
+		 ret = xQueueReceive(UartHalQueueHandle,&UartHalMsgRecv,1);
+		  if(ret==pdTRUE)
+		  {
+			  if(UartHalMsgRecv.event==LPUART_UART_IP_EVENT_RECV_IDLE)
+			  {
+					UartMsg.DataLen = UartHalMsgRecv.value;
+					UartMsg.dataPrt = malloc(UartMsg.DataLen);
+					memset(UartMsg.dataPrt,0,UartMsg.DataLen);
+					memcpy(UartMsg.dataPrt,RX_Buffer[UartHalMsgRecv.Channel],UartMsg.DataLen);
+					if(UartMsg.DataLen>0)
+					{
+						xQueueSend(UartRecvQueue[UartHalMsgRecv.Channel],&UartMsg,10);
+					}
+					T_timeout[UartHalMsgRecv.Channel] = 0;
+					UartState[UartHalMsgRecv.Channel] = UartRecvComplete;
+			  }
+		  }
 	 }
  }
-
- Std_ReturnType  ADC_ReadValue()
+ void Uart_Hal_SendTask(void *pvParameters)
  {
-	 Std_ReturnType ret = E_NOT_OK;
-	 Adc_ValueGroupType    AdcReadGroupBuffer[NUM_RESULTS];
-	 volatile Std_ReturnType Status = TRUE;
-	 for(int i = 0; i<NUM_RESULTS; i++)
+	 UartMsg_t UartSendMsg;
+	 BaseType_t ret = pdFALSE;
+	 uint32 T_bytesRemaining[3] = {0};
+	 uint16 T_timeout[3] = {0};
+	 volatile Std_ReturnType T_Uart_Status[3];
+	 uint8 UartIdx = UART_LPUART0;
+	 uint8 UartSendState[3] = {UartNoDataSend,UartNoDataSend,UartNoDataSend};
+	 while(1)
 	 {
-		 ResultBuffer[i] = 0xFFFF;
-		 AdcReadGroupBuffer[i] = 0xFFFE;
-		 ConvertedBuffer[i] = 0x00;
-	 }
-	 Adc_SetupResultBuffer(AdcGroupSoftwareOneShot, ResultBuffer);
-	 Adc_EnableGroupNotification(AdcGroupSoftwareOneShot);
-	 VarNotification_0 = 0;
-	 Adc_StartGroupConversion(AdcGroupSoftwareOneShot);
-//	 uint32 TimeOut = 0;
-//	 while(VarNotification_0 == 0 && VarNotification_1==0 && TimeOut<0xFFFF)
-//	 {
-//		 TimeOut++;
-//	 }
-//	 AdcStates = Adc_ReadGroup(AdcGroupSoftwareOneShot, AdcReadGroupBuffer);
-//	 if(AdcStates == E_NOT_OK)
-//	 {
-//		 return AdcStates;
-//	 }
-//	 else
-//	 {
-//		 ret = E_OK;
-//	 }
-	 return ret;
- }
-
- /*EEP*/
- static Std_ReturnType TestEep_FlexNvmProgramPartCmd
- (
-     VAR(TestEep_CsecKeySize, AUTOMATIC) eepKeysize,
-     VAR(TestEep_SfeType, AUTOMATIC) eepSecurityFlagExtension,
-     VAR(TestEep_LoadFlexRamType, AUTOMATIC) eepLoadFlexRamAtReset,
-     VAR(TestEep_Eeprom_FlexRamPartitionType, AUTOMATIC) eepFlexRamPartition,
-     VAR(TestEep_Eeprom_FlexNvmPartitionType, AUTOMATIC) eepFlexNvmPartition
- )
- {
-      Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
-      uint32 u32Addr=0;
-      uint32 u32FlexNvmPartSize = 0;
-
-     uint32 u32RegSimFcfg1      = 0UL;
-
-     u32RegSimFcfg1 = IP_SIM->FCFG1;
-
-     /*get DEPART value */
-     u32FlexNvmPartSize = (uint32)( (u32RegSimFcfg1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT );
-
-     /* check that it was not partitioned before */
-     if (u32FlexNvmPartSize == 0xF)
-     {
-         /* if error flags are set the cmd is not executed */
-         REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8);
-
-         /*erase DF 0 sector*/
-         u32Addr=(TEST_EEP_DEEPROM_SECTOR_0_ADDR32 - D_EEPROM_BASE_ADDR) + 0x800000UL;
-
-         REG_WRITE8(TEST_EEP_EEPROM_FCCOB0_ADDR32, TEST_EEP_EEPROM_CMD_ERASE_SECTOR);
-         REG_WRITE8(TEST_EEP_EEPROM_FCCOB1_ADDR32, (uint8)(u32Addr >> 16UL));
-         REG_WRITE8(TEST_EEP_EEPROM_FCCOB2_ADDR32, (uint8)(u32Addr >> 8UL));
-         REG_WRITE8(TEST_EEP_EEPROM_FCCOB3_ADDR32, (uint8)(u32Addr >> 0UL));
-         REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32 , TEST_EEP_EEPROM_FSTAT_CCIF_U8);
-         while((0U == REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_CCIF_U8)))
-         {
-         }
-
-         if(0U==REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32,TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8))
-         {
-             /* run program partition command */
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB0_ADDR32,EEPROM_CMD_PROGRAM_PARTITION);
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB1_ADDR32, (uint8)eepKeysize);
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB2_ADDR32, (uint8)eepSecurityFlagExtension);
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB3_ADDR32, (uint8)eepLoadFlexRamAtReset);
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB4_ADDR32, (uint8)eepFlexRamPartition);
-             REG_WRITE8(TEST_EEP_EEPROM_FCCOB5_ADDR32, (uint8)eepFlexNvmPartition);
-             REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32 , TEST_EEP_EEPROM_FSTAT_CCIF_U8);
-             while((0U == REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_CCIF_U8)))
-             {
-             /* wait for operation to finish */
-             }
-             /* check if errors occured  */
-             if(REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32,TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8))
-             {
-                 /* NOK, error flags are set */
-                 u8RetVal = (Std_ReturnType)E_NOT_OK;
-             }
-         }
-         else
-         {
-             /* NOK, error flags are set */
-             u8RetVal = (Std_ReturnType)E_NOT_OK;
-         }
-     }
-     else
-     {
-         /* NOK, partitioned already */
-         u8RetVal = (Std_ReturnType)E_NOT_OK;
-     }
-     return u8RetVal;
- }
-
- void Eep_DepartParitition(TestEep_Eeprom_FlexNvmPartitionType T_EEP_SIZE)
- {
-     uint32 u32FlexNvmPartSize = 0;
-
-     uint32 u32RegSimFcfg1      = 0UL;
-
-     u32RegSimFcfg1 = IP_SIM->FCFG1;
-
-     /*get DEPART value */
-     u32FlexNvmPartSize = (uint32)( (u32RegSimFcfg1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT );
-     if (u32FlexNvmPartSize == 0xF) /* We just partition again if curent size different with expected */
-     {
-
-         /* partition for EERAM 64K with NOT loading EERAM at reset in hardware */
-         TestEep_FlexNvmProgramPartCmd(EEP_FTFC_KEY_SIZE_0_BYTES, EEP_FTFC_VERIFY_ONLY_DISABLED, \
-                                                EEP_FTFC_LOAD_AT_RESET_ENABLED, EEP_FTFC_EERAM_SIZE_4K, T_EEP_SIZE);
-     }
-
- }
-
-
- /* Erase memory by writing erase value */
- Std_ReturnType HAL_EEP_Erase(uint32 eepEraseStartAddr,uint32 eepEraseSize)
- {
-	 Std_ReturnType retReturnType = E_OK;
-	 MemIf_JobResultType retJobResultType;
-     retReturnType = Eep_Erase(eepEraseStartAddr, eepEraseSize);
-     if(E_OK != retReturnType)
-     {
-         return E_NOT_OK;
-     }
-     while(MEMIF_IDLE != Eep_GetStatus())
-     {
-         Eep_MainFunction();
-     }
-     retJobResultType = Eep_GetJobResult();
-     if(MEMIF_JOB_OK != retJobResultType)
-     {
-         return E_NOT_OK;
-     }
-     return E_OK;
- }
-
-  /* Write one or more complete eeprom pages to the eeprom device */
-  Std_ReturnType HAL_EEP_Write(uint32 eepWriteStartAddr,uint8* pDataNeedtoWrite,uint32 dataSize)
-  {
-	  Std_ReturnType retReturnType = E_OK;
-	  MemIf_JobResultType retJobResultType;
-
-	  /*Erase the EEP before write*/
-	  retReturnType = HAL_EEP_Erase(eepWriteStartAddr,dataSize);
-	  if(E_OK != retReturnType)
-	  {
-		  return E_NOT_OK;
-	  }
+		 ret = xQueueReceive(UartSendQueue[UartIdx],&UartSendMsg,1);
+		 if(ret==pdTRUE)
+		 {
+			 if(UartIdx==UART_LPUART0)
+			 {
+				 Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_ON);
+			 }
+			 T_Uart_Status[UartIdx] = Uart_AsyncSend(UartIdx, UartSendMsg.dataPrt, UartSendMsg.DataLen);
+		     if (E_OK != T_Uart_Status[UartIdx])
+		     {
+		         Uart_Abort(UartIdx, UART_SEND);
+		         UartSendState[UartIdx] = UartAbortSend;
+		     }
+		     else
+		     {
+		    	 UartSendState[UartIdx] = UartStartSend;
+		     }
+		 }
+		 /*开始发送后的判定*/
+		 if(UartSendState[UartIdx] == UartStartSend)
+		 {
+			 Uart_TransmitStatus[UartIdx] = Uart_GetStatus(UartIdx, &T_bytesRemaining[UartIdx], UART_SEND);
+			 T_timeout[UartIdx]++;
+		 }
+		 if(T_timeout[UartIdx]>=1000 || ((Uart_TransmitStatus[UartIdx] != UART_STATUS_OPERATION_ONGOING) && (UartSendState[UartIdx] == UartStartSend)))
+		 {
+			 if(T_timeout[UartIdx]>=1000)
+			 {
+				 Uart_Abort(UartIdx, UART_SEND);
+				 UartSendState[UartIdx] = UartAbortSend;
+			 }
+			 else if(Uart_TransmitStatus[UartIdx] == UART_STATUS_NO_ERROR)
+			 {
+				 UartSendState[UartIdx] = UartSendComplete;
+			 }
+			 T_timeout[UartIdx] = 0;
+		 }
 
-      retReturnType = Eep_Write(eepWriteStartAddr, pDataNeedtoWrite, dataSize);
-      if(E_OK != retReturnType)
-      {
-          return E_NOT_OK;
-      }
-      while(MEMIF_IDLE != Eep_GetStatus())
-      {
-          Eep_MainFunction();
-      }
-      retJobResultType = Eep_GetJobResult();
-      if(MEMIF_JOB_OK != retJobResultType)
-      {
-          return E_NOT_OK;
-      }
-      return E_OK;
-  }
-
-
- /* Reads from eeprom memory */
- Std_ReturnType HAL_EEP_Read(uint32 eepReadStartAddr,uint8* pDataBuffer,uint32 dataSize)
- {
-	 Std_ReturnType retReturnType = E_OK;
-	 MemIf_JobResultType retJobResultType;
-     retReturnType = Eep_Read(eepReadStartAddr, pDataBuffer, dataSize);
-     if(E_OK != retReturnType)
-     {
-         return E_NOT_OK;
-     }
-     while(MEMIF_IDLE != Eep_GetStatus())
-     {
-         Eep_MainFunction();
-     }
-     retJobResultType = Eep_GetJobResult();
-     if(MEMIF_JOB_OK != retJobResultType)
-     {
-         return E_NOT_OK;
-     }
-     return E_OK;
- }
+		 UartIdx = (UartIdx + 1) > 2 ? 0 : (UartIdx + 1);
+	 }
 
- /* Compares a eeprom memory area with an application data buffer */
- Std_ReturnType HAL_EEP_Compare(uint32 eepCompareStartAddr,uint8* pDataNeedtoCompare,uint32 dataSize)
- {
-	 Std_ReturnType retReturnType = E_OK;
-	 MemIf_JobResultType retJobResultType;
-	 retReturnType = Eep_Compare(eepCompareStartAddr, pDataNeedtoCompare, dataSize);
-     if(E_OK != retReturnType)
-     {
-         return E_NOT_OK;
-     }
-     while(MEMIF_IDLE != Eep_GetStatus())
-     {
-         Eep_MainFunction();
-     }
-     retJobResultType = Eep_GetJobResult();
-     if(MEMIF_JOB_OK != retJobResultType)
-     {
-         return E_NOT_OK;
-     }
-     return E_OK;
  }
-
-
-
-
-
-
+//
+//Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen, uint32 T_timeout)
+//{
+//    volatile Std_ReturnType R_Uart_Status;
+//    volatile Std_ReturnType T_Uart_Status;
+//    volatile Uart_StatusType Uart_ReceiveStatus = UART_STATUS_TIMEOUT;
+//    volatile Uart_StatusType Uart_TransmitStatus = UART_STATUS_TIMEOUT;
+//    uint32 T_bytesRemaining;
+//    uint32 R_bytesRemaining;
+//    uint32 timeout = T_timeout;
+//    uint32 retVal = E_NOT_OK;
+//    bufferIdx[recvChannel] = 0;
+//    switch (recvChannel)
+//    {
+//    case 0:
+//        IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    case 1:
+//        IP_LPUART1->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    case 2:
+//        IP_LPUART2->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    default:
+//        break;
+//    }
+//    if (txBuffer == NULL || rxBuffer == NULL)
+//    {
+//        return retVal;
+//    }
+//
+//    /* Uart_AsyncSend transmit data */
+//    Uart_SetBuffer(transChannel, txBuffer, sendLength, UART_SEND);
+//    T_Uart_Status = Uart_AsyncSend(transChannel, txBuffer, sendLength);
+//    if (E_OK != T_Uart_Status)
+//    {
+//        Uart_Abort(transChannel, UART_SEND);
+//        return E_NOT_OK;
+//    }
+//    Uart_SetBuffer(recvChannel, &RX_Buffer[recvChannel][0], DMA_SIZE, UART_RECEIVE);
+//    R_Uart_Status = Uart_AsyncReceive(recvChannel, rxBuffer, DMA_SIZE);
+//    if (E_OK != R_Uart_Status)
+//    {
+//        Uart_Abort(recvChannel, UART_RECEIVE);
+//        return E_NOT_OK;
+//    }
+//    /* Check for no on-going transmission */
+//    do
+//    {
+//        if (Uart_TransmitStatus != UART_STATUS_NO_ERROR)
+//        {
+//            Uart_TransmitStatus = Uart_GetStatus(transChannel, &T_bytesRemaining, UART_SEND);
+//        }
+//        if (Uart_ReceiveStatus != UART_STATUS_NO_ERROR)
+//        {
+//            Uart_ReceiveStatus = Uart_GetStatus(recvChannel, &R_bytesRemaining, UART_RECEIVE);
+//        }
+//        vTaskDelay(pdMS_TO_TICKS(1));
+//    } while (((UART_STATUS_NO_ERROR != Uart_TransmitStatus || UART_STATUS_NO_ERROR != Uart_ReceiveStatus) && 0 < --timeout));
+//    if ((UART_STATUS_NO_ERROR != Uart_TransmitStatus))
+//    {
+//        Uart_Abort(transChannel, UART_SEND);
+//        retVal = E_NOT_OK;
+//    }
+//    else
+//    {
+//        retVal = E_OK;
+//    }
+//    if ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus))
+//    {
+//        Uart_Abort(recvChannel, UART_RECEIVE);
+//        *rxlen = bufferIdx[recvChannel];
+//        retVal = E_NOT_OK;
+//    }
+//    else
+//    {
+//        *rxlen = bufferIdx[recvChannel];
+//        retVal = E_OK;
+//    }
+//    return retVal;
+//}
+//
+//Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout)
+//{
+//
+//    volatile Std_ReturnType T_Uart_Status;
+//    volatile Uart_StatusType Uart_TransmitStatus = UART_STATUS_TIMEOUT;
+//    uint32 T_bytesRemaining;
+//    uint32 timeout = T_timeout;
+//    uint32 retVal = E_NOT_OK;
+//    if (txBuffer == NULL)
+//    {
+//        return retVal;
+//    }
+//
+//    /* Uart_AsyncSend transmit data */
+//    T_Uart_Status = Uart_AsyncSend(transChannel, txBuffer, sendLength);
+//    if (E_OK != T_Uart_Status)
+//    {
+//        Uart_Abort(transChannel, UART_SEND);
+//        return E_NOT_OK;
+//    }
+//    /* Check for no on-going transmission */
+//    do
+//    {
+//        Uart_TransmitStatus = Uart_GetStatus(transChannel, &T_bytesRemaining, UART_SEND);
+//        vTaskDelay(pdMS_TO_TICKS(1));
+//    } while ((UART_STATUS_NO_ERROR != Uart_TransmitStatus && 0 < --timeout));
+//
+//    if ((UART_STATUS_NO_ERROR != Uart_TransmitStatus))
+//    {
+//        retVal = E_NOT_OK;
+//    }
+//    else
+//    {
+//        retVal = E_OK;
+//    }
+//    return retVal;
+//}
+//
+//Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer, uint16 *rxlen, sint32 T_timeout)
+//{
+//    volatile Std_ReturnType R_Uart_Status = E_NOT_OK;
+//    volatile Uart_StatusType Uart_ReceiveStatus = UART_STATUS_TIMEOUT;
+//    uint32 T_bytesRemaining = 0;
+//    uint32 retVal = E_NOT_OK;
+//    //    uint8 Rx_Buffer[MSG_LEN];
+//    bufferIdx[recvChannel] = 0;
+//    *rxlen = 0;
+//    if (rxBuffer == NULL)
+//    {
+//        return retVal;
+//    }
+//    /* Uart_AsyncReceive transmit data */
+//    switch (recvChannel)
+//    {
+//    case 0:
+//        IP_LPUART0->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    case 1:
+//        IP_LPUART1->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    case 2:
+//        IP_LPUART2->CTRL |= LPUART_CTRL_ILIE(1);
+//        break;
+//    default:
+//        break;
+//    }
+//    Uart_SetBuffer(recvChannel, rxBuffer, DMA_SIZE, UART_RECEIVE);
+//    R_Uart_Status = Uart_AsyncReceive(recvChannel, rxBuffer, DMA_SIZE);
+//    if (E_OK != R_Uart_Status)
+//    {
+//        Uart_Abort(recvChannel, UART_RECEIVE);
+//        return E_NOT_OK;
+//    }
+//    /* Check for no on-going transmission */
+//    do
+//    {
+//        Uart_ReceiveStatus = Uart_GetStatus(recvChannel, &T_bytesRemaining, UART_RECEIVE);
+//        vTaskDelay(pdMS_TO_TICKS(1));
+//
+//    } while ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus) && 0 < T_timeout--);
+//    if ((UART_STATUS_NO_ERROR != Uart_ReceiveStatus))
+//    {
+//        Uart_Abort(recvChannel, UART_RECEIVE);
+//        *rxlen = bufferIdx[recvChannel];
+//        retVal = E_NOT_OK;
+//    }
+//    else
+//    {
+//        *rxlen = bufferIdx[recvChannel];
+//        retVal = E_OK;
+//    }
+//    return retVal;
+//}
+extern Lpuart_Uart_Ip_StateStructureType *Lpuart_Uart_Ip_apStateStructuresArray[LPUART_UART_IP_NUMBER_OF_INSTANCES];
+void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event)
+{
+    //    (void)userData;
+		Lpuart_Uart_Ip_StateStructureType * UartState;
+		UartState = (Lpuart_Uart_Ip_StateStructureType *)Lpuart_Uart_Ip_apStateStructuresArray[hwInstance];
+	if (hwInstance==0&&event == LPUART_UART_IP_EVENT_END_TRANSFER)
+	{
+		Dio_WriteChannel(DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN, STD_OFF);
+	}
+    /* Check the event type */
+    if (event == LPUART_UART_IP_EVENT_RX_FULL)
+    {
+        /* The reception stops when receiving idle is detected or the buffer is full */
+        if (bufferIdx[hwInstance] <= (BUFFER_SIZE - DMA_SIZE))
+        {
+            /* Update the buffer index and the rx buffer */
+            bufferIdx[hwInstance] += DMA_SIZE;
+            Uart_SetBuffer(hwInstance, &RX_Buffer[hwInstance][bufferIdx[hwInstance]], DMA_SIZE, UART_RECEIVE);
+            // Lpuart_Uart_Ip_SetRxBuffer(hwInstance, &RX_Buffer[bufferIdx], DMA_SIZE);
+        }
+    }
+    if (event == LPUART_UART_IP_EVENT_ERROR)
+    {
+        //     	/*Get the transfered data size. DMA Channel 1 is used for LPUART DMA receiving, please modify accordingly.*/
+        //     	temp = DMA_SIZE - (uint32_t)IP_DMA->TCD->CITER.ELINKNO;
+        //     	/*Add the remaining data size to the sum of the received size*/
+        //     	bufferIdx[hwInstance] += temp;
+        /*Abort the receiving after detecting IDLE receiving*/
+        Lpuart_Uart_Ip_AbortReceivingData(hwInstance);
+        Lpuart_Uart_Ip_AbortSendingData(hwInstance);
+        //    	bufferIdx = 0;
+    }
+    if (event == LPUART_UART_IP_EVENT_RECV_IDLE)
+    {
+         uint32_t temp;
+         UartHalMsg_t UartHalMsg;
+         UartHalMsg.Channel = hwInstance;
+         UartHalMsg.event = event;
+        /*Get the transfered data size. DMA Channel 1 is used for LPUART DMA receiving, please modify accordingly.*/
+        temp = DMA_SIZE - (uint32_t)IP_DMA->TCD[hwInstance].CITER.ELINKNO;
+        /*Add the remaining data size to the sum of the received size*/
+        bufferIdx[hwInstance] += temp;
+        /*Abort the receiving after detecting IDLE receiving*/
+ 		UartHalMsg.value = bufferIdx[hwInstance];
+ 		xQueueSendFromISR(UartHalQueueHandle,&UartHalMsg,pdFALSE);
+    }
+}
+
+/*CAN*/
+Can_PduType Can_CreatePduInfo(Can_IdType id, CAN_IdFrameType idFrame, PduIdType swPduHandle, uint8 length, uint8 *sdu)
+{
+    Can_PduType PduInfo;
+    switch (idFrame)
+    {
+    case CAN_STANDARD_ID_TYPE:
+        id = id & 0x7FF;
+        break;
+    case CANFD_STANDARD_ID_TYPE:
+        id = (id & 0x7FF) | 0x40000000;
+        break;
+    case CAN_EXTENDED_ID_TYPE:
+        id = id | 0x80000000;
+        break;
+    case CANFD_EXTENDED_ID_TYPE:
+        id = id | 0xC0000000;
+        break;
+    default:
+        id = id & 0x7FF;
+        break;
+    }
+    PduInfo.id = id;
+    PduInfo.swPduHandle = swPduHandle;
+    PduInfo.length = length;
+    PduInfo.sdu = sdu;
+    return PduInfo;
+}
+Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg)
+{
+    volatile Can_PduType Can_PduInfo;
+    volatile Std_ReturnType CAN_Write_Status;
+    Std_ReturnType retVal = E_NOT_OK;
+    uint32 u8TimeOut = 100 * 100;
+    Can_HwHandleType Hth = Can0HardwareObject_TX + (Can_HwHandleType)ControllerId; // controller 0 --> Can0HardwareObject_TX
+
+    Can_PduInfo = Can_CreatePduInfo(CanMsg.id, CanMsg.idFrame, 0, CanMsg.length, CanMsg.sdu);
+
+    CAN_Write_Status = Can_Write(Hth, &Can_PduInfo);
+
+    CanIf_bTxFlag = FALSE;
+    if (CAN_Write_Status == E_OK)
+    {
+        while ((!CanIf_bTxFlag) && (u8TimeOut != 0U))
+        {
+            Can_MainFunction_Write();
+            u8TimeOut--;
+        }
+    }
+
+    if (CanIf_bTxFlag == TRUE)
+    {
+        retVal = E_OK;
+    }
+    else
+    {
+        retVal = E_NOT_OK;
+    }
+    return retVal;
+}
+Can_Msg_Type Can_GetMsgInfo(Can_IdType id, uint8 length, uint8 *sdu)
+{
+    Can_Msg_Type CanMsgInfo;
+
+    CanMsgInfo.idFrame = (CAN_IdFrameType)((id >> 30) & 0x03);
+    if (CanMsgInfo.idFrame & 0x01)
+    {
+        CanMsgInfo.id = id & 0x7FF;
+    }
+    else
+    {
+        CanMsgInfo.id = id & 0x1FFFFFFF;
+    }
+    CanMsgInfo.length = length;
+    CanMsgInfo.sdu = sdu;
+
+    return CanMsgInfo;
+}
+
+void CanIf_ControllerBusOff(uint8 ControllerId)
+{
+    (void)ControllerId;
+}
+
+void CanIf_ControllerModeIndication(uint8 ControllerId, Can_ControllerStateType ControllerMode)
+{
+    (void)ControllerId;
+    (void)ControllerMode;
+}
+void CanIf_TxConfirmation(PduIdType CanTxPduId)
+{
+    CanIf_u8TxConfirmCnt++;
+    CanIf_bTxFlag = TRUE;
+    (void)CanTxPduId;
+}
+void CanIf_RxIndication(const Can_HwType *Mailbox, const PduInfoType *PduInfoPtr)
+{
+    Can_Msg_Type canRxMsg_Buff;
+    Can_Msg_Type_Data canRxMsgQueueData;
+    CanIf_bRxFlag = TRUE; // should not be delete
+    // should put the msg into message queue
+    canRxMsg_Buff = Can_GetMsgInfo(Mailbox->CanId, PduInfoPtr->SduLength, PduInfoPtr->SduDataPtr);
+    canRxMsgQueueData.id = canRxMsg_Buff.id;
+    canRxMsgQueueData.length = canRxMsg_Buff.length;
+    memcpy(canRxMsgQueueData.data, canRxMsg_Buff.sdu, canRxMsgQueueData.length);
+    xQueueSend(CanRecvQueueHandle, &canRxMsgQueueData, 0);
+}
+
+void CanIf_CurrentIcomConfiguration(uint8 ControllerId, IcomConfigIdType ConfigurationId, IcomSwitch_ErrorType Error)
+{
+    (void)ControllerId;
+    (void)ConfigurationId;
+    (void)Error;
+}
+
+void Notification_0(void)
+{
+    ADC_Converter(ResultBuffer, ConvertedBuffer);
+    memcpy(BattTempR, &ConvertedBuffer[3], 4 * sizeof(uint32));
+}
+
+void Notification_1(void)
+{
+    VarNotification_1++;
+}
+
+Std_ReturnType ADC_Converter(Adc_ValueGroupType *Buffer, TP_Value_Type *ConvertedValueR)
+{
+    Adc_ValueGroupType REFH, REFL;
+    REFH = Buffer[0];
+    REFL = Buffer[2];
+    for (int i = 3; i < NUM_RESULTS; i++)
+    {
+        if (Buffer[i] >= REFH)
+        {
+            ConvertedValueR[i] = 40930000;
+        }
+        else if (Buffer[i] <= REFL)
+        {
+            ConvertedValueR[i] = 0x00;
+        }
+        else
+        {
+            ConvertedValueR[i] = (TP_Value_Type)((float)(10000 * (Buffer[i] - REFL) / (float)(REFH - REFL)) / (1 - (float)((Buffer[i] - REFL) / (float)(REFH - REFL))));
+        }
+    }
+}
+
+Std_ReturnType ADC_ReadValue()
+{
+    Std_ReturnType ret = E_NOT_OK;
+    Adc_ValueGroupType AdcReadGroupBuffer[NUM_RESULTS];
+    volatile Std_ReturnType Status = TRUE;
+    for (int i = 0; i < NUM_RESULTS; i++)
+    {
+        ResultBuffer[i] = 0xFFFF;
+        AdcReadGroupBuffer[i] = 0xFFFE;
+        ConvertedBuffer[i] = 0x00;
+    }
+    Adc_SetupResultBuffer(AdcGroupSoftwareOneShot, ResultBuffer);
+    Adc_EnableGroupNotification(AdcGroupSoftwareOneShot);
+    VarNotification_0 = 0;
+    Adc_StartGroupConversion(AdcGroupSoftwareOneShot);
+    //	 uint32 TimeOut = 0;
+    //	 while(VarNotification_0 == 0 && VarNotification_1==0 && TimeOut<0xFFFF)
+    //	 {
+    //		 TimeOut++;
+    //	 }
+    //	 AdcStates = Adc_ReadGroup(AdcGroupSoftwareOneShot, AdcReadGroupBuffer);
+    //	 if(AdcStates == E_NOT_OK)
+    //	 {
+    //		 return AdcStates;
+    //	 }
+    //	 else
+    //	 {
+    //		 ret = E_OK;
+    //	 }
+    return ret;
+}
+
+/*EEP*/
+static Std_ReturnType TestEep_FlexNvmProgramPartCmd(
+    VAR(TestEep_CsecKeySize, AUTOMATIC) eepKeysize,
+    VAR(TestEep_SfeType, AUTOMATIC) eepSecurityFlagExtension,
+    VAR(TestEep_LoadFlexRamType, AUTOMATIC) eepLoadFlexRamAtReset,
+    VAR(TestEep_Eeprom_FlexRamPartitionType, AUTOMATIC) eepFlexRamPartition,
+    VAR(TestEep_Eeprom_FlexNvmPartitionType, AUTOMATIC) eepFlexNvmPartition)
+{
+    Std_ReturnType u8RetVal = (Std_ReturnType)E_OK;
+    uint32 u32Addr = 0;
+    uint32 u32FlexNvmPartSize = 0;
+
+    uint32 u32RegSimFcfg1 = 0UL;
+
+    u32RegSimFcfg1 = IP_SIM->FCFG1;
+
+    /*get DEPART value */
+    u32FlexNvmPartSize = (uint32)((u32RegSimFcfg1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT);
+
+    /* check that it was not partitioned before */
+    if (u32FlexNvmPartSize == 0xF)
+    {
+        //         /* if error flags are set the cmd is not executed */
+        //         REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8);
+        //
+        //         /*erase DF 0 sector*/
+        //         u32Addr=(TEST_EEP_DEEPROM_SECTOR_0_ADDR32 - D_EEPROM_BASE_ADDR) + 0x800000UL;
+        //
+        //         REG_WRITE8(TEST_EEP_EEPROM_FCCOB0_ADDR32, TEST_EEP_EEPROM_CMD_ERASE_SECTOR);
+        //         REG_WRITE8(TEST_EEP_EEPROM_FCCOB1_ADDR32, (uint8)(u32Addr >> 16UL));
+        //         REG_WRITE8(TEST_EEP_EEPROM_FCCOB2_ADDR32, (uint8)(u32Addr >> 8UL));
+        //         REG_WRITE8(TEST_EEP_EEPROM_FCCOB3_ADDR32, (uint8)(u32Addr >> 0UL));
+        //         REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32 , TEST_EEP_EEPROM_FSTAT_CCIF_U8);
+        //         while((0U == REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_CCIF_U8)))
+        //         {
+        //         }
+        //
+        if (0U == REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8))
+        {
+            /* run program partition command */
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB0_ADDR32, EEPROM_CMD_PROGRAM_PARTITION);
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB1_ADDR32, (uint8)eepKeysize);
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB2_ADDR32, (uint8)eepSecurityFlagExtension);
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB3_ADDR32, (uint8)eepLoadFlexRamAtReset);
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB4_ADDR32, (uint8)eepFlexRamPartition);
+            REG_WRITE8(TEST_EEP_EEPROM_FCCOB5_ADDR32, (uint8)eepFlexNvmPartition);
+            REG_WRITE8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_CCIF_U8);
+            while ((0U == REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_CCIF_U8)))
+            {
+                /* wait for operation to finish */
+            }
+            /* check if errors occured  */
+            if (REG_BIT_GET8(TEST_EEP_EEPROM_FSTAT_ADDR32, TEST_EEP_EEPROM_FSTAT_ACCERR_U8 | TEST_EEP_EEPROM_FSTAT_FPVIOL_U8))
+            {
+                /* NOK, error flags are set */
+                u8RetVal = (Std_ReturnType)E_NOT_OK;
+            }
+        }
+        else
+        {
+            /* NOK, error flags are set */
+            u8RetVal = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    else
+    {
+        /* NOK, partitioned already */
+        u8RetVal = (Std_ReturnType)E_NOT_OK;
+    }
+    return u8RetVal;
+}
+
+void Eep_DepartParitition(TestEep_Eeprom_FlexNvmPartitionType T_EEP_SIZE)
+{
+    uint32 u32FlexNvmPartSize = 0;
+
+    uint32 u32RegSimFcfg1 = 0UL;
+
+    u32RegSimFcfg1 = IP_SIM->FCFG1;
+
+    /*get DEPART value */
+    u32FlexNvmPartSize = (uint32)((u32RegSimFcfg1 & SIM_FCFG1_DEPART_MASK) >> SIM_FCFG1_DEPART_SHIFT);
+    if (u32FlexNvmPartSize == 0xF) /* We just partition again if curent size different with expected */
+    {
+        /* partition for EERAM 64K with NOT loading EERAM at reset in hardware */
+        TestEep_FlexNvmProgramPartCmd(EEP_FTFC_KEY_SIZE_0_BYTES, EEP_FTFC_VERIFY_ONLY_DISABLED,
+                                      EEP_FTFC_LOAD_AT_RESET_ENABLED, EEP_FTFC_EERAM_SIZE_4K, T_EEP_SIZE);
+    }
+}
+/* Erase memory by writing erase value */
+Std_ReturnType HAL_EEP_Erase(uint32 eepEraseStartAddr, uint32 eepEraseSize)
+{
+    Std_ReturnType retReturnType = E_OK;
+    MemIf_JobResultType retJobResultType;
+    retReturnType = Eep_Erase(eepEraseStartAddr, eepEraseSize);
+    if (E_OK != retReturnType)
+    {
+        return E_NOT_OK;
+    }
+    while (MEMIF_IDLE != Eep_GetStatus())
+    {
+        Eep_MainFunction();
+    }
+    retJobResultType = Eep_GetJobResult();
+    if (MEMIF_JOB_OK != retJobResultType)
+    {
+        return E_NOT_OK;
+    }
+    return E_OK;
+}
+
+/* Write one or more complete eeprom pages to the eeprom device */
+Std_ReturnType HAL_EEP_Write(uint32 eepWriteStartAddr, uint8 *pDataNeedtoWrite, uint32 dataSize)
+{
+    Std_ReturnType retReturnType = E_OK;
+    MemIf_JobResultType retJobResultType;
+
+    /*Erase the EEP before write*/
+    retReturnType = HAL_EEP_Erase(eepWriteStartAddr, dataSize);
+    if (E_OK != retReturnType)
+    {
+        return E_NOT_OK;
+    }
+
+    retReturnType = Eep_Write(eepWriteStartAddr, pDataNeedtoWrite, dataSize);
+    if (E_OK != retReturnType)
+    {
+        return E_NOT_OK;
+    }
+    while (MEMIF_IDLE != Eep_GetStatus())
+    {
+        Eep_MainFunction();
+    }
+    retJobResultType = Eep_GetJobResult();
+    if (MEMIF_JOB_OK != retJobResultType)
+    {
+        return E_NOT_OK;
+    }
+    return E_OK;
+}
+
+/* Reads from eeprom memory */
+Std_ReturnType HAL_EEP_Read(uint32 eepReadStartAddr, uint8 *pDataBuffer, uint32 dataSize)
+{
+    Std_ReturnType retReturnType = E_OK;
+    MemIf_JobResultType retJobResultType;
+    retReturnType = Eep_Read(eepReadStartAddr, pDataBuffer, dataSize);
+    if (E_OK != retReturnType)
+    {
+        return E_NOT_OK;
+    }
+    while (MEMIF_IDLE != Eep_GetStatus())
+    {
+        Eep_MainFunction();
+    }
+    retJobResultType = Eep_GetJobResult();
+    if (MEMIF_JOB_OK != retJobResultType)
+    {
+        return E_NOT_OK;
+    }
+    return E_OK;
+}
+
+/* Compares a eeprom memory area with an application data buffer */
+Std_ReturnType HAL_EEP_Compare(uint32 eepCompareStartAddr, uint8 *pDataNeedtoCompare, uint32 dataSize)
+{
+    Std_ReturnType retReturnType = E_OK;
+    MemIf_JobResultType retJobResultType;
+    retReturnType = Eep_Compare(eepCompareStartAddr, pDataNeedtoCompare, dataSize);
+    if (E_OK != retReturnType)
+    {
+        return E_NOT_OK;
+    }
+    while (MEMIF_IDLE != Eep_GetStatus())
+    {
+        Eep_MainFunction();
+    }
+    retJobResultType = Eep_GetJobResult();
+    if (MEMIF_JOB_OK != retJobResultType)
+    {
+        return E_NOT_OK;
+    }
+    return E_OK;
+}
+/* @brief VECTKEY value so that AIRCR register write is not ignored. */
+#define FEATURE_SCB_VECTKEY               (0x05FAU)
+void SystemSoftwareReset(void)
+{
+    uint32_t regValue;
+
+    /* Read Application Interrupt and Reset Control Register */
+    regValue = S32_SCB->AIRCR;
+
+    /* Clear register key */
+    regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
+
+    /* Configure System reset request bit and Register Key */
+    regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
+    regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
+
+    /* Write computed register value */
+    S32_SCB->AIRCR = regValue;
+}

src/hal_adapter.h

@@ -3,9 +3,9 @@
  * @Date         : 2022-01-23 13:52:10
  * @Version      : V3.0
  * @LastEditors  : ChenJie
- * @LastEditTime : 2022-01-23 16:10:21
+ * @LastEditTime : 2022-05-17 16:22:16
  * @Description  : file content
- * @FilePath     : \PLAT\project\ec616_0h00\apps\qx_app\src\AT_CMD\hal_adapter.h
+ * @FilePath     : \S32K146_4G\src\hal_adapter.h
  */
 /*
  * hal_adapter.h
@@ -16,187 +16,224 @@
 
 #ifndef HAL_ADAPTER_H_
 #define HAL_ADAPTER_H_
- #include "Mcal.h"
- #include "CAN.h"
- #include "SchM_Can.h"
- #include "Mcu.h"
- #include "Mcl.h"
- #include "Port.h"
- #include "Dio.h"
- #include "Uart.h"
- #include "Platform.h"
- #include "Lpuart_Uart_Ip_Irq.h"
- #include "Flexio_Uart_Ip_Irq.h"
- #include <string.h>
- #include <stdlib.h>
- #include "Dma_Ip.h"
- #include "Dma_Ip_Irq.h"
- #include "Lpuart_Uart_Ip.h"
- #include "FreeRTOS.h"
- #include "timers.h"
- #include "task.h"
- #include "semphr.h"
- #include "Adc.h"
- #include "Eep.h"
- #include "SL_Sc7a20_Driver.h"
+#include "Mcal.h"
+#include "CAN.h"
+#include "SchM_Can.h"
+#include "Mcu.h"
+#include "Mcl.h"
+#include "Port.h"
+#include "Dio.h"
+#include "Uart.h"
+#include "Platform.h"
+#include "Lpuart_Uart_Ip_Irq.h"
+#include "Flexio_Uart_Ip_Irq.h"
+#include <string.h>
+#include <stdlib.h>
+#include "Dma_Ip.h"
+#include "Dma_Ip_Irq.h"
+#include "Lpuart_Uart_Ip.h"
+#include "FreeRTOS.h"
+#include "timers.h"
+#include "task.h"
+#include "semphr.h"
+#include "Adc.h"
+#include "Eep.h"
+#include "Fls.h"
+#include "SchM_Fls.h"
+#include "SL_Sc7a20_Driver.h"
+/*适应性定义*/
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned long UINT32;
+typedef unsigned char BOOL;
+typedef signed char INT8;
+typedef signed short INT16;
+typedef signed long INT32;
+
 #define CAN0 0
 #define CAN1 1
-
 #ifndef min
-#define min(A,B) ((A) <= (B) ? (A) : (B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
 #endif
 #ifndef max
-#define max(A,B) ((A) < (B) ? (B) : (A))
+#define max(A, B) ((A) < (B) ? (B) : (A))
 #endif
-#define getbit(x,y)     ((x) >> (y)&1)                        //获取x的第y位的数值
-#define setbit(x,y)     x|=(1<<y)                             //x的第y位置1
-#define clrbit(x,y)     x&=~(1<<y)                            //x的第y位置0
- #define UART_LPUART0 0
- #define UART_LPUART1 1
- #define UART_LPUART2 2
- #define FLEXIO_RX 3
- #define FLEXIO_TX 4
- #define main_TASK_PRIORITY                ( tskIDLE_PRIORITY + 7 )
-
- #define MSG_LEN 50U
- #define TJA1153_START_ID (uint32_t)(0x555u)
- #define TJA1153_CONFIG_ID (uint32_t)(0x18DA00F1u)
-#define NUM_RESULTS             ADC_CFGSET_VS_0_GROUP_0_CHANNELS
- #define BUFFER_SIZE 1000
- #define DMA_SIZE 20
- extern uint8_t RX_Buffer[3][BUFFER_SIZE];
+#define getbit(x, y) ((x) >> (y)&1) //获取x的第y位的数值
+#define setbit(x, y) x |= (1 << y)  // x的第y位置1
+#define clrbit(x, y) x &= ~(1 << y) // x的第y位置0
+#define UART_LPUART0 0
+#define UART_LPUART1 1
+#define UART_LPUART2 2
+#define FLEXIO_RX 3
+#define FLEXIO_TX 4
+#define main_TASK_PRIORITY (tskIDLE_PRIORITY + 7)
 
- typedef enum
- {
-	 SystemTPChannel = 0,
-	 SlowChargeTPChannel,
-	 QuickChargeTPChannel,
-	 CC1TPChannel,
-	 ChannelCounter = 4,
- }ADC_TP_Channel_Type;
+#define MSG_LEN 50U
+#define TJA1153_START_ID (uint32_t)(0x555u)
+#define TJA1153_CONFIG_ID (uint32_t)(0x18DA00F1u)
+#define NUM_RESULTS ADC_CFGSET_VS_0_GROUP_0_CHANNELS
+#define BUFFER_SIZE 1024
+#define DMA_SIZE 128
 
- typedef uint32 TP_Value_Type;
- Std_ReturnType  ADC_ReadValue(void);
-// extern uint8 GpsBufferGet[GPSBUFFER_SIZE];
- Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 *rxBuffer, uint16 *rxlen,uint32 T_timeout);
- Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout);
- Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer,uint16 *rxlen, sint32 T_timeout);
- void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event);
 
- /*CAN*/
- typedef enum
- {
-     CAN_STANDARD_ID_TYPE = 0x00,   /**< * -00b CAN message with Standard CAN ID  */
-     CANFD_STANDARD_ID_TYPE = 0x01, /**< * -01b CAN FD frame with Standard CAN ID  */
-     CAN_EXTENDED_ID_TYPE = 0x02,   /**< * -10b CAN message with Extended CAN ID  */
-     CANFD_EXTENDED_ID_TYPE = 0x03, /**< * -11b CAN FD frame with Extended CAN ID  */
- } CAN_IdFrameType;
 
  typedef struct
  {
-     Can_IdType id;
-
-     CAN_IdFrameType idFrame;
-
-     uint8 length; /**< @brief DLC = Data Length Code (part of L-PDU that describes
-                                             the SDU length). */
-     uint8 *sdu;   /**< @brief CAN L-SDU = Link Layer Service Data
-                                                            Unit. Data that is transported inside
-                                                            the L-PDU. */
- } Can_Msg_Type;
+     uint16 DataLen;
+     uint8 *dataPrt;
+ } UartMsg_t;
  typedef struct
  {
-	 Can_IdType id;
-	 uint8 length;
-	 uint8 data[8];
- }Can_Msg_Type_Data;
- extern Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg);
-
- /*EEP*/
-
+	 uint8 Channel;
+	 Lpuart_Uart_Ip_EventType event;
+     uint16  value;
+ } UartHalMsg_t;
  typedef enum
  {
-     EEP_FTFC_KEY_SIZE_0_BYTES   = 0x0,  /**< @brief control code for key size 0 bytes, used for the partitioning command */
-     EEP_FTFC_KEY_SIZE_128_BYTES = 0x1,  /**< @brief control code for key size 128 bytes, used for the partitioning command */
-     EEP_FTFC_KEY_SIZE_256_BYTES = 0x2,  /**< @brief control code for key size 256 bytes, used for the partitioning command */
-     EEP_FTFC_KEY_SIZE_512_BYTES = 0x3   /**< @brief control code for key size 512 bytes, used for the partitioning command */
- } TestEep_CsecKeySize;
-
- /**
-     @brief FlexRamPartition Type used for the partitioning command
- */
+	 UartStartRecv = 0,
+	 UartAbortRecv,
+	 UartRecvOnGoing,
+	 UartRecvComplete,
+
+	 UartStartSend,
+	 UartAbortSend,
+	 UartSendOnGoing,
+	 UartSendComplete,
+	 UartNoDataSend,
+ };
  typedef enum
  {
-     EEP_FTFC_EERAM_SIZE_0K  = 0xF,   /**< @brief control code for flexram partitioned as sram, used for the partitioning command */
-     EEP_FTFC_EERAM_SIZE_4K  = 0x2,   /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */
-     EEP_FTFC_EERAM_SIZE_2K  = 0x3    /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */
- } TestEep_Eeprom_FlexRamPartitionType;
-
- /**
-     @brief FlexNvmPartition Type used for the partitioning command
- */
- typedef enum
- {
-     EEP_FTFC_EEEPROM_SIZE_0K_V1   =  0x0,   /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_0K_V2   =  0xC,   /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_0K_V3   =  0x0F,  /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_32K_V1  = 0x3,    /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_32K_V2  = 0xB,    /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_48K_V1  = 0xA,    /**< @brief control code to partition EEPROM backup size as 48K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_64K_V1  = 0x8,    /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_64K_V2  = 0x4,    /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */
-     EEP_FTFC_EEEPROM_SIZE_24K_V2  = 0x9     /**< @brief control code to partition EEPROM backup size as 24K, used for the partitioning command */
- } TestEep_Eeprom_FlexNvmPartitionType;
- /**
-     @brief Sfe Type used for the partitioning command
- */
- typedef enum
- {
-     EEP_FTFC_VERIFY_ONLY_DISABLED  = 0x0,    /**< @brief control code for sfe verify only disabled, used for the partitioning command */
-     EEP_FTFC_VERIFY_ONLY_ENABLED   = 0x1     /**< @brief control code for sfe verify only enabled, used for the partitioning command */
- } TestEep_SfeType;
+	 SystemTPChannel = 0,
+	 SlowChargeTPChannel,
+	 QuickChargeTPChannel,
+	 CC1TPChannel,
+	 ChannelCounter = 4,
+ }ADC_TP_Channel_Type;
 
- /**
-     @brief LoadFlexRam at reset Type used for the partitioning command
- */
- typedef enum
- {
-     EEP_FTFC_LOAD_AT_RESET_ENABLED  = 0x0,  /**< @brief control code for loading flexram at reset, used for the partitioning command */
-     EEP_FTFC_LOAD_AT_RESET_DISABLED = 0x1   /**< @brief control code for not loading flexram at reset, used for the partitioning command */
- } TestEep_LoadFlexRamType;
-
-#define EEP_ERASE_START_ADD         (0U)
-#define EEP_WRTESTPATT_SIZE         (33U)
-#define EEP_RDTESTPATT_SIZE         (33U)
-
-#define REG_WRITE8(address, value)        							(*((volatile uint8*)(address)) = (value))
-#define REG_BIT_GET8(address, mask)       							((*(volatile uint8*)(address))& (mask))
-
-#define T_EEEPROM_SIZE                     							EEP_FTFC_EEEPROM_SIZE_32K_V2
-#define TEST_EEP_EEPROM_FSTAT_ADDR32                               ((uint32)(IP_FTFC_BASE + (uint32)0x00UL)) /**< @brief Eeprom Status Register (FTFE_FSTAT) */
-#define TEST_EEP_EEPROM_FCCOB3_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x04UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB3) */
-#define TEST_EEP_EEPROM_FCCOB2_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x05UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB2) */
-#define TEST_EEP_EEPROM_FCCOB1_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x06UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB1) */
-#define TEST_EEP_EEPROM_FCCOB0_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x07UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB0) */
-#define TEST_EEP_EEPROM_FCCOB7_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x08UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB7) */
-#define TEST_EEP_EEPROM_FCCOB6_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x09UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB6) */
-#define TEST_EEP_EEPROM_FCCOB5_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x0AUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB5) */
-#define TEST_EEP_EEPROM_FCCOB4_ADDR32                              ((uint32)(IP_FTFC_BASE + (uint32)0x0BUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB4) */
-
-#define TEST_EEP_EEPROM_FSTAT_CCIF_U8                              (0x0080U)
-#define TEST_EEP_EEPROM_FSTAT_ACCERR_U8                            (0x0020U)
-#define TEST_EEP_EEPROM_FSTAT_FPVIOL_U8                            (0x0010U)
+typedef uint32 TP_Value_Type;
+uint16 myPrintf(const char *fmt, ...);
+Std_ReturnType ADC_ReadValue(void);
+// extern uint8 GpsBufferGet[GPSBUFFER_SIZE];
+Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, const uint8 *txBuffer, uint32 sendLength, uint8 **rxBuffer, uint16 *rxlen, uint32 T_timeout);
+Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout);
+Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 **rxBuffer, uint16 *rxlen, sint32 T_timeout);
+void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event);
+void UartInit(void);
+void SystemSoftwareReset(void);
+/*CAN*/
+typedef enum
+{
+    CAN_STANDARD_ID_TYPE = 0x00,   /**< * -00b CAN message with Standard CAN ID  */
+    CANFD_STANDARD_ID_TYPE = 0x01, /**< * -01b CAN FD frame with Standard CAN ID  */
+    CAN_EXTENDED_ID_TYPE = 0x02,   /**< * -10b CAN message with Extended CAN ID  */
+    CANFD_EXTENDED_ID_TYPE = 0x03, /**< * -11b CAN FD frame with Extended CAN ID  */
+} CAN_IdFrameType;
+
+typedef struct
+{
+    Can_IdType id;
+
+    CAN_IdFrameType idFrame;
+
+    uint8 length; /**< @brief DLC = Data Length Code (part of L-PDU that describes
+                                            the SDU length). */
+    uint8 *sdu;   /**< @brief CAN L-SDU = Link Layer Service Data
+                                                           Unit. Data that is transported inside
+                                                           the L-PDU. */
+} Can_Msg_Type;
+typedef struct
+{
+    Can_IdType id;
+    uint8 length;
+    uint8 data[8];
+} Can_Msg_Type_Data;
+extern Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg);
+
+/*EEP*/
+
+typedef enum
+{
+    EEP_FTFC_KEY_SIZE_0_BYTES = 0x0,   /**< @brief control code for key size 0 bytes, used for the partitioning command */
+    EEP_FTFC_KEY_SIZE_128_BYTES = 0x1, /**< @brief control code for key size 128 bytes, used for the partitioning command */
+    EEP_FTFC_KEY_SIZE_256_BYTES = 0x2, /**< @brief control code for key size 256 bytes, used for the partitioning command */
+    EEP_FTFC_KEY_SIZE_512_BYTES = 0x3  /**< @brief control code for key size 512 bytes, used for the partitioning command */
+} TestEep_CsecKeySize;
+
+/**
+    @brief FlexRamPartition Type used for the partitioning command
+*/
+typedef enum
+{
+    EEP_FTFC_EERAM_SIZE_0K = 0xF, /**< @brief control code for flexram partitioned as sram, used for the partitioning command */
+    EEP_FTFC_EERAM_SIZE_4K = 0x2, /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */
+    EEP_FTFC_EERAM_SIZE_2K = 0x3  /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */
+} TestEep_Eeprom_FlexRamPartitionType;
+
+/**
+    @brief FlexNvmPartition Type used for the partitioning command
+*/
+typedef enum
+{
+    EEP_FTFC_EEEPROM_SIZE_0K_V1 = 0x0,  /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_0K_V2 = 0xC,  /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_0K_V3 = 0x0F, /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_32K_V1 = 0x3, /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_32K_V2 = 0xB, /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_48K_V1 = 0xA, /**< @brief control code to partition EEPROM backup size as 48K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_64K_V1 = 0x8, /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_64K_V2 = 0x4, /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */
+    EEP_FTFC_EEEPROM_SIZE_24K_V2 = 0x9  /**< @brief control code to partition EEPROM backup size as 24K, used for the partitioning command */
+} TestEep_Eeprom_FlexNvmPartitionType;
+/**
+    @brief Sfe Type used for the partitioning command
+*/
+typedef enum
+{
+    EEP_FTFC_VERIFY_ONLY_DISABLED = 0x0, /**< @brief control code for sfe verify only disabled, used for the partitioning command */
+    EEP_FTFC_VERIFY_ONLY_ENABLED = 0x1   /**< @brief control code for sfe verify only enabled, used for the partitioning command */
+} TestEep_SfeType;
+
+/**
+    @brief LoadFlexRam at reset Type used for the partitioning command
+*/
+typedef enum
+{
+    EEP_FTFC_LOAD_AT_RESET_ENABLED = 0x0, /**< @brief control code for loading flexram at reset, used for the partitioning command */
+    EEP_FTFC_LOAD_AT_RESET_DISABLED = 0x1 /**< @brief control code for not loading flexram at reset, used for the partitioning command */
+} TestEep_LoadFlexRamType;
+
+#define EEP_ERASE_START_ADD (0U)
+#define EEP_WRTESTPATT_SIZE (33U)
+#define EEP_RDTESTPATT_SIZE (33U)
+
+#define REG_WRITE8(address, value) (*((volatile uint8 *)(address)) = (value))
+#define REG_BIT_GET8(address, mask) ((*(volatile uint8 *)(address)) & (mask))
+
+#define T_EEEPROM_SIZE EEP_FTFC_EEEPROM_SIZE_32K_V2
+#define TEST_EEP_EEPROM_FSTAT_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x00UL))  /**< @brief Eeprom Status Register (FTFE_FSTAT) */
+#define TEST_EEP_EEPROM_FCCOB3_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x04UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB3) */
+#define TEST_EEP_EEPROM_FCCOB2_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x05UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB2) */
+#define TEST_EEP_EEPROM_FCCOB1_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x06UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB1) */
+#define TEST_EEP_EEPROM_FCCOB0_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x07UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB0) */
+#define TEST_EEP_EEPROM_FCCOB7_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x08UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB7) */
+#define TEST_EEP_EEPROM_FCCOB6_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x09UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB6) */
+#define TEST_EEP_EEPROM_FCCOB5_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x0AUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB5) */
+#define TEST_EEP_EEPROM_FCCOB4_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x0BUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB4) */
+
+#define TEST_EEP_EEPROM_FSTAT_CCIF_U8 (0x0080U)
+#define TEST_EEP_EEPROM_FSTAT_ACCERR_U8 (0x0020U)
+#define TEST_EEP_EEPROM_FSTAT_FPVIOL_U8 (0x0010U)
 /* Start address for DFLASH sector 0 */
-#define TEST_EEP_DEEPROM_SECTOR_0_ADDR32                           0x10000000
-#define D_EEPROM_BASE_ADDR                                         (0x10000000UL)
-#define TEST_EEP_EEPROM_CMD_ERASE_SECTOR                           (0x09UL)
+#define TEST_EEP_DEEPROM_SECTOR_0_ADDR32 0x10000000
+#define D_EEPROM_BASE_ADDR (0x10000000UL)
+#define TEST_EEP_EEPROM_CMD_ERASE_SECTOR (0x09UL)
 
-#define EEPROM_CMD_PROGRAM_PARTITION                               (0x80UL)
+#define EEPROM_CMD_PROGRAM_PARTITION (0x80UL)
 
- void Eep_DepartParitition(TestEep_Eeprom_FlexNvmPartitionType T_EEP_SIZE);
- Std_ReturnType HAL_EEP_Erase(uint32 eepEraseStartAddr,uint32 eepEraseSize);
- Std_ReturnType HAL_EEP_Read(uint32 eepReadStartAddr,uint8* pDataBuffer,uint32 dataSize);
- Std_ReturnType HAL_EEP_Write(uint32 eepWriteStartAddr,uint8* pDataNeedtoWrite,uint32 dataSize);
- Std_ReturnType HAL_EEP_Compare(uint32 eepCompareStartAddr,uint8* pDataNeedtoCompare,uint32 dataSize);
+void Eep_DepartParitition(TestEep_Eeprom_FlexNvmPartitionType T_EEP_SIZE);
+Std_ReturnType HAL_EEP_Erase(uint32 eepEraseStartAddr, uint32 eepEraseSize);
+Std_ReturnType HAL_EEP_Read(uint32 eepReadStartAddr, uint8 *pDataBuffer, uint32 dataSize);
+Std_ReturnType HAL_EEP_Write(uint32 eepWriteStartAddr, uint8 *pDataNeedtoWrite, uint32 dataSize);
+Std_ReturnType HAL_EEP_Compare(uint32 eepCompareStartAddr, uint8 *pDataNeedtoCompare, uint32 dataSize);
 
 #endif /* HAL_ADAPTER_H_ */

src/main.c

@@ -39,12 +39,16 @@
 #include "Dio.h"
 #include "Uart.h"
 #include "Eep.h"
+#include "Fls.h"
+#include "SchM_Fls.h"
 #include "Platform.h"
 #include "Lpuart_Uart_Ip_Irq.h"
 #include "Flexio_Uart_Ip_Irq.h"
 #include "Dma_Ip.h"
 #include "Dma_Ip_Irq.h"
 #include "Lpuart_Uart_Ip.h"
+#include "Gpt.h"
+#include "Wdg_43_Instance0.h"
 /* User includes */
 
 #include <string.h>
@@ -56,9 +60,8 @@
 #include "AppTaskUart1.h"
 #include "AppTaskCan.h"
 #include "AppTaskGps.h"
+#include "Hal_Fls.h"
 
-#include "Gpt.h"
-#include "Wdg_43_Instance0.h"
 
 
 
@@ -117,12 +120,22 @@ int main(void)
 #endif /* ADC_PRECOMPILE_SUPPORT == STD_ON */
 
     /* Partition only if it was not partitioned before for EERAM with code 0x4 */
-//    Eep_DepartParitition(T_EEEPROM_SIZE);
+    Eep_DepartParitition(T_EEEPROM_SIZE);
     /* Initialize Eep driver */
 #if defined (EEP_PRECOMPILE_SUPPORT)
     Eep_Init(NULL_PTR);
 #else
     Eep_Init(&Eep_Config_VS_0);
+#endif
+    //Init Flash Driver
+#if defined (FLS_PRECOMPILE_SUPPORT)
+    Fls_Init(NULL_PTR);
+#else
+    Fls_Init(&Fls_Config_VS_0);
+    while(MEMIF_IDLE == Fls_GetStatus())
+    {
+    	;
+    }
 #endif
 	// this function should be called in ADC Task at once
 	Adc_CalibrationStatusType CalibStatus;
@@ -146,6 +159,9 @@ int main(void)
 	IP_LPUART0->CTRL |= LPUART_CTRL_ILT(1);
 	IP_LPUART1->CTRL |= LPUART_CTRL_ILT(1);
 	IP_LPUART2->CTRL |= LPUART_CTRL_ILT(1);
+	IP_LPUART0->CTRL |= LPUART_CTRL_IDLECFG(5);
+	IP_LPUART1->CTRL |= LPUART_CTRL_IDLECFG(3);
+	IP_LPUART2->CTRL |= LPUART_CTRL_IDLECFG(3);
 
 	Dio_WriteChannel(DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1, STD_OFF);
 	Dio_WriteChannel(DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2, STD_OFF);
@@ -153,9 +169,10 @@ int main(void)
 	Dio_WriteChannel(DioConf_DioChannel_PTE8_GPIO_OUT_MCU_LED4, STD_OFF);
 	Dio_WriteChannel(DioConf_DioChannel_PTE9_GPIO_OUT_MCU_LED5, STD_OFF);
 
+	UartInit();
 	xTaskCreate(MainTask, (const char *const)"MainTask", 512, (void *)0, main_TASK_PRIORITY + 3, NULL);
 	xTaskCreate(Uart0Task, (const char *const)"Uart0_Bms_Task", 512, (void *)0, main_TASK_PRIORITY + 2, NULL);
-	xTaskCreate(CanTask, (const char *const)"CanTask", 512, (void *)0, main_TASK_PRIORITY + 2, NULL);
+//	xTaskCreate(CanTask, (const char *const)"CanTask", 512, (void *)0, main_TASK_PRIORITY + 2, NULL);
 	xTaskCreate(GpsTask, (const char *const)"GpsTask", 512, (void *)0, main_TASK_PRIORITY + 1, NULL);
 	xTaskCreate(Uart_4G_Task, (const char *const)"Uart_4G_Task", 2048, (void *)0, main_TASK_PRIORITY + 0, NULL);
 	vTaskStartScheduler();