1、增加SPI底层驱动

2、配置PLL，内核时钟采用PLL_CLK（80M），LSPI使用PLL时钟，UART、CAN使用SOSC时钟（16M）
3、删除FlexIO在UART中的应用，仅保留uart0-2

.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="512964616103659477" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="50541842775723316" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -16,7 +16,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="512964616103659477" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="50541842775723316" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -27,7 +27,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="512964616103659477" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="50541842775723316" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -38,7 +38,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="512964616103659477" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="50541842775723316" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

RTD/include/Flexio_Spi_Ip.h

@@ -0,0 +1,317 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_H
+#define FLEXIO_SPI_IP_H
+
+/**
+*   @file     Flexio_Spi_Ip.h
+*
+*   @brief   FLEXIO_SPI IP driver header file.
+*   @details FLEXIO_SPI IP driver header file.
+
+*   @addtogroup FLEXIO_SPI_DRIVER  Flexio_Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Flexio_Spi_Ip_Types.h"
+#ifdef FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT
+#include "Mcal.h"
+#endif
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_VENDOR_ID                       43
+#define FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION        4
+#define FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION        4
+#define FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION     0
+#define FLEXIO_SPI_IP_SW_MAJOR_VERSION                1
+#define FLEXIO_SPI_IP_SW_MINOR_VERSION                0
+#define FLEXIO_SPI_IP_SW_PATCH_VERSION                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Flexio_Spi_Ip.h and Flexio_Spi_Ip_Types.h are of the same vendor */
+#if (FLEXIO_SPI_IP_VENDOR_ID != FLEXIO_SPI_IP_TYPES_VENDOR_ID)
+    #error "Flexio_Spi_Ip.h and Flexio_Spi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if Flexio_Spi_Ip.h file and Flexio_Spi_Ip_Types.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION    != FLEXIO_SPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION    != FLEXIO_SPI_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION != FLEXIO_SPI_IP_TYPES_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip.h and Flexio_Spi_Ip_Types.h are different"
+#endif
+#if ((FLEXIO_SPI_IP_SW_MAJOR_VERSION != FLEXIO_SPI_IP_TYPES_SW_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_MINOR_VERSION != FLEXIO_SPI_IP_TYPES_SW_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_PATCH_VERSION != FLEXIO_SPI_IP_TYPES_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Flexio_Spi_Ip.h and Flexio_Spi_Ip_Types.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    #ifdef FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT
+        /* Check if Flexio_Spi_Ip.h file and Mcal.h file are of the same Autosar version */
+        #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+             (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip.h and Mcal.h are different"
+        #endif
+    #endif /* FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT */
+#endif
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+    
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/**
+* @brief   Export Post-Build configurations.
+*/
+FLEXIO_SPI_IP_CONFIG_EXT
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h" 
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+/**
+* @brief            FLEXIO_SPI peripheral initialization.
+* @details          The function initialize the SPI Unit specified in the configuration.
+*
+* @param[in]        Configuration -  pointer to the specified SPI Unit configuration.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Initialization command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Initialization command has not been accepted.
+* @implements Flexio_Spi_Ip_Init_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_Init(const Flexio_Spi_Ip_ConfigType *Configuration);
+
+/**
+* @brief            FLEXIO_SPI peripheral deinitialization.
+* @details          The function de-initialize the SPI peripheral instance specified.
+*                   All registers of SPI peripheral will be reset.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: De-initialization command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: De-initialization command has not been accepted.
+* @implements Flexio_Spi_Ip_DeInit_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_DeInit(uint8 Instance);
+
+/**
+* @brief            FLEXIO_SPI synchronous transmission.
+* @details          This function initializes a synchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted.
+* @param[in]        TxBuffer - pointer to transmit buffer.
+* @param[in-out]    RxBuffer - pointer to receive buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        TimeOut - duration for sending one frame.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   FLEXIO_SPI_IP_FIFO_ERROR: Overflow or underflow error occurred.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+*                   FLEXIO_SPI_IP_TIMEOUT: Timeout error occurred.
+*
+* @implements Flexio_Spi_Ip_SyncTransmit_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_SyncTransmit(
+                                                      const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, 
+                                                      uint8 *TxBuffer,
+                                                      uint8 *RxBuffer,
+                                                      uint16 Length,
+                                                      uint32 TimeOut
+                                                   );
+
+/**
+* @brief            FLEXIO_SPI asynchronous transmission.
+* @details          This function initializes an asynchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted
+* @param[in]        TxBuffer - pointer to transmit buffer.
+* @param[in-out]    RxBuffer - pointer to receive buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        Callback - callback function is called at the end of transfer.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+* @implements Flexio_Spi_Ip_AsyncTransmit_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_AsyncTransmit(
+                                       const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice,
+                                       uint8* TxBuffer, 
+                                       uint8* RxBuffer,
+                                       uint16 Length, 
+                                       Flexio_Spi_Ip_CallbackType Callback /* TBD de pus la init/instanta */
+                                      );
+
+/**
+* @brief   Get status of HW unit.
+* @details This function will return status of HW unit assigned.
+*
+* @param[in]      instance            Instance of the hardware unit.
+*
+* @return Flexio_Spi_Ip_HwStatusType
+* @retval FLEXIO_SPI_IP_IDLE           Hardware unit is not used
+* @retval FLEXIO_SPI_IP_BUSY           A transfer is in progress
+* @retval FLEXIO_SPI_IP_FAULT          During last transfer a fault occurred
+* @implements Flexio_Spi_Ip_GetStatus_Activity
+*/
+Flexio_Spi_Ip_HwStatusType Flexio_Spi_Ip_GetStatus(uint8 Instance);
+
+/**
+* @brief            Process transfer in POLLING mode.
+* @details          This function shall polls the SPI interrupts linked to SPI peripheral instance allocated to 
+*                   the transmission of data to enable the evolution of transmission state machine.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return void
+* @implements Flexio_Spi_Ip_ManageBuffers_Activity
+*/
+void Flexio_Spi_Ip_ManageBuffers(uint8 Instance);
+
+/**
+* @brief            FLEXIO_SPI change frame size.
+* @details          This function updates frame size of specific external device configuration for next transfers.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        FrameSize - Frame size.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Flexio_Spi_Ip_UpdateFrameSize_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateFrameSize(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, uint8 FrameSize);
+
+/**
+* @brief            FLEXIO_SPI change bit order.
+* @details          This function updates bits order LSB or MSB of specific external device configuration for next transfer.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        Lsb - Data is transferred LSB first or not.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Flexio_Spi_Ip_UpdateLsb_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateLsb(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, boolean Lsb);
+
+/**
+* @brief            FLEXIO_SPI change default transmit data.
+* @details          This function updates default transmit data of specific external device configuration for next transfer.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        DefaultData - New default transmit data.
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Flexio_Spi_Ip_UpdateDefaultTransmitData_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateDefaultTransmitData(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, uint32 DefaultData);
+
+/**
+* @brief            FLEXIO_SPI change transfer mode.
+* @details          This function updates the asynchronous mechanism mode for the specified SPI Hardware microcontroller peripheral.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+* @param[in]        Mode - new mode (interrupt or polling).
+*
+* @return           FLEXIO_SPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   FLEXIO_SPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Flexio_Spi_Ip_UpdateTransferMode_Activity
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateTransferMode(uint8 Instance, Flexio_Spi_Ip_ModeType Mode);
+
+/**
+* @brief   FLEXIO_SPI cancel current transmission.
+* @details This function will cancel current asynchronous transmission.
+*
+* @param[in]      Instance            Instance of the hardware unit.
+*
+* @implements Flexio_Spi_Ip_Cancel_Activity
+*/
+void Flexio_Spi_Ip_Cancel(uint8 Instance);
+
+#if (FLEXIO_SPI_IP_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   This function will change clock mode.
+* @details This function will change clock mode to operate with other clock reference.
+*
+* @param[in]     Instance            Instance of the hardware unit.
+* @param[in]     ClockMode           Clock mode.
+*
+* @return         An error code or FLEXIO_SPI_IP_STATUS_SUCCESS
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_SetClockMode(uint8 Instance, Flexio_Spi_Ip_DualClockModeType ClockMode);
+#endif
+#if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_IrqTxDmaHandler(uint8 Instance);
+void Flexio_Spi_Ip_IrqRxDmaHandler(uint8 Instance);
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#endif /*FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FLEXIO_SPI_IP_H */
+
+/** @} */
+

RTD/include/Flexio_Spi_Ip_Irq.h

@@ -0,0 +1,100 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_IRQ_H
+#define FLEXIO_SPI_IP_IRQ_H
+
+/**
+*   @file     Flexio_Spi_Ip_Irq.h
+*
+*   @brief   FLEXIO_SPI_IP_IRQ IP driver header file.
+*   @details FLEXIO_SPI_IP_IRQ IP driver header file.
+
+*   @addtogroup FLEXIO_SPI_DRIVER  Flexio_Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_IRQ_VENDOR_ID                       43
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_MAJOR_VERSION        4
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_MINOR_VERSION        4
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_REVISION_VERSION     0
+#define FLEXIO_SPI_IP_IRQ_SW_MAJOR_VERSION                1
+#define FLEXIO_SPI_IP_IRQ_SW_MINOR_VERSION                0
+#define FLEXIO_SPI_IP_IRQ_SW_PATCH_VERSION                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+void Flexio_Spi_Ip_IrqHandler(
+                                uint8 ShifterIndex,
+                                uint8 ShifterMaskFlag,
+                                uint8 ShifterErrMaskFlag
+                              );
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+ 
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FLEXIO_SPI_IP_IRQ_H */
+
+/** @} */
+

RTD/include/Flexio_Spi_Ip_Types.h

@@ -0,0 +1,235 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_TYPES_H
+#define FLEXIO_SPI_IP_TYPES_H
+
+/**
+*   @file     Flexio_Spi_Ip_Types.h
+*
+*   @brief   FLEXIO_SPI_IP_TYPES IP driver types header file.
+*   @details FLEXIO_SPI_IP_TYPES IP driver types header file.
+
+*   @addtogroup FLEXIO_SPI_DRIVER  Flexio_Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Flexio_Spi_Ip_Cfg.h"
+#include "StandardTypes.h"
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_TYPES_VENDOR_ID                       43
+#define FLEXIO_SPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION        4
+#define FLEXIO_SPI_IP_TYPES_AR_RELEASE_MINOR_VERSION        4
+#define FLEXIO_SPI_IP_TYPES_AR_RELEASE_REVISION_VERSION     0
+#define FLEXIO_SPI_IP_TYPES_SW_MAJOR_VERSION                1
+#define FLEXIO_SPI_IP_TYPES_SW_MINOR_VERSION                0
+#define FLEXIO_SPI_IP_TYPES_SW_PATCH_VERSION                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Flexio_Spi_Ip_Types.h and Flexio_Spi_Ip_Cfg.h are of the same vendor */
+#if (FLEXIO_SPI_IP_TYPES_VENDOR_ID != FLEXIO_SPI_IP_VENDOR_ID_CFG)
+    #error "Flexio_Spi_Ip_Types.h and Flexio_Spi_Ip_Cfg.h have different vendor ids"
+#endif
+/* Check if Flexio_Spi_Ip_Types.h file and Flexio_Spi_Ip_Cfg.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_TYPES_AR_RELEASE_MINOR_VERSION    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_TYPES_AR_RELEASE_REVISION_VERSION != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_CFG) \
+    )
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip_Types.h and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+#if ((FLEXIO_SPI_IP_TYPES_SW_MAJOR_VERSION != FLEXIO_SPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_TYPES_SW_MINOR_VERSION != FLEXIO_SPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_TYPES_SW_PATCH_VERSION != FLEXIO_SPI_IP_SW_PATCH_VERSION_CFG) \
+    )
+    #error "Software Version Numbers of Flexio_Spi_Ip_Types.h and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if Flexio_Spi_Ip_Types.h file and StandardTypes.h file are of the same Autosar version */
+    #if ((FLEXIO_SPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (FLEXIO_SPI_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Flexio_Spi_Ip_Types.h and StandardTypes.h are different"
+    #endif
+#endif
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+/** @brief   Enum defining the possible events which triggers end of transfer callback.
+*
+* @implements Flexio_Spi_Ip_EventType_enum
+*/
+typedef enum
+{
+    FLEXIO_SPI_IP_EVENT_END_TRANSFER = 0, /**< The transfer is successfully done. */
+    FLEXIO_SPI_IP_EVENT_FAULT = 1         /**< The transfer failed due to overflow/underflow. */
+} Flexio_Spi_Ip_EventType;
+
+/** @brief   Callback for all peripherals which supports SPI features. */
+typedef void (*Flexio_Spi_Ip_CallbackType)(uint8 Instance,  Flexio_Spi_Ip_EventType Event);
+
+/** @brief   Enum defining the possible transfer modes.
+ * @implements Flexio_Spi_Ip_ModeType_enum
+*/
+typedef enum
+{
+    FLEXIO_SPI_IP_POLLING = 0, /**< For polling mode the application must call periodically Spi_Ip_ManageBuffers after asynchronous transfers. */
+    FLEXIO_SPI_IP_INTERRUPT   /**< For interrupt mode the application doesn't need to perform any additional operations after asynchronous transfers.*/   
+}  Flexio_Spi_Ip_ModeType;
+
+/** @brief   Enum defining the possible states of SPI/DSPI hardware unit.
+ * @implements Flexio_Spi_Ip_HwStatusType_enum
+*/
+typedef enum
+{
+   FLEXIO_SPI_IP_UNINIT = 0u, /**< Module is not initialized. */
+   FLEXIO_SPI_IP_IDLE = 1u,   /**< Module is not used. */
+   FLEXIO_SPI_IP_BUSY = 2u,   /**< A transfer is in progress. */
+   FLEXIO_SPI_IP_FAULT = 3u   /**< During last transfer a fault occurred. */
+}  Flexio_Spi_Ip_HwStatusType;
+
+/** @brief   Enum defining the possible return types. 
+ * @implements Flexio_Spi_Ip_StatusType_enum
+*/
+typedef enum
+{
+   FLEXIO_SPI_IP_STATUS_SUCCESS = 0u, /**< Successful operation. */
+   FLEXIO_SPI_IP_STATUS_FAIL    = 1u, /**< Failed operation. */
+   FLEXIO_SPI_IP_FIFO_ERROR     = 2u, /**< Overflow or underflow error. */
+   FLEXIO_SPI_IP_TIMEOUT        = 3u  /**< Timeout error. */
+}  Flexio_Spi_Ip_StatusType;
+
+#if (FLEXIO_SPI_IP_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   Specifies the Clock Modes.
+*/
+typedef enum
+{
+    FLEXIO_SPI_IP_NORMAL_CLOCK = 0,        /**< @brief Clock reference is from SpiClockRef. */
+    FLEXIO_SPI_IP_ALTERNATE_CLOCK          /**< @brief Clock reference is from SpiAlternateClockRef. */
+}Flexio_Spi_Ip_DualClockModeType;
+#endif
+
+/** @brief   Structure defining some parameters often change of the spi bus. */
+typedef struct  
+{
+   uint8 FrameSize;    /**< Frame size configured */
+   boolean Lsb;    /**< Transfer LSB first or MSB first */
+   uint32 DefaultData;  /**< Default data to send when TxBuffer is NULL_PTR */
+} Flexio_Spi_Ip_DeviceParamsType;
+
+/** @brief   Structure defining the parameters of the spi bus. */
+typedef struct  
+{ 
+    uint8 Instance; /**< Instance of the hardware unit. */
+    uint8 Cpol; 
+    uint8 Cpha; 
+#if (FLEXIO_SPI_IP_DUAL_CLOCK_MODE == STD_ON)
+    uint32 ClkTimeCmpBaudRate[2];
+    uint32 ClkTimeCfgTimDec[2];
+#else
+    uint32 ClkTimeCmpBaudRate;
+    uint32 ClkTimeCfgTimDec;
+#endif
+   uint32 TxShiftCtl;     /**< SHIFTCTL register of TX */
+   uint32 TxShiftCfg;     /**< SHIFTCFG register of TX */
+   uint32 RxShiftCtl;     /**< SHIFTCTL register of RX */
+   uint32 RxShiftCfg;     /**< SHIFTCFG register of RX */
+   uint32 ClkTimeCmp;     /**< TIMCMP register of CLK */
+   uint32 ClkTimeCfg;     /**< TIMCFG register of CLK */
+   uint32 ClkTimeCtl;      /**< TIMCTL register of CLK */
+   uint32 CsTimeCmp;      /**< TIMCMP register of CS */
+   uint32 CsTimeCfg;      /**< TIMCFG register of CS */
+   uint32 CsTimeCtl;      /**< TIMCTL register of CS */
+   Flexio_Spi_Ip_DeviceParamsType * DeviceParams;   /**< Contain configuration for bit order, frame size, default transmit data. */   
+} Flexio_Spi_Ip_ExternalDeviceType;
+
+/** @brief   Structure defining information needed for SPI driver initialization. */
+typedef struct  
+{
+   uint8 Instance; /**< Instance of the hardware unit. */
+#if (FLEXIO_SPI_IP_SLAVE_SUPPORT == STD_ON)
+   boolean SlaveMode;
+#endif    
+#if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+   boolean DmaUsed;        /**< DMA is used or not */
+   uint8   TxDmaChannel;    /**< Id of TX DMA channel for transmition */
+   uint8   RxDmaChannel;    /**< Id of RX DMA channel for receive */
+#endif
+   Flexio_Spi_Ip_ModeType TransferMode; /**< Transfer mode for HWunit */
+   uint32 FrameSize;    /**< Frame size configured */
+   boolean Lsb;    /**< Transfer LSB first or MSB first */
+   uint32 DefaultData;  /**< Default data to send when TxBuffer is NULL_PTR */
+   uint8 TxShifterIndex; /**< No. of shifter for TX */
+   uint8 RxShifterIndex; /**< No. of shifter for RX */
+   uint8 ClkTimerIndex;  /**< No. of timer for CLK */
+   uint8 CsTimerIndex;   /**< No. of timer for CS */
+   uint8 StateIndex; /**< State of current transfer  */
+} Flexio_Spi_Ip_ConfigType;
+
+/** @brief   Structure defining information needed for internal state of the driver. */
+typedef struct
+{
+   #if (FLEXIO_SPI_IP_DUAL_CLOCK_MODE == STD_ON)
+   Flexio_Spi_Ip_DualClockModeType ClockMode; /**< Store current clock mode for HWunit */
+   #endif
+   Flexio_Spi_Ip_ModeType TransferMode; /**< Store current transfer mode for HWunit */
+   boolean FirstChannel; /**< This is the first channel in a job */
+   Flexio_Spi_Ip_HwStatusType Status; /**< 0 = available, 1 = busy, 2 = fail due to overflow or underflow */
+   uint8* RxBuffer;  /**< Store pointer for Rx buffer */
+   uint8* TxBuffer;  /**< Store pointer for Tx buffer */
+   Flexio_Spi_Ip_CallbackType Callback;  /**< Store pointer for call back function */
+   uint16 RxIndex;  /**< Store current Rx index to receive data in Rx buffer */
+   uint16 TxIndex;  /**< Store current Tx index to transmit data in Tx buffer */
+   uint16 ExpectedFifoReads;    /**< Store number of frames needs to be receive for current transfer */
+   uint16 ExpectedFifoWrites;   /**< Store number of frames needs to be transmit for current transfer */
+   const Flexio_Spi_Ip_ConfigType *PhyUnitConfig;  
+   const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice; /**< Store externalDevice */
+} Flexio_Spi_Ip_StateStructureType;
+
+#endif /*(FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*FLEXIO_SPI_IP_TYPES*/
+
+/** @} */

RTD/include/Lpspi_Ip.h

@@ -0,0 +1,441 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef LPSPI_IP_H
+#define LPSPI_IP_H
+
+/**
+*   @file    Lpspi_Ip.h
+*   
+*
+*   @brief   LPSPI IP driver header file.
+*   @details LPSPI IP driver header file.
+
+*   @addtogroup LPSPI_DRIVER Lpspi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Lpspi_Ip_Types.h"
+#ifdef LPSPI_IP_ENABLE_USER_MODE_SUPPORT
+#include "Mcal.h"
+#endif
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define LPSPI_IP_VENDOR_ID                       43
+#define LPSPI_IP_AR_RELEASE_MAJOR_VERSION        4
+#define LPSPI_IP_AR_RELEASE_MINOR_VERSION        4
+#define LPSPI_IP_AR_RELEASE_REVISION_VERSION     0
+#define LPSPI_IP_SW_MAJOR_VERSION                1
+#define LPSPI_IP_SW_MINOR_VERSION                0
+#define LPSPI_IP_SW_PATCH_VERSION                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Lpspi_Ip.h and Lpspi_Ip_Types.h are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID != LPSPI_IP_TYPES_VENDOR_ID)
+    #error "Lpspi_Ip.h and Lpspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if Lpspi_Ip.h file and Lpspi_Ip_Types.h file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION != LPSPI_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION != LPSPI_IP_TYPES_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Lpspi_Ip.h and Lpspi_Ip_Types.h are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION != LPSPI_IP_TYPES_SW_MAJOR_VERSION) || \
+     (LPSPI_IP_SW_MINOR_VERSION != LPSPI_IP_TYPES_SW_MINOR_VERSION) || \
+     (LPSPI_IP_SW_PATCH_VERSION != LPSPI_IP_TYPES_SW_PATCH_VERSION))
+#error "Software Version Numbers of Lpspi_Ip.h and Lpspi_Ip_Types.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Lpspi_Ip.h and Mcal.h are different"
+    #endif
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/**
+* @brief   Export Post-Build configurations.
+*/
+LPSPI_IP_CONFIG_EXT
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+/**
+* @brief            LPSPI peripheral initialization.
+* @details          The function initialize the SPI Unit specified in the configuration.
+*
+* @param[in]        PhyUnitConfigPtr -  pointer to the specified SPI Unit configuration.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Initialization command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Initialization command has not been accepted.
+* @implements Lpspi_Ip_Init_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_Init(const Lpspi_Ip_ConfigType *PhyUnitConfigPtr);
+
+/**
+* @brief            LPSPI peripheral deinitialization.
+* @details          The function de-initialize the SPI peripheral instance specified.
+*                   All registers of SPI peripheral will be reset.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: De-initialization command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: De-initialization command has not been accepted.
+* @implements Lpspi_Ip_DeInit_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_DeInit(uint8 Instance);
+
+
+/**
+* @brief            LPSPI synchronous transmission.
+* @details          This function initializes a synchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted.
+* @param[in]        TxBuffer - pointer to transmit buffer.
+* @param[in-out]    RxBuffer - pointer to receive buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        TimeOut - duration for sending one frame.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   LPSPI_IP_FIFO_ERROR: Overflow or underflow error occurred.
+*                   LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+*                   LPSPI_IP_TIMEOUT: Timeout error occurred.
+*
+* @implements Lpspi_Ip_SyncTransmit_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_SyncTransmit(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *TxBuffer,
+                                            uint8 *RxBuffer,
+                                            uint16 Length,
+                                            uint32 TimeOut
+                                         );
+
+/**
+* @brief            LPSPI asynchronous transmission.
+* @details          This function initializes an asynchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted
+* @param[in]        TxBuffer - pointer to transmit buffer.
+* @param[in-out]    RxBuffer - pointer to receive buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        EndCallback - callback function is called at the end of transfer.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+* @implements Lpspi_Ip_AsyncTransmit_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmit(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *TxBuffer,
+                                            uint8 *RxBuffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_CallbackType EndCallback
+                                          );
+
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+/**
+* @brief            LPSPI synchronous transmission support half duplex mode.
+* @details          This function initializes a synchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted.
+* @param[in]        Buffer - pointer to transmit buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        TimeOut - duration for sending one frame.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   LPSPI_IP_FIFO_ERROR: Overflow or underflow error occurred.
+*                   LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+*                   LPSPI_IP_TIMEOUT: Timeout error occurred.
+*
+* @implements Lpspi_Ip_SyncTransmitHalfDuplex_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_SyncTransmitHalfDuplex(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *Buffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_HalfDuplexType TransferType,
+                                            uint32 TimeOut
+                                         );
+
+/**
+* @brief            LPSPI asynchronous transmission support half duplex mode.
+* @details          This function initializes an asynchronous transfer using the bus parameters provided
+*                   by external device.
+*
+* @param[in]        ExternalDevice - pointer to the external device where data is transmitted
+* @param[in]        Buffer - pointer to transmit buffer.
+* @param[in]        Length - number of bytes to be sent.
+* @param[in]        EndCallback - callback function is called at the end of transfer.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+* @implements Lpspi_Ip_AsyncTransmitHalfDuplex_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmitHalfDuplex(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *Buffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_HalfDuplexType TransferType,
+                                            Lpspi_Ip_CallbackType EndCallback
+                                          );
+#endif
+
+#if (LPSPI_IP_DMA_USED == STD_ON)
+#if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+/**
+* @brief            LPSPI asynchronous transmission fast.
+* @details          This function initializes an asynchronous transmission for multiple transfers session
+*                   and CPU used only for processing at the end of sequence transfer.
+*                   The list of transfers session is composed of an array of fast transfers settings.
+*                   The settings array is defined by the user needs: it contains entries parameters to be configured 
+*                   for each transfer session as defined in Lpspi_Ip_FastTransferType.
+*
+*    How to use this interface:
+*    1. Use the "Lpspi_Ip_FastTransferType" to create a list(array) of transfer session.
+*    Each field in Lpspi_Ip_FastTransferType for each transfer session must be configured.
+*    Note: This feature requires:
+*        a. The parameters SpiBaudrate, SpiHwUnit, SpiTimeClk2Cs, SpiTimeCs2Clk, SpiTimeCs2Cs, SpiDataWidth, SpiTransferStart in all External Devices used(pointed by ExternalDevice) must be the same in each transfer session.
+*        b. In each transfer section, the number of data buffer(Length) is NOT higher than 32767 if SpiDataWidth < 9.
+*        c. Only Master mode is supported(SpiPhyUnit/SpiPhyUnitMode = SPI_MASTER).
+*        d. Make sure that SpiPhyUnit/SpiMaxDmaFastTransfer value must NOT lower than total of transfer sessions.
+*        e. Make sure that number of ScatterGathers configuration in SpiPhyUnit/SpiPhyTxDmaChannel must NOT lower than 
+*        total of transfer sessions plus number of time request CS de-assert(KeepCs = FALSE) at the end of transfer session in the list configured.
+*        f. Make sure that number of ScatterGathers configuration in each SpiPhyUnit/SpiPhyRxDmaChannel must NOT lower than total of transfer sessions.
+*    2. Call the "Lpspi_Ip_AsyncTransmitFast()" interface.
+*    
+*    Example:
+*        The user shall create the desired configuration list for his specific application.
+*        For example use case:
+*        - Requiring 2 transfers session, keep CS assert at the end of first transfer session.
+*        - Transfer session 1: 
+*            + Use SpiExternalDevice_0 with SpiCsIdentifier = PCS0, SpiCsContinous = TRUE.
+*            + Send 5 bytes. Tx buffer is "uint8 u8TxBuffer1[5u]={0,1,2,3,4};". Rx buffer is "uint8 u8RxBuffer1[5u];".
+*            + Keep CS assert at the end of this transfer session.
+*        - Transfer session 2: 
+*            + Use SpiExternalDevice_0 with SpiCsIdentifier = PCS0, SpiCsContinous = TRUE.
+*            + Send 10 bytes with default transmit data value is 5. Tx buffer is NULL_PTR. Rx buffer is "uint8 u8RxBuffer2[10u];".
+*            + This is last transfer session, so CS will not kipped by default at the end of last transfer session.
+*        - Configuration example on configuration tool:
+*            + SpiGeneral/SpiEnableDmaFastTransferSupport = true.
+*            + SpiPhyUnit/SpiMaxDmaFastTransfer = 2(2 transfers session).
+*            + Number of ScatterGathers configuration for SpiPhyTxDmaChannel is 3(2 transfers session + 1 time CS de-assert at the end of last transfer session).
+*            + Number of ScatterGathers configuration for SpiPhyRxDmaChannel is 2(2 transfers session).
+*        - Call "UserCallbackFunc" when Fast transfer completed.
+*        - Coding example:
+*            void UserCallbackFunc(uint8 Instance, Lpspi_Ip_EventType event);
+*            Lpspi_Ip_FastTransferType aUserFastTransferCfgList[2u] =
+*            {
+*                {
+*                    Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals, ->Point to External Device 0 configuration generated by configuration tool
+*                    u8TxBuffer1, -> Store pointer for Tx buffer
+*                    u8RxBuffer1, -> Store pointer for Rx buffer
+*                    0u, -> Default transmit data, don't care due to Tx buffer is not NULL_PTR
+*                    5u, -> Number of bytes to be sent
+*                    (boolean)TRUE -> Keep CS signal at the end of this transfer session
+*                },
+*                {
+*                    Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_BOARD_InitPeripherals, -> Point to external device configuration
+*                    NULL_PTR, -> Store pointer for Tx buffer
+*                    u8RxBuffer2, -> Store pointer for Rx buffer
+*                    5u, -> Default transmit data, don't care due to Tx buffer is not NULL_PTR
+*                    10u, -> Number of bytes to be sent
+*                    (boolean)FALSE -> Not keep CS signal at the end of this transfer session, don't care this parameter for last transfer
+*                }
+*            };
+*            Lpspi_Ip_AsyncTransmitFast(aUserFastTransferCfgList, 2u, &UserCallbackFunc);
+*            
+* @param[in-out]    pFastTransferCfg - pointer to the list of transfers section configuration.
+* @param[in]        u16NumberOfTransfer - number of transfers session in the list is pointed by pFastTransferCfg.
+* @param[in]        EndCallback - callback function is called at the end of sequence transfer.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Transmission command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+* @implements Lpspi_Ip_AsyncTransmitFast_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmitFast(
+                                       const Lpspi_Ip_FastTransferType *FastTransferCfg,
+                                       uint8 NumberOfTransfer,
+                                       Lpspi_Ip_CallbackType EndCallback
+                                      );
+#endif
+#endif
+
+/**
+* @brief            Get status of HW unit.
+* @details          This function returns the status of the specified SPI Hardware microcontroller peripheral.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return           Lpspi_Ip_HwStatusType
+* @implements Lpspi_Ip_GetStatus_Activity
+*/
+Lpspi_Ip_HwStatusType Lpspi_Ip_GetStatus(uint8 Instance);
+
+/**
+* @brief            Process transfer in POLLING mode.
+* @details          This function shall polls the SPI interrupts linked to SPI peripheral instance allocated to 
+*                   the transmission of data to enable the evolution of transmission state machine.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return void
+* @implements Lpspi_Ip_ManageBuffers_Activity
+*/
+void Lpspi_Ip_ManageBuffers(uint8 Instance);
+
+/**
+* @brief            LPSPI change frame size.
+* @details          This function updates frame size of specific external device configuration for next transfers.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        FrameSize - Frame size.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Lpspi_Ip_UpdateFrameSize_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateFrameSize(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, uint8 FrameSize);
+
+/**
+* @brief            LPSPI change bit order.
+* @details          This function updates bits order LSB or MSB of specific external device configuration for next transfer.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        Lsb - Data is transferred LSB first or not.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Lpspi_Ip_UpdateLsb_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateLsb(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, boolean Lsb);
+
+/**
+* @brief            LPSPI change default transmit data.
+* @details          This function updates default transmit data of specific external device configuration for next transfer.
+*
+* @param[in]        ExternalDevice - pointer to the external device configuration.
+* @param[in]        DefaultData - New default transmit data.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Lpspi_Ip_UpdateDefaultTransmitData_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateDefaultTransmitData(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, uint32 DefaultData);
+
+/**
+* @brief            LPSPI change transfer mode.
+* @details          This function updates the asynchronous mechanism mode for the specified SPI Hardware microcontroller peripheral.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+* @param[in]        Mode - new mode (interrupt or polling).
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Setting command has not been accepted.
+* @implements Lpspi_Ip_UpdateTransferMode_Activity
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode);
+
+/**
+* @brief            LPSPI cancel current asynchronous transmission.
+* @details          This function cancels an asynchronous transmission in progress for the specified SPI Hardware microcontroller peripheral.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+*
+* @return void
+* @implements Lpspi_Ip_Cancel_Activity
+*/
+void Lpspi_Ip_Cancel(uint8 Instance);
+
+#if (LPSPI_IP_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief            Change clock mode.
+* @details          This function will change clock mode to operate with other clock reference.
+*
+* @param[in]        Instance - SPI peripheral instance number.
+* @param[in]        ClockMode           Clock mode.
+*
+* @return           LPSPI_IP_STATUS_SUCCESS: Setting command has been accepted.
+*                   LPSPI_IP_STATUS_FAIL: Setting command has not been accepted.
+*/
+Lpspi_Ip_StatusType Lpspi_Ip_SetClockMode(uint8 Instance, Lpspi_Ip_DualClockModeType ClockMode);
+#endif
+
+void Lpspi_Ip_IrqHandler(uint8 Instance);
+#if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_IrqTxDmaHandler(uint8 Instance);
+void Lpspi_Ip_IrqRxDmaHandler(uint8 Instance);
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPSPI_IP_H */
+
+/** @} */
+

RTD/include/Lpspi_Ip_Types.h

@@ -0,0 +1,300 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_IP_TYPES_H
+#define SPI_IP_TYPES_H
+
+/**
+*   @file    Lpspi_Ip_Types.h
+*
+*   @brief   LPSPI IP driver types header file.
+*   @details LPSPI IP driver types header file.
+
+*   @addtogroup LPSPI_DRIVER Lpspi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "StandardTypes.h"
+#include "Lpspi_Ip_Cfg.h"
+
+/*==================================================================================================
+*                                 SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define LPSPI_IP_TYPES_VENDOR_ID                    43
+#define LPSPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION     4
+#define LPSPI_IP_TYPES_AR_RELEASE_MINOR_VERSION     4
+#define LPSPI_IP_TYPES_AR_RELEASE_REVISION_VERSION  0
+#define LPSPI_IP_TYPES_SW_MAJOR_VERSION             1
+#define LPSPI_IP_TYPES_SW_MINOR_VERSION             0
+#define LPSPI_IP_TYPES_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                       FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and StandardTypes header file are of the same Autosar version */
+    #if ((LPSPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_TYPES_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Lpspi_Ip_Types.h and StandardTypes.h are different"
+    #endif
+#endif
+
+/* Check if Lpspi_Ip_Types.h header file and Lpspi_Ip_Cfg.h configuration header file are of the same vendor */
+#if (LPSPI_IP_TYPES_VENDOR_ID != LPSPI_IP_VENDOR_ID_CFG)
+    #error "Lpspi_Ip_Types.h and Lpspi_Ip_Cfg.h have different vendor IDs"
+#endif
+    /* Check if Lpspi_Ip_Types.h header file and Lpspi_Ip_Cfg.h  configuration header file are of the same Autosar version */
+#if ((LPSPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (LPSPI_IP_TYPES_AR_RELEASE_MINOR_VERSION != LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (LPSPI_IP_TYPES_AR_RELEASE_REVISION_VERSION != LPSPI_IP_AR_RELEASE_REVISION_VERSION_CFG))
+#error "AutoSar Version Numbers of Lpspi_Ip_Types.h and Lpspi_Ip_Cfg.h are different"
+#endif
+/* Check if Lpspi_Ip_Types.h header file and Lpspi_Ip_Cfg.h configuration header file are of the same software version */
+#if ((LPSPI_IP_TYPES_SW_MAJOR_VERSION != LPSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (LPSPI_IP_TYPES_SW_MINOR_VERSION != LPSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (LPSPI_IP_TYPES_SW_PATCH_VERSION != LPSPI_IP_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Lpspi_Ip_Types.h and Lpspi_Ip_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                                            CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                              ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                  STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/** @brief   Enum defining the possible events which triggers end of transfer callback. 
+*
+* @implements Lpspi_Ip_EventType_enum
+*/
+typedef enum
+{
+    LPSPI_IP_EVENT_END_TRANSFER = 0, /**< The transfer is successfully done. */
+    LPSPI_IP_EVENT_FAULT = 1         /**< The transfer failed due to overflow/underflow. */
+} Lpspi_Ip_EventType;
+
+/** @brief   Callback for all peripherals which supports SPI features. */
+typedef void (*Lpspi_Ip_CallbackType)(uint8 Instance, Lpspi_Ip_EventType event);
+
+/** @brief   Enum defining the possible transfer modes.
+* @implements Lpspi_Ip_ModeType_enum
+*/
+typedef enum
+{
+    LPSPI_IP_POLLING = 0, /**< For polling mode the application must call periodically Spi_Ip_ManageBuffers after asynchronous transfers. */
+    LPSPI_IP_INTERRUPT   /**< For interrupt mode the application doesn't need to perform any additional operations after asynchronous transfers.
+                            The application must enable the interrupt requests and install the right callbacks. */
+} Lpspi_Ip_ModeType;
+
+/** @brief   Enum defining the possible states of SPI/DSPI hardware unit.
+* @implements Lpspi_Ip_HwStatusType_enum
+*/
+typedef enum
+{
+   LPSPI_IP_UNINIT = 0u, /**< Module is not initialized. */
+   LPSPI_IP_IDLE = 1u, /**< Module is not used. */
+   LPSPI_IP_BUSY = 2u,   /**< A transfer is in progress. */
+   LPSPI_IP_FAULT = 3u   /**< During last transfer a fault occurred. */
+} Lpspi_Ip_HwStatusType;
+
+/** @brief   Enum defining the possible return types. 
+* @implements Lpspi_Ip_StatusType_enum
+*/
+typedef enum
+{
+   LPSPI_IP_STATUS_SUCCESS = 0u, /**< Successful operation. */
+   LPSPI_IP_STATUS_FAIL    = 1u, /**< Failed operation. */
+   LPSPI_IP_FIFO_ERROR     = 2u, /**< Overflow or underflow error. */
+   LPSPI_IP_TIMEOUT        = 3u  /**< Timeout error. */
+} Lpspi_Ip_StatusType;
+
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+/** @brief   Enum defining the half duplex types. 
+*/
+typedef enum
+{
+   LPSPI_IP_HALF_DUPLEX_TRANSMIT   = 0u, /**< Transmit only. */
+   LPSPI_IP_HALF_DUPLEX_RECEIVE    = 1u, /**< Receive only. */
+   LPSPI_IP_FULL_DUPLEX                 = 2u /**< Full duplex mode. */
+} Lpspi_Ip_HalfDuplexType;
+#endif
+
+/** @brief   Structure defining some parameters often change of the spi bus. */
+typedef struct  
+{
+   uint8 FrameSize;    /**< Frame size configured */
+   boolean Lsb;    /**< Transfer LSB first or MSB first */
+   uint32 DefaultData;  /**< Default data to send when TxBuffer is NULL_PTR */
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+   Lpspi_Ip_HalfDuplexType TransferType;    /**< TransferType */
+#endif
+} Lpspi_Ip_DeviceParamsType;
+
+/** @brief   Structure defining the parameters of the spi bus. */
+typedef struct
+{
+   uint8 Instance; /**< Instance of the hardware unit. */
+   #if (LPSPI_IP_DUAL_CLOCK_MODE == STD_ON)
+   uint32 Ccr[2u];     /**< CCR register which contains clocking and frame size configuration. */
+   uint32 Tcr[2u];     /**< TCR register which contains clock polarities, frame size, which PCS and continuous mode. */
+   #else
+   uint32 Ccr;     /**< CCR register which contains clocking and frame size configuration. */
+   uint32 Tcr;     /**< TCR register which contains clock polarities, frame size, which PCS and continuous mode. */
+   #endif
+   #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+   uint32 HalfDuplexCfgr1;  /**< CFGR1 register which contains bit fields to support half duplex mode . */
+   #endif
+   Lpspi_Ip_DeviceParamsType * DeviceParams;   /**< Contain configuration for bit order, frame size, default transmit data. */
+} Lpspi_Ip_ExternalDeviceType;
+
+#if (LPSPI_IP_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   Specifies the Clock Modes.
+*/
+typedef enum
+{
+    LPSPI_IP_NORMAL_CLOCK = 0,        /**< @brief Clock reference is from SpiClockRef. */
+    LPSPI_IP_ALTERNATE_CLOCK          /**< @brief Clock reference is from SpiAlternateClockRef. */
+}Lpspi_Ip_DualClockModeType;
+#endif
+
+#if (LPSPI_IP_DMA_USED == STD_ON)
+#if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+/** @brief   Structure defining transmition command needed for Dma Fast transfer. */
+typedef struct  
+{ 
+   uint32 DmaFastTcrCmd;   /**< Contains transfer command for Dma Fast transfer. */
+   uint32 DmaFastTcrCmdLast;   /**< Contains transfer command  and disable continuos mode for Dma Fast transfer. */
+   uint32 DefaultData;  /**< Default data to send when TxBuffer is NULL_PTR */
+} Lpspi_Ip_CmdDmaFastType;
+
+/** @brief   Structure defining information needed for Dma Fast transfer session.
+ * @implements Lpspi_Ip_FastTransferType_struct
+ */
+typedef struct  
+{
+    const Lpspi_Ip_ExternalDeviceType *ExternalDevice; /**< Point to external device configuration */
+    uint8* TxBuffer;  /**< Store pointer for Tx buffer */
+    uint8* RxBuffer;  /**< Store pointer for Rx buffer */
+    uint32 DefaultData;  /**< Default data to send when TxBuffer is NULL_PTR */
+    uint16 Length;  /**< Number of bytes to be sent */
+    boolean KeepCs;  /**< Keep CS signal after transfer session completed */
+} Lpspi_Ip_FastTransferType;
+#endif
+#endif
+
+/** @brief   Structure defining information needed for SPI driver initialization. */
+typedef struct
+{
+   uint8 Instance; /**< Instance of the hardware unit. */
+   uint32  Cr;     /**< It contains only debug enable. */
+   uint32  Cfgr1;  /**< It contains PCS polarities. */
+   #if (LPSPI_IP_SLAVE_SUPPORT == STD_ON)
+   boolean SlaveMode;
+   #endif
+   #if (LPSPI_IP_DMA_USED == STD_ON)
+   boolean DmaUsed;    /**< DMA is used or not */
+   uint8   TxDmaChannel;    /**< Id of TX DMA channel for transmition */
+   uint8   RxDmaChannel;    /**< Id of RX DMA channel for receive */
+   #if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+   uint8 MaxNumOfFastTransfer; /**< Maximum number of transfers in Dma Fast */
+   Lpspi_Ip_CmdDmaFastType *CmdDmaFast; /**< Point to list of TCR command used in Dma Fast transfer */
+   uint8 NumberTxSG; /**< Number of TCD Scatter Gather for Tx DMA channel used in Dma Fast transfer */
+   uint8 NumberRxSG; /**< Number of TCD Scatter Gather for Rx DMA channel used in Dma Fast transfer */
+   const uint8 *TxDmaFastSGId; /**< Point to list of TCD Scatter Gather Id for Tx DMA channel used in Dma Fast transfer */
+   const uint8 *RxDmaFastSGId; /**< Point to list of TCD Scatter Gather Id for Rx DMA channel used in Dma Fast transfer */
+   #endif
+   #endif
+   Lpspi_Ip_ModeType TransferMode; /**< Transfer mode for HWunit */
+   uint8 StateIndex; /**< State of current transfer  */
+} Lpspi_Ip_ConfigType;
+
+/** @brief   Structure defining information needed for internal state of the driver. */
+typedef struct
+{
+   #if (LPSPI_IP_DUAL_CLOCK_MODE == STD_ON)
+   Lpspi_Ip_DualClockModeType ClockMode; /**< Store current clock mode for HWunit */
+   #endif
+   Lpspi_Ip_ModeType TransferMode; /**< Store current transfer mode for HWunit */
+   Lpspi_Ip_HwStatusType Status; /**< 0 = available, 1 = busy, 2 = fail due to overflow or underflow */
+   uint8* RxBuffer;  /**< Store pointer for Rx buffer */
+   uint8* TxBuffer;  /**< Store pointer for Tx buffer */
+   Lpspi_Ip_CallbackType Callback;  /**< Store pointer for call back function */
+   uint16 RxIndex;  /**< Store current Rx index to receive data in Rx buffer */
+   uint16 TxIndex;  /**< Store current Tx index to transmit data in Tx buffer */
+   uint16 ExpectedFifoReads;    /**< Store number of frames needs to be receive for current transfer */
+   uint16 ExpectedFifoWrites;   /**< Store number of frames needs to be transmit for current transfer */
+   boolean KeepCs;   /**< Keep CS signal after tranfers completed. */
+   boolean FirstCmd;
+   const Lpspi_Ip_ConfigType *PhyUnitConfig;
+   const Lpspi_Ip_ExternalDeviceType *ExternalDevice;
+   uint8 TxFrameSize; /**< Store current frame size for HWunit */
+   boolean TxLsb;   /**< Transfer LSB first or MSB first */
+   uint8* TxBufferNext;  /**< Store pointer for Tx buffer */
+   uint8 FrameSizeNext; /**< Store current frame size for HWunit */
+   boolean LsbNext;   /**< Transfer LSB first or MSB first */
+   uint32 DefaultDataNext;  /**< Default data to send when TxBuffer is NULL_PTR */
+   uint16 LengthNext;   /**< Store number of frames needs to be transmit for current transfer */
+   boolean NextTransferConfigAvailable;   /**< Flag to check next transfer configuration is available */
+   boolean NextTransferDone;   /**< Flag to check next transfer done */
+   uint8 CurrentTxFifoSlot;   /**< Number of TX FIFO slots are current available. */
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+   uint32 HalfDuplexTcrCommand;   /**< Save the value which will be written to TCR register in DMA mode */
+   boolean NextChannelIsRX;   /**< Save the value which will be written to TCR register in DMA mode */
+#endif
+   boolean TxDoneFlag;   /**< Flag to check TX is done */
+} Lpspi_Ip_StateStructureType;
+
+/*==================================================================================================
+*                                  GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*LPSPI_IP_TYPES*/
+
+/** @} */

RTD/include/SchM_Spi.h

@@ -0,0 +1,184 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : 
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SCHM_SPI_H
+#define SCHM_SPI_H
+
+/**
+*   @file
+*
+*   @addtogroup RTE_MODULE
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SCHM_SPI_AR_RELEASE_MAJOR_VERSION     4
+#define SCHM_SPI_AR_RELEASE_MINOR_VERSION     4
+#define SCHM_SPI_AR_RELEASE_REVISION_VERSION  0
+#define SCHM_SPI_SW_MAJOR_VERSION             1
+#define SCHM_SPI_SW_MINOR_VERSION             0
+#define SCHM_SPI_SW_PATCH_VERSION             0
+
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                           CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                     FUNCTION PROTOTYPES
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+/*==================================================================================================
+*                                           CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+/* Number of cores id */
+#define NUMBER_OF_CORES         (uint8)(1U)
+
+#ifdef MCAL_TESTING_ENVIRONMENT
+/** 
+@brief   This function checks that all entered exclusive areas were also exited. 
+@details This function checks that all entered exclusive areas were also exited. The check
+         is done by verifying that all reentry_guard_* static variables are back to the
+         zero value.
+    
+@param[in]     void       No input parameters
+@return        void       This function does not return a value. Test asserts are used instead. 
+
+@pre  None
+@post None
+
+@remarks Covers 
+@remarks Implements 
+*/
+void SchM_Check_spi(void);
+#endif /*MCAL_TESTING_ENVIRONMENT*/
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void);
+
+extern void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void);
+extern void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void);
+
+
+void Spi_MainFunction_Handling(void);
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+#endif /* SCHM_SPI_H */

RTD/include/Spi.h

@@ -0,0 +1,1232 @@
+/**
+*   @file    Spi.h
+*   
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi driver header file.
+*   @details AUTOSAR specific Spi driver header file.
+
+*   @addtogroup SPI_DRIVER Spi Driver
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_H
+#define SPI_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "StandardTypes.h"
+#include "Mcal.h"
+#include "Spi_Cfg.h"
+#include "Spi_IPW_Types.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_MODULE_ID                    83
+#define SPI_VENDOR_ID                    43
+#define SPI_AR_RELEASE_MAJOR_VERSION     4
+#define SPI_AR_RELEASE_MINOR_VERSION     4
+#define SPI_AR_RELEASE_REVISION_VERSION  0
+#define SPI_SW_MAJOR_VERSION             1
+#define SPI_SW_MINOR_VERSION             0
+#define SPI_SW_PATCH_VERSION             0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/* Check if this header file and Spi_Cfg.h are of the same vendor */
+#if (SPI_VENDOR_ID != SPI_VENDOR_ID_CFG)
+    #error "Spi.h and Spi_Cfg.h have different vendor ids"
+#endif
+/* Check if source file and SPI header file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION != SPI_AR_RELEASE_MAJOR_VERSION_CFG) || \
+   (SPI_AR_RELEASE_MINOR_VERSION != SPI_AR_RELEASE_MINOR_VERSION_CFG) || \
+   (SPI_AR_RELEASE_REVISION_VERSION != SPI_AR_RELEASE_REVISION_VERSION_CFG))
+  #error "AutoSar Version Numbers of Spi.h and Spi_Cfg.h are different"
+#endif
+/* Check if current file and Spi_Cfg header file are of the same Software version */
+#if ((SPI_SW_MAJOR_VERSION != SPI_SW_MAJOR_VERSION_CFG) || \
+     (SPI_SW_MINOR_VERSION != SPI_SW_MINOR_VERSION_CFG) || \
+     (SPI_SW_PATCH_VERSION != SPI_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Spi.h and Spi_Cfg.h are different"
+#endif
+
+/* Check if this header file and Spi_IPW_Types.h are of the same vendor */
+#if (SPI_VENDOR_ID != SPI_IPW_TYPES_VENDOR_ID)
+    #error "Spi.h and Spi_IPW_Types.h have different vendor ids"
+#endif
+/* Check if current file and Spi_IPW_Types header file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION != SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_AR_RELEASE_MINOR_VERSION != SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_AR_RELEASE_REVISION_VERSION != SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi.h and Spi_IPW_Types.h are different"
+#endif
+  /* Check if current file and Spi_IPW_Types header file are of the same Software version */
+#if ((SPI_SW_MAJOR_VERSION != SPI_IPW_TYPES_SW_MAJOR_VERSION) || \
+     (SPI_SW_MINOR_VERSION != SPI_IPW_TYPES_SW_MINOR_VERSION) || \
+     (SPI_SW_PATCH_VERSION != SPI_IPW_TYPES_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi.h and Spi_IPW_Types.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and StandardTypes header file are of the same Autosar version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
+         (SPI_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi.h and StandardTypes.h are different"
+    #endif
+    
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (SPI_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi.h and Mcal.h are different"
+    #endif
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+#define SPI_PHYUNIT_ASYNC_U32       ((uint32)0u)
+
+/** @brief Define state of hardware unit for synchronous transmission. */
+#define SPI_PHYUNIT_SYNC_U32       ((uint32)1u)
+
+/* Error Values */
+/**
+* @brief API service called with wrong parameter of Channel.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_CHANNEL       ((uint8)0x0Au)
+/**
+* @brief API service called with wrong parameter of Job.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_JOB           ((uint8)0x0Bu)
+/**
+* @brief API service called with wrong parameter of Sequence.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_SEQ           ((uint8)0x0Cu)
+/**
+* @brief API service called with wrong parameter of external buffer length.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_LENGTH        ((uint8)0x0Du)
+/**
+* @brief API service called with wrong parameter of HWUnit.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_UNIT          ((uint8)0x0Eu)
+/**
+* @brief API service called with wrong resource assigned.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_CONFIG        ((uint8)0x0Fu)
+/**
+* @brief API service used without module initialization.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_UNINIT              ((uint8)0x1Au)
+/**
+* @brief Services called in a wrong sequence.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_SEQ_PENDING         ((uint8)0x2Au)
+/**
+* @brief Synchronous transmission service called at wrong time.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_SEQ_IN_PROCESS      ((uint8)0x3Au)
+/**
+* @brief API SPI_Init service called while the SPI driver has already been initialized.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_ALREADY_INITIALIZED ((uint8)0x4Au)
+
+/**
+* @brief   The number of sequences, jobs or channels exceeds precompile time sizes.
+* @details The number of sequences, jobs or channels in the configuration
+*          exceeds precompile time related sizes:
+*          SPI_MAX_SEQUENCE, SPI_MAX_JOB or SPI_MAX_CHANNEL.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_CONFIG_OUT_OF_RANGE ((uint8)0x5Au)
+
+/**
+* @brief API Spi_Init was called with wrong configuration pointer.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_INIT_FAILED              ((uint8)0x6Au)
+
+/**
+* @brief   When a sequence contains uninitialized external buffers.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_EB_UNIT       ((uint8)0x5Bu)
+
+/**
+* @brief   No job in sequence.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_SEQ_EMPTY           ((uint8)0x5Cu)
+
+/**
+* @brief   No channel in job.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_JOB_EMPTY           ((uint8)0x5Du)
+/**
+* @brief   If the parameter versioninfo or Spi configuration is NULL_PTR.
+*
+*/
+/** @implements Spi_ErrorCodes_define  */
+#define SPI_E_PARAM_POINTER           ((uint8)0x10u)
+
+#define SPI_CHANNEL_FLAG_TX_DEFAULT_U8 ((uint8) 0x01u)
+#define SPI_CHANNEL_FLAG_RX_DISCARD_U8 ((uint8) 0x02u)
+
+#define SPI_E_INVALID_POINTER ((uint8)0x6Fu)
+
+#define SPI_E_HWUNIT_BUSY ((uint8)0x7Fu)
+
+
+    /* Service IDs */
+/**
+* @brief API service ID for SPI Init function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_INIT_ID              ((uint8) 0x00u)
+/**
+* @brief API service ID for SPI DeInit function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_DEINIT_ID            ((uint8) 0x01u)
+/**
+* @brief API service ID for SPI write IB function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_WRITEIB_ID           ((uint8) 0x02u)
+/**
+* @brief API service ID for SPI async transmit function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_ASYNCTRANSMIT_ID     ((uint8) 0x03u)
+/**
+* @brief API service ID for SPI read IB function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define */
+#define SPI_READIB_ID            ((uint8) 0x04u)
+/**
+* @brief API service ID for SPI setup EB function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_SETUPEB_ID           ((uint8) 0x05u)
+/**
+* @brief API service ID for SPI get status function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_GETSTATUS_ID         ((uint8) 0x06u)
+/**
+* @brief API service ID for SPI get job result function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_GETJOBRESULT_ID      ((uint8) 0x07u)
+/**
+* @brief API service ID for SPI get sequence result function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_GETSEQUENCERESULT_ID ((uint8) 0x08u)
+/**
+* @brief API service ID for SPI get version info function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_GETVERSIONINFO_ID    ((uint8) 0x09u)
+/**
+* @brief API service ID for SPI sync transmit function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_SYNCTRANSMIT_ID      ((uint8) 0x0Au)
+/**
+* @brief API service ID for SPI get hwunit status function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_GETHWUNITSTATUS_ID   ((uint8) 0x0Bu)
+/**
+* @brief API service ID for SPI cancel function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_CANCEL_ID            ((uint8) 0x0Cu)
+/**
+* @brief API service ID for SPI set async mode function.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_SETASYNCMODE_ID      ((uint8) 0x0Du)
+/**
+* @brief API service ID for SPI main function
+* @details Parameters used when raising an error or exception
+*
+* @implements Spi_ServiceIds_define
+*/
+#define SPI_MAINFUNCTION_HANDLING_ID  ((uint8)0x10u)
+/**
+* @brief API service ID for SPI set HW Unit async mode.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define */
+#define SPI_SETHWUNITASYNCMODE_ID  ((uint8)0x80u)
+/**
+* @brief API service ID for SPI Set Clock Mode.
+* @details Parameters used when raising an error or exception.
+*
+*/
+/** @implements Spi_ServiceIds_define  */
+#define SPI_SETCLOCKMODE_ID  ((uint8)0x81u)
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief   The number of allowed job priority levels (0..3).
+* @details The Priority has to be sint8.
+*
+*/
+#define SPI_JOB_PRIORITY_LEVELS_COUNT    (4)
+#endif /* ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)) */
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+/**
+* @brief   This type defines a range of specific status for SPI Driver.
+*
+* @implements Spi_StatusType_enum
+*/
+typedef enum
+{
+    SPI_UNINIT = 0,          /**< @brief Not initialized or not usable. */
+    SPI_IDLE,                /**< @brief Not currently transmitting any jobs. */
+    SPI_BUSY                 /**< @brief Is performing a SPI Job(transmit). */
+} Spi_StatusType;
+
+/**
+* @brief   This type defines a range of specific Jobs status for SPI Driver.
+*
+* @implements Spi_JobResultType_enum
+*/
+typedef enum
+{
+    SPI_JOB_OK = 0,     /**< @brief The last transmission of the Job has been finished successfully. */
+    SPI_JOB_PENDING,    /**< @brief The SPI handler/Driver is performing a SPI Job. */
+    SPI_JOB_FAILED,     /**< @brief The last transmission of the Job has failed. */
+    SPI_JOB_QUEUED      /**< @brief An asynchronous transmit Job has been accepted, while actual
+                                     transmission for this Job has not started yet. */
+} Spi_JobResultType;
+
+/**
+* @brief   This type defines a range of specific Sequences status for SPI Driver.
+*
+* @implements Spi_SeqResultType_enum
+*/
+typedef enum
+{
+    SPI_SEQ_OK = 0,         /**< @brief The last transmission of the Sequence has been finished successfully. */
+    SPI_SEQ_PENDING,        /**< @brief The SPI handler/Driver is performing a SPI Sequence. */
+    SPI_SEQ_FAILED,         /**< @brief The last transmission of the Sequence has failed. */
+    SPI_SEQ_CANCELLED       /**< @brief The last transmission of the Sequence has been cancelled by the user. */
+} Spi_SeqResultType;
+
+/**
+* @brief   The enumeration containing the designated values for buffer types (internal or external).
+*
+*/
+typedef enum
+{
+    IB = 0,     /**< @brief The Channel is configured using Internal Buffer. */
+    EB          /**< @brief The Channel is configured using External Buffer. */
+} Spi_BufferType;
+
+/**
+* @brief   Specifies the asynchronous mechanism mode for SPI buses handled asynchronously in Level 2
+* @details #if (LEVEL2 == SPI_LEVEL_DELIVERED)
+*            Specifies the asynchronous mechanism mode for SPI buses handled
+*            asynchronously in LEVEL 2. SPI150: This type is available or not
+*           according to the pre compile time parameter:
+*            SPI_LEVEL_DELIVERED. This is only relevant for LEVEL 2.
+*
+* @implements Spi_AsyncModeType_enum
+*/
+typedef enum
+{
+    /** @brief The asynchronous mechanism is ensured by polling, so interrupts
+       related to SPI buses handled asynchronously are disabled. */
+    SPI_POLLING_MODE = 0,
+    /** @brief The asynchronous mechanism is ensured by interrupt, so interrupts
+       related to SPI buses handled asynchronously are enabled. */
+    SPI_INTERRUPT_MODE
+} Spi_AsyncModeType;
+
+#if (SPI_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   Specifies the Clock Modes.
+*
+* @implements Spi_DualClockMode_enum
+*/
+typedef enum
+{
+    SPI_NORMAL = 0,        /**< @brief Clock reference is from SpiClockRef. */
+    SPI_ALTERNATE          /**< @brief Clock reference is from SpiAlternateClockRef. */
+}Spi_DualClockModeType;
+#endif
+
+#ifdef SPI_HALF_DUPLEX_MODE_SUPPORT
+  #if (STD_ON == SPI_HALF_DUPLEX_MODE_SUPPORT)
+/**
+* @brief   Half duplex mode.
+*/
+typedef enum
+{
+    SPI_HALF_DUPLEX_TRANSMIT = 0,        /**< Transmit only. */
+    SPI_HALF_DUPLEX_RECEIVE = 1,          /**< Receive only. */
+    SPI_FULL_DUPLEX = 2                       /**< Full duplex mode. */
+}Spi_HalfDuplexModeType;
+ #endif
+#endif
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*---------------------------------------------------------------------------
+*                 SPI Driver AUTOSAR Related Type Definitions
+-----------------------------------------------------------------------------*/
+/**
+* @brief   Type of application data buffer elements.
+*/
+/**
+* @implements Spi_DataBufferType_typedef
+*/
+typedef uint8 Spi_DataBufferType;
+
+/**
+* @brief   Type for defining the number of data elements of the type Spi_DataBufferType.
+* @details Type for defining the number of data elements of the type Spi_DataBufferType
+*          to send or receive by Channel.
+*
+* @implements Spi_NumberOfDataType_typedef
+*/
+typedef uint16 Spi_NumberOfDataType;
+
+#if (SPI_ALLOW_BIGSIZE_COLLECTIONS == STD_ON)
+
+/**
+* @brief   Specifies the identification (ID) for a Channel.
+*
+* @implements Spi_ChannelType_typedef
+*/
+typedef uint32 Spi_ChannelType;
+
+/**
+* @brief   Specifies the identification (ID) for a Job.
+*
+* @implements Spi_JobType_typedef
+*/
+typedef uint32 Spi_JobType;
+
+/**
+* @brief   Specifies the identification (ID) for a sequence of jobs.
+*
+* @implements Spi_SequenceType_typedef
+*/
+typedef uint32 Spi_SequenceType;
+#else
+
+/**
+* @brief   Specifies the identification (ID) for a Channel.
+*
+* @implements Spi_ChannelType_typedef
+*/
+typedef uint8 Spi_ChannelType;
+
+/**
+* @brief   Specifies the identification (ID) for a Job.
+*
+* @implements Spi_JobType_typedef.
+*/
+typedef uint16 Spi_JobType;
+
+/**
+* @brief   Specifies the identification (ID) for a sequence of jobs.
+*
+* @implements Spi_SequenceType_typedef.
+*/
+typedef uint8 Spi_SequenceType;
+#endif
+
+/**
+* @brief     Specifies the ID for a SPI Hardware microcontroller peripheral unit.
+* @details  This type is used for specifying the identification (ID) for a SPI
+*            Hardware microcontroller peripheral unit.
+*
+* @implements Spi_HWUnitType_typedef
+*/
+typedef uint8 Spi_HWUnitType;
+
+/**
+* @brief     Contains the ID of an external device.
+* @details  This contains the identification (ID) of the external device for which
+*            there's a collection of particular settings
+*
+*/
+typedef uint8 Spi_ExternalDeviceType;
+
+typedef void (Spi_NotifyType) (void);
+
+/**
+* @brief   This structure contains all the needed data to configure one SPI Sequence.
+*
+* @implements Spi_SequenceConfigType_struct
+*/
+typedef struct
+{
+    /** @brief Number of jobs in the sequence. */
+    Spi_JobType NumJobs;
+    /** @brief CoreID used */
+    uint32 SpiCoreUse;
+    /** @brief Job index list. */
+    const Spi_JobType *JobIndexList;
+    /** @brief Job notification handler. */
+    Spi_NotifyType (*EndNotification);
+    /** @brief Boolean indicating if the Sequence is interruptible or not. */
+    uint8 Interruptible;
+    #if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+    /** @brief Boolean indicating if the Sequence is transferred in Dma fast mode or not. */
+    boolean EnableDmaFastTransfer;
+    #endif
+} Spi_SequenceConfigType;
+
+/**
+* @brief   This structure contains Sequence configuration.
+*/
+typedef struct
+{
+    /** @brief Point to Sequence configuration. */
+    const Spi_SequenceConfigType *SeqConfig;
+} Spi_SeqsConfigType;
+
+/**
+* @brief   Internal structure used to manage the sequence state.
+*
+* @implements Spi_SequenceStateType_struct
+*/
+typedef struct
+{
+    /** @brief Sequence Result. */
+    Spi_SeqResultType Result;             
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+    /** @brief Pointer to the configuration. */
+    const Spi_SequenceConfigType *Sequence;
+    /** @brief Position in JobIndexList to the job in transmission of an async sequence. */
+    const Spi_JobType *CurrentJobIndexPointer;
+    /** @brief Number of jobs in a pending async sequence, not yet transmitted. */
+    Spi_JobType RemainingJobs;
+#endif
+} Spi_SequenceStateType;
+
+/**
+* @brief   Internal structure used to manage the job state.
+*
+*/
+typedef struct
+{
+    /** @brief Job Result. */
+    Spi_JobResultType Result;      
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+    /** @brief Pointer to the state information of the async sequence. */
+    Spi_SequenceStateType *AsyncCrtSequenceState;
+    /** @brief Pointer to the next async job planned for transmission. */
+    Spi_JobType AsyncNextJob;
+#endif
+} Spi_JobStateType;
+
+/**
+* @brief   This is the structure containing all the parameters needed to completely define a Job.
+*
+* @implements Spi_JobConfigType_struct
+*/
+typedef struct
+{
+    /** @brief Number of channels in the job. */
+    Spi_ChannelType NumChannels;
+    /** @brief Channel index list. */
+    const Spi_ChannelType *ChannelIndexList;
+    /** @brief Job end notification. */
+    Spi_NotifyType (*EndNotification);
+    /** @brief Job start notification. */
+    Spi_NotifyType (*StartNotification);
+    /** @brief Priority. */
+    sint8 Priority;
+    /** @brief CoreID used */
+    uint32 SpiCoreUse;
+    /** @brief Implementation specific field referencing the channel internal state. */
+    Spi_JobStateType *JobState;
+    /** @brief HWUnit. */
+    Spi_HWUnitType HWUnit;
+    /** @brief ExternalDevice. */
+    Spi_ExternalDeviceType ExternalDevice;
+    /** @brief Implementation specific field: cached LLD device attributes. */
+    const Spi_ExDevicesConfigType *ExternalDeviceConfig;
+} Spi_JobConfigType;
+
+/**
+* @brief   This is the structure containing Job configuration.
+*/
+typedef struct
+{
+    /** @brief Point to Job configuration. */
+    const Spi_JobConfigType *JobCfg;
+} Spi_JobsCfgType;
+
+/**
+* @brief   The structure contains the pointers to the Tx/Rx memory locations for the given buffer (IB or EB).
+*
+*/
+typedef struct
+{
+    /** @brief Transmit buffer pointer. */
+    Spi_DataBufferType *BufferTX;
+    /** @brief Receive buffer pointer. */
+    Spi_DataBufferType *BufferRX;
+} Spi_BufferDescriptorType;
+
+/**
+* @brief   Internal structure used to manage the channel state.
+*
+*/
+typedef struct
+{
+    uint8 Flags;                 /**< @brief Default Transmit Enabled. */
+    Spi_NumberOfDataType Length; /**< @brief Actual Transfer size for EB. */
+} Spi_ChannelStateType;
+
+/**
+* @brief   This structure holds the HWUnit scheduling queue.
+* @details For async transmissions, this structure holds the HWUnit scheduling queue .
+*          For sync transmissions, only HWUnit Status is managed.
+*
+*/
+typedef struct
+{
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+    /** @brief Array of the IDs of jobs to be scheduled, for each priority level. */
+    Spi_JobType ScheduledJobsListHead[SPI_JOB_PRIORITY_LEVELS_COUNT];
+    /** @brief Array of the IDs of last jobs in queues, for each priority level. */
+    Spi_JobType ScheduledJobsListTail[SPI_JOB_PRIORITY_LEVELS_COUNT];
+    /** @brief Array of the IDs of last jobs in queues, for each priority level. */
+    sint8 MaxScheduledPriority;
+#endif /* ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)) */
+    Spi_StatusType Status;    /**< @brief DSPI state. */
+    Spi_ChannelType Channel; /**< Current channel index in Job */
+    Spi_JobType Job; /**< Current job index */
+} Spi_HWUnitQueue;
+
+/**
+* @brief   The structure contains the channel configuration parameters.
+*
+* @implements Spi_ChannelConfigType_struct
+*/
+typedef struct
+{
+    /** @brief Buffer Type IB/EB. */
+    Spi_BufferType BufferType;
+    /** @brief Data frame size. */
+    uint8 FrameSize;
+    /** @brief Bite order (MSB/LSB). */
+    boolean Lsb;
+#ifdef SPI_HALF_DUPLEX_MODE_SUPPORT
+  #if (STD_ON == SPI_HALF_DUPLEX_MODE_SUPPORT)
+    /** @brief Half duplex mode. */
+    Spi_HalfDuplexModeType HalfDuplexMode;
+  #endif
+#endif
+    /** @brief Default Transmit Value. */
+    uint32 DefaultTransmitValue;
+    /** @brief Data length. */
+    Spi_NumberOfDataType Length;
+    /** @brief Buffer Descriptor. */
+    Spi_BufferDescriptorType *BufferDescriptor;
+    /** @brief CoreID assigned */
+    uint32 SpiCoreUse;
+    /** @brief Implementation specific field referencing the channel internal state. */
+    Spi_ChannelStateType *ChannelState;
+} Spi_ChannelConfigType;
+
+/**
+* @brief   The structure contains the channel configuration.
+*/
+typedef struct
+{
+    /** @brief Point to Channel configuration. */
+    const Spi_ChannelConfigType *ChannelCfg;
+} Spi_ChannelsCfgType;
+
+/*---------------------------------------------------------------------------
+*             SPI Driver Low Level Implementation Specific Type Definitions
+-----------------------------------------------------------------------------*/
+
+
+/*---------------------------------------------------------------------------
+*             SPI Driver Configuration Main Structure
+-----------------------------------------------------------------------------*/
+/**
+* @brief   This is the top level structure containing all the 
+*          needed parameters for the SPI Handler Driver.
+*
+* @implements Spi_ConfigType_struct
+*/
+typedef struct
+{
+    /** @brief Number of external devices defined in the configuration. */
+    uint16 MaxExternalDevice;
+    /** @brief Number of channels defined in the configuration. */
+    Spi_ChannelType SpiMaxChannel;
+    /** @brief Number of jobs defined in the configuration. */
+    Spi_JobType SpiMaxJob;
+    /** @brief Number of sequences defined in the configuration. */
+    Spi_SequenceType SpiMaxSequence;
+    /** @brief CoreID used */
+    uint32 SpiCoreUse;
+    /** @brief Pointer to Array of channels defined in the configuration. */
+    const Spi_ChannelsCfgType *ChannelConfig;
+    /** @brief Pointer to Array of jobs defined in the configuration. */
+    const Spi_JobsCfgType *JobConfig;
+    /** @brief Pointer to Array of sequences defined in the configuration. */
+    const Spi_SeqsConfigType *SequenceConfig;
+    /** @brief External device unit attributes. */
+    const Spi_ExDevicesConfigType *ExternalDeviceConfig;
+    /** @brief Pointer to Array of LLD DSPI device instances. */
+    const Spi_PhyUnitsConfigType *HWUnitConfig;
+    /** @brief SPI Driver DEM Error: SPI_E_HARDWARE_ERROR. */
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+    const Mcal_DemErrorType SpiErrorHardwareCfg;
+#endif
+} Spi_ConfigType;
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#if (SPI_PRECOMPILE_SUPPORT == STD_OFF)
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/**
+* @brief   Export Post-Build configurations.
+*/
+SPI_CONFIG_EXT
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+#endif /* (SPI_PRECOMPILE_SUPPORT == STD_OFF) */
+
+#define   SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+extern const Spi_ConfigType *Spi_apxSpiConfigPtr[SPI_MAX_PARTITIONS];
+/**
+* @brief Extern arrays contain the state of Sequences, Jobs and Channels.
+*/
+extern Spi_JobStateType Spi_axSpiJobState[SPI_MAX_JOB];
+extern Spi_ChannelStateType Spi_axSpiChannelState[SPI_MAX_CHANNEL];
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+/**
+* @brief   This function is called after a Job has been executed.
+* @details The function calls Job and Sequence end notifications and schedules
+*          the next job of the sequence or on the liberated HW Unit.
+*
+* @param[in]    JobConfig   The just transmited job pointer.
+*
+* @return void
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+#if ((LEVEL2 == SPI_LEVEL_DELIVERED) || (LEVEL1 == SPI_LEVEL_DELIVERED))
+extern void Spi_JobTransferFinished
+    (
+        const Spi_JobConfigType *JobConfig, Spi_JobResultType JobResult
+    );
+#endif
+
+#if (SPI_VERSION_INFO_API == STD_ON)
+/**
+* @brief   This function returns the version information for the SPI driver.
+* @details This function returns the version information for the SPI driver.
+*          - Service ID:       0x09
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in,out]    VersionInfo      Pointer to where to store the version
+*                                    information of this module.
+*
+* @pre  Pre-compile parameter SPI_VERSION_INFO_API shall be STD_ON.
+* @return void
+*/
+void Spi_GetVersionInfo
+    (
+        Std_VersionInfoType *versioninfo
+    );
+#endif
+
+/**
+* @brief   This function initializes the SPI driver.
+* @details This function initializes the SPI driver using the
+*          pre-established configurations
+*          - Service ID:       0x00
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in]     ConfigPtr      Specifies the pointer to the configuration set
+* @return   void
+*/
+void Spi_Init
+    (
+        const Spi_ConfigType *ConfigPtr
+    );
+
+/**
+* @brief   This function de-initializes the SPI driver.
+* @details This function de-initializes the SPI driver using the
+*          pre-established configurations
+*          - Service ID:       0x01
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @return Std_ReturnType
+* @retval E_OK       de-initialisation command has been accepted
+* @retval E_NOT_OK   de-initialisation command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_DeInit()
+*       otherwise, the function Spi_DeInit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+*/
+Std_ReturnType Spi_DeInit(void);
+
+#if ((USAGE0 == SPI_CHANNEL_BUFFERS_ALLOWED) || (USAGE2 == SPI_CHANNEL_BUFFERS_ALLOWED ))
+/**
+* @brief   This function writes the given data into the buffer of a specific channel.
+* @details This function writes the given data into the buffer of a specific channel.
+*          - Service ID:       0x02
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Channel             Channel ID
+* @param[in]      DataBufferPtr       Pointer to source data buffer
+*
+* @return Std_ReturnType
+* @retval E_OK       Command has been accepted
+* @retval E_NOT_OK   Command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_WriteIB()
+*       otherwise, the function Spi_WriteIB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE0 or USAGE2.
+*
+*/
+Std_ReturnType Spi_WriteIB
+    (
+        Spi_ChannelType Channel,
+        const Spi_DataBufferType *DataBufferPtr
+    );
+
+/**
+* @brief   This function reads the data from the buffer of a channel and puts at the memory location.
+* @details This function reads the data from the buffer of a specific channel
+*          and puts at the specified memory location.
+*          - Service ID:       0x04
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+*
+* @param[in]      Channel             Channel ID
+* @param[in,out]  DataBufferPointer       Pointer to the memory location that will
+*                                     be written with the data in the internal
+*                                     buffer
+*
+* @return Std_ReturnType
+* @retval E_OK      read command has been accepted
+* @retval E_NOT_OK  read command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_ReadIB()
+*       otherwise, the function Spi_ReadIB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE0 or USAGE2.
+*
+* @implements Spi_ReadIB_Activity
+*/
+Std_ReturnType Spi_ReadIB
+    (
+        Spi_ChannelType Channel,
+        Spi_DataBufferType *DataBufferPointer
+    );
+#endif
+
+#if ((LEVEL2 == SPI_LEVEL_DELIVERED) || (LEVEL1 == SPI_LEVEL_DELIVERED))
+/**
+* @brief   This function triggers the asynchronous transmission for the given sequence.
+* @details This function triggers the asynchronous transmission for the given sequence.
+*          - Service ID:       0x03
+*          - Sync or Async:       Asynchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Std_ReturnType
+* @retval E_OK       Transmission command has been accepted
+* @retval E_NOT_OK   Transmission command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_AsyncTransmit()
+*       otherwise, the function Spi_AsyncTransmit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*/
+Std_ReturnType Spi_AsyncTransmit
+    (
+        Spi_SequenceType Sequence
+    );
+#endif
+
+#if ( ( USAGE1 == SPI_CHANNEL_BUFFERS_ALLOWED) || \
+        ( USAGE2 == SPI_CHANNEL_BUFFERS_ALLOWED)  )
+/**
+* @brief   This function setup an external buffer to be used by a specific channel.
+* @details This function setup an external buffer to be used by a specific channel.
+*          - Service ID:       0x05
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Channel             Channel ID
+* @param[in]      SrcDataBufferPtr    Pointer to the memory location that will hold
+*                                     the transmitted data
+* @param[in]      Length              Length of the data in the external buffer
+* @param[out]     DesDataBufferPtr    Pointer to the memory location that will hold
+*                                     the received data
+*
+* @return Std_ReturnType
+* @retval E_OK      Setup command has been accepted
+* @retval E_NOT_OK  Setup command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_SetupEB()
+*       otherwise, the function Spi_SetupEB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE1 or USAGE2.
+*
+*/
+Std_ReturnType Spi_SetupEB
+    (
+        Spi_ChannelType Channel,
+        Spi_DataBufferType *SrcDataBufferPtr,
+        Spi_DataBufferType *DesDataBufferPtr,
+        Spi_NumberOfDataType Length
+    );
+#endif
+
+/**
+* @brief   This function returns the status of the SPI driver.
+* @details This function returns the status of the SPI driver.
+*          - Service ID:       0x06
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @return Spi_StatusType
+* @retval SPI_UNINIT  The driver is un-initialized
+* @retval SPI_IDLE    The driver has no pending transfers
+* @retval SPI_BUSY    The driver is busy
+*
+* @pre  The driver needs to be initialized before calling Spi_GetStatus()
+*       otherwise, the function Spi_GetStatus() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*/
+Spi_StatusType Spi_GetStatus(void);
+
+/**
+* @brief   This function is used to request the status of a specific job.
+* @details This function is used to request the status of a specific job.
+*          - Service ID:       0x07
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Job                 Job ID
+*
+* @return Spi_JobResultType
+* @retval SPI_JOB_OK        The job ended successfully
+* @retval SPI_JOB_PENDING   The job is pending
+* @retval SPI_JOB_FAILED    The job has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_GetJobResult()
+*       otherwise, the function Spi_GetJobResult() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+* @implements Spi_GetJobResult_Activity
+*/
+Spi_JobResultType Spi_GetJobResult
+    (
+        Spi_JobType Job
+    );
+
+/**
+* @brief   This function is used to request the status of a specific sequence.
+* @details This function is used to request the status of a specific sequence.
+*          - Service ID:       0x08
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Spi_SeqResultType
+* @retval SPI_SEQ_OK       The sequence ended successfully
+* @retval SPI_SEQ_PENDING  The sequence is pending
+* @retval SPI_SEQ_FAILED   The sequence has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_GetSequenceResult()
+*       otherwise, the function Spi_GetSequenceResult() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+*/
+Spi_SeqResultType Spi_GetSequenceResult
+    (
+        Spi_SequenceType Sequence
+    );
+
+#if ((LEVEL2 == SPI_LEVEL_DELIVERED) || (LEVEL0 == SPI_LEVEL_DELIVERED))
+/**
+* @brief   This function is used for synchronous transmission of a given sequence.
+* @details This function is used for synchronous transmission of a given sequence.
+*          - Service ID:       0x0a
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Std_ReturnType
+* @retval E_OK      Transmission command has been completed successfully
+* @retval E_NOT_OK  Transmission command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_SyncTransmit().
+*       otherwise, the function Spi_SyncTransmit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL0 or LEVEL2
+*/
+Std_ReturnType Spi_SyncTransmit
+    (
+        Spi_SequenceType Sequence
+    );
+#endif
+
+#if (SPI_HW_STATUS_API == STD_ON)
+/**
+* @brief   This function is used to request the status of a specific SPI peripheral unit.
+* @details This function is used to request the status of a specific SPI peripheral unit.
+*          - Service ID:       0x0b
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      HWUnit              The HW peripheral for which we need the status
+*
+* @return Spi_StatusType
+* @retval SPI_UNINIT  The peripheral is un-initialized
+* @retval SPI_IDLE    The peripheral is in idle state
+* @retval SPI_BUSY    The peripheral is busy
+*
+* @pre  The driver needs to be initialized before calling Spi_GetHWUnitStatus()
+*       otherwise, the function Spi_GetHWUnitStatus() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  SPI_HW_STATUS_API == STD_ON
+*/
+Spi_StatusType Spi_GetHWUnitStatus
+    (
+        Spi_HWUnitType HWUnit
+    );
+#endif
+
+#if (SPI_CANCEL_API == STD_ON)
+/**
+* @brief   This function is used to request the cancelation of the given sequence.
+* @details This function is used to request the cancelation of the given sequence.
+*          - Service ID:       0x0c
+*          - Sync or Async:       Asynchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @pre  The driver needs to be initialized before calling Spi_Cancel()
+*       otherwise, the function Spi_Cancel() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CANCEL_API shall be STD_ON
+* @post  The SPI Handler Driver is not responsible on external devices damages or
+*       undefined state due to cancelling a sequence transmission.
+*/
+void Spi_Cancel
+    (
+        Spi_SequenceType Sequence
+    );
+#endif
+
+#if (SPI_LEVEL_DELIVERED == LEVEL2)
+/**
+* @brief   This function specifies the asynchronous mode for the SPI busses handled asynchronously.
+* @details This function specifies the asynchronous mode for the SPI busses
+*          handled asynchronously.
+*          - Service ID:       0x0d
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in]      AsyncMode    This parameter specifies the asynchronous
+*                              operating mode (SPI_POLLING_MODE or
+*                              SPI_INTERRUPT_MODE)
+*
+* @return Std_ReturnType
+* @retval E_OK      The command ended successfully
+* @retval E_NOT_OK  The command has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_SetAsyncMode()
+*       otherwise, the function Spi_SetAsyncMode() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL2
+*/
+Std_ReturnType Spi_SetAsyncMode
+    (
+        Spi_AsyncModeType AsyncMode
+    );
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON))
+/**
+* @brief   This function specifies the asynchronous mode for a given HWUnit.
+* @details This function specifies the asynchronous mode for the SPI busses
+*          handled asynchronously.
+*          For synchronous HW units, the function has no impact.
+*          The function will fail in two cases:
+*          - driver not initialised (SPI_E_UNINIT reported by DET)
+*          - a sequence transmission is pending the the asynchronous HW unit
+*            (SPI_E_SEQ_PENDING reported by DET)
+*
+* @param[in]      HWUnit       The ID of the HWUnit to be configured
+* @param[in]      AsyncMode    This parameter specifies the asynchronous
+*                              operating mode (SPI_POLLING_MODE or
+*                              SPI_INTERRUPT_MODE)
+*
+* @return Std_ReturnType
+* @retval E_OK       The command ended successfully
+* @retval E_NOT_OK   The command has failed
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL2 and
+*       SPI_HWUNIT_ASYNC_MODE should be on STD_ON
+*/
+Std_ReturnType Spi_SetHWUnitAsyncMode
+    (
+        Spi_HWUnitType HWUnit,
+        Spi_AsyncModeType AsyncMode
+    );
+#endif /* (SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON) */
+
+#if (SPI_DUAL_CLOCK_MODE == STD_ON)
+Std_ReturnType Spi_SetClockMode
+    (
+        Spi_DualClockModeType ClockMode
+    );
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SPI_H */
+
+/** @} */
+

RTD/include/Spi_IPW.h

@@ -0,0 +1,190 @@
+/**
+*   @file    Spi_IPW.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi middle level driver header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            LLD.
+*   @addtogroup SPI_DRIVER Spi Driver
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_IPW_H
+#define SPI_IPW_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Spi.h"
+#include "Lpspi_Ip.h"
+#include "Flexio_Spi_Ip.h"
+#include "Spi_IPW_Types.h"
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_VENDOR_ID                       43
+#define SPI_IPW_AR_RELEASE_MAJOR_VERSION        4
+#define SPI_IPW_AR_RELEASE_MINOR_VERSION        4
+#define SPI_IPW_AR_RELEASE_REVISION_VERSION     0
+#define SPI_IPW_SW_MAJOR_VERSION                1
+#define SPI_IPW_SW_MINOR_VERSION                0
+#define SPI_IPW_SW_PATCH_VERSION                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Spi.h and Spi_IPW.h are of the same vendor */
+#if (SPI_VENDOR_ID != SPI_IPW_VENDOR_ID)
+    #error "Spi.h and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if Spi.h file and Spi_IPW.h file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_AR_RELEASE_MINOR_VERSION != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_AR_RELEASE_REVISION_VERSION != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Spi.h and Spi_IPW.h are different"
+#endif
+#if ((SPI_SW_MAJOR_VERSION != SPI_IPW_SW_MAJOR_VERSION) || \
+     (SPI_SW_MINOR_VERSION != SPI_IPW_SW_MINOR_VERSION) || \
+     (SPI_SW_PATCH_VERSION != SPI_IPW_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Spi.h and Spi_IPW.h are different"
+#endif
+
+/* Check if Spi_IPW.h and Flexio_Spi_Ip.h are of the same vendor */
+#if (SPI_IPW_VENDOR_ID != FLEXIO_SPI_IP_VENDOR_ID)
+    #error "Spi_IPW.h and Flexio_Spi_Ip.h have different vendor ids"
+#endif
+/* Check if Spi_IPW.h file and Flexio_Spi_Ip.h file are of the same Autosar version */
+#if ((SPI_IPW_AR_RELEASE_MAJOR_VERSION    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_MINOR_VERSION    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_REVISION_VERSION != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Spi_IPW.h and Flexio_Spi_Ip.h are different"
+#endif
+#if ((SPI_IPW_SW_MAJOR_VERSION != FLEXIO_SPI_IP_SW_MAJOR_VERSION) || \
+     (SPI_IPW_SW_MINOR_VERSION != FLEXIO_SPI_IP_SW_MINOR_VERSION) || \
+     (SPI_IPW_SW_PATCH_VERSION != FLEXIO_SPI_IP_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Spi_IPW.h and Flexio_Spi_Ip.h are different"
+#endif
+
+/* Check if Lpspi_Ip.h and Spi_IPW.h are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID != SPI_IPW_VENDOR_ID)
+    #error "Lpspi_Ip.h and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if Lpspi_Ip.h file and Spi_IPW.h file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Lpspi_Ip.h and Spi_IPW.h are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION != SPI_IPW_SW_MAJOR_VERSION) || \
+     (LPSPI_IP_SW_MINOR_VERSION != SPI_IPW_SW_MINOR_VERSION) || \
+     (LPSPI_IP_SW_PATCH_VERSION != SPI_IPW_SW_PATCH_VERSION))
+#error "Software Version Numbers of Lpspi_Ip.h and Spi_IPW.h are different"
+#endif
+
+/* Check if Spi_IPW_Types.h and Spi_IPW.h are of the same vendor */
+#if (SPI_IPW_TYPES_VENDOR_ID != SPI_IPW_VENDOR_ID)
+    #error "Spi_IPW_Types.h and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if Spi_IPW_Types.h file and Spi_IPW.h file are of the same Autosar version */
+#if ((SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi_IPW_Types.h and Spi_IPW.h are different"
+#endif
+#if ((SPI_IPW_TYPES_SW_MAJOR_VERSION != SPI_IPW_SW_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_MINOR_VERSION != SPI_IPW_SW_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_PATCH_VERSION != SPI_IPW_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi_IPW_Types.h and Spi_IPW.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+void Spi_Ipw_Init(const Spi_HWUnitType HWUnitId, const Spi_HWUnitConfigType * HWUnit);
+
+void Spi_Ipw_DeInit(Spi_HWUnitType HWUnit, uint32 SpiCoreID);
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0))
+Std_ReturnType Spi_Ipw_SyncTransmit(const Spi_JobConfigType *JobConfig, uint32 SpiCoreID);
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) ) */
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+void Spi_Ipw_JobTransfer(const Spi_JobConfigType *JobConfig);
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+void Spi_Ipw_IrqPoll(Spi_HWUnitType HWUnit, uint32 SpiCoreID);
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+void Spi_Ipw_IrqConfig(Spi_HWUnitType HWUnit, Spi_AsyncModeType Mode, uint32 SpiCoreID);
+#endif
+
+#if ((SPI_SLAVE_SUPPORT == STD_ON) && (SPI_CANCEL_API == STD_ON))
+    #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+void Spi_Ipw_SlaveCancel(const Spi_JobConfigType *JobConfig);
+    #endif
+#endif
+
+#if (SPI_DUAL_CLOCK_MODE == STD_ON)
+void Spi_Ipw_SetClockMode(Spi_DualClockModeType ClockMode, const Spi_HWUnitConfigType * HWUnitConfig);
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*SPI_IPW_H*/
+
+/** @} */

RTD/include/Spi_IPW_Types.h

@@ -0,0 +1,230 @@
+
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_IPW_TYPES_H
+#define SPI_IPW_TYPES_H
+
+/**
+*   @file    Spi_IPW_Types.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi middle level driver header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            LLD.
+*   @addtogroup SPI_DRIVER Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Lpspi_Ip_Types.h"
+#include "Flexio_Spi_Ip_Types.h"
+#include "Spi_Ipw_Cfg.h"
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_TYPES_VENDOR_ID                       43
+#define SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION        4
+#define SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION        4
+#define SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION     0
+#define SPI_IPW_TYPES_SW_MAJOR_VERSION                1
+#define SPI_IPW_TYPES_SW_MINOR_VERSION                0
+#define SPI_IPW_TYPES_SW_PATCH_VERSION                0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Spi_IPW_Types.h and Lpspi_Ip_Types.h are of the same vendor */
+#if (SPI_IPW_TYPES_VENDOR_ID != LPSPI_IP_TYPES_VENDOR_ID)
+    #error "Spi_IPW_Types.h and Lpspi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if Spi_IPW_Types.h file and Lpspi_Ip_Types.h file are of the same Autosar version */
+#if ((SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION != LPSPI_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION != LPSPI_IP_TYPES_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Spi_IPW_Types.h and Lpspi_Ip_Types.h are different"
+#endif
+
+#if ((SPI_IPW_TYPES_SW_MAJOR_VERSION != LPSPI_IP_TYPES_SW_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_MINOR_VERSION != LPSPI_IP_TYPES_SW_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_PATCH_VERSION != LPSPI_IP_TYPES_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Spi_IPW_Types.h and Lpspi_Ip_Types.h are different"
+#endif
+
+/* Check if Spi_IPW_Types.h and Flexio_Spi_Ip_Types.h are of the same vendor */
+#if (SPI_IPW_TYPES_VENDOR_ID != FLEXIO_SPI_IP_TYPES_VENDOR_ID)
+    #error "Spi_IPW_Types.h and Flexio_Spi_Ip_Types.h have different vendor ids"
+#endif
+/* Check if Spi_IPW_Types.h file and Flexio_Spi_Ip_Types.h file are of the same Autosar version */
+#if ((SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION    != FLEXIO_SPI_IP_TYPES_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION    != FLEXIO_SPI_IP_TYPES_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION != FLEXIO_SPI_IP_TYPES_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Spi_IPW_Types.h and Flexio_Spi_Ip_Types.h are different"
+#endif
+#if ((SPI_IPW_TYPES_SW_MAJOR_VERSION != FLEXIO_SPI_IP_TYPES_SW_MAJOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_MINOR_VERSION != FLEXIO_SPI_IP_TYPES_SW_MINOR_VERSION) || \
+     (SPI_IPW_TYPES_SW_PATCH_VERSION != FLEXIO_SPI_IP_TYPES_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Spi_IPW_Types.h and Flexio_Spi_Ip_Types.h are different"
+#endif
+
+/* Check if Spi_IPW_Types.h and Spi_Ipw_Cfg.h are of the same vendor */
+#if (SPI_IPW_TYPES_VENDOR_ID != SPI_IPW_VENDOR_ID_CFG_H)
+    #error "Spi_IPW_Types.h and Spi_Ipw_Cfg.h have different vendor ids"
+#endif
+/* Check if Spi_IPW_Types.h file and Spi_Ipw_Cfg.h file are of the same Autosar version */
+#if ((SPI_IPW_TYPES_AR_RELEASE_MAJOR_VERSION != SPI_IPW_AR_RELEASE_MAJOR_VERSION_CFG_H) || \
+     (SPI_IPW_TYPES_AR_RELEASE_MINOR_VERSION != SPI_IPW_AR_RELEASE_MINOR_VERSION_CFG_H) || \
+     (SPI_IPW_TYPES_AR_RELEASE_REVISION_VERSION != SPI_IPW_AR_RELEASE_REVISION_VERSION_CFG_H))
+#error "AutoSar Version Numbers of Spi_IPW_Types.h and Spi_Ipw_Cfg.h are different"
+#endif
+#if ((SPI_IPW_TYPES_SW_MAJOR_VERSION != SPI_IPW_SW_MAJOR_VERSION_CFG_H) || \
+     (SPI_IPW_TYPES_SW_MINOR_VERSION != SPI_IPW_SW_MINOR_VERSION_CFG_H) || \
+     (SPI_IPW_TYPES_SW_PATCH_VERSION != SPI_IPW_SW_PATCH_VERSION_CFG_H))
+#error "Software Version Numbers of Spi_IPW_Types.h and Spi_Ipw_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/**
+ * @brief This enum contains all IPs which can integrate SPI functionalityes
+ */
+typedef enum
+{
+    SPI_OVER_LPSPI = 0,
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    SPI_OVER_FLEXIO = 1
+#endif
+} Spi_Ipw_SupportedIPsType;
+
+/** 
+ * @bried This union contains config structure for all IPs available.
+ */
+typedef struct
+{
+    const Lpspi_Ip_ConfigType *LpspiIpConfig;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    const Flexio_Spi_Ip_ConfigType *FlexioSpiIpConfig;
+#endif
+#if (SPI_IPW_DMA_USED == STD_ON)
+#if (SPI_IPW_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+    Lpspi_Ip_FastTransferType *LpspiFastTransferCfg; /* config structure for a sequence transfer with Dma Fast */
+#endif
+#endif
+} Spi_Ipw_IpConfigType;
+
+/** 
+ * @bried This union contains config structure for all external device available.
+ */
+typedef struct
+{
+    const Lpspi_Ip_ExternalDeviceType *LpspiExternalDeviceConfig;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    const Flexio_Spi_Ip_ExternalDeviceType *Flexio_SpiExternalDeviceConfig;
+#endif
+} Spi_Ipw_ExternalDeviceType;
+
+/**
+* @brief   This structure holds the HWUnit configuration parameters.
+*
+* @implements Spi_HWUnitConfigType_struct
+*/
+typedef struct
+{
+    Spi_Ipw_SupportedIPsType IpType;
+    uint8 Instance;
+    uint32 SpiCoreUse;
+    Spi_Ipw_IpConfigType IpConfig;
+    uint32 IsSync;
+} Spi_HWUnitConfigType;
+
+/**
+* @brief   This structure holds the PhyUnit configuration.
+*/
+typedef struct
+{
+    /** @brief Point to PhyUnit configuration. */
+    const Spi_HWUnitConfigType * PhyUnitConfig;
+} Spi_PhyUnitsConfigType;
+
+/**
+* @brief   This structure holds the configuration parameters for each ExternalDevice.
+*/
+typedef struct
+{
+    Spi_Ipw_SupportedIPsType IpType;
+    uint8 Instance;
+    Spi_Ipw_ExternalDeviceType ExternalDeviceConfig;
+    uint32 SpiCoreUse;
+} Spi_ExternalDeviceConfigType;
+
+/**
+* @brief   This structure holds the ExternalDevice configuration.
+*/
+typedef struct
+{
+    /** @brief Point to ExternalDevice configuration. */
+    const Spi_ExternalDeviceConfigType * ExDeviceConfig;
+} Spi_ExDevicesConfigType;
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*SPI_IPW_TYPES_H*/
+
+/** @} */

RTD/src/Flexio_Spi_Ip.c

@@ -0,0 +1,1778 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Flexio_Spi_Ip.c
+*
+*   @brief   FLEXIO_SPI low-level driver implementations.
+*   @details FLEXIO_SPI low-level driver implementations.
+*
+*   @addtogroup FLEXIO_DRIVER Flexio_Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Mcal.h"
+#include "Flexio_Spi_Ip.h"
+#include "Flexio_Spi_Ip_Irq.h"
+#include "Flexio_Spi_Ip_Cfg.h"
+#include "OsIf.h"
+
+#if (STD_ON == FLEXIO_SPI_IP_ENABLE)
+#include "Flexio_Mcl_Ip_HwAccess.h"
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+   #include "Dma_Ip.h"
+#endif
+#if (STD_ON == FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT)
+   #define USER_MODE_REG_PROT_ENABLED   (FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT)
+   #include "RegLockMacros.h"
+#endif
+#include "SchM_Spi.h"
+#if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    #include "Devassert.h"
+#endif
+#endif /*#if (FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+
+/*==================================================================================================
+*                                       SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_VENDOR_ID_C                      43
+#define FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C       4
+#define FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C       4
+#define FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_C    0
+#define FLEXIO_SPI_IP_SW_MAJOR_VERSION_C               1
+#define FLEXIO_SPI_IP_SW_MINOR_VERSION_C               0
+#define FLEXIO_SPI_IP_SW_PATCH_VERSION_C               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    #if (STD_ON == FLEXIO_SPI_IP_ENABLE)
+        /* Check if current file and Mcal header file are of the same Autosar version */
+        #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+             (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION))
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Mcal.h are different"
+        #endif
+
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+            /* Check if current file and Dma_Ip header file are of the same Autosar version */
+            #if ((DMA_IP_AR_RELEASE_MAJOR_VERSION_H != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C) || \
+                 (DMA_IP_AR_RELEASE_MINOR_VERSION_H != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C))
+                #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Dma_Ip.h are different"
+            #endif
+        #endif
+        
+        #if (STD_ON == FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT)
+            #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
+                 (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
+                #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and RegLockMacros.h are different"
+            #endif
+        #endif
+
+        /* Check if the current file and SchM_Spi.h header file are of the same version */
+        #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_SPI_AR_RELEASE_MAJOR_VERSION) || \
+             (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_SPI_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and SchM_Spi.h are different"
+        #endif
+
+        /* Check if the current file and OsIf.h header file are of the same version */
+        #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+             (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and OsIf.h are different"
+        #endif
+
+        #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+            /* Check if the current file and Devassert.h header file are of the same version */
+            #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
+                 (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \
+                )
+                #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Devassert.h are different"
+            #endif
+        #endif /* (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT) */
+
+        /* Check if the current file and Flexio_Mcl_Ip_HwAccess.h header file are of the same version */
+        #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C != FLEXIO_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H) || \
+             (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C != FLEXIO_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H) \
+            )
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Flexio_Mcl_Ip_HwAccess.h are different"
+        #endif
+    #endif /* (STD_ON == FLEXIO_SPI_IP_ENABLE) */
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+/* Check if Flexio_Spi_Ip.h and Flexio_Spi_Ip.c are of the same vendor */
+#if (FLEXIO_SPI_IP_VENDOR_ID_C != FLEXIO_SPI_IP_VENDOR_ID)
+    #error "Flexio_Spi_Ip.c and Flexio_Spi_Ip.h have different vendor ids"
+#endif
+
+/* Check if Flexio_Spi_Ip.c file and Flexio_Spi_Ip.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_C != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip.h are different"
+#endif
+
+#if ((FLEXIO_SPI_IP_SW_MAJOR_VERSION_C != FLEXIO_SPI_IP_SW_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_MINOR_VERSION_C != FLEXIO_SPI_IP_SW_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_PATCH_VERSION_C != FLEXIO_SPI_IP_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip.h are different"
+#endif
+
+/* Check if Flexio_Spi_Ip_Irq.h and Flexio_Spi_Ip.c are of the same vendor */
+#if (FLEXIO_SPI_IP_VENDOR_ID_C != FLEXIO_SPI_IP_IRQ_VENDOR_ID)
+    #error "Flexio_Spi_Ip.c and Flexio_Spi_Ip_Irq.h have different vendor ids"
+#endif
+
+/* Check if Flexio_Spi_Ip.c file and Flexio_Spi_Ip_Irq.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C    != FLEXIO_SPI_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C    != FLEXIO_SPI_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_C != FLEXIO_SPI_IP_IRQ_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip_Irq.h are different"
+#endif
+
+#if ((FLEXIO_SPI_IP_SW_MAJOR_VERSION_C != FLEXIO_SPI_IP_IRQ_SW_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_MINOR_VERSION_C != FLEXIO_SPI_IP_IRQ_SW_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_SW_PATCH_VERSION_C != FLEXIO_SPI_IP_IRQ_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip_Irq.h are different"
+#endif
+
+/* Check if Flexio_Spi_Ip.c and Flexio_Spi_Ip_Cfg.h are of the same vendor */
+#if (FLEXIO_SPI_IP_VENDOR_ID_C != FLEXIO_SPI_IP_VENDOR_ID_CFG)
+    #error "Flexio_Spi_Ip.c and Flexio_Spi_Ip_Cfg.h have different vendor ids"
+#endif
+
+/* Check if Flexio_Spi_Ip.c file and Flexio_Spi_Ip_Cfg.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_C != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_CFG))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+
+#if ((FLEXIO_SPI_IP_SW_MAJOR_VERSION_C != FLEXIO_SPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_SW_MINOR_VERSION_C != FLEXIO_SPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_SW_PATCH_VERSION_C != FLEXIO_SPI_IP_SW_PATCH_VERSION_CFG))
+    #error "Software Version Numbers of Flexio_Spi_Ip.c and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+#if (STD_ON == FLEXIO_SPI_IP_ENABLE)
+
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    /* the maximum of Major loop when Minor loop Channel Linking Disabled */
+    #define FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16 ((uint16)0x7FFFu)
+#endif
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+                                    GLOBAL VARIABLES
+==================================================================================================*/
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+
+static Flexio_Spi_Ip_StateStructureType Flexio_Spi_Ip_axStateStructure[FLEXIO_SPI_IP_NUMBER_OF_INSTANCES];
+
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    #define SPI_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
+    #include "Spi_MemMap.h"
+static uint32 Flexio_Spi_Ip_u32DiscardData;
+    #define SPI_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
+    #include "Spi_MemMap.h"
+#endif
+#define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+Flexio_Spi_Ip_StateStructureType* Flexio_Spi_Ip_apxStateStructureArray[FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8];
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#define SPI_START_SEC_CONST_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+static FLEXIO_Type* const Flexio_Spi_Ip_apxBases[FLEXIO_SPI_IP_INSTANCE_COUNT] = IP_FLEXIO_BASE_PTRS;
+
+#define SPI_STOP_SEC_CONST_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+static void Flexio_Spi_Ip_TransferProcess(
+                                            uint8 Instance,
+                                            uint8 ShifterIndex,
+                                            uint8 ShifterMaskFlag,
+                                            uint8 ShifterErrMaskFlag
+                                         );
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+static void Flexio_Spi_Ip_TxDmaConfig(uint8 Instance);
+static void Flexio_Spi_Ip_RxDmaConfig(uint8 Instance);
+static void Flexio_Spi_Ip_TxDmaContinueTransfer(uint8 Instance);
+static void Flexio_Spi_Ip_RxDmaContinueTransfer(uint8 Instance);
+#endif
+#if (STD_ON == FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT)
+static void Flexio_Spi_Ip_SetUserAccess(uint8 Instance);
+static void Flexio_Spi_Ip_SetUserAccessAllowed(uint8 Instance);
+#endif /* FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT */
+
+static void Flexio_Spi_Ip_WriteShifterBuffer
+(
+    uint8 Instance,
+    uint8 TxShifterIndex
+);
+
+static void Flexio_Spi_Ip_ReadShifterBuffer
+(
+    uint8 Instance,
+    uint8 RxShifterIndex
+);
+
+static void Flexio_Spi_Ip_ClearShifterTimerRegisters
+(
+    uint8 Instance
+);
+static void Flexio_Spi_Ip_ConfigExternalDevice
+(
+    const Flexio_Spi_Ip_StateStructureType *State
+);
+
+static void Flexio_Spi_Ip_SyncTransmitProcessData
+(
+    const uint8 InstanceFlexio
+);
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+/**
+* @brief   This function is called by Flexio_Spi_Ip_IrqHandler or Flexio_Spi_Ip_ManageBuffers. It will process transfer in interrupt mode or polling mode.
+* @details This function will fill Data into TX SHIFTBUF and read Data in RX SHIFTBUF fill to Rx Buffers.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Flexio_Spi_Ip_TransferProcess(
+                                            uint8 Instance,
+                                            uint8 ShifterIndex,
+                                            uint8 ShifterMaskFlag,
+                                            uint8 ShifterErrMaskFlag
+                                         )
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    boolean ErrorFlag = FALSE;
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+
+    if (FLEXIO_SPI_IP_BUSY == State->Status)
+    {
+        /* Get Shifters and timers index */
+        TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+        RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+        
+        if (0u != ShifterErrMaskFlag)
+        {
+            ErrorFlag = TRUE;
+        }
+        else
+        {
+            if (0u != ShifterMaskFlag)
+            {
+                /* Transmit */
+                if (State->TxIndex != State->ExpectedFifoWrites)
+                {
+                    /* SHIFTBUF is available to transfer */
+                    if (ShifterIndex == TxShifterIndex)
+                    {
+                        Flexio_Spi_Ip_WriteShifterBuffer(Instance, TxShifterIndex);
+                    }
+                }
+                
+                /* Receive */
+                if (State->RxIndex != State->ExpectedFifoReads)
+                {
+                    /* SHIFTBUF is available to receive */
+                    if (ShifterIndex == RxShifterIndex)
+                    {
+                        Flexio_Spi_Ip_ReadShifterBuffer(Instance, RxShifterIndex);
+                    }
+                }
+            }
+
+        }
+        
+        /* End of transfer */
+        if ((State->RxIndex == State->ExpectedFifoReads) || (TRUE == ErrorFlag))
+        {
+            /* Disable ISRs */
+            Flexio_Mcl_Ip_SetShifterInterrupt(Base, (1u<<TxShifterIndex) | (1u<<RxShifterIndex), FALSE);
+            /* Disable Error interrupts */
+            Flexio_Mcl_Ip_SetShifterErrorInterrupt(Base, (1u<<TxShifterIndex) | (1u<<RxShifterIndex), FALSE);
+            
+            if (TRUE == ErrorFlag)
+            {
+                State->Status = FLEXIO_SPI_IP_FAULT;
+            }
+            else
+            {
+                State->Status = FLEXIO_SPI_IP_IDLE;
+            }
+            if (State->Callback != NULL_PTR)
+            {
+                if (TRUE == ErrorFlag)
+                {
+                    State->Callback(Instance, FLEXIO_SPI_IP_EVENT_FAULT);
+                }
+                else
+                {
+                    State->Callback(Instance, FLEXIO_SPI_IP_EVENT_END_TRANSFER);
+                }
+            }
+        }
+    }
+}
+
+/**
+* @brief   Configure Flexio register for an external device.
+* @details This function initializes the SPI instance from Configurations in Slave or Master mode 
+*          and other hardware specific parameters. This function won't initialize spi bus parameters.
+*
+* @param[in]      Configuration      Pointer to configurations of the hardware unit.
+*/
+static void Flexio_Spi_Ip_ConfigExternalDevice(
+                                                const Flexio_Spi_Ip_StateStructureType *State
+                                              )
+{
+    uint8 TxShifterIndex;
+    uint8 RxShifterIndex;
+    uint8 ClkTimerIndex;
+    uint8 CsTimerIndex;
+    uint8 InstanceFlexio;
+    uint32 ClkTimerTrgsel;
+    uint32 FrameSize;
+    const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice;
+    FLEXIO_Type* Base;
+
+    Base = Flexio_Spi_Ip_apxBases[0];
+    ExternalDevice = State->ExternalDevice;
+    InstanceFlexio = ExternalDevice->Instance;
+    /* Prepare frame size to write to TIMCMP register */
+    FrameSize = ((uint32)ExternalDevice->DeviceParams->FrameSize * 2UL) - 1UL;
+
+    /* Get Shifters and timers index */
+    TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+    RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+    ClkTimerIndex = State->PhyUnitConfig->ClkTimerIndex;
+    CsTimerIndex = State->PhyUnitConfig->CsTimerIndex;
+
+    /* Select compatible shifter Status flag */
+    ClkTimerTrgsel = ((uint32)TxShifterIndex * 4UL) + 1UL;
+
+    /* Disable DMA requests and all interrupts before initialization, they will be enabled later */
+    Flexio_Mcl_Ip_SetShifterInterrupt(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+    Flexio_Mcl_Ip_SetShifterDMARequest(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+    /* Disable error interrupt */
+    Flexio_Mcl_Ip_SetShifterErrorInterrupt(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+
+    /* Clear Shifter and Timer Configuration registers */
+    Flexio_Spi_Ip_ClearShifterTimerRegisters(InstanceFlexio);
+    /* Clear Error status flag */
+    Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, TxShifterIndex);
+    Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, RxShifterIndex);
+    /* Clear Rx shifter flag to avoid read data from previous transfer */
+    Flexio_Mcl_Ip_ClearShifterStatus(Base, RxShifterIndex);
+
+    /* Write to TX shifter SHIFTCTL */
+    Base->SHIFTCTL[TxShifterIndex] = ExternalDevice->TxShiftCtl;
+    /* Write to TX SHIFTCFG */
+    Base->SHIFTCFG[TxShifterIndex] = ExternalDevice->TxShiftCfg;
+    
+    /* Write to RX shifter SHIFTCTL */
+    Base->SHIFTCTL[RxShifterIndex] = ExternalDevice->RxShiftCtl;
+    /* Write to RX SHIFTCFG */
+    Base->SHIFTCFG[RxShifterIndex] = ExternalDevice->RxShiftCfg;
+
+    /* Write to CLK Timer TIMCMP */
+    /* Baudrate and frame size */
+#if (STD_ON == FLEXIO_SPI_IP_SLAVE_SUPPORT)
+    if (State->PhyUnitConfig->SlaveMode)
+    {
+        Base->TIMCMP[ClkTimerIndex] = FrameSize & ((uint32)FLEXIO_TIMCMP_CMP_MASK);
+        /* Write to CLK Timer TIMCFG */
+        Base->TIMCFG[ClkTimerIndex] = ExternalDevice->ClkTimeCfg;
+        /* Write to CLK Timer TIMCTL */
+        Base->TIMCTL[ClkTimerIndex] = ExternalDevice->ClkTimeCtl;
+    }
+    else
+    {
+#endif
+        /* The value will be written to 8 upper bits fiel of TIMCMP */
+        FrameSize = FrameSize << 8u;
+        /* Write to CLK Timer TIMCFG */
+        Base->TIMCFG[ClkTimerIndex] = ExternalDevice->ClkTimeCfg;
+    #if ( STD_ON == FLEXIO_SPI_IP_DUAL_CLOCK_MODE)
+        Base->TIMCMP[ClkTimerIndex] =  ( (ExternalDevice->ClkTimeCmpBaudRate[State->ClockMode] & FLEXIO_SPI_IP_TIMECMP_BAUDRATE_MASK_U32) \
+                                    |  (FrameSize & FLEXIO_SPI_IP_TIMECMP_FRAMESIZE_MASK_U32) )  \
+                                        & ((uint32)FLEXIO_TIMCMP_CMP_MASK);
+        Base->TIMCFG[ClkTimerIndex] |= ExternalDevice->ClkTimeCfgTimDec[State->ClockMode];
+    #else
+        Base->TIMCMP[ClkTimerIndex] =  ( (ExternalDevice->ClkTimeCmpBaudRate & FLEXIO_SPI_IP_TIMECMP_BAUDRATE_MASK_U32) \
+                                    |  (FrameSize & FLEXIO_SPI_IP_TIMECMP_FRAMESIZE_MASK_U32) )  \
+                                        & ((uint32)FLEXIO_TIMCMP_CMP_MASK);
+        Base->TIMCFG[ClkTimerIndex] |= ExternalDevice->ClkTimeCfgTimDec;
+    #endif  
+        /* Write to CLK Timer TIMCTL */
+        Base->TIMCTL[ClkTimerIndex] = ExternalDevice->ClkTimeCtl | ((uint32)ClkTimerTrgsel << 24u);
+
+        /* Write to CS Timer TIMCMP */
+        Base->TIMCMP[CsTimerIndex] = ExternalDevice->CsTimeCmp;
+        /* Write to CS Timer TIMCFG */
+        Base->TIMCFG[CsTimerIndex] = ExternalDevice->CsTimeCfg;
+        /* Write to CS Timer TIMCTL */
+        Base->TIMCTL[CsTimerIndex] = ExternalDevice->CsTimeCtl;
+#if (STD_ON == FLEXIO_SPI_IP_SLAVE_SUPPORT)
+    }
+#endif
+}
+
+static void Flexio_Spi_Ip_SyncTransmitProcessData(
+                                                    const uint8 InstanceFlexio
+                                                 )
+{
+    boolean IsShifterFlagRaised;
+    uint8 TxShifterIndex;
+    uint8 RxShifterIndex;
+    const FLEXIO_Type *Base = (const FLEXIO_Type *)Flexio_Spi_Ip_apxBases[0];
+    const Flexio_Spi_Ip_StateStructureType *State = (const Flexio_Spi_Ip_StateStructureType *)Flexio_Spi_Ip_apxStateStructureArray[InstanceFlexio];
+
+    TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+    RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+    /* Transmit */
+    if (State->TxIndex != State->ExpectedFifoWrites)
+    {
+        /* Get Tx shifter status */
+        IsShifterFlagRaised = Flexio_Mcl_Ip_GetShifterStatus(Base, TxShifterIndex);
+        /* SHIFTBUF is available to transfer */
+        if (IsShifterFlagRaised)
+        {
+            Flexio_Spi_Ip_WriteShifterBuffer(InstanceFlexio, TxShifterIndex);
+        }
+    }
+
+    /* Receive */
+    if (State->RxIndex != State->ExpectedFifoReads)
+    {
+        /* Get Tx shifter status */
+        IsShifterFlagRaised = Flexio_Mcl_Ip_GetShifterStatus(Base, RxShifterIndex);
+        /* SHIFTBUF is available to read */
+        if (IsShifterFlagRaised)
+        {
+            Flexio_Spi_Ip_ReadShifterBuffer(InstanceFlexio, RxShifterIndex);
+        }
+    }
+}
+
+#if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+/**
+* @brief   This function will configure hardware TCDs for the channels TX DMA, RX DMA 
+*          according to current transfer Configuration. DMA channels will be started at the end of the function.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Flexio_Spi_Ip_TxDmaConfig(uint8 Instance)
+{
+    const FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoWrites;
+    uint8 TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+
+    /* Limits number of major count */
+    if (FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    /* Update buffers index */
+    State->TxIndex = NumberDmaIterWrite;
+
+    /* configure TX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    
+    if (TRUE == State->ExternalDevice->DeviceParams->Lsb)
+    {
+        DmaTcdList[1u].Value = (uint32)&Base->SHIFTBUF[TxShifterIndex];    /* dest address write*/
+    }
+    else /* MSB mode */
+    {
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            DmaTcdList[1u].Value = (uint32)&Base->SHIFTBUFBIS[TxShifterIndex] + 3u;    /* dest address write*/
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            DmaTcdList[1u].Value = (uint32)&Base->SHIFTBUFBIS[TxShifterIndex] + 2u;    /* dest address write*/
+        }
+        else
+        {
+            DmaTcdList[1u].Value = (uint32)&Base->SHIFTBUFBIS[TxShifterIndex];    /* dest address write*/
+        }
+    }
+
+    if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+    {
+        DmaTcdList[2u].Value = 1u;  /* src offset is 1 byte */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+        DmaTcdList[5u].Value = 1u;   /* bytes to transfer for each request */
+    }
+    else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+    {
+        DmaTcdList[2u].Value = 2u;  /* src offset is 2 bytes */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+        DmaTcdList[5u].Value = 2u;   /* bytes to transfer for each request */
+    }
+    else
+    {
+        DmaTcdList[2u].Value = 4u;  /* src offset is 4 bytes */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[5u].Value = 4u;   /* bytes to transfer for each request */
+    }
+    DmaTcdList[6u].Value = 0u; /* no dest offset */
+    DmaTcdList[7u].Value = NumberDmaIterWrite; /* iteration count */
+    DmaTcdList[8u].Value = 1u; /* disable hardware request when major loop complete */
+    if (NULL_PTR == State->TxBuffer)
+    {
+        /* send default Data */
+        DmaTcdList[0u].Value = (uint32)&State->ExternalDevice->DeviceParams->DefaultData; /* src address read */
+        DmaTcdList[2u].Value = 0u;  /* src offset is 0 byte */
+    }
+    else
+    {
+        DmaTcdList[0u].Value = (uint32)State->TxBuffer; /* src address read */
+    }
+    /* write TCD for TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 9u);
+
+    /* Enable TX DMA HW request */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+
+/**
+* @brief   This function will configure hardware TCDs for the channels TX DMA, RX DMA 
+*          according to current transfer Configuration. DMA channels will be started at the end of the function.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Flexio_Spi_Ip_RxDmaConfig(uint8 Instance)
+{
+    const FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoReads;
+    uint8 RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+
+    /* Limits number of major count */
+    if (FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    /* Update buffers index */
+    State->RxIndex = NumberDmaIterWrite;
+
+    /* configure RX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+
+    /* LSB mode */
+    if (TRUE == State->ExternalDevice->DeviceParams->Lsb)
+    {
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            DmaTcdList[0u].Value = (uint32)&Base->SHIFTBUF[RxShifterIndex] + 3u; /* src address read */
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            DmaTcdList[0u].Value = (uint32)&Base->SHIFTBUF[RxShifterIndex] + 2u; /* src address read */
+        }
+        else 
+        {
+            DmaTcdList[0u].Value = (uint32)&Base->SHIFTBUF[RxShifterIndex]; /* src address read */
+        }
+    }
+    else /* MSB mode */
+    {
+        DmaTcdList[0u].Value = (uint32)&Base->SHIFTBUFBIS[RxShifterIndex]; /* src address read */
+    }
+    
+    DmaTcdList[2u].Value = 0u;  /* no src offset */
+    if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+        DmaTcdList[5u].Value = 1u;   /* 1 byte to transfer for each request */
+        DmaTcdList[6u].Value = 1u; /* dest offset is 1 bytes */
+    }
+    else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+        DmaTcdList[5u].Value = 2u;   /* 2 bytes to transfer for each request */
+        DmaTcdList[6u].Value = 2u; /* dest offset is 2 bytes */
+    }
+    else
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[5u].Value = 4u;   /* 4 bytes to transfer for each request */
+        DmaTcdList[6u].Value = 4u; /* dest offset is 4 bytes */
+    }
+    if (NULL_PTR == State->RxBuffer)
+    {
+        /* Discard Data */
+        DmaTcdList[1u].Value = (uint32)&Flexio_Spi_Ip_u32DiscardData;    /* dest address write*/
+        DmaTcdList[6u].Value = 0u; /* dest offset is 0 bytes */
+    }
+    else
+    {
+        DmaTcdList[1u].Value = (uint32)State->RxBuffer;    /* dest address write*/
+    }
+    DmaTcdList[7u].Value = NumberDmaIterWrite; /* iteration count */
+    DmaTcdList[8u].Value = 1u; /* disable hardware request when major loop complete */
+    /* write TCD for RX DMA channel */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 9u);
+
+    /* Enable RX DMA HW request */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+
+static void Flexio_Spi_Ip_TxDmaContinueTransfer(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex;
+    uint8 TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+
+    /* Limits number of major count */
+    if (FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    State->TxIndex += NumberDmaIterWrite;
+
+    /* Update TX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[0u].Value = NumberDmaIterWrite;    /* iteration count */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+
+    /* Disable TX DMA request to avoid overflow because RX DMA needs time to be initialized for next transfer,
+    TX DMA request will be enabled later when RX DMA complete by Flexio_Spi_Ip_RxDmaContinueTransfer. */
+    Flexio_Mcl_Ip_SetShifterDMARequest(Base, 1u << TxShifterIndex, FALSE);
+    
+    /* Enable TX DMA HW request for TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+    /* Push first frame to TX FIFO to ensure that previous received frame will be pushed to RX FIFO and RX DMA can be completed in the case of CS continue */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_SOFTWARE_REQUEST);
+}
+
+static void Flexio_Spi_Ip_RxDmaContinueTransfer(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State =  Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoReads - State->RxIndex;
+    uint8 TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+
+    /* Limits number of major count */
+    if (FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = FLEXIO_SPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    State->RxIndex += NumberDmaIterWrite;
+
+    /* Update RX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[0u].Value = NumberDmaIterWrite;    /* iteration count */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u);
+
+    /* Enable DMA HW request for RX DMA channel */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+    /* Enable TX DMA request due to it is disabled in Flexio_Spi_Ip_TxDmaContinueTransfer */
+    Flexio_Mcl_Ip_SetShifterDMARequest(Base, 1u << TxShifterIndex, TRUE);
+}
+
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+/**
+* @brief   This function will process TX DMA transfer complete interrupt. 
+* @details This function will process continue transfer or end of transfer via TX DMA.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+* @implements Flexio_Spi_Ip_IrqTxDmaHandler_Activity
+*/
+void Flexio_Spi_Ip_IrqTxDmaHandler(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    boolean ErrorFlag = FALSE;
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    boolean IsTxShifterErrorRaised = FALSE;
+    boolean IsRxShifterErrorRaised = FALSE;
+
+    if (NULL_PTR != State)
+    {
+        if (FLEXIO_SPI_IP_BUSY == State->Status)
+        {
+            /* Get Shifters and timers index */
+            TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+            RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+            /* Read error Status and clear flags. */
+            IsTxShifterErrorRaised = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, TxShifterIndex);
+            IsRxShifterErrorRaised = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, RxShifterIndex);
+            /* Clear shifter error flag */
+            Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, TxShifterIndex);
+            Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, RxShifterIndex);
+
+            if (IsTxShifterErrorRaised || IsRxShifterErrorRaised)
+            {
+                /* mark error flag */
+                ErrorFlag = TRUE;
+            }
+            else
+            {
+                if (State->ExpectedFifoWrites != State->TxIndex)
+                {
+                    /* Transfer is not finished => update TX pointers */
+                    Flexio_Spi_Ip_TxDmaContinueTransfer(Instance);
+                }
+                else
+                {
+                    /* Disable TX DMA request to avoid overflow because RX DMA needs time to be initialized for next transfer,
+                    TX DMA request will be enabled later when RX DMA completed and next transfer initialized by Flexio_Spi_Ip_AsyncTransmit. */
+                    Flexio_Mcl_Ip_SetShifterDMARequest(Base, 1u << TxShifterIndex, FALSE);
+                    Flexio_Spi_Ip_TxDmaConfig(Instance);
+                }
+            }
+            
+            if (TRUE == ErrorFlag)
+            {
+                /* Disable DMA requests. */
+                Flexio_Mcl_Ip_SetShifterDMARequest(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+
+                /* Disable RX DMA HW request because may RX DMA is not completed, no need to apply for TX DMA due to DMA HW request is cleared automatically */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+                State->Status = FLEXIO_SPI_IP_FAULT;
+                if (State->Callback != NULL_PTR)
+                {
+                    State->Callback(Instance, FLEXIO_SPI_IP_EVENT_FAULT);
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Driver is initialized but there was no poll request*/
+        /* nothing to do */
+    }
+}
+
+/**
+* @brief   This function will process RX DMA transfer complete interrupt. 
+* @details This function will process continue transfer or end of transfer via RX DMA.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+* @implements Flexio_Spi_Ip_IrqRxDmaHandler_Activity
+*/
+void Flexio_Spi_Ip_IrqRxDmaHandler(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    boolean ErrorFlag = FALSE;
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    boolean EndOfTransferFlag = FALSE;
+    boolean IsTxShifterErrorRaised = FALSE;
+    boolean IsRxShifterErrorRaised = FALSE;
+
+
+    if (NULL_PTR != State)
+    {
+        if (FLEXIO_SPI_IP_BUSY == State->Status)
+        {
+            /* Get Shifters and timers index */
+            TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+            RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+            /* Read error Status and clear flags. */
+            IsTxShifterErrorRaised = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, TxShifterIndex);
+            IsRxShifterErrorRaised = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, RxShifterIndex);
+            /* Clear shifter error flag */
+            Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, TxShifterIndex);
+            Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, RxShifterIndex);
+
+            if (IsTxShifterErrorRaised || IsRxShifterErrorRaised)
+            {
+                 /* mark error flag */
+                ErrorFlag = TRUE;
+            }
+            else
+            {
+                if (State->ExpectedFifoReads != State->RxIndex)
+                {
+                    /* Transfer is not finished => update RX pointers */
+                    Flexio_Spi_Ip_RxDmaContinueTransfer(Instance);
+                }
+                else
+                {
+                    EndOfTransferFlag = TRUE;
+                }
+            }
+
+            if ((TRUE == EndOfTransferFlag) || (TRUE == ErrorFlag))
+            {
+                /* Disable DMA requests. */
+                Flexio_Mcl_Ip_SetShifterDMARequest(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+
+                if (TRUE == ErrorFlag)
+                {
+                    State->Status = FLEXIO_SPI_IP_FAULT;
+                    /* Disable TX DMA HW request because may TX DMA is not completed, no need to apply for RX DMA due to DMA HW request is cleared automatically */
+                    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+                }
+                else
+                {
+                    State->Status = FLEXIO_SPI_IP_IDLE;
+                }
+                if (State->Callback != NULL_PTR)
+                {
+                    if (TRUE == ErrorFlag)
+                    {
+                        State->Callback(Instance, FLEXIO_SPI_IP_EVENT_FAULT);
+                    }
+                    else
+                    {
+                        State->Callback(Instance, FLEXIO_SPI_IP_EVENT_END_TRANSFER);
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Driver is initialized but there was no poll request*/
+        /* nothing to do */
+    }
+}
+#endif /* (STD_ON == FLEXIO_SPI_IP_DMA_USED) */
+
+#if (STD_ON == FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT)
+/**
+* @brief This function will set UAA bit in REG_PROT for SPI unit
+*/
+static void Flexio_Spi_Ip_SetUserAccess(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    
+    SET_USER_ACCESS_ALLOWED((uint32)Base,FLEXIO_SPI_IP_PROT_MEM_U32);
+}
+
+/**
+* @brief This function will enable writing all SPI registers under protection in User mode by configuring REG_PROT
+*/
+static void Flexio_Spi_Ip_SetUserAccessAllowed(uint8 Instance)
+{
+    OsIf_Trusted_Call1param(Flexio_Spi_Ip_SetUserAccess, Instance);
+}
+#endif /* FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT */
+
+/**
+* @brief This function will write to Shifter buffer
+*/
+static void Flexio_Spi_Ip_WriteShifterBuffer
+(
+    uint8 Instance,
+    uint8 TxShifterIndex
+)
+{
+    Flexio_Spi_Ip_StateStructureType *State;
+    uint32 Data;
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    
+    if (NULL_PTR != State->TxBuffer)
+    {
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            Data = *((uint8*)(&State->TxBuffer[State->TxIndex]));
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            Data = *((uint16*)(&State->TxBuffer[2u * State->TxIndex]));
+        }
+        else
+        {
+            Data = *((uint32*)(&State->TxBuffer[4u * State->TxIndex]));
+        }
+    }
+    else
+    {
+        Data = State->ExternalDevice->DeviceParams->DefaultData;
+    }
+    /* Write to SHIFTBUF */
+    /* LSB mode */
+    if (TRUE == State->ExternalDevice->DeviceParams->Lsb)
+    {
+        Base->SHIFTBUF[TxShifterIndex] = Data;
+    }
+    else /* MSB mode */
+    {
+        Data = Data << (32u - State->ExternalDevice->DeviceParams->FrameSize);
+        Base->SHIFTBUFBIS[TxShifterIndex] = Data;
+    }
+    State->TxIndex++;
+}
+
+/**
+* @brief This function will write to Shifter buffer
+*/
+static void Flexio_Spi_Ip_ReadShifterBuffer
+(
+    uint8 Instance,
+    uint8 RxShifterIndex
+)
+{
+    Flexio_Spi_Ip_StateStructureType *State;
+    uint32 Data = 0u;
+    const FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    
+    /* LSB mode */
+    if (TRUE == State->ExternalDevice->DeviceParams->Lsb)
+    {
+        Data = Base->SHIFTBUF[RxShifterIndex];
+        Data = Data >> (32u - State->ExternalDevice->DeviceParams->FrameSize);
+    }
+    else /* MSB mode */
+    {
+        Data = Base->SHIFTBUFBIS[RxShifterIndex];
+    }
+
+    if (NULL_PTR != State->RxBuffer)
+    {
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            *((uint8*)(&State->RxBuffer[State->RxIndex])) = (uint8)Data;
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            *((uint16*)(&State->RxBuffer[2u * State->RxIndex])) = (uint16)Data;
+        }
+        else
+        {
+            *((uint32*)(&State->RxBuffer[4u * State->RxIndex])) = Data;
+        }
+    }
+    else
+    {
+        /* Discard data */
+        (void)Data;
+    }
+
+    State->RxIndex++;
+}
+
+/**
+* @brief This function will clear all shifter and timer Configuration registers at beginning of transfer function.
+*/
+static void Flexio_Spi_Ip_ClearShifterTimerRegisters(
+                                                        uint8 Instance
+                                                    )
+{
+    const Flexio_Spi_Ip_StateStructureType *State;
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+#if (STD_ON == FLEXIO_SPI_IP_SLAVE_SUPPORT)
+    uint8 ClkTimerIndex = 0u;
+#endif
+    State = (const Flexio_Spi_Ip_StateStructureType *)Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+    RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+    
+    Base->SHIFTCTL[TxShifterIndex] = (uint32)0U;
+    Base->SHIFTCTL[RxShifterIndex] = (uint32)0U;
+    
+    Base->SHIFTCFG[TxShifterIndex] = (uint32)0U;
+    Base->SHIFTCFG[RxShifterIndex] = (uint32)0U;
+#if (STD_ON == FLEXIO_SPI_IP_SLAVE_SUPPORT)
+    ClkTimerIndex = State->PhyUnitConfig->ClkTimerIndex;
+    if (State->PhyUnitConfig->SlaveMode)
+    {
+        Base->TIMCMP[ClkTimerIndex] = (uint32)0U;
+        Base->TIMCFG[ClkTimerIndex] = (uint32)0U;
+        Base->TIMCTL[ClkTimerIndex] = (uint32)0U;
+    }
+#endif
+}
+
+/**
+* @brief   FLEXIO_SPI peripheral initialization.
+* @details This function initializes the SPI instance from Configurations in Slave or Master mode 
+*          and other hardware specific parameters. This function won't initialize spi bus parameters.
+*
+* @param[in]      Configuration      Pointer to configurations of the hardware unit.
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_Init(const Flexio_Spi_Ip_ConfigType *Configuration)
+{
+    Flexio_Spi_Ip_StateStructureType* State;
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    uint8 FlexioInstance = 0u;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Configuration != NULL_PTR);
+    #endif
+    FlexioInstance = Configuration->Instance;
+    State = Flexio_Spi_Ip_apxStateStructureArray[FlexioInstance];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State == NULL_PTR);
+    #endif
+    {
+        Flexio_Spi_Ip_apxStateStructureArray[FlexioInstance] = &Flexio_Spi_Ip_axStateStructure[Configuration->StateIndex];
+        State = Flexio_Spi_Ip_apxStateStructureArray[FlexioInstance];
+        State->PhyUnitConfig = Configuration;
+        /* get  Framesize, LSB/MSB, Clock mode, Default Data, Slave mode values if this fucntion is only called from IP labyer */
+        #if ( STD_ON == FLEXIO_SPI_IP_DUAL_CLOCK_MODE)
+        State->ClockMode = FLEXIO_SPI_IP_NORMAL_CLOCK;
+        #endif
+        /* set State to idle */
+        State->Status = FLEXIO_SPI_IP_IDLE;
+        /* Set to Polling mode by default */
+        (void)Flexio_Spi_Ip_UpdateTransferMode(FlexioInstance, FLEXIO_SPI_IP_POLLING);
+    }
+    return Status;
+}
+
+/**
+* @brief   This function performs the de-initialization of a specific peripheral unit.
+* @details This function de-initializes all configured values
+*          in all registers.
+*
+* @param[in]     Instance      Index of the hardware instance.
+*
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_DeInit(uint8 Instance)
+{
+    const Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    DevAssert(NULL_PTR != State);
+    #endif
+    if (FLEXIO_SPI_IP_BUSY == State->Status)
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+
+        Flexio_Spi_Ip_apxStateStructureArray[Instance] = NULL_PTR;
+    }
+    return Status;
+}
+/**
+* @brief   This function performs the synchronous transmission.
+* @details This function performs spi transfer by synchronous method
+*
+* @param[in]     Sequence      Specifies the sequence for which we will have
+*                              the synchronous transmission
+*
+* @return Flexio_Spi_Ip_StatusType
+* @retval FLEXIO_SPI_IP_STATUS_SUCCESS  Transmission command has been completed
+* @retval FLEXIO_SPI_IP_STATUS_FAIL     Transmission command has been incompleted
+*
+* @implements Flexio_Spi_Ip_SyncTransmit
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_SyncTransmit(
+                                                    const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice,
+                                                    uint8* TxBuffer,
+                                                    uint8* RxBuffer,
+                                                    uint16 Length,
+                                                    uint32 TimeOut
+                                                   )
+{
+    Flexio_Spi_Ip_StateStructureType *State;
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(TimeOut, FLEXIO_SPI_IP_TIMEOUT_METHOD);
+    uint32 CurrentTicks = 0u;
+    uint32 ElapsedTicks = 0u; /* elapsed will give timeout */
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    uint8 InstanceFlexio = 0u;
+    boolean TxShifterError = FALSE;
+    boolean RxShifterError = FALSE;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    DevAssert(0u != Length);
+    DevAssert(0u != TimeOut);
+    #endif
+    InstanceFlexio = ExternalDevice->Instance;
+    State = Flexio_Spi_Ip_apxStateStructureArray[InstanceFlexio];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17();
+    if (FLEXIO_SPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17();
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        /* Mark the hardware as busy. */
+        State->Status = FLEXIO_SPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17();
+
+        /* Get Shifters and timers index */
+        TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+        RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+
+        /* Update State structure */
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            State->ExpectedFifoWrites = Length;
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            State->ExpectedFifoWrites = Length/2u;
+        }
+        else
+        {
+            State->ExpectedFifoWrites = Length/4u;
+        }
+
+        /* Update Data buffer */
+        State->ExpectedFifoReads = State->ExpectedFifoWrites;
+        State->TxIndex = 0u;
+        State->TxBuffer = TxBuffer;
+        State->RxIndex = 0u;
+        State->RxBuffer = RxBuffer;
+        /* Configure timer, shifter registers to start transfer */
+        Flexio_Spi_Ip_ConfigExternalDevice(State);
+
+        CurrentTicks = OsIf_GetCounter(FLEXIO_SPI_IP_TIMEOUT_METHOD); /* initialize current counter */
+        while (((State->RxIndex != State->ExpectedFifoReads) || (State->TxIndex != State->ExpectedFifoWrites)) && (FLEXIO_SPI_IP_STATUS_SUCCESS == Status))
+        {
+            ElapsedTicks = 0;
+            /* Process transmitting and receiving data */
+            Flexio_Spi_Ip_SyncTransmitProcessData(InstanceFlexio);
+
+            /* Check if errors like overflow or underflow are reported in Status register. */
+            TxShifterError = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, TxShifterIndex);
+            RxShifterError = Flexio_Mcl_Ip_GetShifterErrorStatus(Base, RxShifterIndex);
+            if (TxShifterError || RxShifterError)
+            {
+                /* If underflow */
+                if (TxShifterError)
+                {
+                    Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, TxShifterIndex);
+                }
+                /* If overflow */
+                if (RxShifterError)
+                {
+                    Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, RxShifterIndex);
+                }
+                Status = FLEXIO_SPI_IP_FIFO_ERROR;
+            }
+            ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, FLEXIO_SPI_IP_TIMEOUT_METHOD);
+            if (ElapsedTicks >= TimeoutTicks)
+            {
+                Status = FLEXIO_SPI_IP_TIMEOUT;
+            }
+        }
+    }
+    if (FLEXIO_SPI_IP_STATUS_SUCCESS != Status)
+    {
+        State->Status = FLEXIO_SPI_IP_FAULT;
+    }
+    else
+    {
+        State->Status = FLEXIO_SPI_IP_IDLE;
+    }
+    return Status;
+}
+
+/**
+* @brief   This function performs the asynchronous transmission.
+* @details This function performs spi transfer by asynchronous method
+*
+* @param[in]     Sequence      Specifies the sequence for which we will have
+*                              the asynchronous transmission
+*
+* @return Flexio_Spi_Ip_StatusType
+* @retval FLEXIO_SPI_IP_STATUS_SUCCESS  Transmission command has been started
+* @retval FLEXIO_SPI_IP_STATUS_FAIL     Transmission command has not been accepted
+*
+* @implements Flexio_Spi_Ip_AsyncTransmit
+*/
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_AsyncTransmit(
+                                       const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice,
+                                       uint8* TxBuffer,
+                                       uint8* RxBuffer,
+                                       uint16 Length,
+                                       Flexio_Spi_Ip_CallbackType Callback
+                                      )
+{
+    Flexio_Spi_Ip_StateStructureType *State;
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    uint8 InstanceFlexio = 0u;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    DevAssert(0u != Length);
+    #endif
+    InstanceFlexio = ExternalDevice->Instance;
+    State = Flexio_Spi_Ip_apxStateStructureArray[InstanceFlexio];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    DevAssert(
+              (TRUE != State->PhyUnitConfig->DmaUsed) ||
+              (FALSE != ExternalDevice->DeviceParams->Lsb) ||
+              (
+                (8u != ExternalDevice->DeviceParams->FrameSize) &&
+                (16u != ExternalDevice->DeviceParams->FrameSize) &&
+                (32u != ExternalDevice->DeviceParams->FrameSize)
+              )
+             );
+    #endif
+    #endif /* (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT) */
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18();
+    if (FLEXIO_SPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18();
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        /* Mark the hardware as busy. */
+        State->Status = FLEXIO_SPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18();
+
+        /* Get Shifters and timers index */
+        TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+        RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+
+        /* Update State structure */
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            State->ExpectedFifoWrites = Length;
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            State->ExpectedFifoWrites = Length/2u;
+        }
+        else
+        {
+            State->ExpectedFifoWrites = Length/4u;
+        }
+
+        /* Update Data buffer */
+        State->ExpectedFifoReads = State->ExpectedFifoWrites;
+        State->TxIndex = 0u;
+        State->TxBuffer = TxBuffer;
+        State->RxIndex = 0u;
+        State->RxBuffer = RxBuffer;
+        /* Configure timer, shifter registers to start transfer */
+        Flexio_Spi_Ip_ConfigExternalDevice(State);
+
+        /* Update State structure. */
+        State->Callback = Callback;
+
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        if (FALSE == State->PhyUnitConfig->DmaUsed)
+        #endif
+        {
+            /* Set mode */
+            switch (State->TransferMode)
+            {
+                case FLEXIO_SPI_IP_POLLING:
+                    /* Disable interrupts. It was done at beginning of this function */
+                    break;
+                case FLEXIO_SPI_IP_INTERRUPT:
+                    /* Enable intterrupts. Both tranfer and Error ISRs */
+                    Flexio_Mcl_Ip_SetShifterErrorInterrupt(Base, (1u << TxShifterIndex)|(1u << RxShifterIndex), TRUE);
+                    Flexio_Mcl_Ip_SetShifterInterrupt(Base, (1u << TxShifterIndex)|(1u << RxShifterIndex), TRUE);
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }
+        }
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        else
+        {
+            /* Initialize DMA Configuration for RX before TX*/
+            Flexio_Spi_Ip_RxDmaConfig(InstanceFlexio);
+            if (State->FirstChannel)
+            {
+                Flexio_Spi_Ip_TxDmaConfig(InstanceFlexio);
+            }
+            /* Enable DMA request. */
+            Flexio_Mcl_Ip_SetShifterDMARequest(Base, (1u<<TxShifterIndex)|(1u<<RxShifterIndex), TRUE);
+        }
+        #endif
+    }
+    return Status;
+}
+
+void Flexio_Spi_Ip_ManageBuffers(uint8 Instance)
+{
+    #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    Dma_Ip_LogicChannelStatusType DmaChannelStatus;
+    #endif
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0u];
+    const Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    uint8 ShifterMaskFlag         = (uint8)0U;
+    uint8 ShifterErrMaskFlag      = (uint8)0U;
+    uint8 TxRxMask = 0u;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    DevAssert(NULL_PTR != State);
+    #endif
+    if (FLEXIO_SPI_IP_POLLING == State->TransferMode)
+    {
+        /* Get Shifters and timers index */
+        TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+        RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+        
+        TxRxMask = ((uint8)(1u<<TxShifterIndex) | (uint8)(1u<<RxShifterIndex));
+        
+        ShifterMaskFlag        = (uint8)Flexio_Mcl_Ip_GetAllShifterStatus(Base) & TxRxMask;
+        ShifterErrMaskFlag     = (uint8)Flexio_Mcl_Ip_GetAllShifterErrorStatus(Base) & TxRxMask;
+        /* Clear error flag, transfer flag will be cleared automatically by write/read shifter buffer */
+        Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, TxShifterIndex);
+        Flexio_Mcl_Ip_ClearShifterErrorStatus(Base, RxShifterIndex);
+    
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        if(FALSE == State->PhyUnitConfig->DmaUsed)
+        #endif
+        {
+            /* TX ISR */
+            if ( ((ShifterMaskFlag & (1u<<TxShifterIndex)) != 0u) || ((ShifterErrMaskFlag & (1u<<TxShifterIndex)) != 0u) )
+            {
+                Flexio_Spi_Ip_TransferProcess(Instance, TxShifterIndex, ShifterMaskFlag, ShifterErrMaskFlag);
+            }
+            /* RX ISR */
+            if ( ((ShifterMaskFlag & (1u<<RxShifterIndex)) != 0u) || ((ShifterErrMaskFlag & (1u<<RxShifterIndex)) != 0u) )
+            {
+                Flexio_Spi_Ip_TransferProcess(Instance, RxShifterIndex, ShifterMaskFlag, ShifterErrMaskFlag);
+            }
+        }
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        else
+        {
+            /* Polling RX before TX */
+            (void)Dma_Ip_GetLogicChannelStatus(State->PhyUnitConfig->RxDmaChannel, &DmaChannelStatus);
+            if(TRUE == DmaChannelStatus.Done)
+            {
+                /* Clear DONE bit */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_DONE);
+                Flexio_Spi_Ip_IrqRxDmaHandler(Instance);
+            }
+            
+            (void)Dma_Ip_GetLogicChannelStatus(State->PhyUnitConfig->TxDmaChannel, &DmaChannelStatus);
+            if(TRUE == DmaChannelStatus.Done)
+            {
+                /* Clear DONE bit */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_DONE);
+                Flexio_Spi_Ip_IrqTxDmaHandler(Instance);
+            }
+        }
+        #endif
+    }
+}
+
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateFrameSize(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, uint8 FrameSize)
+{
+    const Flexio_Spi_Ip_StateStructureType* State;
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    DevAssert(FLEXIO_SPI_IP_FRAMESIZE_MAX_U8 >= FrameSize);
+    DevAssert(FLEXIO_SPI_IP_FRAMESIZE_MIN_U8 <= FrameSize);
+    #endif
+    State = Flexio_Spi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Frame size can be changed when no transfers are in progress. */
+    if (FLEXIO_SPI_IP_BUSY != State->Status)
+    {
+        ExternalDevice->DeviceParams->FrameSize = FrameSize;
+    }
+    else
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateLsb(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, boolean Lsb)
+{
+    const Flexio_Spi_Ip_StateStructureType* State;
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    #endif
+    State = Flexio_Spi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Bite order can be changed when no transfers are in progress. */
+    if (FLEXIO_SPI_IP_BUSY != State->Status)
+    {
+        ExternalDevice->DeviceParams->Lsb = Lsb;
+    }
+    else
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateDefaultTransmitData(const Flexio_Spi_Ip_ExternalDeviceType *ExternalDevice, uint32 DefaultData)
+{
+    const Flexio_Spi_Ip_StateStructureType* State;
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    #endif
+    State = Flexio_Spi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Bit order can be changed when no transfers are in progress. */
+    if (FLEXIO_SPI_IP_BUSY != State->Status)
+    {
+        ExternalDevice->DeviceParams->DefaultData = DefaultData;
+    }
+    else
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_UpdateTransferMode(uint8 Instance, Flexio_Spi_Ip_ModeType Mode)
+{
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    #endif
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Transfer mode can be changed when no transfers are in progress. */
+    if (FLEXIO_SPI_IP_BUSY != State->Status)
+    {
+        State->TransferMode = Mode;
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        if(TRUE == State->PhyUnitConfig->DmaUsed)
+        {
+            /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */
+            DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+            switch(Mode)
+            {
+                case FLEXIO_SPI_IP_POLLING:
+                    /* Disable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 0u;
+                    break;
+                case FLEXIO_SPI_IP_INTERRUPT:
+                    /* Enable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 1u;
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }
+            (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+            (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u);
+        }
+        #endif
+    }
+    else
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+ 
+void Flexio_Spi_Ip_Cancel(uint8 Instance)
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    uint8 ClkTimerIndex = 0u;
+    
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    DevAssert(NULL_PTR != State);
+    #endif
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16();
+    if (FLEXIO_SPI_IP_BUSY == State->Status)
+    {
+        /* Get Shifters and timers index */
+        TxShifterIndex = State->PhyUnitConfig->TxShifterIndex;
+        RxShifterIndex = State->PhyUnitConfig->RxShifterIndex;
+        ClkTimerIndex = State->PhyUnitConfig->ClkTimerIndex;
+        
+        /* Disable interrupts and DMA requests. */
+        Flexio_Mcl_Ip_SetShifterInterrupt(Base, (1u<<TxShifterIndex)|(1u<<RxShifterIndex), FALSE);
+        Flexio_Mcl_Ip_SetShifterDMARequest(Base, (1u<<TxShifterIndex)|(1u<<RxShifterIndex), FALSE);
+        /* Disable error interrupt */
+        Flexio_Mcl_Ip_SetShifterErrorInterrupt(Base, (1u << TxShifterIndex) | (1u << RxShifterIndex), FALSE);
+        
+        #if (STD_ON == FLEXIO_SPI_IP_DMA_USED)
+        if(TRUE == State->PhyUnitConfig->DmaUsed)
+        {
+            /* Disable all HW request */
+            (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+            (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+        }
+        #endif
+        /* Remove CLK TIMER Configuration */
+        Base->TIMCMP[ClkTimerIndex] =  (uint32)0u;
+        Base->TIMCFG[ClkTimerIndex] = (uint32)0u;
+        Base->TIMCTL[ClkTimerIndex] = (uint32)0u;
+        
+        /* Clear SHFIBUF */
+        Base->SHIFTBUF[TxShifterIndex] = (uint32)0u;
+        Base->SHIFTBUF[RxShifterIndex] = (uint32)0u;
+        Base->SHIFTBUFBIS[TxShifterIndex] = (uint32)0u;
+        Base->SHIFTBUFBIS[RxShifterIndex] = (uint32)0u;
+        
+        /* set State to idle */
+        State->Status = FLEXIO_SPI_IP_IDLE;
+    }
+    SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16();
+}
+/*****************************************************************************************/
+/**
+* @brief   This function is called by FLEXIO ISRs.
+* @details This function will process activities for flags TDF, RDF, REF and TEF.
+*
+* @param[in]     Instance            Instance of the hardware unit.
+*
+* @implements Flexio_Spi_Ip_IrqHandler_Activity
+*/
+void Flexio_Spi_Ip_IrqHandler(
+                                uint8 ShifterIndex,
+                                uint8 ShifterMaskFlag,
+                                uint8 ShifterErrMaskFlag
+                              )
+{
+    FLEXIO_Type *Base = Flexio_Spi_Ip_apxBases[0];
+    const Flexio_Spi_Ip_StateStructureType* State = NULL_PTR;
+    uint8 TxShifterIndex = 0u;
+    uint8 RxShifterIndex = 0u;
+    uint8 i = 0u;
+    uint8 Instance = 0;
+    uint8 ShifterEnabledIrq     = (uint8)0U;
+    uint8 ShifterErrEnabledIrq  = (uint8)0U;
+    uint8 ShifterEnabledIsrFlag = 0u;
+    uint8 ShifterErrEnabledIrqFlag = 0u;
+    
+    /* Get current instance */
+    for (i=0; i< FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8; i++)
+    {
+       TxShifterIndex = Flexio_Spi_Ip_apxStateStructureArray[i]->PhyUnitConfig->TxShifterIndex;
+       RxShifterIndex = Flexio_Spi_Ip_apxStateStructureArray[i]->PhyUnitConfig->RxShifterIndex;
+       if((ShifterIndex == TxShifterIndex) || (ShifterIndex == RxShifterIndex))
+       {
+           Instance = i;
+           State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+           break;
+       }
+    }
+
+    if (NULL_PTR != State)
+    {
+        ShifterEnabledIrq        = (uint8)Flexio_Mcl_Ip_GetAllShifterInterrupt(Base);
+        ShifterEnabledIsrFlag    = ShifterMaskFlag & (ShifterEnabledIrq & (1u << ShifterIndex));
+
+        ShifterErrEnabledIrq     = (uint8)Flexio_Mcl_Ip_GetAllShifterErrorInterrupt(Base);
+        ShifterErrEnabledIrqFlag = ShifterErrMaskFlag & (ShifterErrEnabledIrq & (1u << ShifterIndex));
+
+        Flexio_Spi_Ip_TransferProcess(Instance, ShifterIndex, ShifterEnabledIsrFlag, ShifterErrEnabledIrqFlag);
+    }
+    else
+    {
+        /* the driver has not been initialized */
+        /* clear all flags */
+        Flexio_Mcl_Ip_ClearShifterStatus(Base, TxShifterIndex);
+        Flexio_Mcl_Ip_ClearShifterStatus(Base, RxShifterIndex);
+    }
+}
+
+Flexio_Spi_Ip_HwStatusType Flexio_Spi_Ip_GetStatus(uint8 Instance)
+{
+    const Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Flexio_Spi_Ip_HwStatusType Status = FLEXIO_SPI_IP_UNINIT;
+    
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    #endif
+    if (NULL_PTR != State)
+    {
+        Status = State->Status;
+    }   
+    return Status;
+}
+
+#if (STD_ON == FLEXIO_SPI_IP_DUAL_CLOCK_MODE)
+Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_SetClockMode(uint8 Instance, Flexio_Spi_Ip_DualClockModeType ClockMode)
+{
+    Flexio_Spi_Ip_StateStructureType* State = Flexio_Spi_Ip_apxStateStructureArray[Instance];
+    Flexio_Spi_Ip_StatusType Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == FLEXIO_SPI_IP_DEV_ERROR_DETECT)
+    DevAssert(FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8 > Instance);
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Clock mode can be changed when no transfers are in progress. */
+    if (FLEXIO_SPI_IP_BUSY != State->Status)
+    {
+        State->ClockMode = ClockMode;
+    }
+    else
+    {
+        Status = FLEXIO_SPI_IP_STATUS_FAIL;
+    }    
+    return Status;
+}
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#endif /*(FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Flexio_Spi_Ip_Irq.c

@@ -0,0 +1,212 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Flexio_Spi_Ip_Irq.c
+*   @implements     Flexio_Spi_Ip_Irq.c_Artifact
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file.
+*   @details Generated Post-Build(PB) configuration file.
+*
+*   @addtogroup FLEXIO_SPI_IP_DRIVER Flexio_Spi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Flexio_Spi_Ip.h"
+
+/*==================================================================================================
+*                                       SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_IRQ_VENDOR_ID_C                      43
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C       4
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_MINOR_VERSION_C       4
+#define FLEXIO_SPI_IP_IRQ_AR_RELEASE_REVISION_VERSION_C    0
+#define FLEXIO_SPI_IP_IRQ_SW_MAJOR_VERSION_C               1
+#define FLEXIO_SPI_IP_IRQ_SW_MINOR_VERSION_C               0
+#define FLEXIO_SPI_IP_IRQ_SW_PATCH_VERSION_C               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Flexio_Spi_Ip_Irq.h and Flexio_Spi_Ip.c are of the same vendor */
+#if (FLEXIO_SPI_IP_IRQ_VENDOR_ID_C != FLEXIO_SPI_IP_VENDOR_ID)
+    #error "Flexio_Spi_Ip_Irq.h and Flexio_Spi_Ip.h have different vendor ids"
+#endif
+
+/* Check if Flexio_Spi_Ip_Irq.h file and Flexio_Spi_Ip.h file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_IRQ_AR_RELEASE_MAJOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_IRQ_AR_RELEASE_MINOR_VERSION_C    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_IRQ_AR_RELEASE_REVISION_VERSION_C != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip_Irq.h and Flexio_Spi_Ip.h are different"
+#endif
+
+#if ((FLEXIO_SPI_IP_IRQ_SW_MAJOR_VERSION_C != FLEXIO_SPI_IP_SW_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_IRQ_SW_MINOR_VERSION_C != FLEXIO_SPI_IP_SW_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_IRQ_SW_PATCH_VERSION_C != FLEXIO_SPI_IP_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Flexio_Spi_Ip_Irq.h and Flexio_Spi_Ip.h are different"
+#endif
+/*==================================================================================================
+*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+    
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef FLEXIO_SPI_IP_0_ENABLED
+    #if (FLEXIO_SPI_IP_0_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_0_IrqTxDmaHandler(void);
+void Flexio_Spi_Ip_FLEXIO_SPI_0_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_1_ENABLED
+    #if (FLEXIO_SPI_IP_1_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_1_IrqTxDmaHandler(void);
+void Flexio_Spi_Ip_FLEXIO_SPI_1_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_2_ENABLED
+    #if (FLEXIO_SPI_IP_2_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_2_IrqTxDmaHandler(void);
+void Flexio_Spi_Ip_FLEXIO_SPI_2_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_3_ENABLED
+    #if (FLEXIO_SPI_IP_3_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_3_IrqTxDmaHandler(void);
+void Flexio_Spi_Ip_FLEXIO_SPI_3_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+#ifdef FLEXIO_SPI_IP_0_ENABLED
+    #if (FLEXIO_SPI_IP_0_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_0_IrqTxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqTxDmaHandler(0u);
+}
+void Flexio_Spi_Ip_FLEXIO_SPI_0_IrqRxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqRxDmaHandler(0u);
+}
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_1_ENABLED
+    #if (FLEXIO_SPI_IP_1_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_1_IrqTxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqTxDmaHandler(1u);
+}
+void Flexio_Spi_Ip_FLEXIO_SPI_1_IrqRxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqRxDmaHandler(1u);
+}
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_2_ENABLED
+    #if (FLEXIO_SPI_IP_2_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_2_IrqTxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqTxDmaHandler(2u);
+}
+void Flexio_Spi_Ip_FLEXIO_SPI_2_IrqRxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqRxDmaHandler(2u);
+}
+        #endif
+    #endif
+#endif
+#ifdef FLEXIO_SPI_IP_3_ENABLED
+    #if (FLEXIO_SPI_IP_3_ENABLED == STD_ON)
+        #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+void Flexio_Spi_Ip_FLEXIO_SPI_3_IrqTxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqTxDmaHandler(3u);
+}
+void Flexio_Spi_Ip_FLEXIO_SPI_3_IrqRxDmaHandler(void)
+{
+    Flexio_Spi_Ip_IrqRxDmaHandler(3u);
+}
+        #endif
+    #endif
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#endif /*(FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Lpspi_Ip.c

@@ -0,0 +1,3020 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Lpspi_Ip.c
+*   
+*
+*   @brief   LPSPI low-level driver implementations.
+*   @details LPSPI low-level driver implementations.
+*
+*   @addtogroup LPSPI_DRIVER Lpspi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Mcal.h"
+#include "Lpspi_Ip.h"
+#include "Lpspi_Ip_Cfg.h"
+#include "OsIf.h"
+#if (STD_ON == LPSPI_IP_DMA_USED)
+    #include "Dma_Ip.h"
+#endif
+#if (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+   #define USER_MODE_REG_PROT_ENABLED   (LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+   #include "RegLockMacros.h"
+#endif
+#include "SchM_Spi.h"
+#if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    #include "Devassert.h"
+#endif
+
+/*==================================================================================================
+*                                       SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define LPSPI_IP_VENDOR_ID_C                      43
+#define LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C       4
+#define LPSPI_IP_AR_RELEASE_MINOR_VERSION_C       4
+#define LPSPI_IP_AR_RELEASE_REVISION_VERSION_C    0
+#define LPSPI_IP_SW_MAJOR_VERSION_C               1
+#define LPSPI_IP_SW_MINOR_VERSION_C               0
+#define LPSPI_IP_SW_PATCH_VERSION_C               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION_C != MCAL_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Lpspi_Ip.c and Mcal.h are different"
+    #endif
+
+    #if (STD_ON == LPSPI_IP_DMA_USED)
+        /* Check if current file and Dma_Ip header file are of the same Autosar version */
+        #if ((DMA_IP_AR_RELEASE_MAJOR_VERSION_H != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C) || \
+             (DMA_IP_AR_RELEASE_MINOR_VERSION_H != LPSPI_IP_AR_RELEASE_MINOR_VERSION_C))
+            #error "AutoSar Version Numbers of Lpspi_Ip.c and Dma_Ip.h are different"
+        #endif
+    #endif
+    
+    #if (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+        #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
+             (LPSPI_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
+            #error "AutoSar Version Numbers of Lpspi_Ip.c and RegLockMacros.h are different"
+        #endif
+    #endif
+
+    /* Check if the current file and SchM_Spi.h header file are of the same version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_SPI_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_SPI_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Lpspi_Ip.c and SchM_Spi.h are different"
+    #endif
+
+    /* Check if the current file and OsIf.h header file are of the same version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Lpspi_Ip.c and OsIf.h are different"
+    #endif
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+        /* Check if the current file and Devassert.h header file are of the same version */
+        #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
+             (LPSPI_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION) \
+            )
+            #error "AutoSar Version Numbers of Lpspi_Ip.c and Devassert.h are different"
+        #endif
+    #endif /* (STD_ON == LPSPI_IP_DEV_ERROR_DETECT) */
+#endif
+
+/* Check if Lpspi_Ip.h and Lpspi_Ip.c are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID != LPSPI_IP_VENDOR_ID_C)
+    #error "Lpspi_Ip.h and Lpspi_Ip.c have different vendor ids"
+#endif
+/* Check if Lpspi_Ip.h file and Lpspi_Ip.c file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION != LPSPI_IP_AR_RELEASE_MINOR_VERSION_C) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION != LPSPI_IP_AR_RELEASE_REVISION_VERSION_C))
+#error "AutoSar Version Numbers of Lpspi_Ip.h and Lpspi_Ip.c are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION != LPSPI_IP_SW_MAJOR_VERSION_C) || \
+     (LPSPI_IP_SW_MINOR_VERSION != LPSPI_IP_SW_MINOR_VERSION_C) || \
+     (LPSPI_IP_SW_PATCH_VERSION != LPSPI_IP_SW_PATCH_VERSION_C))
+#error "Software Version Numbers of Lpspi_Ip.h and Lpspi_Ip.c are different"
+#endif
+
+/* Check if Lpspi_Ip_Cfg.h and Lpspi_Ip.c are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID_CFG != LPSPI_IP_VENDOR_ID_C)
+    #error "Lpspi_Ip_Cfg.h and Lpspi_Ip.c have different vendor ids"
+#endif
+/* Check if Lpspi_Ip_Cfg.h file and Lpspi_Ip.c file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_C) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != LPSPI_IP_AR_RELEASE_MINOR_VERSION_C) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION_CFG != LPSPI_IP_AR_RELEASE_REVISION_VERSION_C))
+#error "AutoSar Version Numbers of Lpspi_Ip_Cfg.h and Lpspi_Ip.c are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION_CFG != LPSPI_IP_SW_MAJOR_VERSION_C) || \
+     (LPSPI_IP_SW_MINOR_VERSION_CFG != LPSPI_IP_SW_MINOR_VERSION_C) || \
+     (LPSPI_IP_SW_PATCH_VERSION_CFG != LPSPI_IP_SW_PATCH_VERSION_C))
+#error "Software Version Numbers of Lpspi_Ip_Cfg.h and Lpspi_Ip.c are different"
+#endif
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+#if (STD_ON == LPSPI_IP_DMA_USED)
+    /* the maximum of Major loop when Minor loop Channel Linking Disabled */
+    #define LPSPI_IP_DMA_MAX_ITER_CNT_U16 ((uint16)0x7FFFu)
+#endif
+
+/**
+* @brief SR mask
+*/
+#define LPSPI_IP_SR_W1C_MASK_U32    (uint32)((uint32)LPSPI_SR_WCF_MASK | (uint32)LPSPI_SR_FCF_MASK | (uint32)LPSPI_SR_TCF_MASK | \
+                                             (uint32)LPSPI_SR_TEF_MASK | (uint32)LPSPI_SR_REF_MASK | (uint32)LPSPI_SR_DMF_MASK)
+                                            
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+                                    GLOBAL VARIABLES
+==================================================================================================*/
+#if (STD_ON == LPSPI_IP_DMA_USED)
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+static Lpspi_Ip_StateStructureType Lpspi_Ip_axStateStructure[LPSPI_IP_NUMBER_OF_INSTANCES];
+#if (STD_ON == LPSPI_IP_DMA_USED)
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+
+#if (STD_ON == LPSPI_IP_DMA_USED)
+    #define SPI_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
+    #include "Spi_MemMap.h"
+static uint32 Lpspi_Ip_u32DiscardData;
+    #define SPI_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
+    #include "Spi_MemMap.h"
+#endif
+
+#define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+Lpspi_Ip_StateStructureType* Lpspi_Ip_apxStateStructureArray[LPSPI_INSTANCE_COUNT];
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#define SPI_START_SEC_CONST_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+static LPSPI_Type* const Lpspi_Ip_apxBases[LPSPI_INSTANCE_COUNT] = IP_LPSPI_BASE_PTRS;
+
+#define SPI_STOP_SEC_CONST_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+LOCAL_INLINE void Lpspi_Ip_ReadDataFromFifo(uint8 Instance, uint8 NumberOfReads);
+LOCAL_INLINE void Lpspi_Ip_PushDataToFifo(uint8 Instance, uint8 NumberOfWrites);
+static void Lpspi_Ip_ChannelFinished(uint8 Instance, boolean ErrorFlag);
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+static void Lpspi_Ip_TransferProcessHalfDuplex(uint8 Instance);
+static boolean Lpspi_Ip_HalfDupleTransmitChannelComplete(uint8 Instance);
+LOCAL_INLINE boolean Lpspi_Ip_HalfDuplexTransmitProcess(uint8 Instance, uint8 NumberOfWrites);
+LOCAL_INLINE void Lpspi_Ip_HalfDuplexPushDataToFifo(uint8 Instance, uint8 NumberOfWrites);
+static void Lpspi_Ip_HalfDuplexPrepare(uint8 Instance, uint8* Buffer);
+#endif
+static void Lpspi_Ip_TransferProcess(uint8 Instance);
+static void Lpspi_TransmitTxInit(uint8 Instance,
+                                 uint8* TxBuffer,
+                                 uint8 TxFrameSize,
+                                 boolean TxLsb,
+                                 uint16 NumberOfFrames
+                                );
+static void Lpspi_TransmitRxInit(uint8 Instance,
+                                 uint8* RxBuffer,
+                                 uint8 RxFrameSize,
+                                 uint16 NumberOfFrames
+                                );
+#if (STD_ON == LPSPI_IP_DMA_USED)
+static void Lpspi_Ip_TxDmaConfig(uint8 Instance);
+static void Lpspi_Ip_RxDmaConfig(uint8 Instance);
+static void Lpspi_Ip_TxDmaContinueTransfer(uint8 Instance);
+static void Lpspi_Ip_RxDmaContinueTransfer(uint8 Instance);
+
+#if (STD_ON == LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT)
+static void Lpspi_Ip_DmaFastConfig(uint8 Instance, const Lpspi_Ip_FastTransferType *FastTransferCfg, uint8 NumberOfTransfer);
+static void Lpspi_Ip_RxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint8 DisHwReq);
+static void Lpspi_Ip_RxDmaTcdSGInit(uint8 Instance);
+static void Lpspi_Ip_TxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint8 DisHwReq, const uint32 *DefaultDataAddress);
+static void Lpspi_Ip_TxDmaTcdSGInit(uint8 Instance);
+static void Lpspi_Ip_CmdTxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint32 CmdAdd, uint8 DisHwReq);
+#endif
+#endif
+#if (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+static void Lpspi_Ip_SetUserAccess(uint8 Instance);
+static void Lpspi_Ip_SetUserAccessAllowed(uint8 Instance);
+#endif /* LPSPI_IP_ENABLE_USER_MODE_SUPPORT */
+#if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+static void Lpspi_Ip_CheckValidParameters
+(
+    const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+    uint16 Length
+);
+#endif
+#if (STD_ON == LPSPI_IP_DMA_USED)
+static void Lpspi_Ip_TxDmaFinishTransfer
+(
+    const uint8 Instance
+);
+#endif /* (STD_ON == LPSPI_IP_DMA_USED) */
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+/**
+* @brief   This function will read Data from RX FIFO.
+* @details This function will read Data from RX FIFO.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @param[in]     NumberOfReads      Number of Data can be read from RX FIFO.
+* @return void
+*/
+LOCAL_INLINE void Lpspi_Ip_ReadDataFromFifo(uint8 Instance, uint8 NumberOfReads)
+{
+    const LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 Data = 0u;
+    uint8 Index = 0u;
+
+    /* To increase the performance of transfer, we will reduce the checking conditions in per "for" statement so we should have more than 1 "for" statement here */   
+    if (NULL_PTR != State->RxBuffer)
+    {
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            for (Index = 0; Index < NumberOfReads; Index++)
+            {
+                Data = Base->RDR;
+                *((uint8*)(&State->RxBuffer[State->RxIndex + Index])) = (uint8)Data;
+            }
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            for (Index = 0; Index < NumberOfReads; Index++)
+            {
+                Data = Base->RDR;
+                *((uint16*)(&State->RxBuffer[2u * (State->RxIndex + Index)])) = (uint16)Data;
+            }
+        }
+        else
+        {
+            for (Index = 0; Index < NumberOfReads; Index++)
+            {
+                Data = Base->RDR;
+                *((uint32*)(&State->RxBuffer[4u * (State->RxIndex + Index)])) = (uint32)Data;
+            }
+        }
+    }
+    else
+    {
+        for (Index = 0; Index < NumberOfReads; Index++)
+        {
+            /* Read RDR register to discard data */
+            (void)Base->RDR;
+        }
+    }
+    State->RxIndex += NumberOfReads;
+}
+
+/**
+* @brief   This function will push Data into TX FIFO.
+* @details This function will push Data into TX FIFO.
+*
+* @param[in]     Instance            Index of the hardware instance.
+* @param[in]     NumberOfWrites      Number of Data can be pushed to TX FIFO.
+* @return void
+*/
+LOCAL_INLINE void Lpspi_Ip_PushDataToFifo(uint8 Instance, uint8 NumberOfWrites)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 Data = 0u;
+    uint8 Index = 0u;
+    
+    /* Default data will be sent if TX buffer is null */
+    Data = State->ExternalDevice->DeviceParams->DefaultData;
+    /* To increase the performance of transfer, we will reduce the checking conditions in per "for" statement so we should have more than 1 "for" statement here */
+    if (NULL_PTR != State->TxBuffer)
+    {
+        if (State->TxFrameSize < 9u)
+        {
+            for (Index = 0; Index < NumberOfWrites; Index++)
+            {
+                Data = *((uint8*)(&State->TxBuffer[State->TxIndex + Index]));
+                Base->TDR = Data;
+            }
+        }
+        else if (State->TxFrameSize < 17u)
+        {
+            for (Index = 0; Index < NumberOfWrites; Index++)
+            {
+                Data = *((uint16*)(&State->TxBuffer[2u * (State->TxIndex + Index)]));
+                Base->TDR = Data;
+            }
+        }
+        else
+        {
+            for (Index = 0; Index < NumberOfWrites; Index++)
+            {
+                Data = *((uint32*)(&State->TxBuffer[4u * (State->TxIndex + Index)]));
+                Base->TDR = Data;
+            }
+        }
+    }
+    else
+    {
+        for (Index = 0; Index < NumberOfWrites; Index++)
+        {
+            Base->TDR = Data;
+        }
+    }
+    State->TxIndex += NumberOfWrites;
+}
+
+/**
+* @brief   This function will finish transfer of a channel.
+* @details This function will finish transfer of a channel.
+*
+* @param[in]     Instance            Index of the hardware instance.
+* @param[in]     ErrorFlag           Save the status of transfer error flags
+* @return void
+*/
+static void Lpspi_Ip_ChannelFinished(uint8 Instance, boolean ErrorFlag)
+{
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    
+    if(TRUE == ErrorFlag)
+    {
+        State->Status = LPSPI_IP_FAULT;
+    }
+    else
+    {
+        State->Status = LPSPI_IP_IDLE;
+    }
+    if (State->Callback != NULL_PTR)
+    {
+        if(TRUE == ErrorFlag)
+        {
+            State->Callback(Instance, LPSPI_IP_EVENT_FAULT);
+        }
+        else
+        {
+            State->Callback(Instance, LPSPI_IP_EVENT_END_TRANSFER);
+        }
+    }
+}
+
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+/**
+* @brief   This function is called by Lpspi_Ip_IrqHandler or Lpspi_Ip_ManageBuffers. It will process transfer in interrupt mode or polling mode.
+* @details This function will fill Data into TX FIFO and read Data in RX FIFO fill to Rx Buffers.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Lpspi_Ip_TransferProcessHalfDuplex(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 SrStatusRegister;
+    uint8 NumberOfWrites = 0u;
+    uint8 NumberOfReads = 0u;
+    boolean ErrorFlag = FALSE;
+    Lpspi_Ip_HalfDuplexType TransferType;
+    boolean TransferCompleted = FALSE;
+    uint8 NumberOfFramesTxFifo;
+
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        /* Read Status and clear all flags. */
+        SrStatusRegister = Base->SR;
+        Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+        TransferType = State->ExternalDevice->DeviceParams->TransferType;       
+        
+        if ((SrStatusRegister & (LPSPI_SR_REF_MASK | LPSPI_SR_TEF_MASK)) != 0u)
+        {
+            /* mark error flag */
+            ErrorFlag = TRUE;
+        }
+        else
+        {
+            /* TX of latest channel in job have done */
+            /* Check TX FIFO is available to fill CMD */
+            if((State->ExpectedFifoWrites == State->TxIndex) && (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType))
+            {
+                ErrorFlag = Lpspi_Ip_HalfDupleTransmitChannelComplete(Instance);
+                /* In Transmit only mode, masks the transfer has finish */
+                TransferCompleted = TRUE;
+            }
+            if (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)
+            {
+                /* RECEIVE DATA */
+                /* Read all Data available in receive HW fifo. */
+                NumberOfReads = (uint8)(((Base->FSR) & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
+                if (NumberOfReads > (State->ExpectedFifoReads - State->RxIndex))
+                {
+                    NumberOfReads = (uint8)(State->ExpectedFifoReads - State->RxIndex);
+                }
+                if (0u != NumberOfReads)
+                {
+                    Lpspi_Ip_ReadDataFromFifo(Instance, NumberOfReads);
+                }
+                /* In slave mode, do not need push CMD */
+                #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+                if (FALSE == State->PhyUnitConfig->SlaveMode)
+                #endif
+                {
+                    /* PUSH CMD */
+                    /* Only write to TCR when TX FIFO is empty in receive mode */
+                    if ((0u == ((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK)) && (State->ExpectedFifoWrites != State->TxIndex))
+                    {
+                        /* Push one CMD to start transfer. */
+                        Base->TCR = State->HalfDuplexTcrCommand;
+                        State->TxIndex++;
+                    }
+                }
+            }
+            else 
+            {
+                /* TRANSMIT */
+                /* Push Data until HW fifo is full or transfer is done. */
+                NumberOfFramesTxFifo = (uint8)(((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
+                NumberOfWrites = LPSPI_IP_FIFO_SIZE_U8 - NumberOfFramesTxFifo;
+                if((0u != NumberOfWrites) && (State->ExpectedFifoWrites != State->TxIndex))
+                {
+                    Lpspi_Ip_HalfDuplexPushDataToFifo(Instance, NumberOfWrites);
+                }
+            }
+        }
+        
+        /* End of transfer */
+        if(
+            ((LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType) && (TRUE == TransferCompleted)) || 
+            ((State->RxIndex == State->ExpectedFifoReads) && (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)) ||
+            (TRUE == ErrorFlag)
+           )
+        {
+            /* Disable interrupts */
+            Base->IER = 0u;
+            Lpspi_Ip_ChannelFinished(Instance, ErrorFlag);
+        }
+    }
+}
+
+/**
+* @brief   This function to complete TX channel in HD mode.
+* @details This function to complete TX channel in HD mode.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static boolean Lpspi_Ip_HalfDupleTransmitChannelComplete(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    const Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(LPSPI_IP_HALF_DUPLEX_TIMEOUT_COUNTER, LPSPI_IP_TIMEOUT_METHOD);
+    uint32 CurrentTicks = 0u; /* initialize current counter */
+    uint32 ElapsedTicks = 0u; /* elapsed will give timeout */ 
+    boolean TimeOutError = FALSE;
+    
+    /* TX of latest channel in job have done */
+    if (FALSE == State->KeepCs)
+    {
+        /* No need clear for slave mode */
+        #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+        if (TRUE == State->PhyUnitConfig->SlaveMode)
+        #endif
+        {
+            /* Clear CS */
+            Base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+        }
+    }
+    if ((TRUE == State->NextChannelIsRX) || (FALSE == State->KeepCs))
+    {
+        /* If this is latest channel, waiting for all frames in TXFIFO have moved out before finish transfer for next job */
+        /* If next channel is in receive mode, waiting for TX of this channel to complete before start next channel */
+        while ((((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK) != 0u) && (ElapsedTicks < TimeoutTicks))
+        {
+            CurrentTicks = OsIf_GetCounter(LPSPI_IP_TIMEOUT_METHOD);
+            ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, LPSPI_IP_TIMEOUT_METHOD);  
+        }
+        if(ElapsedTicks >= TimeoutTicks)
+        {
+            /* mark error flag */
+            TimeOutError = TRUE;
+            /* Clear TX FIFO */
+            Base->CR |= LPSPI_CR_RTF_MASK;
+        }
+    }
+    return TimeOutError;
+}
+
+/**
+* @brief   This function will process to transmit data.
+* @details This function will process to transmit data.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+LOCAL_INLINE boolean Lpspi_Ip_HalfDuplexTransmitProcess(uint8 Instance, uint8 NumberOfWrites)
+{
+    const Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    boolean TransferCompleted = FALSE;
+
+    if(State->ExpectedFifoWrites != State->TxIndex)
+    {
+        Lpspi_Ip_HalfDuplexPushDataToFifo(Instance, NumberOfWrites);
+    }
+    else
+    {
+        /* At least 1 TX FIFO slot must be available at here to make sure that driver can push one more CMD to TX FIFO to clear CONT at the end of latest channel in a job */
+        if((FALSE == State->KeepCs))
+        {
+            /* Clear CS if there is request to clear CONT bit, make sure that is having at least 1 entry TX FIFO is available to fill CMD by check TDF flag */
+            if(0u != (Base->TCR & LPSPI_TCR_CONT_MASK))
+            {
+                Base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+                /* Set transfer flag is done to break from while loop to finish transfer */
+            }
+        }
+        /* Transfer is finished */
+        TransferCompleted = TRUE;
+    }
+    return TransferCompleted;
+}
+
+/**
+* @brief   This function will perform Transmit data in half duplex mode.
+* @details This function will perform Transmit data in half duplex mode.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+LOCAL_INLINE void Lpspi_Ip_HalfDuplexPushDataToFifo(uint8 Instance, uint8 NumberOfWrites)
+{
+    const Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint8 WriteToFifoTime = NumberOfWrites;
+
+    /* Limits to remaining frames. */
+    if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))
+    {
+        WriteToFifoTime = (uint8)(State->ExpectedFifoWrites - State->TxIndex);
+    }
+    /* Push Data into TX FIFO */
+    Lpspi_Ip_PushDataToFifo(Instance, WriteToFifoTime);
+}
+/**
+* @brief   This function will prepare to transfer in half duplex mode.
+* @details This function will prepare to transfer in half duplex mode.
+*
+* @param[in]     Instance           Index of the hardware instance.
+* @param[in]     Buffer             Transfer buffer.
+* @return void
+*/
+static void Lpspi_Ip_HalfDuplexPrepare(uint8 Instance, uint8* Buffer)
+{
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    uint8 LsbWriteValue = State->TxLsb ? 1U : 0U;
+
+    /* In half duplex mode, CFGR1 register should be updated to configure PCSCFG, OUTCFG, PINCFG fields. This bit fields should be reset before write new value */
+    Base->CFGR1 &= ~(LPSPI_CFGR1_PCSCFG_MASK | LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK);
+    Base->CFGR1 |= State->ExternalDevice->HalfDuplexCfgr1;
+    /* This variable will be used only in polling mode, It do not determine the number of frames in TX FIFO in half mode. it only makes sure that in Slave receive mode, TDF is set but it will not be used to execute process function */
+    /* Set this variable to different 0 if is not in Slave Receive mode */
+    State->CurrentTxFifoSlot = 1u; 
+    if(LPSPI_IP_HALF_DUPLEX_TRANSMIT == State->ExternalDevice->DeviceParams->TransferType)
+    {
+        State->TxBuffer = Buffer;
+    }
+    else
+    {
+        State->RxBuffer = Buffer;
+        
+        /* Update TCR value to using in ISR function */
+        #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+        State->HalfDuplexTcrCommand = State->ExternalDevice->Tcr[State->ClockMode] | LPSPI_TCR_FRAMESZ((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) | LPSPI_TCR_LSBF(LsbWriteValue);
+        #else
+        State->HalfDuplexTcrCommand = State->ExternalDevice->Tcr | LPSPI_TCR_FRAMESZ((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) | LPSPI_TCR_LSBF(LsbWriteValue);
+        #endif
+        /* In Slave mode, CONT bit should be cleared */
+        #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+        if(TRUE == State->PhyUnitConfig->SlaveMode)
+        {
+            State->HalfDuplexTcrCommand &= ~LPSPI_TCR_CONT_MASK;
+            /* This variable will be used only in polling mode, It do not determine the number of frames in TX FIFO in half mode. it only makes sure that in Slave receive mode, TDF is set but it will not be used to execute process function */
+            /* Set this variable to 0 in Slave Receive mode */
+            State->CurrentTxFifoSlot = 0u;              
+        }
+        #endif
+        /* Because of not supporting CS continous mode so nothing need to be done with CONT bit */
+        /* Mark TX FIFO */    
+        State->HalfDuplexTcrCommand |= LPSPI_TCR_TXMSK_MASK;
+    }
+}
+#endif
+
+/**
+* @brief   This function is called by Lpspi_Ip_IrqHandler or Lpspi_Ip_ManageBuffers. It will process transfer in interrupt mode or polling mode.
+* @details This function will fill Data into TX FIFO and read Data in RX FIFO fill to Rx Buffers.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Lpspi_Ip_TransferProcess(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 SrStatusRegister;
+    uint8 NumberOfWrites = 0u;
+    uint8 NumberOfReads = 0u;
+    boolean ErrorFlag = FALSE;
+
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        /* Read Status and clear all flags. */
+        SrStatusRegister = Base->SR;
+        Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+        
+        if ((SrStatusRegister & (LPSPI_SR_REF_MASK | LPSPI_SR_TEF_MASK)) != 0u)
+        {
+            /* mark error flag */
+            ErrorFlag = TRUE;
+        }
+        else
+        {
+            /* Read all Data available in receive HW fifo. */
+            NumberOfReads = (uint8)(((Base->FSR) & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
+            if (NumberOfReads != 0u)
+            {
+                if (NumberOfReads > (State->ExpectedFifoReads - State->RxIndex))
+                {
+                    NumberOfReads = (uint8)(State->ExpectedFifoReads - State->RxIndex);
+                }
+                /* If these are the first frames of this channel. Current TXFIFO slot must be plus 1 because the slot of CMD have moved out and
+                  CurrentTxFifoSlot was minus 1 when prepare TX channel */
+                if (0u == State->RxIndex)
+                {
+                    State->CurrentTxFifoSlot += 1u;
+                }
+                /* Read Data from RX FIFO */
+                Lpspi_Ip_ReadDataFromFifo(Instance, NumberOfReads);
+                /* Update current FIFO slots are available to fill .*/
+                State->CurrentTxFifoSlot += NumberOfReads;
+            }
+            
+            /*TRANSMIT*/
+            /* Push Data until HW fifo is full or transfer is done. */
+            /* After driver code read all frames in RX FIFO, if there are still some frames in TX FIFO, at the time before driver code check number of frames available in TX FIFO to prepare 
+            to fill TX FIFO. At that time, another interrupt occurred and preemptive current interrupt, and the time to process that interrupt is longer than the time to transfer all frames 
+            in TX FIFO. So TX FIFO will be empty and some frames received in RX FIFO, then the program is returned from that interrupt and fill TX FIFO until full and exist SPI interrupt function. 
+            And if there is a interrupt occurred with higher priority of SPI interrupt and the time to process that interrupt is longer than the time to transfer all frames in TX FIFO. 
+            So, RX FIFO can be overflow due to SPI interrupt function is not serviced to read RX FIFO.
+            State->CurrentTxFifoSlot variable is used to hanlde number of frames are "on bus transfer". They are always less than FIFO size */
+            if((State->CurrentTxFifoSlot != 0u) && (State->TxDoneFlag != TRUE))
+            {
+                if(State->ExpectedFifoWrites != State->TxIndex)
+                {
+                    NumberOfWrites = State->CurrentTxFifoSlot;
+                    /* Limits to remaining frames. */
+                    if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))
+                    {
+                        NumberOfWrites = (uint8)(State->ExpectedFifoWrites - State->TxIndex);
+                    }
+                    /* Push Data into TX FIFO */
+                    Lpspi_Ip_PushDataToFifo(Instance, NumberOfWrites);
+                    State->CurrentTxFifoSlot -= NumberOfWrites;
+                }
+                else
+                {
+                    if(TRUE == State->NextTransferConfigAvailable)
+                    {
+                        /* Initialize next transfer */
+                        State->ExternalDevice->DeviceParams->DefaultData = State->DefaultDataNext;
+                        State->FirstCmd = FALSE;
+                        Lpspi_TransmitTxInit(Instance, State->TxBufferNext, State->FrameSizeNext, State->LsbNext, State->LengthNext);
+                        State->NextTransferConfigAvailable = FALSE;
+                    }
+                    else
+                    {
+                        State->TxDoneFlag = TRUE;
+                        /* Disable TX interrupt */
+                        Base->IER &= ~LPSPI_IER_TDIE_MASK;
+                        if((FALSE == State->KeepCs) && (0u != (Base->TCR & LPSPI_TCR_CONT_MASK)))
+                        {
+                            /* Clear CS */
+                            Base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+                        }
+                    }
+                }
+            }
+        }
+        
+        /* End of transfer */
+        if((State->RxIndex == State->ExpectedFifoReads) || (TRUE == ErrorFlag))
+        {
+            /* In slave mode. After Slave devices to finish its transfer then SPI module masks rx to avoid un-expected extra Data from Master device */
+            #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+            if ( ((FALSE == State->KeepCs) || (TRUE == ErrorFlag)) && (TRUE == State->PhyUnitConfig->SlaveMode) )
+            {
+                SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12();
+                /* Mask Rx */
+                Base->TCR |= LPSPI_TCR_RXMSK(1);
+                SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12();
+            }
+            #endif
+            /* Disable interrupts */
+            Base->IER = 0u;
+            Lpspi_Ip_ChannelFinished(Instance, ErrorFlag);
+        }
+    }
+}
+
+#if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+/**
+* @brief   This function will verify the validation of some input parameters of transmision functions.
+* @details This function will verify the validation of some input parameters of transmision functions. 
+*
+* @param[in]     ExternalDevice   Pointer to the external device where data is transmitted.
+* @param[in]     Length         Number of bytes to be sent.
+* @return        LPSPI_IP_STATUS_SUCCESS: Don't have any errors was found.
+*                LPSPI_IP_STATUS_FAIL: Transmission command has not been accepted.
+*/
+static void Lpspi_Ip_CheckValidParameters(
+                                                const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                                uint16 Length
+                                          )
+{
+
+    if (ExternalDevice->DeviceParams->FrameSize > 16u)
+    {
+        DevAssert((Length%4) == 0u);
+    }
+    else if (ExternalDevice->DeviceParams->FrameSize > 8u)
+    {
+        DevAssert((Length%2) == 0u);
+    }
+    else
+    {
+        /* do nothing */
+    }
+}
+#endif
+
+#if (STD_ON == LPSPI_IP_DMA_USED)
+#if (STD_ON == LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT)
+static void Lpspi_Ip_TxDmaTcdSGInit(uint8 Instance)
+{
+    const Lpspi_Ip_StateStructureType* State = (const Lpspi_Ip_StateStructureType*)Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+    uint8 TcdSgIndex = 0u;
+
+    /* initialze configuration software TCD Scatter Gather for Tx DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; 
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    
+    DmaTcdList[1u].Value = 0u;    /* dummy dest address write, will be updated latter according to ScatterGather to update TCR or TDR */
+    DmaTcdList[2u].Value = 1u;  /* dummy src offset is 1 byte, will be updated latter according to frame size and transfer default Data */
+    DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte src transfer size, will be updated latter according to frame size */
+    DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* dummy 1 byte dest transfer size, will be updated latter according to frame size */
+    DmaTcdList[5u].Value = 1u;   /* dummy bytes to transfer for each request, will be updated latter according to frame size */
+    DmaTcdList[6u].Value = 0u; /* no dest offset */
+    DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter according to number of frames */
+    DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be updated latter according to last transfer or not */
+    DmaTcdList[0u].Value = 0u; /* dummy src address read, will be updated latter Base on TxBuffer */
+    
+    for(TcdSgIndex = 0u; TcdSgIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TcdSgIndex++)
+    {
+        /* Update software TX DMA TCD Scatter Gather */
+        (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[TcdSgIndex], DmaTcdList, 9u);
+    }
+}
+
+static void Lpspi_Ip_CmdTxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint32 CmdAdd, uint8 DisHwReq)
+{
+    const LPSPI_Type* Base = (const LPSPI_Type *)Lpspi_Ip_apxBases[Instance];
+    const Lpspi_Ip_StateStructureType* State = (const Lpspi_Ip_StateStructureType *)Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+
+    /* configure TX DMA TCD Scatter Gather to update transfer command TCR */
+    /* No need to configure dest offset due to it are already set by Lpspi_Ip_TxDmaTcdSGInit */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+    
+    DmaTcdList[0u].Value = CmdAdd; /* src address read */
+    DmaTcdList[1u].Value = (uint32)&Base->TCR;    /* dest address write*/
+    DmaTcdList[2u].Value = 0u;  /* src offset is 0 byte */
+    DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+    DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+    DmaTcdList[5u].Value = 4u;   /* bytes to transfer for each request */
+    DmaTcdList[6u].Value = 1u; /* iteration count */
+    DmaTcdList[7u].Value = DisHwReq; /* disable hardware request when major loop complete */
+    DmaTcdList[8u].Value = DisHwReq; /* Enable Major interrupt at the end of transfer sequence(meanning when DisHwReq = 1u) */
+
+    /* Update software TX DMA TCD Scatter Gather */
+    (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[TcdSgIndex], DmaTcdList, 9u);
+}
+
+static void Lpspi_Ip_TxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint8 DisHwReq, const uint32 *DefaultDataAddress)
+{
+    const LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+
+    /* Update buffers index */
+    State->TxIndex = State->ExpectedFifoWrites;
+
+    /* configure TX DMA TCD Scatter Gather to fill tx Data to TDR */
+    /* No need to configure dest offset due to it are already set by Lpspi_Ip_TxDmaTcdSGInit */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+    DmaTcdList[1u].Value = (uint32)&Base->TDR;    /* dest address write*/
+    if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+    {
+        DmaTcdList[2u].Value = 1u;  /* src offset is 1 byte */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+        DmaTcdList[5u].Value = 1u;   /* bytes to transfer for each request */
+    }
+    else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+    {
+        DmaTcdList[2u].Value = 2u;  /* src offset is 2 bytes */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+        DmaTcdList[5u].Value = 2u;   /* bytes to transfer for each request */
+    }
+    else
+    {
+        DmaTcdList[2u].Value = 4u;  /* src offset is 4 bytes */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[5u].Value = 4u;   /* bytes to transfer for each request */
+    }
+    DmaTcdList[6u].Value = State->ExpectedFifoWrites; /* iteration count */
+    DmaTcdList[7u].Value = DisHwReq; /* disable hardware request when major loop complete */
+    DmaTcdList[8u].Value = DisHwReq; /* Enable Major interrupt at the end of transfer sequence(meanning when DisHwReq = 1u) */
+    if (NULL_PTR == State->TxBuffer)
+    {
+        /* send default Data */
+        DmaTcdList[0u].Value = (uint32)DefaultDataAddress; /* src address read */
+        DmaTcdList[2u].Value = 0u;  /* src offset is 0 byte */
+    }
+    else
+    {
+        DmaTcdList[0u].Value = (uint32)State->TxBuffer; /* src address read */
+        /* cast to avoid CW */
+        (void)DefaultDataAddress;
+    }
+
+    /* Update software TX DMA TCD Scatter Gather */
+    (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[TcdSgIndex], DmaTcdList, 9u);
+}
+
+static void Lpspi_Ip_RxDmaTcdSGInit(uint8 Instance)
+{
+    const LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    const Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[9u];
+    uint8 TcdSgIndex = 0u;
+
+    /* initialze configuration software TCD Scatter Gather for Rx DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS; 
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    
+    DmaTcdList[0u].Value = (uint32)&Base->RDR; /* src address read */
+    DmaTcdList[2u].Value = 0u;  /* no src offset */
+    DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* dummy 1 byte src transfer size, will be updated latter Base on frame size */
+    DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* dummy 1 byte dest transfer size, will be updated latter Base on frame size */
+    DmaTcdList[5u].Value = 1u;   /* dummy 1 byte to transfer for each request, will be updated latter Base on frame size */
+    DmaTcdList[6u].Value = 1u; /* dummy dest offset is 1 byte, will be updated latter Base on frame size and discard info */
+    DmaTcdList[1u].Value = 0u;    /* dummy dest address write, will be updated latter Base on RxBuffer */ 
+    DmaTcdList[7u].Value = 0u; /* dummy iteration count, will be updated latter Base on number of frames */
+    DmaTcdList[8u].Value = 1u; /* dummy disable hardware request when major loop complete, will be updated latter according to last transfer or not */
+    
+    for(TcdSgIndex = 0u; TcdSgIndex < State->PhyUnitConfig->MaxNumOfFastTransfer; TcdSgIndex++)
+    {
+        /* Update software RX DMA TCD Scatter Gather */
+        (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitConfig->RxDmaFastSGId[TcdSgIndex], DmaTcdList, 9u);
+    }
+}
+
+static void Lpspi_Ip_RxDmaTcdSGConfig(uint8 Instance, uint8 TcdSgIndex, uint8 DisHwReq)
+{
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[8u];
+
+    /* Update buffers index */
+    State->RxIndex = State->ExpectedFifoReads;
+    
+    /* configure RX DMA TCD Scatter Gather */
+    /* No need to configure src address and src offset due to they are already set by Lpspi_Ip_RxDmaTcdSGInit */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+
+    if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+    {
+        DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+        DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+        DmaTcdList[3u].Value = 1u;   /* 1 byte to transfer for each request */
+        DmaTcdList[4u].Value = 1u; /* dest offset is 1 bytes */
+    }
+    else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+    {
+        DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+        DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+        DmaTcdList[3u].Value = 2u;   /* 2 bytes to transfer for each request */
+        DmaTcdList[4u].Value = 2u; /* dest offset is 2 bytes */
+    }
+    else
+    {
+        DmaTcdList[1u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[2u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[3u].Value = 4u;   /* 4 bytes to transfer for each request */
+        DmaTcdList[4u].Value = 4u; /* dest offset is 4 bytes */
+    }
+    if (NULL_PTR == State->RxBuffer)
+    {
+        /* Discard Data */
+        DmaTcdList[0u].Value = (uint32)&Lpspi_Ip_u32DiscardData;    /* dest address write*/ 
+        DmaTcdList[4u].Value = 0u; /* dest offset is 0 bytes */
+    }
+    else
+    {
+        DmaTcdList[0u].Value = (uint32)State->RxBuffer;    /* dest address write*/ 
+    }
+    DmaTcdList[5u].Value = State->ExpectedFifoReads; /* iteration count */
+    DmaTcdList[6u].Value = DisHwReq; /* disable hardware request when major loop complete */
+    DmaTcdList[7u].Value = DisHwReq; /* Enable Major interrupt at the end of transfer sequence(meanning when DisHwReq = 1u) */
+
+    /* Update software RX DMA TCD Scatter Gather */
+    (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitConfig->RxDmaFastSGId[TcdSgIndex], DmaTcdList, 8u);
+}
+#endif /* (STD_ON == LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT) */
+
+/**
+* @brief   This function will configure hardware TCDs for the channels TX DMA, RX DMA 
+*          according to current transfer configuration. DMA channels will be started at the end of the function.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Lpspi_Ip_TxDmaConfig(uint8 Instance)
+{
+    const LPSPI_Type* Base = (const LPSPI_Type*)Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[10u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoWrites;
+
+    /* Limits number of major count */
+    if (LPSPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = LPSPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    /* Update buffers index */
+    State->TxIndex = NumberDmaIterWrite;
+
+    /* configure TX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    DmaTcdList[9u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    /* In Half duplex receive mode. TX DMA will be used to push CMD to TXFIFO to start transfer */    
+    if (LPSPI_IP_HALF_DUPLEX_RECEIVE == State->ExternalDevice->DeviceParams->TransferType)
+    {
+        DmaTcdList[0u].Value = (uint32)&State->HalfDuplexTcrCommand; /* src address read */
+        DmaTcdList[1u].Value = (uint32)&Base->TCR;    /* dest address write*/
+        DmaTcdList[2u].Value = 0u;  /* src offset is 0 bytes */
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[5u].Value = 4u;   /* bytes to transfer for each request */        
+    }
+    else
+#endif
+    {
+        DmaTcdList[1u].Value = (uint32)&Base->TDR;    /* dest address write*/
+        if (State->TxFrameSize < 9u)
+        {
+            DmaTcdList[2u].Value = 1u;  /* src offset is 1 byte */
+            DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+            DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+            DmaTcdList[5u].Value = 1u;   /* bytes to transfer for each request */
+        }
+        else if (State->TxFrameSize < 17u)
+        {
+            DmaTcdList[2u].Value = 2u;  /* src offset is 2 bytes */
+            DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+            DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+            DmaTcdList[5u].Value = 2u;   /* bytes to transfer for each request */
+        }
+        else
+        {
+            DmaTcdList[2u].Value = 4u;  /* src offset is 4 bytes */
+            DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+            DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+            DmaTcdList[5u].Value = 4u;   /* bytes to transfer for each request */
+        }
+        if (NULL_PTR == State->TxBuffer)
+        {
+            /* send default Data */
+            DmaTcdList[0u].Value = (uint32)&State->ExternalDevice->DeviceParams->DefaultData; /* src address read */
+            DmaTcdList[2u].Value = 0u;  /* src offset is 0 byte */
+        }
+        else
+        {
+            DmaTcdList[0u].Value = (uint32)State->TxBuffer; /* src address read */
+        }
+    }
+    
+    DmaTcdList[6u].Value = 0u; /* no dest offset */
+    DmaTcdList[7u].Value = NumberDmaIterWrite; /* iteration count */
+    DmaTcdList[8u].Value = 1u; /* disable hardware request when major loop complete */
+    
+    /* Set DESTINATION_SIGNED_LAST_ADDR_ADJ = 0 to avoid the case it still stored from previous TCD Scatter Gather */
+    DmaTcdList[9u].Value = 0u;    /* No adjust DADD when major loop completed */
+    /* write TCD for TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 10u);
+
+    /* Enable TX DMA HW request */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+
+/**
+* @brief   This function will configure hardware TCDs for the channels TX DMA, RX DMA 
+*          according to current transfer configuration. DMA channels will be started at the end of the function.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Lpspi_Ip_RxDmaConfig(uint8 Instance)
+{
+    const LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[10u];
+    uint16 NumberDmaIterRead = State->ExpectedFifoReads;
+
+    /* Limits number of major count */
+    if (LPSPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterRead)
+    {
+        NumberDmaIterRead = LPSPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    /* Update buffers index */
+    State->RxIndex = NumberDmaIterRead;
+
+    /* configure RX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
+    DmaTcdList[1u].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
+    DmaTcdList[2u].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
+    DmaTcdList[3u].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
+    DmaTcdList[4u].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
+    DmaTcdList[5u].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
+    DmaTcdList[6u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
+    DmaTcdList[7u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[8u].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
+    DmaTcdList[9u].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
+    
+    DmaTcdList[0u].Value = (uint32)&Base->RDR; /* src address read */
+    DmaTcdList[2u].Value = 0u;  /* no src offset */
+    if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE; /* 1 byte src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_1_BYTE;    /* 1 byte dest transfer size */
+        DmaTcdList[5u].Value = 1u;   /* 1 byte to transfer for each request */
+        DmaTcdList[6u].Value = 1u; /* dest offset is 1 bytes */
+    }
+    else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE; /* 2 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_2_BYTE;    /* 2 bytes dest transfer size */
+        DmaTcdList[5u].Value = 2u;   /* 2 bytes to transfer for each request */
+        DmaTcdList[6u].Value = 2u; /* dest offset is 2 bytes */
+    }
+    else
+    {
+        DmaTcdList[3u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE; /* 4 bytes src transfer size */
+        DmaTcdList[4u].Value = DMA_IP_TRANSFER_SIZE_4_BYTE;    /* 4 bytes dest transfer size */
+        DmaTcdList[5u].Value = 4u;   /* 4 bytes to transfer for each request */
+        DmaTcdList[6u].Value = 4u; /* dest offset is 4 bytes */
+    }
+    if (NULL_PTR == State->RxBuffer)
+    {
+        /* Discard Data */
+        DmaTcdList[1u].Value = (uint32)&Lpspi_Ip_u32DiscardData;    /* dest address write*/ 
+        DmaTcdList[6u].Value = 0u; /* dest offset is 0 bytes */
+    }
+    else
+    {
+        DmaTcdList[1u].Value = (uint32)State->RxBuffer;    /* dest address write*/ 
+    }
+    DmaTcdList[7u].Value = NumberDmaIterRead; /* iteration count */
+    DmaTcdList[8u].Value = 1u; /* disable hardware request when major loop complete */
+    /* Set DESTINATION_SIGNED_LAST_ADDR_ADJ = 0 to avoid the case it still stored from previous TCD Scatter Gather */
+    DmaTcdList[9u].Value = 0u;    /* No adjust DADD when major loop completed */
+    /* write TCD for RX DMA channel */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 10u);
+
+    /* Enable RX DMA HW request */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+
+static void Lpspi_Ip_TxDmaContinueTransfer(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    uint16 NumberDmaIterWrite = State->ExpectedFifoWrites - State->TxIndex;
+
+    /* Limits number of major count */
+    if (LPSPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterWrite)
+    {
+        NumberDmaIterWrite = LPSPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    State->TxIndex += NumberDmaIterWrite;
+
+    /* Update TX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[0u].Value = NumberDmaIterWrite;    /* iteration count */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+
+    /* Disable TX DMA request to avoid overflow because RX DMA needs time to be initialized for next transfer,
+    TX DMA request will be enabled later when RX DMA complete by Lpspi_Ip_RxDmaContinueTransfer. */
+    Base->DER &= ~LPSPI_DER_TDDE_MASK;
+    /* Enable TX DMA HW request for TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+    #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+    if(TRUE == State->PhyUnitConfig->SlaveMode)
+    {
+        /* Push first frame to TX FIFO to ensure that TX FIFO is not empty and CS can be kept in the case of CS continue */
+        (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_SOFTWARE_REQUEST);
+    }
+    #endif
+}
+
+static void Lpspi_Ip_RxDmaContinueTransfer(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    uint16 NumberDmaIterRead = State->ExpectedFifoReads - State->RxIndex;
+
+    /* Limits number of major count */
+    if (LPSPI_IP_DMA_MAX_ITER_CNT_U16 < NumberDmaIterRead)
+    {
+        NumberDmaIterRead = LPSPI_IP_DMA_MAX_ITER_CNT_U16;
+    }
+    else
+    {
+        /* Nothing to do */
+    }
+
+    State->RxIndex += NumberDmaIterRead;
+
+    /* Update RX DMA channel */
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
+    DmaTcdList[0u].Value = NumberDmaIterRead;    /* iteration count */
+    (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u);
+
+    /* Enable DMA HW request for RX DMA channel */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+    /* Enable TX DMA request due to it is disabled in Lpspi_Ip_TxDmaContinueTransfer */
+    Base->DER |= LPSPI_DER_TDDE_MASK;
+}
+
+/**
+* @brief   This function will finish channel transmission via DMA.
+* @details This function will finish channel transmission via DMA.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+*/
+static void Lpspi_Ip_TxDmaFinishTransfer(const uint8 Instance)
+{
+    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    Lpspi_Ip_HalfDuplexType TransferType;
+    uint32 CurrentTicks = 0u; /* initialize current counter */
+    uint32 ElapsedTicks = 0u; /* elapsed will give timeout */
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(LPSPI_IP_HALF_DUPLEX_TIMEOUT_COUNTER, LPSPI_IP_TIMEOUT_METHOD);      
+    #endif
+    LPSPI_Type *Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType *State = Lpspi_Ip_apxStateStructureArray[Instance];
+
+    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    TransferType = State->ExternalDevice->DeviceParams->TransferType;
+    if (((TRUE == State->NextChannelIsRX) && (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType)) || (FALSE == State->KeepCs))
+    #else
+    if (FALSE == State->KeepCs)
+    #endif
+    {
+        if (FALSE == State->KeepCs)
+        {
+            /* Clear CS, in slave mode CONT bit is always 0 so nothing will be done. */
+            if (0u != (Base->TCR & LPSPI_TCR_CONT_MASK))
+            {
+                Base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+            }
+        }
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        if (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType)
+        {
+            /* If this is latest channel, waiting for all frames in TXFIFO have moved out before finish transfer for next job */
+            /* If next channel is in receive mode, waiting for TX of this channel to complete before start next channel */
+            while ((((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK) != 0u) && (ElapsedTicks < TimeoutTicks))
+            {
+                CurrentTicks = OsIf_GetCounter(LPSPI_IP_TIMEOUT_METHOD);
+                ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, LPSPI_IP_TIMEOUT_METHOD);  
+            }
+            if(ElapsedTicks >= TimeoutTicks)
+            {
+                /* Clear TX FIFO */
+                Base->CR |= LPSPI_CR_RTF_MASK;
+            }
+        }
+        #endif
+    }
+    else
+    {
+        /* In Half duplex trasnmit mode, we do not need to care about received datas of current channel so do not need to configure next channel here */
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        if (LPSPI_IP_FULL_DUPLEX == TransferType)
+        #endif
+        {
+            if (TRUE == State->NextTransferConfigAvailable)
+            {
+                /* Initialize next transfer */
+                State->ExternalDevice->DeviceParams->DefaultData = State->DefaultDataNext;
+                State->FirstCmd = FALSE;
+                Lpspi_TransmitTxInit(Instance, State->TxBufferNext, State->FrameSizeNext, State->LsbNext, State->LengthNext);
+                State->NextTransferConfigAvailable = FALSE;
+                /* Disable TX DMA request to avoid overflow because RX DMA needs time to be initialized for next transfer,
+                TX DMA request will be enabled later when RX DMA completed and next transfer initialized by Lpspi_Ip_AsyncTransmit. */
+                Base->DER &= ~LPSPI_DER_TDDE_MASK;
+                Lpspi_Ip_TxDmaConfig(Instance);
+                /* Push first frame to TX FIFO to ensure that previous received frame will be pushed to RX FIFO and RX DMA can be completed in the case of CS continue */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_SOFTWARE_REQUEST);
+            }
+            else
+            {
+                /* Set flag next transfer has been completed */
+                State->NextTransferDone = TRUE;
+            }
+        }
+    }
+}
+
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+/**
+* @brief   This function will process TX DMA transfer complete interrupt. 
+* @details This function will process continue transfer or end of transfer via TX DMA.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+* @implements Lpspi_Ip_IrqTxDmaHandler_Activity
+*/
+void Lpspi_Ip_IrqTxDmaHandler(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 SrStatusRegister = 0u;
+    boolean ErrorFlag = FALSE;
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    boolean EndOfTransferFlag = FALSE;
+    Lpspi_Ip_HalfDuplexType TransferType;
+    Lpspi_Ip_EventType EventState = LPSPI_IP_EVENT_FAULT;
+#endif
+
+    if (NULL_PTR != State)
+    {
+        if (LPSPI_IP_BUSY == State->Status)
+        {
+            #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+            TransferType = State->ExternalDevice->DeviceParams->TransferType;
+            #endif
+            /* Read Status an clear all flags. */
+            SrStatusRegister = Base->SR;
+            Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+
+            if ((SrStatusRegister & (LPSPI_SR_REF_MASK | LPSPI_SR_TEF_MASK)) != 0u)
+            {
+                 /* mark error flag */
+                ErrorFlag = TRUE;
+            }
+            else
+            {
+                if (State->ExpectedFifoWrites != State->TxIndex)
+                {
+                    /* Transfer is not finished => update TX pointers */
+                    Lpspi_Ip_TxDmaContinueTransfer(Instance);
+                }
+                else
+                {
+                    /* Mask EndOfTransferFlag to TRUE to finish transfer if transmit only mode */
+                    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+                    TransferType = State->ExternalDevice->DeviceParams->TransferType;
+                    /* In Transmit only mode, the transfer can be finished after TX have done transfer */
+                    /* In Receive only mode, the trasfer need to wait for RX finish */
+                    if (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType)
+                    {
+                        EndOfTransferFlag = TRUE;
+                    }
+                    #endif
+                    Lpspi_Ip_TxDmaFinishTransfer(Instance);
+                }
+            }
+
+            #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+            if ((TRUE == ErrorFlag) || (TRUE == EndOfTransferFlag))
+            #else
+            if (TRUE == ErrorFlag)
+            #endif
+            {
+                /* In slave mode. After Slave device finish its transfer or Transfer errors apprear then SPI module masks Rx to avoid un-expected extra Data from Master device */
+                #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+                if(TRUE == State->PhyUnitConfig->SlaveMode)
+                {
+                    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13();
+                    /* Mask Rx */
+                    Base->TCR |= LPSPI_TCR_RXMSK(1);
+                    SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13();
+                }
+                #endif
+                /* Disable DMA requests. */
+                Base->DER = 0u;
+                #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+                if (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType)
+                {
+                    if(TRUE == ErrorFlag)
+                    {
+                        State->Status = LPSPI_IP_FAULT;
+                        EventState = LPSPI_IP_EVENT_FAULT;
+                    }
+                    else
+                    {
+                        State->Status = LPSPI_IP_IDLE;
+                        EventState = LPSPI_IP_EVENT_END_TRANSFER;
+                    }
+
+                    if (NULL_PTR != State->Callback)
+                    {
+                        State->Callback(Instance, EventState);
+                    }
+                }
+                else
+                #endif
+                {
+                    /* Disable RX DMA HW request because may RX DMA is not completed, no need to apply for TX DMA due to DMA HW request is cleared automatically */
+                    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+                    State->Status = LPSPI_IP_FAULT;
+
+                    if (State->Callback != NULL_PTR)
+                    {
+                        State->Callback(Instance, LPSPI_IP_EVENT_FAULT);
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Driver is initialized but there was no poll request*/
+        /* nothing to do */
+    }
+}
+
+/**
+* @brief   This function will process RX DMA transfer complete interrupt. 
+* @details This function will process continue transfer or end of transfer via RX DMA.
+*
+* @param[in]     Instance      Index of the hardware instance.
+* @return void
+* @implements Lpspi_Ip_IrqRxDmaHandler_Activity
+*/
+void Lpspi_Ip_IrqRxDmaHandler(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 SrStatusRegister = 0u;
+    boolean ErrorFlag = FALSE;
+    boolean EndOfTransferFlag = FALSE;
+
+    if (NULL_PTR != State)
+    {
+        if (LPSPI_IP_BUSY == State->Status)
+        {
+            /* Read Status an clear all flags. */
+            SrStatusRegister = Base->SR;
+            Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+
+            if ((SrStatusRegister & (LPSPI_SR_REF_MASK | LPSPI_SR_TEF_MASK)) != 0u)
+            {
+                 /* mark error flag */
+                ErrorFlag = TRUE;
+            }
+            else
+            {
+                if (State->ExpectedFifoReads != State->RxIndex)
+                {
+                    /* Transfer is not finished => update RX pointers */
+                    Lpspi_Ip_RxDmaContinueTransfer(Instance);
+                }
+                else
+                {
+                    EndOfTransferFlag = TRUE;
+                }
+            }
+
+            if ((TRUE == EndOfTransferFlag) || (TRUE == ErrorFlag))
+            {
+                /* In slave mode. After Slave device finish its transfer or Transfer errors apprear then SPI module masks Rx to avoid un-expected extra Data from Master device */
+                #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+                if(TRUE == State->PhyUnitConfig->SlaveMode)
+                {
+                    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14();
+                    /* Mask Rx */
+                    Base->TCR |= LPSPI_TCR_RXMSK(1);
+                    SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14();
+                }
+                #endif
+                /* Disable DMA requests. */
+                Base->DER = 0u;
+                if(TRUE == ErrorFlag)
+                {
+                    State->Status = LPSPI_IP_FAULT;
+                    /* Disable TX DMA HW request because may TX DMA is not completed, no need to apply for RX DMA due to DMA HW request is cleared automatically */
+                    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+                }
+                else
+                {
+                    State->Status = LPSPI_IP_IDLE;
+                }
+                if (State->Callback != NULL_PTR)
+                {
+                    if(TRUE == ErrorFlag)
+                    {
+                        State->Callback(Instance, LPSPI_IP_EVENT_FAULT);
+                    }
+                    else
+                    {
+                        State->Callback(Instance, LPSPI_IP_EVENT_END_TRANSFER);
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Driver is initialized but there was no poll request*/
+        /* nothing to do */
+    }
+}
+#endif /* (STD_ON == LPSPI_IP_DMA_USED) */
+
+#if (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+/**
+* @brief This function will set UAA bit in REG_PROT for SPI unit
+*/
+static void Lpspi_Ip_SetUserAccess(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    
+    SET_USER_ACCESS_ALLOWED((uint32)Base,LPSPI_IP_PROT_MEM_U32);
+}
+
+/**
+* @brief This function will enable writing all SPI registers under protection in User mode by configuring REG_PROT
+*/
+static void Lpspi_Ip_SetUserAccessAllowed(uint8 Instance)
+{
+    OsIf_Trusted_Call1param(Lpspi_Ip_SetUserAccess, Instance);
+}
+#endif /* LPSPI_IP_ENABLE_USER_MODE_SUPPORT */
+/*================================================================================================*/
+Lpspi_Ip_StatusType Lpspi_Ip_Init(const Lpspi_Ip_ConfigType *PhyUnitConfigPtr)
+{
+    LPSPI_Type* Base;
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint8 Instance = 0u;
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(PhyUnitConfigPtr != NULL_PTR);
+    #endif
+    Instance = PhyUnitConfigPtr->Instance;
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    Base = Lpspi_Ip_apxBases[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State == NULL_PTR);
+    #endif
+    Lpspi_Ip_apxStateStructureArray[Instance] = &Lpspi_Ip_axStateStructure[PhyUnitConfigPtr->StateIndex];
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    State->PhyUnitConfig = PhyUnitConfigPtr;
+    /* enable in debug mode to ensure CS will be kept when CPU halts at breakpoint */
+    Base->CR = PhyUnitConfigPtr->Cr | LPSPI_CR_DBGEN_MASK;
+    Base->CFGR1 = PhyUnitConfigPtr->Cfgr1;
+    /* Set TX WATER. it will be set again in DMA mode */
+    Base->FCR = LPSPI_FCR_TXWATER((uint32)LPSPI_IP_FIFO_SIZE_U8 - (uint32)1u);
+    #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+    State->ClockMode = LPSPI_IP_NORMAL_CLOCK;
+    #endif
+    State->KeepCs = FALSE;
+    State->FirstCmd = TRUE;
+    #if ((STD_ON == LPSPI_IP_DMA_USED) && (STD_ON == LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT))
+    Lpspi_Ip_TxDmaTcdSGInit(Instance);
+    Lpspi_Ip_RxDmaTcdSGInit(Instance);
+    #endif
+    /* set State to idle */
+    State->Status = LPSPI_IP_IDLE;
+    (void)Lpspi_Ip_UpdateTransferMode(Instance, PhyUnitConfigPtr->TransferMode);
+    
+    /* Enable SPI module */
+    Base->CR |= LPSPI_CR_MEN_MASK;
+    return Status;
+}
+/*================================================================================================*/
+Lpspi_Ip_StatusType Lpspi_Ip_DeInit(uint8 Instance)
+{
+    LPSPI_Type* Base;
+    const Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    Base = Lpspi_Ip_apxBases[Instance];
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        /* Use reset hardware feature. */
+        Base->CR |= LPSPI_CR_RST(1u);
+        Base->CR = 0;
+
+        Lpspi_Ip_apxStateStructureArray[Instance] = NULL_PTR;
+    }
+    return Status;
+}
+
+/*================================================================================================*/
+Lpspi_Ip_StatusType Lpspi_Ip_SyncTransmit(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *TxBuffer,
+                                            uint8 *RxBuffer,
+                                            uint16 Length,
+                                            uint32 TimeOut
+                                         )
+{
+    LPSPI_Type *Base;
+    Lpspi_Ip_StateStructureType *State;
+    uint8 NumberOfWrites, NumberOfReads;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(TimeOut, LPSPI_IP_TIMEOUT_METHOD);
+    uint32 CurrentTicks = 0u; /* initialize current counter */
+    uint32 ElapsedTicks = 0u; /* elapsed will give timeout */
+    uint8 Instance = 0u;
+    boolean TxDoneFlag = FALSE;
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(ExternalDevice != NULL_PTR);
+    DevAssert(0u != Length);
+    DevAssert(0u != TimeOut);
+    Lpspi_Ip_CheckValidParameters(ExternalDevice, Length);
+    #endif
+    Instance = ExternalDevice->Instance;
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State != NULL_PTR);
+    #endif
+    
+    Base = Lpspi_Ip_apxBases[Instance];    
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08();
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        /* Clear some bits which support for half duplex mode at previous transfer */
+        Base->CFGR1 &= ~(LPSPI_CFGR1_PCSCFG_MASK | LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK);
+        #endif
+        
+        /* Mark the hardware as busy. */
+        State->Status = LPSPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08();
+        
+        /* Disable DMA requests and all interrupts */
+        Base->DER = 0u;
+        Base->IER = 0u;
+        
+        /* Update State structure. */
+        State->NextTransferConfigAvailable = State->KeepCs;
+        
+        /* Set clock configuration */
+        if(TRUE == State->FirstCmd)
+        {
+            /* Make sure that FIFOs will be empty before start new transfer session */
+            Base->CR |= LPSPI_CR_RTF_MASK|LPSPI_CR_RRF_MASK;
+            /* clear all flags */
+
+            #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+            Base->CCR = ExternalDevice->Ccr[State->ClockMode];
+            #else
+            Base->CCR = ExternalDevice->Ccr;
+            #endif
+                /* Reset current FIFO slots are available to fill at beginning of job (HLD).*/
+            State->CurrentTxFifoSlot = LPSPI_IP_FIFO_SIZE_U8;
+            Lpspi_TransmitTxInit(Instance, TxBuffer, State->ExternalDevice->DeviceParams->FrameSize, State->ExternalDevice->DeviceParams->Lsb, Length);
+        }
+        Lpspi_TransmitRxInit(Instance, RxBuffer, State->ExternalDevice->DeviceParams->FrameSize, Length);
+        /* initialize current counter */
+        CurrentTicks = OsIf_GetCounter(LPSPI_IP_TIMEOUT_METHOD);
+        while(State->RxIndex != State->ExpectedFifoReads)
+        {
+            /* RECEIVE DATA */
+            /* The receiving should be performed first because maybe have a last frame in RX FIFO from previous channel
+                , it should be read to clear RXFIFO before start a new write to TXFIFO */
+            /* Read all Data available in receive HW fifo. */
+            NumberOfReads = (uint8)(((Base->FSR) & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
+            /* Limits to remaining frames. */
+            
+            if (NumberOfReads != 0u)
+            {
+                if (NumberOfReads > (State->ExpectedFifoReads - State->RxIndex))
+                {
+                    NumberOfReads = (uint8)(State->ExpectedFifoReads - State->RxIndex);
+                }
+                /* If these are the first frames of this channel. Current TXFIFO slot must be plus 1 because the slot of CMD have moved out */
+                if (0u == State->RxIndex)
+                {
+                    State->CurrentTxFifoSlot += 1u;
+                }
+                /* Read Data from RX FIFO */
+                Lpspi_Ip_ReadDataFromFifo(Instance, NumberOfReads);
+                /* Update current FIFO slots are available to fill .*/
+                State->CurrentTxFifoSlot += NumberOfReads;
+                ElapsedTicks = 0u;
+            }
+            
+            /* TRANSMIT DATA */                    
+            /* Push Data until HW fifo is full or transfer is done. */
+            /* After driver code read all frames in RX FIFO, if there are still some frames in TX FIFO, at the time before driver code check number of frames available in TX FIFO 
+            to prepare to fill TX FIFO. At that time, interrupt occurred, and the time to process interrupt is longer than the time to transfer all frames in TX FIFO. 
+            So TX FIFO will be empty and some frames received in RX FIFO, then the program is returned from interrupt and fill TX FIFO until full. 
+            And there is a interrupt occurred after that before read all frames in RX FIFO, and the time to process interrupt is longer than the time to transfer all frames in TX FIFO.
+            State->CurrentTxFifoSlot variable is used to hanlde number of frames are "on bus transfer". They are always less than FIFO size */
+            if((State->CurrentTxFifoSlot != 0u) && (TxDoneFlag != TRUE))
+            {
+                if(State->ExpectedFifoWrites != State->TxIndex)
+                {
+                    NumberOfWrites = State->CurrentTxFifoSlot;
+                    /* Limits to remaining frames. */
+                    if (NumberOfWrites > (State->ExpectedFifoWrites - State->TxIndex))
+                    {
+                        NumberOfWrites = (uint8)(State->ExpectedFifoWrites - State->TxIndex);
+                    }
+                    /* Push Data into TX FIFO */
+                    Lpspi_Ip_PushDataToFifo(Instance, NumberOfWrites);
+                    State->CurrentTxFifoSlot -= NumberOfWrites;
+                    ElapsedTicks = 0u;
+                }
+                else
+                {
+                    if(TRUE == State->NextTransferConfigAvailable)
+                    {
+                        /* Initialize next transfer */
+                        State->ExternalDevice->DeviceParams->DefaultData = State->DefaultDataNext;
+                        State->FirstCmd = FALSE;
+                        Lpspi_TransmitTxInit(Instance, State->TxBufferNext, State->FrameSizeNext, State->LsbNext, State->LengthNext);
+                        State->NextTransferConfigAvailable = FALSE;
+                    }
+                    else
+                    {
+                        TxDoneFlag = TRUE;
+                        if((FALSE == State->KeepCs) && (0u != (Base->TCR & LPSPI_TCR_CONT_MASK)))
+                        {
+                            /* Clear CS */
+                            Base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+                        }
+                    }
+                }
+            }
+            ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, LPSPI_IP_TIMEOUT_METHOD);
+            if (ElapsedTicks >= TimeoutTicks)
+            {
+                Status = LPSPI_IP_TIMEOUT;
+                break;
+            }
+        }
+        if (LPSPI_IP_STATUS_SUCCESS != Status)
+        {
+            State->Status = LPSPI_IP_FAULT;
+        }
+        else
+        {
+            State->Status = LPSPI_IP_IDLE;
+        }
+    }
+    return Status;
+}
+
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+Lpspi_Ip_StatusType Lpspi_Ip_SyncTransmitHalfDuplex(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *Buffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_HalfDuplexType TransferType,
+                                            uint32 TimeOut
+                                         )
+{
+    LPSPI_Type *Base;
+    Lpspi_Ip_StateStructureType *State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint32 TimeoutTicks = OsIf_MicrosToTicks(TimeOut, LPSPI_IP_TIMEOUT_METHOD);
+    uint32 CurrentTicks = 0u; /* initialize current counter */
+    uint32 ElapsedTicks = 0u; /* elapsed will give timeout */
+    uint8 Instance = 0u;
+    boolean TransferCompleted = FALSE;
+    uint8 NumberOfFramesTxFifo;
+    uint8 NumberOfWrites;
+    uint8 NumberOfReads;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(ExternalDevice != NULL_PTR);
+    DevAssert(0u != Length);
+    Lpspi_Ip_CheckValidParameters(ExternalDevice, Length);
+    #endif
+    Instance = ExternalDevice->Instance;
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State != NULL_PTR);
+    #endif
+    
+    Base = Lpspi_Ip_apxBases[Instance];
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08();
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        /* Mark the hardware as busy. */
+        State->Status = LPSPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        /* Update TransferType */
+        State->ExternalDevice->DeviceParams->TransferType = TransferType;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08();
+        
+        /* Prepare the transfer: Write to CFGR1 register the bit fields supporting Half duplex, get transfer buffer, get CMD value in reeive mode.*/
+        Lpspi_Ip_HalfDuplexPrepare(Instance, Buffer);
+        
+        /* Disable DMA requests and all interrupts */
+        Base->DER = 0u;
+        Base->IER = 0u;
+        
+        /* Update State structure. */
+        State->NextTransferConfigAvailable = State->KeepCs;
+        
+        /* Set clock configuration */
+        if(TRUE == State->FirstCmd)
+        {
+            /* Make sure that FIFOs will be empty before start new transfer session */
+            Base->CR |= LPSPI_CR_RTF_MASK|LPSPI_CR_RRF_MASK;
+            /* clear all flags */
+
+            #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+            Base->CCR = ExternalDevice->Ccr[State->ClockMode];
+            #else
+            Base->CCR = ExternalDevice->Ccr;
+            #endif
+        }
+        /* Init TX channel */
+        Lpspi_TransmitTxInit(Instance, NULL_PTR, State->ExternalDevice->DeviceParams->FrameSize, State->ExternalDevice->DeviceParams->Lsb, Length);
+        /* If in half duplex Transmit only mode, RX do not need to be configured */
+        if (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)
+        {
+            Lpspi_TransmitRxInit(Instance, NULL_PTR, State->ExternalDevice->DeviceParams->FrameSize, Length);
+        }
+        /* initialize current counter */
+        CurrentTicks = OsIf_GetCounter(LPSPI_IP_TIMEOUT_METHOD);
+        while((TRUE != TransferCompleted) && (LPSPI_IP_STATUS_SUCCESS == Status))
+        {
+            if(LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)
+            {
+                /* RECEIVE DATA */
+                /* Read all Data available in receive HW fifo. */
+                NumberOfReads = (uint8)(((Base->FSR) & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
+                if (NumberOfReads > (State->ExpectedFifoReads - State->RxIndex))
+                {
+                    NumberOfReads = (uint8)(State->ExpectedFifoReads - State->RxIndex);
+                }
+                if (0u != NumberOfReads)
+                {
+                    Lpspi_Ip_ReadDataFromFifo(Instance, NumberOfReads);
+                }
+                /* PUSH CMD */
+                /* Only write to TCR when TX FIFO is empty in receive mode */
+                if ((0u == ((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK)) && (State->ExpectedFifoWrites != State->TxIndex))
+                {
+                    /* Push one CMD to start transfer. */    
+                    Base->TCR = State->HalfDuplexTcrCommand;
+                    State->TxIndex++;
+                }
+                ElapsedTicks = 0u;
+                if (State->ExpectedFifoReads == State->RxIndex)
+                {
+                    /* if all frames have received, break from the while loop to finish transfer */  
+                    break;
+                }
+            }             
+            else
+            {
+                /* TRANSMIT DATA */                    
+                /* Push Data until HW fifo is full or transfer is done. */   
+                NumberOfFramesTxFifo = (uint8)(((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
+                NumberOfWrites = LPSPI_IP_FIFO_SIZE_U8 - NumberOfFramesTxFifo;
+                if(0u != NumberOfWrites)
+                {
+                    TransferCompleted = Lpspi_Ip_HalfDuplexTransmitProcess(Instance, NumberOfWrites);
+                }
+                /* If this is latest channel, waiting for all frames in TXFIFO have moved out before finish transfer for next job */
+                /* If next channel is in receive mode, waiting for TX of this channel to complete before start next channel */
+                if ((TRUE == TransferCompleted) && ((TRUE == State->NextChannelIsRX) || (FALSE == State->KeepCs)))
+                {
+                    TransferCompleted = FALSE;
+                    if (((Base->FSR) & LPSPI_FSR_TXCOUNT_MASK) == 0u)
+                    {
+                        TransferCompleted = TRUE;
+                    }
+                }
+                ElapsedTicks = 0u;
+            }
+            ElapsedTicks += OsIf_GetElapsed(&CurrentTicks, LPSPI_IP_TIMEOUT_METHOD);
+            if (ElapsedTicks >= TimeoutTicks)
+            {
+                Status = LPSPI_IP_TIMEOUT;
+            }
+        }
+        if (LPSPI_IP_STATUS_SUCCESS != Status)
+        {
+            State->Status = LPSPI_IP_FAULT;
+        }
+        else
+        {
+            State->Status = LPSPI_IP_IDLE;
+        }
+    }
+    return Status;
+}
+#endif
+
+static void Lpspi_TransmitTxInit(uint8 Instance,
+                                 uint8* TxBuffer,
+                                 uint8 TxFrameSize,
+                                 boolean TxLsb,
+                                 uint16 NumberOfFrames
+                                )
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 TransferCommand = 0u;
+    uint8 LsbWriteValue = TxLsb ? 1U : 0U;
+
+    State->TxFrameSize = TxFrameSize;
+    State->TxLsb = TxLsb;
+    /* Get transfer command */
+#if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+    TransferCommand = State->ExternalDevice->Tcr[State->ClockMode] | LPSPI_TCR_FRAMESZ((uint32)TxFrameSize - 1u) | LPSPI_TCR_LSBF(LsbWriteValue);
+#else
+    TransferCommand = State->ExternalDevice->Tcr | LPSPI_TCR_FRAMESZ((uint32)TxFrameSize - 1u) | LPSPI_TCR_LSBF(LsbWriteValue);
+#endif
+#if ((STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT) && (STD_ON == LPSPI_IP_SLAVE_SUPPORT))
+    /* In Receive only mode of Slave, a CMD with TXMSK should be push here */
+    if ((LPSPI_IP_HALF_DUPLEX_RECEIVE == State->ExternalDevice->DeviceParams->TransferType) && (TRUE == State->PhyUnitConfig->SlaveMode))
+    {
+        /* Mask TX in Transmit only mode */
+        TransferCommand |= LPSPI_TCR_TXMSK_MASK;
+        TransferCommand &= ~LPSPI_TCR_CONT_MASK;
+        Base->TCR = TransferCommand;
+    }
+#endif
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    /* In RX only mode, TX FIFO will be masked, Push CMD to TX FIFO to transfer and pushing CMD will be done in transfer time. Push nothing to TCR register here */
+    if (LPSPI_IP_HALF_DUPLEX_RECEIVE != State->ExternalDevice->DeviceParams->TransferType)
+#endif
+    {
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        if (LPSPI_IP_HALF_DUPLEX_TRANSMIT == State->ExternalDevice->DeviceParams->TransferType)
+        {
+            /* Mask RX FIFO in Transmit only mode */
+            TransferCommand |= LPSPI_TCR_RXMSK_MASK;
+        }
+        #endif
+        /* In Slave mode, CONT bit should be cleared */
+        #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+        if(TRUE == State->PhyUnitConfig->SlaveMode)
+        {
+            TransferCommand &= ~LPSPI_TCR_CONT_MASK;
+        }
+        #endif
+        
+        if(TRUE == State->FirstCmd)
+        {
+            /* Set transfer command */
+            Base->TCR = TransferCommand;
+        }
+        else
+        {
+            if (0u != (TransferCommand & LPSPI_TCR_CONT_MASK))
+            {
+                Base->TCR = TransferCommand | LPSPI_TCR_CONTC_MASK;
+            }
+            else
+            {
+                Base->TCR = TransferCommand;
+            }
+        }
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        if (LPSPI_IP_FULL_DUPLEX == State->ExternalDevice->DeviceParams->TransferType)
+        #endif
+        {
+            /* CMD will take 1 slot in TXFIFO, update current TX FIFO slot. it will be plus 1 when the first frames of channel have recieved */
+            State->CurrentTxFifoSlot -= 1u;
+        }
+    }
+    
+    /* Update State structure. */
+    State->TxIndex = 0u;
+    
+    /* In half duplex mode, TX buffer have updated */
+    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    if (LPSPI_IP_FULL_DUPLEX == State->ExternalDevice->DeviceParams->TransferType)
+    #endif
+    {
+        State->TxBuffer = TxBuffer;  
+    }
+    
+    if (TxFrameSize < 9u)
+    {
+        State->ExpectedFifoWrites = NumberOfFrames;
+    }
+    else if (TxFrameSize < 17u)
+    {
+        State->ExpectedFifoWrites = NumberOfFrames/2u;
+    }
+    else
+    {
+        State->ExpectedFifoWrites = NumberOfFrames/4u;
+    }
+}
+
+static void Lpspi_TransmitRxInit(uint8 Instance,
+                                      uint8* RxBuffer,
+                                      uint8 RxFrameSize,
+                                      uint16 NumberOfFrames
+                                     )
+{
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    
+    /* Update State structure. */
+    State->RxIndex = 0u;
+    
+    /* In half duplex mode, RX buffer have updated */
+    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+    if (LPSPI_IP_FULL_DUPLEX != State->ExternalDevice->DeviceParams->TransferType)
+    {
+        (void)RxBuffer; 
+    }
+    else
+    #endif        
+    {
+        State->RxBuffer = RxBuffer; 
+    }
+    
+    if (RxFrameSize < 9u)
+    {
+        State->ExpectedFifoReads = NumberOfFrames;
+    }
+    else if (RxFrameSize < 17u)
+    {
+        State->ExpectedFifoReads = NumberOfFrames/2u;
+    }
+    else
+    {
+        State->ExpectedFifoReads = NumberOfFrames/4u;
+    }
+}
+
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmit(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *TxBuffer,
+                                            uint8 *RxBuffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_CallbackType EndCallback
+                                          )
+{
+    LPSPI_Type* Base;
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint8 Instance = 0u;
+    #if (STD_ON == LPSPI_IP_DMA_USED)
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    #endif
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(ExternalDevice != NULL_PTR);
+    DevAssert(0u != Length);
+    Lpspi_Ip_CheckValidParameters(ExternalDevice, Length);
+    #endif
+    Instance = ExternalDevice->Instance;
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State != NULL_PTR);
+    #endif
+    
+    Base = Lpspi_Ip_apxBases[Instance];
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09();
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        /* Clear some bits which support for half duplex mode at previous transfer */
+        Base->CFGR1 &= ~(LPSPI_CFGR1_PCSCFG_MASK | LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK);
+        #endif
+        /* Mark the hardware as busy. */
+        State->Status = LPSPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09();
+        
+        /* Update State structure. */
+        State->Callback = EndCallback;
+        State->NextTransferConfigAvailable = State->KeepCs;
+        
+        /* Reset TX done flag */
+        State->TxDoneFlag = FALSE;
+        
+        /* Set clock configuration */
+        if(TRUE == State->FirstCmd)
+        {
+            SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11();
+            /* Make sure that FIFOs will be empty before start new transfer session */
+            Base->CR |= LPSPI_CR_RTF_MASK|LPSPI_CR_RRF_MASK;
+            /* clear all flags */
+            Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+            /* Does not use the Clock Configuration Register (CCR) for Slave mode */
+            #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+            if(FALSE == State->PhyUnitConfig->SlaveMode)
+            #endif
+            {
+                #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+                Base->CCR = ExternalDevice->Ccr[State->ClockMode];
+                #else
+                Base->CCR = ExternalDevice->Ccr;
+                #endif
+            }
+            /* Update current FIFO slots are available to fill .*/
+            State->CurrentTxFifoSlot = LPSPI_IP_FIFO_SIZE_U8;
+            /* In setting up Transmit command register, the RXMSK is also cleared */
+            Lpspi_TransmitTxInit(Instance, TxBuffer, State->ExternalDevice->DeviceParams->FrameSize, State->ExternalDevice->DeviceParams->Lsb, Length);
+            SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11();
+        }
+        Lpspi_TransmitRxInit(Instance, RxBuffer, State->ExternalDevice->DeviceParams->FrameSize, Length);
+        
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        if (FALSE == State->PhyUnitConfig->DmaUsed)
+        #endif
+        {
+            #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+            if (TRUE == State->PhyUnitConfig->SlaveMode)
+            {
+                Base->FCR = LPSPI_FCR_TXWATER(0u);
+            }
+            else
+            #endif
+            {
+                /* Set TX water */
+                Base->FCR = LPSPI_FCR_TXWATER((uint32)LPSPI_IP_FIFO_SIZE_U8 - (uint32)1u);
+            }
+            
+            /* Disable DMA requests */
+            Base->DER = 0u;
+            switch (State->TransferMode)
+            {
+                case LPSPI_IP_POLLING:
+                    /* Disable interrupts. */
+                    Base->IER = 0u;
+                    break;
+                case LPSPI_IP_INTERRUPT:
+                    Base->IER = LPSPI_IER_RDIE_MASK | LPSPI_IER_TDIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_TEIE_MASK;
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }
+        }
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        else
+        {
+            /* Disable all interrupts */
+            Base->IER = 0u;
+            /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */
+            DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+            switch(State->TransferMode)
+            {
+                case LPSPI_IP_POLLING:
+                    /* Disable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 0u;
+                    break;
+                case LPSPI_IP_INTERRUPT:
+                    /* Enable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 1u;
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }
+            /* TX WATER should be set again to LPSPI_IP_FIFO_SIZE_U8 - 3 to make sure when TX DMA finish, at least 2 TX FIFO slots are available to
+                fill CMD and the first frame of next channel */
+            Base->FCR = LPSPI_FCR_TXWATER((uint32)LPSPI_IP_FIFO_SIZE_U8 - (uint32)3u);
+            
+            (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+            (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u);
+
+            /* Initialize DMA configuration for RX before TX*/
+            Lpspi_Ip_RxDmaConfig(Instance);
+            if(TRUE == State->FirstCmd)
+            {
+                /* Call function to configure TX DMA channel only for the first channel, others channels will be done in TX DMA notification function */
+                Lpspi_Ip_TxDmaConfig(Instance);
+            }
+            /* Enable DMA request. */
+            Base->DER = LPSPI_DER_RDDE_MASK | LPSPI_DER_TDDE_MASK;
+        }
+        #endif
+    }
+    return Status;
+}
+
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmitHalfDuplex(
+                                            const Lpspi_Ip_ExternalDeviceType *ExternalDevice,
+                                            uint8 *Buffer,
+                                            uint16 Length,
+                                            Lpspi_Ip_HalfDuplexType TransferType,
+                                            Lpspi_Ip_CallbackType EndCallback
+                                          )
+{
+    LPSPI_Type* Base;
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint8 Instance = 0u;
+    uint32 InterruptEnable = 0u;
+    #if (STD_ON == LPSPI_IP_DMA_USED)
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    #endif
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(ExternalDevice != NULL_PTR);
+    DevAssert(0u != Length);
+    Lpspi_Ip_CheckValidParameters(ExternalDevice, Length);
+    #endif
+    Instance = ExternalDevice->Instance;
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(State != NULL_PTR);
+    #endif
+    
+    Base = Lpspi_Ip_apxBases[Instance];
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09();
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        /* Mark the hardware as busy. */
+        State->Status = LPSPI_IP_BUSY;
+        State->ExternalDevice = ExternalDevice;
+        /* Update TransferType */
+        State->ExternalDevice->DeviceParams->TransferType = TransferType;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09();
+
+        /* Prepare the transfer: Write to CFGR1 register the bit fields supporting Half duplex, get transfer buffer, get CMD value in reeive mode.*/
+        Lpspi_Ip_HalfDuplexPrepare(Instance, Buffer);
+        
+        /* Update State structure. */
+        State->Callback = EndCallback;
+        State->NextTransferConfigAvailable = State->KeepCs;
+        
+        /* Set clock configuration */
+        if(TRUE == State->FirstCmd)
+        {
+            SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11();
+            /* Make sure that FIFOs will be empty before start new transfer session */
+            Base->CR |= LPSPI_CR_RTF_MASK|LPSPI_CR_RRF_MASK;
+            /* clear all flags */
+            Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+            /* Does not use the Clock Configuration Register (CCR) for Slave mode */
+            #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+            if(FALSE == State->PhyUnitConfig->SlaveMode)
+            #endif
+            {
+                #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+                Base->CCR = ExternalDevice->Ccr[State->ClockMode];
+                #else
+                Base->CCR = ExternalDevice->Ccr;
+                #endif
+            }
+            SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11();
+        }
+        /* Init TX channel */
+        Lpspi_TransmitTxInit(Instance, NULL_PTR, State->ExternalDevice->DeviceParams->FrameSize, State->ExternalDevice->DeviceParams->Lsb, Length);
+        /* If in Transmit only mode, RX do not need to be configured */
+        if (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)
+        {
+            Lpspi_TransmitRxInit(Instance, NULL_PTR, State->ExternalDevice->DeviceParams->FrameSize, Length);
+        }
+        
+        #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+        if ((TRUE == State->PhyUnitConfig->SlaveMode) && (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType))
+        {
+            /* In slave receive mode, only use RX Flags */
+            InterruptEnable = LPSPI_IER_RDIE_MASK | LPSPI_IER_REIE_MASK;
+        }
+        else
+        #endif                
+        {
+            /* Others mode still use TX flag to trigger to push CMDs */
+            InterruptEnable = LPSPI_IER_RDIE_MASK | LPSPI_IER_TDIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_TEIE_MASK;
+        }
+        
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        if (FALSE == State->PhyUnitConfig->DmaUsed)
+        #endif
+        {
+            /* In Receive mode, Next CMD could only be pushed to TXFIFO when previous CMD have moved out (TXFIFO is empty) 
+               On Slave receive mode, do not care about TX WATER because TDIE flag is not set */
+            if (LPSPI_IP_HALF_DUPLEX_RECEIVE == TransferType)
+            {
+                Base->FCR = LPSPI_FCR_TXWATER(0u);
+            }
+            else
+            {
+                Base->FCR = LPSPI_FCR_TXWATER((uint32)LPSPI_IP_FIFO_SIZE_U8 - (uint32)1u);
+            }                
+            /* Disable DMA requests */
+            Base->DER = 0u;               
+            switch (State->TransferMode)
+            {
+                case LPSPI_IP_POLLING:
+                    /* Disable interrupts. */
+                    Base->IER = 0u;
+                    break;
+                case LPSPI_IP_INTERRUPT:
+                    Base->IER = InterruptEnable;
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }
+        }
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        else
+        {
+            /* Disable all interrupts */
+            Base->IER = 0u;
+            /* Activate TX DMA and RX DMA interrupt in interrupt mode or disable then in polling mode. */
+            DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+            switch(State->TransferMode)
+            {
+                case LPSPI_IP_POLLING:
+                    /* Disable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 0u;
+                    break;
+                case LPSPI_IP_INTERRUPT:
+                    /* Enable DMA major interrupt. */
+                    DmaTcdList[0u].Value = 1u;
+                    break;
+                default:
+                    /* Nothing to do */
+                    break;
+            }               
+            if (LPSPI_IP_HALF_DUPLEX_TRANSMIT == TransferType)
+            {
+                (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+                
+                /* TX WATER should be set again to LPSPI_IP_FIFO_SIZE_U8 - 2 to make sure when TX DMA finish, at least 1 TX FIFO slots are available to
+                fill CMD (in the case clear CONT bit) at latest channel in job */
+                Base->FCR = LPSPI_FCR_TXWATER((uint32)LPSPI_IP_FIFO_SIZE_U8 - (uint32)2u);
+                
+                /* Call function to configure TX DMA channel only for the first channel, others channels will be done in TX DMA notification function */
+                /* In Transmit only mode, this function only is called here */
+                Lpspi_Ip_TxDmaConfig(Instance);
+                /* Enable DMA request. */
+                Base->DER = LPSPI_DER_TDDE_MASK;
+            }
+            else
+            {
+                /* Reveive only mode still need TX channel to sent CMD to provide clock out */
+                (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->TxDmaChannel, DmaTcdList, 1u);
+                (void)Dma_Ip_SetLogicChannelTransferList(State->PhyUnitConfig->RxDmaChannel, DmaTcdList, 1u);
+                
+                /* TX WATER sets to 0 to make sure that TX DMA only write 1 CMD and wait for this CMD have moved out to perform to push next CMD */
+                Base->FCR = LPSPI_FCR_TXWATER(0u);
+                
+                #if (STD_ON == LPSPI_IP_SLAVE_SUPPORT)
+                if (TRUE == State->PhyUnitConfig->SlaveMode)
+                {
+                    /* In Half duplex slave receive mode, only RX DMA channel needed */
+                    Lpspi_Ip_RxDmaConfig(Instance);
+                    /* Enable DMA request. */
+                    Base->DER = LPSPI_DER_RDDE_MASK;  
+                }
+                else
+                #endif
+                {
+                    /* In receive only mode, TX DMA Channel will be used to push CMD to start transfer */
+                    Lpspi_Ip_RxDmaConfig(Instance);
+                    Lpspi_Ip_TxDmaConfig(Instance);
+                    /* Enable DMA request. */
+                    Base->DER = LPSPI_DER_RDDE_MASK | LPSPI_DER_TDDE_MASK;  
+                }
+            }
+        }
+        #endif
+    }
+    return Status;
+}
+#endif
+
+#if (STD_ON == LPSPI_IP_DMA_USED)
+#if (STD_ON == LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT)
+Lpspi_Ip_StatusType Lpspi_Ip_AsyncTransmitFast(
+                                       const Lpspi_Ip_FastTransferType *FastTransferCfg,
+                                       uint8 NumberOfTransfer,
+                                       Lpspi_Ip_CallbackType EndCallback
+                                      )
+{
+    LPSPI_Type* Base;
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    uint8 Instance = 0u;
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    uint8 Count = 0u;
+
+    DevAssert(NULL_PTR != FastTransferCfg);
+    DevAssert(NULL_PTR != FastTransferCfg[0u].ExternalDevice);
+    #endif
+    Instance = FastTransferCfg[0u].ExternalDevice->Instance;
+    Base = Lpspi_Ip_apxBases[Instance];
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR == State);
+    DevAssert(State->TransferMode == LPSPI_IP_INTERRUPT);
+    DevAssert(NumberOfTransfer <= State->PhyUnitConfig->MaxNumOfFastTransfer);
+    for(Count = 0u; Count < NumberOfTransfer; Count++)
+    {
+        DevAssert(NULL_PTR != FastTransferCfg[Count].ExternalDevice);
+        DevAssert(0u != FastTransferCfg[Count].Length);
+        DevAssert(FastTransferCfg[0u].ExternalDevice->DeviceParams->FrameSize <= 16u);
+        if (FastTransferCfg[0u].ExternalDevice->DeviceParams->FrameSize > 8u)
+        {
+            DevAssert((FastTransferCfg[Count].Length%2) == 0u);
+        }
+        else
+        {
+            DevAssert(LPSPI_IP_DMA_MAX_ITER_CNT_U16 >= FastTransferCfg[Count].Length);
+        }
+    }
+    #endif
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15();
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    else
+    {
+        #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+        /* Clear some bits which support for half duplex mode at previous transfer */
+        Base->CFGR1 &= ~(LPSPI_CFGR1_PCSCFG_MASK | LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK);
+        #endif
+        
+        /* Mark the hardware as busy. */
+        State->Status = LPSPI_IP_BUSY;
+
+        /* Update State structure. */
+        /* For Dma Fast transfer, All transfers use the same HWUnit and in Master mode only.
+        Some parameters such as Baudrate, Delays timming SpiTimeClk2Cs, SpiTimeCs2Clk, SpiTimeCs2Cs, SpiDataWidth, SpiTransferStart configuration 
+        must be the same between transfers. So, make sure they are configured the same in each External Device allocated for Dma Fast Transfers.
+        And all those attributes can be got from first transfer in FastTransferCfg */
+        State->ExternalDevice = FastTransferCfg[0u].ExternalDevice;
+        State->Callback = EndCallback;
+
+        /* Disable module before configure CCR */
+        Base->CR &= ~LPSPI_CR_MEN_MASK;
+        /* Make sure that FIFOs will be empty before start new transfer session */
+        Base->CR |= LPSPI_CR_RTF_MASK|LPSPI_CR_RRF_MASK;
+
+        /* clear all flags */
+        Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+        #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+        Base->CCR = FastTransferCfg[0u].ExternalDevice->Ccr[State->ClockMode];
+        #else
+        Base->CCR = FastTransferCfg[0u].ExternalDevice->Ccr;
+        #endif
+        Base->CR |= LPSPI_CR_MEN_MASK;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15();
+
+        /* Disable all interrupts */
+        Base->IER = 0u;
+        /* Enable DMA request. */
+        Base->DER = LPSPI_DER_RDDE_MASK | LPSPI_DER_TDDE_MASK;
+
+        Lpspi_Ip_DmaFastConfig(Instance, FastTransferCfg, NumberOfTransfer);
+    }
+    return Status;
+}
+
+/**
+* @brief   This function will configure Scatter/Gather TCDs for the channels TX DMA, RX DMA and CMD DMA 
+*          according to Dma Fast transfers configuration. DMA channels will be started at the end of the function.
+*/
+static void Lpspi_Ip_DmaFastConfig(uint8 Instance, const Lpspi_Ip_FastTransferType *FastTransferCfg, uint8 NumberOfTransfer)
+{
+    Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    boolean ClearCS = FALSE;
+    uint8 DisHwRequest = 0u;
+    uint8 Count = 0u;
+    uint8 TxDmaTCDSGIndex = 0u;
+    uint32 TransferCommand = 0u;
+    uint32 LSBBit = 0UL;
+    boolean FirstCmd = TRUE;
+    Dma_Ip_LogicChannelTransferListType DmaTcdList[1u];
+    
+    DmaTcdList[0u].Param = DMA_IP_CH_SET_CONTROL_EN_MAJOR_INTERRUPT;
+    DmaTcdList[0u].Value = 1u;
+
+    for(Count = 0u; Count < NumberOfTransfer; Count++)
+    {
+        /* Update State structure. */
+        State->RxIndex = 0u;
+        State->TxIndex = 0u;
+        State->TxBuffer = FastTransferCfg[Count].TxBuffer;
+        State->RxBuffer = FastTransferCfg[Count].RxBuffer;
+        if (State->ExternalDevice->DeviceParams->FrameSize < 9u)
+        {
+            State->ExpectedFifoWrites = FastTransferCfg[Count].Length;
+        }
+        else if (State->ExternalDevice->DeviceParams->FrameSize < 17u)
+        {
+            State->ExpectedFifoWrites = FastTransferCfg[Count].Length/2u;
+        }
+        else
+        {
+            State->ExpectedFifoWrites = FastTransferCfg[Count].Length/4u;
+        }
+        State->ExpectedFifoReads = State->ExpectedFifoWrites;
+        State->PhyUnitConfig->CmdDmaFast[Count].DefaultData = FastTransferCfg[Count].DefaultData;
+        LSBBit = State->ExternalDevice->DeviceParams->Lsb ? 1UL : 0UL;
+
+        /* Get transfer command */
+    #if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+        TransferCommand = FastTransferCfg[Count].ExternalDevice->Tcr[State->ClockMode] | LPSPI_TCR_FRAMESZ((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) | LPSPI_TCR_LSBF(LSBBit);
+    #else
+        TransferCommand = FastTransferCfg[Count].ExternalDevice->Tcr | LPSPI_TCR_FRAMESZ((uint32)State->ExternalDevice->DeviceParams->FrameSize - 1u) | LPSPI_TCR_LSBF(LSBBit);
+    #endif
+
+        if (0u != (TransferCommand & LPSPI_TCR_CONT_MASK))
+        {
+            if(TRUE == FirstCmd)
+            {
+                FirstCmd = FALSE;
+                /* In continue CS, no need to set CONTC for first command */
+                State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmd = TransferCommand;
+            }
+            else
+            {
+                /* In continue CS, need to set CONTC for next command */
+                State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmd = TransferCommand | LPSPI_TCR_CONTC_MASK;
+            }
+            State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmdLast = TransferCommand & (~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK));
+        }
+        else
+        {
+            /* In non-continue CS, set DmaFastTcrCmd = DmaFastTcrCmdLast */
+            State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmd = TransferCommand;
+            State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmdLast = TransferCommand;
+        }
+        if(FALSE == FastTransferCfg[Count].KeepCs)
+        {
+            /* After CS is cleared, next transfer will be set as first command */
+            FirstCmd = TRUE;
+        }
+
+        /* CS will be cleared for last transfer or depend on KeepCs if not last transfer.
+        Disable DMA HW request at the end of transfer. */
+        if (Count == (NumberOfTransfer - 1u))
+        {
+            ClearCS = TRUE;
+            DisHwRequest = 1u;
+        }
+        else
+        {
+            if(FALSE == FastTransferCfg[Count].KeepCs)
+            {
+                ClearCS = TRUE;
+            }
+            else
+            {
+                ClearCS = FALSE;
+            }
+            DisHwRequest = 0u;
+        }
+
+        /* Configure software TCDs Scatter Gather for TX DMA channel to update TCR */
+        /* No disable dma hw request for transfer command */
+        Lpspi_Ip_CmdTxDmaTcdSGConfig(Instance, TxDmaTCDSGIndex, (uint32)&State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmd, 0u);
+        TxDmaTCDSGIndex++;
+
+        if((TRUE == ClearCS) && (0u != (TransferCommand & LPSPI_TCR_CONT_MASK)))
+        {
+            /* Configure software TCDs Scatter Gather for TX DMA channel to fill TDR, no disable dma hw request */
+            Lpspi_Ip_TxDmaTcdSGConfig(Instance, TxDmaTCDSGIndex, 0u, (const uint32 *)&State->PhyUnitConfig->CmdDmaFast[Count].DefaultData);
+            TxDmaTCDSGIndex++;
+            /* disable dma hw request for last transfer command */
+            Lpspi_Ip_CmdTxDmaTcdSGConfig(Instance, TxDmaTCDSGIndex, (uint32)&State->PhyUnitConfig->CmdDmaFast[Count].DmaFastTcrCmdLast, DisHwRequest);
+            TxDmaTCDSGIndex++;
+        }
+        else
+        {
+            /* Configure software TCDs Scatter Gather for TX DMA channel to fill TDR */
+            Lpspi_Ip_TxDmaTcdSGConfig(Instance, TxDmaTCDSGIndex, DisHwRequest, (const uint32 *)&State->PhyUnitConfig->CmdDmaFast[Count].DefaultData);
+            TxDmaTCDSGIndex++;
+        }
+        
+        /* Configure software TCDs Scatter Gather for RX DMA channel */
+        Lpspi_Ip_RxDmaTcdSGConfig(Instance, Count, DisHwRequest);
+    }
+    
+    /* When all transfers session are completed and next TCD ScatterGather is loaded to HW. If next TCD ScatterGather loaded has INTMAJOR=0 then 
+    Dma_Ip interrupt function will not call Spi Dma notification due to it understood as spurious interrupt(Done flag = 1, INTMAJOR=0).
+    So, the workaround is set INTMAJOR=1 for next TCD ScatterGather. */
+    if (TxDmaTCDSGIndex < State->PhyUnitConfig->NumberTxSG)
+    {
+        /* Set INTMAJOR=1 for next TX TCD ScatterGather */
+        (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[TxDmaTCDSGIndex], DmaTcdList, 1u);
+    }
+    if (NumberOfTransfer < State->PhyUnitConfig->NumberRxSG)
+    {
+        /* Set INTMAJOR=1 for next RX TCD ScatterGather */
+        (void)Dma_Ip_SetLogicChannelScatterGatherList(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitConfig->RxDmaFastSGId[NumberOfTransfer], DmaTcdList, 1u);
+    }
+    
+    /* Load first software TCD to hardware TCD for TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->TxDmaChannel, State->PhyUnitConfig->TxDmaFastSGId[0u]);
+    /* Load first software TCD to hardware TCD for RX DMA channel */
+    (void)Dma_Ip_SetLogicChannelScatterGatherConfig(State->PhyUnitConfig->RxDmaChannel, State->PhyUnitConfig->RxDmaFastSGId[0u]);
+
+    /* Enable HW request for RX DMA channel before TX DMA channel */
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+    (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
+}
+#endif
+#endif
+
+void Lpspi_Ip_ManageBuffers(uint8 Instance)
+{
+    const LPSPI_Type* Base;
+    const Lpspi_Ip_StateStructureType* State;
+    #if (STD_ON == LPSPI_IP_DMA_USED)
+    Dma_Ip_LogicChannelStatusType DmaChannelStatus;
+    #endif
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    Base = Lpspi_Ip_apxBases[Instance];
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    if (LPSPI_IP_POLLING == State->TransferMode)
+    {
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        if(FALSE == State->PhyUnitConfig->DmaUsed)
+        #endif
+        {
+            /* In half duplex master mode:
+                - Transmit: TDF is set only, RDF will never be set by RX FIFO have masked.
+                - Receive: Both TDF (push CDM) and DRF (receive data) are set.
+               In half duplex Slave mode:
+                - Transmit: TDF is set only, RDF will never be set by RX FIFO have masked.
+                - Receive: Both TDF and RDF are set. But only process for RDF to receive data. In this case, State->CurrentTxFifoSlot will be set to 0 */
+            if(
+                (0u != (Base->SR & LPSPI_SR_RDF_MASK)) ||
+                ((0u != (Base->SR & LPSPI_SR_TDF_MASK)) && (0u!= State->CurrentTxFifoSlot))
+               )
+            {
+                #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+                if (LPSPI_IP_FULL_DUPLEX != State->ExternalDevice->DeviceParams->TransferType)
+                {
+                    Lpspi_Ip_TransferProcessHalfDuplex(Instance);
+                }
+                else
+                #endif
+                {
+                    Lpspi_Ip_TransferProcess(Instance); 
+                }
+            }
+        }
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        else
+        {
+            /* Polling RX before TX */
+            (void)Dma_Ip_GetLogicChannelStatus(State->PhyUnitConfig->RxDmaChannel, &DmaChannelStatus);
+            if(TRUE == DmaChannelStatus.Done)
+            {
+                /* Clear DONE bit */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_DONE);
+                Lpspi_Ip_IrqRxDmaHandler(Instance);
+            }
+            
+            (void)Dma_Ip_GetLogicChannelStatus(State->PhyUnitConfig->TxDmaChannel, &DmaChannelStatus);
+            if(TRUE == DmaChannelStatus.Done)
+            {
+                /* Clear DONE bit */
+                (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_DONE);
+                Lpspi_Ip_IrqTxDmaHandler(Instance);
+            }
+        }
+        #endif
+    }
+}
+/*================================================================================================*/
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateFrameSize(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, uint8 FrameSize)
+{
+    const Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    DevAssert(LPSPI_IP_FRAMESIZE_MAX_U8 >= FrameSize);
+    DevAssert(LPSPI_IP_FRAMESIZE_MIN_U8 <= FrameSize);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Frame size can be changed when no transfers are in progress. */
+    if (State->Status != LPSPI_IP_BUSY)
+    {
+        ExternalDevice->DeviceParams->FrameSize = FrameSize;
+    }
+    else
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateLsb(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, boolean Lsb)
+{
+    const Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Bite order can be changed when no transfers are in progress. */
+    if (State->Status != LPSPI_IP_BUSY)
+    {
+        ExternalDevice->DeviceParams->Lsb = Lsb;
+    }
+    else
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateDefaultTransmitData(const Lpspi_Ip_ExternalDeviceType *ExternalDevice, uint32 DefaultData)
+{
+    const Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != ExternalDevice);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[ExternalDevice->Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Bite order can be changed when no transfers are in progress. */
+    if (State->Status != LPSPI_IP_BUSY)
+    {
+        ExternalDevice->DeviceParams->DefaultData = DefaultData;
+    }
+    else
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+Lpspi_Ip_StatusType Lpspi_Ip_UpdateTransferMode(uint8 Instance, Lpspi_Ip_ModeType Mode)
+{
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Transfer mode can be changed when no transfers are in progress. */
+    if (State->Status != LPSPI_IP_BUSY)
+    {
+        State->TransferMode = Mode;
+    }
+    else
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }
+    return Status;
+}
+
+void Lpspi_Ip_Cancel(uint8 Instance)
+{
+    LPSPI_Type* Base;
+    Lpspi_Ip_StateStructureType* State;
+    uint32 Cfgr1 = 0u;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    Base = Lpspi_Ip_apxBases[Instance];
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10();
+    if (LPSPI_IP_BUSY == State->Status)
+    {
+        /* Mask Rx to discard received data */
+        Base->TCR |= LPSPI_TCR_RXMSK(1);
+        /* store CFGR1 and restore after all registers are reset */
+        Cfgr1 = Base->CFGR1;
+        /* Disable interrupts and DMA requests. */
+        /* Clear FIFO */
+        /* RTF and RRF will not clear shifter, so RST must be used to ensure old Data in shifter will also be cleared. */
+        Base->CR |= LPSPI_CR_RST_MASK;
+        Base->CR &= ~LPSPI_CR_RST_MASK;
+        /* restore CFGR1 */
+        Base->CFGR1 = Cfgr1;
+        #if (STD_ON == LPSPI_IP_DMA_USED)
+        if(TRUE == State->PhyUnitConfig->DmaUsed)
+        {
+            /* Disable all HW request */
+            (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->RxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+            (void)Dma_Ip_SetLogicChannelCommand(State->PhyUnitConfig->TxDmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
+        }
+        #endif
+        /* set State to idle */
+        State->Status = LPSPI_IP_IDLE;
+    }
+    SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10();
+}
+/**
+* @brief   This function is called by LSPI ISRs.
+* @details This function will process activities for flags TDF, RDF, REF and TEF.
+*
+* @param[in]     Instance            Instance of the hardware unit.
+*
+* @implements Lpspi_Ip_IrqHandler_Activity
+*/
+void Lpspi_Ip_IrqHandler(uint8 Instance)
+{
+    LPSPI_Type* Base = Lpspi_Ip_apxBases[Instance];
+    const Lpspi_Ip_StateStructureType* State = Lpspi_Ip_apxStateStructureArray[Instance];
+    uint32 IrqFlags = 0u;
+
+    if (NULL_PTR != State)
+    {
+        /* the driver has been initialized */
+        IrqFlags = Base->SR & (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK);
+        IrqFlags &= Base->IER & (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK);
+        if (0u != IrqFlags)
+        {
+            #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)
+            if (
+                (LPSPI_IP_HALF_DUPLEX_TRANSMIT == State->ExternalDevice->DeviceParams->TransferType) ||
+                (LPSPI_IP_HALF_DUPLEX_RECEIVE == State->ExternalDevice->DeviceParams->TransferType)
+                )
+            {
+                Lpspi_Ip_TransferProcessHalfDuplex(Instance);    
+            }
+            else
+            #endif
+            {
+                Lpspi_Ip_TransferProcess(Instance); 
+            }
+        }
+        else
+        {
+            /* Driver has been initialized and received an unconfigured interrupt, clear all flags */
+            Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+        }
+    }
+    else
+    {
+        /* the driver has not been initialized */
+        /* clear all flags */
+        Base->SR &= LPSPI_IP_SR_W1C_MASK_U32;
+    }
+}
+
+Lpspi_Ip_HwStatusType Lpspi_Ip_GetStatus(uint8 Instance)
+{
+    const Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_HwStatusType Status = LPSPI_IP_UNINIT;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    if (State != NULL_PTR)
+    {
+        Status = State->Status;
+    }
+    
+    return Status;
+}
+
+#if (STD_ON == LPSPI_IP_DUAL_CLOCK_MODE)
+Lpspi_Ip_StatusType Lpspi_Ip_SetClockMode(uint8 Instance, Lpspi_Ip_DualClockModeType ClockMode)
+{
+    Lpspi_Ip_StateStructureType* State;
+    Lpspi_Ip_StatusType Status = LPSPI_IP_STATUS_SUCCESS;
+    
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(Instance < LPSPI_INSTANCE_COUNT);
+    #endif
+    State = Lpspi_Ip_apxStateStructureArray[Instance];
+    #if (STD_ON == LPSPI_IP_DEV_ERROR_DETECT)
+    DevAssert(NULL_PTR != State);
+    #endif
+    /* Clock mode can be changed when no transfers are in progress. */
+    if (State->Status != LPSPI_IP_BUSY)
+    {
+        State->ClockMode = ClockMode;
+    }
+    else
+    {
+        Status = LPSPI_IP_STATUS_FAIL;
+    }  
+    return Status;
+}
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Lpspi_Ip_Irq.c

@@ -0,0 +1,286 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Lpspi_Ip_Irq.c
+*   @implements     Lpspi_Ip_Irq.c_Artifact
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file.
+*   @details Generated Post-Build(PB) configuration file.
+*
+*   @addtogroup LPSPI_DRIVER Lpspi Driver
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Lpspi_Ip.h"
+
+/*==================================================================================================
+*                                       SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define LPSPI_IP_VENDOR_ID_IRQ_C                      43
+#define LPSPI_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C       4
+#define LPSPI_IP_AR_RELEASE_MINOR_VERSION_IRQ_C       4
+#define LPSPI_IP_AR_RELEASE_REVISION_VERSION_IRQ_C    0
+#define LPSPI_IP_SW_MAJOR_VERSION_IRQ_C               1
+#define LPSPI_IP_SW_MINOR_VERSION_IRQ_C               0
+#define LPSPI_IP_SW_PATCH_VERSION_IRQ_C               0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Lpspi_Ip.h and Lpspi_Ip_Irq.c are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID != LPSPI_IP_VENDOR_ID_IRQ_C)
+    #error "Lpspi_Ip.h and Lpspi_Ip_Irq.c have different vendor ids"
+#endif
+/* Check if Lpspi_Ip.h file and Lpspi_Ip_Irq.c file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION != LPSPI_IP_AR_RELEASE_MINOR_VERSION_IRQ_C) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION != LPSPI_IP_AR_RELEASE_REVISION_VERSION_IRQ_C))
+#error "AutoSar Version Numbers of Lpspi_Ip.h and Lpspi_Ip_Irq.c are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION != LPSPI_IP_SW_MAJOR_VERSION_IRQ_C) || \
+     (LPSPI_IP_SW_MINOR_VERSION != LPSPI_IP_SW_MINOR_VERSION_IRQ_C) || \
+     (LPSPI_IP_SW_PATCH_VERSION != LPSPI_IP_SW_PATCH_VERSION_IRQ_C))
+#error "Software Version Numbers of Lpspi_Ip.h and Lpspi_Ip_Irq.c are different"
+#endif
+/*==================================================================================================
+*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef LPSPI_IP_0_ENABLED
+    #if (LPSPI_IP_0_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_0_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_0_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_0_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_1_ENABLED
+    #if (LPSPI_IP_1_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_1_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_1_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_1_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_2_ENABLED
+    #if (LPSPI_IP_2_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_2_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_2_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_2_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_3_ENABLED
+    #if (LPSPI_IP_3_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_3_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_3_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_3_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_4_ENABLED
+    #if (LPSPI_IP_4_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_4_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_4_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_4_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_5_ENABLED
+    #if (LPSPI_IP_5_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_5_IRQHandler);
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_5_IrqTxDmaHandler(void);
+void Lpspi_Ip_LPSPI_5_IrqRxDmaHandler(void);
+        #endif
+    #endif
+#endif
+
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+#ifdef LPSPI_IP_0_ENABLED
+    #if (LPSPI_IP_0_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_0_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(0u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_0_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(0u);
+}
+void Lpspi_Ip_LPSPI_0_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(0u);
+}
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_1_ENABLED
+    #if (LPSPI_IP_1_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_1_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(1u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_1_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(1u);
+}
+void Lpspi_Ip_LPSPI_1_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(1u);
+}
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_2_ENABLED
+    #if (LPSPI_IP_2_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_2_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(2u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_2_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(2u);
+}
+void Lpspi_Ip_LPSPI_2_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(2u);
+}
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_3_ENABLED
+    #if (LPSPI_IP_3_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_3_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(3u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_3_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(3u);
+}
+void Lpspi_Ip_LPSPI_3_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(3u);
+}
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_4_ENABLED
+    #if (LPSPI_IP_4_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_4_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(4u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_4_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(4u);
+}
+void Lpspi_Ip_LPSPI_4_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(4u);
+}
+        #endif
+    #endif
+#endif
+#ifdef LPSPI_IP_5_ENABLED
+    #if (LPSPI_IP_5_ENABLED == STD_ON)
+ISR(Lpspi_Ip_LPSPI_5_IRQHandler)
+{
+    Lpspi_Ip_IrqHandler(5u);
+    EXIT_INTERRUPT();
+}
+        #if (LPSPI_IP_DMA_USED == STD_ON)
+void Lpspi_Ip_LPSPI_5_IrqTxDmaHandler(void)
+{
+    Lpspi_Ip_IrqTxDmaHandler(5u);
+}
+void Lpspi_Ip_LPSPI_5_IrqRxDmaHandler(void)
+{
+    Lpspi_Ip_IrqRxDmaHandler(5u);
+}
+        #endif
+    #endif
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/SchM_Spi.c

@@ -0,0 +1,1188 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : 
+*   Dependencies         : none
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file
+*
+*   @addtogroup RTE_MODULE
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                         INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Std_Types.h"
+#include "Mcal.h"
+#include "OsIf.h"
+#include "SchM_Spi.h"
+#ifdef MCAL_TESTING_ENVIRONMENT
+#include "EUnit.h" /* EUnit Test Suite */
+#endif
+
+/*==================================================================================================
+*                               SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SCHM_SPI_AR_RELEASE_MAJOR_VERSION_C     4
+#define SCHM_SPI_AR_RELEASE_MINOR_VERSION_C     4
+#define SCHM_SPI_AR_RELEASE_REVISION_VERSION_C  0
+#define SCHM_SPI_SW_MAJOR_VERSION_C             1
+#define SCHM_SPI_SW_MINOR_VERSION_C             0
+#define SCHM_SPI_SW_PATCH_VERSION_C             0
+
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+#ifdef MCAL_PLATFORM_ARM
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        #define ISR_STATE_MASK     ((uint32)0x00000002UL)   /**< @brief DAIF bit I and F */
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        #define ISR_STATE_MASK     ((uint32)0x00000080UL)   /**< @brief CPSR bit I */
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+            #define ISR_STATE_MASK     ((uint32)0x000000FFUL)   /**< @brief BASEPRI[7:0] mask */
+        #else
+            #define ISR_STATE_MASK     ((uint32)0x00000001UL)   /**< @brief PRIMASK bit 0 */
+        #endif
+    #endif 
+#else
+    #ifdef MCAL_PLATFORM_S12
+        #define ISR_STATE_MASK     ((uint32)0x00000010UL)   /**< @brief I bit of CCR */
+    #else
+        #define ISR_STATE_MASK     ((uint32)0x00008000UL)   /**< @brief EE bit of MSR */
+    #endif
+#endif
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+#ifdef MCAL_PLATFORM_ARM
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)3)
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
+    #else
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
+    #endif    
+#else
+    #ifdef MCAL_PLATFORM_S12
+        #define ISR_ON(msr)            (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
+    #else
+        #define ISR_ON(msr)            (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
+    #endif
+#endif
+
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+#define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
+#include "Rte_MemMap.h"
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
+static volatile uint32 msr_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
+static volatile uint32 reentry_guard_SPI_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
+
+#define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
+#include "Rte_MemMap.h"
+/*==================================================================================================
+*                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifndef _COSMIC_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Spi_schm_read_msr(void); 
+#endif /*ifndef _COSMIC_C_S32K1XX_*/
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+#if (defined(_GREENHILLS_C_S32K1XX_) || defined(_CODEWARRIOR_C_S32K1XX_))
+/*================================================================================================*/
+/** 
+* @brief   This macro returns the MSR register value (32 bits). 
+* @details This macro function implementation returns the MSR register value in r3 (32 bits). 
+*     
+* @pre  None
+* @post None
+* 
+*/
+#ifdef MCAL_PLATFORM_ARM
+#if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+    mrs x0, S3_3_c4_c2_1
+}
+#elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+    mrs r0, CPSR
+}
+#else
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+    mrs r0, BASEPRI
+#else
+    mrs r0, PRIMASK
+#endif
+}
+#endif
+#else
+#ifdef MCAL_PLATFORM_S12
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+   tfr ccr, d6
+}
+#else
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+    mfmsr r3
+}
+#endif
+#endif
+#endif /*#ifdef GHS||CW*/
+
+#ifdef _DIABDATA_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+#ifdef MCAL_PLATFORM_ARM
+uint32 Spi_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#else
+ASM_KEYWORD uint32 Spi_schm_read_msr(void)
+{
+    mfmsr r3
+}    
+#endif  /* MCAL_PLATFORM_ARM */
+
+#endif   /* _DIABDATA_C_S32K1XX_*/
+
+#ifdef _COSMIC_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+
+#ifdef MCAL_PLATFORM_S12
+    #define Spi_schm_read_msr()  ASM_KEYWORD("tfr ccr, d6")
+#else
+    #define Spi_schm_read_msr() ASM_KEYWORD("mfmsr r3")
+#endif
+
+#endif  /*Cosmic compiler only*/
+
+
+#ifdef _HITECH_C_S32K1XX_
+/*================================================================================================*/
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Spi_schm_read_msr(void)
+{
+    uint32 result;
+    __asm volatile("mfmsr %0" : "=r" (result) :);
+    return result;
+}
+
+#endif  /*HighTec compiler only*/
+ /*================================================================================================*/
+#ifdef _LINARO_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Spi_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#endif   /* _LINARO_C_S32K1XX_*/
+/*================================================================================================*/
+
+#ifdef _ARM_DS5_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Spi_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+    #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
+        __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
+    #elif  (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
+        __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
+    #else
+        #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+        #else
+        __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+        #endif
+    #endif
+    return (uint32)reg_tmp;
+}
+#endif   /* _ARM_DS5_C_S32K1XX_ */
+
+#ifdef _IAR_C_S32K1XX_
+/** 
+* @brief   This function returns the MSR register value (32 bits). 
+* @details This function returns the MSR register value (32 bits). 
+*     
+* @param[in]     void        No input parameters
+* @return        uint32 msr  This function returns the MSR register value (32 bits). 
+* 
+* @pre  None
+* @post None
+* 
+*/
+uint32 Spi_schm_read_msr(void)
+{
+    register uint32 reg_tmp;
+
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+   __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
+#else
+   __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
+#endif
+
+    return (uint32)reg_tmp;
+}
+#endif   /* _IAR_C_S32K1XX_ */
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+/*==================================================================================================
+*                                        GLOBAL FUNCTIONS
+==================================================================================================*/
+#define RTE_START_SEC_CODE
+#include "Rte_MemMap.h"
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_00[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_00[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_01[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_01[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_02[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_02[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_03[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_03[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_04[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_04[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_05[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_05[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_06[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_06[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_07[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_07[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_08(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_08[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_08[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_08(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_09(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_09[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_09[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_09(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_10(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_10[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_10[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_10(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_11(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_11[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_11[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_11(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_12(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_12[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_12[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_12(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_13(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_13[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_13[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_13(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_14(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_14[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_14[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_14(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_15(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_15[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_15[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_15(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_16(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_16[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_16[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_16(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_17(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_17[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_17[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_17(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+void SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_18(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    if(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId])
+    {
+#if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
+        msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = OsIf_Trusted_Call_Return(Spi_schm_read_msr);
+#else
+        msr_SPI_EXCLUSIVE_AREA_18[u32CoreId] = Spi_schm_read_msr();  /*read MSR (to store interrupts state)*/
+#endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
+        if (ISR_ON(msr_SPI_EXCLUSIVE_AREA_18[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
+        {
+            OsIf_SuspendAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+            ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+        }
+    }
+    reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]++;
+}
+
+void SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_18(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]--;
+    if ((ISR_ON(msr_SPI_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]))         /*if interrupts were enabled*/
+    {
+        OsIf_ResumeAllInterrupts();
+#ifdef _ARM_DS5_C_S32K1XX_
+        ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
+#endif
+    }
+}
+
+
+#ifdef MCAL_TESTING_ENVIRONMENT
+/** 
+@brief   This function checks that all entered exclusive areas were also exited. 
+@details This function checks that all entered exclusive areas were also exited. The check
+         is done by verifying that all reentry_guard_* static variables are back to the
+         zero value.
+    
+@param[in]     void       No input parameters
+@return        void       This function does not return a value. Test asserts are used instead. 
+
+@pre  None
+@post None
+
+@remarks Covers 
+@remarks Implements 
+*/
+void SchM_Check_spi(void)
+{
+    uint32 u32CoreId = (uint32)OsIf_GetCoreID();
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_00 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_01 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_02 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_03 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_04 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_05 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_06 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_07 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_08 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_09 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_10 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_11 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_12 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_13 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_14 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_15 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_16 for the next test in the suite*/
+    
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_17 for the next test in the suite*/
+
+    EU_ASSERT(0UL == reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId]);
+    reentry_guard_SPI_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_SPI_EXCLUSIVE_AREA_18 for the next test in the suite*/
+
+
+}
+#endif /*MCAL_TESTING_ENVIRONMENT*/
+
+#define RTE_STOP_SEC_CODE
+#include "Rte_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

RTD/src/Spi.c

@@ -0,0 +1,3331 @@
+/**
+*   @file    Spi.c
+*   @implements Spi.c_Artifact
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Implements the AUTOSAR SPI driver functionality.
+*   @details Implements the AUTOSAR SPI driver. All the API functions are described by AUTOSAR
+*
+*   @addtogroup SPI_DRIVER Spi Driver
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+*/
+#include "Spi.h"
+#include "Spi_IPW.h"
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+    #include "Dem.h"
+#endif
+#include "Det.h"
+#include "SchM_Spi.h"
+
+/*
+*                                       SOURCE FILE VERSION INFORMATION
+*/
+#define SPI_MODULE_ID_C                     83
+#define SPI_VENDOR_ID_C                     43
+#define SPI_AR_RELEASE_MAJOR_VERSION_C      4
+#define SPI_AR_RELEASE_MINOR_VERSION_C      4
+#define SPI_AR_RELEASE_REVISION_VERSION_C   0
+#define SPI_SW_MAJOR_VERSION_C              1
+#define SPI_SW_MINOR_VERSION_C              0
+#define SPI_SW_PATCH_VERSION_C              0
+
+/*
+*                                     FILE VERSION CHECKS
+*/
+/* Check if this file and Spi.h are of the same vendor */
+#if (SPI_VENDOR_ID_C != SPI_VENDOR_ID)
+    #error "Spi.c and Spi.h have different vendor ids"
+#endif
+/* Check if current file and Spi header file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION_C != SPI_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_AR_RELEASE_MINOR_VERSION_C != SPI_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_AR_RELEASE_REVISION_VERSION_C != SPI_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi.c and Spi.h are different"
+#endif
+  /* Check if current file and Spi header file are of the same Software version */
+#if ((SPI_SW_MAJOR_VERSION_C != SPI_SW_MAJOR_VERSION) || \
+     (SPI_SW_MINOR_VERSION_C != SPI_SW_MINOR_VERSION) || \
+     (SPI_SW_PATCH_VERSION_C != SPI_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi.c and Spi.h are different"
+#endif
+
+/* Check if this header file and Spi_IPW_Types.h are of the same vendor */
+#if (SPI_VENDOR_ID_C != SPI_IPW_VENDOR_ID)
+    #error "Spi.c and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if current file and Spi_IPW header file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION_C != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_AR_RELEASE_MINOR_VERSION_C != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_AR_RELEASE_REVISION_VERSION_C != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi.c and Spi_IPW.h are different"
+#endif
+  /* Check if current file and Spi_IPW header file are of the same Software version */
+#if ((SPI_SW_MAJOR_VERSION_C != SPI_IPW_SW_MAJOR_VERSION) || \
+     (SPI_SW_MINOR_VERSION_C != SPI_IPW_SW_MINOR_VERSION) || \
+     (SPI_SW_PATCH_VERSION_C != SPI_IPW_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi.c and Spi_IPW.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Det.h header file are of the same Software version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION_C != DET_AR_RELEASE_MAJOR_VERSION) || \
+       (SPI_AR_RELEASE_MINOR_VERSION_C != DET_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi.h and Det.h are different"
+    #endif
+  
+    #if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+      /* Check if the current file and Dem.h header file are of the same version */
+      #if ((SPI_AR_RELEASE_MAJOR_VERSION_C != DEM_AR_RELEASE_MAJOR_VERSION) || \
+           (SPI_AR_RELEASE_MINOR_VERSION_C != DEM_AR_RELEASE_MINOR_VERSION))
+      #error "AutoSar Version Numbers of Spi.c and Dem.h are different"
+      #endif
+    #endif
+
+    /* Check if the current file and SchM_Spi.h header file are of the same version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION_C != SCHM_SPI_AR_RELEASE_MAJOR_VERSION) || \
+         (SPI_AR_RELEASE_MINOR_VERSION_C != SCHM_SPI_AR_RELEASE_MINOR_VERSION) \
+        )
+        #error "AutoSar Version Numbers of Spi.c and SchM_Spi.h are different"
+    #endif
+#endif
+
+/*
+*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+*/
+/**
+* @brief   This structure holds the HWUnit scheduling queue.
+* @details For async transmissions, this structure holds the HWUnit scheduling queue .
+*          For sync transmissions, only HWUnit Status is managed.
+*
+*/
+
+/*
+*                                       LOCAL MACROS
+*/
+
+/*
+*                                      LOCAL CONSTANTS
+*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief  Values used to denote NULL indexes.
+*/
+#define SPI_JOB_NULL            ((Spi_JobType)(-1))
+#endif /* ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)) */
+
+/*
+*                                      LOCAL VARIABLES
+*/
+
+#define   SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+/**
+* @brief Array of HW units queues.
+*/
+Spi_HWUnitQueue Spi_aSpiHWUnitQueueArray[SPI_MAX_HWUNIT];
+
+#define   SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+
+/*
+*                                      GLOBAL CONSTANTS
+*/
+
+
+/*
+*                                      GLOBAL VARIABLES
+*/
+#if (SPI_PRECOMPILE_SUPPORT == STD_ON)
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+
+#include "Spi_MemMap.h"
+
+extern const Spi_ConfigType * const Spi_PBCfgVariantPredefined[SPI_MAX_PARTITIONS];
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+#endif /* (SPI_PRECOMPILE_SUPPORT == STD_ON) */
+
+#define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+const Spi_ConfigType *Spi_apxSpiConfigPtr[SPI_MAX_PARTITIONS];
+
+/**
+* @brief Spi State.
+*/
+static Spi_SequenceStateType Spi_axSpiSequenceState[SPI_MAX_SEQUENCE];
+
+Spi_JobStateType Spi_axSpiJobState[SPI_MAX_JOB];
+
+Spi_ChannelStateType Spi_axSpiChannelState[SPI_MAX_CHANNEL];
+
+#if (SPI_MAX_HWUNIT > 32u)
+    #error "Too many HW Units in configuration (max 32 units allowed)"
+#endif
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#define   SPI_START_SEC_VAR_CLEARED_32
+#include "Spi_MemMap.h"
+
+/**
+* @note Array of used HW units per sequence:
+*         The element corresponding to a given sequence will have asserted the bits
+*         corresponding to the used HW units.
+*/
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+static uint32 Spi_au32SpiSeqUsedHWUnits[SPI_MAX_SEQUENCE];
+#endif
+
+/**
+* @brief Spi Sync Transmit Running HWUnits Status.
+*/
+static volatile uint32 Spi_au32SpiBusySyncHWUnitsStatus[SPI_MAX_HWUNIT];
+
+#define   SPI_STOP_SEC_VAR_CLEARED_32
+#include "Spi_MemMap.h"
+
+
+/*
+*                                  LOCAL FUNCTION PROTOTYPES
+*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static inline void Spi_ScheduleJob
+    (
+        Spi_HWUnitQueue* HWUnitQueue,
+        Spi_JobType Job,
+        const Spi_JobConfigType *JobConfig
+    );
+#endif
+
+#if (SPI_LEVEL_DELIVERED == LEVEL2)
+static inline Spi_StatusType Spi_GetAsyncStatus(void);
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static Std_ReturnType Spi_LockJobs
+    (
+        Spi_SequenceType SequenceId,
+        const Spi_SequenceConfigType *Sequence
+    );
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static inline void Spi_UnlockRemainingJobs
+    (
+        Spi_JobType RemainingJobs,
+        const Spi_SequenceConfigType *Sequence
+    );
+#endif
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static void Spi_ScheduleNextJob
+  (
+      Spi_HWUnitQueue *HWUnitQueue,
+      uint32 SpiCoreID
+   );
+#endif
+static inline Std_ReturnType Spi_CheckInit
+    ( 
+        const Spi_ConfigType *ConfigPtr,
+        uint32 SpiCoreID
+    );
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )  
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+static Std_ReturnType Spi_SynctransmitCheckChannelsIsValid
+    (
+        uint32 SpiCoreID,
+        const Spi_JobConfigType *JobConfig
+    );
+#endif
+#endif
+#endif
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+static Std_ReturnType Spi_SynctransmitCheckJobsIsValid
+    (
+        const Spi_SequenceConfigType *SequenceConfig,
+        uint32 SpiCoreID
+    );
+#endif /* #if (SPI_DEV_ERROR_DETECT == STD_ON)*/
+    
+static Std_ReturnType Spi_SyncJobsTranfer
+    (
+        const Spi_SequenceConfigType *SequenceConfig,
+        uint32 SpiCoreID
+    );
+#endif /* ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )*/
+
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+static Std_ReturnType Spi_ChannelCheckValidity
+    (
+        const Spi_ChannelType Channel,
+        const uint8 FunctionId
+    );
+
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+static Std_ReturnType Spi_SetupEbCheckLength
+    (
+        const Spi_ChannelConfigType *ChannelConfig,
+        Spi_NumberOfDataType Length
+    );
+#endif
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+static Std_ReturnType Spi_AsyncTransmitCheckDemReport
+    (
+        uint32 SpiCoreID,
+        Spi_SequenceType Sequence
+    );
+#endif
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+static Std_ReturnType Spi_AsyncTransmitCheckValidityOfChannels
+    (
+        uint32 SpiCoreID,
+        const Spi_JobConfigType *JobConfig
+    );
+#endif
+#endif
+#endif
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+static Std_ReturnType Spi_InitCheckDemError
+    (
+        uint32 SpiCoreID,
+        const Spi_ConfigType *ConfigPtr
+    );
+#endif
+
+static void Spi_InitChannelsJobsSeqsState
+    (
+        uint32 SpiCoreID
+    );
+    
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static void Spi_InitJobsList
+    (
+        uint32 HWUnit
+    );
+#endif
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+static Std_ReturnType Spi_SyncTransmitCheckDemReport
+    (
+        uint32 SpiCoreID,
+        Spi_SequenceType Sequence
+    );
+#endif
+#endif
+
+static Spi_StatusType Spi_GetStatusAsyncCheckHwBusy
+    (
+        uint32 SpiCoreID
+    );
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))    
+static Std_ReturnType Spi_LockJobsProcess
+    (
+        Spi_SequenceType SequenceId,
+        const Spi_SequenceConfigType *Sequence,
+        Spi_JobType JobCount
+    );
+#endif
+
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+static inline void Spi_DemReportStatus
+    (
+        uint32 SpiCoreID,
+        Dem_EventStatusType EventStatus
+    );
+#endif
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    #if ( ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON)) || (SPI_HW_STATUS_API == STD_ON) )
+static Std_ReturnType Spi_HWUnitCheckValidity
+    (
+        const Spi_HWUnitType HWUnit,
+        const uint8 FunctionId
+    );
+    #endif /* ( ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON)) || (SPI_HW_STATUS_API == STD_ON) ) */
+#endif /* (SPI_DEV_ERROR_DETECT == STD_ON) */
+
+/*
+*                                       LOCAL FUNCTIONS
+*/
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    #if ( ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON)) || (SPI_HW_STATUS_API == STD_ON) )
+/**
+* @brief   This function check valid of HWUnit input
+*
+* @param[in]     HWUnit         The hardware Peripheral
+* @param[in]     FunctionId     The Function Id to report error
+* @param[out]    Std_ReturnType
+* @retval E_OK      No error was reported
+* @retval E_NOT_OK  Error was reported
+*
+*/
+static Std_ReturnType Spi_HWUnitCheckValidity
+    (
+        const Spi_HWUnitType HWUnit,
+        const uint8 FunctionId
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType) E_NOT_OK;
+    uint32 SpiCoreID = Spi_GetCoreID;
+
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_UNINIT);
+
+    }
+    else if (HWUnit >= SPI_MAX_HWUNIT)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_UNIT);
+    }
+    /* Check core has assigned for sequence */
+    else if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig)
+    {
+        /* Call Det_ReportError for wrong core */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_CONFIG);
+    }
+    else if (SpiCoreID != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+    {
+        /* Call Det_ReportError for wrong core */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_CONFIG);
+    }
+    else
+    {
+        Status = (Std_ReturnType)E_OK;
+    }
+
+    return Status;
+}
+    #endif /* ( ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON)) || (SPI_HW_STATUS_API == STD_ON) ) */
+#endif /* (SPI_DEV_ERROR_DETECT == STD_ON) */
+
+/**
+* @brief   This function report production error SPI_E_HARDWARE_ERROR to DEM.
+*
+* @param[in]     ReportStatus       Specifies the Event status
+* @param[out]    void
+*
+*/
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+static inline void Spi_DemReportStatus
+    (
+        uint32 SpiCoreID,
+        Dem_EventStatusType EventStatus
+    )
+{
+    /* Call Dem_SetEventStatus. */
+    if ((uint32)STD_ON == Spi_apxSpiConfigPtr[SpiCoreID]->SpiErrorHardwareCfg.state)
+    {
+        (void)Dem_SetEventStatus((Dem_EventIdType)Spi_apxSpiConfigPtr[SpiCoreID]->SpiErrorHardwareCfg.id, EventStatus);
+    }
+    else
+    {
+        /* Do nothing */
+    }
+}
+#endif
+
+/**
+* @brief   This function checks parameters for initialization of SPI driver.
+* @details This function checks parameters for initialization of SPI driver.
+*
+* @param[in]     ConfigPtr       Specifies the pointer to the configuration set
+* @param[out]    CheckStatus      Specifies status of checking
+*               - E_OK: The parameters are valid
+*               - E_NOT_OK: The parameters are invalid
+*
+*/
+static inline Std_ReturnType Spi_CheckInit
+    ( 
+        const Spi_ConfigType *ConfigPtr,
+        uint32 SpiCoreID
+    )
+{
+    Std_ReturnType CheckStatus = (Std_ReturnType)E_OK;
+#if (SPI_PRECOMPILE_SUPPORT == STD_OFF)
+    uint32 Channel;
+    uint32 Job;
+    uint32 Sequence;
+#endif
+
+#if (SPI_PRECOMPILE_SUPPORT == STD_OFF)
+    /* Configuration sizes must be checked for Post Build & Link Time configurations */
+    Channel  = (uint32)(ConfigPtr->SpiMaxChannel);
+    Job      = (uint32)(ConfigPtr->SpiMaxJob);
+    Sequence = (uint32)(ConfigPtr->SpiMaxSequence);
+
+    if ((Channel >= SPI_MAX_CHANNEL) || (Job >= SPI_MAX_JOB) || (Sequence >= SPI_MAX_SEQUENCE))
+    {
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_CONFIG_OUT_OF_RANGE);
+#endif
+    }
+    if (SpiCoreID != ConfigPtr->SpiCoreUse)
+    {
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_PARAM_CONFIG);
+#endif
+    }
+#else /* (SPI_CONFIG_VARIANT == SPI_VARIANT_PRECOMPILE) */
+    (void)ConfigPtr;
+    if ( NULL_PTR == Spi_PBCfgVariantPredefined[SpiCoreID] )
+    {
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_INVALID_POINTER);
+#endif
+    }
+#endif /* (SPI_PRECOMPILE_SUPPORT == STD_OFF) */
+
+    return CheckStatus;
+}
+
+/**
+* @brief   This function returns the status of the SPI driver related to async HW Units.
+* @details Return SPI_BUSY if at least one async HW unit is busy.
+*
+* @return Spi_StatusType
+* @retval SPI_UNINIT  The driver is un-initialized  ->TBD pare ca nu se poate indeplini aceast status
+* @retval SPI_IDLE    The driver has no pending transfers
+* @retval SPI_BUSY    The driver is busy
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL2.
+*/
+/*=====*/
+#if (SPI_LEVEL_DELIVERED == LEVEL2)
+static inline Spi_StatusType Spi_GetAsyncStatus(void)
+{
+    Spi_StatusType StatusFlag = SPI_IDLE;
+    Spi_HWUnitType HWUnit;
+    uint32 SpiCoreID;
+
+    SpiCoreID = Spi_GetCoreID;
+
+    if(NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        for (HWUnit = 0u; HWUnit < (Spi_HWUnitType)SPI_MAX_HWUNIT; HWUnit++)
+        {
+            if ((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+                (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+               )
+            {
+                if ((SPI_BUSY == Spi_aSpiHWUnitQueueArray[HWUnit].Status) &&
+                    (SPI_PHYUNIT_ASYNC_U32 == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IsSync))
+                {
+                    StatusFlag = SPI_BUSY;
+                    break;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    return StatusFlag;
+}
+#endif /* (SPI_LEVEL_DELIVERED == LEVEL2) */
+
+/*=====*/
+/**
+* @brief   This function is called in order to mark the jobs of a sequence as ready to be transmitted.
+* @details For each job in sequence, the function checks if it is already
+*          linked to another pending sequence.
+*          If at least one job is already linked, the function returns E_NOT_OK.
+*          Elsewhere, all jobs in sequence are locked (linked to the current
+*          sequence)
+*
+* @param[in]      Sequence        The sequence ID.
+* @param[in]      Sequence       The sequence configuration.
+*
+* @return Std_ReturnType
+* @retval E_OK       The given sequence does not share its jobs with some
+*                    other sequences, and all its jobs were successfully
+*                    locked.
+* @retval E_NOT_OK  The given sequence shares its jobs with some other
+*                   sequences. No lock performed for its jobs.
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static Std_ReturnType Spi_LockJobs
+    (
+        Spi_SequenceType SequenceId,
+        const Spi_SequenceConfigType *Sequence
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_JobType JobCount = Sequence->NumJobs;
+    const Spi_JobType *Jobs = Sequence->JobIndexList;
+    Spi_JobStateType *JobState;
+
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_03();
+    /* Use an optimized implementation for one job sequences */
+    if (1u == JobCount)
+    {
+        JobState = &Spi_axSpiJobState[*Jobs];
+        if (NULL_PTR == JobState->AsyncCrtSequenceState)
+        {
+            /* Job not yet linked => link it to the current sequence */
+            JobState->AsyncCrtSequenceState = &Spi_axSpiSequenceState[SequenceId];
+        }
+        else
+        {
+            /* The job is already locked by a pending sequence */
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    else
+    {
+        Status = Spi_LockJobsProcess(SequenceId, Sequence, JobCount);
+    }
+    SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_03();
+    
+    return Status;
+}
+#endif /* ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)) */
+
+/*=====*/
+/**
+* @brief   This function is called to release the jobs at the end of an async sequence transmission.
+* @details Mark the linked sequence for all jobs as NULL_PTR.
+*
+* @param[in]      RemainingJobs    The starting job
+* @param[in]      Sequence        The sequence configuration
+*
+* @pre  Pre-compile parameter SPI_CANCEL_API shall be STD_ON.
+*
+*/
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static inline void Spi_UnlockRemainingJobs
+    (
+        Spi_JobType RemainingJobs,
+        const Spi_SequenceConfigType *Sequence
+    )
+{
+    Spi_JobType NumJobsInSeq = Sequence->NumJobs;
+    Spi_JobType JobIdx;
+
+    for (JobIdx = NumJobsInSeq-RemainingJobs; JobIdx < NumJobsInSeq; JobIdx++)
+    {
+        Spi_axSpiJobState[Sequence->JobIndexList[JobIdx]].AsyncCrtSequenceState = NULL_PTR;
+    }
+}
+#endif /* (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) */
+
+/*=====*/
+/**
+* @brief   This function will schedule a job for a given HW unit.
+* @details If the HWUnit is not busy, the transfer is started and the HW unit is
+*          marked as busy.
+*          If the HWUnit is not busy (another job is in progress), the new job is
+*          scheduled in a waiting job list, according to its priority.
+*
+* @param[in]      HWUnitQueue     HW Unit to be used by the job
+* @param[in]      Job             ID of the scheduled job
+* @param[in]      JobConfig      Configuration of the scheduled job
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static inline void Spi_ScheduleJob
+    (
+        Spi_HWUnitQueue *HWUnitQueue,
+        Spi_JobType Job,
+        const Spi_JobConfigType *JobConfig
+    )
+{
+    sint8 Priority;
+    Spi_JobType *pJobListTail;
+
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_00();
+    if (SPI_IDLE == HWUnitQueue->Status)
+    {
+        /* idle unit => the job can be started */
+        HWUnitQueue->Status = SPI_BUSY;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00();
+
+        /* mark the job as pending */
+        Spi_axSpiJobState[Job].Result = SPI_JOB_PENDING;
+        HWUnitQueue->Channel = 0;
+        HWUnitQueue->Job = Job;
+        Spi_Ipw_JobTransfer(JobConfig);
+    }
+    else
+    {
+        /* add the job to the scheduling corresponding queue */
+
+        /* retrieve the tail of the scheduling queue for the job priority */
+        Priority = JobConfig->Priority;
+        pJobListTail = &HWUnitQueue->ScheduledJobsListTail[Priority];
+
+        if (SPI_JOB_NULL == *pJobListTail)
+        {
+            /* the list is empty => set also the head of the list */
+            HWUnitQueue->ScheduledJobsListHead[Priority] = Job;
+        }
+        else
+        {
+            /* add the item at the end of the list */
+            Spi_axSpiJobState[*pJobListTail].AsyncNextJob = Job;
+        }
+
+        /* set the new tail of the list */
+        *pJobListTail = Job;
+
+        /* the new item will be the last element in the list */
+        Spi_axSpiJobState[Job].AsyncNextJob = SPI_JOB_NULL;
+
+        if (HWUnitQueue->MaxScheduledPriority < Priority)
+        {
+            HWUnitQueue->MaxScheduledPriority = Priority;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_00();
+    }
+}
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) ) */
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+/**
+* @brief   This function will check validation of channels in a jobs in Synchronous mode.
+* @details This function will check validation of channels in a jobs in Synchronous mode.
+*
+* @param[in]      SequenceConfig     The sequence configuration
+* @param[in]      SpiCoreID         ID of Core
+*
+* @retval E_OK      No invalid configuration was found.
+* @retval E_NOT_OK  The HWUnit which are assigning to the job is Async mode Or the buffer of channel is EB so Lenght is 0.
+*
+* @pre  This function will be called by Spi_Synctransmit()
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL0 or LEVEL2
+*/
+static Std_ReturnType Spi_SynctransmitCheckChannelsIsValid
+    (
+        uint32 SpiCoreID,
+        const Spi_JobConfigType *JobConfig
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_ChannelType ChannelID;
+    Spi_ChannelType ChannelIndex;
+    Spi_ChannelType NumChannelsInJob = JobConfig->NumChannels;
+    
+    for(ChannelIndex=(Spi_ChannelType)0;ChannelIndex < NumChannelsInJob; ChannelIndex++)
+    {
+        ChannelID = JobConfig->ChannelIndexList[ChannelIndex];
+        if (EB == Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[ChannelID].ChannelCfg->BufferType)
+        {
+            /* Channel length is 0 for unconfigured ext. buffers */
+            if (0U == Spi_axSpiChannelState[ChannelID].Length)
+            {
+                /* An used EB not initialized  */
+                (void)Det_ReportError((uint16) SPI_MODULE_ID, (uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_PARAM_EB_UNIT);
+                Status = (Std_ReturnType)E_NOT_OK;
+                break;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+    return Status;
+}
+#endif
+#endif
+#endif
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   This function will check validation of jobs in a sequence in Synchronous mode.
+* @details This function will check validation of jobs in a sequence in Synchronous mode.
+*
+* @param[in]      SequenceConfig     The sequence configuration
+* @param[in]      SpiCoreID         ID of Core
+*
+* @retval E_OK      No invalid configuration was found.
+* @retval E_NOT_OK  The HWUnit which are assigning to the job is Async mode Or the buffer of channel is EB so Lenght is 0.
+*
+* @pre  This function will be called by Spi_Synctransmit()
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL0 or LEVEL2
+*/
+static Std_ReturnType Spi_SynctransmitCheckJobsIsValid
+    (
+        const Spi_SequenceConfigType *SequenceConfig,
+        uint32 SpiCoreID
+    )
+{
+    Spi_JobType NumJobsInSequence;
+    Spi_JobType Job;
+    Spi_JobType JobIndex;
+    Spi_HWUnitType HWUnit;
+    const Spi_JobConfigType *JobConfig;
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    uint32 UnitIsSync;
+    /* Get the number of jobs in the sequence */
+    NumJobsInSequence = SequenceConfig->NumJobs;
+    for (JobIndex = 0u; JobIndex < NumJobsInSequence; JobIndex++)
+    {
+        /* Get the job id */
+        Job = SequenceConfig->JobIndexList[JobIndex];
+        JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg;
+        /* Logical Spi HWUnit */
+        HWUnit = JobConfig->HWUnit;
+        UnitIsSync = Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IsSync;
+        if ((uint32)(SPI_PHYUNIT_ASYNC_U32) == (UnitIsSync))
+        {
+            /* HwUnit is not prearranged for dedicated Synchronous
+               transmission */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_PARAM_UNIT);
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+        if ((Std_ReturnType)E_OK == Status)
+        {
+            /* Check if all EBs have been setup */
+            Status = Spi_SynctransmitCheckChannelsIsValid(SpiCoreID, JobConfig);
+        }
+        else
+        {
+            /* Do nothing */
+        }
+#endif /* ((SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) ) */
+        if ((Std_ReturnType)E_NOT_OK == Status)
+        {
+            /* break */
+            break;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+    return Status;
+}
+
+#endif /*#if (SPI_DEV_ERROR_DETECT == STD_ON)*/
+/**
+* @brief   This function transmit Jobs in a sequence by Synctransmit mode.
+* @details This function transmit Jobs in a sequence by Synctransmit mode.
+*
+* @param[in]      SequenceConfig     The sequence configuration.
+* @param[in]      SpiCoreID         ID of Core
+* @return Std_ReturnType
+* @retval E_OK      Transmission command has been completed successfully
+* @retval E_NOT_OK  Transmission command has not been accepted
+*
+* @pre  This function will be called by Spi_Synctransmit()
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL0 or LEVEL2
+*
+*/
+static Std_ReturnType Spi_SyncJobsTranfer
+    (
+        const Spi_SequenceConfigType *SequenceConfig,
+        uint32 SpiCoreID
+    )
+{
+    Spi_JobType JobsCount;
+    const Spi_JobType *JobIndexList;
+    Spi_JobType Job;
+    Spi_JobStateType *JobState;
+    const Spi_JobConfigType *JobConfig;
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    
+    /* Get the number of jobs in the sequence */
+    JobsCount = SequenceConfig->NumJobs;
+    JobIndexList = SequenceConfig->JobIndexList;
+    while (0u < JobsCount)
+    {
+        /* Get the job id */
+        Job = *JobIndexList;
+        /* Set the job status as pending */
+        JobState = &Spi_axSpiJobState[Job];
+        JobState->Result = SPI_JOB_PENDING;
+        JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg;
+        
+        /* start job notification to assert the non-cs pin,
+        when non-cs pin is used as chipselect*/
+        if (NULL_PTR != JobConfig->StartNotification)
+        {
+            JobConfig->StartNotification();
+        }
+        else
+        {
+            /* Do nothing */
+        }
+        /* Mark HWUnit as busy */
+        Spi_aSpiHWUnitQueueArray[JobConfig->HWUnit].Status = SPI_BUSY;
+        
+        Status = Spi_Ipw_SyncTransmit(JobConfig, SpiCoreID);
+        
+        /* release HWUnit */
+        Spi_aSpiHWUnitQueueArray[JobConfig->HWUnit].Status = SPI_IDLE;
+        
+        if ((Std_ReturnType)E_OK == Status)
+        {
+            /* Job is done set the status as OK */
+            JobState->Result = SPI_JOB_OK;
+            /* Perform job EndNotification (if there is one) */
+            if (NULL_PTR != JobConfig->EndNotification)
+            {
+                JobConfig->EndNotification();
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+        else
+        {
+            /* transmission failed */
+            /* set the remaining job status (including the current one) as FAILED */
+            do
+            {
+                /* Set the job status as FAILED */
+                Spi_axSpiJobState[*JobIndexList].Result = SPI_JOB_FAILED;
+                /* Update pointer position for JobConfig */
+                JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[*JobIndexList].JobCfg;
+                /* Perform job EndNotification (if there is one) */
+                if (NULL_PTR != JobConfig->EndNotification)
+                {
+                    JobConfig->EndNotification();
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+                JobIndexList++;
+                JobsCount--;
+            } while (0u < JobsCount);
+            JobsCount = 1u;  /* needed to end correctly the outer loop */
+        }
+        /* iterate to next job in sequence */
+        JobIndexList++;
+        JobsCount--;
+    } /* while (JobsCount > 0u) */
+    return Status;
+}
+#endif /* ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )*/
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   This function check valid for input Channel.
+* @details This function check valid for input Channel.
+*
+* @param[in]      Channel              ID channel
+* @param[in]      FunctionId           Function Id to report error
+* @return Std_ReturnType
+* @retval E_OK      No error was reported
+* @retval E_NOT_OK  Error was reported
+*
+*
+*/
+static Std_ReturnType Spi_ChannelCheckValidity
+    (
+        const Spi_ChannelType Channel,
+        const uint8 FunctionId
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    uint32 SpiCoreID = Spi_GetCoreID;
+
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_UNINIT);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    /* Channel ID - Valid channels range is from 0 to SpiMaxChannel*/
+    else if (Channel > Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxChannel)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_CHANNEL);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    /* Check core has assigned for this channel */
+    else if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_CONFIG);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (SpiCoreID != Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg->SpiCoreUse)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, FunctionId, SPI_E_PARAM_CONFIG);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    return Status;
+}
+#endif /* (SPI_DEV_ERROR_DETECT == STD_ON) */
+
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   This function check valid for input parameters Length and CoreId.
+* @details This function check valid for input parameters Length and CoreId.
+*
+* @param[in]      SpiCoreID         ID of Core
+* @param[in]      Channel              ID channel
+* @param[in]      Length               Number of bytes 
+* @return Std_ReturnType
+* @retval E_OK      No error was reported
+* @retval E_NOT_OK  Error was reported
+*
+*
+*/
+
+/**
+* @brief   This function transmit Jobs in a sequence by Synctransmit mode.
+* @details This function transmit Jobs in a sequence by Synctransmit mode.
+*
+* @param[in]      ChannelConfig      Channel configuration
+* @param[in]      Length               Number of bytes 
+* @return none
+*
+*
+*/
+static Std_ReturnType Spi_SetupEbCheckLength
+    (
+        const Spi_ChannelConfigType *ChannelConfig,
+        Spi_NumberOfDataType Length
+    )
+{
+    Spi_NumberOfDataType SurplusLength;
+    Spi_NumberOfDataType LengthCheck = Length;
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    
+    if ((ChannelConfig->FrameSize > 8u) && (ChannelConfig->FrameSize < 17u))
+    {
+        SurplusLength = (Spi_NumberOfDataType)(LengthCheck%2u);
+        /* If number of bytes of channel is not divisible by 2 then the surplus bytes will be lost */
+        if (0u != SurplusLength)
+        {
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETUPEB_ID,SPI_E_PARAM_LENGTH);
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    else if ((ChannelConfig->FrameSize > 16u) && (ChannelConfig->FrameSize < 33u))
+    {
+        SurplusLength = (Spi_NumberOfDataType)(LengthCheck%4u);
+        /* If number of bytes of channel is not divisible by 4 then the surplus bytes will be lost */
+        if (0u != SurplusLength)
+        {
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETUPEB_ID,SPI_E_PARAM_LENGTH);
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    return Status;
+}
+#endif /*#if (SPI_DEV_ERROR_DETECT == STD_ON)*/
+#endif /* ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) ) */
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   This function check the initialization of driver and sequence ID is compatible.
+* @details This function check the initialization of driver and sequence ID is compatible.
+*
+* @param[in]      SpiCoreID      CoreID
+* @param[in]      Sequence          Sequence ID 
+* @return Std_ReturnType
+* @retval E_OK      No error was reported
+* @retval E_NOT_OK  Error was reported
+*
+*
+*/
+static Std_ReturnType Spi_AsyncTransmitCheckDemReport
+    (
+        uint32 SpiCoreID,
+        Spi_SequenceType Sequence
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_UNINIT);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    /* Sequence Valid Range */
+    else if (Sequence > (Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxSequence))
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_PARAM_SEQ);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+        /* Do nothing */
+    }
+    return Status;
+}
+#endif /*((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))*/
+#endif /*#if (SPI_DEV_ERROR_DETECT == STD_ON)*/
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+/**
+* @brief   Check channel with EB buffer.
+* @details Check channel with EB buffer.
+*
+* @param[in]      SpiCoreID      ID of core
+* @param[in]      JobConfig       Job configuration 
+* @return Std_ReturnType
+*
+*
+*/
+static Std_ReturnType Spi_AsyncTransmitCheckValidityOfChannels
+    (
+        uint32 SpiCoreID,
+        const Spi_JobConfigType *JobConfig        
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_ChannelType ChannelID;
+    Spi_ChannelType NumChannelsInJob;
+    Spi_ChannelType ChannelIndex;
+    
+    /* Check if all EBs have been setup */
+    NumChannelsInJob = JobConfig->NumChannels;
+    for(ChannelIndex=(Spi_ChannelType)0;ChannelIndex < NumChannelsInJob; ChannelIndex++)
+    {
+        ChannelID = JobConfig->ChannelIndexList[ChannelIndex];
+        if (EB == Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[ChannelID].ChannelCfg->BufferType)
+        {
+            /* Length is 0 for unconfigured ext. buffers */
+            if (0U == Spi_axSpiChannelState[ChannelID].Length)
+            {
+                /* An used EB not initialized  */
+                (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_PARAM_EB_UNIT);
+                Status = (Std_ReturnType)E_NOT_OK;
+                break;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+    return Status;
+}
+#endif /* #if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) ) */
+#endif /* (SPI_DEV_ERROR_DETECT == STD_OFF) */
+#endif /* #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)) */
+
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   Check Dem report error in Init function.
+* @details Check Dem report error in Init function.
+*
+* @param[in]      SpiCoreID      ID of core
+* @return Std_ReturnType
+*
+*
+*/
+static Std_ReturnType Spi_InitCheckDemError
+    (
+        uint32 SpiCoreID,
+        const Spi_ConfigType *ConfigPtr        
+    )
+{
+    Std_ReturnType CheckStatus = (Std_ReturnType)E_OK;
+    
+    if (NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_ALREADY_INITIALIZED);
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+    }
+    #if (SPI_PRECOMPILE_SUPPORT == STD_OFF)
+    else if (NULL_PTR == ConfigPtr)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_INIT_FAILED);
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+    }
+    #else /* (SPI_CONFIG_VARIANT == SPI_VARIANT_PRECOMPILE) */
+    else if (NULL_PTR != ConfigPtr)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_INIT_ID,SPI_E_INIT_FAILED);
+        CheckStatus = (Std_ReturnType)E_NOT_OK;
+    }
+    #endif /*(SPI_PRECOMPILE_SUPPORT == STD_OFF)*/
+    else 
+    {
+        /* Do nothing */
+    }
+    return CheckStatus;
+}
+#endif
+
+/**
+* @brief   This function initiate channels, jobs, sequences state.
+* @details This function initiate channels, jobs, sequences state.
+*
+* @param[in]      SpiCoreID      ID of core
+* @return None
+*
+*
+*/
+static void Spi_InitChannelsJobsSeqsState
+    (
+        uint32 SpiCoreID      
+    )
+{
+    uint32 Channel;
+    uint32 Job;
+    uint32 Sequence;
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_ON)
+    Spi_HWUnitType HWUnit;
+#endif
+#endif
+    const Spi_ChannelConfigType *ChannelConfig;
+    const Spi_JobConfigType *JobConfig;
+    const Spi_SequenceConfigType *SequenceConfig;
+    
+    for (Channel = 0u;
+        Channel <= (uint32)(Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxChannel);
+        Channel++)
+    {
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg;
+        /* Check which channel has assigned for current core */
+        if((NULL_PTR != ChannelConfig) && (SpiCoreID == ChannelConfig->SpiCoreUse))
+        {
+            /* Check if configured buffers are External (EB) */
+            if (EB == ChannelConfig->BufferType)
+            {
+                /* Initialize all buffers */
+                ChannelConfig->BufferDescriptor->BufferTX = NULL_PTR;
+                ChannelConfig->BufferDescriptor->BufferRX = NULL_PTR;
+    
+                /* Channel length is zero for unconfigured external buffers */
+                Spi_axSpiChannelState[Channel].Length = (Spi_NumberOfDataType) 0;
+            }
+            else
+            {
+                /* Setup channel length according to configuration */
+                Spi_axSpiChannelState[Channel].Length = ChannelConfig->Length;
+            }
+            Spi_axSpiChannelState[Channel].Flags = SPI_CHANNEL_FLAG_TX_DEFAULT_U8;
+        }
+    }
+    
+    /* initialize job results */
+    for (Job = 0u;
+        Job <= (uint32)( Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxJob);
+        Job++)
+    {
+        JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg;
+        if((NULL_PTR != JobConfig) && (SpiCoreID == JobConfig->SpiCoreUse))
+        {
+            Spi_axSpiJobState[Job].Result = SPI_JOB_OK;
+        #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+            /* mark the job as unlocked / not linked to a pending async sequence */
+            Spi_axSpiJobState[Job].AsyncCrtSequenceState = NULL_PTR;
+        #endif
+        }
+    }
+    
+    for (Sequence = 0u;
+        Sequence <= (uint32)(Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxSequence);
+        Sequence++)
+    {
+        SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+        if ((NULL_PTR != SequenceConfig) && (SpiCoreID == SequenceConfig->SpiCoreUse))
+        {
+            #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+            SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+            Spi_axSpiSequenceState[Sequence].Sequence = SequenceConfig;
+            #endif
+    
+            /* initialize sequence results */
+            Spi_axSpiSequenceState[Sequence].Result = SPI_SEQ_OK;
+    
+            #if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+            #if (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_ON)
+            SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+            /* initialize the map of used HWUnits per sequence */
+            Spi_au32SpiSeqUsedHWUnits[Sequence] = (uint32)0;
+    
+            for (Job = 0u; Job < SequenceConfig->NumJobs; Job++)
+            {
+                HWUnit = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[SequenceConfig->JobIndexList[Job]].JobCfg->HWUnit;
+    
+                Spi_au32SpiSeqUsedHWUnits[Sequence] |=
+                    (uint32)((uint32)1 << (HWUnit));
+            }
+            #else /* (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_OFF) */
+            /* SPI135: Spi_SyncTransmit() must fail if an other sync transmission
+                    is ongoing.*/
+            /* mark all HW units as used by the sync transmission, in order to
+                force the mutual exclusion of Spi_SyncTransmit() calls */
+    
+            Spi_au32SpiSeqUsedHWUnits[Sequence] = 0xFFFFFFFFU;
+            #endif /* (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_OFF) */
+            #endif /* ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) ) */
+    
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+}
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief   This function initiate the jobs list.
+* @details This function initiate the jobs list.
+*
+* @param[in]      HWUnit      The HW peripheral
+* @return None
+*
+*
+*/
+static void Spi_InitJobsList
+    (
+        uint32 HWUnit      
+    )
+{
+    sint8 Priority;
+    
+    /* initialize the Job lists => no scheduled job for the unit */
+    for (Priority = 0; Priority < SPI_JOB_PRIORITY_LEVELS_COUNT; Priority++)
+    {
+        Spi_aSpiHWUnitQueueArray[HWUnit].ScheduledJobsListHead[Priority] = SPI_JOB_NULL;
+        Spi_aSpiHWUnitQueueArray[HWUnit].ScheduledJobsListTail[Priority] = SPI_JOB_NULL;
+    }
+    
+    /* no scheduled job => MaxScheduledPriority is -1 */
+    Spi_aSpiHWUnitQueueArray[HWUnit].MaxScheduledPriority = -1;
+}
+#endif
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+/**
+* @brief   This function check the initialization of driver and sequence ID is compatible in Synchronous mode.
+* @details This function check the initialization of driver and sequence ID is compatible in Synchronous mode.
+*
+* @param[in]      SpiCoreID      CoreID
+* @param[in]      Sequence          Sequence ID 
+* @return Std_ReturnType
+* @retval E_OK      No error was reported
+* @retval E_NOT_OK  Error was reported
+*
+*
+*/
+static Std_ReturnType Spi_SyncTransmitCheckDemReport
+    (
+        uint32 SpiCoreID,
+        Spi_SequenceType Sequence
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0, SPI_SYNCTRANSMIT_ID,SPI_E_UNINIT);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    /* Sequence Valid Range */
+    else if (Sequence > Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxSequence)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_PARAM_SEQ);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    /* Verify the core has assigned for sequence */
+    else if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig)
+    {
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_PARAM_CONFIG); 
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else if (SpiCoreID != Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig->SpiCoreUse)
+    {
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_PARAM_CONFIG); 
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+        /*Do nothing */
+    }
+    return Status;
+}
+#endif
+#endif
+
+/**
+* @brief   Check for busy HWUnit in async transmissions.
+* @details Check for busy HWUnit in async transmissions.
+*
+* @param[in]      SpiCoreID      CoreID
+* @return Spi_StatusType
+*
+*
+*/
+static Spi_StatusType Spi_GetStatusAsyncCheckHwBusy
+    (
+        uint32 SpiCoreID
+    )
+{
+    Spi_StatusType StatusFlag = SPI_IDLE;
+    Spi_HWUnitType HWUnit;
+    
+    for (HWUnit = 0u; HWUnit < (Spi_HWUnitType)SPI_MAX_HWUNIT; HWUnit++)
+    {
+        if ((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+            (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+           )
+        {
+            if (SPI_BUSY == Spi_aSpiHWUnitQueueArray[HWUnit].Status)
+            {
+                StatusFlag = SPI_BUSY;
+                break;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+    return StatusFlag;
+}
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief   This function is called in order to mark the jobs of a sequence as ready to be transmitted.
+* @details For each job in sequence, the function checks if it is already
+*          linked to another pending sequence.
+*          If at least one job is already linked, the function returns E_NOT_OK.
+*          Elsewhere, all jobs in sequence are locked (linked to the current
+*          sequence)
+*
+* @param[in]      Sequence        The sequence ID.
+* @param[in]      JobCount        Number of job in sequence
+*
+* @return Std_ReturnType
+* @retval E_OK       The given sequence does not share its jobs with some
+*                    other sequences, and all its jobs were successfully
+*                    locked.
+* @retval E_NOT_OK  The given sequence shares its jobs with some other
+*                   sequences. No lock performed for its jobs.
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+static Std_ReturnType Spi_LockJobsProcess
+    (
+        Spi_SequenceType SequenceId,
+        const Spi_SequenceConfigType *Sequence,
+        Spi_JobType JobCount
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_JobType JobCountProcess = JobCount;
+    Spi_JobStateType *JobState;
+    const Spi_JobType *Jobs = Sequence->JobIndexList;
+    Spi_SequenceStateType *SequenceState;
+
+    SequenceState = &Spi_axSpiSequenceState[SequenceId];    
+    while (0u < JobCountProcess)
+    {
+        JobState = &Spi_axSpiJobState[*Jobs];
+        if (NULL_PTR == JobState->AsyncCrtSequenceState)
+        {
+            /* Job not yet linked => link it to the current sequence */
+            JobState->AsyncCrtSequenceState = SequenceState;
+        }
+        else
+        {
+            /* The job is already locked by a pending sequence =>
+               rollback all the previous locks */
+            if (JobCountProcess < Sequence->NumJobs)
+            {
+                do
+                {
+                    JobCountProcess++;
+                    Jobs--;
+                    Spi_axSpiJobState[*Jobs].AsyncCrtSequenceState = NULL_PTR;
+                }
+                while (JobCountProcess < Sequence->NumJobs);
+            }
+            else
+            {
+                /* Do nothing */
+            }
+            Status = (Std_ReturnType)E_NOT_OK;
+            break;
+        }
+
+        /* Next job */
+        JobCountProcess--;
+        Jobs++;
+    }
+    return Status;
+}
+#endif
+/*
+*                                      GLOBAL FUNCTIONS
+*/
+
+#if (SPI_VERSION_INFO_API == STD_ON)
+/*=====*/
+/**
+* @brief   This function returns the version information for the SPI driver.
+* @details This function returns the version information for the SPI driver.
+*          - Service ID:       0x09
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in,out]    VersionInfo      Pointer to where to store the version
+*                                    information of this module.
+*
+* @pre  Pre-compile parameter SPI_VERSION_INFO_API shall be STD_ON.
+*
+*/
+/** @implements Spi_GetVersionInfo_Activity */
+void Spi_GetVersionInfo 
+    (
+        Std_VersionInfoType *versioninfo
+    )
+{
+#if( SPI_DEV_ERROR_DETECT == STD_ON )
+    if(NULL_PTR == versioninfo)
+    {
+        (void)Det_ReportError((uint16)SPI_MODULE_ID,(uint8)0,SPI_GETVERSIONINFO_ID,SPI_E_PARAM_POINTER);
+    }
+    else
+    {
+#endif /* SPI_DEV_ERROR_DETECT == STD_ON */
+    versioninfo->vendorID = (uint16)SPI_VENDOR_ID;
+    versioninfo->moduleID = (uint8)SPI_MODULE_ID;
+    versioninfo->sw_major_version = (uint8)SPI_SW_MAJOR_VERSION;
+    versioninfo->sw_minor_version = (uint8)SPI_SW_MINOR_VERSION;
+    versioninfo->sw_patch_version = (uint8)SPI_SW_PATCH_VERSION;
+#if(SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /* SPI_DEV_ERROR_DETECT == STD_ON */
+}
+#endif /* (SPI_VERSION_INFO_API == STD_ON) */
+
+/*=====*/
+/**
+* @brief   This function initializes the SPI driver.
+* @details This function initializes the SPI driver using the
+*          pre-established configurations
+*          - Service ID:       0x00
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in]     ConfigPtr      Specifies the pointer to the configuration set
+*
+*/
+/** @implements Spi_Init_Activity */
+void Spi_Init
+    (
+        const Spi_ConfigType *ConfigPtr
+    )
+{
+    Spi_HWUnitType HWUnit;
+    uint32 SpiCoreID;
+    Std_ReturnType CheckStatus = (Std_ReturnType)E_OK;
+
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    CheckStatus = Spi_InitCheckDemError(SpiCoreID, ConfigPtr);
+    if ((Std_ReturnType)E_OK == CheckStatus) 
+    {
+#endif /*(SPI_DEV_ERROR_DETECT == STD_ON)*/
+
+    CheckStatus = Spi_CheckInit(ConfigPtr, SpiCoreID);
+
+    if((Std_ReturnType)E_OK == CheckStatus )
+    {
+    #if (SPI_PRECOMPILE_SUPPORT == STD_OFF)
+        Spi_apxSpiConfigPtr[SpiCoreID] = ConfigPtr;
+    #else /* (SPI_CONFIG_VARIANT == SPI_VARIANT_PRECOMPILE) */
+        Spi_apxSpiConfigPtr[SpiCoreID] = Spi_PBCfgVariantPredefined[SpiCoreID];
+    #endif /* (SPI_PRECOMPILE_SUPPORT == STD_OFF) */
+    /* Initiate Channels, Jobs, Sequences state */
+    Spi_InitChannelsJobsSeqsState(SpiCoreID);
+        
+        /* initialize all physical HWUnits */
+        for (HWUnit = (Spi_HWUnitType) 0;
+            HWUnit < (Spi_HWUnitType) SPI_MAX_HWUNIT;
+            HWUnit++)
+        {
+            if((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+               (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+              )
+            {
+                Spi_Ipw_Init(HWUnit, Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig);
+        
+#if (SPI_LEVEL_DELIVERED == LEVEL1)
+            /* handler uses interrupt mode only if LEVEL 1 is selected */
+                Spi_Ipw_IrqConfig(HWUnit, SPI_INTERRUPT_MODE, SpiCoreID);
+#endif            
+#if (SPI_LEVEL_DELIVERED == LEVEL2)
+            /* handler uses polling mode only if LEVEL 2 is selected */
+                Spi_Ipw_IrqConfig(HWUnit, SPI_POLLING_MODE, SpiCoreID);
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+                /* initialize the Job lists => no scheduled job for the unit */
+                Spi_InitJobsList(HWUnit);
+#endif
+                Spi_aSpiHWUnitQueueArray[HWUnit].Status = SPI_IDLE;
+            }
+
+        }
+    }
+    else
+    {
+        /*Do nothing. Should not enter here*/
+    }
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif /*(SPI_DEV_ERROR_DETECT == STD_ON)*/
+}
+/*=====*/
+/**
+* @brief   This function de-initializes the SPI driver.
+* @details This function de-initializes the SPI driver using the
+*          pre-established configurations
+*          - Service ID:       0x01
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @return Std_ReturnType
+* @retval E_OK       de-initialisation command has been accepted
+* @retval E_NOT_OK   de-initialisation command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_DeInit()
+*       otherwise, the function Spi_DeInit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+* @implements Spi_DeInit_Activity
+*/
+Std_ReturnType Spi_DeInit(void)
+{
+    Std_ReturnType TempExit = (Std_ReturnType)E_OK;
+    Spi_HWUnitType HWUnit;
+    uint32 SpiCoreID;
+
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_DEINIT_ID,SPI_E_UNINIT);
+        TempExit = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+#endif
+        /* Check if Spi Status is Busy */
+        if (SPI_BUSY == Spi_GetStatus())
+        {
+            TempExit = E_NOT_OK;
+        }
+        else
+        {
+            /* De-initialize all physical HWUnits */
+            for (HWUnit = (Spi_HWUnitType) 0;
+                 HWUnit < (Spi_HWUnitType) SPI_MAX_HWUNIT;
+                 HWUnit++)
+            {
+                if ((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+                    (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+                   )
+                {
+                    Spi_Ipw_DeInit(HWUnit, SpiCoreID);
+    
+                    Spi_aSpiHWUnitQueueArray[HWUnit].Status = SPI_UNINIT;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            /* Reset configuration pointer */
+            Spi_apxSpiConfigPtr[SpiCoreID] = NULL_PTR;
+        }
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return TempExit;
+}
+
+/*=====*/
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE0) ||(SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+/**
+* @brief   This function writes the given data into the buffer of a specific channel.
+* @details This function writes the given data into the buffer of a specific channel.
+*          - Service ID:       0x02
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Channel             Channel ID
+* @param[in]      DataBufferPtr       Pointer to source data buffer
+*
+* @return Std_ReturnType
+* @retval E_OK       Command has been accepted
+* @retval E_NOT_OK   Command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_WriteIB()
+*       otherwise, the function Spi_WriteIB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE0 or USAGE2.
+*
+*/
+/** @implements Spi_WriteIB_Activity */
+Std_ReturnType Spi_WriteIB
+    (
+        Spi_ChannelType Channel,
+        const Spi_DataBufferType *DataBufferPtr
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    uint16 Index;
+    Spi_ChannelStateType *ChannelState;
+    const Spi_ChannelConfigType *ChannelConfig;
+    Spi_DataBufferType *DataBufferDes;
+    const Spi_DataBufferType *DataBufferSrc;
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    Status = Spi_ChannelCheckValidity(Channel, SPI_WRITEIB_ID);
+
+    if ((Std_ReturnType)E_OK != Status)
+    {
+       /* Do nothing */
+    }
+    else
+    {
+#endif
+        ChannelState = &Spi_axSpiChannelState[Channel];
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg;
+
+        /* exit early if this is the wrong buffer type */
+        if (EB == ChannelConfig->BufferType)
+        {
+            Status = (Std_ReturnType)E_NOT_OK;
+            /* Call Det_ReportError */
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_WRITEIB_ID,SPI_E_PARAM_CHANNEL);
+#endif
+        }
+        else
+        {
+            SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_04();
+            /* if DataBufferPtr is zero, then transmit default value */
+            if (NULL_PTR == DataBufferPtr)
+            {
+
+                ChannelState->Flags |= SPI_CHANNEL_FLAG_TX_DEFAULT_U8;
+            }
+
+            /* otherwise, copy data from DataBufferPtr to IB */
+            else
+            {
+                DataBufferDes = ChannelConfig->BufferDescriptor->BufferTX;
+                DataBufferSrc = DataBufferPtr;
+                for (Index = 0u; Index < ChannelConfig->Length; Index++)
+                {
+                    *DataBufferDes=*DataBufferSrc;
+                    DataBufferDes++;
+                    DataBufferSrc++;
+                }
+                ChannelState->Flags = 
+                    (uint8)(ChannelState->Flags & ((uint8)(~SPI_CHANNEL_FLAG_TX_DEFAULT_U8)));
+            }
+            SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_04();
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    /* Return status */
+    return Status;
+}
+#endif
+
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief   This function triggers the asynchronous transmission for the given sequence.
+* @details This function triggers the asynchronous transmission for the given sequence.
+*          - Service ID:       0x03
+*          - Sync or Async:       Asynchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Std_ReturnType
+* @retval E_OK       Transmission command has been accepted
+* @retval E_NOT_OK   Transmission command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_AsyncTransmit()
+*       otherwise, the function Spi_AsyncTransmit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+/** @implements Spi_AsyncTransmit_Activity */
+Std_ReturnType Spi_AsyncTransmit
+    (
+        Spi_SequenceType Sequence
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_JobType NumJobsInSequence;
+    Spi_JobType JobIndex;
+    Spi_JobType JobId;
+    const Spi_SequenceConfigType *SequenceConfig;
+    Spi_SequenceStateType *SequenceState;
+    const Spi_JobConfigType *JobConfig;
+    const Spi_JobType *Job;
+    const Spi_JobType *JobCount;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    Spi_HWUnitType HWUnit;
+#endif
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error and do nothing if driver isn't init or sequen ID is not in correct range */
+    Status = Spi_AsyncTransmitCheckDemReport(SpiCoreID, Sequence);
+    if ((Std_ReturnType)E_OK == Status)
+    {
+        /* Check core has assigned for sequence */
+        if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig)
+        {
+            /* Has wrong core */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_PARAM_CONFIG);
+            Status = (Std_ReturnType)E_NOT_OK;
+        } else if (SpiCoreID != Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig->SpiCoreUse)
+        {
+            /* Has wrong core */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_PARAM_CONFIG);
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#endif
+        SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+        /* Get the number of jobs in the sequence */
+        NumJobsInSequence = SequenceConfig->NumJobs;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* check for empty sequence */
+        if (0u == NumJobsInSequence)
+        {
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_SEQ_EMPTY);
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+#endif /* (SPI_DEV_ERROR_DETECT == STD_OFF) */
+
+        JobIndex = 0u;
+        while(JobIndex < NumJobsInSequence)
+        {
+            /* Get the job id */
+            JobId = SequenceConfig->JobIndexList[JobIndex];
+
+            JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[JobId].JobCfg;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            /* check for empty jobs */
+            if (0u == JobConfig->NumChannels)
+            {
+                /* Call Det_ReportError */
+                (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_JOB_EMPTY);
+                Status = (Std_ReturnType)E_NOT_OK;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+
+            /* Logical Spi HWUnit */
+            HWUnit = JobConfig->HWUnit;
+
+            if (SPI_PHYUNIT_ASYNC_U32 != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IsSync)
+            {
+                /* HwUnit is not prearranged for dedicated Asynchronous
+                   transmission */
+                /* Call Det_ReportError */
+                (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_PARAM_UNIT);
+                Status = (Std_ReturnType)E_NOT_OK;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+            if ((Std_ReturnType)E_OK == Status)
+            {
+                /* Check the validity of EB channels */
+                Status = Spi_AsyncTransmitCheckValidityOfChannels(SpiCoreID, JobConfig);
+            }
+#endif /* ((SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) ) */
+            if ((Std_ReturnType)E_OK != Status)
+            {
+                /* break */
+                break;
+            }
+            else
+            {
+                /* Do nothing */
+            }
+#endif /* (SPI_DEV_ERROR_DETECT == STD_OFF) */
+            JobIndex++;
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        if ((Std_ReturnType)E_OK == Status)
+        {
+#endif /* (SPI_DEV_ERROR_DETECT == STD_OFF) */
+
+            Status = Spi_LockJobs(Sequence, SequenceConfig);
+            if ((Std_ReturnType)E_OK == Status)
+            {
+                SequenceState = &Spi_axSpiSequenceState[Sequence];
+                /* Mark sequence pending */
+                SequenceState->Result = SPI_SEQ_PENDING;
+
+                /* Initialize job related information */
+                SequenceState->RemainingJobs = SequenceConfig->NumJobs - 1u;
+                Job = &SequenceConfig->JobIndexList[0];
+                SequenceState->CurrentJobIndexPointer = Job;
+                for(JobIndex = 0u; JobIndex < NumJobsInSequence; JobIndex++)
+                {
+                    JobCount = &SequenceConfig->JobIndexList[JobIndex];
+                    Spi_axSpiJobState[*JobCount].Result = SPI_JOB_QUEUED;
+                }
+                /* Schedule transmission of the first job */
+                JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[*Job].JobCfg;
+                Spi_ScheduleJob(&Spi_aSpiHWUnitQueueArray[JobConfig->HWUnit],
+                                *Job, JobConfig);
+            }
+            else
+            {
+                /* Call Det_ReportRuntimeError */
+                (void)Det_ReportRuntimeError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_ASYNCTRANSMIT_ID,SPI_E_SEQ_PENDING);
+            }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+#endif /* (SPI_DEV_ERROR_DETECT == STD_OFF) */
+
+    return Status;
+}
+
+#endif
+
+/*=====*/
+#if ((SPI_CHANNEL_BUFFERS_ALLOWED == USAGE0) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2))
+/**
+* @brief   This function reads the data from the buffer of a channel and puts at the memory location.
+* @details This function reads the data from the buffer of a specific channel
+*          and puts at the specified memory location.
+*          - Service ID:       0x04
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+*
+* @param[in]      Channel             Channel ID
+* @param[in,out]  DataBufferPointer       Pointer to the memory location that will
+*                                     be written with the data in the internal
+*                                     buffer
+*
+* @return Std_ReturnType
+* @retval E_OK      read command has been accepted
+* @retval E_NOT_OK  read command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_ReadIB()
+*       otherwise, the function Spi_ReadIB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE0 or USAGE2.
+*
+*/
+/** @implements Spi_ReadIB_Activity */
+Std_ReturnType Spi_ReadIB
+    (
+        Spi_ChannelType Channel,
+        Spi_DataBufferType *DataBufferPointer
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_NumberOfDataType Index;
+    const Spi_ChannelConfigType *ChannelConfig;
+    const Spi_DataBufferType *pDataBufferSrc;
+    Spi_DataBufferType *DataBufferDes;
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    Status = Spi_ChannelCheckValidity(Channel, SPI_READIB_ID);
+
+    if ((Std_ReturnType)E_OK != Status)
+    {
+        /* Do nothing */
+    }
+    else
+    {
+#endif
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg;
+
+        /* exit early if this is the wrong buffer type or destination
+           is invalid */
+        if (EB == ChannelConfig->BufferType)
+        {
+            /* Call Det_ReportError */
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_READIB_ID,SPI_E_PARAM_CHANNEL);
+#endif
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else if (NULL_PTR == DataBufferPointer)
+        {
+            /* Call Det_ReportError */
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_READIB_ID,SPI_E_PARAM_CHANNEL);
+#endif
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* Copy Rx buffer to IB buffer */
+            pDataBufferSrc = ChannelConfig->BufferDescriptor->BufferRX;
+            DataBufferDes = DataBufferPointer;
+            for (Index = 0u; Index < ChannelConfig->Length; Index++)
+            {
+                    *DataBufferDes=*pDataBufferSrc;
+                    DataBufferDes++;
+                    pDataBufferSrc++;
+            }
+        }
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return Status;
+}
+#endif
+
+/*=====*/
+#if ( (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE1) || (SPI_CHANNEL_BUFFERS_ALLOWED == USAGE2) )
+/**
+* @brief   This function setup an external buffer to be used by a specific channel.
+* @details This function setup an external buffer to be used by a specific channel.
+*          - Service ID:       0x05
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Channel             Channel ID
+* @param[in]      SrcDataBufferPtr    Pointer to the memory location that will hold
+*                                     the transmitted data
+* @param[in]      Length              Length of the data in the external buffer
+* @param[out]     DesDataBufferPtr    Pointer to the memory location that will hold
+*                                     the received data
+*
+* @return Std_ReturnType
+* @retval E_OK      Setup command has been accepted
+* @retval E_NOT_OK  Setup command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_SetupEB()
+*       otherwise, the function Spi_SetupEB() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CHANNEL_BUFFERS_ALLOWED shall be USAGE1 or USAGE2.
+*
+*/
+/** @implements Spi_SetupEB_Activity */
+Std_ReturnType Spi_SetupEB
+    (
+        Spi_ChannelType Channel,
+        Spi_DataBufferType *SrcDataBufferPtr,
+        Spi_DataBufferType *DesDataBufferPtr,
+        Spi_NumberOfDataType Length
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_ChannelStateType *ChannelState;
+    const Spi_ChannelConfigType *ChannelConfig;
+    uint32 SpiCoreID;
+
+    /* get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    Status = Spi_ChannelCheckValidity(Channel, SPI_SETUPEB_ID);
+
+    if ((Std_ReturnType)E_OK != Status)
+    {
+        /* Do nothing */
+    }
+    /* Length - Valid range */
+    else if ((Length > Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg->Length) || (0u == Length))
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETUPEB_ID, SPI_E_PARAM_LENGTH);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+#endif
+        ChannelState = &Spi_axSpiChannelState[Channel];
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Channel].ChannelCfg;
+        /* exit early if this is the wrong buffer type */
+        if (IB == ChannelConfig->BufferType)
+        {
+            /* Call Det_ReportError */
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETUPEB_ID,SPI_E_PARAM_CHANNEL);
+#endif
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            /* Length and Framesize - aren't compatible */
+            /* If 8 < Framesize =< 16: Length must be divisible by 2 */
+            /* If 16 < Framesize =< 32: Length must be divisible by 4 */
+            Status = Spi_SetupEbCheckLength(ChannelConfig, Length);
+#endif
+            SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_05();
+            /* save the new parameters */
+            ChannelConfig->BufferDescriptor->BufferTX = SrcDataBufferPtr;
+            ChannelConfig->BufferDescriptor->BufferRX = DesDataBufferPtr;
+
+            ChannelState->Length = Length;
+
+            /* if source data pointer is zero, transmit default value */
+            if (NULL_PTR == SrcDataBufferPtr)
+            {
+                ChannelState->Flags |= SPI_CHANNEL_FLAG_TX_DEFAULT_U8;
+            }
+            else
+            {
+                ChannelState->Flags &= (uint8) (~SPI_CHANNEL_FLAG_TX_DEFAULT_U8);
+            }
+
+            /* if destination data pointer is zero, discard receiving data */
+            if (NULL_PTR == DesDataBufferPtr)
+            {
+                ChannelState->Flags |= SPI_CHANNEL_FLAG_RX_DISCARD_U8;
+            }
+            else
+            {
+                ChannelState->Flags &= (uint8) (~SPI_CHANNEL_FLAG_RX_DISCARD_U8);
+            }
+            SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_05();
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return Status;
+}
+#endif
+/*=====*/
+/**
+* @brief   This function returns the status of the SPI driver.
+* @details This function returns the status of the SPI driver.
+*          - Service ID:       0x06
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @return Spi_StatusType
+* @retval SPI_UNINIT  The driver is un-initialized
+* @retval SPI_IDLE    The driver has no pending transfers
+* @retval SPI_BUSY    The driver is busy
+*
+* @pre  The driver needs to be initialized before calling Spi_GetStatus()
+*       otherwise, the function Spi_GetStatus() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+* @implements Spi_GetStatus_Activity
+*/
+Spi_StatusType Spi_GetStatus(void)
+{
+    Spi_StatusType StatusFlag = SPI_IDLE;
+    Spi_HWUnitType HWUnit;
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* If Development Error Detection is enabled, report error if not */
+        /* initialized */
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETSTATUS_ID,SPI_E_UNINIT);
+#endif
+        StatusFlag = SPI_UNINIT;
+    }
+    else
+    {
+        /* The SPI Handler Driver software module shall be busy when any
+           HWUnit is busy */
+        for (HWUnit = 0u; HWUnit < (Spi_HWUnitType)SPI_MAX_HWUNIT; HWUnit++)
+        {
+            if ((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+                (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+               )
+            {
+                if (1u == Spi_au32SpiBusySyncHWUnitsStatus[HWUnit])
+                {
+                    StatusFlag = SPI_BUSY;
+                    break;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            else
+            {
+                /* Do nothing */
+            }
+        }
+        /* check for busy HWUnit in async transmissions */
+        if (SPI_BUSY != StatusFlag)
+        {
+            /* Note: Checking for IsSync attribute for HWUnit is not really needed
+                 It is preferable to skip this check in order to have a more compact code
+            */
+            StatusFlag = Spi_GetStatusAsyncCheckHwBusy(SpiCoreID);
+        }
+        else
+        {
+            /* Do notthing */
+        }
+    }
+    return StatusFlag;
+}
+
+/**
+* @brief   This function is used to request the status of a specific job.
+* @details This function is used to request the status of a specific job.
+*          - Service ID:       0x07
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Job                 Job ID
+*
+* @return Spi_JobResultType
+* @retval SPI_JOB_OK        The job ended successfully
+* @retval SPI_JOB_PENDING   The job is pending
+* @retval SPI_JOB_FAILED    The job has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_GetJobResult()
+*       otherwise, the function Spi_GetJobResult() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+*/
+/** @implements Spi_GetJobResult_Activity */
+Spi_JobResultType Spi_GetJobResult
+    (
+        Spi_JobType Job
+    )
+{
+    Spi_JobResultType JobResult;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+    /* If Development Error Detection is enabled, report error if not */
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        JobResult = SPI_JOB_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETJOBRESULT_ID,SPI_E_UNINIT);
+    }
+    /* Job Valid Range - from 0 to SpiMaxJob*/
+    else if (Job > Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxJob)
+    {
+        JobResult = SPI_JOB_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETJOBRESULT_ID,SPI_E_PARAM_JOB);
+    }
+    else if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg)
+    {
+        JobResult = SPI_JOB_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETJOBRESULT_ID,SPI_E_PARAM_CONFIG);
+    }
+    else if (SpiCoreID != Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg->SpiCoreUse) 
+    {
+        JobResult = SPI_JOB_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETJOBRESULT_ID,SPI_E_PARAM_CONFIG);
+    }
+    else
+    {
+#endif
+        JobResult = Spi_axSpiJobState[Job].Result;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return JobResult;
+}
+
+/**
+* @brief   This function is used to request the status of a specific sequence.
+* @details This function is used to request the status of a specific sequence.
+*          - Service ID:       0x08
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Spi_SeqResultType
+* @retval SPI_SEQ_OK       The sequence ended successfully
+* @retval SPI_SEQ_PENDING  The sequence is pending
+* @retval SPI_SEQ_FAILED   The sequence has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_GetSequenceResult()
+*       otherwise, the function Spi_GetSequenceResult() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+*
+*/
+/** @implements Spi_GetSequenceResult_Activity */
+Spi_SeqResultType Spi_GetSequenceResult
+    (
+        Spi_SequenceType Sequence
+    )
+{
+    Spi_SeqResultType SequenceResult;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    uint32 SpiCoreID;
+    const Spi_SequenceConfigType *SequenceConfig;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#endif
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        SequenceResult = SPI_SEQ_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETSEQUENCERESULT_ID,SPI_E_UNINIT);
+    }
+    /* Sequence Valid Range from 0 to SpiMaxSequence*/
+    else if (Sequence > Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxSequence)
+    {
+        SequenceResult = SPI_SEQ_FAILED;
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETSEQUENCERESULT_ID,SPI_E_PARAM_SEQ);
+    }
+    else
+    {
+        SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+        /* Check core has assigned for sequence */
+        if (NULL_PTR == SequenceConfig)
+        {
+            SequenceResult = SPI_SEQ_FAILED;
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETSEQUENCERESULT_ID,SPI_E_PARAM_CONFIG);
+        }
+        else if (SpiCoreID != SequenceConfig->SpiCoreUse)
+        {
+            SequenceResult = SPI_SEQ_FAILED;
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_GETSEQUENCERESULT_ID,SPI_E_PARAM_CONFIG);
+        }
+        else
+        {
+#endif
+           SequenceResult = Spi_axSpiSequenceState[Sequence].Result;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif
+
+    return SequenceResult;
+}
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+/*=====*/
+/**
+* @brief   This function is used for synchronous transmission of a given sequence.
+* @details This function is used for synchronous transmission of a given sequence.
+*          - Service ID:       0x0a
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @return Std_ReturnType
+* @retval E_OK      Transmission command has been completed successfully
+* @retval E_NOT_OK  Transmission command has not been accepted
+*
+* @pre  The driver needs to be initialized before calling Spi_SyncTransmit().
+*       otherwise, the function Spi_SyncTransmit() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL0 or LEVEL2
+*
+*/
+/** @implements Spi_SyncTransmit_Activity */
+Std_ReturnType Spi_SyncTransmit
+    (
+        Spi_SequenceType Sequence
+    )
+{
+    Spi_SequenceStateType *SequenceState;
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    Spi_HWUnitType HWUnit;
+    Spi_JobType JobIndex;
+    const Spi_SequenceConfigType *SequenceConfig;
+    Spi_JobType NumJobsInSequence;
+    Spi_JobType Job;
+    const Spi_JobConfigType *JobConfig;
+    uint32 SpiCoreID;
+
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    Status = Spi_SyncTransmitCheckDemReport(SpiCoreID, Sequence);
+    if ((Std_ReturnType)E_NOT_OK != Status)
+    {
+        SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+        /* Check the validation of Job */
+        Status = Spi_SynctransmitCheckJobsIsValid(SequenceConfig, SpiCoreID);
+
+        if ((Std_ReturnType)E_NOT_OK != Status)
+        {
+#endif /* (SPI_DEV_ERROR_DETECT == STD_ON) */
+            SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+            /* Get the number of jobs in the sequence */
+            NumJobsInSequence = SequenceConfig->NumJobs;
+
+            SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_06();
+            /* check if there are HW units already running */
+            for (HWUnit = 0u; HWUnit < (Spi_HWUnitType)SPI_MAX_HWUNIT; HWUnit++)
+            {
+                if (0u != ((Spi_au32SpiBusySyncHWUnitsStatus[HWUnit] << HWUnit) & Spi_au32SpiSeqUsedHWUnits[Sequence]))
+                {
+                    Status = (Std_ReturnType)E_NOT_OK;
+                }
+                else
+                {
+                    /* Do notthing */
+                }
+            }
+            
+            if ((Std_ReturnType)E_NOT_OK != Status)
+            {
+                /* Set the sequence as pending */
+                SequenceState = &Spi_axSpiSequenceState[Sequence];
+                SequenceState->Result = SPI_SEQ_PENDING;
+                /* set used HW units as busy */
+                for (JobIndex = 0u; JobIndex < NumJobsInSequence; JobIndex++)
+                {
+                    /* Get the job id */
+                    Job = SequenceConfig->JobIndexList[JobIndex];
+                    JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg;
+                    /* Logical Spi HWUnit */
+                    HWUnit = JobConfig->HWUnit;
+                    Spi_au32SpiBusySyncHWUnitsStatus[HWUnit] = 1u;
+                }
+                SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06();
+                /* Transmit Jobs */
+                Status = Spi_SyncJobsTranfer(SequenceConfig, SpiCoreID);
+                
+                if ((Std_ReturnType)E_OK == Status)
+                {
+                    /* Set the sequence as OK */
+                    SequenceState->Result = SPI_SEQ_OK;
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+                    /* Report to DEM */
+                    Spi_DemReportStatus(SpiCoreID, DEM_EVENT_STATUS_PASSED);
+#endif
+                }
+                else
+                {
+                    /* Set the sequence as FAILED */
+                    SequenceState->Result = SPI_SEQ_FAILED;
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+                    /* Report to DEM */
+                    Spi_DemReportStatus(SpiCoreID, DEM_EVENT_STATUS_FAILED);
+#endif
+                }
+                
+                SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_07();
+                /* set used HW units as idle */
+                for (JobIndex = 0u; JobIndex < NumJobsInSequence; JobIndex++)
+                {
+                    /* Get the job id */
+                    Job = SequenceConfig->JobIndexList[JobIndex];
+                    JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg;
+                    /* Logical Spi HWUnit */
+                    HWUnit = JobConfig->HWUnit;
+                    Spi_au32SpiBusySyncHWUnitsStatus[HWUnit] = 0u;
+                }
+                SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_07();
+                
+                /* End Sequence Notification */
+                if (NULL_PTR != SequenceConfig->EndNotification)
+                {
+                    SequenceConfig->EndNotification();
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            else
+            {
+                SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_06();
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+#if (SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT == STD_ON)
+                /* Call Det_ReportRuntimeError */
+                (void)Det_ReportRuntimeError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SYNCTRANSMIT_ID,SPI_E_SEQ_IN_PROCESS);
+#endif
+#endif
+            }
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        }
+        else
+        {
+            /* Do nothing */
+        }
+    }
+#endif
+
+    return Status;
+}
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) ) */
+
+/*=====*/
+#if (SPI_HW_STATUS_API == STD_ON)
+/**
+* @brief   This function is used to request the status of a specific SPI peripheral unit.
+* @details This function is used to request the status of a specific SPI peripheral unit.
+*          - Service ID:       0x0b
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      HWUnit              The HW peripheral for which we need the status
+*
+* @return Spi_StatusType
+* @retval SPI_UNINIT  The peripheral is un-initialized
+* @retval SPI_IDLE    The peripheral is in idle state
+* @retval SPI_BUSY    The peripheral is busy
+*
+* @pre  The driver needs to be initialized before calling Spi_GetHWUnitStatus()
+*       otherwise, the function Spi_GetHWUnitStatus() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  SPI_HW_STATUS_API == STD_ON
+*
+*/
+/** @implements Spi_GetHWUnitStatus_Activity */
+Spi_StatusType Spi_GetHWUnitStatus
+    (
+        Spi_HWUnitType HWUnit
+    )
+{
+    Spi_StatusType Status = SPI_UNINIT;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    if ((Std_ReturnType)E_OK != Spi_HWUnitCheckValidity(HWUnit, SPI_GETHWUNITSTATUS_ID))
+    {
+        /* Do nothing */
+    }
+    else
+    {
+#endif
+        Status = Spi_aSpiHWUnitQueueArray[HWUnit].Status;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+    return Status;
+}
+#endif
+/*=====*/
+#if (SPI_CANCEL_API == STD_ON)
+/**
+* @brief   This function is used to request the cancelation of the given sequence.
+* @details This function is used to request the cancelation of the given sequence.
+*          - Service ID:       0x0c
+*          - Sync or Async:       Asynchronous
+*          - Reentrancy:       Reentrant
+*
+* @param[in]      Sequence            Sequence ID
+*
+* @pre  The driver needs to be initialized before calling Spi_Cancel()
+*       otherwise, the function Spi_Cancel() shall raise the development error
+*       if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_CANCEL_API shall be STD_ON
+* @post  The SPI Handler Driver is not responsible on external devices damages or
+*       undefined state due to cancelling a sequence transmission.
+*
+*/
+/**  @implements Spi_Cancel_Activity */
+void Spi_Cancel(Spi_SequenceType Sequence)
+{
+#if ((SPI_SLAVE_SUPPORT == STD_ON) && (SPI_LEVEL_DELIVERED != LEVEL0))
+    const Spi_JobConfigType *JobConfig;
+#endif
+#if (((SPI_SLAVE_SUPPORT == STD_ON) && (SPI_LEVEL_DELIVERED != LEVEL0)) \
+    || (SPI_DEV_ERROR_DETECT == STD_ON))
+    const Spi_SequenceConfigType *SequenceConfig;
+    uint32 SpiCoreID;
+
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+#endif      
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_CANCEL_ID,SPI_E_UNINIT);
+    }
+    /* Sequence Valid Range  from 0 to SpiMaxSequence*/
+    else if (Sequence > Spi_apxSpiConfigPtr[SpiCoreID]->SpiMaxSequence)
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_CANCEL_ID,SPI_E_PARAM_SEQ);
+    }
+    else
+    {
+#endif
+#if (((SPI_SLAVE_SUPPORT == STD_ON) && (SPI_LEVEL_DELIVERED != LEVEL0)) \
+    || (SPI_DEV_ERROR_DETECT == STD_ON))
+        SequenceConfig = Spi_apxSpiConfigPtr[SpiCoreID]->SequenceConfig[Sequence].SeqConfig;
+#endif
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        /* Check core has assigned for sequence */
+        if (NULL_PTR == SequenceConfig)
+        {
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_CANCEL_ID,SPI_E_PARAM_CONFIG);
+        }
+        else if (SpiCoreID != SequenceConfig->SpiCoreUse)
+        {
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_CANCEL_ID,SPI_E_PARAM_CONFIG);
+        }
+        else
+        {
+#endif
+            /* Set sequence state to Cancel */
+            Spi_axSpiSequenceState[Sequence].Result = SPI_SEQ_CANCELLED;
+    
+            /* In Slave mode: Stop sequence immediately */
+            #if (SPI_SLAVE_SUPPORT == STD_ON)
+            #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+            JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[SequenceConfig->JobIndexList[0u]].JobCfg;
+            Spi_Ipw_SlaveCancel(JobConfig);
+            #endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) ) */
+            #endif
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+        }
+    }
+#endif
+}
+#endif
+/*=====*/
+#if (SPI_LEVEL_DELIVERED == LEVEL2)
+/**
+* @brief   This function specifies the asynchronous mode for the SPI busses handled asynchronously.
+* @details This function specifies the asynchronous mode for the SPI busses
+*          handled asynchronously.
+*          - Service ID:       0x0d
+*          - Sync or Async:       Synchronous
+*          - Reentrancy:       Non-Reentrant
+*
+* @param[in]      AsyncMode    This parameter specifies the asynchronous
+*                              operating mode (SPI_POLLING_MODE or
+*                              SPI_INTERRUPT_MODE)
+*
+* @return Std_ReturnType
+* @retval E_OK      The command ended successfully
+* @retval E_NOT_OK  The command has failed
+*
+* @pre  The driver needs to be initialized before calling Spi_SetAsyncMode()
+*       otherwise, the function Spi_SetAsyncMode() shall raise the development
+*       error if SPI_DEV_ERROR_DETECT is STD_ON.
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL2
+*
+*/
+/** @implements Spi_SetAsyncMode_Activity */
+Std_ReturnType Spi_SetAsyncMode
+    (
+        Spi_AsyncModeType AsyncMode
+    )
+{
+    Spi_HWUnitType HWUnit;
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETASYNCMODE_ID,SPI_E_UNINIT);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+#endif
+        if (SPI_BUSY == Spi_GetAsyncStatus())
+        {
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* set the async mode for each HW Unit;
+               activate/deactivate EOQ interrupts for Async HWUnits */
+            for (HWUnit = 0u; HWUnit < (Spi_HWUnitType) SPI_MAX_HWUNIT; HWUnit++)
+            {
+                if ((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+                    (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse) &&
+                    (SPI_PHYUNIT_ASYNC_U32 == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IsSync)
+                   )
+                {
+                    Spi_Ipw_IrqConfig(HWUnit, AsyncMode, SpiCoreID);
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return Status;
+}
+#endif
+
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON))
+/**
+* @brief   This function specifies the asynchronous mode for a given HWUnit.
+* @details This function specifies the asynchronous mode for the SPI busses
+*          handled asynchronously.
+*          For synchronous HW units, the function has no impact.
+*          The function will fail in two cases:
+*          - driver not initialised (SPI_E_UNINIT reported by DET)
+*          - a sequence transmission is pending the the asynchronous HW unit
+*            (SPI_E_SEQ_PENDING reported by DET)
+*
+* @param[in]      HWUnit       The ID of the HWUnit to be configured
+* @param[in]      AsyncMode    This parameter specifies the asynchronous
+*                              operating mode (SPI_POLLING_MODE or
+*                              SPI_INTERRUPT_MODE)
+*
+* @return Std_ReturnType
+* @retval E_OK       The command ended successfully
+* @retval E_NOT_OK   The command has failed
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL2 and
+*       SPI_HWUNIT_ASYNC_MODE should be on STD_ON
+*
+*/
+/** @implements Spi_SetHWUnitAsyncMode_Activity */
+Std_ReturnType Spi_SetHWUnitAsyncMode
+    (
+        Spi_HWUnitType HWUnit,
+        Spi_AsyncModeType AsyncMode
+    )
+{
+    Std_ReturnType Status = (Std_ReturnType)E_OK;
+    uint32 SpiCoreID = Spi_GetCoreID;
+
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    Status = Spi_HWUnitCheckValidity(HWUnit, SPI_SETHWUNITASYNCMODE_ID);
+
+    if ((Std_ReturnType)E_OK != Status)
+    {
+        /* Do nothing */
+    }
+    else
+    {
+#endif
+        if (SPI_PHYUNIT_ASYNC_U32 != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IsSync)
+        {
+            /* return E_NOT_OK if HWUnit is Sync */
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+            /* Call Det_ReportError */
+            (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETHWUNITASYNCMODE_ID,SPI_E_PARAM_UNIT);
+#endif
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else if (SPI_BUSY == Spi_aSpiHWUnitQueueArray[HWUnit].Status)
+        {
+            /* return E_NOT_OK if HWUnit is Async and Busy */
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            /* set the async mode & activate/deactivate the interrupts for the HW Unit */
+            Spi_Ipw_IrqConfig(HWUnit, AsyncMode, SpiCoreID);
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+
+    return Status;
+}
+#endif /* (SPI_LEVEL_DELIVERED == LEVEL2) && (SPI_HWUNIT_ASYNC_MODE == STD_ON) */
+
+/*=====*/
+/**
+* @brief   This function shall asynchronously poll SPI interrupts and call ISR if appropriate.
+* @details This function shall asynchronously poll SPI interrupts and call
+*          ISR if appropriate.
+*          - Service ID:       0x10
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+/** @implements Spi_MainFunction_Handling_Activity */
+void Spi_MainFunction_Handling(void)
+{
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+    Spi_HWUnitType HWUnit;
+    uint32 SpiCoreID;
+    
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+
+    if (NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        for (HWUnit = 0u; HWUnit < (Spi_HWUnitType) SPI_MAX_HWUNIT; HWUnit++)
+        {
+            if((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+               (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+              )
+            {
+                if (SPI_BUSY == Spi_aSpiHWUnitQueueArray[HWUnit].Status)
+                {
+                    Spi_Ipw_IrqPoll(HWUnit, SpiCoreID);
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+            else
+            {
+                /*Do nothing */
+            }
+        }
+    }
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) ) */
+}
+
+/*=====*/
+/**
+* @brief   This function starts the transfer of the first scheduled job for a given HW unit.
+* @details If the list of scheduled jobs is not empty, pop the first job and
+*          start the transfer. Elsewhere, mark the HW unit as IDLE.
+*
+* @param[in]      HWUnitQueue     The HW Unit used for scheduling
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static void Spi_ScheduleNextJob
+    (
+        Spi_HWUnitQueue *HWUnitQueue,
+        uint32 SpiCoreID
+    )
+{
+    Spi_JobType Job;
+    Spi_JobType *JobListHead;
+    sint8 Priority;
+    sint8 MaxScheduledPriority;
+
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_01();
+    MaxScheduledPriority = HWUnitQueue->MaxScheduledPriority;
+    if (0 > MaxScheduledPriority)
+    {
+        /* no job waiting => mark the HWUnit as IDLE */
+        HWUnitQueue->Status = SPI_IDLE;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01();
+    }
+    else
+    {
+        /* a job is waiting => get the job ID from the highest priority queue */
+        JobListHead = &HWUnitQueue->ScheduledJobsListHead[MaxScheduledPriority];
+        Job = *JobListHead;
+
+        /* set the new head of the list */
+        *JobListHead = Spi_axSpiJobState[Job].AsyncNextJob;
+
+        /* if the list is empty, set the tail accordingly and adjust the
+           scheduled priority level */
+        if (SPI_JOB_NULL == *JobListHead)
+        {
+            /* reset the tail */
+            HWUnitQueue->ScheduledJobsListTail[MaxScheduledPriority] = SPI_JOB_NULL;
+
+            /* find the first non empty scheduling queue */
+            for (Priority = MaxScheduledPriority - 1; Priority >= 0; Priority--)
+            {
+                if (SPI_JOB_NULL != HWUnitQueue->ScheduledJobsListHead[Priority])
+                {
+                    /* there is a scheduled Job for this priority level */
+                    break;
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+            }
+
+            /* Priority is set on the highest priority queue having
+               scheduled jobs, or -1 if no other jobs scheduled */
+            HWUnitQueue->MaxScheduledPriority = Priority;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_01();
+
+        /* mark the job as pending */
+        Spi_axSpiJobState[Job].Result = SPI_JOB_PENDING;
+        HWUnitQueue->Channel = 0u;
+        HWUnitQueue->Job = Job;
+        Spi_Ipw_JobTransfer(Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg);
+    }
+}
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) ) */
+
+/*=====*/
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/**
+* @brief   This function is called after a Job has been executed.
+* @details The function calls Job and Sequence end notifications and schedules
+*          the next job of the sequence or on the liberated HW Unit.
+*
+* @param[in]    JobConfig   The just transmited job pointer.
+*
+* @pre  Pre-compile parameter SPI_LEVEL_DELIVERED shall be LEVEL1 or LEVEL2.
+*
+* @implements Spi_JobTransferFinished_Activity
+*/
+void Spi_JobTransferFinished
+    (
+        const Spi_JobConfigType *JobConfig, Spi_JobResultType JobResult
+    )
+{
+    Spi_HWUnitType HWUnit = JobConfig->HWUnit;
+    Spi_HWUnitQueue *HWUnitQueue = &Spi_aSpiHWUnitQueueArray[HWUnit];
+    Spi_JobStateType *JobState = JobConfig->JobState;
+    Spi_SequenceStateType *SequenceState;
+    const Spi_SequenceConfigType *SequenceConfig;
+    const Spi_JobType *Job;
+    const Spi_JobConfigType *CurrentJobConfig;
+    Spi_JobType JobId;
+    uint32 SpiCoreID;
+    #if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+    Spi_JobType JobIdx;
+    #endif
+
+    SchM_Enter_Spi_SPI_EXCLUSIVE_AREA_02();
+    if((SPI_JOB_OK != JobState->Result) && (NULL_PTR != JobState->AsyncCrtSequenceState))
+    {
+        JobState->Result = JobResult;
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02();
+        
+        SpiCoreID = JobConfig->SpiCoreUse;
+        SequenceState = JobState->AsyncCrtSequenceState;
+        SequenceConfig = SequenceState->Sequence;
+        /* unlink the job from its sequence */
+        JobState->AsyncCrtSequenceState = NULL_PTR;
+        /* Perform job EndNotification (if there is one) */
+        if (NULL_PTR != JobConfig->EndNotification)
+        {
+            JobConfig->EndNotification();
+        }
+        else
+        {
+            /* Do nothing */
+        }
+        /* set Sequence to fail if Job has been failed */
+        if((SPI_JOB_FAILED == JobState->Result) && (SequenceState->Result != SPI_SEQ_CANCELLED))
+        {
+            SequenceState->Result = SPI_SEQ_FAILED;
+        }
+        else
+        {
+            /* Do nothing */
+        }
+        /* Check if current sequence has been cancelled or fail*/
+#if (SPI_CANCEL_API == STD_ON)
+        if ((SPI_SEQ_CANCELLED == SequenceState->Result) || (SPI_SEQ_FAILED == SequenceState->Result))
+#else
+        if (SPI_SEQ_FAILED == SequenceState->Result)
+#endif
+        {
+            /* unlock jobs */
+            Spi_UnlockRemainingJobs(SequenceState->RemainingJobs, SequenceConfig);
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+            if(SPI_SEQ_FAILED == SequenceState->Result)
+            {
+                /* Report to DEM */
+                Spi_DemReportStatus(SpiCoreID, DEM_EVENT_STATUS_FAILED);
+            }
+            else
+            {
+                /* Report to DEM */
+                Spi_DemReportStatus(SpiCoreID, DEM_EVENT_STATUS_PASSED);
+            }
+#endif
+            /* SeqEndNotification */
+            if (NULL_PTR != SequenceConfig->EndNotification)
+            {
+                SequenceConfig->EndNotification();
+            }
+            else
+            {
+                /* Do nothing */
+            }
+
+            Spi_ScheduleNextJob(HWUnitQueue, SpiCoreID);
+        }
+        else
+        {
+            #if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+            if(TRUE == SequenceConfig->EnableDmaFastTransfer)
+            {
+                /* Set Job result to SPI_JOB_OK for all remaining Jobs */
+                for (JobIdx = SequenceConfig->NumJobs-SequenceState->RemainingJobs; JobIdx < SequenceConfig->NumJobs; JobIdx++)
+                {
+                    Spi_axSpiJobState[SequenceConfig->JobIndexList[JobIdx]].Result = SPI_JOB_OK;
+                }
+                /* unlock jobs */
+                Spi_UnlockRemainingJobs(SequenceState->RemainingJobs, SequenceConfig);
+                /* Set remaining Jobs to 0 */
+                SequenceState->RemainingJobs = 0u;
+            }
+            else
+            {
+                /* nothing to do */
+            }
+            #endif
+            /* Check if this job is the last one */
+            if (0u == SequenceState->RemainingJobs)
+            {
+                /* Reset sequence state */
+                SequenceState->Result = SPI_SEQ_OK;
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+                /* Report to DEM */
+                Spi_DemReportStatus(SpiCoreID, DEM_EVENT_STATUS_PASSED);
+#endif
+
+                /* SeqEndNotification */
+                if (NULL_PTR != SequenceConfig->EndNotification)
+                {
+                    SequenceConfig->EndNotification();
+                }
+                else
+                {
+                    /* Do nothing */
+                }
+
+                Spi_ScheduleNextJob(HWUnitQueue, SpiCoreID);
+
+            }
+            else
+            {
+                /* advance to the next job */
+                SequenceState->CurrentJobIndexPointer++;
+                Job = SequenceState->CurrentJobIndexPointer;
+                JobId = *Job;
+                SequenceState->RemainingJobs--;
+                CurrentJobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[JobId].JobCfg;
+                if (HWUnit != CurrentJobConfig->HWUnit)
+                {
+                    /* schedule the next job on the new DSPI unit */
+                    Spi_ScheduleJob(&Spi_aSpiHWUnitQueueArray[CurrentJobConfig->HWUnit], JobId, CurrentJobConfig);
+
+                    /* transmit the next scheduled job on the current DSPI unit */
+                    Spi_ScheduleNextJob(HWUnitQueue, SpiCoreID);
+                }
+                else
+                {
+                    /* the next job uses the same DSPI unit */
+
+#if (SPI_INTERRUPTIBLE_SEQ_ALLOWED == STD_ON)
+                    if (1u == SequenceConfig->Interruptible)
+                    {
+                        /* if the sequence is interruptible,
+                           then schedule the next job */
+                        /* DSPI is marked as BUSY => the new job is scheduled only */
+                        Spi_ScheduleJob(HWUnitQueue, JobId, CurrentJobConfig);
+
+                        /* run the first eligible job */
+                        Spi_ScheduleNextJob(HWUnitQueue, SpiCoreID);
+                    }
+                    else
+#endif
+                    {
+                        /* non-interruptible sequence =>
+                           start transmission without scheduling */
+                        /* mark the job as pending */
+                        Spi_axSpiJobState[JobId].Result = SPI_JOB_PENDING;
+                        HWUnitQueue->Channel = 0;
+                        HWUnitQueue->Job = JobId;
+                        Spi_Ipw_JobTransfer(CurrentJobConfig);
+                    }
+                }
+            }
+        }
+    }
+    else
+    {
+        SchM_Exit_Spi_SPI_EXCLUSIVE_AREA_02();
+    }
+}
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2) ) */
+
+#if (SPI_DUAL_CLOCK_MODE == STD_ON)
+/**
+* @brief   This function shall set different MCU clock configuration .
+* @details This function shall set different MCU clock configuration .
+*
+* @param[in]    ClockMode   Clock mode to be set (SPI_NORMAL | SPI_ALTERNATE).
+*
+* @return Std_ReturnType
+* @retval E_OK       The driver is initialised and in an IDLE state. The clock
+*                    mode can be changed.
+* @retval E_NOT_OK   The driver is NOT initialised OR is NOT in an IDLE state.
+*                    The clock mode can NOT be changed.
+*
+* @pre  Pre-compile parameter SPI_DUAL_CLOCK_MODE shall be STD_ON.
+*
+*/
+/** @implements Spi_SetClockMode_Activity */
+Std_ReturnType Spi_SetClockMode
+    (
+        Spi_DualClockModeType ClockMode
+    )
+{
+   Std_ReturnType Status = (Std_ReturnType)E_OK;
+   Spi_HWUnitType HWUnit;
+   uint32 SpiCoreID;
+   
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    /* If Development Error Detection is enabled, report error if not */
+    /* initialized */
+    if (NULL_PTR == Spi_apxSpiConfigPtr[SpiCoreID])
+    {
+        /* Call Det_ReportError */
+        (void)Det_ReportError((uint16) SPI_MODULE_ID,(uint8) 0,SPI_SETCLOCKMODE_ID,SPI_E_UNINIT);
+        Status = (Std_ReturnType)E_NOT_OK;
+    }
+    else
+    {
+#endif
+        /* Check if Spi Status is Busy */
+        if (SPI_BUSY == Spi_GetStatus())
+        {
+            Status = (Std_ReturnType)E_NOT_OK;
+        }
+        else
+        {
+            for (HWUnit = (Spi_HWUnitType)0;
+            HWUnit < (Spi_HWUnitType)SPI_MAX_HWUNIT;
+            HWUnit++)
+            {
+                if((NULL_PTR != Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig) &&
+                   (SpiCoreID == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->SpiCoreUse)
+                  )
+                {
+                    Spi_Ipw_SetClockMode(ClockMode, Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig);
+                }
+            }
+        }
+#if (SPI_DEV_ERROR_DETECT == STD_ON)
+    }
+#endif
+    return Status;
+}
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

RTD/src/Spi_IPW.c

@@ -0,0 +1,914 @@
+/**
+*   @file    Spi_Ipw.c
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Isolation level file for SPI driver.
+*   @details Implementation file for function definition on isolation level between high and low level driver.
+*
+*   @addtogroup SPI_DRIVER Spi Driver
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Spi_IPW.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_VENDOR_ID_C                       43
+#define SPI_IPW_AR_RELEASE_MAJOR_VERSION_C        4
+#define SPI_IPW_AR_RELEASE_MINOR_VERSION_C        4
+#define SPI_IPW_AR_RELEASE_REVISION_VERSION_C     0
+#define SPI_IPW_SW_MAJOR_VERSION_C                1
+#define SPI_IPW_SW_MINOR_VERSION_C                0
+#define SPI_IPW_SW_PATCH_VERSION_C                0
+/*==================================================================================================
+*                                      FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Spi_IPW.c and Spi_IPW.h are of the same vendor */
+#if (SPI_IPW_VENDOR_ID_C != SPI_IPW_VENDOR_ID)
+    #error "Spi_IPW.c and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if Spi_IPW.c file and Spi_IPW.h file are of the same Autosar version */
+#if ((SPI_IPW_AR_RELEASE_MAJOR_VERSION_C != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_MINOR_VERSION_C != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_REVISION_VERSION_C != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi_IPW.c and Spi_IPW.h are different"
+#endif
+#if ((SPI_IPW_SW_MAJOR_VERSION_C != SPI_IPW_SW_MAJOR_VERSION) || \
+     (SPI_IPW_SW_MINOR_VERSION_C != SPI_IPW_SW_MINOR_VERSION) || \
+     (SPI_IPW_SW_PATCH_VERSION_C != SPI_IPW_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi_IPW.c and Spi_IPW.h are different"
+#endif
+/*==================================================================================================
+*                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       GLOBAL VARIABLES
+==================================================================================================*/
+#define   SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+extern Spi_HWUnitQueue Spi_aSpiHWUnitQueueArray[SPI_MAX_HWUNIT];
+
+extern Lpspi_Ip_StateStructureType* Lpspi_Ip_apxStateStructureArray[LPSPI_INSTANCE_COUNT];
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+extern Flexio_Spi_Ip_StateStructureType* Flexio_Spi_Ip_apxStateStructureArray[FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8];
+#endif
+
+/**
+* @brief Mapping between Lpspi channel id and instance id
+*/
+static Spi_HWUnitType Spi_Ipw_au8LpspiHWUnitMapping[LPSPI_IP_NUMBER_OF_INSTANCES];
+
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+/**
+* @brief Mapping between Flexio channel id and hardware unit id
+*/
+static Spi_HWUnitType Spi_Ipw_au8FlexioHWUnitMapping[FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8];
+#endif
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/*==================================================================================================
+*                                   LOCAL FUNCTION PROTOTYPES 
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+static void Spi_Ipw_CallbackLpspi(uint8 Instance, Lpspi_Ip_EventType Event);
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+static void Spi_Ipw_CallbackFlexio(uint8 Instance, Flexio_Spi_Ip_EventType Event);
+#endif
+static void Spi_Ipw_EndChannelCallback(uint8 Instance, Spi_Ipw_SupportedIPsType IpType, Spi_JobResultType JobResult);
+#if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+static void Spi_Ipw_SequenceDmaFastTransfer(const Spi_SequenceConfigType *SequenceConfig, uint8 HWUnit, uint32 SpiCoreID);
+#endif
+#endif
+
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+static Std_ReturnType Spi_Ipw_SyncTransmitProcess
+    (
+        const Spi_JobConfigType *JobConfig,
+        const Spi_ChannelConfigType *ChannelConfig,
+        Spi_DataBufferType *RxBuffer,
+        Spi_DataBufferType *TxBuffer
+    );
+#endif
+/*==================================================================================================
+*                                       LOCAL FUNCTIONS
+==================================================================================================*/
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+static Std_ReturnType Spi_Ipw_SyncTransmitProcess
+    (
+        const Spi_JobConfigType *JobConfig,
+        const Spi_ChannelConfigType *ChannelConfig,
+        Spi_DataBufferType *RxBuffer,
+        Spi_DataBufferType *TxBuffer
+    )
+{
+    Lpspi_Ip_StatusType Lpspi_spiStatus = LPSPI_IP_STATUS_SUCCESS;
+    const Lpspi_Ip_ExternalDeviceType* LpspiExternalDevice;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    Flexio_Spi_Ip_StatusType Flexio_spiStatus = FLEXIO_SPI_IP_STATUS_SUCCESS;
+    const Flexio_Spi_Ip_ExternalDeviceType* Flexio_SpiExternalDevice;
+#endif
+    Std_ReturnType Ipw_Status = (Std_ReturnType)E_OK;
+    Spi_NumberOfDataType NumberOfBytes;
+    Spi_Ipw_SupportedIPsType IpType = JobConfig->ExternalDeviceConfig->ExDeviceConfig->IpType;
+#if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+    Lpspi_Ip_HalfDuplexType HalfDuplexMode;
+    boolean HalfDuplexModeSupport = TRUE;
+    Spi_DataBufferType *Buffer;
+
+    if (SPI_HALF_DUPLEX_TRANSMIT == ChannelConfig->HalfDuplexMode)
+    {
+        HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_TRANSMIT;
+        Buffer = TxBuffer;
+    }
+    else if (SPI_HALF_DUPLEX_RECEIVE == ChannelConfig->HalfDuplexMode)
+    {
+        HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_RECEIVE;
+        Buffer = RxBuffer;
+    }
+    else
+    {
+        HalfDuplexMode = LPSPI_IP_FULL_DUPLEX;
+        HalfDuplexModeSupport = FALSE;
+    }
+#endif
+    
+    NumberOfBytes = ChannelConfig->ChannelState->Length;
+    if (SPI_OVER_LPSPI == IpType)
+    {
+        LpspiExternalDevice = JobConfig->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.LpspiExternalDeviceConfig;
+        Lpspi_spiStatus = Lpspi_Ip_UpdateDefaultTransmitData(LpspiExternalDevice, ChannelConfig->DefaultTransmitValue);
+        if (LPSPI_IP_STATUS_SUCCESS == Lpspi_spiStatus)
+        {
+            Lpspi_spiStatus = Lpspi_Ip_UpdateFrameSize(LpspiExternalDevice, ChannelConfig->FrameSize);
+            if (LPSPI_IP_STATUS_SUCCESS == Lpspi_spiStatus)
+            {
+                Lpspi_spiStatus = Lpspi_Ip_UpdateLsb(LpspiExternalDevice, ChannelConfig->Lsb);
+                if (LPSPI_IP_STATUS_SUCCESS == Lpspi_spiStatus)
+                {
+                    #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                    if(HalfDuplexModeSupport)
+                    {
+                        Lpspi_spiStatus = Lpspi_Ip_SyncTransmitHalfDuplex(LpspiExternalDevice, Buffer, NumberOfBytes, HalfDuplexMode, SPI_TIMEOUT_COUNTER);
+                    }
+                    else
+                    #endif
+                    {
+                        Lpspi_spiStatus = Lpspi_Ip_SyncTransmit(LpspiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, SPI_TIMEOUT_COUNTER);
+                    }
+                }
+            }
+        }
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        Flexio_SpiExternalDevice = JobConfig->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.Flexio_SpiExternalDeviceConfig;
+        Flexio_spiStatus = Flexio_Spi_Ip_UpdateDefaultTransmitData(Flexio_SpiExternalDevice, ChannelConfig->DefaultTransmitValue);
+        if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_spiStatus)
+        {
+            Flexio_spiStatus = Flexio_Spi_Ip_UpdateFrameSize(Flexio_SpiExternalDevice, ChannelConfig->FrameSize);
+            if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_spiStatus)
+            {
+                Flexio_spiStatus = Flexio_Spi_Ip_UpdateLsb(Flexio_SpiExternalDevice, ChannelConfig->Lsb);
+                if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_spiStatus)
+                {
+                    Flexio_spiStatus = Flexio_Spi_Ip_SyncTransmit(Flexio_SpiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, SPI_TIMEOUT_COUNTER);
+                }
+            }
+        }
+    }
+    if( (LPSPI_IP_STATUS_SUCCESS != Lpspi_spiStatus) || (FLEXIO_SPI_IP_STATUS_SUCCESS != Flexio_spiStatus))
+#else
+    if(LPSPI_IP_STATUS_SUCCESS != Lpspi_spiStatus)
+#endif /*(SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)*/
+    {
+        Ipw_Status = (Std_ReturnType)E_NOT_OK;
+    }
+    return Ipw_Status;
+}
+#endif
+/*==================================================================================================
+*                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+/* Spi_Ipw_Init */
+void Spi_Ipw_Init(const Spi_HWUnitType HWUnitId, const Spi_HWUnitConfigType *HWUnit)
+{
+    if (SPI_OVER_LPSPI == HWUnit->IpType)
+    {
+        Spi_Ipw_au8LpspiHWUnitMapping[HWUnit->Instance] = HWUnitId;
+        (void)Lpspi_Ip_Init(HWUnit->IpConfig.LpspiIpConfig);
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        Spi_Ipw_au8FlexioHWUnitMapping[HWUnit->Instance] = HWUnitId;
+        (void)Flexio_Spi_Ip_Init(HWUnit->IpConfig.FlexioSpiIpConfig);
+    }
+#endif
+}
+
+/* Spi_Ipw_DeInit */
+void Spi_Ipw_DeInit(Spi_HWUnitType HWUnit, uint32 SpiCoreID)
+{
+    if (SPI_OVER_LPSPI == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IpType)
+    {
+        (void)Lpspi_Ip_DeInit(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance);
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        (void)Flexio_Spi_Ip_DeInit(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance);
+    }
+#endif
+}
+
+/* Spi_Ipw_SyncTransmit */
+#if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) )
+Std_ReturnType Spi_Ipw_SyncTransmit(const Spi_JobConfigType *JobConfig, uint32 SpiCoreID)
+{
+
+    Std_ReturnType Ipw_Status = (Std_ReturnType)E_OK;
+    Spi_DataBufferType *RxBuffer;
+    Spi_DataBufferType *TxBuffer;
+    const Spi_ChannelConfigType *ChannelConfig;
+    const Spi_ChannelConfigType *NextChannelConfig;
+    Spi_ChannelType ChannelID;
+    Spi_ChannelType NumChannelsInJob;
+    Spi_ChannelType ChannelIndex;
+    Spi_Ipw_SupportedIPsType IpType = JobConfig->ExternalDeviceConfig->ExDeviceConfig->IpType;
+    
+    NumChannelsInJob = JobConfig->NumChannels;
+    for (ChannelIndex = (Spi_ChannelType)0; ChannelIndex < NumChannelsInJob; ChannelIndex++)
+    {
+        ChannelID = JobConfig->ChannelIndexList[ChannelIndex];
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[ChannelID].ChannelCfg;
+        RxBuffer = ChannelConfig->BufferDescriptor->BufferRX;
+        if(0u != (ChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+        {
+            TxBuffer = NULL_PTR;
+        }
+        else
+        {
+            TxBuffer = ChannelConfig->BufferDescriptor->BufferTX;
+        }
+        
+        if (SPI_OVER_LPSPI == IpType)
+        {
+            if(ChannelIndex == (NumChannelsInJob - 1u))
+            {
+                /* Clear CS after current channel */
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->KeepCs = FALSE;
+            }
+            else
+            {
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->KeepCs = TRUE;
+                /* update data for next transfer */
+                NextChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[JobConfig->ChannelIndexList[ChannelIndex + 1u]].ChannelCfg;
+                if(0u != (NextChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+                {
+                    Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->TxBufferNext = NULL_PTR;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->TxBufferNext = NextChannelConfig->BufferDescriptor->BufferTX;
+                }
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->FrameSizeNext = NextChannelConfig->FrameSize;
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->LsbNext = NextChannelConfig->Lsb;
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->DefaultDataNext = NextChannelConfig->DefaultTransmitValue;
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->LengthNext = NextChannelConfig->ChannelState->Length;
+                #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                /* Get mode of next channel */
+                if (SPI_HALF_DUPLEX_RECEIVE == NextChannelConfig->HalfDuplexMode)
+                {
+                    Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->NextChannelIsRX = TRUE;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->NextChannelIsRX = FALSE;
+                }
+                #endif
+            }
+            
+            if(0u == ChannelIndex)
+            {
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->FirstCmd = TRUE;
+            }
+            else
+            {
+                Lpspi_Ip_apxStateStructureArray[JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance]->FirstCmd = FALSE;
+            }
+        }
+        Ipw_Status = Spi_Ipw_SyncTransmitProcess(JobConfig, ChannelConfig, RxBuffer, TxBuffer);
+    }
+    return Ipw_Status;
+}
+#endif /* #if ( (SPI_LEVEL_DELIVERED == LEVEL2) || (SPI_LEVEL_DELIVERED == LEVEL0) ) */
+
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/* Spi_Ipw_IrqPoll */
+void Spi_Ipw_IrqPoll(Spi_HWUnitType HWUnit, uint32 SpiCoreID)
+{
+    if (SPI_OVER_LPSPI == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IpType)
+    {
+        if(LPSPI_IP_POLLING == Lpspi_Ip_apxStateStructureArray[Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance]->TransferMode)
+        {
+            Lpspi_Ip_ManageBuffers(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance);
+        }
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        if(FLEXIO_SPI_IP_POLLING == Flexio_Spi_Ip_apxStateStructureArray[Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance]->TransferMode)
+        {
+            Flexio_Spi_Ip_ManageBuffers(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance);
+        }
+    }
+#endif
+}
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/* Spi_Ipw_IrqConfig */
+void Spi_Ipw_IrqConfig(Spi_HWUnitType HWUnit, Spi_AsyncModeType Mode, uint32 SpiCoreID)
+{
+    Lpspi_Ip_StatusType Lpspi_Ip_Status = LPSPI_IP_STATUS_SUCCESS;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    Flexio_Spi_Ip_StatusType Flexio_Spi_Ip_Status = FLEXIO_SPI_IP_STATUS_SUCCESS;
+#endif
+    
+    if (SPI_OVER_LPSPI == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IpType)
+    {
+        if (SPI_POLLING_MODE == Mode)
+        {
+            Lpspi_Ip_Status = Lpspi_Ip_UpdateTransferMode(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance, LPSPI_IP_POLLING);
+        }
+        else
+        {
+            Lpspi_Ip_Status = Lpspi_Ip_UpdateTransferMode(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance, LPSPI_IP_INTERRUPT);
+        }
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        if (SPI_POLLING_MODE == Mode)
+        {
+            Flexio_Spi_Ip_Status = Flexio_Spi_Ip_UpdateTransferMode(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance, FLEXIO_SPI_IP_POLLING);
+        }
+        else
+        {
+            Flexio_Spi_Ip_Status = Flexio_Spi_Ip_UpdateTransferMode(Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->Instance, FLEXIO_SPI_IP_INTERRUPT);
+        }
+    }
+    (void) Flexio_Spi_Ip_Status;
+#endif
+    /* HLD do not require return value. This code to avoid misra violation */
+    (void) Lpspi_Ip_Status;
+}
+#endif
+
+#if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+/* Function to manage switching between channels. */
+static void Spi_Ipw_EndChannelCallback(uint8 Instance, Spi_Ipw_SupportedIPsType IpType, Spi_JobResultType JobResult)
+{
+    uint32 SpiCoreID;
+    Spi_HWUnitType HwUnit = 0;
+    Spi_ChannelType ChannelIndex, NumberOfChannels, ChannelNumber;
+    Spi_JobType Job;
+    const Lpspi_Ip_ExternalDeviceType *LpspiExternalDevice;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    const Flexio_Spi_Ip_ExternalDeviceType *Flexio_SpiExternalDevice;
+    Flexio_Spi_Ip_StatusType Flexio_SpiStatus;
+#endif
+    const Spi_ChannelConfigType *ChannelConfig;
+    const Spi_ChannelConfigType *NextChannelConfig;
+    Spi_NumberOfDataType NumberOfBytes;
+    Spi_DataBufferType *RxBuffer;
+    Spi_DataBufferType *TxBuffer;
+    /* Get current coreID */
+    SpiCoreID = Spi_GetCoreID;
+    Lpspi_Ip_StatusType LpspiStatus;
+#if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+    Lpspi_Ip_HalfDuplexType HalfDuplexMode;
+    boolean HalfDuplexModeSupport = TRUE;
+    Spi_DataBufferType *Buffer;
+#endif
+
+    if (SPI_OVER_LPSPI == IpType)
+    {
+        HwUnit = Spi_Ipw_au8LpspiHWUnitMapping[Instance];
+    }
+    #if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        HwUnit = Spi_Ipw_au8FlexioHWUnitMapping[Instance];
+    }
+    #endif
+
+    ChannelIndex = Spi_aSpiHWUnitQueueArray[HwUnit].Channel;
+    Job = Spi_aSpiHWUnitQueueArray[HwUnit].Job;
+    NumberOfChannels = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg->NumChannels;
+
+    if (((ChannelIndex + 1u) < NumberOfChannels) && (SPI_JOB_OK == JobResult))
+    {
+        Spi_aSpiHWUnitQueueArray[HwUnit].Channel++;
+        ChannelIndex++;
+        ChannelNumber = (Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig)[Job].JobCfg->ChannelIndexList[ChannelIndex];
+        ChannelConfig = (Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig)[ChannelNumber].ChannelCfg;
+        NumberOfBytes = ChannelConfig->ChannelState->Length;
+        RxBuffer = ChannelConfig->BufferDescriptor->BufferRX;
+        TxBuffer = ChannelConfig->BufferDescriptor->BufferTX;
+        if (SPI_OVER_LPSPI == IpType)
+        {
+#if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+            if (SPI_HALF_DUPLEX_TRANSMIT == ChannelConfig->HalfDuplexMode)
+            {
+                HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_TRANSMIT;
+                Buffer = TxBuffer;
+            }
+            else if (SPI_HALF_DUPLEX_RECEIVE == ChannelConfig->HalfDuplexMode)
+            {
+                HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_RECEIVE;
+                Buffer = RxBuffer;
+            }
+            else
+            {
+                HalfDuplexMode = LPSPI_IP_FULL_DUPLEX;
+                HalfDuplexModeSupport = FALSE;
+            }
+#endif
+            LpspiExternalDevice = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.LpspiExternalDeviceConfig;
+            if(ChannelIndex == (NumberOfChannels - 1u))
+            {
+                /* Clear CS after current channel */
+                Lpspi_Ip_apxStateStructureArray[Instance]->KeepCs = FALSE;
+            }
+            else
+            {
+                Lpspi_Ip_apxStateStructureArray[Instance]->KeepCs = TRUE;
+                /* update data for next transfer */
+                NextChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg->ChannelIndexList[ChannelIndex + 1u]].ChannelCfg;
+                if(0u != (NextChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->TxBufferNext = NULL_PTR;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->TxBufferNext = NextChannelConfig->BufferDescriptor->BufferTX;
+                }
+                Lpspi_Ip_apxStateStructureArray[Instance]->FrameSizeNext = NextChannelConfig->FrameSize;
+                Lpspi_Ip_apxStateStructureArray[Instance]->LsbNext = NextChannelConfig->Lsb;
+                Lpspi_Ip_apxStateStructureArray[Instance]->DefaultDataNext = NextChannelConfig->DefaultTransmitValue;
+                Lpspi_Ip_apxStateStructureArray[Instance]->LengthNext = NextChannelConfig->ChannelState->Length;
+                #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                /* Get mode of next channel */
+                if (SPI_HALF_DUPLEX_RECEIVE == NextChannelConfig->HalfDuplexMode)
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->NextChannelIsRX = TRUE;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->NextChannelIsRX = FALSE;
+                }
+                #endif
+            }
+            Lpspi_Ip_apxStateStructureArray[Instance]->FirstCmd = FALSE;
+            
+            /* update default data */
+            LpspiStatus = Lpspi_Ip_UpdateDefaultTransmitData(LpspiExternalDevice, ChannelConfig->DefaultTransmitValue);
+            if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+            {
+                LpspiStatus = Lpspi_Ip_UpdateFrameSize(LpspiExternalDevice, ChannelConfig->FrameSize);
+            }
+            if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+            {
+                LpspiStatus = Lpspi_Ip_UpdateLsb(LpspiExternalDevice, ChannelConfig->Lsb);
+            }
+            if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+            {
+                #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                if(HalfDuplexModeSupport)
+                {
+                    (void)Lpspi_Ip_AsyncTransmitHalfDuplex(LpspiExternalDevice, Buffer, NumberOfBytes, HalfDuplexMode, &Spi_Ipw_CallbackLpspi);    
+                }
+                else
+                #endif
+                {
+                    (void)Lpspi_Ip_AsyncTransmit(LpspiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, &Spi_Ipw_CallbackLpspi); 
+                }
+            }
+        }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+        else
+        {
+            Flexio_SpiExternalDevice = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.Flexio_SpiExternalDeviceConfig;
+            
+            Flexio_SpiStatus = Flexio_Spi_Ip_UpdateDefaultTransmitData(Flexio_SpiExternalDevice, ChannelConfig->DefaultTransmitValue);
+            if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+            {
+                Flexio_SpiStatus = Flexio_Spi_Ip_UpdateFrameSize(Flexio_SpiExternalDevice, ChannelConfig->FrameSize);
+            }
+            if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+            {
+                Flexio_SpiStatus = Flexio_Spi_Ip_UpdateLsb(Flexio_SpiExternalDevice, ChannelConfig->Lsb);
+            }
+            if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+            {
+                (void)Flexio_Spi_Ip_AsyncTransmit(Flexio_SpiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, &Spi_Ipw_CallbackFlexio);
+            }
+        }
+#endif
+    }
+    else
+    {
+        Spi_JobTransferFinished(Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Job].JobCfg, JobResult);
+    }
+ }
+
+/* LPSPI end of channel callback. */
+static void Spi_Ipw_CallbackLpspi(uint8 Instance, Lpspi_Ip_EventType Event)
+{
+    Spi_Ipw_SupportedIPsType IpType = SPI_OVER_LPSPI;
+    if (Event != LPSPI_IP_EVENT_END_TRANSFER)
+    {
+        Spi_Ipw_EndChannelCallback(Instance, IpType, SPI_JOB_FAILED);
+    }
+    else
+    {
+        Spi_Ipw_EndChannelCallback(Instance, IpType, SPI_JOB_OK);
+    }
+}
+
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+/* FLEXIO_SPI end of channel callback. */
+static void Spi_Ipw_CallbackFlexio(uint8 Instance, Flexio_Spi_Ip_EventType Event)
+{
+    Spi_Ipw_SupportedIPsType IpType = SPI_OVER_FLEXIO;
+    if (Event != FLEXIO_SPI_IP_EVENT_END_TRANSFER)
+    {
+        Spi_Ipw_EndChannelCallback(Instance, IpType, SPI_JOB_FAILED);
+    }
+    else
+    {
+        Spi_Ipw_EndChannelCallback(Instance, IpType, SPI_JOB_OK);
+    }
+}
+#endif
+
+#if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+static void Spi_Ipw_SequenceDmaFastTransfer(const Spi_SequenceConfigType *SequenceConfig, uint8 HWUnit, uint32 SpiCoreID)
+{
+    Lpspi_Ip_FastTransferType *pDmaFastTransferCfg = Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[HWUnit].PhyUnitConfig->IpConfig.LpspiFastTransferCfg;
+    uint8 TransferCount = 0u;
+    Spi_JobType JobsCount;
+    const Spi_JobType *JobIndexList;
+    const Spi_JobConfigType *JobConfig;
+    const Spi_ChannelConfigType *ChannelConfig;
+    Spi_ChannelType ChannelID;
+    Spi_ChannelType NumChannelsInJob;
+    Spi_ChannelType ChannelIndex;
+
+    /* Get the number of Jobs in the sequence */
+    JobsCount = SequenceConfig->NumJobs;
+    JobIndexList = SequenceConfig->JobIndexList;
+    while (0u < JobsCount)
+    {
+        /* Set the Job status as pending */
+        Spi_axSpiJobState[*JobIndexList].Result = SPI_JOB_PENDING;
+        JobConfig = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[*JobIndexList].JobCfg;
+        NumChannelsInJob = JobConfig->NumChannels;
+        for (ChannelIndex = (Spi_ChannelType)0; ChannelIndex < NumChannelsInJob; ChannelIndex++)
+        {
+            ChannelID = JobConfig->ChannelIndexList[ChannelIndex];
+            ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[ChannelID].ChannelCfg;
+            pDmaFastTransferCfg[TransferCount].Length = ChannelConfig->ChannelState->Length;
+            pDmaFastTransferCfg[TransferCount].RxBuffer = ChannelConfig->BufferDescriptor->BufferRX;
+            if(0u != (ChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+            {
+                pDmaFastTransferCfg[TransferCount].TxBuffer = NULL_PTR;
+            }
+            else
+            {
+                pDmaFastTransferCfg[TransferCount].TxBuffer = ChannelConfig->BufferDescriptor->BufferTX;
+            }
+            
+            if (SPI_OVER_LPSPI == JobConfig->ExternalDeviceConfig->ExDeviceConfig->IpType)
+            {
+                pDmaFastTransferCfg[TransferCount].ExternalDevice = JobConfig->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.LpspiExternalDeviceConfig;
+                if(ChannelIndex == (NumChannelsInJob - 1u))
+                {
+                    /* Clear CS after current channel */
+                    pDmaFastTransferCfg[TransferCount].KeepCs = FALSE;
+                }
+                else
+                {
+                    pDmaFastTransferCfg[TransferCount].KeepCs = TRUE;
+                }
+                /* For Dma Fast transfer, All transfers use the same HWUnit and in Master Mode only.
+                Some parameters such as Baudrate, Delays timming SpiTimeClk2Cs, SpiTimeCs2Clk, SpiTimeCs2Cs, SpiDataWidth, SpiTransferStart configuration 
+                must be the same between transfers. So, make sure they are configured the same in each External Device allocated to Jobs for Dma Fast Transfers. */
+                /* update default data */
+                pDmaFastTransferCfg[TransferCount].DefaultData = ChannelConfig->DefaultTransmitValue;
+                (void)Lpspi_Ip_UpdateFrameSize(pDmaFastTransferCfg[TransferCount].ExternalDevice, ChannelConfig->FrameSize);
+                (void)Lpspi_Ip_UpdateLsb(pDmaFastTransferCfg[TransferCount].ExternalDevice, ChannelConfig->Lsb);
+            }
+            else
+            {
+                /* Do nothing */
+            }
+            TransferCount++;
+        }
+        /* iterate to next Job in sequence */
+        JobIndexList++;
+        JobsCount--;
+    } /* while (JobsCount > 0u) */
+
+    /* Because of all Channels and all Jobs are transferred successfully when Spi_Ipw_CallbackLpspi called.
+    So, remaining of Channels in current Job must set to 0, this will lead to Spi_JobTransferFinished() called when Spi_Ipw_CallbackLpspi called.
+    And Spi_JobTransferFinished() will set remainning of Job to 0 and set all Jobs result to SPI_JOB_OK, unlock all Jobs for this Dma Fast Sequence. */
+    Spi_aSpiHWUnitQueueArray[HWUnit].Channel = Spi_apxSpiConfigPtr[SpiCoreID]->JobConfig[Spi_aSpiHWUnitQueueArray[HWUnit].Job].JobCfg->NumChannels - 1u;
+
+    (void)Lpspi_Ip_AsyncTransmitFast(pDmaFastTransferCfg, TransferCount, &Spi_Ipw_CallbackLpspi);
+}
+#endif
+
+/* Triggers first channel of the Job. */
+void Spi_Ipw_JobTransfer(const Spi_JobConfigType *JobConfig)
+{
+    const Lpspi_Ip_ExternalDeviceType *LpspiExternalDevice;
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    const Flexio_Spi_Ip_ExternalDeviceType *Flexio_SpiExternalDevice;
+    Flexio_Spi_Ip_StatusType Flexio_SpiStatus;
+#endif
+    uint8 Instance;
+    const Spi_ChannelConfigType *ChannelConfig;
+    const Spi_ChannelConfigType *NextChannelConfig;
+    Spi_NumberOfDataType NumberOfBytes;
+    Spi_DataBufferType *RxBuffer;
+    Spi_DataBufferType *TxBuffer;
+    uint32 SpiCoreID;
+    Lpspi_Ip_StatusType LpspiStatus;
+#if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+    const Spi_SequenceConfigType *SequenceConfig = JobConfig->JobState->AsyncCrtSequenceState->Sequence;
+#endif
+#if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)    
+    Lpspi_Ip_HalfDuplexType HalfDuplexMode;
+    boolean HalfDuplexModeSupport = TRUE;
+    Spi_DataBufferType *Buffer;
+#endif
+    
+    /* get core ID */
+    SpiCoreID = Spi_GetCoreID;
+    /* Perform Job StartNotification (if there is one) */
+    if (NULL_PTR != JobConfig->StartNotification)
+    {
+        JobConfig->StartNotification();
+    }
+    else
+    {
+        /* Do nothing */
+    }
+
+    #if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+    if(TRUE == SequenceConfig->EnableDmaFastTransfer)
+    {
+        Spi_Ipw_SequenceDmaFastTransfer(SequenceConfig, JobConfig->HWUnit, SpiCoreID);
+    }
+    else
+    #endif
+    {
+        #if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+        Flexio_SpiExternalDevice = JobConfig->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.Flexio_SpiExternalDeviceConfig;
+        #endif
+        LpspiExternalDevice = JobConfig->ExternalDeviceConfig->ExDeviceConfig->ExternalDeviceConfig.LpspiExternalDeviceConfig;
+        Instance = JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance;
+        ChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[JobConfig->ChannelIndexList[0u]].ChannelCfg;
+        NumberOfBytes = ChannelConfig->ChannelState->Length;
+        RxBuffer = ChannelConfig->BufferDescriptor->BufferRX;
+        if(0u != (ChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+        {
+            TxBuffer = NULL_PTR;
+        }
+        else
+        {
+            TxBuffer = ChannelConfig->BufferDescriptor->BufferTX;
+        }
+        
+#if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+        if (SPI_HALF_DUPLEX_TRANSMIT == ChannelConfig->HalfDuplexMode)
+        {
+            HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_TRANSMIT;
+            Buffer = TxBuffer;
+        }
+        else if (SPI_HALF_DUPLEX_RECEIVE == ChannelConfig->HalfDuplexMode)
+        {
+            HalfDuplexMode = LPSPI_IP_HALF_DUPLEX_RECEIVE;
+            Buffer = RxBuffer;
+        }
+        else
+        {
+            HalfDuplexMode = LPSPI_IP_FULL_DUPLEX;
+            HalfDuplexModeSupport = FALSE;
+        }
+#endif
+        if (SPI_OVER_LPSPI == Spi_apxSpiConfigPtr[SpiCoreID]->HWUnitConfig[JobConfig->HWUnit].PhyUnitConfig->IpType)
+        {
+            if (1u == JobConfig->NumChannels)
+            {
+                /* Clear CS after current channel */
+                Lpspi_Ip_apxStateStructureArray[Instance]->KeepCs = FALSE;
+            }
+            else
+            {
+                Lpspi_Ip_apxStateStructureArray[Instance]->KeepCs = TRUE;
+                /* update data for next transfer */
+                NextChannelConfig = Spi_apxSpiConfigPtr[SpiCoreID]->ChannelConfig[JobConfig->ChannelIndexList[1u]].ChannelCfg;
+                if(0u != (NextChannelConfig->ChannelState->Flags & SPI_CHANNEL_FLAG_TX_DEFAULT_U8))
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->TxBufferNext = NULL_PTR;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->TxBufferNext = NextChannelConfig->BufferDescriptor->BufferTX;
+                }
+                Lpspi_Ip_apxStateStructureArray[Instance]->FrameSizeNext = NextChannelConfig->FrameSize;
+                Lpspi_Ip_apxStateStructureArray[Instance]->LsbNext = NextChannelConfig->Lsb;
+                Lpspi_Ip_apxStateStructureArray[Instance]->DefaultDataNext = NextChannelConfig->DefaultTransmitValue;
+                Lpspi_Ip_apxStateStructureArray[Instance]->LengthNext = NextChannelConfig->ChannelState->Length;
+                #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                /* Get mode of next channel */
+                if (SPI_HALF_DUPLEX_RECEIVE == NextChannelConfig->HalfDuplexMode)
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->NextChannelIsRX = TRUE;
+                }
+                else
+                {
+                    Lpspi_Ip_apxStateStructureArray[Instance]->NextChannelIsRX = FALSE;
+                }
+                #endif
+            }
+            Lpspi_Ip_apxStateStructureArray[Instance]->FirstCmd = TRUE;
+            /* update default data */
+            LpspiStatus = Lpspi_Ip_UpdateDefaultTransmitData(LpspiExternalDevice, ChannelConfig->DefaultTransmitValue);
+            if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+            {
+                LpspiStatus = Lpspi_Ip_UpdateFrameSize(LpspiExternalDevice, ChannelConfig->FrameSize);
+                if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+                {
+                    LpspiStatus = Lpspi_Ip_UpdateLsb(LpspiExternalDevice, ChannelConfig->Lsb);
+                    if (LPSPI_IP_STATUS_SUCCESS == LpspiStatus)
+                    {
+                        #if (STD_ON == SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT)
+                        if (HalfDuplexModeSupport)
+                        {
+                            (void)Lpspi_Ip_AsyncTransmitHalfDuplex(LpspiExternalDevice, Buffer, NumberOfBytes, HalfDuplexMode, &Spi_Ipw_CallbackLpspi);
+                        }
+                        else
+                        #endif
+                        {
+                            (void)Lpspi_Ip_AsyncTransmit(LpspiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, &Spi_Ipw_CallbackLpspi); 
+                        }
+                    }
+                }
+            }
+        }
+        #if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+        else
+        {
+            /* Mark for the first channel */
+            Flexio_Spi_Ip_apxStateStructureArray[Instance]->FirstChannel = TRUE;
+            /* update default data */
+            Flexio_SpiStatus = Flexio_Spi_Ip_UpdateDefaultTransmitData(Flexio_SpiExternalDevice, ChannelConfig->DefaultTransmitValue);
+            if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+            {
+                 Flexio_SpiStatus = Flexio_Spi_Ip_UpdateFrameSize(Flexio_SpiExternalDevice, ChannelConfig->FrameSize);
+                 if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+                 {
+                     Flexio_SpiStatus = Flexio_Spi_Ip_UpdateLsb(Flexio_SpiExternalDevice, ChannelConfig->Lsb);
+                     if (FLEXIO_SPI_IP_STATUS_SUCCESS == Flexio_SpiStatus)
+                     {
+                         Flexio_SpiStatus = Flexio_Spi_Ip_AsyncTransmit(Flexio_SpiExternalDevice, TxBuffer, RxBuffer, NumberOfBytes, &Spi_Ipw_CallbackFlexio);
+                         /* avoid misra violation */
+                         (void)Flexio_SpiStatus;
+                     }
+                 }
+            }
+        }
+        #endif /*(SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)*/
+    }
+}
+#endif
+
+#if ((SPI_SLAVE_SUPPORT == STD_ON) && (SPI_CANCEL_API == STD_ON))
+    #if ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2))
+void Spi_Ipw_SlaveCancel(const Spi_JobConfigType *JobConfig)
+{
+    boolean SlaveMode;
+    if (SPI_OVER_LPSPI == JobConfig->ExternalDeviceConfig->ExDeviceConfig->IpType)
+    {
+#if (LPSPI_IP_SLAVE_SUPPORT == STD_ON)
+        SlaveMode = Spi_apxSpiConfigPtr[Spi_GetCoreID]->HWUnitConfig[JobConfig->HWUnit].PhyUnitConfig->IpConfig.LpspiIpConfig->SlaveMode;
+        if(TRUE == SlaveMode)
+        {
+            Lpspi_Ip_Cancel(JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance);
+            Spi_JobTransferFinished(JobConfig, SPI_JOB_FAILED);
+        }
+#endif
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+#if (FLEXIO_SPI_IP_SLAVE_SUPPORT == STD_ON)
+        SlaveMode = Spi_apxSpiConfigPtr[Spi_GetCoreID]->HWUnitConfig[JobConfig->HWUnit].PhyUnitConfig->IpConfig.FlexioSpiIpConfig->SlaveMode;
+        if(TRUE == SlaveMode)
+        {
+            Flexio_Spi_Ip_Cancel(JobConfig->ExternalDeviceConfig->ExDeviceConfig->Instance);
+            Spi_JobTransferFinished(JobConfig, SPI_JOB_FAILED);
+        }
+#endif
+    }
+#endif
+}
+    #endif
+#endif
+
+#if (SPI_DUAL_CLOCK_MODE == STD_ON)
+void Spi_Ipw_SetClockMode(Spi_DualClockModeType ClockMode, const Spi_HWUnitConfigType * HWUnitConfig)
+{
+    if (SPI_OVER_LPSPI == HWUnitConfig->IpType)
+    {
+        (void)Lpspi_Ip_SetClockMode(HWUnitConfig->Instance, (Lpspi_Ip_DualClockModeType)ClockMode);
+    }
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+    else
+    {
+        (void)Flexio_Spi_Ip_SetClockMode(HWUnitConfig->Instance, (Flexio_Spi_Ip_DualClockModeType)ClockMode);
+    }
+#endif
+}
+#endif
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+/** @} */

S32K146_4G.mex

@@ -16,9 +16,10 @@
       <update_include_paths>true</update_include_paths>
    </preferences>
    <tools>
-      <pins name="Pins" version="6.0" enabled="true" update_project_code="true">
+      <pins name="Pins" version="10.0" enabled="true" update_project_code="true">
          <pins_profile>
             <processor_version>0.0.0</processor_version>
+            <power_domains/>
          </pins_profile>
          <functions_list>
             <function name="BOARD_InitPins">
@@ -32,7 +33,7 @@
             </function>
          </functions_list>
       </pins>
-      <clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
+      <clocks name="Clocks" version="8.0" enabled="true" update_project_code="true">
          <generated_project_files>
             <file path="board/Clock_Ip_Cfg.c" update_enabled="true"/>
             <file path="board/Clock_Ip_Cfg.h" update_enabled="true"/>
@@ -196,7 +197,39 @@
             <processor_version>N/A</processor_version>
          </quadspi_profile>
       </quadspi>
-      <periphs name="Peripherals" version="6.0" enabled="true" update_project_code="true">
+      <periphs name="Peripherals" version="10.0" enabled="true" update_project_code="true">
+         <dependencies>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="工具链/IDE工程中未找到osif。工程不会被编译！" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="工具链/IDE工程不支持osif版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">1.0.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.port_ip" description="工具链/IDE工程中未找到port_ip。工程不会被编译！" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.port_ip" description="工具链/IDE工程不支持port_ip版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">1.0.0</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.spi" description="工具链/IDE工程中未找到Spi。工程不会被编译！" problem_level="2" source="Peripherals">
+               <feature name="enabled" evaluation="equal">
+                  <data type="Boolean">true</data>
+               </feature>
+            </dependency>
+            <dependency resourceType="SWComponent" resourceId="platform.driver.spi" description="工具链/IDE工程不支持Spi版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
+               <feature name="version" evaluation="equivalent">
+                  <data type="Version">1.0.0</data>
+               </feature>
+            </dependency>
+         </dependencies>
          <peripherals_profile>
             <processor_version>0.0.0</processor_version>
          </peripherals_profile>
@@ -226,6 +259,168 @@
                         </struct>
                      </config_set>
                   </instance>
+                  <instance name="Spi_1" uuid="d52e3268-a692-4da3-9090-3f7ee388dcfe" type="Spi" type_id="Spi" mode="autosar" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
+                     <config_set name="Spi" quick_selection="Default">
+                        <setting name="Name" value="Spi"/>
+                        <struct name="ConfigTimeSupport" quick_selection="Default">
+                           <setting name="POST_BUILD_VARIANT_USED" value="false"/>
+                           <setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
+                        </struct>
+                        <array name="SpiDemEventParameterRefs"/>
+                        <struct name="SpiDriver" quick_selection="Default">
+                           <setting name="Name" value="SpiDriver"/>
+                           <array name="SpiMaxChannel">
+                              <setting name="0" value="0"/>
+                           </array>
+                           <array name="SpiMaxJob">
+                              <setting name="0" value="0"/>
+                           </array>
+                           <array name="SpiMaxSequence">
+                              <setting name="0" value="0"/>
+                           </array>
+                           <array name="SpiChannel">
+                              <struct name="0">
+                                 <setting name="Name" value="SpiChannel_0"/>
+                                 <setting name="SpiChannelId" value="0"/>
+                                 <setting name="SpiChannelType" value="IB"/>
+                                 <setting name="SpiDataWidth" value="8"/>
+                                 <array name="SpiDefaultData">
+                                    <setting name="0" value="1"/>
+                                 </array>
+                                 <setting name="SpiEbMaxLength" value="1"/>
+                                 <setting name="SpiIbNBuffers" value="1"/>
+                                 <setting name="SpiTransferStart" value="LSB"/>
+                                 <setting name="SpiChannelHalfDuplexSupport" value="false"/>
+                                 <setting name="SpiChannelHalfDuplexDirection" value="HALF_DUPLEX_TRANSMIT"/>
+                                 <array name="SpiChannelEcucPartitionRef"/>
+                              </struct>
+                           </array>
+                           <array name="SpiExternalDevice">
+                              <struct name="0">
+                                 <setting name="Name" value="SpiExternalDevice_0"/>
+                                 <setting name="SpiBaudrate" value="100000"/>
+                                 <setting name="SpiCsIdentifier" value="PCS0"/>
+                                 <setting name="SpiCsPolarity" value="LOW"/>
+                                 <array name="SpiCsSelection">
+                                    <setting name="0" value="CS_VIA_PERIPHERAL_ENGINE"/>
+                                 </array>
+                                 <setting name="SpiDataShiftEdge" value="LEADING"/>
+                                 <setting name="SpiEnableCs" value="true"/>
+                                 <setting name="SpiHwUnit" value="CSIB0"/>
+                                 <setting name="SpiShiftClockIdleLevel" value="HIGH"/>
+                                 <setting name="SpiTimeClk2Cs" value="0.000001"/>
+                                 <setting name="SpiTimeCs2Clk" value="0.000001"/>
+                                 <setting name="SpiTimeCs2Cs" value="0.0000064"/>
+                                 <setting name="SpiDeviceHalfDuplexSupport" value="false"/>
+                                 <setting name="SpiTransferWidth" value="TRANSFER_1_BIT"/>
+                                 <setting name="SpiHalfDuplexPinSelect" value="HALF_DUPLEX_SIN"/>
+                                 <setting name="SpiCsContinous" value="TRUE"/>
+                                 <array name="SpiDeviceEcucPartitionRef"/>
+                              </struct>
+                           </array>
+                           <array name="SpiJob">
+                              <struct name="0">
+                                 <setting name="Name" value="SpiJob_0"/>
+                                 <array name="SpiJobEndNotification">
+                                    <setting name="0" value="NULL_PTR"/>
+                                 </array>
+                                 <array name="SpiJobStartNotification">
+                                    <setting name="0" value="NULL_PTR"/>
+                                 </array>
+                                 <setting name="SpiJobId" value="0"/>
+                                 <setting name="SpiJobPriority" value="0"/>
+                                 <setting name="SpiDeviceAssignment" value="/Spi_1/Spi/SpiDriver/SpiExternalDevice_0"/>
+                                 <array name="SpiChannelList">
+                                    <struct name="0">
+                                       <setting name="Name" value="SpiChannelList_0"/>
+                                       <setting name="SpiChannelIndex" value="0"/>
+                                       <setting name="SpiChannelAssignment" value="/Spi_1/Spi/SpiDriver/SpiChannel_0"/>
+                                    </struct>
+                                 </array>
+                              </struct>
+                           </array>
+                           <array name="SpiSequence">
+                              <struct name="0">
+                                 <setting name="Name" value="SpiSequence_0"/>
+                                 <setting name="SpiInterruptibleSequence" value="false"/>
+                                 <array name="SpiSeqEndNotification">
+                                    <setting name="0" value="NULL_PTR"/>
+                                 </array>
+                                 <setting name="SpiSequenceId" value="0"/>
+                                 <setting name="SpiEnableDmaFastTransfer" value="false"/>
+                                 <array name="SpiJobAssignment">
+                                    <setting name="0" value="/Spi_1/Spi/SpiDriver/SpiJob_0"/>
+                                 </array>
+                              </struct>
+                           </array>
+                        </struct>
+                        <struct name="SpiGeneral" quick_selection="Default">
+                           <setting name="Name" value="SpiGeneral"/>
+                           <setting name="SpiMulticoreSupport" value="false"/>
+                           <setting name="SpiCancelApi" value="true"/>
+                           <setting name="SpiChannelBuffersAllowed" value="0"/>
+                           <setting name="SpiDevErrorDetect" value="true"/>
+                           <setting name="SpiHwStatusApi" value="true"/>
+                           <setting name="SpiInterruptibleSeqAllowed" value="false"/>
+                           <setting name="SpiLevelDelivered" value="2"/>
+                           <array name="SpiMainFunctionPeriod">
+                              <setting name="0" value="0.01"/>
+                           </array>
+                           <setting name="SpiSupportConcurrentSyncTransmit" value="false"/>
+                           <setting name="SpiVersionInfoApi" value="true"/>
+                           <setting name="SpiGlobalDmaEnable" value="false"/>
+                           <setting name="SpiFlexioEnable" value="false"/>
+                           <setting name="SpiTimeoutMethod" value="OSIF_COUNTER_DUMMY"/>
+                           <setting name="SpiTransmitTimeout" value="50000"/>
+                           <array name="SpiEcucPartitionRef"/>
+                           <array name="SpiKernelEcucPartitionRef"/>
+                           <array name="SpiPhyUnit">
+                              <struct name="0">
+                                 <setting name="Name" value="SpiPhyUnit_0"/>
+                                 <setting name="SpiPhyUnitMapping" value="LPSPI_0"/>
+                                 <setting name="SpiPinConfiguration" value="0"/>
+                                 <setting name="SpiSamplePoint" value="0"/>
+                                 <setting name="SpiPhyUnitClockRef" value=""/>
+                                 <array name="SpiPhyUnitAlternateClockRef"/>
+                                 <setting name="SpiPhyUnitMode" value="SPI_MASTER"/>
+                                 <setting name="SpiPhyUnitSync" value="true"/>
+                                 <setting name="SpiPhyUnitAsyncUseDma" value="false"/>
+                                 <array name="SpiPhyTxDmaChannel"/>
+                                 <array name="SpiPhyRxDmaChannel"/>
+                                 <array name="SpiMaxDmaFastTransfer"/>
+                                 <array name="SpiFlexioTxAndClkChannelsConfig"/>
+                                 <array name="SpiFlexioRxAndCsChannelsConfig"/>
+                              </struct>
+                           </array>
+                        </struct>
+                        <struct name="SpiPublishedInformation" quick_selection="Default">
+                           <setting name="Name" value="SpiPublishedInformation"/>
+                           <setting name="SpiMaxHwUnit" value="0"/>
+                        </struct>
+                        <struct name="SpiAutosarExt" quick_selection="Default">
+                           <setting name="Name" value="SpiAutosarExt"/>
+                           <setting name="SpiEnableUserModeSupport" value="false"/>
+                           <setting name="SpiEnableDmaFastTransferSupport" value="false"/>
+                           <setting name="SpiHalfDuplexModeSupport" value="false"/>
+                           <setting name="SpiAllowBigSizeCollections" value="false"/>
+                           <setting name="SpiEnableHWUnitAsyncMode" value="true"/>
+                           <setting name="SpiJobStartNotificationEnable" value="false"/>
+                           <setting name="SpiDisableDemReportErrorStatus" value="false"/>
+                        </struct>
+                        <struct name="CommonPublishedInformation" quick_selection="Default">
+                           <setting name="Name" value="CommonPublishedInformation"/>
+                           <setting name="ModuleId" value="83"/>
+                           <setting name="VendorId" value="43"/>
+                           <array name="VendorApiInfix"/>
+                           <setting name="ArReleaseMajorVersion" value="4"/>
+                           <setting name="ArReleaseMinorVersion" value="4"/>
+                           <setting name="ArReleaseRevisionVersion" value="0"/>
+                           <setting name="SwMajorVersion" value="1"/>
+                           <setting name="SwMinorVersion" value="0"/>
+                           <setting name="SwPatchVersion" value="0"/>
+                        </struct>
+                     </config_set>
+                  </instance>
                </instances>
             </functional_group>
          </functional_groups>

generate/include/Dio_Cfg.h

@@ -288,6 +288,38 @@ extern "C" {
 */
 #define  DioConf_DioChannel_PTB4_GPIO_OUT_MCU_RS485_EN ((uint16)0x0024U)
 
+/* ---------- DioPort_C ---------- */
+
+/**
+* @brief          Symbolic name for the port DioPort_C.
+*
+*/
+#define DioConf_DioPort_DioPort_C  ((uint8)0x02U)
+
+
+
+/**
+* @brief          Symbolic name for the channel PTC0_SPI2_SIN_MCU_3D_SDI.
+*
+*/
+#define  DioConf_DioChannel_PTC0_SPI2_SIN_MCU_3D_SDI ((uint16)0x0040U)
+
+
+
+/**
+* @brief          Symbolic name for the channel PTC1_SPI2_SOUT_MCU_3D_SDO.
+*
+*/
+#define  DioConf_DioChannel_PTC1_SPI2_SOUT_MCU_3D_SDO ((uint16)0x0041U)
+
+
+
+/**
+* @brief          Symbolic name for the channel PTC14_SPI2_PCS0_MCU_3D_CS.
+*
+*/
+#define  DioConf_DioChannel_PTC14_SPI2_PCS0_MCU_3D_CS ((uint16)0x004eU)
+
 /* ---------- DioPort_D ---------- */
 
 /**

generate/include/Flexio_Mcl_Ip_Cfg_Defines.h

@@ -39,6 +39,10 @@ extern "C"
 #include "StandardTypes.h"
 #include "BasicTypes.h"
 
+#include "Flexio_Spi_Ip_CfgDefines.h"
+#if defined(SPI_CHANNEL_0_USED) || defined(SPI_CHANNEL_1_USED) || defined(SPI_CHANNEL_2_USED) || defined(SPI_CHANNEL_3_USED)|| defined(SPI_CHANNEL_4_USED) || defined(SPI_CHANNEL_5_USED) || defined(SPI_CHANNEL_6_USED) || defined(SPI_CHANNEL_7_USED)
+    #define USE_SPI_MODULE
+#endif
 #include "Flexio_Uart_Ip_CfgDefines.h"
 #if defined(UART_CHANNEL_0_USED) || defined(UART_CHANNEL_1_USED) || defined(UART_CHANNEL_2_USED) || defined(UART_CHANNEL_3_USED)|| defined(UART_CHANNEL_4_USED) || defined(UART_CHANNEL_5_USED) || defined(UART_CHANNEL_6_USED) || defined(UART_CHANNEL_7_USED)
     #define USE_UART_MODULE

generate/include/Flexio_Spi_Ip_Cfg.h

@@ -0,0 +1,278 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_CFG_H
+#define FLEXIO_SPI_IP_CFG_H
+
+/**
+*   @file     Flexio_Spi_Ip_Cfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            module configuration(s).
+*   @addtogroup FLEXIO_DRIVER_CONFIGURATION  Flexio_Spi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+#include "Mcal.h"
+#include "OsIf.h"
+
+#include "Flexio_Spi_Ip_VS_0_PBcfg.h"
+
+#include "S32K146_FLEXIO.h"
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define FLEXIO_SPI_IP_VENDOR_ID_CFG                       43
+#define FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG        4
+#define FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG        4
+#define FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_CFG     0
+#define FLEXIO_SPI_IP_SW_MAJOR_VERSION_CFG                1
+#define FLEXIO_SPI_IP_SW_MINOR_VERSION_CFG                0
+#define FLEXIO_SPI_IP_SW_PATCH_VERSION_CFG                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG != MCAL_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Flexio_Spi_Ip_Cfg.h and Mcal.h are different"
+    #endif
+
+    /* Check if current file and OsIf header file are of the same Autosar version */
+    #if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG != OSIF_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Flexio_Spi_Ip_Cfg.h and OsIf.h are different"
+    #endif
+#endif
+
+
+
+/* Check if Flexio_Spi_Ip_VS_0_PBcfg header file and Spi configuration header file are of the same vendor */
+#if (FLEXIO_SPI_IP_VS_0_VENDOR_ID_PBCFG != FLEXIO_SPI_IP_VENDOR_ID_CFG)
+    #error "Flexio_Spi_Ip_VS_0_PBcfg.h and Flexio_Spi_Ip_Cfg.h have different vendor IDs"
+#endif
+    /* Check if Flexio_Spi_Ip_VS_0_PBcfg header file and Spi  configuration header file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_CFG))
+#error "AutoSar Version Numbers of Flexio_Spi_Ip_VS_0_PBcfg.h and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+/* Check if Flexio_Spi_Ip_VS_0_PBcfg header file and Spi configuration header file are of the same software version */
+#if ((FLEXIO_SPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG != FLEXIO_SPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_VS_0_SW_MINOR_VERSION_PBCFG != FLEXIO_SPI_IP_SW_MINOR_VERSION_CFG) || \
+     (FLEXIO_SPI_IP_VS_0_SW_PATCH_VERSION_PBCFG != FLEXIO_SPI_IP_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Flexio_Spi_Ip_VS_0_PBcfg.h and Flexio_Spi_Ip_Cfg.h are different"
+#endif
+
+
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/**
+* @brief Flexio SPI supported enable.
+* @details Flexio SPI supported enable. 
+*/
+#define FLEXIO_SPI_IP_ENABLE     (STD_OFF)
+
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+#define FLEXIO_SPI_IP_CONFIG_EXT \
+ FLEXIO_SPI_IP_CONFIG_VS_0_PB \
+
+
+/** @brief Total number of SpiPhyUnit configured. */
+#define FLEXIO_SPI_IP_NUMBER_OF_INSTANCES           (1U)
+
+/** @brief Total number of FLEXIO_SPI HW Unit are supported . */
+#define FLEXIO_SPI_IP_NUMBER_OF_HWUNIT_U8         (uint8)(2U)
+
+/** @brief Total number of Flexio instance. */
+#define FLEXIO_SPI_IP_INSTANCE_COUNT           (FLEXIO_INSTANCE_COUNT)
+
+/** @brief HWUnits enabled/disabled */
+
+#define FLEXIO_SPI_IP_SLAVE_SUPPORT  ((STD_OFF))
+
+
+/**
+* @brief Defines if transfers are made using DMA or FIFO.
+* @details Defines if transfers are made using DMA or FIFO.
+*/
+#define FLEXIO_SPI_IP_DMA_USED     (STD_OFF)
+
+/**
+* @brief If enabled, allows dual MCU clock configuration settings.
+* @details If enabled, allows dual MCU clock configuration settings.
+*/
+#define FLEXIO_SPI_IP_DUAL_CLOCK_MODE  (STD_OFF)
+
+/**
+* @brief Define Timeout Method.
+* @details Define a certain timeout method from OsIf will be used in the driver.
+*/
+#define FLEXIO_SPI_IP_TIMEOUT_METHOD           (OSIF_COUNTER_SYSTEM)
+
+/**
+* @brief          Enable User Mode Support.
+* @details        When SpiAutosarExt/SpiEnableUserModeSupport = TRUE,
+*                 the SPI driver can be executed from both supervisor and user mode.
+*
+* @api
+*/
+#define FLEXIO_SPI_IP_ENABLE_USER_MODE_SUPPORT (STD_OFF)
+
+/**
+* @brief Switches ON or OFF for the detection and reporting of development errors(API parameter checking) at IP level.
+*/
+/** @implements FLEXIO_SPI_IP_DEV_ERROR_DETECT_define  */
+#define FLEXIO_SPI_IP_DEV_ERROR_DETECT     (STD_OFF)
+
+/**
+* @brief Maximum of frame size supported.
+*/
+#define FLEXIO_SPI_IP_FRAMESIZE_MAX_U8                              ((uint8)32U)
+
+/**
+* @brief Maximum of frame size supported.
+*/
+#define FLEXIO_SPI_IP_FRAMESIZE_MIN_U8                              ((uint8)4U)
+
+/** @brief Write to CTRL */
+#define FLEXIO_SPI_IP_CTRL_FLEXEN(x)  FLEXIO_CTRL_FLEXEN(x)
+
+/** @brief Write to  TIMCMP */
+#define FLEXIO_SPI_IP_TIMECMP_BAUDRATE_MASK_U32  ((uint32) 0x00FFu)
+#define FLEXIO_SPI_IP_TIMECMP_FRAMESIZE_MASK_U32 ((uint32) 0xFF00u)
+#define FLEXIO_SPI_IP_TIMCMP_CMP(x)        FLEXIO_TIMCMP_CMP(x)
+
+/** @brief CPOL and CPHA selection */
+#define FLEXIO_SPI_IP_CPOL_LOW_U8          ((uint8) 0U)
+#define FLEXIO_SPI_IP_CPOL_HIGH_U8         ((uint8) 1U)
+#define FLEXIO_SPI_IP_CPHA_LEADING_U8      ((uint8) 0U)
+#define FLEXIO_SPI_IP_CPHA_TRAILING_U8     ((uint8) 1U)
+
+/** @brief Write to  SHIFTCTL */
+#define FLEXIO_SPI_IP_SHIFTCTL_TIMSEL(x)     FLEXIO_SHIFTCTL_TIMSEL(x)
+#define FLEXIO_SPI_IP_SHIFTCTL_PINSEL(x)     FLEXIO_SHIFTCTL_PINSEL(x)
+#define FLEXIO_SPI_IP_SHIFTCTL_PINCFG(x)     FLEXIO_SHIFTCTL_PINCFG(x) 
+#define FLEXIO_SPI_IP_SHIFTCTL_SMOD(x)       FLEXIO_SHIFTCTL_SMOD(x)
+#define FLEXIO_SPI_IP_SHIFTCTL_TIMPOL(x)     FLEXIO_SHIFTCTL_TIMPOL(x)
+
+/** @brief Write to SHIFTCFG */
+#define FLEXIO_SPI_IP_SHIFTCFG_SSTOP(x)      FLEXIO_SHIFTCFG_SSTOP(x)
+#define FLEXIO_SPI_IP_SHIFTCFG_SSTART(x)     FLEXIO_SHIFTCFG_SSTART(x)
+#define FLEXIO_SPI_IP_TIMCFG_TIMDEC(x)       FLEXIO_TIMCFG_TIMDEC(x)
+
+/** @brief Write to TIMCTL  */
+#define FLEXIO_SPI_IP_TIMCTL_PINSEL(x)             FLEXIO_TIMCTL_PINSEL(x)
+#define FLEXIO_SPI_IP_TIMCTL_TRGSEL(x)             FLEXIO_TIMCTL_TRGSEL(x)
+#define FLEXIO_SPI_IP_TIMCTL_TRGSRC(x)             FLEXIO_TIMCTL_TRGSRC(x)
+#define FLEXIO_SPI_IP_TIMCTL_TIMOD(x)              FLEXIO_TIMCTL_TIMOD(x)
+#define FLEXIO_SPI_IP_TIMCTL_TRGPOL(x)             FLEXIO_TIMCTL_TRGPOL(x)
+#define FLEXIO_SPI_IP_TIMCTL_PINPOL(x)             FLEXIO_TIMCTL_PINPOL(x)
+#define FLEXIO_SPI_IP_TIMCTL_PINCFG(x)             FLEXIO_TIMCTL_PINCFG(x)
+#define FLEXIO_SPI_IP_TIMCTL_ONETIM(x)             FLEXIO_TIMCTL_ONETIM(x)
+
+/** @brief Write to TIMCFG  */
+#define FLEXIO_SPI_IP_TIMCFG_TIMOUT(x)             FLEXIO_TIMCFG_TIMOUT(x)
+#define FLEXIO_SPI_IP_TIMCFG_TIMDIS(x)             FLEXIO_TIMCFG_TIMDIS(x)
+#define FLEXIO_SPI_IP_TIMCFG_TIMENA(x)             FLEXIO_TIMCFG_TIMENA(x)
+#define FLEXIO_SPI_IP_TIMCFG_TIMRST(x)             FLEXIO_TIMCFG_TIMRST(x)
+#define FLEXIO_SPI_IP_TIMCFG_DEFAULT_MASTER_VALUE         ((uint32) 0x00000222u)
+#define FLEXIO_SPI_IP_TIMCFG_DEFAULT_SLAVE_CPHA0_VALUE         ((uint32) 0x01200600u)
+#define FLEXIO_SPI_IP_TIMCFG_DEFAULT_SLAVE_CPHA1_VALUE         ((uint32) 0x01206602u)
+
+/** @brief Write to SHIFTSIEN and SHIFTSDEN */
+#define FLEXIO_SPI_IP_SHIFTSIEN_SSIE(x)         FLEXIO_SHIFTSIEN_SSIE(x)
+#define FLEXIO_SPI_IP_SHIFTSDEN_SSDE(x)         FLEXIO_SHIFTSDEN_SSDE(x) 
+
+/**
+* @brief Shifters and Timer index
+*/
+#define FLEXIO_SPI_IP_SHIFTER_0_U8                   ((uint8)0U)
+#define FLEXIO_SPI_IP_SHIFTER_1_U8                   ((uint8)1U)
+#define FLEXIO_SPI_IP_SHIFTER_2_U8                   ((uint8)2U)
+#define FLEXIO_SPI_IP_SHIFTER_3_U8                   ((uint8)3U)
+#define FLEXIO_SPI_IP_SHIFTER_4_U8                   ((uint8)4U)
+#define FLEXIO_SPI_IP_SHIFTER_5_U8                   ((uint8)5U)
+#define FLEXIO_SPI_IP_SHIFTER_6_U8                   ((uint8)6U)
+#define FLEXIO_SPI_IP_SHIFTER_7_U8                   ((uint8)7U)
+
+#define FLEXIO_SPI_IP_TIMER_0_U8                     ((uint8)0U)
+#define FLEXIO_SPI_IP_TIMER_1_U8                     ((uint8)1U)
+#define FLEXIO_SPI_IP_TIMER_2_U8                     ((uint8)2U)
+#define FLEXIO_SPI_IP_TIMER_3_U8                     ((uint8)3U)
+#define FLEXIO_SPI_IP_TIMER_4_U8                     ((uint8)4U)
+#define FLEXIO_SPI_IP_TIMER_5_U8                     ((uint8)5U)
+#define FLEXIO_SPI_IP_TIMER_6_U8                     ((uint8)6U)
+#define FLEXIO_SPI_IP_TIMER_7_U8                     ((uint8)7U)
+
+#endif /*(FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+/*==================================================================================================
+ *                                     DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+/** @} */

generate/include/Flexio_Spi_Ip_CfgDefines.h

@@ -0,0 +1,103 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_CFG_DEFINES_H
+#define FLEXIO_SPI_IP_CFG_DEFINES_H
+
+/**
+*   @file     Flexio_Spi_Ip_CfgDefines.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            module configuration(s).
+*   @addtogroup FLEXIO_DRIVER_CONFIGURATION  Flexio_Spi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                                 SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define FLEXIO_SPI_IP_CFG_DEFINES_VENDOR_ID_H                    43
+#define FLEXIO_SPI_IP_CFG_DEFINES_MODULE_ID_H                    83
+#define FLEXIO_SPI_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION_H     4
+#define FLEXIO_SPI_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION_H     4
+#define FLEXIO_SPI_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION_H  0
+#define FLEXIO_SPI_IP_CFG_DEFINES_SW_MAJOR_VERSION_H             1
+#define FLEXIO_SPI_IP_CFG_DEFINES_SW_MINOR_VERSION_H             0
+#define FLEXIO_SPI_IP_CFG_DEFINES_SW_PATCH_VERSION_H             0
+
+/*==================================================================================================
+*                                       FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       DEFINES AND MACROS
+==================================================================================================*/
+
+
+
+/* Macros that indicate FLEXIO channels used by SPI */
+
+/* Macros that indicate FLEXIO pins used by SPI */
+
+/* Macros that indicate FLEXIO channels used by SPI */
+
+/*==================================================================================================
+*                                              ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                  STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                  GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                       FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* FLEXIO_SPI_IP_CFG_DEFINES_H */

generate/include/Flexio_Spi_Ip_VS_0_PBcfg.h

@@ -0,0 +1,109 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef FLEXIO_SPI_IP_VS_0_PBCFG_H
+#define FLEXIO_SPI_IP_VS_0_PBCFG_H
+
+/**   
+*   @file     Flexio_Spi_Ip_PBcfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup FLEXIO_SPI_DRIVER_CONFIGURATION  Flexio_Spi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+/* Inclusion of incompatible header files shall be avoided */
+#define FLEXIO_SPI_IP_VS_0_VENDOR_ID_PBCFG                        43
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG         4
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG         4
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG      0
+#define FLEXIO_SPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG                 1
+#define FLEXIO_SPI_IP_VS_0_SW_MINOR_VERSION_PBCFG                 0
+#define FLEXIO_SPI_IP_VS_0_SW_PATCH_VERSION_PBCFG                 0
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#define FLEXIO_SPI_IP_CONFIG_VS_0_PB \
+
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
+

generate/include/Flexio_Uart_Ip_CfgDefines.h

@@ -75,46 +75,10 @@ extern "C"{
  *                                     DEFINES AND MACROS
 ==================================================================================================*/
 /* Macros that indicate FLEXIO channels used by UART */
-#ifndef FLEXIO_0_CH_0_USED
-    #define FLEXIO_0_CH_0_USED
-#else
-    #error "CHANNEL_0 cannot be used by UART driver. Channel locked by another driver!"
-#endif
-
-#ifndef FLEXIO_0_CH_1_USED
-    #define FLEXIO_0_CH_1_USED
-#else
-    #error "CHANNEL_1 cannot be used by UART driver. Channel locked by another driver!"
-#endif
-
 
 /* Macros that indicate FLEXIO pins used by UART */
-#ifndef FLEXIO_0_PIN_6_USED
-    #define FLEXIO_0_PIN_6_USED
-#else
-    #error "PIN_6 cannot be used by UART driver. Pin used by another driver!"
-#endif
-
-#ifndef FLEXIO_0_PIN_7_USED
-    #define FLEXIO_0_PIN_7_USED
-#else
-    #error "PIN_7 cannot be used by UART driver. Pin used by another driver!"
-#endif
-
 
 /* Macros that indicate FLEXIO channels used by UART */
-#ifdef FLEXIO_0_CH_0_USED
-    #define UART_CHANNEL_0_USED
-#else
-    #error "CHANNEL_0 cannot be used by UART driver. Channel locked by other driver!"
-#endif
-
-#ifdef FLEXIO_0_CH_1_USED
-    #define UART_CHANNEL_1_USED
-#else
-    #error "CHANNEL_1 cannot be used by UART driver. Channel locked by other driver!"
-#endif
-
 
 /*==================================================================================================
 *                                            ENUMS

generate/include/Flexio_Uart_Ip_Defines.h

@@ -78,7 +78,7 @@ extern "C"{
 ==================================================================================================*/
 
 /* @brief Using FLEXIO */
-#define FLEXIO_UART_IP_IS_USING                         (STD_ON)
+#define FLEXIO_UART_IP_IS_USING                         (STD_OFF)
 /* @brief Development error detection */
 #define FLEXIO_UART_IP_DEV_ERROR_DETECT                 (STD_ON)
 

generate/include/Flexio_Uart_Ip_VS_0_PBcfg.h

@@ -117,13 +117,7 @@ extern void Uart_Ipw_FlexioTransferCallback(const uint32 HwChannel, const Flexio
 
 
 
-#define FLEXIO_UART_IP_CONFIG_VS_0_PB \
-
-extern const Flexio_Uart_Ip_UserConfigType Flexio_Uart_Ip_xHwConfigPB_3_VS_0;\
-
-
-extern const Flexio_Uart_Ip_UserConfigType Flexio_Uart_Ip_xHwConfigPB_4_VS_0;\
-
+#define FLEXIO_UART_IP_CONFIG_VS_0_PB
 
 /*==================================================================================================
                                    LOCAL FUNCTION PROTOTYPES

generate/include/IntCtrl_Ip_Cfg.h

@@ -99,7 +99,10 @@ extern void Dma0_Ch2_IRQHandler(void);
 extern void Dma0_Ch3_IRQHandler(void);
 extern void Dma0_Ch4_IRQHandler(void);
 extern void Dma0_Ch5_IRQHandler(void);
+extern void Dma0_Ch6_IRQHandler(void);
+extern void Dma0_Ch7_IRQHandler(void);
 extern void undefined_handler(void);
+extern void Lpspi_Ip_LPSPI_2_IRQHandler(void);
 extern void LPUART_UART_IP_0_IRQHandler(void);
 extern void LPUART_UART_IP_1_IRQHandler(void);
 extern void LPUART_UART_IP_2_IRQHandler(void);

generate/include/Lpspi_Ip_Cfg.h

@@ -0,0 +1,239 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef LPSPI_IP_CFG_H
+#define LPSPI_IP_CFG_H
+
+/**
+*   @file    Lpspi_Ip_Cfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            module configuration(s).
+*   @addtogroup LPSPI_DRIVER_CONFIGURATION Lpspi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+#include "Mcal.h"
+#include "OsIf.h"
+
+#include "Lpspi_Ip_VS_0_PBcfg.h"
+
+#include "S32K146_LPSPI.h"
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define LPSPI_IP_VENDOR_ID_CFG                       43
+#define LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG        4
+#define LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG        4
+#define LPSPI_IP_AR_RELEASE_REVISION_VERSION_CFG     0
+#define LPSPI_IP_SW_MAJOR_VERSION_CFG                1
+#define LPSPI_IP_SW_MINOR_VERSION_CFG                0
+#define LPSPI_IP_SW_PATCH_VERSION_CFG                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != MCAL_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Lpspi_Ip_Cfg.h and Mcal.h are different"
+    #endif
+
+    /* Check if current file and OsIf header file are of the same Autosar version */
+    #if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != OSIF_AR_RELEASE_MINOR_VERSION))
+        #error "AutoSar Version Numbers of Lpspi_Ip_Cfg.h and OsIf.h are different"
+    #endif
+#endif
+
+
+
+/* Check if Lpspi_Ip_VS_0_PBcfg header file and Spi configuration header file are of the same vendor */
+#if (LPSPI_IP_VS_0_VENDOR_ID_PBCFG != LPSPI_IP_VENDOR_ID_CFG)
+    #error "Lpspi_Ip_VS_0_PBcfg.h and Lpspi_Ip_Cfg.h have different vendor IDs"
+#endif
+    /* Check if Lpspi_Ip_VS_0_PBcfg header file and Spi  configuration header file are of the same Autosar version */
+#if ((LPSPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG != LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (LPSPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG != LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (LPSPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG != LPSPI_IP_AR_RELEASE_REVISION_VERSION_CFG))
+#error "AutoSar Version Numbers of Lpspi_Ip_VS_0_PBcfg.h and Lpspi_Ip_Cfg.h are different"
+#endif
+/* Check if Lpspi_Ip_VS_0_PBcfg header file and Spi configuration header file are of the same software version */
+#if ((LPSPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG != LPSPI_IP_SW_MAJOR_VERSION_CFG) || \
+     (LPSPI_IP_VS_0_SW_MINOR_VERSION_PBCFG != LPSPI_IP_SW_MINOR_VERSION_CFG) || \
+     (LPSPI_IP_VS_0_SW_PATCH_VERSION_PBCFG != LPSPI_IP_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Lpspi_Ip_VS_0_PBcfg.h and Lpspi_Ip_Cfg.h are different"
+#endif
+
+
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+#define LPSPI_IP_CONFIG_EXT \
+ LPSPI_IP_CONFIG_VS_0_PB \
+
+
+/** @brief Total number of SpiPhyUnit configured. */
+#define LPSPI_IP_NUMBER_OF_INSTANCES           (1U)
+
+/** @brief Number of FIFO entries supported */
+#define LPSPI_IP_FIFO_SIZE_U8   ((uint8)4U)
+
+/** @brief HWUnits enabled/disabled */
+
+#define LPSPI_IP_2_ENABLED  (STD_ON)
+    
+#define LPSPI_IP_SLAVE_SUPPORT  ((STD_OFF))
+
+
+/**
+* @brief Defines if transfers are made using DMA or FIFO.
+* @details Defines if transfers are made using DMA or FIFO.
+*/
+#define LPSPI_IP_DMA_USED     (STD_OFF)
+
+/**
+* @brief If enabled, allows dual MCU clock configuration settings.
+* @details If enabled, allows dual MCU clock configuration settings.
+*/
+#define LPSPI_IP_DUAL_CLOCK_MODE  (STD_OFF)
+
+/**
+* @brief          Enable Dma Fast transfer support.
+* @details        When SpiAutosarExt/SpiEnableDmaFastTransferSupport = TRUE,
+*                 the SPI driver can be supported to transfer multiple Jobs, Channels and CPU used only for processing end of Sequence transfer.
+*/
+#define LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT   (STD_OFF)
+
+/**
+* @brief          Enable User Mode Support.
+* @details        When SpiAutosarExt/SpiEnableUserModeSupport = TRUE,
+*                 the SPI driver can be executed from both supervisor and user mode.
+*
+* @api
+*/
+#define LPSPI_IP_ENABLE_USER_MODE_SUPPORT   (STD_OFF)
+
+#ifndef MCAL_ENABLE_USER_MODE_SUPPORT
+ #ifdef LPSPI_IP_ENABLE_USER_MODE_SUPPORT
+  #if (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT)
+   #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running  Spi in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
+  #endif /* (STD_ON == LPSPI_IP_ENABLE_USER_MODE_SUPPORT) */
+ #endif /* ifdef MCAL_ENABLE_USER_MODE_SUPPORT */
+#endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT*/
+
+/**
+* @brief SPI registers is controlled by REG_PROT IP.
+*/
+#define LPSPI_IP_REG_PROT_AVAILABLE   (STD_OFF)
+
+#if (STD_ON == LPSPI_IP_REG_PROT_AVAILABLE)
+/**
+* @brief The protection size
+*/
+    #define LPSPI_IP_PROT_MEM_U32                           ((uint32)4U)
+#endif
+
+/**
+* @brief Maximum of frame size supported.
+*/
+#define LPSPI_IP_FRAMESIZE_MAX_U8                              ((uint8)32U)
+
+/**
+* @brief Minimum of frame size supported.
+*/
+#define LPSPI_IP_FRAMESIZE_MIN_U8                              ((uint8)4U)
+
+/**
+* @brief Define Timeout Method.
+* @details Define a certain timeout method from OsIf will be used in the driver.
+*/
+#define LPSPI_IP_TIMEOUT_METHOD           (OSIF_COUNTER_SYSTEM)
+
+/**
+* @brief Switches ON or OFF for the detection and reporting of development errors(API parameter checking) at IP level.
+*/
+/** @implements LPSPI_IP_DEV_ERROR_DETECT_define  */
+#define LPSPI_IP_DEV_ERROR_DETECT     (STD_OFF)
+
+/**
+* @brief Half duplex supported.
+*/
+/** @implements LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT_define  */
+#define LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT     (STD_OFF)
+
+/**
+* @brief Defines the "Number of Loops" timeout.
+* @details Defines the "Number of Loops" timeout used Spi_AsyncTransmitHalfDuplex in half duplex mode
+*         during the wait on TX transmission to complete before start next channel that in receive mode or latest channel in job.
+*        One timeout unit means that no TX or RX was executed(the IF statements are returning FALSE).
+*/
+#define LPSPI_IP_HALF_DUPLEX_TIMEOUT_COUNTER       ((uint32)(50000))
+
+/*==================================================================================================
+ *                                     DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif 
+
+/** @} */

generate/include/Lpspi_Ip_VS_0_PBcfg.h

@@ -0,0 +1,103 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef LPSPI_IP_VS_0_PBCFG_H
+#define LPSPI_IP_VS_0_PBCFG_H
+
+/**
+*   @file    Lpspi_Ip_PBcfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup LPSPI_DRIVER_CONFIGURATION Lpspi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+/* Inclusion of incompatible header files shall be avoided */
+#define LPSPI_IP_VS_0_VENDOR_ID_PBCFG                        43
+#define LPSPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG         4
+#define LPSPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG         4
+#define LPSPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG      0
+#define LPSPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG                 1
+#define LPSPI_IP_VS_0_SW_MINOR_VERSION_PBCFG                 0
+#define LPSPI_IP_VS_0_SW_PATCH_VERSION_PBCFG                 0
+
+/*==================================================================================================
+                                      FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      DEFINES AND MACROS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                             ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#define LPSPI_IP_CONFIG_VS_0_PB \
+ extern const Lpspi_Ip_ExternalDeviceType Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_VS_0; \
+ extern const Lpspi_Ip_ConfigType Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_VS_0; \
+
+
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
+

generate/include/Lpuart_Uart_Ip_VS_0_PBcfg.h

@@ -107,7 +107,7 @@ extern "C"{
     #define LPUART_UART_IP_INSTANCE_USING_2    2U
 #endif
 
-            
+        
 
 /*==================================================================================================
                                        LOCAL CONSTANTS

generate/include/Mcu_Cfg.h

@@ -284,7 +284,7 @@ extern "C"{
 /**
 * @brief            This parameter shall be set True, if the H/W does not have a PLL or the PLL circuitry is enabled after the power on without S/W intervention.
 */
-#define MCU_NO_PLL   (STD_ON)
+#define MCU_NO_PLL   (STD_OFF)
 
 /**
 * @brief            define for interrupt CMU, PMC, SCG peripheral
@@ -408,7 +408,7 @@ extern "C"{
 /**
 * @brief            Maximum number of MCU Mode configurations.
 */
-#define MCU_MAX_MODECONFIGS   ((uint32)1U)
+#define MCU_MAX_MODECONFIGS   ((uint32)3U)
 
 
 /**
@@ -655,9 +655,19 @@ typedef uint32 Mcu_PowerModeStateType;
 */
 
 
-#define McuModeSettingConf_0   ((Mcu_ModeType)0U)
+#define McuModeSettingConf_Run   ((Mcu_ModeType)0U)
 
-#define McuConf_McuModeSettingConf_McuModeSettingConf_0   ((Mcu_ModeType)0U)
+#define McuConf_McuModeSettingConf_McuModeSettingConf_Run   ((Mcu_ModeType)0U)
+
+
+#define McuModeSettingConf_HSRun   ((Mcu_ModeType)1U)
+
+#define McuConf_McuModeSettingConf_McuModeSettingConf_HSRun   ((Mcu_ModeType)1U)
+
+
+#define McuModeSettingConf_VLPR   ((Mcu_ModeType)2U)
+
+#define McuConf_McuModeSettingConf_McuModeSettingConf_VLPR   ((Mcu_ModeType)2U)
 
 
 /**

generate/include/Port_Cfg.h

@@ -580,6 +580,7 @@ PORT_CONFIG_VS_0_PB \
 #define PortConfigSet_PortContainer_SPI_PTC15_SPI2_SCK_MCU_3D_SPC  16
 #define PortConfigSet_PortContainer_SPI_PTC0_SPI2_SIN_MCU_3D_SDI  17
 #define PortConfigSet_PortContainer_SPI_PTC1_SPI2_SOUT_MCU_3D_SDO  18
+#define PortConfigSet_PortContainer_SPI_PTC14_SPI2_PCS0_MCU_3D_CS  40
 #define PortConfigSet_PortContainer_INT_PTE11_LPTMR0_ALT1_MCU_3D_INT1  19
 #define PortConfigSet_PortContainer_INT_PTD5_LPTMR0_ATL2_MCU_3D_INT2  20
 #define PortConfigSet_PortContainer_INT_PTB0_LPTMR0_ATL3_MCU_CC1_INT  21
@@ -621,12 +622,12 @@ PORT_CONFIG_VS_0_PB \
 /**
 * @brief The maximum number of configured pins
 */
-#define PORT_MAX_CONFIGURED_PADS_U16                        ((uint16)40)
+#define PORT_MAX_CONFIGURED_PADS_U16                        ((uint16)41)
 
 /**
  * @brief Number of UnUsed pin array
 */
-#define PORT_MAX_UNUSED_PADS_U16   (81U)
+#define PORT_MAX_UNUSED_PADS_U16   (80U)
 
 /**
 * @brief Port driver Pre-Compile configuration switch

generate/include/Port_Ci_Port_Ip_Cfg.h

@@ -120,7 +120,7 @@ extern "C"{
 /*! @brief Definitions for BOARD_InitPins Functional Group */
 
 /*! @brief User number of configured pins */
-#define NUM_OF_CONFIGURED_PINS 40
+#define NUM_OF_CONFIGURED_PINS 41
 
 #define PORT_START_SEC_CONFIG_DATA_UNSPECIFIED
 #include "Port_MemMap.h"

generate/include/Power_Ip_Cfg_Defines.h

@@ -116,7 +116,7 @@ extern "C"{
 /**
 * @brief            This parameter shall be set True, if the H/W does not have a PLL or the PLL circuitry is enabled after the power on without S/W intervention.
 */
-#define POWER_IP_NO_PLL   (STD_ON)
+#define POWER_IP_NO_PLL   (STD_OFF)
 
 
 /**

generate/include/Spi_Cfg.h

@@ -0,0 +1,392 @@
+/**
+*   @file    Spi_Cfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the necessary information for SPI
+*            module configuration(s).
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_CFG_H
+#define SPI_CFG_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+#include "Mcal.h"
+#include "OsIf.h"
+
+#include "Spi_VS_0_PBcfg.h"
+
+#include "Spi_Ipw_Cfg.h"
+
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define SPI_VENDOR_ID_CFG                       43
+#define SPI_AR_RELEASE_MAJOR_VERSION_CFG        4
+#define SPI_AR_RELEASE_MINOR_VERSION_CFG        4
+#define SPI_AR_RELEASE_REVISION_VERSION_CFG     0
+#define SPI_SW_MAJOR_VERSION_CFG                1
+#define SPI_SW_MINOR_VERSION_CFG                0
+#define SPI_SW_PATCH_VERSION_CFG                0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    /* Check if current file and Mcal header file are of the same Autosar version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION_CFG != MCAL_AR_RELEASE_MAJOR_VERSION) || \
+         (SPI_AR_RELEASE_MINOR_VERSION_CFG != MCAL_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi_Cfg.h and Mcal.h are different"
+    #endif
+     /* Check if the current file and OsIf.h header file are of the same version */
+    #if ((SPI_AR_RELEASE_MAJOR_VERSION_CFG != OSIF_AR_RELEASE_MAJOR_VERSION) || \
+         (SPI_AR_RELEASE_MINOR_VERSION_CFG != OSIF_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi_Cfg.h and OsIf.h are different"
+    #endif   
+#endif
+
+
+
+/* Check if Spi_VS_0_PBcfg header file and Spi configuration header file are of the same vendor */
+#if (SPI_VENDOR_ID_VS_0_PBCFG_H != SPI_VENDOR_ID_CFG)
+    #error "Spi_VS_0_PBcfg.h and Spi_Cfg.h have different vendor IDs"
+#endif
+    /* Check if Spi_VS_0_PBcfg header file and Spi  configuration header file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != SPI_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (SPI_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != SPI_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (SPI_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != SPI_AR_RELEASE_REVISION_VERSION_CFG))
+#error "AutoSar Version Numbers of Spi_VS_0_PBcfg.h and Spi_Cfg.h are different"
+#endif
+/* Check if Spi_VS_0_PBcfg header file and Spi configuration header file are of the same software version */
+#if ((SPI_SW_MAJOR_VERSION_VS_0_PBCFG_H != SPI_SW_MAJOR_VERSION_CFG) || \
+     (SPI_SW_MINOR_VERSION_VS_0_PBCFG_H != SPI_SW_MINOR_VERSION_CFG) || \
+     (SPI_SW_PATCH_VERSION_VS_0_PBCFG_H != SPI_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Spi_VS_0_PBcfg.h and Spi_Cfg.h are different"
+#endif
+
+
+
+
+/* Check if Spi_Ipw_Cfg header file and Spi configuration header file are of the same vendor */
+#if (SPI_IPW_VENDOR_ID_CFG_H != SPI_VENDOR_ID_CFG)
+    #error "Spi_Ipw_Cfg.h and Spi_Cfg.h have different vendor IDs"
+#endif
+    /* Check if Spi_Ipw_Cfg header file and Spi configuration header file are of the same Autosar version */
+#if ((SPI_IPW_AR_RELEASE_MAJOR_VERSION_CFG_H != SPI_AR_RELEASE_MAJOR_VERSION_CFG) || \
+     (SPI_IPW_AR_RELEASE_MINOR_VERSION_CFG_H != SPI_AR_RELEASE_MINOR_VERSION_CFG) || \
+     (SPI_IPW_AR_RELEASE_REVISION_VERSION_CFG_H != SPI_AR_RELEASE_REVISION_VERSION_CFG))
+#error "AutoSar Version Numbers of Spi_Ipw_Cfg.h and Spi_Cfg.h are different"
+#endif
+/* Check if Spi_Ipw_Cfg header file and Spi configuration header file are of the same software version */
+#if ((SPI_IPW_SW_MAJOR_VERSION_CFG_H != SPI_SW_MAJOR_VERSION_CFG) || \
+     (SPI_IPW_SW_MINOR_VERSION_CFG_H != SPI_SW_MINOR_VERSION_CFG) || \
+     (SPI_IPW_SW_PATCH_VERSION_CFG_H != SPI_SW_PATCH_VERSION_CFG))
+#error "Software Version Numbers of Spi_Ipw_Cfg.h and Spi_Cfg.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/**
+* @brief Switches the Development Error functionality ON or OFF.
+* @details Switches the Development Error Detection and Notification ON or OFF.
+* @implements SPI_DEV_ERROR_DETECT_define
+*/
+
+#define SPI_DEV_ERROR_DETECT           (STD_ON)
+
+/**
+* @brief Switches the Version Information API functionality ON or OFF.
+* @details Switches the Spi_GetVersionInfo function ON or OFF.
+*/
+
+#define SPI_VERSION_INFO_API           (STD_ON)
+
+/**
+* @brief Switches the Interruptible Sequences handling functionality ON or OFF. 
+* @details This parameter depends on SPI_LEVEL_DELIVERED value. 
+*        It is only used for SPI_LEVEL_DELIVERED configured to 1 or 2.
+* @implements SPI_INTERRUPTIBLE_SEQ_ALLOWED_define
+*/
+
+#define SPI_INTERRUPTIBLE_SEQ_ALLOWED  (STD_OFF)
+
+/**
+* @brief Switches the Spi_GetHWUnitStatus function ON or OFF.
+* @details Switches the Spi_GetHWUnitStatus function ON or OFF.
+* @implements SPI_HW_STATUS_API_define
+*/
+
+#define SPI_HW_STATUS_API          (STD_ON)
+
+/**
+* @brief Switches the Spi_Cancel function ON or OFF.
+* @details Switches the Spi_Cancel function ON or OFF. (see chapter 8.3.13)
+* @implements SPI_CANCEL_API_define
+*/
+#define SPI_CANCEL_API             (STD_ON)
+
+/* Only Internal Buffers are allowed in Handler Driver.*/
+#define USAGE0                          0x00u
+
+/* Only External Buffers are allowed in Handler Driver.*/
+#define USAGE1                          0x01u
+
+/* Both Buffer types are allowd in Handler Driver. */
+#define USAGE2                          0x02u
+
+/**
+* @brief Selects the SPI Handler Driver Channel Buffers usage allowed and delivered.
+* @details Selects the SPI Handler Driver Channel Buffers usage allowed and delivered.
+*        (see chapter 7.2.1)
+* @implements SPI_CHANNEL_BUFFERS_ALLOWED_define
+*/
+#define SPI_CHANNEL_BUFFERS_ALLOWED    (USAGE1)
+
+/* The LEVEL 0 Simple Synchronous SPI Handler Driver functionalities are selected.*/
+#define LEVEL0                          0x00u
+
+/* The LEVEL 1 Basic Asynchronous SPI Handler Driver functionalities are selected.*/
+#define LEVEL1                          0x01u
+
+/* The LEVEL 2 Enhanced SPI Handler Driver functionalities are selected. */
+#define LEVEL2                          0x02u
+
+/**
+* @brief Selects the SPI Handler Driver level of scalable functionality.
+* @details Selects the SPI Handler Driver level of scalable functionality that 
+* is available and delivered. (see chapter 7.1)
+* @implements SPI_LEVEL_DELIVERED_define
+*/
+#define SPI_LEVEL_DELIVERED            (LEVEL2)
+
+/**
+* @brief Defines the maximum number of supported channels.
+* @details Defines the maximum number of supported channels
+*     for all the driver configurations.
+*/
+#define SpiConf_SpiChannel_SpiChannel_0    ((Spi_ChannelType)0)
+#define SPI_MAX_CHANNEL  (1u)
+
+/**
+* @brief Total number of Jobs configured.
+* @details Defines the maximum number of supported jobs
+*     for all the driver configurations.
+*/
+#define SpiConf_SpiJob_SpiJob_0   ((Spi_JobType)0)
+#define SPI_MAX_JOB     (1u)
+
+/**
+* @brief Total number of Sequences configured.
+* @details Defines the maximum number of supported sequences
+*     for all the driver configurations.
+*/
+#define SpiConf_SpiSequence_SpiSequence_0   ((Spi_SequenceType)0)
+#define SPI_MAX_SEQUENCE  (1u)
+
+/**
+* @brief Defines the peripherals used throughout the configuration(s).
+* @details Defines the peripherals used throughout the configuration(s).
+*/
+#define CSIB0  ((uint8)0u)
+
+/**
+* @brief Total number of SpiPhyUnit configured.
+*/
+#define SPI_MAX_HWUNIT   (1u)
+
+/**
+* @brief Defines the external devices the driver will use.
+* @details Reference to the external device used by this job.
+*/
+#define SPI_SpiExternalDevice_0  ((Spi_ExternalDeviceType)0u)
+
+
+/**
+* @brief   Switches the Production Error Detection and Notification OFF
+*
+* @implements SPI_DISABLE_DEM_REPORT_ERROR_STATUS_define
+* 
+*/
+#define SPI_DISABLE_DEM_REPORT_ERROR_STATUS   (STD_ON) /* Disable Production Error Detection */
+
+
+/*==================================================================================================
+ *                                     DEFINES AND MACROS
+==================================================================================================*/
+
+
+/**
+* @brief Define values for Autosar configuration variants.
+* @details Define values for Autosar configuration variants.
+*/
+#define SPI_VARIANT_PRECOMPILE  (0)
+#define SPI_VARIANT_POSTBUILD   (1)
+#define SPI_VARIANT_LINKTIME    (2)
+
+/**
+* @brief Defines the use of Pre-Compile(PC) support
+* @details VARIANT-PRE-COMPILE: Only parameters with "Pre-compile time" configu-ration are allowed 
+*        in this variant.
+*/
+/* Pre-Compile(PC) Support. */
+/* Link Time Support. */
+#define SPI_CONFIG_VARIANT      (SPI_VARIANT_PRECOMPILE)
+
+/**
+* @brief Define precompile support.
+* @details Define precompile support if VariantPreCompile or VariantLinkTime is selected and number of variant <=1.
+*/
+#define SPI_PRECOMPILE_SUPPORT      (STD_ON)
+
+/**
+* @brief Defines the "Number of Loops" timeout.
+* @details Defines the "Number of Loops" timeout used by Spi_SyncTransmit and Spi_AsyncTransmit
+*        function during the wait on TX/RX transmission to complete one frame.
+*        One timeout unit means that no TX or RX was executed(the IF statements are returning FALSE).
+*/
+#define SPI_TIMEOUT_COUNTER       ((uint32)(50000))
+
+/**
+* @brief Allow simultaneous calls to Spi_SyncTransmit() for different threads.
+* @details Two concurrent calls to Spi_SyncTransmit() will be allowed only if the related sequences
+*       do not share HW units.
+*/
+#define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT    (STD_ON)
+
+/*==================================================================================================
+ *                                           SpiAutosarExt DEFINES
+==================================================================================================*/
+/**
+* @brief If enabled, the asyncronous operation mode (POLLING or INTERRUPT)
+* @details If enabled, the asyncronous operation mode (POLLING or INTERRUPT) can
+*       be defined independently for each HWUnit using Spi_SetHWUnitAsyncMode().
+* @implements SPI_HWUNIT_ASYNC_MODE_define
+*/
+#define SPI_HWUNIT_ASYNC_MODE  (STD_OFF)
+
+/**
+* @brief If enabled, allows to configure more than 256 sequences, jobs and channels.
+*/
+#define SPI_ALLOW_BIGSIZE_COLLECTIONS  (STD_OFF)
+
+/**
+* @brief If enabled, SPI_MAIN_FUNCTION_PERIOD defines the cycle time of the function Spi_MainFunction_Handling in seconds
+*/
+
+/**
+* @brief Total number of partitions configured in Ecu.
+*/
+#define SPI_MAX_PARTITIONS             (1U)
+
+/**
+* @brief          Enable Multicore Support.
+* @details        When SpiGeneral/SpiMulticoreSupport = TRUE,
+*                 the SPI driver can be configured to support multicore.
+*/
+#define SPI_MULTICORE_ENABLED          (STD_OFF)
+
+#if (STD_OFF == SPI_MULTICORE_ENABLED)
+/**
+* @brief Defines default CodeId value which is assigned to HWUnits, Sequences, Jobs and Channels in the case multicore is not enabled.
+*/
+    #define SPI_SPURIOUS_CORE_ID        ((uint32)0UL)
+#endif
+
+#if (STD_ON == SPI_MULTICORE_ENABLED)
+    #define Spi_GetCoreID     ((uint32)OsIf_GetCoreID())
+#else
+    #define Spi_GetCoreID     SPI_SPURIOUS_CORE_ID
+#endif
+
+/**
+* @brief  Slave support
+*/
+#define SPI_SLAVE_SUPPORT SPI_IPW_SLAVE_SUPPORT
+
+/**
+* @brief Defines if transfers are made using DMA or FIFO.
+* @details Defines if transfers are made using DMA or FIFO.
+* @implements SPI_DMA_USED_define
+*/
+#define SPI_DMA_USED SPI_IPW_DMA_USED
+
+/**
+* @brief If enabled, allows dual MCU clock configuration settings.
+* @details If enabled, allows dual MCU clock configuration settings.
+* @implements SPI_DUAL_CLOCK_MODE_define
+*/
+#define SPI_DUAL_CLOCK_MODE SPI_IPW_DUAL_CLOCK_MODE
+
+/**
+* @brief If enabled, allows to Sequence transfer in Dma Fast mode.
+*/
+#define SPI_ENABLE_DMAFASTTRANSFER_SUPPORT  SPI_IPW_ENABLE_DMAFASTTRANSFER_SUPPORT
+
+/**
+* @brief Half duplex mdoe enable .
+*/
+#define SPI_HALF_DUPLEX_MODE_SUPPORT  SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*SPI_CFG_H*/
+
+/** @} */

generate/include/Spi_Ipw_Cfg.h

@@ -0,0 +1,125 @@
+/**
+*   @file    Spi_Ipw_Cfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the extern declaration for SPI
+*            module configuration(s).
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_IPW_CFG_H
+#define SPI_IPW_CFG_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_VENDOR_ID_CFG_H                    43
+#define SPI_IPW_AR_RELEASE_MAJOR_VERSION_CFG_H     4
+#define SPI_IPW_AR_RELEASE_MINOR_VERSION_CFG_H     4
+#define SPI_IPW_AR_RELEASE_REVISION_VERSION_CFG_H  0
+#define SPI_IPW_SW_MAJOR_VERSION_CFG_H             1
+#define SPI_IPW_SW_MINOR_VERSION_CFG_H             0
+#define SPI_IPW_SW_PATCH_VERSION_CFG_H             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+/** @brief HWUnits enabled/disabled */
+
+#define SPI_IPW_SLAVE_SUPPORT  ((STD_OFF))
+
+
+/**
+* @brief Defines if transfers are made using DMA or FIFO.
+* @details Defines if transfers are made using DMA or FIFO.
+*/
+#define SPI_IPW_DMA_USED     (STD_OFF)
+
+/**
+* @brief If enabled, allows dual MCU clock configuration settings.
+* @details If enabled, allows dual MCU clock configuration settings.
+*/
+#define SPI_IPW_DUAL_CLOCK_MODE  (STD_OFF)
+
+/**
+* @brief          Enable Dma Fast transfer support.
+* @details        When SpiAutosarExt/SpiEnableDmaFastTransferSupport = TRUE,
+*                 the SPI driver can be supported to transfer multiple Jobs, Channels and CPU used only for processing end of Sequence transfer.
+*/
+#define SPI_IPW_ENABLE_DMAFASTTRANSFER_SUPPORT   (STD_OFF)
+
+/**
+* @brief          Half duplex mdoe enable 
+*/
+#define SPI_IPW_SPI_HALF_DUPLEX_MODE_SUPPORT   (STD_OFF)
+
+/*
+* @brief Flexio SPI supported enable.
+* @details Flexio SPI supported enable. 
+*/
+#define SPI_IPW_SPI_FLEXIO_ENABLE     (STD_OFF)
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+/** @} */

generate/include/Spi_Ipw_VS_0_PBcfg.h

@@ -0,0 +1,116 @@
+/**
+*   @file    Spi_Ipw_VS_0_PBcfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the extern declaration for SPI
+*            module configuration(s).
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+#ifndef SPI_IPW_VS_0_PBCFG_H
+#define SPI_IPW_VS_0_PBCFG_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+#include "Spi_IPW.h"
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_VENDOR_ID_VS_0_PBCFG_H                    43
+#define SPI_IPW_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H     4
+#define SPI_IPW_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H     4
+#define SPI_IPW_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H  0
+#define SPI_IPW_SW_MAJOR_VERSION_VS_0_PBCFG_H             1
+#define SPI_IPW_SW_MINOR_VERSION_VS_0_PBCFG_H             0
+#define SPI_IPW_SW_PATCH_VERSION_VS_0_PBCFG_H             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if this header file and Spi_IPW.h are of the same vendor */
+#if (SPI_IPW_VENDOR_ID_VS_0_PBCFG_H != SPI_IPW_VENDOR_ID)
+    #error "Spi_Ipw_PBcfg.h and Spi_IPW.h have different vendor ids"
+#endif
+/* Check if Spi_Ipw_PBcfg.h file and Spi_IPW.h file are of the same Autosar version */
+#if ((SPI_IPW_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != SPI_IPW_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != SPI_IPW_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_IPW_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != SPI_IPW_AR_RELEASE_REVISION_VERSION))
+#error "AutoSar Version Numbers of Spi_Ipw_PBcfg.h and Spi_IPW.h are different"
+#endif
+#if ((SPI_IPW_SW_MAJOR_VERSION_VS_0_PBCFG_H != SPI_IPW_SW_MAJOR_VERSION) || \
+     (SPI_IPW_SW_MINOR_VERSION_VS_0_PBCFG_H != SPI_IPW_SW_MINOR_VERSION) || \
+     (SPI_IPW_SW_PATCH_VERSION_VS_0_PBCFG_H != SPI_IPW_SW_PATCH_VERSION))
+#error "Software Version Numbers of Spi_Ipw_PBcfg.h and Spi_IPW.h are different"
+#endif
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/* External device Configuration */
+extern const Spi_ExDevicesConfigType Spi_aExternalDeviceConfigList_VS_0[1U];
+
+/* Hardwre unit device configuration */
+extern const Spi_PhyUnitsConfigType Spi_aHwUnitConfigList_VS_0[SPI_MAX_HWUNIT];
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+/** @} */

generate/include/Spi_VS_0_PBcfg.h

@@ -0,0 +1,92 @@
+/**
+*   @file    Spi_VS_0_PBcfg.h
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Spi configuration header file.
+*   @details This file is the header containing all the extern declaration for SPI
+*            module configuration(s).
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+
+#ifndef SPI_VS_0_PBCFG_H
+#define SPI_VS_0_PBCFG_H
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+* 4) user callback header files
+==================================================================================================*/
+
+/*==================================================================================================
+*                              SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_VENDOR_ID_VS_0_PBCFG_H                    43
+#define SPI_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H     4
+#define SPI_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H     4
+#define SPI_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H  0
+#define SPI_SW_MAJOR_VERSION_VS_0_PBCFG_H             1
+#define SPI_SW_MINOR_VERSION_VS_0_PBCFG_H             0
+#define SPI_SW_PATCH_VERSION_VS_0_PBCFG_H             0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/*==================================================================================================
+*                                          CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                            ENUMS
+==================================================================================================*/
+
+/*==================================================================================================
+*                               STRUCTURES AND OTHER TYPEDEFS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                GLOBAL VARIABLE DECLARATIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                    FUNCTION PROTOTYPES
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @} */

generate/include/Uart_Defines.h

@@ -86,7 +86,7 @@ extern "C"
 #define UART_RUNTIME_ERROR_DETECT       (STD_ON)
 
 /* @brief Number of Channels configured. */
-#define UART_CH_MAX_CONFIG              (5U)
+#define UART_CH_MAX_CONFIG              (3U)
 
 /* @brief UART Osif source counter. This parameter is used to select between different OsIf counter implementation */
 #define UART_TIMEOUT_TYPE               (OSIF_COUNTER_SYSTEM)

generate/include/Uart_Ipw_VS_0_PBcfg.h

@@ -93,18 +93,11 @@ extern "C"{
     extern const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_0_VS_0; \
     extern const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_1_VS_0; \
     extern const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_2_VS_0; \
-    extern const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_3_VS_0; \
-    extern const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_4_VS_0; \
 
 
 #ifndef UART_IPW_LPUART_HW_USING
     #define UART_IPW_LPUART_HW_USING
 #endif
-
-#ifndef UART_IPW_FLEXIO_HW_USING
-    #define UART_IPW_FLEXIO_HW_USING
-#endif
-
 /*==================================================================================================
 *                                  GLOBAL VARIABLE DECLARATIONS
 ==================================================================================================*/
@@ -154,18 +147,6 @@ extern void UART_Callback(uint8 HwInstance, Uart_EventType Event);
 
 
 
-
-
-
-
-
-
-
-
-
-
-
-
 /*==================================================================================================
 *                                       FUNCTION PROTOTYPES
 ==================================================================================================*/

generate/include/modules.h

@@ -258,7 +258,7 @@ extern "C" {
 * @brief This constant used for other modules to check if SPI is present in the project.  
 * @violates @ref modules_h_REF_1 MISRA 2012 Advisory Rule 2.5, unused macro. 
 */
-#define USE_SPI_MODULE              (STD_OFF)
+#define USE_SPI_MODULE              (STD_ON)
 
 /** 
 * @brief This constant used for other modules to check if WDG is present in the project.  

generate/output/Can.epc

@@ -133,7 +133,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/Can_TS_T40D2M10I0R0/Can/CanConfigSet/CanController/CanControllerBaudrateConfig/CanControllerPrescaller</DEFINITION-REF>
-                          <VALUE>12</VALUE>
+                          <VALUE>8</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/Can_TS_T40D2M10I0R0/Can/CanConfigSet/CanController/CanControllerBaudrateConfig/CanControllerPrescallerAlternate</DEFINITION-REF>
@@ -336,7 +336,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/Can_TS_T40D2M10I0R0/Can/CanConfigSet/CanController/CanControllerBaudrateConfig/CanControllerPrescaller</DEFINITION-REF>
-                          <VALUE>12</VALUE>
+                          <VALUE>8</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/Can_TS_T40D2M10I0R0/Can/CanConfigSet/CanController/CanControllerBaudrateConfig/CanControllerPrescallerAlternate</DEFINITION-REF>

generate/output/CanIf.epc

@@ -37,6 +37,22 @@
                     </ECUC-REFERENCE-VALUE>
                   </REFERENCE-VALUES>
                 </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>CanIfCtrlCfg_1</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/CanIf/CanIfCtrlDrvCfg/CanIfCtrlCfg</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/CanIf/CanIfCtrlDrvCfg/CanIfCtrlCfg/CanIfCtrlId</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <REFERENCE-VALUES>
+                    <ECUC-REFERENCE-VALUE>
+                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/CanIf/CanIfCtrlDrvCfg/CanIfCtrlCfg/CanIfCtrlCanCtrlRef</DEFINITION-REF>
+                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Can/Can/CanConfigSet/CanController_1</VALUE-REF>
+                    </ECUC-REFERENCE-VALUE>
+                  </REFERENCE-VALUES>
+                </ECUC-CONTAINER-VALUE>
               </SUB-CONTAINERS>
             </ECUC-CONTAINER-VALUE>
           </CONTAINERS>

generate/output/Dio.epc

@@ -147,6 +147,48 @@
                     </ECUC-CONTAINER-VALUE>
                   </SUB-CONTAINERS>
                 </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>DioPort_C</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioPortId</DEFINITION-REF>
+                      <VALUE>2</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <SUB-CONTAINERS>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTC0_SPI2_SIN_MCU_3D_SDI</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel/DioChannelId</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTC14_SPI2_PCS0_MCU_3D_CS</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel/DioChannelId</DEFINITION-REF>
+                          <VALUE>14</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTC1_SPI2_SOUT_MCU_3D_SDO</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort/DioChannel/DioChannelId</DEFINITION-REF>
+                          <VALUE>1</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                  </SUB-CONTAINERS>
+                </ECUC-CONTAINER-VALUE>
                 <ECUC-CONTAINER-VALUE>
                   <SHORT-NAME>DioPort_D</SHORT-NAME>
                   <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Dio/DioConfig/DioPort</DEFINITION-REF>

generate/output/EcuM.epc

@@ -97,7 +97,7 @@
                       <REFERENCE-VALUES>
                         <ECUC-REFERENCE-VALUE>
                           <DEFINITION-REF DEST="ECUC-SYMBOLIC-NAME-REFERENCE-DEF">/TS_T40D2M10I0R0/EcuM/EcuMConfiguration/EcuMCommonConfiguration/EcuMSleepMode/EcuMSleepModeMcuModeRef</DEFINITION-REF>
-                          <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcu/Mcu/McuModuleConfiguration/McuModeSettingConf_0</VALUE-REF>
+                          <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcu/Mcu/McuModuleConfiguration/McuModeSettingConf_Run</VALUE-REF>
                         </ECUC-REFERENCE-VALUE>
                         <ECUC-REFERENCE-VALUE>
                           <DEFINITION-REF DEST="ECUC-SYMBOLIC-NAME-REFERENCE-DEF">/TS_T40D2M10I0R0/EcuM/EcuMConfiguration/EcuMCommonConfiguration/EcuMSleepMode/EcuMWakeupSourceMask</DEFINITION-REF>

generate/output/Mcu.epc

@@ -138,7 +138,7 @@
                 </ECUC-NUMERICAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuGeneralConfiguration/McuNoPll</DEFINITION-REF>
-                  <VALUE>1</VALUE>
+                  <VALUE>0</VALUE>
                 </ECUC-NUMERICAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>
@@ -172,7 +172,7 @@
                 </ECUC-TEXTUAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>
-                  <VALUE>1</VALUE>
+                  <VALUE>3</VALUE>
                 </ECUC-NUMERICAL-PARAM-VALUE>
                 <ECUC-NUMERICAL-PARAM-VALUE>
                   <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuRTC_CLKINFrequencyHz</DEFINITION-REF>
@@ -202,11 +202,11 @@
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuAllowedModes/McuAllowHighSpeedRunMode</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuAllowedModes/McuAllowVeryLowPowerModes</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
@@ -220,7 +220,7 @@
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuScgClkOutSelect</DEFINITION-REF>
-                      <VALUE>SLOW_CLK</VALUE>
+                      <VALUE>SPLL_CLK</VALUE>
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSysClockUnderMcuControl</DEFINITION-REF>
@@ -292,11 +292,11 @@
                       <PARAMETER-VALUES>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockFrequencySelect</DEFINITION-REF>
-                          <VALUE>CUSTOM</VALUE>
+                          <VALUE>SOSC_CLK</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -314,6 +314,20 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>McuClockReferencePoint_LPSI2</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockFrequencySelect</DEFINITION-REF>
+                          <VALUE>LPSPI2_CLK</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>
+                          <VALUE>4.0E7</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
                     <ECUC-CONTAINER-VALUE>
                       <SHORT-NAME>McuClockReferencePoint_LPUART0_CLK</SHORT-NAME>
                       <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>
@@ -324,7 +338,7 @@
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -338,7 +352,7 @@
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -352,7 +366,7 @@
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -404,23 +418,23 @@
                       <PARAMETER-VALUES>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuBusClockDivider</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuBusClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>4.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuCoreClockDivider</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuCoreClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>8.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuFlashClockFrequency</DEFINITION-REF>
-                          <VALUE>2.4E7</VALUE>
+                          <VALUE>2.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuPreDivSystemClockFrequency</DEFINITION-REF>
@@ -428,19 +442,19 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuScgClkOutFrequency</DEFINITION-REF>
-                          <VALUE>2.4E7</VALUE>
+                          <VALUE>1.6E8</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuSlowClockDivider</DEFINITION-REF>
-                          <VALUE>2</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuSystemClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>8.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuHsrunClockConfig/McuSystemClockSwitch</DEFINITION-REF>
-                          <VALUE>FIRC_CLK</VALUE>
+                          <VALUE>SPLL_CLK</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -1176,11 +1190,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockSelect</DEFINITION-REF>
-                          <VALUE>SIRC</VALUE>
+                          <VALUE>SOSC</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockUnderMcuControl</DEFINITION-REF>
@@ -1210,11 +1224,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockSelect</DEFINITION-REF>
-                          <VALUE>SIRC</VALUE>
+                          <VALUE>SOSC</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockUnderMcuControl</DEFINITION-REF>
@@ -1278,11 +1292,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockFrequency</DEFINITION-REF>
-                          <VALUE>4000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockSelect</DEFINITION-REF>
-                          <VALUE>SIRC</VALUE>
+                          <VALUE>SOSC</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockUnderMcuControl</DEFINITION-REF>
@@ -1584,11 +1598,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockFrequency</DEFINITION-REF>
-                          <VALUE>0.0</VALUE>
+                          <VALUE>4.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockSelect</DEFINITION-REF>
-                          <VALUE>CLOCK_IS_OFF</VALUE>
+                          <VALUE>SPLL</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuPeripheralClockConfig/McuPeripheralClockUnderMcuControl</DEFINITION-REF>
@@ -1606,23 +1620,23 @@
                       <PARAMETER-VALUES>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuBusClockDivider</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuBusClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>4.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuCoreClockDivider</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuCoreClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>8.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuFlashClockFrequency</DEFINITION-REF>
-                          <VALUE>2.4E7</VALUE>
+                          <VALUE>2.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuPreDivSystemClockFrequency</DEFINITION-REF>
@@ -1630,19 +1644,19 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuScgClkOutFrequency</DEFINITION-REF>
-                          <VALUE>2.4E7</VALUE>
+                          <VALUE>1.6E8</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuSlowClockDivider</DEFINITION-REF>
-                          <VALUE>2</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuSystemClockFrequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>8.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuRunClockConfig/McuSystemClockSwitch</DEFINITION-REF>
-                          <VALUE>FIRC_CLK</VALUE>
+                          <VALUE>SPLL_CLK</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -1836,11 +1850,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCDiv1</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCDiv1Frequency</DEFINITION-REF>
-                          <VALUE>8000000.0</VALUE>
+                          <VALUE>4000000.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCDiv2</DEFINITION-REF>
@@ -1848,7 +1862,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCDiv2Frequency</DEFINITION-REF>
-                          <VALUE>8000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCEnable</DEFINITION-REF>
@@ -1860,7 +1874,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCFrequency</DEFINITION-REF>
-                          <VALUE>8000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemOSCClockConfig/McuSOSCHighGainOscillatorSelect</DEFINITION-REF>
@@ -1882,7 +1896,7 @@
                       <PARAMETER-VALUES>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLClockMonitorEnable</DEFINITION-REF>
-                          <VALUE>0</VALUE>
+                          <VALUE>1</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLClockMonitorResetEnable</DEFINITION-REF>
@@ -1890,27 +1904,27 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLDiv1</DEFINITION-REF>
-                          <VALUE>1</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLDiv1Frequency</DEFINITION-REF>
-                          <VALUE>9.6E7</VALUE>
+                          <VALUE>8.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLDiv2</DEFINITION-REF>
-                          <VALUE>2</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLDiv2Frequency</DEFINITION-REF>
-                          <VALUE>4.8E7</VALUE>
+                          <VALUE>4.0E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLEnable</DEFINITION-REF>
-                          <VALUE>0</VALUE>
+                          <VALUE>1</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLFrequency</DEFINITION-REF>
-                          <VALUE>9.6E7</VALUE>
+                          <VALUE>1.6E8</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLInputClkPreDivider</DEFINITION-REF>
@@ -1918,11 +1932,11 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLInputFrequency</DEFINITION-REF>
-                          <VALUE>8000000.0</VALUE>
+                          <VALUE>1.6E7</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLMultiplier</DEFINITION-REF>
-                          <VALUE>24</VALUE>
+                          <VALUE>20</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSPLLSelectSourceClock</DEFINITION-REF>
@@ -1930,7 +1944,7 @@
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuSystemPll/McuSystemPllUnderMcuControl</DEFINITION-REF>
-                          <VALUE>0</VALUE>
+                          <VALUE>1</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -1940,23 +1954,23 @@
                       <PARAMETER-VALUES>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuBusClockDivider</DEFINITION-REF>
-                          <VALUE>8</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuBusClockFrequency</DEFINITION-REF>
-                          <VALUE>125000.0</VALUE>
+                          <VALUE>500000.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuCoreClockDivider</DEFINITION-REF>
-                          <VALUE>8</VALUE>
+                          <VALUE>4</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuCoreClockFrequency</DEFINITION-REF>
-                          <VALUE>1000000.0</VALUE>
+                          <VALUE>2000000.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuFlashClockFrequency</DEFINITION-REF>
-                          <VALUE>250000.0</VALUE>
+                          <VALUE>1000000.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuPreDivSystemClockFrequency</DEFINITION-REF>
@@ -1964,15 +1978,15 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuScgClkOutFrequency</DEFINITION-REF>
-                          <VALUE>250000.0</VALUE>
+                          <VALUE>0.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuSlowClockDivider</DEFINITION-REF>
-                          <VALUE>4</VALUE>
+                          <VALUE>2</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuSystemClockFrequency</DEFINITION-REF>
-                          <VALUE>1000000.0</VALUE>
+                          <VALUE>2000000.0</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuVlprClockConfig/McuSystemClockSwitch</DEFINITION-REF>
@@ -1997,7 +2011,25 @@
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
                 <ECUC-CONTAINER-VALUE>
-                  <SHORT-NAME>McuModeSettingConf_0</SHORT-NAME>
+                  <SHORT-NAME>McuModeSettingConf_HSRun</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuEnableSleepOnExit</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuPowerMode</DEFINITION-REF>
+                      <VALUE>HSRUN</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>McuModeSettingConf_Run</SHORT-NAME>
                   <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
@@ -2014,6 +2046,24 @@
                     </ECUC-TEXTUAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>McuModeSettingConf_VLPR</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuEnableSleepOnExit</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>
+                      <VALUE>2</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuModeSettingConf/McuPowerMode</DEFINITION-REF>
+                      <VALUE>VLPR</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                </ECUC-CONTAINER-VALUE>
                 <ECUC-CONTAINER-VALUE>
                   <SHORT-NAME>McuPowerControl</SHORT-NAME>
                   <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl</DEFINITION-REF>
@@ -2032,15 +2082,15 @@
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl/McuLowVoltageDetectInterruptEnable</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl/McuLowVoltageDetectResetEnable</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Mcu/McuModuleConfiguration/McuPowerControl/McuLowVoltageWarningInterruptEnable</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>

generate/output/Platform.epc

@@ -511,7 +511,7 @@
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrPriority</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>3</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
@@ -1133,7 +1133,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrEnabled</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>
@@ -1141,7 +1141,7 @@
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrPriority</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>3</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
@@ -1331,7 +1331,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrEnabled</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>1</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>
@@ -1339,7 +1339,7 @@
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Platform/IntCtrlConfig/PlatformIsrConfig/IsrPriority</DEFINITION-REF>
-                      <VALUE>0</VALUE>
+                      <VALUE>3</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                 </ECUC-CONTAINER-VALUE>
@@ -2345,7 +2345,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-FUNCTION-NAME-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrHandler</DEFINITION-REF>
-                      <VALUE>undefined_handler</VALUE>
+                      <VALUE>Lpspi_Ip_LPSPI_2_IRQHandler</VALUE>
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>
@@ -2975,7 +2975,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-FUNCTION-NAME-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrHandler</DEFINITION-REF>
-                      <VALUE>undefined_handler</VALUE>
+                      <VALUE>Dma0_Ch6_IRQHandler</VALUE>
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>
@@ -3173,7 +3173,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-FUNCTION-NAME-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrHandler</DEFINITION-REF>
-                      <VALUE>undefined_handler</VALUE>
+                      <VALUE>Dma0_Ch7_IRQHandler</VALUE>
                     </ECUC-TEXTUAL-PARAM-VALUE>
                     <ECUC-TEXTUAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Platform/MscmConfig/PlatformIsrConfig/IsrName</DEFINITION-REF>

generate/output/Port.epc

@@ -2308,7 +2308,7 @@
                   <PARAMETER-VALUES>
                     <ECUC-NUMERICAL-PARAM-VALUE>
                       <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortNumberOfPortPins</DEFINITION-REF>
-                      <VALUE>3</VALUE>
+                      <VALUE>4</VALUE>
                     </ECUC-NUMERICAL-PARAM-VALUE>
                   </PARAMETER-VALUES>
                   <SUB-CONTAINERS>
@@ -2352,6 +2352,64 @@
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinModeChangeable</DEFINITION-REF>
                           <VALUE>1</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPE</DEFINITION-REF>
+                          <VALUE>PullEnabled</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPFE</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPS</DEFINITION-REF>
+                          <VALUE>PullUp</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPcr</DEFINITION-REF>
+                          <VALUE>64</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>PTC14_SPI2_PCS0_MCU_3D_CS</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinDSE</DEFINITION-REF>
+                          <VALUE>Low_Drive_Strength</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>
+                          <VALUE>PORT_PIN_OUT</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>
+                          <VALUE>1</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>
+                          <VALUE>41</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinInitialMode</DEFINITION-REF>
+                          <VALUE>PORT_GPIO_MODE</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinLK</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>
+                          <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-TEXTUAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>
+                          <VALUE>LPSPI2_PCS0</VALUE>
+                        </ECUC-TEXTUAL-PARAM-VALUE>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinModeChangeable</DEFINITION-REF>
+                          <VALUE>1</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPE</DEFINITION-REF>
                           <VALUE>PullDisabled</VALUE>
@@ -2366,7 +2424,7 @@
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPcr</DEFINITION-REF>
-                          <VALUE>64</VALUE>
+                          <VALUE>78</VALUE>
                         </ECUC-NUMERICAL-PARAM-VALUE>
                       </PARAMETER-VALUES>
                     </ECUC-CONTAINER-VALUE>
@@ -2470,7 +2528,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPE</DEFINITION-REF>
-                          <VALUE>PullDisabled</VALUE>
+                          <VALUE>PullEnabled</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPFE</DEFINITION-REF>
@@ -2478,7 +2536,7 @@
                         </ECUC-NUMERICAL-PARAM-VALUE>
                         <ECUC-TEXTUAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPS</DEFINITION-REF>
-                          <VALUE>PullDown</VALUE>
+                          <VALUE>PullUp</VALUE>
                         </ECUC-TEXTUAL-PARAM-VALUE>
                         <ECUC-NUMERICAL-PARAM-VALUE>
                           <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Port/PortConfigSet/PortContainer/PortPin/PortPinPcr</DEFINITION-REF>

generate/output/Spi.epc

@@ -0,0 +1,362 @@
+<?xml version='1.0'?>
+<AUTOSAR xmlns="http://autosar.org/schema/r4.0"
+         xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+         xsi:schemaLocation="http://autosar.org/schema/r4.0 AUTOSAR_00046.xsd">
+  <AR-PACKAGES>
+    <AR-PACKAGE>
+      <SHORT-NAME>Spi</SHORT-NAME>
+      <ELEMENTS>
+        <ECUC-MODULE-CONFIGURATION-VALUES>
+          <SHORT-NAME>Spi</SHORT-NAME>
+          <DEFINITION-REF DEST="ECUC-MODULE-DEF">/TS_T40D2M10I0R0/Spi</DEFINITION-REF>
+          <IMPLEMENTATION-CONFIG-VARIANT>VARIANT-PRE-COMPILE</IMPLEMENTATION-CONFIG-VARIANT>
+          <POST-BUILD-VARIANT-USED>true</POST-BUILD-VARIANT-USED>
+          <CONTAINERS>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>CommonPublishedInformation</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation</DEFINITION-REF>
+              <PARAMETER-VALUES>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/ArReleaseMajorVersion</DEFINITION-REF>
+                  <VALUE>4</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/ArReleaseMinorVersion</DEFINITION-REF>
+                  <VALUE>4</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/ArReleaseRevisionVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/ModuleId</DEFINITION-REF>
+                  <VALUE>83</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/SwMajorVersion</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/SwMinorVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/SwPatchVersion</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/CommonPublishedInformation/VendorId</DEFINITION-REF>
+                  <VALUE>43</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+            </ECUC-CONTAINER-VALUE>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>SpiAutosarExt</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt</DEFINITION-REF>
+              <PARAMETER-VALUES>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiAllowBigSizeCollections</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiDisableDemReportErrorStatus</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiEnableDmaFastTransferSupport</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiEnableHWUnitAsyncMode</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiEnableUserModeSupport</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiFlexioEnable</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiHalfDuplexModeSupport</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiAutosarExt/SpiJobStartNotificationEnable</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+            </ECUC-CONTAINER-VALUE>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>SpiDriver</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver</DEFINITION-REF>
+              <SUB-CONTAINERS>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>SpiChannel_0</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiChannelId</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiChannelType</DEFINITION-REF>
+                      <VALUE>EB</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiDataWidth</DEFINITION-REF>
+                      <VALUE>8</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiEbMaxLength</DEFINITION-REF>
+                      <VALUE>1000</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiIbNBuffers</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiChannel/SpiTransferStart</DEFINITION-REF>
+                      <VALUE>MSB</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>SpiExternalDevice_0</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiBaudrate</DEFINITION-REF>
+                      <VALUE>1000000.0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiCsContinous</DEFINITION-REF>
+                      <VALUE>TRUE</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-STRING-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiCsIdentifier</DEFINITION-REF>
+                      <VALUE>PCS0</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiCsPolarity</DEFINITION-REF>
+                      <VALUE>LOW</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiCsSelection</DEFINITION-REF>
+                      <VALUE>CS_VIA_PERIPHERAL_ENGINE</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiDataShiftEdge</DEFINITION-REF>
+                      <VALUE>LEADING</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiDeviceHalfDuplexSupport</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiEnableCs</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiHalfDuplexPinSelect</DEFINITION-REF>
+                      <VALUE>HALF_DUPLEX_SOUT</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiHwUnit</DEFINITION-REF>
+                      <VALUE>CSIB0</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiShiftClockIdleLevel</DEFINITION-REF>
+                      <VALUE>HIGH</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiTimeClk2Cs</DEFINITION-REF>
+                      <VALUE>3.0E-6</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiTimeCs2Clk</DEFINITION-REF>
+                      <VALUE>1.0E-6</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-FLOAT-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiTimeCs2Cs</DEFINITION-REF>
+                      <VALUE>2.0E-6</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiExternalDevice/SpiTransferWidth</DEFINITION-REF>
+                      <VALUE>TRANSFER_1_BIT</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>SpiJob_0</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiJobId</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiJobPriority</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <REFERENCE-VALUES>
+                    <ECUC-REFERENCE-VALUE>
+                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiDeviceAssignment</DEFINITION-REF>
+                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Spi/Spi/SpiDriver/SpiExternalDevice_0</VALUE-REF>
+                    </ECUC-REFERENCE-VALUE>
+                  </REFERENCE-VALUES>
+                  <SUB-CONTAINERS>
+                    <ECUC-CONTAINER-VALUE>
+                      <SHORT-NAME>SpiChannelList_0</SHORT-NAME>
+                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiChannelList</DEFINITION-REF>
+                      <PARAMETER-VALUES>
+                        <ECUC-NUMERICAL-PARAM-VALUE>
+                          <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiChannelList/SpiChannelIndex</DEFINITION-REF>
+                          <VALUE>0</VALUE>
+                        </ECUC-NUMERICAL-PARAM-VALUE>
+                      </PARAMETER-VALUES>
+                      <REFERENCE-VALUES>
+                        <ECUC-REFERENCE-VALUE>
+                          <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiJob/SpiChannelList/SpiChannelAssignment</DEFINITION-REF>
+                          <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Spi/Spi/SpiDriver/SpiChannel_0</VALUE-REF>
+                        </ECUC-REFERENCE-VALUE>
+                      </REFERENCE-VALUES>
+                    </ECUC-CONTAINER-VALUE>
+                  </SUB-CONTAINERS>
+                </ECUC-CONTAINER-VALUE>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>SpiSequence_0</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiSequence</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiSequence/SpiEnableDmaFastTransfer</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiSequence/SpiInterruptibleSequence</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiSequence/SpiSequenceId</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <REFERENCE-VALUES>
+                    <ECUC-REFERENCE-VALUE>
+                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Spi/SpiDriver/SpiSequence/SpiJobAssignment</DEFINITION-REF>
+                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Spi/Spi/SpiDriver/SpiJob_0</VALUE-REF>
+                    </ECUC-REFERENCE-VALUE>
+                  </REFERENCE-VALUES>
+                </ECUC-CONTAINER-VALUE>
+              </SUB-CONTAINERS>
+            </ECUC-CONTAINER-VALUE>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>SpiGeneral</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral</DEFINITION-REF>
+              <PARAMETER-VALUES>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiCancelApi</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiChannelBuffersAllowed</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiDevErrorDetect</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiGlobalDmaEnable</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiHwStatusApi</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiInterruptibleSeqAllowed</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiLevelDelivered</DEFINITION-REF>
+                  <VALUE>2</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiMulticoreSupport</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiSupportConcurrentSyncTransmit</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-TEXTUAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiTimeoutMethod</DEFINITION-REF>
+                  <VALUE>OSIF_COUNTER_SYSTEM</VALUE>
+                </ECUC-TEXTUAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiTransmitTimeout</DEFINITION-REF>
+                  <VALUE>50000</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiVersionInfoApi</DEFINITION-REF>
+                  <VALUE>1</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+              <SUB-CONTAINERS>
+                <ECUC-CONTAINER-VALUE>
+                  <SHORT-NAME>SpiPhyUnit_0</SHORT-NAME>
+                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit</DEFINITION-REF>
+                  <PARAMETER-VALUES>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPhyUnitAsyncUseDma</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPhyUnitMapping</DEFINITION-REF>
+                      <VALUE>LPSPI_2</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-TEXTUAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPhyUnitMode</DEFINITION-REF>
+                      <VALUE>SPI_MASTER</VALUE>
+                    </ECUC-TEXTUAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-BOOLEAN-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPhyUnitSync</DEFINITION-REF>
+                      <VALUE>1</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPinConfiguration</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                    <ECUC-NUMERICAL-PARAM-VALUE>
+                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiSamplePoint</DEFINITION-REF>
+                      <VALUE>0</VALUE>
+                    </ECUC-NUMERICAL-PARAM-VALUE>
+                  </PARAMETER-VALUES>
+                  <REFERENCE-VALUES>
+                    <ECUC-REFERENCE-VALUE>
+                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Spi/SpiGeneral/SpiPhyUnit/SpiPhyUnitClockRef</DEFINITION-REF>
+                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcu/Mcu/McuModuleConfiguration/McuClockSettingConfig_0/McuClockReferencePoint_LPSI2</VALUE-REF>
+                    </ECUC-REFERENCE-VALUE>
+                  </REFERENCE-VALUES>
+                </ECUC-CONTAINER-VALUE>
+              </SUB-CONTAINERS>
+            </ECUC-CONTAINER-VALUE>
+            <ECUC-CONTAINER-VALUE>
+              <SHORT-NAME>SpiPublishedInformation</SHORT-NAME>
+              <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Spi/SpiPublishedInformation</DEFINITION-REF>
+              <PARAMETER-VALUES>
+                <ECUC-NUMERICAL-PARAM-VALUE>
+                  <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Spi/SpiPublishedInformation/SpiMaxHwUnit</DEFINITION-REF>
+                  <VALUE>0</VALUE>
+                </ECUC-NUMERICAL-PARAM-VALUE>
+              </PARAMETER-VALUES>
+            </ECUC-CONTAINER-VALUE>
+          </CONTAINERS>
+        </ECUC-MODULE-CONFIGURATION-VALUES>
+      </ELEMENTS>
+    </AR-PACKAGE>
+  </AR-PACKAGES>
+</AUTOSAR>

generate/output/Uart.epc

@@ -100,106 +100,6 @@
               <SHORT-NAME>UartGlobalConfig</SHORT-NAME>
               <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig</DEFINITION-REF>
               <SUB-CONTAINERS>
-                <ECUC-CONTAINER-VALUE>
-                  <SHORT-NAME>FLEXIO_RX</SHORT-NAME>
-                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel</DEFINITION-REF>
-                  <PARAMETER-VALUES>
-                    <ECUC-NUMERICAL-PARAM-VALUE>
-                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartChannelId</DEFINITION-REF>
-                      <VALUE>3</VALUE>
-                    </ECUC-NUMERICAL-PARAM-VALUE>
-                    <ECUC-TEXTUAL-PARAM-VALUE>
-                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartHwUsing</DEFINITION-REF>
-                      <VALUE>FLEXIO_IP</VALUE>
-                    </ECUC-TEXTUAL-PARAM-VALUE>
-                  </PARAMETER-VALUES>
-                  <REFERENCE-VALUES>
-                    <ECUC-REFERENCE-VALUE>
-                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartClockRef</DEFINITION-REF>
-                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcu/Mcu/McuModuleConfiguration/McuClockSettingConfig_0/McuClockReferencePoint_FLEXIO_CLK</VALUE-REF>
-                    </ECUC-REFERENCE-VALUE>
-                  </REFERENCE-VALUES>
-                  <SUB-CONTAINERS>
-                    <ECUC-CONTAINER-VALUE>
-                      <SHORT-NAME>FlexioModuleConfiguration</SHORT-NAME>
-                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration</DEFINITION-REF>
-                      <PARAMETER-VALUES>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/DesireBaudrate</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_BAUDRATE_9600</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/FlexioUartInteruptDmaMethod</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_DRIVER_TYPE_INTERRUPTS</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/bitCount</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_8_BITS_PER_CHAR</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/driverDirection</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_DIRECTION_RX</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                      </PARAMETER-VALUES>
-                      <REFERENCE-VALUES>
-                        <ECUC-REFERENCE-VALUE>
-                          <DEFINITION-REF DEST="ECUC-CHOICE-REFERENCE-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/UartHwChannelRef</DEFINITION-REF>
-                          <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcl/Mcl/MclConfig/FlexioCommon_0/FLEXIO_RX</VALUE-REF>
-                        </ECUC-REFERENCE-VALUE>
-                      </REFERENCE-VALUES>
-                    </ECUC-CONTAINER-VALUE>
-                  </SUB-CONTAINERS>
-                </ECUC-CONTAINER-VALUE>
-                <ECUC-CONTAINER-VALUE>
-                  <SHORT-NAME>FLEXIO_TX</SHORT-NAME>
-                  <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel</DEFINITION-REF>
-                  <PARAMETER-VALUES>
-                    <ECUC-NUMERICAL-PARAM-VALUE>
-                      <DEFINITION-REF DEST="ECUC-INTEGER-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartChannelId</DEFINITION-REF>
-                      <VALUE>4</VALUE>
-                    </ECUC-NUMERICAL-PARAM-VALUE>
-                    <ECUC-TEXTUAL-PARAM-VALUE>
-                      <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartHwUsing</DEFINITION-REF>
-                      <VALUE>FLEXIO_IP</VALUE>
-                    </ECUC-TEXTUAL-PARAM-VALUE>
-                  </PARAMETER-VALUES>
-                  <REFERENCE-VALUES>
-                    <ECUC-REFERENCE-VALUE>
-                      <DEFINITION-REF DEST="ECUC-REFERENCE-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/UartClockRef</DEFINITION-REF>
-                      <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcu/Mcu/McuModuleConfiguration/McuClockSettingConfig_0/McuClockReferencePoint_FLEXIO_CLK</VALUE-REF>
-                    </ECUC-REFERENCE-VALUE>
-                  </REFERENCE-VALUES>
-                  <SUB-CONTAINERS>
-                    <ECUC-CONTAINER-VALUE>
-                      <SHORT-NAME>FlexioModuleConfiguration</SHORT-NAME>
-                      <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration</DEFINITION-REF>
-                      <PARAMETER-VALUES>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/DesireBaudrate</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_BAUDRATE_9600</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/FlexioUartInteruptDmaMethod</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_DRIVER_TYPE_INTERRUPTS</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/bitCount</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_8_BITS_PER_CHAR</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                        <ECUC-TEXTUAL-PARAM-VALUE>
-                          <DEFINITION-REF DEST="ECUC-ENUMERATION-PARAM-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/driverDirection</DEFINITION-REF>
-                          <VALUE>FLEXIO_UART_IP_DIRECTION_TX</VALUE>
-                        </ECUC-TEXTUAL-PARAM-VALUE>
-                      </PARAMETER-VALUES>
-                      <REFERENCE-VALUES>
-                        <ECUC-REFERENCE-VALUE>
-                          <DEFINITION-REF DEST="ECUC-CHOICE-REFERENCE-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel/FlexioModuleConfiguration/UartHwChannelRef</DEFINITION-REF>
-                          <VALUE-REF DEST="ECUC-CONTAINER-VALUE">/Mcl/Mcl/MclConfig/FlexioCommon_0/FLEXIO_TX</VALUE-REF>
-                        </ECUC-REFERENCE-VALUE>
-                      </REFERENCE-VALUES>
-                    </ECUC-CONTAINER-VALUE>
-                  </SUB-CONTAINERS>
-                </ECUC-CONTAINER-VALUE>
                 <ECUC-CONTAINER-VALUE>
                   <SHORT-NAME>LPUART0_RS485</SHORT-NAME>
                   <DEFINITION-REF DEST="ECUC-PARAM-CONF-CONTAINER-DEF">/TS_T40D2M10I0R0/Uart/UartGlobalConfig/UartChannel</DEFINITION-REF>

generate/src/Can_VS_0_PBcfg.c

@@ -502,14 +502,14 @@ static const Can_BaudrateConfigType Can_aBaudrateConfig_Ctrl0[1U]=
         /* Nominal bit rate */
         {
             (uint8)2U,
-            (uint8)5U,
-            (uint8)5U,
-            (uint16)11U,
+            (uint8)1U,
+            (uint8)1U,
+            (uint16)7U,
             #if (CAN_DUAL_CLOCK_MODE == STD_ON)
             /* Alternative Baudrate Nominal Prescaler */
             (uint16)9U,
             #endif
-            (uint8)3U
+            (uint8)1U
         },
         
         /* Data bit rate */
@@ -554,14 +554,14 @@ static const Can_BaudrateConfigType Can_aBaudrateConfig_Ctrl1[1U]=
         /* Nominal bit rate */
         {
             (uint8)2U,
-            (uint8)5U,
-            (uint8)5U,
-            (uint16)11U,
+            (uint8)1U,
+            (uint8)1U,
+            (uint16)7U,
             #if (CAN_DUAL_CLOCK_MODE == STD_ON)
             /* Alternative Baudrate Nominal Prescaler */
             (uint16)9U,
             #endif
-            (uint8)3U
+            (uint8)1U
         },
         
         /* Data bit rate */

generate/src/Clock_Ip_VS_0_PBcfg.c

@@ -176,9 +176,9 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         0U,                                 /* clkConfigId */
         1U,                                 /* ircoscsCount */
         1U,                                 /* xoscsCount */
-        0U,                                 /* pllsCount */
+        1U,                                 /* pllsCount */
         22U,                                /* selectorsCount */
-        14U,                                /* dividersCount */
+        16U,                                /* dividersCount */
         0U,                                 /* dividerTriggersCount */
         0U,                                /* fracDivsCount */
         4U,                                /* extClksCount */
@@ -214,7 +214,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_XOSCS_NO > 0U
             {
                 SOSC_CLK,                    /* Clock name associated to xosc */
-                8000000U,                    /* External oscillator frequency. */
+                16000000U,                    /* External oscillator frequency. */
                 1U,                           /* Enable xosc. */
                 0U,                         /* Startup stabilization time. */
                 0U,                           /* XOSC bypass option */
@@ -229,23 +229,23 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
 
         /* PLL initialization. */
         {
-                #if CLOCK_PLLS_NO > 0U
+            #if CLOCK_PLLS_NO > 0U
             {
-                RESERVED_CLK,           /* name */
-                0U,                     /* enable */
-                RESERVED_CLK,           /* inputReference */
-                0U,                     /* Bypass */
-                0U,                     /* predivider */
-                0U,                     /* numeratorFracLoopDiv */
-                0U,                     /* mulFactorDiv */
-                0U,                     /* modulation */
-                0U,                     /* Modulaton type: Spread spectrum modulation bypassed */
-                0U,                     /* modulationPeriod */
-                0U,                     /* incrementStep */
-                0U,                     /* sigmaDelta */
-                0U,                     /* ditherControl */
-                0U,                     /* ditherControlValue */
-                0U,                     /* Monitor type  */
+                SPLL_CLK,                  /*!<     name;                    */
+                1U,                           /*!<     enable;                  */
+                SOSC_CLK,                    /*!<     inputReference           */
+                0U,                           /*!<     bypass;                  */
+                1U,                           /*!<     predivider;              */
+                0U,                           /*!<     numeratorFracLoopDiv;    */
+                20U,                          /*!<     mulFactorDiv;            */
+                0U,                           /*!<     modulation;              */
+                0U,                           /*!<     modulationType;          */
+                0U,                           /*!<     modulationPeriod;        */
+                0U,                           /*!<     incrementStep;           */
+                0U,                           /*!<     sigmaDelta;              */
+                0U,                           /*!<     ditherControl;           */
+                0U,                           /*!<     ditherControlValue;      */
+                FEATURE_CLOCK_IP_HAS_MONITOR_INT,        /*!<     Monitor type             */
             },
             #endif
 
@@ -257,7 +257,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_SELECTORS_NO > 0U
             {
                 SCS_RUN_CLK,                     /* Clock name associated to selector */
-                FIRC_CLK,                       /* Name of the selected input source */
+                SPLL_CLK,                       /* Name of the selected input source */
             },
             #endif
         
@@ -271,14 +271,14 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_SELECTORS_NO > 2U
             {
                 SCS_HSRUN_CLK,                     /* Clock name associated to selector */
-                FIRC_CLK,                       /* Name of the selected input source */
+                SPLL_CLK,                       /* Name of the selected input source */
             },
             #endif
         
             #if CLOCK_SELECTORS_NO > 3U
             {
                 SCG_CLKOUT_CLK,                     /* Clock name associated to selector */
-                SLOW_CLK,                       /* Name of the selected input source */
+                SPLL_CLK,                       /* Name of the selected input source */
             },
             #endif
         
@@ -348,7 +348,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_SELECTORS_NO > 13U
             {
                 LPSPI2_CLK,                     /* Clock name associated to selector */
-                CLOCK_IS_OFF,                       /* Name of the selected input source */
+                SPLLDIV2_CLK,                       /* Name of the selected input source */
             },
             #endif
         
@@ -383,21 +383,21 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_SELECTORS_NO > 18U
             {
                 LPUART0_CLK,                     /* Clock name associated to selector */
-                SIRCDIV2_CLK,                       /* Name of the selected input source */
+                SOSCDIV2_CLK,                       /* Name of the selected input source */
             },
             #endif
         
             #if CLOCK_SELECTORS_NO > 19U
             {
                 LPUART1_CLK,                     /* Clock name associated to selector */
-                SIRCDIV2_CLK,                       /* Name of the selected input source */
+                SOSCDIV2_CLK,                       /* Name of the selected input source */
             },
             #endif
         
             #if CLOCK_SELECTORS_NO > 20U
             {
                 LPUART2_CLK,                     /* Clock name associated to selector */
-                SIRCDIV2_CLK,                       /* Name of the selected input source */
+                SOSCDIV2_CLK,                       /* Name of the selected input source */
             },
             #endif
         
@@ -486,7 +486,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
             #if CLOCK_DIVIDERS_NO > 2U
             {
                 SOSCDIV1_CLK,
-                1U,
+                4U,
                 {
                     0U,
                 }
@@ -505,8 +505,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 4U
             {
-                CORE_RUN_CLK,
-                1U,
+                SPLLDIV1_CLK,
+                2U,
                 {
                     0U,
                 }
@@ -515,8 +515,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 5U
             {
-                CORE_VLPR_CLK,
-                8U,
+                SPLLDIV2_CLK,
+                4U,
                 {
                     0U,
                 }
@@ -525,8 +525,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 6U
             {
-                CORE_HSRUN_CLK,
-                1U,
+                CORE_RUN_CLK,
+                2U,
                 {
                     0U,
                 }
@@ -535,8 +535,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 7U
             {
-                BUS_RUN_CLK,
-                1U,
+                CORE_VLPR_CLK,
+                4U,
                 {
                     0U,
                 }
@@ -545,8 +545,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 8U
             {
-                BUS_VLPR_CLK,
-                8U,
+                CORE_HSRUN_CLK,
+                2U,
                 {
                     0U,
                 }
@@ -555,8 +555,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 9U
             {
-                BUS_HSRUN_CLK,
-                1U,
+                BUS_RUN_CLK,
+                2U,
                 {
                     0U,
                 }
@@ -565,8 +565,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 10U
             {
-                SLOW_RUN_CLK,
-                2U,
+                BUS_VLPR_CLK,
+                4U,
                 {
                     0U,
                 }
@@ -575,8 +575,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 11U
             {
-                SLOW_VLPR_CLK,
-                4U,
+                BUS_HSRUN_CLK,
+                2U,
                 {
                     0U,
                 }
@@ -585,8 +585,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 12U
             {
-                SLOW_HSRUN_CLK,
-                2U,
+                SLOW_RUN_CLK,
+                4U,
                 {
                     0U,
                 }
@@ -595,29 +595,33 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
         
             #if CLOCK_DIVIDERS_NO > 13U
             {
-                LPTMR0_CLK,
-                1U,
+                SLOW_VLPR_CLK,
+                2U,
                 {
-                    1U,
+                    0U,
                 }
             },
             #endif
         
+            #if CLOCK_DIVIDERS_NO > 14U
             {
-                RESERVED_CLK,
-                0U,
+                SLOW_HSRUN_CLK,
+                4U,
                 {
                     0U,
-                },
+                }
             },
+            #endif
         
+            #if CLOCK_DIVIDERS_NO > 15U
             {
-                RESERVED_CLK,
-                0U,
+                LPTMR0_CLK,
+                1U,
                 {
-                    0U,
-                },
+                    1U,
+                }
             },
+            #endif
         
             {
                 RESERVED_CLK,

generate/src/FlexCAN_Ip_VS_0_PBcfg.c

@@ -150,17 +150,17 @@ const Flexcan_Ip_ConfigType Flexcan_aCtrlConfigPB_VS_0[2U]=
         /* Values for normal baudrate .bitrate */
         {
             (uint8)2U,
-            (uint8)5U,
-            (uint8)5U,
-            (uint16)11,
-            (uint8)3U
+            (uint8)1U,
+            (uint8)1U,
+            (uint16)7,
+            (uint8)1U
         },
         /* Values for CBT baudrate .bitrate_cbt */
         {
             (uint8)5U,
             (uint8)4U,
             (uint8)5U,
-            (uint16)11U,
+            (uint16)7U,
             (uint8)0U
         },
         /* Fifo Transfer Type .transfer_type */
@@ -213,17 +213,17 @@ const Flexcan_Ip_ConfigType Flexcan_aCtrlConfigPB_VS_0[2U]=
         /* Values for normal baudrate .bitrate */
         {
             (uint8)2U,
-            (uint8)5U,
-            (uint8)5U,
-            (uint16)11,
-            (uint8)3U
+            (uint8)1U,
+            (uint8)1U,
+            (uint16)7,
+            (uint8)1U
         },
         /* Values for CBT baudrate .bitrate_cbt */
         {
             (uint8)5U,
             (uint8)4U,
             (uint8)5U,
-            (uint16)11U,
+            (uint16)7U,
             (uint8)0U
         },
         /* Fifo Transfer Type .transfer_type */

generate/src/Flexio_Spi_Ip_VS_0_PBcfg.c

@@ -0,0 +1,155 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**   
+*   @file     Flexio_Spi_Ip_VS_0_PBcfg.c
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup FLEXIO_DRIVER_CONFIGURATION  Flexio_Spi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Flexio_Spi_Ip.h"
+
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+#if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+#include "Dma_Ip.h"
+#endif
+#endif
+
+/*==================================================================================================
+*                                    SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define FLEXIO_SPI_IP_VS_0_VENDOR_ID_PBCFG_C                        43
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C         4
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C         4
+#define FLEXIO_SPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C      0
+#define FLEXIO_SPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG_C                 1
+#define FLEXIO_SPI_IP_VS_0_SW_MINOR_VERSION_PBCFG_C                 0
+#define FLEXIO_SPI_IP_VS_0_SW_PATCH_VERSION_PBCFG_C                 0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Flexio_Spi_Ip__VS_0_PBcfg source file and Spi configuration header file are of the same vendor */
+#if (FLEXIO_SPI_IP_VS_0_VENDOR_ID_PBCFG_C != FLEXIO_SPI_IP_VENDOR_ID)
+    #error "Flexio_Spi_Ip_VS_0_PBcfg.c and Flexio_Spi_Ip.h have different vendor IDs"
+#endif
+
+#if ((FLEXIO_SPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C    != FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C    != FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C != FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip_VS_0_PBcfg.h and Flexio_Spi_Ip.h are different"
+#endif
+/* Check if Flexio_Spi_Ip__VS_0_PBcfg header file and Spi configuration header file are of the same software version */
+#if ((FLEXIO_SPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG_C != FLEXIO_SPI_IP_SW_MAJOR_VERSION) || \
+     (FLEXIO_SPI_IP_VS_0_SW_MINOR_VERSION_PBCFG_C != FLEXIO_SPI_IP_SW_MINOR_VERSION) || \
+     (FLEXIO_SPI_IP_VS_0_SW_PATCH_VERSION_PBCFG_C != FLEXIO_SPI_IP_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Flexio_Spi_Ip_VS_0_PBcfg.h and Flexio_Spi_Ip.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    #if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+    #if (FLEXIO_SPI_IP_DMA_USED == STD_ON)
+        #if ((FLEXIO_SPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C != DMA_IP_AR_RELEASE_MAJOR_VERSION_H) || \
+             (FLEXIO_SPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C != DMA_IP_AR_RELEASE_MINOR_VERSION_H) \
+            )
+            #error "AutoSar Version Numbers of Flexio_Spi_Ip_VS_0_PBcfg.h and Dma_Ip.h are different"
+        #endif
+    #endif /* (FLEXIO_SPI_IP_DMA_USED == STD_ON) */
+    #endif /* (FLEXIO_SPI_IP_ENABLE == STD_ON) */
+#endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
+
+
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL VARIABLES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL VARIABLES
+==================================================================================================*/
+#if (FLEXIO_SPI_IP_ENABLE == STD_ON)
+
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#endif /*(FLEXIO_SPI_IP_ENABLE == STD_ON)*/
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

generate/src/Flexio_Uart_Ip_VS_0_PBcfg.c

@@ -122,7 +122,7 @@ extern "C"{
 ==================================================================================================*/
 #define UART_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
 #include "Uart_MemMap.h"
-extern Flexio_Uart_Ip_StateStructureType Flexio_Uart_Ip_apStateStructure[2U];
+
 #define UART_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
 #include "Uart_MemMap.h"
 
@@ -130,84 +130,6 @@ extern Flexio_Uart_Ip_StateStructureType Flexio_Uart_Ip_apStateStructure[2U];
 #include "Uart_MemMap.h"
 
 
-/**
-* @brief          Hardware configuration for Uart Hardware - Configuration:
-*
-* @api
-*/
-const Flexio_Uart_Ip_UserConfigType Flexio_Uart_Ip_xHwConfigPB_3_VS_0 =
-{
-
-    /*!< Flexio Uart Channel has been configured */
-    0U,
-    /*!< Driver type: interrupts/DMA */
-    FLEXIO_UART_IP_DRIVER_TYPE_INTERRUPTS,
-    /*!< Baudrate divider */
-    207U,
-    /*!< The source of the Timer decrement and the source of the Shift clock */
-    FLEXIO_TIMER_DECREMENT_FXIO_CLK_SHIFT_TMR,
-    /*!< Baud rate in hertz */
-    9615U,
-    /*!< Number of bits per word */
-    FLEXIO_UART_IP_8_BITS_PER_CHAR,
-    /*!< Driver direction: Tx or Rx */
-    FLEXIO_UART_IP_DIRECTION_RX,
-    /*!< Flexio pin to use as Tx or Rx pin */
-    6U,
-    /*!< User callback function. Note that this function will be
-        called from the interrupt service routine, so itsexecution time
-        should be as small as possible. It can be NULL if it is not needed */
-    NULL_PTR,
-    /* Callback parameter pointer.*/
-    NULL_PTR,
-#if (FLEXIO_UART_IP_HAS_DMA_ENABLED == STD_ON)
-    /* DMA channel number for DMA-based Rx or DMA-based Tx. */
-    255,
-
-#endif
-    &Flexio_Uart_Ip_apStateStructure[0]
-
-};
-
-/**
-* @brief          Hardware configuration for Uart Hardware - Configuration:
-*
-* @api
-*/
-const Flexio_Uart_Ip_UserConfigType Flexio_Uart_Ip_xHwConfigPB_4_VS_0 =
-{
-
-    /*!< Flexio Uart Channel has been configured */
-    1U,
-    /*!< Driver type: interrupts/DMA */
-    FLEXIO_UART_IP_DRIVER_TYPE_INTERRUPTS,
-    /*!< Baudrate divider */
-    207U,
-    /*!< The source of the Timer decrement and the source of the Shift clock */
-    FLEXIO_TIMER_DECREMENT_FXIO_CLK_SHIFT_TMR,
-    /*!< Baud rate in hertz */
-    9615U,
-    /*!< Number of bits per word */
-    FLEXIO_UART_IP_8_BITS_PER_CHAR,
-    /*!< Driver direction: Tx or Rx */
-    FLEXIO_UART_IP_DIRECTION_TX,
-    /*!< Flexio pin to use as Tx or Rx pin */
-    7U,
-    /*!< User callback function. Note that this function will be
-        called from the interrupt service routine, so itsexecution time
-        should be as small as possible. It can be NULL if it is not needed */
-    NULL_PTR,
-    /* Callback parameter pointer.*/
-    NULL_PTR,
-#if (FLEXIO_UART_IP_HAS_DMA_ENABLED == STD_ON)
-    /* DMA channel number for DMA-based Rx or DMA-based Tx. */
-    255,
-
-#endif
-    &Flexio_Uart_Ip_apStateStructure[1]
-
-};
-
 #define UART_STOP_SEC_CONFIG_DATA_UNSPECIFIED
 #include "Uart_MemMap.h"
 /*==================================================================================================

generate/src/IntCtrl_Ip_Cfg.c

@@ -67,8 +67,8 @@ static const IntCtrl_Ip_IrqConfigType aIrqConfiguration[] = {
     {DMA3_IRQn, (boolean)TRUE, 3U},
     {DMA4_IRQn, (boolean)TRUE, 3U},
     {DMA5_IRQn, (boolean)TRUE, 3U},
-    {DMA6_IRQn, (boolean)FALSE, 0U},
-    {DMA7_IRQn, (boolean)FALSE, 0U},
+    {DMA6_IRQn, (boolean)TRUE, 3U},
+    {DMA7_IRQn, (boolean)TRUE, 3U},
     {DMA8_IRQn, (boolean)FALSE, 0U},
     {DMA9_IRQn, (boolean)FALSE, 0U},
     {DMA10_IRQn, (boolean)FALSE, 0U},
@@ -89,7 +89,7 @@ static const IntCtrl_Ip_IrqConfigType aIrqConfiguration[] = {
     {LPI2C0_Slave_IRQn, (boolean)TRUE, 0U},
     {LPSPI0_IRQn, (boolean)FALSE, 0U},
     {LPSPI1_IRQn, (boolean)FALSE, 0U},
-    {LPSPI2_IRQn, (boolean)TRUE, 0U},
+    {LPSPI2_IRQn, (boolean)TRUE, 3U},
     {LPUART0_RxTx_IRQn, (boolean)TRUE, 3U},
     {LPUART1_RxTx_IRQn, (boolean)TRUE, 3U},
     {LPUART2_RxTx_IRQn, (boolean)TRUE, 3U},
@@ -179,8 +179,8 @@ static const IntCtrl_Ip_IrqRouteConfigType aIrqRouteConfig[] = {
         {DMA3_IRQn, 0U, Dma0_Ch3_IRQHandler},
         {DMA4_IRQn, 0U, Dma0_Ch4_IRQHandler},
         {DMA5_IRQn, 0U, Dma0_Ch5_IRQHandler},
-        {DMA6_IRQn, 0U, undefined_handler},
-        {DMA7_IRQn, 0U, undefined_handler},
+        {DMA6_IRQn, 0U, Dma0_Ch6_IRQHandler},
+        {DMA7_IRQn, 0U, Dma0_Ch7_IRQHandler},
         {DMA8_IRQn, 0U, undefined_handler},
         {DMA9_IRQn, 0U, undefined_handler},
         {DMA10_IRQn, 0U, undefined_handler},
@@ -201,7 +201,7 @@ static const IntCtrl_Ip_IrqRouteConfigType aIrqRouteConfig[] = {
         {LPI2C0_Slave_IRQn, 0U, undefined_handler},
         {LPSPI0_IRQn, 0U, undefined_handler},
         {LPSPI1_IRQn, 0U, undefined_handler},
-        {LPSPI2_IRQn, 0U, undefined_handler},
+        {LPSPI2_IRQn, 0U, Lpspi_Ip_LPSPI_2_IRQHandler},
         {LPUART0_RxTx_IRQn, 0U, LPUART_UART_IP_0_IRQHandler},
         {LPUART1_RxTx_IRQn, 0U, LPUART_UART_IP_1_IRQHandler},
         {LPUART2_RxTx_IRQn, 0U, LPUART_UART_IP_2_IRQHandler},

generate/src/Lpspi_Ip_VS_0_PBcfg.c

@@ -0,0 +1,221 @@
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+
+/**
+*   @file    Lpspi_Ip_VS_0_PBcfg.c
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup LPSPI_DRIVER_CONFIGURATION Lpspi Driver Configuration
+*   @{
+*/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Lpspi_Ip.h"
+#if (LPSPI_IP_DMA_USED == STD_ON)
+#include "Dma_Ip.h"
+#endif
+/*==================================================================================================
+*                                    SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+
+#define LPSPI_IP_VS_0_VENDOR_ID_PBCFG_C                        43
+#define LPSPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C         4
+#define LPSPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C         4
+#define LPSPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C      0
+#define LPSPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG_C                 1
+#define LPSPI_IP_VS_0_SW_MINOR_VERSION_PBCFG_C                 0
+#define LPSPI_IP_VS_0_SW_PATCH_VERSION_PBCFG_C                 0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Lpspi_Ip.h and Lpspi_Ip_PBcfg.c are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID != LPSPI_IP_VS_0_VENDOR_ID_PBCFG_C)
+    #error "Lpspi_Ip.h and Lpspi_Ip_PBcfg.c have different vendor ids"
+#endif
+/* Check if Lpspi_Ip.h file and Lpspi_Ip_PBcfg.c file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION != LPSPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION != LPSPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION != LPSPI_IP_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C))
+#error "AutoSar Version Numbers of Lpspi_Ip.h and Lpspi_Ip_PBcfg.c are different"
+#endif
+#if ((LPSPI_IP_SW_MAJOR_VERSION != LPSPI_IP_VS_0_SW_MAJOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_SW_MINOR_VERSION != LPSPI_IP_VS_0_SW_MINOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_SW_PATCH_VERSION != LPSPI_IP_VS_0_SW_PATCH_VERSION_PBCFG_C))
+#error "Software Version Numbers of Lpspi_Ip.h and Lpspi_Ip_PBcfg.c are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+    #if (LPSPI_IP_DMA_USED == STD_ON)
+        /* Check if current file and Dma_Ip header file are of the same Autosar version */
+        #if ((DMA_IP_AR_RELEASE_MAJOR_VERSION_H != LPSPI_IP_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+             (DMA_IP_AR_RELEASE_MINOR_VERSION_H != LPSPI_IP_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C))
+        #error "AutoSar Version Numbers of Lpspi_Ip_Cfg.h and Dma_Ip.h are different"
+        #endif
+    #endif
+#endif
+/*==================================================================================================
+*                                        LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                          LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL VARIABLES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL VARIABLES
+==================================================================================================*/
+
+#if (LPSPI_IP_DMA_USED == STD_ON)
+    #define SPI_START_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_START_SEC_VAR_INIT_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+
+/* Spi_Ip_DeviceParamsCfg_VS_0 Device Attribute Configuration of Spi*/
+static Lpspi_Ip_DeviceParamsType Lpspi_Ip_DeviceParamsCfg_VS_0[1U] =
+{
+
+    {
+        (uint8)8U, /* Frame size - dummy value */
+        (boolean)TRUE, /*Lsb - dummy value */
+        (uint32)1U  /* Default Data - dummy value */
+#if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT)        
+        , LPSPI_IP_FULL_DUPLEX /* Transfer mode - dummy value */
+#endif
+    }            
+};
+
+#if (LPSPI_IP_DMA_USED == STD_ON)
+    #define SPI_STOP_SEC_VAR_INIT_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_STOP_SEC_VAR_INIT_UNSPECIFIED
+#endif
+#include "Spi_MemMap.h"
+
+#if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+#define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#include "Spi_MemMap.h"
+
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#include "Spi_MemMap.h"
+#endif /*(LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)*/
+
+
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/* Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_VS_0 Device Attribute Configuration of Spi*/
+const Lpspi_Ip_ExternalDeviceType Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_VS_0 =
+{
+    2U,  /* Instance */
+        (uint32)(LPSPI_CCR_SCKPCS(119U) | LPSPI_CCR_PCSSCK(39U) | LPSPI_CCR_SCKDIV(38U) | LPSPI_CCR_DBT(79U)), /* CCR */
+                (uint32)LPSPI_TCR_WIDTH(0U) | (LPSPI_TCR_CPOL(1U) | LPSPI_TCR_CPHA(1U) | LPSPI_TCR_PRESCALE(0U) |         LPSPI_TCR_PCS(0U) | LPSPI_TCR_CONT(1U)) /* TCR */
+        
+    #if (STD_ON == LPSPI_IP_HALF_DUPLEX_MODE_SUPPORT) 
+    ,(uint32)0U /* This device do not support half duplex mode */    
+    #endif
+    
+    ,&Lpspi_Ip_DeviceParamsCfg_VS_0[0U]
+};
+/* The SPI Hw Unit configuration structures */
+const Lpspi_Ip_ConfigType Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_VS_0 =
+{
+    2U,  /* Instance */
+    /* CR */
+    (uint32)0,
+    /* CFGR1 */
+    (uint32)(LPSPI_CFGR1_PINCFG(0U) | LPSPI_CFGR1_PCSPOL(0U) | LPSPI_CFGR1_MASTER(1U) | LPSPI_CFGR1_SAMPLE(0U)),
+    #if (LPSPI_IP_SLAVE_SUPPORT == STD_ON)
+    (boolean)FALSE,
+    #endif
+    #if (LPSPI_IP_DMA_USED == STD_ON)
+    (boolean)FALSE,
+    (uint8)0U, /* txDmaChannel */
+    (uint8)0U, /* rxDmaChannel */
+    #if (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON)
+    (uint8)0U, /* u8NumOfDmaFastTransfer */
+    NULL_PTR, /* pCmdDmaFast */
+    (uint8)0U,
+    (uint8)0U,
+    NULL_PTR, /* List of Tx SG Id */
+    NULL_PTR, /* List of Rx SG Id */
+    #endif
+    #endif  /* (LPSPI_IP_DMA_USED == STD_ON) */
+    LPSPI_IP_POLLING, /* Transfer mode */
+    (uint8)0U /* State structure element from the array */
+};
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+                                   LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       LOCAL FUNCTIONS
+==================================================================================================*/
+
+
+/*==================================================================================================
+                                       GLOBAL FUNCTIONS
+==================================================================================================*/
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */

generate/src/Lpuart_Uart_Ip_VS_0_PBcfg.c

@@ -156,11 +156,11 @@ const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_0_VS_0 =
 {
 
     /*!< Baud rate in hertz */
-    9615U,
+    9603U,
     /* Baud clock divisor*/
-    13U,
+    98U,
     /* Over sampling ratio*/
-    32U,
+    17U,
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */
@@ -193,11 +193,11 @@ const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_1_VS_0 =
 {
 
     /*!< Baud rate in hertz */
-    117647U,
+    115942U,
     /* Baud clock divisor*/
-    2U,
+    6U,
     /* Over sampling ratio*/
-    17U,
+    23U,
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */
@@ -230,11 +230,11 @@ const Lpuart_Uart_Ip_UserConfigType Lpuart_Uart_Ip_xHwConfigPB_2_VS_0 =
 {
 
     /*!< Baud rate in hertz */
-    9615U,
+    9603U,
     /* Baud clock divisor*/
-    13U,
+    98U,
     /* Over sampling ratio*/
-    32U,
+    17U,
     /* Parity type */
     LPUART_UART_IP_PARITY_DISABLED,
     /* Number of stop bits, 1 stop bit (default) or 2 stop bits */

generate/src/Mcu_VS_0_PBcfg.c

@@ -152,7 +152,7 @@ const Mcu_ConfigType Mcu_PreCompileConfig =
     (Mcu_RamSectionType)0U,
 
     /* Number of Power Modes configurations. */
-    (Mcu_ModeType)1U,
+    (Mcu_ModeType)3U,
 
 #if (MCU_INIT_CLOCK == STD_ON)
     /* Number of Clock Setting configurations. */

generate/src/OsIf_Cfg.c

@@ -138,7 +138,7 @@ extern "C"{
 static const OsIf_ConfigType OsIf_xPredefinedConfig =
 {
     /*.counterId */         0U,
-    /*.counterFrequency */  4000000U
+    /*.counterFrequency */  16000000U
 };
 
 #define BASE_STOP_SEC_CONFIG_DATA_UNSPECIFIED

generate/src/Port_Ci_Port_Ip_VS_0_PBcfg.c

@@ -317,7 +317,7 @@ const Port_Ci_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr_VS_0[NUM_OF_CONF
         .pinPortIdx                  = 0,
         .mux                         = PORT_MUX_ALT3,
         .direction                   = PORT_CI_PORT_PIN_IN,
-        .pullConfig                  = PORT_INTERNAL_PULL_NOT_ENABLED,
+        .pullConfig                  = PORT_INTERNAL_PULL_UP_ENABLED,
         .driveStrength               = PORT_DRIVE_STRENGTH_LOW,
         .passiveFilter               = (boolean)FALSE,
         .lockRegister                = PORT_LOCK_REGISTER_DISABLED,
@@ -329,6 +329,18 @@ const Port_Ci_Port_Ip_PinSettingsConfig g_pin_mux_InitConfigArr_VS_0[NUM_OF_CONF
         .pinPortIdx                  = 1,
         .mux                         = PORT_MUX_ALT3,
         .direction                   = PORT_CI_PORT_PIN_OUT,
+        .pullConfig                  = PORT_INTERNAL_PULL_UP_ENABLED,
+        .driveStrength               = PORT_DRIVE_STRENGTH_LOW,
+        .passiveFilter               = (boolean)FALSE,
+        .lockRegister                = PORT_LOCK_REGISTER_DISABLED,
+        .digitalFilter               = (boolean)FALSE
+    },
+    {
+        .portBase                    = IP_PORTC,
+        .gpioBase                    = NULL_PTR,
+        .pinPortIdx                  = 14,
+        .mux                         = PORT_MUX_ALT3,
+        .direction                   = PORT_CI_PORT_PIN_OUT,
         .pullConfig                  = PORT_INTERNAL_PULL_NOT_ENABLED,
         .driveStrength               = PORT_DRIVE_STRENGTH_LOW,
         .passiveFilter               = (boolean)FALSE,

generate/src/Port_VS_0_PBcfg.c

@@ -167,6 +167,7 @@ static const uint32 au32Port_PinToPartitionMap_VS_0[PORT_MAX_CONFIGURED_PADS_U16
     (uint32)0x00000001,
     (uint32)0x00000001,
     (uint32)0x00000001,
+    (uint32)0x00000001,
     (uint32)0x00000001
 };
 #define PORT_STOP_SEC_CONFIG_DATA_32
@@ -221,7 +222,6 @@ static const uint16 Port_au16NoUnUsedPadsArrayDefault_VS_0[PORT_MAX_UNUSED_PADS_
     (uint16)75,
     (uint16)76,
     (uint16)77,
-    (uint16)78,
     (uint16)80,
     (uint16)81,
     (uint16)83,
@@ -319,9 +319,9 @@ static const Port_PinConfigType Port_aPinConfigDefault_VS_0[PORT_MAX_CONFIGURED_
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
     {(uint16)79, (uint32)0x00000300, (uint8)1, (Port_PinDirectionType)2, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
-    {(uint16)64, (uint32)0x00000300, (uint8)1, (Port_PinDirectionType)1, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
+    {(uint16)64, (uint32)0x00000303, (uint8)1, (Port_PinDirectionType)1, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
-    {(uint16)65, (uint32)0x00000300, (uint8)1, (Port_PinDirectionType)2, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
+    {(uint16)65, (uint32)0x00000303, (uint8)1, (Port_PinDirectionType)2, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
     {(uint16)139, (uint32)0x00000300, (uint8)0, (Port_PinDirectionType)1, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE},
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
@@ -363,7 +363,9 @@ static const Port_PinConfigType Port_aPinConfigDefault_VS_0[PORT_MAX_CONFIGURED_
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
     {(uint16)137, (uint32)0x00000100, (uint8)1, (Port_PinDirectionType)2, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE},
     /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
-    {(uint16)36, (uint32)0x00000100, (uint8)0, (Port_PinDirectionType)2, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE}
+    {(uint16)36, (uint32)0x00000100, (uint8)0, (Port_PinDirectionType)2, (boolean)TRUE, (boolean)TRUE, (boolean)TRUE},
+    /* PCR Id, PCR Value, Output Level, Direction, IsGpio, Direction Configurable, Mode Changeable */
+    {(uint16)78, (uint32)0x00000300, (uint8)1, (Port_PinDirectionType)2, (boolean)FALSE, (boolean)FALSE, (boolean)TRUE}
 
 };
 

generate/src/Power_Ip_VS_0_PBcfg.c

@@ -189,13 +189,13 @@ static const Power_Ip_PMC_ConfigType Power_Ip_PMC_ConfigPB_VS_0 =
     
     /* Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1). This register only exist on 1xx series of devices */
     (
-        PMC_LVDSC1_LVD_DISABLE_U8 |
-        PMC_LVDSC1_LVDRE_DISABLE_U8
+        PMC_LVDSC1_LVD_ENABLE_U8 |
+        PMC_LVDSC1_LVDRE_ENABLE_U8
     ),
     
     /* Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2) */
     (
-        PMC_LVDSC2_LVW_DISABLE_U8
+        PMC_LVDSC2_LVW_ENABLE_U8
     ),
     /* Regulator Status and Control Register (PMC_REGSC) */
     (
@@ -217,8 +217,8 @@ static const Power_Ip_SMC_ConfigType Power_Ip_SMC_ConfigPB_VS_0 =
 {
     /* Allowed modes */
     (
-        SMC_PMPROT_HSRUN_NOT_ALLOWED_U32 |
-        SMC_PMPROT_VLP_NOT_ALLOWED_U32
+        SMC_PMPROT_HSRUN_ALLOWED_U32 |
+        SMC_PMPROT_VLP_ALLOWED_U32
     ),
 };
 
@@ -229,7 +229,7 @@ static const Power_Ip_SMC_ConfigType Power_Ip_SMC_ConfigPB_VS_0 =
 * @details        Static configuration realized by calling Mcu_SetMode() API.
 *
 */
-const Power_Ip_ModeConfigType Power_Ip_aModeConfigPB_VS_0[1U] =
+const Power_Ip_ModeConfigType Power_Ip_aModeConfigPB_VS_0[3U] =
 {
     /* Start of Mcu_aModeConfig[0] */
     {
@@ -241,7 +241,29 @@ const Power_Ip_ModeConfigType Power_Ip_aModeConfigPB_VS_0[1U] =
 
         /* The Sleep On Exit configuration */
         0U,
-    } /* End of Mcu_aModeConfig[0] */
+    }, /* End of Mcu_aModeConfig[0] */
+    /* Start of Mcu_aModeConfig[1] */
+    {
+        /* Mode Configuration ID. */
+        (Power_Ip_ModeType)1U,
+
+        /* The Power Mode name (code). */
+        POWER_IP_HSRUN_MODE,
+
+        /* The Sleep On Exit configuration */
+        0U,
+    }, /* End of Mcu_aModeConfig[1] */
+    /* Start of Mcu_aModeConfig[2] */
+    {
+        /* Mode Configuration ID. */
+        (Power_Ip_ModeType)2U,
+
+        /* The Power Mode name (code). */
+        POWER_IP_VLPR_MODE,
+
+        /* The Sleep On Exit configuration */
+        0U,
+    } /* End of Mcu_aModeConfig[2] */
 };
 
 

generate/src/Spi_Ipw_VS_0_PBcfg.c

@@ -0,0 +1,234 @@
+/**   
+*   @file    Spi_Ipw_VS_0_PBcfg.c
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+#include "Spi_Ipw_VS_0_PBcfg.h"
+#include "Lpspi_Ip_Cfg.h"
+#include "Flexio_Spi_Ip_Cfg.h"
+#include "Spi.h"
+
+
+/*==================================================================================================
+*                                    SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_IPW_VS_0_VENDOR_ID_PBCFG_C                        43
+#define SPI_IPW_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C         4
+#define SPI_IPW_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C         4
+#define SPI_IPW_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C      0
+#define SPI_IPW_VS_0_SW_MAJOR_VERSION_PBCFG_C                 1
+#define SPI_IPW_VS_0_SW_MINOR_VERSION_PBCFG_C                 0
+#define SPI_IPW_VS_0_SW_PATCH_VERSION_PBCFG_C                 0
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if Spi_Ipw_PBcfg.h and Spi_Ipw_PBcfg.c are of the same vendor */
+#if (SPI_IPW_VENDOR_ID_VS_0_PBCFG_H != SPI_IPW_VS_0_VENDOR_ID_PBCFG_C)
+    #error "Spi_Ipw_PBcfg.h and Spi_Ipw_PBcfg.c have different vendor ids"
+#endif
+/* Check if Spi_Ipw_PBcfg.h file and Spi_Ipw_PBcfg.c file are of the same Autosar version */
+#if ((SPI_IPW_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+     (SPI_IPW_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C) || \
+     (SPI_IPW_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C))
+    #error "AutoSar Version Numbers of Spi_Ipw_PBcfg.h and Spi_Ipw_PBcfg.c are different"
+#endif
+#if ((SPI_IPW_SW_MAJOR_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_SW_MAJOR_VERSION_PBCFG_C) || \
+     (SPI_IPW_SW_MINOR_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_SW_MINOR_VERSION_PBCFG_C) || \
+     (SPI_IPW_SW_PATCH_VERSION_VS_0_PBCFG_H != SPI_IPW_VS_0_SW_PATCH_VERSION_PBCFG_C))
+    #error "Software Version Numbers of Spi_Ipw_PBcfg.h and Spi_Ipw_PBcfg.c are different"
+#endif
+
+/* Check if Lpspi_Ip_Cfg.h and Spi_Ipw_PBcfg.c are of the same vendor */
+#if (LPSPI_IP_VENDOR_ID_CFG != SPI_IPW_VS_0_VENDOR_ID_PBCFG_C)
+    #error "Lpspi_Ip_Cfg.h and Spi_Ipw_PBcfg.c have different vendor ids"
+#endif
+/* Check if Lpspi_Ip_Cfg.h file and Spi_Ipw_PBcfg.c file are of the same Autosar version */
+#if ((LPSPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_AR_RELEASE_MINOR_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_AR_RELEASE_REVISION_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C))
+    #error "AutoSar Version Numbers of Lpspi_Ip_Cfg.h and Spi_Ipw_PBcfg.c are different"
+#endif
+
+#if ((LPSPI_IP_SW_MAJOR_VERSION_CFG != SPI_IPW_VS_0_SW_MAJOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_SW_MINOR_VERSION_CFG != SPI_IPW_VS_0_SW_MINOR_VERSION_PBCFG_C) || \
+     (LPSPI_IP_SW_PATCH_VERSION_CFG != SPI_IPW_VS_0_SW_PATCH_VERSION_PBCFG_C))
+    #error "Software Version Numbers of Lpspi_Ip_Cfg.h and Spi_Ipw_PBcfg.c are different"
+#endif
+
+/* Check if Spi.h and Spi_Ipw_PBcfg.c are of the same vendor */
+#if (SPI_VENDOR_ID != SPI_IPW_VS_0_VENDOR_ID_PBCFG_C)
+    #error "Spi.h and Spi_Ipw_PBcfg.c have different vendor ids"
+#endif
+/* Check if Spi.h file and Spi_Ipw_PBcfg.c file are of the same Autosar version */
+#if ((SPI_AR_RELEASE_MAJOR_VERSION != SPI_IPW_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+     (SPI_AR_RELEASE_MINOR_VERSION != SPI_IPW_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C) || \
+     (SPI_AR_RELEASE_REVISION_VERSION != SPI_IPW_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C))
+    #error "AutoSar Version Numbers of Spi.h and Spi_Ipw_PBcfg.c are different"
+#endif
+#if ((SPI_SW_MAJOR_VERSION != SPI_IPW_VS_0_SW_MAJOR_VERSION_PBCFG_C) || \
+     (SPI_SW_MINOR_VERSION != SPI_IPW_VS_0_SW_MINOR_VERSION_PBCFG_C) || \
+     (SPI_SW_PATCH_VERSION != SPI_IPW_VS_0_SW_PATCH_VERSION_PBCFG_C))
+    #error "Software Version Numbers of Spi.h and Spi_Ipw_PBcfg.c are different"
+#endif
+
+/* Check if Flexio_Spi_Ip_Cfg.h and Spi_Ipw_PBcfg.c are of the same vendor */
+#if (FLEXIO_SPI_IP_VENDOR_ID_CFG != SPI_IPW_VS_0_VENDOR_ID_PBCFG_C)
+    #error "Flexio_Spi_Ip_Cfg.h and Spi_Ipw_VS_0_PBcfg.c have different vendor ids"
+#endif
+/* Check if Flexio_Spi_Ip_Cfg.h file and Spi_Ipw_PBcfg.c file are of the same Autosar version */
+#if ((FLEXIO_SPI_IP_AR_RELEASE_MAJOR_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_MINOR_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C) || \
+     (FLEXIO_SPI_IP_AR_RELEASE_REVISION_VERSION_CFG != SPI_IPW_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C))
+    #error "AutoSar Version Numbers of Flexio_Spi_Ip_Cfg.h and Spi_Ipw_VS_0_PBcfg.c are different"
+#endif
+
+#if ((FLEXIO_SPI_IP_SW_MAJOR_VERSION_CFG != SPI_IPW_VS_0_SW_MAJOR_VERSION_PBCFG_C) || \
+     (FLEXIO_SPI_IP_SW_MINOR_VERSION_CFG != SPI_IPW_VS_0_SW_MINOR_VERSION_PBCFG_C) || \
+     (FLEXIO_SPI_IP_SW_PATCH_VERSION_CFG != SPI_IPW_VS_0_SW_PATCH_VERSION_PBCFG_C))
+    #error "Software Version Numbers of Flexio_Spi_Ip_Cfg.h and Spi_Ipw_VS_0_PBcfg.c are different"
+#endif
+/*==================================================================================================
+*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+#define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+
+#define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/* External device Configuration of SpiExternalDevice_0*/
+static const Spi_ExternalDeviceConfigType Spi_ExternalDeviceConfig_SpiExternalDevice_0_VS_0 =
+{
+        /* SpiExternalDevice_0*/
+        SPI_OVER_LPSPI, /* IpType */
+        2U,  /* Instance */
+        
+        {   /* ExternalDeviceConfig */
+            &Lpspi_Ip_DeviceAttributes_SpiExternalDevice_0_VS_0 /* LPSPI ExternalDeviceConfig */
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+            ,NULL_PTR /* Don't have FLEXIO_SPI ExternalDeviceConfig */
+#endif
+        },
+        
+        SPI_SPURIOUS_CORE_ID};
+/* Spi_apExternalDeviceConfigList_VS_0 External device Configuration of Spi*/
+const Spi_ExDevicesConfigType Spi_aExternalDeviceConfigList_VS_0[1U] =
+{
+    {
+    /* SpiExternalDevice_0 */
+    &Spi_ExternalDeviceConfig_SpiExternalDevice_0_VS_0
+    }
+};
+
+/* Hardware Unit configuration for SpiPhyUnit_0 */
+static const Spi_HWUnitConfigType Spi_HwUnitConfig_SpiPhyUnit_0_VS_0 =
+{
+        SPI_OVER_LPSPI, /* IpType */
+        (uint8)2U, /* Instance */
+        SPI_SPURIOUS_CORE_ID, /* SpiCoreUse */
+        {
+            &Lpspi_Ip_PhyUnitConfig_SpiPhyUnit_0_VS_0 /* LPSPI IpConfig */
+#if (SPI_IPW_SPI_FLEXIO_ENABLE == STD_ON)
+            ,NULL_PTR /* Don't have Ipconfig of FLEXIO_SPI */
+#endif
+            #if ((LPSPI_IP_DMA_USED == STD_ON) && (LPSPI_IP_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+            ,NULL_PTR
+            #endif
+        },
+        SPI_PHYUNIT_SYNC_U32 /* IsSync */
+};
+/* Array of Hardware Unit configurations */
+const Spi_PhyUnitsConfigType Spi_aHwUnitConfigList_VS_0[SPI_MAX_HWUNIT] =
+{
+    /* SpiPhyUnit_0 */
+    {
+    &Spi_HwUnitConfig_SpiPhyUnit_0_VS_0
+    }
+};
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Spi_VS_0_PBcfg.c

@@ -0,0 +1,340 @@
+/**   
+*   @file    Spi_PBcfg.c
+*   @implements Spi_PBcfg.c_Artifact
+*   @version 1.0.0
+*
+*   @brief   AUTOSAR Spi - Post-Build(PB) configuration file code template.
+*   @details Code template for Post-Build(PB) configuration file generation.
+*
+*   @addtogroup SPI_DRIVER_CONFIGURATION Spi Driver Configuration
+*   @{
+*/
+/*==================================================================================================
+*   Project              : RTD AUTOSAR 4.4
+*   Platform             : CORTEXM
+*   Peripheral           : LPSPI
+*   Dependencies         : 
+*
+*   Autosar Version      : 4.4.0
+*   Autosar Revision     : ASR_REL_4_4_REV_0000
+*   Autosar Conf.Variant :
+*   SW Version           : 1.0.0
+*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
+*
+*   (c) Copyright 2020-2021 NXP Semiconductors
+*   All Rights Reserved.
+*
+*   NXP Confidential. This software is owned or controlled by NXP and may only be
+*   used strictly in accordance with the applicable license terms. By expressly
+*   accepting such terms or by downloading, installing, activating and/or otherwise
+*   using the software, you are agreeing that you have read, and that you agree to
+*   comply with and are bound by, such license terms. If you do not agree to be
+*   bound by the applicable license terms, then you may not retain, install,
+*   activate or otherwise use the software.
+==================================================================================================*/
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+
+/*==================================================================================================
+*                                        INCLUDE FILES
+* 1) system and project includes
+* 2) needed interfaces from external units
+* 3) internal and external interfaces from this unit
+==================================================================================================*/
+
+#include "Spi.h"
+#include "Spi_Ipw_VS_0_PBcfg.h"
+
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+#include "Dem.h"
+#endif
+
+/*==================================================================================================
+*                                    SOURCE FILE VERSION INFORMATION
+==================================================================================================*/
+#define SPI_VS_0_MODULE_ID_PBCFG_C                        83
+#define SPI_VS_0_VENDOR_ID_PBCFG_C                        43
+#define SPI_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C         4
+#define SPI_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C         4
+#define SPI_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C      0
+#define SPI_VS_0_SW_MAJOR_VERSION_PBCFG_C                 1
+#define SPI_VS_0_SW_MINOR_VERSION_PBCFG_C                 0
+#define SPI_VS_0_SW_PATCH_VERSION_PBCFG_C                 0
+
+/*==================================================================================================
+*                                     FILE VERSION CHECKS
+==================================================================================================*/
+/* Check if current file and SPI header file are of the same vendor */
+#if (SPI_VS_0_VENDOR_ID_PBCFG_C != SPI_VENDOR_ID)
+    #error "Spi_PBCfg.c and Spi.h have different vendor ids"
+#endif
+/* Check if current file and SPI header file are of the same Autosar version */
+#if ((SPI_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C    != SPI_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C    != SPI_AR_RELEASE_MINOR_VERSION) || \
+     (SPI_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C != SPI_AR_RELEASE_REVISION_VERSION))
+    #error "AutoSar Version Numbers of Spi_PBCfg.c and Spi.h are different"
+#endif
+/* Check if current file and SPI header file are of the same Software version */
+#if ((SPI_VS_0_SW_MAJOR_VERSION_PBCFG_C != SPI_SW_MAJOR_VERSION) || \
+     (SPI_VS_0_SW_MINOR_VERSION_PBCFG_C != SPI_SW_MINOR_VERSION) || \
+     (SPI_VS_0_SW_PATCH_VERSION_PBCFG_C != SPI_SW_PATCH_VERSION))
+    #error "Software Version Numbers of Spi_PBCfg.c and Spi.h are different"
+#endif
+
+/* Check if current file and SPI header file are of the same vendor */
+#if (SPI_VS_0_VENDOR_ID_PBCFG_C != SPI_IPW_VENDOR_ID_VS_0_PBCFG_H)
+    #error "Spi_PBCfg.c and Spi_Ipw_PBCfg.h have different vendor ids"
+#endif
+/* Check if current file and SPI header file are of the same Autosar version */
+#if ((SPI_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C    != SPI_IPW_AR_RELEASE_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (SPI_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C    != SPI_IPW_AR_RELEASE_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (SPI_VS_0_AR_RELEASE_REVISION_VERSION_PBCFG_C != SPI_IPW_AR_RELEASE_REVISION_VERSION_VS_0_PBCFG_H ))
+    #error "AutoSar Version Numbers of Spi_PBCfg.c and Spi_Ipw_PBCfg.h are different"
+#endif
+/* Check if current file and SPI header file are of the same Software version */
+#if ((SPI_VS_0_SW_MAJOR_VERSION_PBCFG_C != SPI_IPW_SW_MAJOR_VERSION_VS_0_PBCFG_H) || \
+     (SPI_VS_0_SW_MINOR_VERSION_PBCFG_C != SPI_IPW_SW_MINOR_VERSION_VS_0_PBCFG_H) || \
+     (SPI_VS_0_SW_PATCH_VERSION_PBCFG_C != SPI_IPW_SW_PATCH_VERSION_VS_0_PBCFG_H))
+    #error "Software Version Numbers of Spi_PBCfg.c and Spi_Ipw_PBCfg.h are different"
+#endif
+
+#ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+/* Check if current file and Dem.h file are of the same Autosar version */
+#if ((SPI_VS_0_AR_RELEASE_MAJOR_VERSION_PBCFG_C    != DEM_AR_RELEASE_MAJOR_VERSION) || \
+     (SPI_VS_0_AR_RELEASE_MINOR_VERSION_PBCFG_C    != DEM_AR_RELEASE_MINOR_VERSION))
+    #error "AutoSar Version Numbers of Spi_PBCfg.c and Dem.h are different"
+#endif
+#endif
+#endif
+
+/*==================================================================================================
+*                         LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                       LOCAL MACROS
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                  LOCAL FUNCTION PROTOTYPES
+==================================================================================================*/
+
+
+/*==================================================================================================
+*                                      LOCAL FUNCTIONS
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      GLOBAL FUNCTIONS
+==================================================================================================*/
+#define SPI_START_SEC_CODE
+#include "Spi_MemMap.h"
+
+/* List Of Notification Functions */
+/* Job start Notifications */
+
+/* Job End Notifications */
+
+/* Sequence End Notifications */
+
+
+#define SPI_STOP_SEC_CODE
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                      GLOBAL VARIABLES
+==================================================================================================*/
+
+/*==================================================================================================
+*                                      LOCAL VARIABLES
+==================================================================================================*/
+#if ((SPI_DMA_USED == STD_ON) && \
+    ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)))
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_START_SEC_VAR_CLEARED_UNSPECIFIED
+#endif /* ((SPI_DMA_USED == STD_ON) && ((SPI_LEVEL_DELIVERED == LEVEL1) ||
+        (SPI_LEVEL_DELIVERED == LEVEL2))) */
+#include "Spi_MemMap.h"
+
+/* Buffers Descriptors for EB Channels and Allocate Buffers for IB Channels */
+static Spi_BufferDescriptorType Spi_Buffer_VS_0_SpiChannel_0;
+/* Allocate Buffers for IB Channels (if any) */
+
+
+#if ((SPI_DMA_USED == STD_ON) && \
+    ((SPI_LEVEL_DELIVERED == LEVEL1) || (SPI_LEVEL_DELIVERED == LEVEL2)))
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
+#else
+    #define SPI_STOP_SEC_VAR_CLEARED_UNSPECIFIED
+#endif /* ((SPI_DMA_USED == STD_ON) && ((SPI_LEVEL_DELIVERED == LEVEL1) ||
+        (SPI_LEVEL_DELIVERED == LEVEL2))) */
+#include "Spi_MemMap.h"
+
+#define SPI_START_SEC_VAR_INIT_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/* Buffers Descriptors for IB Channels */
+    /*  Buffers Descriptors for IB Channels (if any) */
+
+
+
+#define SPI_STOP_SEC_VAR_INIT_UNSPECIFIED
+#include "Spi_MemMap.h"
+/*==================================================================================================
+*                                      LOCAL CONSTANTS
+==================================================================================================*/
+#define SPI_START_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+/* Channel Configuration */
+/* Channel Configuration of SpiChannel_0*/
+static const Spi_ChannelConfigType Spi_ChannelConfig_SpiChannel_0_VS_0 =
+{
+        /* SpiChannel_0*/
+        EB, /* BufferType IB or EB */
+        8U, /* Frame size */
+                (boolean)FALSE, /* Bite order */
+        
+#ifdef SPI_HALF_DUPLEX_MODE_SUPPORT
+  #if (STD_ON == SPI_HALF_DUPLEX_MODE_SUPPORT)
+        
+        SPI_FULL_DUPLEX,
+        
+  #endif
+#endif
+        (uint32)1U, /* In the case SpiDefaultData is disabled. Set this value is 1U */
+        1000U, /* Length (configured in SpiEbMaxLength) */
+        &Spi_Buffer_VS_0_SpiChannel_0, /* pcBufferDescriptor */
+        SPI_SPURIOUS_CORE_ID,
+        &Spi_axSpiChannelState[0U] /* pChannelState pointer */
+};
+/* Spi_apChannelConfigList_VS_0 Channel Configuration of Spi*/
+static const Spi_ChannelsCfgType Spi_aChannelConfigList_VS_0[1] =
+{
+    {
+    /* SpiChannel_0 */
+    /* SpiChannel_0 */
+    &Spi_ChannelConfig_SpiChannel_0_VS_0
+    }
+
+};
+
+/* Channel Assignment of Jobs */
+
+/* Channel to Job Assignment */
+
+static const Spi_ChannelType Spi_SpiJob_0_ChannelAssignment_VS_0[1] = {SpiConf_SpiChannel_SpiChannel_0};
+
+/* Configuration of Jobs */
+
+/* Job Configuration of SpiJob_0*/
+static const Spi_JobConfigType Spi_JobConfig_SpiJob_0_VS_0 =
+{
+        /* SpiJob_0 */
+        (Spi_ChannelType)1U, /* NumChannels field */
+        Spi_SpiJob_0_ChannelAssignment_VS_0, /* List of Channels */
+        
+            NULL_PTR,
+        
+        
+            NULL_PTR,
+        
+        (sint8)0, /* Priority */
+        SPI_SPURIOUS_CORE_ID,        &Spi_axSpiJobState[0], /* JobState instance */
+        CSIB0, /* HWUnit index */
+        /* External Device Settings */
+        SPI_SpiExternalDevice_0, /* External Device */
+                &Spi_aExternalDeviceConfigList_VS_0[SPI_SpiExternalDevice_0] /* pcExternalDeviceConfig - pointer to the external device configuration */        };
+/* Spi_apJobConfigList_VS_0 Job Configuration of Spi*/
+static const Spi_JobsCfgType Spi_aJobConfigList_VS_0[1] =
+{
+    {
+    /* SpiJob_0 */
+    /* SpiJob_0 */
+    &Spi_JobConfig_SpiJob_0_VS_0
+    }
+
+};
+
+
+/* Job Assignment of Sequences  */
+/* Job to Sequence Assignment */
+
+static const Spi_JobType Spi_SpiSequence_0_JobAssignment_VS_0[1] = {SpiConf_SpiJob_SpiJob_0};
+/* Configuration of Sequences */
+
+/* Sequence Configuration of SpiSequence_0_VS_0 */
+static const Spi_SequenceConfigType Spi_SequenceConfig_SpiSequence_0_VS_0 =
+{
+        /* SpiSequence_0 */
+        (Spi_JobType)1U,
+        SPI_SPURIOUS_CORE_ID,
+        Spi_SpiSequence_0_JobAssignment_VS_0, /* List of Jobs */
+        NULL_PTR, /* End Notification */
+        (uint8)FALSE /* Interruptible */
+                #if ((SPI_DMA_USED == STD_ON) && (SPI_ENABLE_DMAFASTTRANSFER_SUPPORT == STD_ON))
+        , (boolean)FALSE /* Enable Dma fast transfer */
+        #endif
+        
+};
+/* Spi_apSequenceConfigList_VS_0 Sequence Configuration of Spi*/
+static const Spi_SeqsConfigType Spi_aSequenceConfigList_VS_0[1] =
+{
+    {
+    /* SpiSequence_0 */
+    /* SpiSequence_0 */
+    &Spi_SequenceConfig_SpiSequence_0_VS_0
+    }
+};
+
+/*==================================================================================================
+*                                      GLOBAL CONSTANTS
+==================================================================================================*/
+/* Spi Configuration */
+
+
+/** Compiler_Warning: In some cases, the partition configuration may not be used by the application. */
+static const Spi_ConfigType Spi_Config=
+{
+    1U, /* u16MaxExternalDevice - number of external devices */
+    0U, /* Spi_Max_Channel - number of channels */
+    0U, /* Spi_Max_Job - number of jobs */
+    0U, /* Spi_Max_Sequence - number of sequences */
+    SPI_SPURIOUS_CORE_ID, /* u32SpiCoreUse */
+    Spi_aChannelConfigList_VS_0, /* pcChannelConfig */
+    Spi_aJobConfigList_VS_0, /* pcJobConfig */
+    Spi_aSequenceConfigList_VS_0, /* pcSequenceConfig */
+    Spi_aExternalDeviceConfigList_VS_0, /* pcExternalDeviceConfig */
+    Spi_aHwUnitConfigList_VS_0 /* pcHWUnitConfig */
+#if (SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF)
+            ,{ (uint32)STD_OFF, (uint32)0U}/* SPI_E_HARDWARE_ERROR parameters*/         
+#endif /* SPI_DISABLE_DEM_REPORT_ERROR_STATUS == STD_OFF */  
+};
+
+
+
+
+const Spi_ConfigType * const Spi_PBCfgVariantPredefined[SPI_MAX_PARTITIONS]=
+{
+    &Spi_Config
+};
+
+
+
+
+
+#define SPI_STOP_SEC_CONFIG_DATA_UNSPECIFIED
+#include "Spi_MemMap.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+

generate/src/Uart_Ipw_VS_0_PBcfg.c

@@ -256,72 +256,6 @@ const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_2_VS_0 =
     &Uart_Ipw_IpChnConfigPB_2_VS_0
 };
 
-
-
-/**
-* @brief   The Ip configuration structure pointer
-*/
-const Uart_Ipw_IpConfigType Uart_Ipw_IpChnConfigPB_3_VS_0 =
-{
-
-    /* Not use Lpuart Ip configuration structure  */
-    NULL_PTR,
-
-
-    /* Flexio Uart Ip configuration structure  */
-    &Flexio_Uart_Ip_xHwConfigPB_3_VS_0
-
-};
-
-/**
-* @brief    Hardware configuration for Uart Hardware - Configuration.
-*/
-
-const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_3_VS_0 =
-{
-    /* Uart Hardware Channel.*/
-    0U,
-    /* Type of Hardware interface configured.*/
-    FLEXIO_IP,
-    /* User Callback */
-    NULL_PTR,
-    /* Pointer to the Ip configuration structure.*/
-    &Uart_Ipw_IpChnConfigPB_3_VS_0
-};
-
-
-
-/**
-* @brief   The Ip configuration structure pointer
-*/
-const Uart_Ipw_IpConfigType Uart_Ipw_IpChnConfigPB_4_VS_0 =
-{
-
-    /* Not use Lpuart Ip configuration structure  */
-    NULL_PTR,
-
-
-    /* Flexio Uart Ip configuration structure  */
-    &Flexio_Uart_Ip_xHwConfigPB_4_VS_0
-
-};
-
-/**
-* @brief    Hardware configuration for Uart Hardware - Configuration.
-*/
-
-const Uart_Ipw_HwConfigType Uart_Ipw_xHwConfigPB_4_VS_0 =
-{
-    /* Uart Hardware Channel.*/
-    1U,
-    /* Type of Hardware interface configured.*/
-    FLEXIO_IP,
-    /* User Callback */
-    NULL_PTR,
-    /* Pointer to the Ip configuration structure.*/
-    &Uart_Ipw_IpChnConfigPB_4_VS_0
-};
-
 #define UART_STOP_SEC_CONFIG_DATA_UNSPECIFIED
 #include "Uart_MemMap.h"
 /*==================================================================================================

generate/src/Uart_VS_0_PBcfg.c

@@ -176,7 +176,7 @@ const Uart_ChannelConfigType Uart_ChannelConfig_0_VS_0 =
 #if (UART_MULTICORE_SUPPORT == STD_ON)
     UART_CORE_ID, /*Uart Channel Core Id*/
 #endif
-    4000000U, /* Clock frequency */
+    16000000U, /* Clock frequency */
     &Uart_Ipw_xHwConfigPB_0_VS_0  /* Uart Hardware config */
 };
 
@@ -192,7 +192,7 @@ const Uart_ChannelConfigType Uart_ChannelConfig_1_VS_0 =
 #if (UART_MULTICORE_SUPPORT == STD_ON)
     UART_CORE_ID, /*Uart Channel Core Id*/
 #endif
-    4000000U, /* Clock frequency */
+    16000000U, /* Clock frequency */
     &Uart_Ipw_xHwConfigPB_1_VS_0  /* Uart Hardware config */
 };
 
@@ -208,42 +208,10 @@ const Uart_ChannelConfigType Uart_ChannelConfig_2_VS_0 =
 #if (UART_MULTICORE_SUPPORT == STD_ON)
     UART_CORE_ID, /*Uart Channel Core Id*/
 #endif
-    4000000U, /* Clock frequency */
+    16000000U, /* Clock frequency */
     &Uart_Ipw_xHwConfigPB_2_VS_0  /* Uart Hardware config */
 };
 
-/**
-* @brief          Configuration for Uart Channel 3
-*
-*
-*/
-const Uart_ChannelConfigType Uart_ChannelConfig_3_VS_0 =
-{
-    3, /*Uart Channel Id*/
-
-#if (UART_MULTICORE_SUPPORT == STD_ON)
-    UART_CORE_ID, /*Uart Channel Core Id*/
-#endif
-    4000000U, /* Clock frequency */
-    &Uart_Ipw_xHwConfigPB_3_VS_0  /* Uart Hardware config */
-};
-
-/**
-* @brief          Configuration for Uart Channel 4
-*
-*
-*/
-const Uart_ChannelConfigType Uart_ChannelConfig_4_VS_0 =
-{
-    4, /*Uart Channel Id*/
-
-#if (UART_MULTICORE_SUPPORT == STD_ON)
-    UART_CORE_ID, /*Uart Channel Core Id*/
-#endif
-    4000000U, /* Clock frequency */
-    &Uart_Ipw_xHwConfigPB_4_VS_0  /* Uart Hardware config */
-};
-
 
 
 
@@ -273,14 +241,6 @@ static const Uart_ConfigType Uart_xConfig =
             
         &Uart_ChannelConfig_2_VS_0
 
-    ,
-            
-        &Uart_ChannelConfig_3_VS_0
-
-    ,
-            
-        &Uart_ChannelConfig_4_VS_0
-
 
 
 

src/SL_Sc7a20_Driver.c

@@ -0,0 +1,472 @@
+#include "SL_Sc7a20_Driver.h"
+#include "string.h"
+
+Std_ReturnType Gsensor_SPI_Read(uint8 Addr,uint8 *DataBufferPtr,uint16 Length)
+{
+	Std_ReturnType spiSendStatus;
+	Spi_DataBufferType txBuffer[Length+1];
+	Spi_DataBufferType rxBuffer[Length+1];
+
+	memset(txBuffer,0,sizeof(txBuffer));
+	memset(rxBuffer,0,sizeof(rxBuffer));
+	if(Length == 1)
+	{
+		txBuffer[0] = Addr | 0x80;
+	}
+	else if(Length > 1)
+	{
+		txBuffer[0] = Addr | 0x80 | 0x40;
+	}
+	else
+	{
+		return E_NOT_OK;
+	}
+
+	Spi_SetupEB(0,txBuffer,rxBuffer,Length+1);
+	spiSendStatus = Spi_SyncTransmit(0);
+
+	if(spiSendStatus == E_OK)
+	{
+		memcpy(DataBufferPtr,&rxBuffer[1],Length);
+		return E_OK;
+	}
+	else
+	{
+		return E_NOT_OK;
+	}
+}
+
+Std_ReturnType Gsensor_SPI_Write(uint8 Addr,uint8 *DataBufferPtr,uint16 Length)
+{
+	Std_ReturnType spiSendStatus;
+	Spi_DataBufferType txBuffer[Length+1];
+	memset(txBuffer,0,sizeof(txBuffer));
+	if(Length == 1)
+	{
+		txBuffer[0] = Addr;
+	}
+	else if(Length > 1)
+	{
+		txBuffer[0] = Addr | 0x40;
+	}
+	else
+	{
+		return E_NOT_OK;
+	}
+	memcpy(&txBuffer[1],DataBufferPtr,Length);
+
+	Spi_SetupEB(0,txBuffer,NULL,Length+1);
+	spiSendStatus = Spi_SyncTransmit(0);
+
+	if(spiSendStatus == E_OK)
+	{
+		return E_OK;
+	}
+	else
+	{
+		return E_NOT_OK;
+	}
+}
+
+
+/***************在线测试**********************/
+Std_ReturnType  SL_SC7A20_Online_Test(void)
+{
+	uint8 SL_Read_Reg[1]= {0xff};
+    Gsensor_SPI_Read(SC7A20_CHIP_ID_ADDRESS,SL_Read_Reg,1);
+    if(SL_Read_Reg[0]==SC7A20_CHIP_ID_VALUE)
+    	return  E_OK;
+    else
+    	return E_NOT_OK;
+}
+
+/***************BOOT 重载内部寄存器值*********************/
+Std_ReturnType  SL_SC7A20_BOOT(void)
+{
+	uint8 SL_Read_Reg[1]={0xff};
+	uint8 SL_Write_Reg[1];
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG5,SL_Read_Reg,1);
+    SL_Write_Reg[0] = SL_SC7A20_BOOT_ENABLE | SL_Read_Reg[0];
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG5, SL_Write_Reg,1);
+    return  E_OK;
+}
+
+Std_ReturnType  SL_SC7A20_INT_Config(void)
+{
+	uint8 SL_Read_Reg[1]={0xff};
+	uint8 SL_Write_Reg[1];
+
+    /*******************AOI1  IN  INT1********************/
+	SL_Write_Reg[0]=0x08;//AOI1 LATCH
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG5, SL_Write_Reg,1);
+
+    SL_Write_Reg[0]=SL_SC7A20_INT_ACTIVE_HIGH_LEVEL;
+    //interrupt happen,int pin output lower level
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG6, SL_Write_Reg,1);
+
+    //AOI1 CONFIG
+    SL_Write_Reg[0]=0x00;            //0x7F
+#if  SL_6D4D2D1D_SEL== 1
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x02;//X
+#elif SL_6D4D2D1D_SEL== 2
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x02;//X
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x04;//Yֵ
+#elif SL_6D4D2D1D_SEL== 4
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x03;//X
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x0C;//Y
+#elif  SL_6D4D2D1D_SEL== 6
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x03;//Xֵ
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x0C;//Yֵ
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x30;//Z
+#endif
+
+    Gsensor_SPI_Write(SL_SC7A20_INT1_CFG, SL_Write_Reg,1);
+
+    //HPF SET
+  //  Gsensor_SPI_Read(SL_SC7A20_CTRL_REG2,1, &SL_Read_Reg);
+    SL_Write_Reg[0]=0xCF;//SL_Read_Reg|0x81;//Normal HP , HPF TO AOI1
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG2, SL_Write_Reg,1);
+
+#if SL_6D4D2D1D_SEL== 6
+    SL_Write_Reg[0] = SL_SC7A20_INT_THS_20PERCENT;
+	Gsensor_SPI_Write(SL_SC7A20_INT1_THS, SL_Write_Reg,1);
+
+	SL_Write_Reg[0] = SL_SC7A20_INT_DURATION_30CLK;
+	Gsensor_SPI_Write(SL_SC7A20_INT1_DURATION, SL_Write_Reg, 1);
+#else
+    SL_Write_Reg[0] = SL_SC7A20_INT_THS_10PERCENT;
+	Gsensor_SPI_Write(SL_SC7A20_INT1_THS, SL_Write_Reg,1);
+
+	SL_Write_Reg[0] = SL_SC7A20_INT_DURATION_2CLK;
+	Gsensor_SPI_Write(SL_SC7A20_INT1_DURATION, SL_Write_Reg, 1);
+#endif
+
+
+    //AOI1 TO INT1
+   // Gsensor_SPI_Read(SL_SC7A20_CTRL_REG3,1, &SL_Read_Reg);
+    SL_Write_Reg[0]=0x40;//SL_Read_Reg|0x40; //AOI1 TO INT1
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG3, SL_Write_Reg,1);
+    /*******************AOI1  IN  INT1********************/
+
+
+    /*******************AOI2  IN  INT2********************/
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG5,SL_Read_Reg, 1);
+    SL_Write_Reg[0]=SL_Read_Reg[0]|0x02;//AOI2 LATCH
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG5, SL_Write_Reg,1);
+
+
+    //AOI2 CONFIG
+    SL_Write_Reg[0]=0x00;            //0xFF
+
+#if  SL_6D4D2D1D_SEL== 1
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x02;//X
+#elif SL_6D4D2D1D_SEL== 2
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x02;//X
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x04;//Y
+#elif SL_6D4D2D1D_SEL== 4
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x03;//Xֵ
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x0C;//Y
+#elif  SL_6D4D2D1D_SEL== 6
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x03;//Xֵ
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x0C;//Y
+    SL_Write_Reg[0]=SL_Write_Reg[0]|0x30;//Z
+#endif
+    Gsensor_SPI_Write(SL_SC7A20_INT2_CFG, SL_Write_Reg,1);
+
+    //HPF SET
+#if SL_6D4D2D1D_SEL== 6
+    SL_Read_Reg[0]= 0x00;
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG2,SL_Read_Reg,1);
+#endif
+   //SL_Read_Reg=SL_Read_Reg&0xFD;//NO HPF TO AOI2
+   // Gsensor_SPI_Write(SL_SC7A20_CTRL_REG2, SL_Read_Reg);
+
+
+
+#if SL_6D4D2D1D_SEL== 6
+    SL_Write_Reg[0] = SL_SC7A20_INT_THS_5PERCENT;
+#else
+    SL_Write_Reg[0] = SL_SC7A20_INT_THS_10PERCENT;
+#endif
+    Gsensor_SPI_Write(SL_SC7A20_INT2_THS,SL_Write_Reg,1 );
+
+    SL_Write_Reg[0] = SL_SC7A20_INT_DURATION_2CLK;
+    Gsensor_SPI_Write(SL_SC7A20_INT2_DURATION, SL_Write_Reg,1);
+
+    //AOI2 TO INT2
+    memset(SL_Read_Reg,0xFF,1);
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG6,SL_Read_Reg,1);
+    SL_Write_Reg[0]=SL_Read_Reg[0]|0x20; //AOI2 TO INT2
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG6, SL_Write_Reg,1);
+    /*******************AOI2  IN  INT2********************/
+
+    return  E_OK;
+}
+
+
+
+//retrun_value&0x20=0x20  ZH
+//retrun_value&0x20=0x10  ZL
+//retrun_value&0x20=0x08  YH
+//retrun_value&0x20=0x04  YL
+//retrun_value&0x20=0x02  XH
+//retrun_value&0x20=0x01  XL
+Std_ReturnType  SL_SC7A20_INT_RESET(void)
+{
+
+	uint8 SL_Write_Reg[1] = {0x00};
+    uint8 SL_Read_Reg1[1] = {0xFF};
+    uint8 SL_Read_Reg2[1] = {0xFF};
+
+
+
+    //SL_Read_Reg1 display the int1 type
+    Gsensor_SPI_Read(SL_SC7A20_INT1_SRC,SL_Read_Reg1,1);
+    //SL_Read_Reg2 display the int2 type
+    Gsensor_SPI_Read(SL_SC7A20_INT2_SRC,SL_Read_Reg2,1);
+
+    //close INT1
+    SL_Write_Reg[0] = 0x00;
+    Gsensor_SPI_Write(SL_SC7A20_INT1_CFG, SL_Write_Reg, 1);
+    //close INT2
+    Gsensor_SPI_Write(SL_SC7A20_INT2_CFG, SL_Write_Reg ,1);
+
+    if((SL_Read_Reg2[0]&0x02)==0x02)
+    {
+        //X+
+    }
+    if((SL_Read_Reg2[0]&0x01)==0x01)
+    {
+        //X-
+    }
+    if((SL_Read_Reg2[0]&0x08)==0x08)
+    {
+        //Y+
+    }
+    if((SL_Read_Reg2[0]&0x04)==0x04)
+    {
+        //Y-
+    }
+    if((SL_Read_Reg2[0]&0x20)==0x20)
+    {
+        //Z+
+    }
+    if((SL_Read_Reg2[0]&0x10)==0x10)
+    {
+        //Z-
+    }
+
+    if(SL_Read_Reg1[0]!=0||SL_Read_Reg2[0]!=0)
+    {
+        return E_OK;
+    }
+    else
+    {
+        return E_NOT_OK;
+    }
+
+}
+
+
+void  SL_SC7A20_AOI1_event(void)
+{
+
+    uint8 SL_SRC_Reg1[1] = {0xFF};
+    uint8 SL_THS_Reg1[1] = {0xFF};
+    uint8 SL_DURATION_Reg1 = {0xFF};
+
+
+    //SL_Read_Reg1 display the int1 type
+    Gsensor_SPI_Read(SL_SC7A20_INT1_SRC,SL_SRC_Reg1,1);
+    Gsensor_SPI_Read(SL_SC7A20_INT1_THS,SL_THS_Reg1,1);
+    Gsensor_SPI_Read(SL_SC7A20_INT1_DURATION,SL_DURATION_Reg1,1);
+
+//    printf("SL_SC7A20_INT1_SRC=%#x\r\n",SL_SRC_Reg1);
+ //   if((SL_SRC_Reg1&0x40)==0x40){
+
+	    if((SL_SRC_Reg1[0]&0x01)==0x01)
+	    {
+	        //X-
+//		    printf("X1-\r\n");
+	    }
+	    if((SL_SRC_Reg1[0]&0x02)==0x02)
+	    {
+	        //X+
+//		    printf("X1+\r\n");
+	    }
+	    if((SL_SRC_Reg1[0]&0x04)==0x04)
+	    {
+	        //Y-
+//		    printf("Y1-\r\n");
+	    }
+	    if((SL_SRC_Reg1[0]&0x08)==0x08)
+	    {
+	        //Y+
+//		    printf("Y1+\r\n");
+	    }
+	    if((SL_SRC_Reg1[0]&0x10)==0x10)
+	    {
+	        //Z-
+//		    printf("Z1-\r\n");
+	    }
+	    if((SL_SRC_Reg1[0]&0x20)==0x20)
+	    {
+	        //Z+
+//		    printf("Z1+\r\n");
+	    }
+//    }
+
+}
+
+
+void  SL_SC7A20_AOI2_event(void)
+{
+
+    uint8 SL_SRC_Reg2[1] = {0xFF};
+    uint8 SL_THS_Reg2 = {0xFF};
+    uint8 SL_DURATION_Reg2 = {0xFF};
+
+
+    //SL_Read_Reg1 display the int1 type
+    Gsensor_SPI_Read(SL_SC7A20_INT2_SRC,SL_SRC_Reg2,1);
+    Gsensor_SPI_Read(SL_SC7A20_INT2_THS,SL_THS_Reg2,1);
+    Gsensor_SPI_Read(SL_SC7A20_INT2_DURATION,SL_DURATION_Reg2,1);
+
+//    printf("SL_SC7A20_INT2_SRC=%#x\r\n",SL_SRC_Reg2);
+  //  if((SL_SRC_Reg2&0x40)==0x40){
+
+	    if((SL_SRC_Reg2[0]&0x01)==0x01)
+	    {
+	        //X-
+//		    printf("X2-\r\n");
+	    }
+	    if((SL_SRC_Reg2[0]&0x02)==0x02)
+	    {
+	        //X+
+//		    printf("X2+\r\n");
+	    }
+	    if((SL_SRC_Reg2[0]&0x04)==0x04)
+	    {
+	        //Y-
+//		    printf("Y2-\r\n");
+	    }
+	    if((SL_SRC_Reg2[0]&0x08)==0x08)
+	    {
+	        //Y+
+//		    printf("Y2+\r\n");
+	    }
+	    if((SL_SRC_Reg2[0]&0x10)==0x10)
+	    {
+	        //Z-
+//		    printf("Z2-\r\n");
+	    }
+	    if((SL_SRC_Reg2[0]&0x20)==0x20)
+	    {
+	        //Z+
+//		    printf("Z2+\r\n");
+	    }
+ //   }
+
+}
+
+
+void  SL_SC7A20_Reg_read_all(void)
+{
+    uint8 SL_Read_Reg[32];
+    memset(SL_Read_Reg,0xFF,32);
+//    printf("SL_SC7A20_Reg_readall ++++++++\r\n");
+    /*******************AOI1  IN  INT1********************/
+	uint8 adr = 0x20;
+	for(adr=0x20;adr<=0x3F;adr++)
+	{
+		Gsensor_SPI_Read(adr,&SL_Read_Reg[adr-0x20],1);
+//		printf("%#x = %#x\r\n",adr,SL_Read_Reg[adr-0x20]);
+	}
+
+//    printf("SL_SC7A20_Reg_readall --------\r\n");
+}
+
+
+/***************传感器量程设置**********************/
+Std_ReturnType  SL_SC7A20_FS_Config(uint8 Sc7a20_FS_Reg)
+{
+	uint8 SL_Read_Reg[1]={0xff};
+	uint8 SL_Write_Reg[1];
+
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG4,SL_Read_Reg,1);
+    SL_Write_Reg[0]=0x80|Sc7a20_FS_Reg|SL_SC7A20_HR_ENABLE;
+
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG4, SL_Write_Reg,1);
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG4,SL_Read_Reg,1);
+    if(SL_Read_Reg[0]==SL_Write_Reg[0])
+    {
+    	return  E_OK;
+    }
+    else
+    {
+    	return E_NOT_OK;
+    }
+}
+
+/***************数据更新速率**加速度计使能**********/
+Std_ReturnType  SL_SC7A20_Power_Config(uint8 Power_Config_Reg)
+{
+	uint8 SL_Read_Reg[1]={0xff};
+	uint8 SL_Write_Reg[1];
+
+#if  SL_SC7A20_MTP_ENABLE == 0X01
+    SL_Read_Reg  = 0x00;
+    Gsensor_SPI_Write(SL_SC7A20_SPI_IIC_MODE,SL_SC7A20_MTP_CFG, SL_SC7A20_MTP_VALUE);
+    Gsensor_SPI_Read(SL_SC7A20_SPI_IIC_MODE,SL_SC7A20_SDOI2C_PU_CFG,1, &SL_Read_Reg);
+    SL_Read_Reg=SL_Read_Reg|SL_SC7A20_SDO_PU_MSK|SL_SC7A20_I2C_PU_MSK;
+    Gsensor_SPI_Write(SL_SC7A20_SPI_IIC_MODE,SL_SC7A20_SDOI2C_PU_CFG, SL_Read_Reg);
+#endif
+    SL_Write_Reg[0] = Power_Config_Reg;
+    Gsensor_SPI_Write(SL_SC7A20_CTRL_REG1, SL_Write_Reg,1);
+    Gsensor_SPI_Read(SL_SC7A20_CTRL_REG1,SL_Read_Reg,1);
+
+    if(SL_Read_Reg[0]==Power_Config_Reg)
+    	return  E_OK;
+    else
+    	return E_NOT_OK;
+}
+
+
+/***************加速度计数据读取*16bits*********/
+Std_ReturnType  SL_SC7A20_Read_XYZ_Data(sint16 *SL_SC7A20_Data_XYZ_Buf)
+{
+    uint8 SL_Read_Buf[7];
+    
+    Gsensor_SPI_Read(SL_SC7A20_STATUS_REG,&SL_Read_Buf[0],1);
+    
+    if((SL_Read_Buf[0]&0x0f)==0x0f)
+    {
+
+        Gsensor_SPI_Read(SL_SC7A20_DATA_OUT,&SL_Read_Buf[1],6);
+        SL_SC7A20_Data_XYZ_Buf[0]=(sint16)((SL_Read_Buf[2]<<8) + SL_Read_Buf[1]);
+        SL_SC7A20_Data_XYZ_Buf[1]=(sint16)((SL_Read_Buf[4]<<8) + SL_Read_Buf[3]);
+        SL_SC7A20_Data_XYZ_Buf[2]=(sint16)((SL_Read_Buf[6]<<8) + SL_Read_Buf[5]);
+        return  E_OK;
+
+    }
+    else
+    {
+    	return E_NOT_OK;
+    }
+}
+
+Std_ReturnType GsensorInit(void)
+{
+	Std_ReturnType Status = E_NOT_OK;
+	Status = SL_SC7A20_Online_Test();
+	if(Status==E_OK)
+	{
+
+		SL_SC7A20_BOOT();
+		SL_SC7A20_FS_Config(SL_SC7A20_FS_4G);
+		SL_SC7A20_INT_Config();
+		//SL_SC7A20_INT_RESET();
+		SL_SC7A20_Power_Config(SL_SC7A20_LOWER_POWER_ODR_400HZ);
+	}
+	return Status;
+}

src/SL_Sc7a20_Driver.h

@@ -0,0 +1,212 @@
+#ifndef __SL_SC7A20_DRIVER_H__
+#define __SL_SC7A20_DRIVER_H__
+
+#include "PlatformTypes.h"
+#include "StandardTypes.h"
+#include "Spi.h"
+
+/***使用驱动前请根据实际接线情况配置******/
+/**SC7A20的SDO 脚接地：  0****************/
+/**SC7A20的SDO 脚接电源：1****************/
+#define SC7A20_SDO_VDD_GND            1
+/*****************************************/
+
+/***使用驱动前请根据实际IIC情况进行配置***/
+/**SC7A20的IIC 接口地址类型 7bits：  0****/
+/**SC7A20的IIC 接口地址类型 8bits：  1****/
+#define SC7A20_IIC_7BITS_8BITS        0
+/*****************************************/
+
+#define  SL_SC7A20_16BIT_8BIT         1
+/**SC7A20的数据位数选择  16bits：    1****/
+/**SC7A20的数据位数选择   8bits：    0****/
+/*****************************************/
+
+#define  SL_SC7A20_SPI_IIC_MODE       0
+/**SC7A20 SPI IIC 选择    SPI：      0****/
+/**SC7A20 SPI IIC 选择    IIC：      1****/
+/*****************************************/
+
+#define SL_6D4D2D1D_SEL   			 6
+
+#if SL_SC7A20_SPI_IIC_MODE==1
+
+#if SC7A20_SDO_VDD_GND==0
+#define SC7A20_IIC_7BITS_ADDR        0x18
+#define SC7A20_IIC_8BITS_ADDR        0x30
+#else
+#define SC7A20_IIC_7BITS_ADDR        0x19
+#define SC7A20_IIC_8BITS_ADDR        0x32
+#endif
+
+
+#if SC7A20_IIC_7BITS_8BITS==0
+#define SC7A20_IIC_ADDRESS  SC7A20_IIC_7BITS_ADDR
+#else
+#define SC7A20_IIC_ADDRESS  SC7A20_IIC_8BITS_ADDR
+#endif
+
+#endif
+
+
+#define SC7A20_CHIP_ID_ADDRESS    (uint8)0x0F
+#define SC7A20_CHIP_ID_VALUE      (uint8)0x11
+
+#define  SL_SC7A20_CTRL_REG1      (uint8)0x20
+#define  SL_SC7A20_CTRL_REG2      (uint8)0x21
+#define  SL_SC7A20_CTRL_REG3      (uint8)0x22
+#define  SL_SC7A20_CTRL_REG4      (uint8)0x23
+#define  SL_SC7A20_CTRL_REG5      (uint8)0x24
+#define  SL_SC7A20_CTRL_REG6      (uint8)0x25
+
+#define  SL_SC7A20_STATUS_REG     (uint8)0x27
+
+#define  SL_SC7A20_OUT_X_L        (uint8)0x28
+#define  SL_SC7A20_OUT_X_H        (uint8)0x29
+#define  SL_SC7A20_OUT_Y_L        (uint8)0x2A
+#define  SL_SC7A20_OUT_Y_H        (uint8)0x2B
+#define  SL_SC7A20_OUT_Z_L        (uint8)0x2C
+#define  SL_SC7A20_OUT_Z_H        (uint8)0x2D
+
+#define  SL_SC7A20_FIFO_CTRL_REG  (uint8)0x2E
+#define  SL_SC7A20_FIFO_SRC_REG   (uint8)0x2F
+
+#define  SL_SC7A20_INT1_CFG    	  (uint8)0x30
+#define  SL_SC7A20_INT1_SRC       (uint8)0x31
+#define  SL_SC7A20_INT1_THS    	  (uint8)0x32
+#define  SL_SC7A20_INT1_DURATION  (uint8)0x33
+
+#define  SL_SC7A20_INT2_CFG    	  (uint8)0x34
+#define  SL_SC7A20_INT2_SRC       (uint8)0x35
+#define  SL_SC7A20_INT2_THS    	  (uint8)0x36
+#define  SL_SC7A20_INT2_DURATION  (uint8)0x37
+#define  SL_SC7A20_CLICK_CFG   	  (uint8)0x38
+#define  SL_SC7A20_CLICK_SRC   	  (uint8)0x39
+#define  SL_SC7A20_CLICK_THS   	  (uint8)0x3A
+#define  SL_SC7A20_TIME_LIMIT     (uint8)0x3B
+#define  SL_SC7A20_TIME_LATENCY   (uint8)0x3C
+#define  SL_SC7A20_TIME_WINDOW    (uint8)0x3D
+#define  SL_SC7A20_ACT_THS        (uint8)0x3E
+#define  SL_SC7A20_ACT_DURATION   (uint8)0x3F
+	
+/*连续读取数据时的数据寄存器地址*/
+#define  SL_SC7A20_DATA_OUT       (uint8)(SL_SC7A20_OUT_X_L|0x80)
+
+/**********特殊功能寄存器**********/
+/*非原厂技术人员请勿修改*/
+#define  SL_SC7A20_MTP_ENABLE            0x00
+#define  SL_SC7A20_MTP_CFG    	  (uint8)0x1E
+#define  SL_SC7A20_MTP_VALUE   	  (uint8)0x05
+#define  SL_SC7A20_SDOI2C_PU_CFG  (uint8)0x57
+#define  SL_SC7A20_SDO_PU_MSK     (uint8)0x08
+#define  SL_SC7A20_I2C_PU_MSK     (uint8)0x04
+#define  SL_SC7A20_HR_ENABLE      (uint8)0X08
+#define  SL_SC7A20_BOOT_ENABLE    (uint8)0X80
+/*非原厂技术人员请勿修改*/
+
+
+/***************数据更新速率**加速度计使能**********/
+#define  SL_SC7A20_ODR_POWER_DOWN (uint8)0x00
+#define  SL_SC7A20_ODR_1HZ        (uint8)0x17
+#define  SL_SC7A20_ODR_10HZ       (uint8)0x27
+#define  SL_SC7A20_ODR_25HZ       (uint8)0x37
+#define  SL_SC7A20_ODR_50HZ       (uint8)0x47
+#define  SL_SC7A20_ODR_100HZ      (uint8)0x57
+#define  SL_SC7A20_ODR_200HZ      (uint8)0x67
+#define  SL_SC7A20_ODR_400HZ      (uint8)0x77
+#define  SL_SC7A20_ODR_1600HZ     (uint8)0x87
+#define  SL_SC7A20_ODR_1250HZ     (uint8)0x97
+#define  SL_SC7A20_ODR_5000HZ     (uint8)0x9F
+    
+#define  SL_SC7A20_LOWER_POWER_ODR_1HZ        (uint8)0x1F
+#define  SL_SC7A20_LOWER_POWER_ODR_10HZ       (uint8)0x2F
+#define  SL_SC7A20_LOWER_POWER_ODR_25HZ       (uint8)0x3F
+#define  SL_SC7A20_LOWER_POWER_ODR_50HZ       (uint8)0x4F
+#define  SL_SC7A20_LOWER_POWER_ODR_100HZ      (uint8)0x5F
+#define  SL_SC7A20_LOWER_POWER_ODR_200HZ      (uint8)0x6F
+#define  SL_SC7A20_LOWER_POWER_ODR_400HZ      (uint8)0x7F
+/***************数据更新速率**加速度计使能**********/
+
+
+/***************传感器量程设置**********************/
+#define  SL_SC7A20_FS_2G          (uint8)0x00
+#define  SL_SC7A20_FS_4G          (uint8)0x10
+#define  SL_SC7A20_FS_8G          (uint8)0x20
+#define  SL_SC7A20_FS_16G         (uint8)0x30
+/***************传感器量程设置**********************/
+
+
+/***取值在0-127之间，此处仅举例****/
+#define SL_SC7A20_INT_THS_5PERCENT   (uint8)0x06
+#define SL_SC7A20_INT_THS_10PERCENT  (uint8)0x0C
+#define SL_SC7A20_INT_THS_20PERCENT  (uint8)0x18
+#define SL_SC7A20_INT_THS_40PERCENT  (uint8)0x30
+#define SL_SC7A20_INT_THS_80PERCENT  (uint8)0x60
+
+
+/***取值在0-127之间，此处仅举例 乘以ODR单位时间****/
+#define SL_SC7A20_INT_DURATION_2CLK  (uint8)0x02
+#define SL_SC7A20_INT_DURATION_5CLK  (uint8)0x05
+#define SL_SC7A20_INT_DURATION_10CLK (uint8)0x0A
+#define SL_SC7A20_INT_DURATION_30CLK  (uint8)0x2E
+
+
+/***中断有效时的电平设置，高电平相当于上升沿，低电平相当于下降沿****/
+#define SL_SC7A20_INT_ACTIVE_LOWER_LEVEL 0x02 //0x02:中断时INT1脚输出 低电平
+#define SL_SC7A20_INT_ACTIVE_HIGH_LEVEL  0x00 //0x00:中断时INT1脚输出 高电平 
+
+/***中断有效时的电平设置，高电平相当于上升沿，低电平相当于下降沿****/
+#define SL_SC7A20_INT_AOI1_INT1          0x40 //AOI1 TO INT1
+#define SL_SC7A20_INT_AOI2_INT1          0x20 //AOI2 TO INT1
+
+/********客户需要进行的IIC接口封包函数****************/
+Std_ReturnType Gsensor_SPI_Write(uint8 Addr,uint8 *DataBufferPtr,uint16 Length);
+Std_ReturnType Gsensor_SPI_Read(uint8 Addr,uint8 *DataBufferPtr,uint16 Length);
+/**Gsensor_SPI_Write 函数中， sl_spi_iic:0=spi  1=i2c  Reg：寄存器地址   data：寄存器的配置值******************/
+/**Gsensor_SPI_Write 函数 是一个单次写的函数*******************************************************************/
+/***Gsensor_SPI_Read 函数中， sl_spi_iic:0=spi  1=i2c Reg 同上，len:读取数据长度，buf:存储数据首地址（指针）***/
+/***Gsensor_SPI_Read 函数 是可以进行单次读或多次连续读取的函数*************************************************/
+
+
+
+/*** 客户IIC函数封装举例
+uint8 SL_MEMS_i2c_spi_Write(uint8 reg, uint8 data)
+{
+    i2cWrite(SC7A20_IIC_ADDRESS,  reg,  data);       //由客户的II函数接口决定
+    return 1;
+}
+
+uint8 SL_MEMS_i2c_spi_Read(uint8 reg, uint8 len, uint8 *buf)
+{
+    i2cRead( SC7A20_IIC_ADDRESS,  reg,  len, buf);//由客户的II函数接口决定
+    return 1;
+}
+***/
+
+
+
+
+
+Std_ReturnType  SL_SC7A20_Online_Test(void);
+Std_ReturnType  SL_SC7A20_BOOT(void);
+Std_ReturnType  SL_SC7A20_INT_Config(void);
+Std_ReturnType  SL_SC7A20_INT_RESET(void);
+
+Std_ReturnType  SL_SC7A20_FS_Config(uint8 Sc7a20_FS_Reg);
+Std_ReturnType  SL_SC7A20_Power_Config(uint8 Power_Config_Reg);
+Std_ReturnType  SL_SC7A20_Read_XYZ_Data(sint16 *SL_SC7A20_Data_XYZ_Buf);
+void  SL_SC7A20_AOI1_event(void);
+void  SL_SC7A20_AOI2_event(void);
+void  SL_SC7A20_Reg_read_all(void);
+Std_ReturnType GsensorInit(void);
+
+//步骤如下：
+//0.signed char  SL_SC7A20_BOOT(void);
+//1.signed char  SL_SC7A20_Online_Test(void);
+//2.signed char  SL_SC7A20_FS_Config(uint8 Sc7a20_FS_Reg);
+//3.signed char  SL_SC7A20_Power_Config(uint8 Power_Config_Reg);
+//6.signed char  SL_SC7A20_Read_XYZ_Data(signed char  *SL_SC7A20_Data_XYZ_Buf);
+//6.signed char  SL_SC7A20_Read_XYZ_Data(signed short *SL_SC7A20_Data_XYZ_Buf);
+
+#endif /* __SL_SC7A20_DRIVER_H */
+

src/main.c

@@ -65,15 +65,15 @@ int main(void)
 	Mcu_InitClock(McuClockSettingConfig_0);
 
 	/* Wait until PLL is locked */
-	// while ( MCU_PLL_LOCKED != Mcu_GetPllStatus() )
+	 while ( MCU_PLL_LOCKED != Mcu_GetPllStatus() )
 	{
 		/* Busy wait until the System PLL is locked */
 	}
-	// Mcu_DistributePllClock();
+	 Mcu_DistributePllClock();
 	/* Initialize Mcl module */
 	Mcl_Init(NULL_PTR);
 
-	Mcu_SetMode(McuModeSettingConf_0);
+	Mcu_SetMode(McuModeSettingConf_Run);
 	OsIf_Init(NULL_PTR);
 	Platform_Init(NULL_PTR);
 	//    Platform_InstallIrqHandler(LPUART0_RxTx_IRQn, LPUART_UART_IP_0_IRQHandler, NULL_PTR);