/* * @Author : ChenJie * @Date : 2022-01-23 13:52:10 * @Version : V3.0 * @LastEditors : ChenJie * @LastEditTime : 2022-05-17 16:22:16 * @Description : file content * @FilePath : \S32K146_4G\src\hal_adapter.h */ /* * hal_adapter.h *中间层函数调用库 * Created on: 2022年1月18日 * Author: QiXiang_CHENJIE */ #ifndef HAL_ADAPTER_H_ #define HAL_ADAPTER_H_ #include "Mcal.h" #include "CAN.h" #include "SchM_Can.h" #include "Mcu.h" #include "Mcl.h" #include "Port.h" #include "Dio.h" #include "Uart.h" #include "Platform.h" #include "Lpuart_Uart_Ip_Irq.h" #include "Flexio_Uart_Ip_Irq.h" #include #include #include "Dma_Ip.h" #include "Dma_Ip_Irq.h" #include "Lpuart_Uart_Ip.h" #include "FreeRTOS.h" #include "timers.h" #include "task.h" #include "semphr.h" #include "Adc.h" #include "Eep.h" #include "Fls.h" #include "SchM_Fls.h" #include "SL_Sc7a20_Driver.h" #include "SEGGER_RTT_Conf.h" #include "SEGGER_RTT.h" #include "hal_Wdg.h" #include "rtwtypes.h" /*适应性定义*/ typedef unsigned char UINT8; typedef unsigned short UINT16; typedef unsigned long UINT32; typedef unsigned char BOOL; typedef signed char INT8; typedef signed short INT16; typedef signed long INT32; #define CAN0 0 #define CAN1 1 #ifndef min #define min(A, B) ((A) <= (B) ? (A) : (B)) #endif #ifndef max #define max(A, B) ((A) < (B) ? (B) : (A)) #endif #define getbit(x, y) ((x) >> (y)&1) // 获取x的第y位的数值 #define setbit(x, y) x |= (1 << y) // x的第y位置1 #define clrbit(x, y) x &= ~(1 << y) // x的第y位置0 #define UART_LPUART0 0 #define UART_LPUART1 1 #define UART_LPUART2 2 #define FLEXIO_RX 3 #define FLEXIO_TX 4 #define main_TASK_PRIORITY (tskIDLE_PRIORITY + 7) /*LED*/ #define LED_INDEX2 DioConf_DioChannel_PTE0_GPIO_OUT_MCU_LED1 #define LED_INDEX3 DioConf_DioChannel_PTE1_GPIO_OUT_MCU_LED2 #define LED_INDEX4 DioConf_DioChannel_PTE7_GPIO_OUT_MCU_LED3 #define MSG_LEN 50U #define TJA1153_START_ID (uint32_t)(0x555u) #define TJA1153_CONFIG_ID (uint32_t)(0x18DA00F1u) #define NUM_RESULTS ADC_CFGSET_VS_0_GROUP_0_CHANNELS #define BUFFER_SIZE 1024 #define DMA_SIZE 128 void Uart_Hal_RecvTask(void *pvParameters); void Uart_Hal_SendTask(void *pvParameters); typedef struct { uint8_t *source; uint32_t br; uint32_t bw; uint32_t btoRead; uint32_t length; } ringbuffer_t; typedef struct { uint16 DataLen; uint8 *dataPtr; uint32 dataAddr; } UartMsg_t; typedef struct { uint8 Channel; Lpuart_Uart_Ip_EventType event; uint16 value; } UartHalMsg_t; typedef enum { UartStartRecv = 0, UartAbortRecv, UartRecvOnGoing, UartRecvComplete, UartStartSend, UartAbortSend, UartSendOnGoing, UartSendComplete, UartNoDataSend, }; typedef enum { SystemTPChannel = 0, SlowChargeTPChannel, QuickChargeTPChannel, CC1TPChannel, ChannelCounter = 4, } ADC_TP_Channel_Type; typedef uint32 TP_Value_Type; /*CAN*/ typedef enum { CAN_STANDARD_ID_TYPE = 0x00, /**< * -00b CAN message with Standard CAN ID */ CANFD_STANDARD_ID_TYPE = 0x01, /**< * -01b CAN FD frame with Standard CAN ID */ CAN_EXTENDED_ID_TYPE = 0x02, /**< * -10b CAN message with Extended CAN ID */ CANFD_EXTENDED_ID_TYPE = 0x03, /**< * -11b CAN FD frame with Extended CAN ID */ } CAN_IdFrameType; typedef struct { Can_IdType id; CAN_IdFrameType idFrame; uint8 length; /**< @brief DLC = Data Length Code (part of L-PDU that describes the SDU length). */ uint8 *sdu; /**< @brief CAN L-SDU = Link Layer Service Data Unit. Data that is transported inside the L-PDU. */ } Can_Msg_Type; typedef struct { Can_IdType id; uint8 length; uint8 data[8]; } Can_Msg_Type_Data; /*EEP*/ typedef enum { EEP_FTFC_KEY_SIZE_0_BYTES = 0x0, /**< @brief control code for key size 0 bytes, used for the partitioning command */ EEP_FTFC_KEY_SIZE_128_BYTES = 0x1, /**< @brief control code for key size 128 bytes, used for the partitioning command */ EEP_FTFC_KEY_SIZE_256_BYTES = 0x2, /**< @brief control code for key size 256 bytes, used for the partitioning command */ EEP_FTFC_KEY_SIZE_512_BYTES = 0x3 /**< @brief control code for key size 512 bytes, used for the partitioning command */ } TestEep_CsecKeySize; /** @brief FlexRamPartition Type used for the partitioning command */ typedef enum { EEP_FTFC_EERAM_SIZE_0K = 0xF, /**< @brief control code for flexram partitioned as sram, used for the partitioning command */ EEP_FTFC_EERAM_SIZE_4K = 0x2, /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */ EEP_FTFC_EERAM_SIZE_2K = 0x3 /**< @brief control code for flexram partitioned as eeram, used for the partitioning command */ } TestEep_Eeprom_FlexRamPartitionType; /** @brief FlexNvmPartition Type used for the partitioning command */ typedef enum { EEP_FTFC_EEEPROM_SIZE_0K_V1 = 0x0, /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_0K_V2 = 0xC, /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_0K_V3 = 0x0F, /**< @brief control code to partition EEPROM backup size as 0K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_32K_V1 = 0x3, /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_32K_V2 = 0xB, /**< @brief control code to partition EEPROM backup size as 32K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_48K_V1 = 0xA, /**< @brief control code to partition EEPROM backup size as 48K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_64K_V1 = 0x8, /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_64K_V2 = 0x4, /**< @brief control code to partition EEPROM backup size as 64K, used for the partitioning command */ EEP_FTFC_EEEPROM_SIZE_24K_V2 = 0x9 /**< @brief control code to partition EEPROM backup size as 24K, used for the partitioning command */ } TestEep_Eeprom_FlexNvmPartitionType; /** @brief Sfe Type used for the partitioning command */ typedef enum { EEP_FTFC_VERIFY_ONLY_DISABLED = 0x0, /**< @brief control code for sfe verify only disabled, used for the partitioning command */ EEP_FTFC_VERIFY_ONLY_ENABLED = 0x1 /**< @brief control code for sfe verify only enabled, used for the partitioning command */ } TestEep_SfeType; /** @brief LoadFlexRam at reset Type used for the partitioning command */ typedef enum { EEP_FTFC_LOAD_AT_RESET_ENABLED = 0x0, /**< @brief control code for loading flexram at reset, used for the partitioning command */ EEP_FTFC_LOAD_AT_RESET_DISABLED = 0x1 /**< @brief control code for not loading flexram at reset, used for the partitioning command */ } TestEep_LoadFlexRamType; #define EEP_ERASE_START_ADD (0U) #define EEP_WRTESTPATT_SIZE (33U) #define EEP_RDTESTPATT_SIZE (33U) #define REG_WRITE8(address, value) (*((volatile uint8 *)(address)) = (value)) #define REG_BIT_GET8(address, mask) ((*(volatile uint8 *)(address)) & (mask)) #define T_EEEPROM_SIZE EEP_FTFC_EEEPROM_SIZE_32K_V2 #define TEST_EEP_EEPROM_FSTAT_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x00UL)) /**< @brief Eeprom Status Register (FTFE_FSTAT) */ #define TEST_EEP_EEPROM_FCCOB3_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x04UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB3) */ #define TEST_EEP_EEPROM_FCCOB2_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x05UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB2) */ #define TEST_EEP_EEPROM_FCCOB1_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x06UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB1) */ #define TEST_EEP_EEPROM_FCCOB0_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x07UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB0) */ #define TEST_EEP_EEPROM_FCCOB7_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x08UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB7) */ #define TEST_EEP_EEPROM_FCCOB6_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x09UL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB6) */ #define TEST_EEP_EEPROM_FCCOB5_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x0AUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB5) */ #define TEST_EEP_EEPROM_FCCOB4_ADDR32 ((uint32)(IP_FTFC_BASE + (uint32)0x0BUL)) /**< @brief Eeprom Common Command Object Registers(FTFE_FCCOB4) */ #define TEST_EEP_EEPROM_FSTAT_CCIF_U8 (0x0080U) #define TEST_EEP_EEPROM_FSTAT_ACCERR_U8 (0x0020U) #define TEST_EEP_EEPROM_FSTAT_FPVIOL_U8 (0x0010U) /* Start address for DFLASH sector 0 */ #define TEST_EEP_DEEPROM_SECTOR_0_ADDR32 0x10000000 #define D_EEPROM_BASE_ADDR (0x10000000UL) #define TEST_EEP_EEPROM_CMD_ERASE_SECTOR (0x09UL) #define EEPROM_CMD_PROGRAM_PARTITION (0x80UL) extern Std_ReturnType CanIf_SendMessage(uint8 ControllerId, Can_Msg_Type CanMsg); void Eep_DepartParitition(TestEep_Eeprom_FlexNvmPartitionType T_EEP_SIZE); Std_ReturnType HAL_EEP_Erase(uint32 eepEraseStartAddr, uint32 eepEraseSize); Std_ReturnType HAL_EEP_Read(uint32 eepReadStartAddr, uint8 *pDataBuffer, uint32 dataSize); Std_ReturnType HAL_EEP_Write(uint32 eepWriteStartAddr, uint8 *pDataNeedtoWrite, uint32 dataSize); Std_ReturnType HAL_EEP_Compare(uint32 eepCompareStartAddr, uint8 *pDataNeedtoCompare, uint32 dataSize); Std_ReturnType ADC_ReadValue(void); sint8 AtcmdDelayRecvFunc(uint8 recvChannel, char *ResultStrPtr, uint16 delayTime); Std_ReturnType UART_Query_Data(uint8 transChannel, uint8 recvChannel, uint8 *txBuffer, uint16 sendLength, uint8 *rxBuffer, uint16 *rxlen, uint32 T_timeout); Std_ReturnType UART_Send_Data(uint8 transChannel, const uint8 *txBuffer, uint32 sendLength, uint32 T_timeout); Std_ReturnType UART_Receive_Data(uint8 recvChannel, uint8 *rxBuffer, uint8 *rxlen, uint32 T_timeout); Std_ReturnType UART_Reset(uint8 recvChannel); void UART_Callback(uint32 hwInstance, Lpuart_Uart_Ip_EventType event); void UartInit(void); void SystemSoftwareReset(void); void create_ringBuffer(ringbuffer_t *ringBuf, uint8_t *buf, uint32_t buf_len); void clear_ringBuffer(ringbuffer_t *ringBuf); uint32_t write_ringBuffer(uint8_t *buffer, uint32_t size, ringbuffer_t *ringBuf); uint32_t read_ringBuffer(uint8_t *buffer, uint32_t size, ringbuffer_t *ringBuf); void coreInit(void); void SystemModulesInit(void); void Icu_DeInit(void); void SystemDeinit(void); void MCUSleep(void); void MCUEnterSleep(void); void displayResetReasonWithLED(void); #endif /* HAL_ADAPTER_H_ */