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- #ifndef ADC_IP_HW_ACCESS_H
- #define ADC_IP_HW_ACCESS_H
- #include "StandardTypes.h"
- #define ADC_IP_VENDOR_ID_HWACCESS_H 43
- #define ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H 4
- #define ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H 4
- #define ADC_IP_AR_RELEASE_REVISION_VERSION_HWACCESS_H 0
- #define ADC_IP_SW_MAJOR_VERSION_HWACCESS_H 1
- #define ADC_IP_SW_MINOR_VERSION_HWACCESS_H 0
- #define ADC_IP_SW_PATCH_VERSION_HWACCESS_H 0
- #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
- #if ((ADC_IP_AR_RELEASE_MAJOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MAJOR_VERSION) || \
- (ADC_IP_AR_RELEASE_MINOR_VERSION_HWACCESS_H != STD_AR_RELEASE_MINOR_VERSION) \
- )
- #error "AutoSar Version Numbers of Adc_Ip_HwAccess.h and StandardTypes.h are different"
- #endif
- #endif
- #if defined (__cplusplus)
- extern "C" {
- #endif
- #define ADC_START_SEC_CODE
- #include "Adc_MemMap.h"
- static inline void Adc_HwAcc_SetSC2Reg(ADC_Type * const Base, const uint32 ClearMask, const uint32 Value)
- {
-
- uint32 Sc2Reg = Base->SC2;
- Sc2Reg &= ~(ClearMask);
- Sc2Reg |= Value;
- Base->SC2 = Sc2Reg;
- }
- static inline void Adc_HwAcc_SetClock(ADC_Type * const Base, const Adc_Ip_ClockSelType ClockDivide, const Adc_Ip_ClkSourceType InputClock)
- {
-
- uint32 Cfg1Reg = Base->CFG1;
- Cfg1Reg &= ~(ADC_CFG1_ADIV_MASK | ADC_CFG1_ADICLK_MASK);
- Cfg1Reg |= ADC_CFG1_ADIV(ClockDivide);
- Cfg1Reg |= ADC_CFG1_ADICLK(InputClock);
- Base->CFG1 = Cfg1Reg;
- }
- static inline Adc_Ip_ClockSelType Adc_HwAcc_GetClockDivide(const uint32 Reg)
- {
-
- Adc_Ip_ClockSelType ReturnValue = ADC_IP_CLK_FULL_BUS;
- switch ((Reg & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
- {
- case 1u:
- ReturnValue = ADC_IP_CLK_HALF_BUS;
- break;
- case 2u:
- ReturnValue = ADC_IP_CLK_QUARTER_BUS;
- break;
- case 3u:
- ReturnValue = ADC_IP_CLK_EIGHTH_BUS;
- break;
- default:
- ;
- break;
- }
- return ReturnValue;
- }
- static inline Adc_Ip_ClkSourceType Adc_HwAcc_GetInputClock(const uint32 Reg)
- {
-
- Adc_Ip_ClkSourceType ReturnValue = ADC_IP_CLK_ALT_1;
- switch ((Reg & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
- {
- case 1u:
- ReturnValue = ADC_IP_CLK_ALT_2;
- break;
- case 2u:
- ReturnValue = ADC_IP_CLK_ALT_3;
- break;
- case 3u:
- ReturnValue = ADC_IP_CLK_ALT_4;
- break;
- default:
- ;
- break;
- }
- return ReturnValue;
- }
- static inline void Adc_HwAcc_SetSampleTime(ADC_Type * const Base, const uint8 SampleTime)
- {
-
- uint8 ClippedSampleTime = (uint8)((SampleTime > 0U) ? SampleTime : 1U);
-
- uint32 Cfg2Reg = Base->CFG2;
- Cfg2Reg &= ~(ADC_CFG2_SMPLTS_MASK);
- Cfg2Reg |= ADC_CFG2_SMPLTS(ClippedSampleTime);
- Base->CFG2 = Cfg2Reg;
- }
- static inline void Adc_HwAcc_SetAveraging(ADC_Type * const Base, const boolean AvgEn, const Adc_Ip_AvgSelectType AvgSel)
- {
-
- uint32 Sc3Reg = Base->SC3;
- Sc3Reg &= ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
- Sc3Reg |= ADC_SC3_AVGE(AvgEn ? 1u : 0u);
- Sc3Reg |= ADC_SC3_AVGS(AvgSel);
- Base->SC3 = Sc3Reg;
- }
- static inline Adc_Ip_AvgSelectType Adc_HwAcc_GetAverageSelect(const uint32 Reg)
- {
-
- Adc_Ip_AvgSelectType ReturnValue = ADC_IP_AVG_4_CONV;
- switch ((Reg & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
- {
- case 1u:
- ReturnValue = ADC_IP_AVG_8_CONV;
- break;
- case 2u:
- ReturnValue = ADC_IP_AVG_16_CONV;
- break;
- case 3u:
- ReturnValue = ADC_IP_AVG_32_CONV;
- break;
- default:
- ;
- break;
- }
- return ReturnValue;
- }
- static inline void Adc_HwAcc_SetTriggerMode(ADC_Type * const Base, const Adc_Ip_TrigType TriggerMode)
- {
-
- uint32 Sc2Reg = Base->SC2;
- Sc2Reg &= ~(ADC_SC2_ADTRG_MASK);
- Sc2Reg |= ADC_SC2_ADTRG(TriggerMode);
- Base->SC2 = Sc2Reg;
- }
- static inline Adc_Ip_TrigType Adc_HwAcc_GetTriggerMode(const uint32 Reg)
- {
-
- Adc_Ip_TrigType ReturnValue = ADC_IP_TRIGGER_SOFTWARE;
- if (((Reg & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT) == 1u)
- {
- ReturnValue = ADC_IP_TRIGGER_HARDWARE;
- }
- return ReturnValue;
- }
- static inline void Adc_HwAcc_SetChannel(ADC_Type * const Base, const uint8 ChnIdx, const Adc_Ip_InputChannelType InputChannel, const boolean InterruptEnable)
- {
-
- uint32 Sc1Reg = SC1(Base, ChnIdx);
- Sc1Reg &= ~(ADC_SC1_ADCH_MASK | ADC_SC1_AIEN_MASK);
- Sc1Reg |= ADC_SC1_ADCH(InputChannel);
- Sc1Reg |= ADC_SC1_AIEN(InterruptEnable ? 1u : 0u);
- SC1(Base, ChnIdx) = Sc1Reg;
- }
- static inline void Adc_HwAcc_SetUserGainAndOffset(ADC_Type * const Base, const uint16 UsrGain, const uint16 UsrOffset)
- {
-
- Base->USR_OFS = ADC_USR_OFS_USR_OFS(UsrOffset);
- Base->UG = ADC_UG_UG(UsrGain);
- }
- static inline boolean Adc_HwAcc_GetAIEN(const uint32 Reg)
- {
-
- return (((Reg & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT) != 0u) ? TRUE : FALSE;
- }
- static inline boolean Adc_HwAcc_GetCOCO(const uint32 Reg)
- {
-
- return (((Reg & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT) != 0u) ? TRUE : FALSE;
- }
- static inline uint16 Adc_HwAcc_GetData(const ADC_Type * const Base, const uint8 ChnIdx)
- {
-
- uint16 Result = (uint16) R(Base, ChnIdx);
- Result = (uint16) ((Result & ADC_R_D_MASK) >> ADC_R_D_SHIFT);
- return Result;
- }
- #define ADC_STOP_SEC_CODE
- #include "Adc_MemMap.h"
- #if defined (__cplusplus)
- }
- #endif
- #endif
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