SchM_Ocu.c 47 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188
  1. /*==================================================================================================
  2. * Project : RTD AUTOSAR 4.4
  3. * Platform : CORTEXM
  4. * Peripheral :
  5. * Dependencies : none
  6. *
  7. * Autosar Version : 4.4.0
  8. * Autosar Revision : ASR_REL_4_4_REV_0000
  9. * Autosar Conf.Variant :
  10. * SW Version : 1.0.0
  11. * Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
  12. *
  13. * (c) Copyright 2020-2021 NXP Semiconductors
  14. * All Rights Reserved.
  15. *
  16. * NXP Confidential. This software is owned or controlled by NXP and may only be
  17. * used strictly in accordance with the applicable license terms. By expressly
  18. * accepting such terms or by downloading, installing, activating and/or otherwise
  19. * using the software, you are agreeing that you have read, and that you agree to
  20. * comply with and are bound by, such license terms. If you do not agree to be
  21. * bound by the applicable license terms, then you may not retain, install,
  22. * activate or otherwise use the software.
  23. ==================================================================================================*/
  24. /**
  25. * @file
  26. *
  27. * @addtogroup RTE_MODULE
  28. * @{
  29. */
  30. #ifdef __cplusplus
  31. extern "C"{
  32. #endif
  33. /*==================================================================================================
  34. * INCLUDE FILES
  35. * 1) system and project includes
  36. * 2) needed interfaces from external units
  37. * 3) internal and external interfaces from this unit
  38. ==================================================================================================*/
  39. #include "Std_Types.h"
  40. #include "Mcal.h"
  41. #include "OsIf.h"
  42. #include "SchM_Ocu.h"
  43. #ifdef MCAL_TESTING_ENVIRONMENT
  44. #include "EUnit.h" /* EUnit Test Suite */
  45. #endif
  46. /*==================================================================================================
  47. * SOURCE FILE VERSION INFORMATION
  48. ==================================================================================================*/
  49. #define SCHM_OCU_AR_RELEASE_MAJOR_VERSION_C 4
  50. #define SCHM_OCU_AR_RELEASE_MINOR_VERSION_C 4
  51. #define SCHM_OCU_AR_RELEASE_REVISION_VERSION_C 0
  52. #define SCHM_OCU_SW_MAJOR_VERSION_C 1
  53. #define SCHM_OCU_SW_MINOR_VERSION_C 0
  54. #define SCHM_OCU_SW_PATCH_VERSION_C 0
  55. /*==================================================================================================
  56. * LOCAL CONSTANTS
  57. ==================================================================================================*/
  58. #ifdef MCAL_PLATFORM_ARM
  59. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  60. #define ISR_STATE_MASK ((uint32)0x00000002UL) /**< @brief DAIF bit I and F */
  61. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  62. #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
  63. #else
  64. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  65. #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
  66. #else
  67. #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
  68. #endif
  69. #endif
  70. #else
  71. #ifdef MCAL_PLATFORM_S12
  72. #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
  73. #else
  74. #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
  75. #endif
  76. #endif
  77. /*==================================================================================================
  78. * LOCAL MACROS
  79. ==================================================================================================*/
  80. #ifdef MCAL_PLATFORM_ARM
  81. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  82. #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)3)
  83. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  84. #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
  85. #else
  86. #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
  87. #endif
  88. #else
  89. #ifdef MCAL_PLATFORM_S12
  90. #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
  91. #else
  92. #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
  93. #endif
  94. #endif
  95. /*==================================================================================================
  96. * FILE VERSION CHECKS
  97. ==================================================================================================*/
  98. /*==================================================================================================
  99. * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
  100. ==================================================================================================*/
  101. /*==================================================================================================
  102. * LOCAL VARIABLES
  103. ==================================================================================================*/
  104. #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
  105. #include "Rte_MemMap.h"
  106. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
  107. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
  108. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
  109. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
  110. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
  111. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
  112. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
  113. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
  114. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
  115. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
  116. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
  117. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
  118. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
  119. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
  120. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
  121. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
  122. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
  123. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
  124. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
  125. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
  126. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
  127. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
  128. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
  129. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
  130. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
  131. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
  132. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
  133. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
  134. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
  135. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
  136. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
  137. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
  138. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
  139. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
  140. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
  141. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
  142. static volatile uint32 msr_OCU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
  143. static volatile uint32 reentry_guard_OCU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
  144. #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
  145. #include "Rte_MemMap.h"
  146. /*==================================================================================================
  147. * GLOBAL CONSTANTS
  148. ==================================================================================================*/
  149. /*==================================================================================================
  150. * GLOBAL VARIABLES
  151. ==================================================================================================*/
  152. /*==================================================================================================
  153. * LOCAL FUNCTION PROTOTYPES
  154. ==================================================================================================*/
  155. #ifndef _COSMIC_C_S32K1XX_
  156. /*================================================================================================*/
  157. /**
  158. * @brief This function returns the MSR register value (32 bits).
  159. * @details This function returns the MSR register value (32 bits).
  160. *
  161. * @param[in] void No input parameters
  162. * @return uint32 msr This function returns the MSR register value (32 bits).
  163. *
  164. * @pre None
  165. * @post None
  166. *
  167. */
  168. uint32 Ocu_schm_read_msr(void);
  169. #endif /*ifndef _COSMIC_C_S32K1XX_*/
  170. /*==================================================================================================
  171. * LOCAL FUNCTIONS
  172. ==================================================================================================*/
  173. #define RTE_START_SEC_CODE
  174. #include "Rte_MemMap.h"
  175. #if (defined(_GREENHILLS_C_S32K1XX_) || defined(_CODEWARRIOR_C_S32K1XX_))
  176. /*================================================================================================*/
  177. /**
  178. * @brief This macro returns the MSR register value (32 bits).
  179. * @details This macro function implementation returns the MSR register value in r3 (32 bits).
  180. *
  181. * @pre None
  182. * @post None
  183. *
  184. */
  185. #ifdef MCAL_PLATFORM_ARM
  186. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  187. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  188. {
  189. mrs x0, S3_3_c4_c2_1
  190. }
  191. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  192. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  193. {
  194. mrs r0, CPSR
  195. }
  196. #else
  197. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  198. {
  199. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  200. mrs r0, BASEPRI
  201. #else
  202. mrs r0, PRIMASK
  203. #endif
  204. }
  205. #endif
  206. #else
  207. #ifdef MCAL_PLATFORM_S12
  208. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  209. {
  210. tfr ccr, d6
  211. }
  212. #else
  213. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  214. {
  215. mfmsr r3
  216. }
  217. #endif
  218. #endif
  219. #endif /*#ifdef GHS||CW*/
  220. #ifdef _DIABDATA_C_S32K1XX_
  221. /**
  222. * @brief This function returns the MSR register value (32 bits).
  223. * @details This function returns the MSR register value (32 bits).
  224. *
  225. * @param[in] void No input parameters
  226. * @return uint32 msr This function returns the MSR register value (32 bits).
  227. *
  228. * @pre None
  229. * @post None
  230. *
  231. */
  232. #ifdef MCAL_PLATFORM_ARM
  233. uint32 Ocu_schm_read_msr(void)
  234. {
  235. register uint32 reg_tmp;
  236. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  237. __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
  238. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  239. __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
  240. #else
  241. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  242. __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
  243. #else
  244. __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
  245. #endif
  246. #endif
  247. return (uint32)reg_tmp;
  248. }
  249. #else
  250. ASM_KEYWORD uint32 Ocu_schm_read_msr(void)
  251. {
  252. mfmsr r3
  253. }
  254. #endif /* MCAL_PLATFORM_ARM */
  255. #endif /* _DIABDATA_C_S32K1XX_*/
  256. #ifdef _COSMIC_C_S32K1XX_
  257. /*================================================================================================*/
  258. /**
  259. * @brief This function returns the MSR register value (32 bits).
  260. * @details This function returns the MSR register value (32 bits).
  261. *
  262. * @param[in] void No input parameters
  263. * @return uint32 msr This function returns the MSR register value (32 bits).
  264. *
  265. * @pre None
  266. * @post None
  267. *
  268. */
  269. #ifdef MCAL_PLATFORM_S12
  270. #define Ocu_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
  271. #else
  272. #define Ocu_schm_read_msr() ASM_KEYWORD("mfmsr r3")
  273. #endif
  274. #endif /*Cosmic compiler only*/
  275. #ifdef _HITECH_C_S32K1XX_
  276. /*================================================================================================*/
  277. /**
  278. * @brief This function returns the MSR register value (32 bits).
  279. * @details This function returns the MSR register value (32 bits).
  280. *
  281. * @param[in] void No input parameters
  282. * @return uint32 msr This function returns the MSR register value (32 bits).
  283. *
  284. * @pre None
  285. * @post None
  286. *
  287. */
  288. uint32 Ocu_schm_read_msr(void)
  289. {
  290. uint32 result;
  291. __asm volatile("mfmsr %0" : "=r" (result) :);
  292. return result;
  293. }
  294. #endif /*HighTec compiler only*/
  295. /*================================================================================================*/
  296. #ifdef _LINARO_C_S32K1XX_
  297. /**
  298. * @brief This function returns the MSR register value (32 bits).
  299. * @details This function returns the MSR register value (32 bits).
  300. *
  301. * @param[in] void No input parameters
  302. * @return uint32 msr This function returns the MSR register value (32 bits).
  303. *
  304. * @pre None
  305. * @post None
  306. *
  307. */
  308. uint32 Ocu_schm_read_msr(void)
  309. {
  310. register uint32 reg_tmp;
  311. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  312. __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
  313. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  314. __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
  315. #else
  316. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  317. __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
  318. #else
  319. __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
  320. #endif
  321. #endif
  322. return (uint32)reg_tmp;
  323. }
  324. #endif /* _LINARO_C_S32K1XX_*/
  325. /*================================================================================================*/
  326. #ifdef _ARM_DS5_C_S32K1XX_
  327. /**
  328. * @brief This function returns the MSR register value (32 bits).
  329. * @details This function returns the MSR register value (32 bits).
  330. *
  331. * @param[in] void No input parameters
  332. * @return uint32 msr This function returns the MSR register value (32 bits).
  333. *
  334. * @pre None
  335. * @post None
  336. *
  337. */
  338. uint32 Ocu_schm_read_msr(void)
  339. {
  340. register uint32 reg_tmp;
  341. #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
  342. __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
  343. #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
  344. __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
  345. #else
  346. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  347. __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
  348. #else
  349. __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
  350. #endif
  351. #endif
  352. return (uint32)reg_tmp;
  353. }
  354. #endif /* _ARM_DS5_C_S32K1XX_ */
  355. #ifdef _IAR_C_S32K1XX_
  356. /**
  357. * @brief This function returns the MSR register value (32 bits).
  358. * @details This function returns the MSR register value (32 bits).
  359. *
  360. * @param[in] void No input parameters
  361. * @return uint32 msr This function returns the MSR register value (32 bits).
  362. *
  363. * @pre None
  364. * @post None
  365. *
  366. */
  367. uint32 Ocu_schm_read_msr(void)
  368. {
  369. register uint32 reg_tmp;
  370. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  371. __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
  372. #else
  373. __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
  374. #endif
  375. return (uint32)reg_tmp;
  376. }
  377. #endif /* _IAR_C_S32K1XX_ */
  378. #define RTE_STOP_SEC_CODE
  379. #include "Rte_MemMap.h"
  380. /*==================================================================================================
  381. * GLOBAL FUNCTIONS
  382. ==================================================================================================*/
  383. #define RTE_START_SEC_CODE
  384. #include "Rte_MemMap.h"
  385. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_00(void)
  386. {
  387. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  388. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId])
  389. {
  390. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  391. msr_OCU_EXCLUSIVE_AREA_00[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  392. #else
  393. msr_OCU_EXCLUSIVE_AREA_00[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  394. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  395. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_00[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  396. {
  397. OsIf_SuspendAllInterrupts();
  398. #ifdef _ARM_DS5_C_S32K1XX_
  399. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  400. #endif
  401. }
  402. }
  403. reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId]++;
  404. }
  405. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_00(void)
  406. {
  407. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  408. reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId]--;
  409. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
  410. {
  411. OsIf_ResumeAllInterrupts();
  412. #ifdef _ARM_DS5_C_S32K1XX_
  413. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  414. #endif
  415. }
  416. }
  417. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_01(void)
  418. {
  419. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  420. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId])
  421. {
  422. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  423. msr_OCU_EXCLUSIVE_AREA_01[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  424. #else
  425. msr_OCU_EXCLUSIVE_AREA_01[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  426. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  427. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_01[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  428. {
  429. OsIf_SuspendAllInterrupts();
  430. #ifdef _ARM_DS5_C_S32K1XX_
  431. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  432. #endif
  433. }
  434. }
  435. reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId]++;
  436. }
  437. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_01(void)
  438. {
  439. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  440. reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId]--;
  441. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
  442. {
  443. OsIf_ResumeAllInterrupts();
  444. #ifdef _ARM_DS5_C_S32K1XX_
  445. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  446. #endif
  447. }
  448. }
  449. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_02(void)
  450. {
  451. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  452. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId])
  453. {
  454. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  455. msr_OCU_EXCLUSIVE_AREA_02[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  456. #else
  457. msr_OCU_EXCLUSIVE_AREA_02[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  458. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  459. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_02[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  460. {
  461. OsIf_SuspendAllInterrupts();
  462. #ifdef _ARM_DS5_C_S32K1XX_
  463. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  464. #endif
  465. }
  466. }
  467. reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId]++;
  468. }
  469. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_02(void)
  470. {
  471. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  472. reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId]--;
  473. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
  474. {
  475. OsIf_ResumeAllInterrupts();
  476. #ifdef _ARM_DS5_C_S32K1XX_
  477. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  478. #endif
  479. }
  480. }
  481. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_03(void)
  482. {
  483. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  484. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId])
  485. {
  486. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  487. msr_OCU_EXCLUSIVE_AREA_03[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  488. #else
  489. msr_OCU_EXCLUSIVE_AREA_03[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  490. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  491. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_03[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  492. {
  493. OsIf_SuspendAllInterrupts();
  494. #ifdef _ARM_DS5_C_S32K1XX_
  495. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  496. #endif
  497. }
  498. }
  499. reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId]++;
  500. }
  501. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_03(void)
  502. {
  503. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  504. reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId]--;
  505. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
  506. {
  507. OsIf_ResumeAllInterrupts();
  508. #ifdef _ARM_DS5_C_S32K1XX_
  509. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  510. #endif
  511. }
  512. }
  513. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_04(void)
  514. {
  515. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  516. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId])
  517. {
  518. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  519. msr_OCU_EXCLUSIVE_AREA_04[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  520. #else
  521. msr_OCU_EXCLUSIVE_AREA_04[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  522. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  523. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_04[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  524. {
  525. OsIf_SuspendAllInterrupts();
  526. #ifdef _ARM_DS5_C_S32K1XX_
  527. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  528. #endif
  529. }
  530. }
  531. reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId]++;
  532. }
  533. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_04(void)
  534. {
  535. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  536. reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId]--;
  537. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
  538. {
  539. OsIf_ResumeAllInterrupts();
  540. #ifdef _ARM_DS5_C_S32K1XX_
  541. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  542. #endif
  543. }
  544. }
  545. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_05(void)
  546. {
  547. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  548. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId])
  549. {
  550. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  551. msr_OCU_EXCLUSIVE_AREA_05[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  552. #else
  553. msr_OCU_EXCLUSIVE_AREA_05[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  554. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  555. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_05[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  556. {
  557. OsIf_SuspendAllInterrupts();
  558. #ifdef _ARM_DS5_C_S32K1XX_
  559. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  560. #endif
  561. }
  562. }
  563. reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId]++;
  564. }
  565. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_05(void)
  566. {
  567. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  568. reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId]--;
  569. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
  570. {
  571. OsIf_ResumeAllInterrupts();
  572. #ifdef _ARM_DS5_C_S32K1XX_
  573. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  574. #endif
  575. }
  576. }
  577. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_06(void)
  578. {
  579. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  580. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId])
  581. {
  582. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  583. msr_OCU_EXCLUSIVE_AREA_06[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  584. #else
  585. msr_OCU_EXCLUSIVE_AREA_06[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  586. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  587. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_06[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  588. {
  589. OsIf_SuspendAllInterrupts();
  590. #ifdef _ARM_DS5_C_S32K1XX_
  591. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  592. #endif
  593. }
  594. }
  595. reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId]++;
  596. }
  597. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_06(void)
  598. {
  599. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  600. reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId]--;
  601. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
  602. {
  603. OsIf_ResumeAllInterrupts();
  604. #ifdef _ARM_DS5_C_S32K1XX_
  605. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  606. #endif
  607. }
  608. }
  609. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_07(void)
  610. {
  611. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  612. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId])
  613. {
  614. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  615. msr_OCU_EXCLUSIVE_AREA_07[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  616. #else
  617. msr_OCU_EXCLUSIVE_AREA_07[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  618. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  619. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_07[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  620. {
  621. OsIf_SuspendAllInterrupts();
  622. #ifdef _ARM_DS5_C_S32K1XX_
  623. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  624. #endif
  625. }
  626. }
  627. reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId]++;
  628. }
  629. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_07(void)
  630. {
  631. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  632. reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId]--;
  633. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
  634. {
  635. OsIf_ResumeAllInterrupts();
  636. #ifdef _ARM_DS5_C_S32K1XX_
  637. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  638. #endif
  639. }
  640. }
  641. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_10(void)
  642. {
  643. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  644. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId])
  645. {
  646. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  647. msr_OCU_EXCLUSIVE_AREA_10[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  648. #else
  649. msr_OCU_EXCLUSIVE_AREA_10[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  650. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  651. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_10[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  652. {
  653. OsIf_SuspendAllInterrupts();
  654. #ifdef _ARM_DS5_C_S32K1XX_
  655. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  656. #endif
  657. }
  658. }
  659. reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId]++;
  660. }
  661. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_10(void)
  662. {
  663. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  664. reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId]--;
  665. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
  666. {
  667. OsIf_ResumeAllInterrupts();
  668. #ifdef _ARM_DS5_C_S32K1XX_
  669. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  670. #endif
  671. }
  672. }
  673. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_11(void)
  674. {
  675. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  676. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId])
  677. {
  678. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  679. msr_OCU_EXCLUSIVE_AREA_11[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  680. #else
  681. msr_OCU_EXCLUSIVE_AREA_11[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  682. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  683. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_11[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  684. {
  685. OsIf_SuspendAllInterrupts();
  686. #ifdef _ARM_DS5_C_S32K1XX_
  687. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  688. #endif
  689. }
  690. }
  691. reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId]++;
  692. }
  693. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_11(void)
  694. {
  695. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  696. reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId]--;
  697. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
  698. {
  699. OsIf_ResumeAllInterrupts();
  700. #ifdef _ARM_DS5_C_S32K1XX_
  701. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  702. #endif
  703. }
  704. }
  705. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_12(void)
  706. {
  707. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  708. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId])
  709. {
  710. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  711. msr_OCU_EXCLUSIVE_AREA_12[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  712. #else
  713. msr_OCU_EXCLUSIVE_AREA_12[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  714. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  715. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_12[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  716. {
  717. OsIf_SuspendAllInterrupts();
  718. #ifdef _ARM_DS5_C_S32K1XX_
  719. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  720. #endif
  721. }
  722. }
  723. reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId]++;
  724. }
  725. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_12(void)
  726. {
  727. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  728. reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId]--;
  729. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
  730. {
  731. OsIf_ResumeAllInterrupts();
  732. #ifdef _ARM_DS5_C_S32K1XX_
  733. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  734. #endif
  735. }
  736. }
  737. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_13(void)
  738. {
  739. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  740. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId])
  741. {
  742. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  743. msr_OCU_EXCLUSIVE_AREA_13[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  744. #else
  745. msr_OCU_EXCLUSIVE_AREA_13[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  746. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  747. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_13[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  748. {
  749. OsIf_SuspendAllInterrupts();
  750. #ifdef _ARM_DS5_C_S32K1XX_
  751. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  752. #endif
  753. }
  754. }
  755. reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId]++;
  756. }
  757. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_13(void)
  758. {
  759. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  760. reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId]--;
  761. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
  762. {
  763. OsIf_ResumeAllInterrupts();
  764. #ifdef _ARM_DS5_C_S32K1XX_
  765. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  766. #endif
  767. }
  768. }
  769. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_14(void)
  770. {
  771. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  772. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId])
  773. {
  774. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  775. msr_OCU_EXCLUSIVE_AREA_14[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  776. #else
  777. msr_OCU_EXCLUSIVE_AREA_14[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  778. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  779. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_14[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  780. {
  781. OsIf_SuspendAllInterrupts();
  782. #ifdef _ARM_DS5_C_S32K1XX_
  783. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  784. #endif
  785. }
  786. }
  787. reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId]++;
  788. }
  789. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_14(void)
  790. {
  791. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  792. reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId]--;
  793. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
  794. {
  795. OsIf_ResumeAllInterrupts();
  796. #ifdef _ARM_DS5_C_S32K1XX_
  797. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  798. #endif
  799. }
  800. }
  801. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_15(void)
  802. {
  803. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  804. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId])
  805. {
  806. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  807. msr_OCU_EXCLUSIVE_AREA_15[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  808. #else
  809. msr_OCU_EXCLUSIVE_AREA_15[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  810. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  811. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_15[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  812. {
  813. OsIf_SuspendAllInterrupts();
  814. #ifdef _ARM_DS5_C_S32K1XX_
  815. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  816. #endif
  817. }
  818. }
  819. reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId]++;
  820. }
  821. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_15(void)
  822. {
  823. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  824. reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId]--;
  825. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
  826. {
  827. OsIf_ResumeAllInterrupts();
  828. #ifdef _ARM_DS5_C_S32K1XX_
  829. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  830. #endif
  831. }
  832. }
  833. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_16(void)
  834. {
  835. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  836. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId])
  837. {
  838. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  839. msr_OCU_EXCLUSIVE_AREA_16[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  840. #else
  841. msr_OCU_EXCLUSIVE_AREA_16[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  842. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  843. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_16[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  844. {
  845. OsIf_SuspendAllInterrupts();
  846. #ifdef _ARM_DS5_C_S32K1XX_
  847. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  848. #endif
  849. }
  850. }
  851. reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId]++;
  852. }
  853. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_16(void)
  854. {
  855. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  856. reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId]--;
  857. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
  858. {
  859. OsIf_ResumeAllInterrupts();
  860. #ifdef _ARM_DS5_C_S32K1XX_
  861. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  862. #endif
  863. }
  864. }
  865. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_20(void)
  866. {
  867. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  868. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId])
  869. {
  870. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  871. msr_OCU_EXCLUSIVE_AREA_20[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  872. #else
  873. msr_OCU_EXCLUSIVE_AREA_20[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  874. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  875. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_20[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  876. {
  877. OsIf_SuspendAllInterrupts();
  878. #ifdef _ARM_DS5_C_S32K1XX_
  879. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  880. #endif
  881. }
  882. }
  883. reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId]++;
  884. }
  885. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_20(void)
  886. {
  887. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  888. reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId]--;
  889. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
  890. {
  891. OsIf_ResumeAllInterrupts();
  892. #ifdef _ARM_DS5_C_S32K1XX_
  893. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  894. #endif
  895. }
  896. }
  897. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_21(void)
  898. {
  899. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  900. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId])
  901. {
  902. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  903. msr_OCU_EXCLUSIVE_AREA_21[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  904. #else
  905. msr_OCU_EXCLUSIVE_AREA_21[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  906. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  907. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_21[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  908. {
  909. OsIf_SuspendAllInterrupts();
  910. #ifdef _ARM_DS5_C_S32K1XX_
  911. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  912. #endif
  913. }
  914. }
  915. reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId]++;
  916. }
  917. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_21(void)
  918. {
  919. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  920. reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId]--;
  921. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
  922. {
  923. OsIf_ResumeAllInterrupts();
  924. #ifdef _ARM_DS5_C_S32K1XX_
  925. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  926. #endif
  927. }
  928. }
  929. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_22(void)
  930. {
  931. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  932. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId])
  933. {
  934. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  935. msr_OCU_EXCLUSIVE_AREA_22[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  936. #else
  937. msr_OCU_EXCLUSIVE_AREA_22[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  938. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  939. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_22[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  940. {
  941. OsIf_SuspendAllInterrupts();
  942. #ifdef _ARM_DS5_C_S32K1XX_
  943. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  944. #endif
  945. }
  946. }
  947. reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId]++;
  948. }
  949. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_22(void)
  950. {
  951. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  952. reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId]--;
  953. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
  954. {
  955. OsIf_ResumeAllInterrupts();
  956. #ifdef _ARM_DS5_C_S32K1XX_
  957. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  958. #endif
  959. }
  960. }
  961. void SchM_Enter_Ocu_OCU_EXCLUSIVE_AREA_23(void)
  962. {
  963. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  964. if(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId])
  965. {
  966. #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
  967. msr_OCU_EXCLUSIVE_AREA_23[u32CoreId] = OsIf_Trusted_Call_Return(Ocu_schm_read_msr);
  968. #else
  969. msr_OCU_EXCLUSIVE_AREA_23[u32CoreId] = Ocu_schm_read_msr(); /*read MSR (to store interrupts state)*/
  970. #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
  971. if (ISR_ON(msr_OCU_EXCLUSIVE_AREA_23[u32CoreId])) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
  972. {
  973. OsIf_SuspendAllInterrupts();
  974. #ifdef _ARM_DS5_C_S32K1XX_
  975. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  976. #endif
  977. }
  978. }
  979. reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId]++;
  980. }
  981. void SchM_Exit_Ocu_OCU_EXCLUSIVE_AREA_23(void)
  982. {
  983. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  984. reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId]--;
  985. if ((ISR_ON(msr_OCU_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
  986. {
  987. OsIf_ResumeAllInterrupts();
  988. #ifdef _ARM_DS5_C_S32K1XX_
  989. ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
  990. #endif
  991. }
  992. }
  993. #ifdef MCAL_TESTING_ENVIRONMENT
  994. /**
  995. @brief This function checks that all entered exclusive areas were also exited.
  996. @details This function checks that all entered exclusive areas were also exited. The check
  997. is done by verifying that all reentry_guard_* static variables are back to the
  998. zero value.
  999. @param[in] void No input parameters
  1000. @return void This function does not return a value. Test asserts are used instead.
  1001. @pre None
  1002. @post None
  1003. @remarks Covers
  1004. @remarks Implements
  1005. */
  1006. void SchM_Check_ocu(void)
  1007. {
  1008. uint32 u32CoreId = (uint32)OsIf_GetCoreID();
  1009. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId]);
  1010. reentry_guard_OCU_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_00 for the next test in the suite*/
  1011. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId]);
  1012. reentry_guard_OCU_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_01 for the next test in the suite*/
  1013. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId]);
  1014. reentry_guard_OCU_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_02 for the next test in the suite*/
  1015. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId]);
  1016. reentry_guard_OCU_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_03 for the next test in the suite*/
  1017. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId]);
  1018. reentry_guard_OCU_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_04 for the next test in the suite*/
  1019. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId]);
  1020. reentry_guard_OCU_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_05 for the next test in the suite*/
  1021. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId]);
  1022. reentry_guard_OCU_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_06 for the next test in the suite*/
  1023. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId]);
  1024. reentry_guard_OCU_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_07 for the next test in the suite*/
  1025. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId]);
  1026. reentry_guard_OCU_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_10 for the next test in the suite*/
  1027. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId]);
  1028. reentry_guard_OCU_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_11 for the next test in the suite*/
  1029. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId]);
  1030. reentry_guard_OCU_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_12 for the next test in the suite*/
  1031. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId]);
  1032. reentry_guard_OCU_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_13 for the next test in the suite*/
  1033. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId]);
  1034. reentry_guard_OCU_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_14 for the next test in the suite*/
  1035. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId]);
  1036. reentry_guard_OCU_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_15 for the next test in the suite*/
  1037. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId]);
  1038. reentry_guard_OCU_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_16 for the next test in the suite*/
  1039. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId]);
  1040. reentry_guard_OCU_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_20 for the next test in the suite*/
  1041. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId]);
  1042. reentry_guard_OCU_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_21 for the next test in the suite*/
  1043. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId]);
  1044. reentry_guard_OCU_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_22 for the next test in the suite*/
  1045. EU_ASSERT(0UL == reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId]);
  1046. reentry_guard_OCU_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_OCU_EXCLUSIVE_AREA_23 for the next test in the suite*/
  1047. }
  1048. #endif /*MCAL_TESTING_ENVIRONMENT*/
  1049. #define RTE_STOP_SEC_CODE
  1050. #include "Rte_MemMap.h"
  1051. #ifdef __cplusplus
  1052. }
  1053. #endif
  1054. /** @} */