Power_Ip_CortexM4.c 8.0 KB

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  1. /*==================================================================================================
  2. * Project : RTD AUTOSAR 4.4
  3. * Platform : CORTEXM
  4. * Peripheral :
  5. * Dependencies : none
  6. *
  7. * Autosar Version : 4.4.0
  8. * Autosar Revision : ASR_REL_4_4_REV_0000
  9. * Autosar Conf.Variant :
  10. * SW Version : 1.0.0
  11. * Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
  12. *
  13. * (c) Copyright 2020-2021 NXP Semiconductors
  14. * All Rights Reserved.
  15. *
  16. * NXP Confidential. This software is owned or controlled by NXP and may only be
  17. * used strictly in accordance with the applicable license terms. By expressly
  18. * accepting such terms or by downloading, installing, activating and/or otherwise
  19. * using the software, you are agreeing that you have read, and that you agree to
  20. * comply with and are bound by, such license terms. If you do not agree to be
  21. * bound by the applicable license terms, then you may not retain, install,
  22. * activate or otherwise use the software.
  23. ==================================================================================================*/
  24. /**
  25. * @file Power_Ip_CotexM4.c
  26. * @version 1.0.0
  27. *
  28. * @brief POWER driver implementations.
  29. * @details POWER driver implementations.
  30. *
  31. * @addtogroup POWER_DRIVER Power Ip Driver
  32. * @{
  33. */
  34. #ifdef __cplusplus
  35. extern "C"{
  36. #endif
  37. /*==================================================================================================
  38. * INCLUDE FILES
  39. * 1) system and project includes
  40. * 2) needed interfaces from external units
  41. * 3) internal and external interfaces from this unit
  42. ==================================================================================================*/
  43. #include "Power_Ip_CortexM4.h"
  44. /*==================================================================================================
  45. SOURCE FILE VERSION INFORMATION
  46. ==================================================================================================*/
  47. #define POWER_IP_CORTEXM4_VENDOR_ID_C 43
  48. #define POWER_IP_CORTEXM4_AR_RELEASE_MAJOR_VERSION_C 4
  49. #define POWER_IP_CORTEXM4_AR_RELEASE_MINOR_VERSION_C 4
  50. #define POWER_IP_CORTEXM4_AR_RELEASE_REVISION_VERSION_C 0
  51. #define POWER_IP_CORTEXM4_SW_MAJOR_VERSION_C 1
  52. #define POWER_IP_CORTEXM4_SW_MINOR_VERSION_C 0
  53. #define POWER_IP_CORTEXM4_SW_PATCH_VERSION_C 0
  54. /*==================================================================================================
  55. * FILE VERSION CHECKS
  56. ==================================================================================================*/
  57. /* Check if Power_Ip_CortexM4.c file and Power_Ip_CortexM4.h file are of the same vendor */
  58. #if (POWER_IP_CORTEXM4_VENDOR_ID_C != POWER_IP_CORTEXM4_VENDOR_ID)
  59. #error "Power_Ip_CortexM4.c and Power_Ip_CortexM4.h have different vendor ids"
  60. #endif
  61. /* Check if Power_Ip_CortexM4.c file and Power_Ip_CortexM4.h file are of the same Autosar version */
  62. #if ((POWER_IP_CORTEXM4_AR_RELEASE_MAJOR_VERSION_C != POWER_IP_CORTEXM4_AR_RELEASE_MAJOR_VERSION) || \
  63. (POWER_IP_CORTEXM4_AR_RELEASE_MINOR_VERSION_C != POWER_IP_CORTEXM4_AR_RELEASE_MINOR_VERSION) || \
  64. (POWER_IP_CORTEXM4_AR_RELEASE_REVISION_VERSION_C != POWER_IP_CORTEXM4_AR_RELEASE_REVISION_VERSION) \
  65. )
  66. #error "AutoSar Version Numbers of Power_Ip_CortexM4.c and Power_Ip_CortexM4.h are different"
  67. #endif
  68. /* Check if Power_Ip_CortexM4.c file and Power_Ip_CortexM4.h file are of the same Software version */
  69. #if ((POWER_IP_CORTEXM4_SW_MAJOR_VERSION_C != POWER_IP_CORTEXM4_SW_MAJOR_VERSION) || \
  70. (POWER_IP_CORTEXM4_SW_MINOR_VERSION_C != POWER_IP_CORTEXM4_SW_MINOR_VERSION) || \
  71. (POWER_IP_CORTEXM4_SW_PATCH_VERSION_C != POWER_IP_CORTEXM4_SW_PATCH_VERSION) \
  72. )
  73. #error "Software Version Numbers of Power_Ip_CortexM4.c and Power_Ip_CortexM4.h are different"
  74. #endif
  75. /*==================================================================================================
  76. * GLOBAL VARIABLE DECLARATIONS
  77. ==================================================================================================*/
  78. #define MCU_START_SEC_VAR_INIT_UNSPECIFIED
  79. #include "Mcu_MemMap.h"
  80. static Power_Ip_CM4_Type * pCM4 = (Power_Ip_CM4_Type *)CM4_AIRCR_BASEADDR;
  81. #define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
  82. #include "Mcu_MemMap.h"
  83. /*==================================================================================================
  84. * ENUMS
  85. ==================================================================================================*/
  86. /*==================================================================================================
  87. * CONSTANTS
  88. ==================================================================================================*/
  89. /*==================================================================================================
  90. * DEFINES AND MACROS
  91. ==================================================================================================*/
  92. /*==================================================================================================
  93. * STRUCTURES AND OTHER TYPEDEFS
  94. ==================================================================================================*/
  95. /*==================================================================================================
  96. * LOCAL FUNCTION
  97. ==================================================================================================*/
  98. #define MCU_START_SEC_CODE
  99. #include "Mcu_MemMap.h"
  100. #if (MCU_PERFORM_RESET_API == STD_ON)
  101. /**
  102. * @brief The function initiates a system reset request to reset the SoC.
  103. * @details The function initiates a system reset request to reset the SoC
  104. *
  105. * @param[in] none
  106. *
  107. * @return void
  108. *
  109. */
  110. void Power_Ip_CM4_SystemReset(void)
  111. {
  112. uint32 u32TmpValue;
  113. u32TmpValue = (pCM4->AIRCR) & (uint32)CM4_AIRCR_PRIGROUP_MASK;
  114. u32TmpValue |= (uint32)CM4_AIRCR_SYSRESETREQ_MASK;
  115. u32TmpValue |= (uint32)CM4_AIRCR_VECTKEY(0x5FAU);
  116. ASM_KEYWORD(" dsb"); /* All memory accesses have to be completed before reset */
  117. pCM4->AIRCR = u32TmpValue;
  118. ASM_KEYWORD(" dsb"); /* All memory accesses have to be completed */
  119. }
  120. #endif
  121. #ifdef POWER_IP_SLEEPONEXIT_SUPPORT
  122. #if (POWER_IP_SLEEPONEXIT_SUPPORT == STD_ON)
  123. /**
  124. * @brief The function disable SLEEPONEXIT bit.
  125. * @details The function disable SLEEPONEXIT bit.
  126. *
  127. * @param[in] none
  128. *
  129. * @return void
  130. */
  131. void Power_Ip_CM4_DisableSleepOnExit(void)
  132. {
  133. uint32 tempValue = 0;
  134. tempValue = pCM4->SCR;
  135. tempValue &= ~(CM4_SCR_SLEEPONEXIT_MASK32);
  136. pCM4->SCR = tempValue;
  137. }
  138. #endif
  139. #endif
  140. #ifdef POWER_IP_SLEEPONEXIT_SUPPORT
  141. #if (POWER_IP_SLEEPONEXIT_SUPPORT == STD_ON)
  142. /**
  143. * @brief The function enable SLEEPONEXIT bit.
  144. * @details The function enable SLEEPONEXIT bit.
  145. *
  146. * @param[in] none
  147. *
  148. * @return void
  149. */
  150. void Power_Ip_CM4_EnableSleepOnExit(void)
  151. {
  152. uint32 tempValue = 0;
  153. tempValue = pCM4->SCR;
  154. tempValue |= (CM4_SCR_SLEEPONEXIT_MASK32);
  155. pCM4->SCR = tempValue;
  156. }
  157. #endif
  158. #endif
  159. /**
  160. * @brief The function enables DEEPSLEEP.
  161. * @details The function enables DEEPSLEEP.
  162. *
  163. * @param[in] none
  164. *
  165. * @return void
  166. */
  167. void Power_Ip_CM4_EnableDeepSleep(void)
  168. {
  169. uint32 tempValue = 0;
  170. tempValue = pCM4->SCR;
  171. tempValue |= CM4_SCR_SLEEPDEEP_MASK32;
  172. pCM4->SCR = tempValue;
  173. }
  174. /**
  175. * @brief The function disables DEEPSLEEP.
  176. * @details The function disables DEEPSLEEP.
  177. *
  178. * @param[in] none
  179. *
  180. * @return void
  181. */
  182. void Power_Ip_CM4_DisableDeepSleep(void)
  183. {
  184. uint32 tempValue = 0;
  185. tempValue = pCM4->SCR;
  186. tempValue &= ~(CM4_SCR_SLEEPDEEP_MASK32);
  187. pCM4->SCR = tempValue;
  188. }
  189. #define MCU_STOP_SEC_CODE
  190. #include "Mcu_MemMap.h"
  191. #ifdef __cplusplus
  192. }
  193. #endif
  194. /** @} */