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- #ifndef QUADSPI_HW_ACCESS_H
- #define QUADSPI_HW_ACCESS_H
- #ifdef __cplusplus
- extern "C"{
- #endif
- #include "Qspi_Ip.h"
- #include "Qspi_Ip_Common.h"
- #define QSPI_IP_HW_ACCESS_VENDOR_ID_H 43
- #define QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H 4
- #define QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H 4
- #define QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H 0
- #define QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H 1
- #define QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H 0
- #define QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H 0
- #if (QSPI_IP_HW_ACCESS_VENDOR_ID_H != QSPI_IP_VENDOR_ID_H)
- #error "Qspi_Ip_HwAccess.h and Qspi_Ip.h have different vendor ids"
- #endif
- #if ((QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H != QSPI_IP_AR_RELEASE_MAJOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H != QSPI_IP_AR_RELEASE_MINOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_AR_RELEASE_REVISION_VERSION_H) \
- )
- #error "AutoSar Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip.h are different"
- #endif
- #if ((QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H != QSPI_IP_SW_MAJOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H != QSPI_IP_SW_MINOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H != QSPI_IP_SW_PATCH_VERSION_H) \
- )
- #error "Software Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip.h are different"
- #endif
- #if (QSPI_IP_HW_ACCESS_VENDOR_ID_H != QSPI_IP_COMMON_VENDOR_ID_H)
- #error "Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h have different vendor ids"
- #endif
- #if ((QSPI_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_H != QSPI_IP_COMMON_AR_RELEASE_MAJOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_H != QSPI_IP_COMMON_AR_RELEASE_MINOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_H != QSPI_IP_COMMON_AR_RELEASE_REVISION_VERSION_H) \
- )
- #error "AutoSar Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h are different"
- #endif
- #if ((QSPI_IP_HW_ACCESS_SW_MAJOR_VERSION_H != QSPI_IP_COMMON_SW_MAJOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_SW_MINOR_VERSION_H != QSPI_IP_COMMON_SW_MINOR_VERSION_H) || \
- (QSPI_IP_HW_ACCESS_SW_PATCH_VERSION_H != QSPI_IP_COMMON_SW_PATCH_VERSION_H) \
- )
- #error "Software Version Numbers of Qspi_Ip_HwAccess.h and Qspi_Ip_Common.h are different"
- #endif
- #if (QSPI_IP_MEM_INSTANCE_COUNT > 0)
- #define QSPI_IP_RX_READOUT_IP 1U /* RX Buffer content is read using the AHB Bus registers QSPI_ARDBn */
- static inline void Qspi_Ip_ResetAllRegisters(QuadSPI_Type *baseAddr)
- {
- uint8 cnt;
-
- baseAddr->MCR = (uint32)0x000F400CUL;
-
- baseAddr->IPCR = (uint32)0x00000000UL;
-
- baseAddr->FLSHCR = (uint32)0x00000303UL;
-
- baseAddr->BUF0CR = (uint32)0x00000003UL;
-
- baseAddr->BUF1CR = (uint32)0x00000002UL;
-
- baseAddr->BUF2CR = (uint32)0x00000001UL;
-
- baseAddr->BUF3CR = (uint32)0x80000000UL;
-
- baseAddr->BFGENCR = (uint32)0x00000000UL;
-
- baseAddr->SOCCR = (uint32)0x00000000UL;
-
- baseAddr->BUF0IND = (uint32)0x00000000UL;
-
- baseAddr->BUF1IND = (uint32)0x00000000UL;
-
- baseAddr->BUF2IND = (uint32)0x00000000UL;
-
- baseAddr->SFAR = (uint32)0x00000000UL;
-
- baseAddr->SFACR = (uint32)0x00000000UL;
-
- baseAddr->SMPR = (uint32)0x00000000UL;
-
- baseAddr->RBCT = (uint32)0x00000000UL;
-
- baseAddr->TBDR = (uint32)0x00000000UL;
-
- baseAddr->TBCT = (uint32)0x00000000UL;
-
- baseAddr->FR = (uint32)0x0C83F0C1UL;
-
- baseAddr->RSER = (uint32)0x00000000UL;
-
- baseAddr->SPTRCLR = (uint32)0x00000000UL;
-
- baseAddr->SFA1AD = (uint32)0x6C000000UL;
-
- baseAddr->SFA2AD = (uint32)0x6C000000UL;
-
- baseAddr->SFB1AD = (uint32)0x70000000UL;
-
- baseAddr->SFB2AD = (uint32)0x70000000UL;
-
- baseAddr->LUTKEY = (uint32)0x5AF05AF0UL;
-
- baseAddr->LCKCR = (uint32)0x00000002UL;
-
- baseAddr->LUT[0] = (uint32)0x08180403UL;
-
- baseAddr->LUT[1] = (uint32)0x24001C08UL;
- for (cnt = 2U; cnt < QuadSPI_LUT_COUNT; cnt++)
- {
- baseAddr->LUT[cnt] = (uint32)0x00000000UL;
- }
- }
- static inline void Qspi_Ip_IpTrigger(QuadSPI_Type *baseAddr,
- uint8 seqID,
- uint16 dataSize
- )
- {
- baseAddr->IPCR = QuadSPI_IPCR_SEQID(seqID)
- | QuadSPI_IPCR_IDATSZ(dataSize);
- }
- static inline void Qspi_Ip_ClearRxBuf(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR |= QuadSPI_MCR_CLR_RXF_MASK;
- }
- static inline void Qspi_Ip_ClearTxBuf(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR |= QuadSPI_MCR_CLR_TXF_MASK;
- }
- static inline boolean Qspi_Ip_GetClrTxStatus(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->MCR;
- regValue = (regValue & QuadSPI_MCR_CLR_TXF_MASK) >> QuadSPI_MCR_CLR_TXF_SHIFT;
- return (0U == regValue)? TRUE : FALSE;
- }
- #ifdef QuadSPI_SPTRCLR_ABRT_CLR_MASK
- static inline void Qspi_Ip_ClearAhbBuf(QuadSPI_Type *baseAddr)
- {
- baseAddr->SPTRCLR |= QuadSPI_SPTRCLR_ABRT_CLR_MASK;
- }
- static inline boolean Qspi_Ip_GetClrAhbStatus(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->SPTRCLR;
- regValue = (regValue & QuadSPI_SPTRCLR_ABRT_CLR_MASK) >> QuadSPI_SPTRCLR_ABRT_CLR_SHIFT;
- return (0U == regValue)? TRUE : FALSE;
- }
- #endif
- static inline void Qspi_Ip_Enable(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR &= ~QuadSPI_MCR_MDIS_MASK;
- }
- static inline void Qspi_Ip_Disable(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR |= QuadSPI_MCR_MDIS_MASK;
- }
- static inline void QSPI_DDR_Enable(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR |= QuadSPI_MCR_DDR_EN_MASK;
- }
- static inline void QSPI_DDR_Disable(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
- }
- static inline void QSPI_DQS_LatEnable(QuadSPI_Type *baseAddr, boolean enable)
- {
- uint32 regValue = (uint32)baseAddr->MCR;
- regValue &= (uint32)(~((uint32)QuadSPI_MCR_DQS_LAT_EN_MASK));
- regValue |= QuadSPI_MCR_DQS_LAT_EN(enable? 1U : 0U);
- baseAddr->MCR = (uint32)regValue;
- }
- static inline void QSPI_DQS_Enable(QuadSPI_Type *baseAddr)
- {
- (void)baseAddr;
- #ifdef QuadSPI_MCR_DQS_EN_MASK
- baseAddr->MCR |= QuadSPI_MCR_DQS_EN_MASK;
- #endif
- }
- static inline void QSPI_DQS_Disable(QuadSPI_Type *baseAddr)
- {
- (void)baseAddr;
- #ifdef QuadSPI_MCR_DQS_EN_MASK
- baseAddr->MCR &= ~QuadSPI_MCR_DQS_EN_MASK;
- #endif
- }
- static inline void Qspi_Ip_SwResetOn(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR |= QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK;
- }
- static inline void Qspi_Ip_SwResetOff(QuadSPI_Type *baseAddr)
- {
- baseAddr->MCR &= ~(QuadSPI_MCR_SWRSTHD_MASK | QuadSPI_MCR_SWRSTSD_MASK);
- }
- static inline void Qspi_Ip_SetIdleLineValues(QuadSPI_Type *baseAddr,
- uint8 iofa2IdleValue,
- uint8 iofa3IdleValue,
- uint8 iofb2IdleValue,
- uint8 iofb3IdleValue
- )
- {
-
- uint32 regValue = (uint32)baseAddr->MCR;
-
- regValue &= (uint32)(~(QuadSPI_MCR_ISD2FA_MASK | QuadSPI_MCR_ISD3FA_MASK | QuadSPI_MCR_ISD2FB_MASK | QuadSPI_MCR_ISD3FB_MASK));
- regValue |= (QuadSPI_MCR_ISD2FA(iofa2IdleValue) |
- QuadSPI_MCR_ISD3FA(iofa3IdleValue) |
- QuadSPI_MCR_ISD2FB(iofb2IdleValue) |
- QuadSPI_MCR_ISD3FB(iofb3IdleValue));
-
- baseAddr->MCR = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetMemMapSizeA(uint32 instance, QuadSPI_Type *baseAddr, uint32 sizeA1, uint32 sizeA2)
- {
- baseAddr->SFA1AD = Qspi_Ip_AhbAddress[instance] + sizeA1;
- baseAddr->SFA2AD = Qspi_Ip_AhbAddress[instance] + sizeA1 + sizeA2;
- }
- static inline void Qspi_Ip_SetMemMapSizeB(QuadSPI_Type *baseAddr, uint32 sizeB1, uint32 sizeB2)
- {
-
- uint32 regValue = (uint32)baseAddr->SFA2AD;
- baseAddr->SFB1AD = regValue + sizeB1;
- baseAddr->SFB2AD = regValue + sizeB1 + sizeB2;
- }
- static inline void Qspi_Ip_SetCsHoldTime(QuadSPI_Type *baseAddr, uint8 cycles)
- {
- uint32 regValue = (uint32)baseAddr->FLSHCR;
- regValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSH_MASK));
- regValue |= QuadSPI_FLSHCR_TCSH(cycles);
- baseAddr->FLSHCR = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetCsSetupTime(QuadSPI_Type *baseAddr, uint8 cycles)
- {
- uint32 regValue = (uint32)baseAddr->FLSHCR;
- regValue &= (uint32)(~((uint32)QuadSPI_FLSHCR_TCSS_MASK));
- regValue |= QuadSPI_FLSHCR_TCSS(cycles);
- baseAddr->FLSHCR = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetDataInHoldTime(QuadSPI_Type *baseAddr, Qspi_Ip_FlashDataAlignType enable)
- {
- uint32 regValue = (uint32)baseAddr->FLSHCR;
- regValue &= (uint32)(~(QuadSPI_FLSHCR_TDH_MASK));
- regValue |= QuadSPI_FLSHCR_TDH(enable);
- baseAddr->FLSHCR = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetAhbBuf0(QuadSPI_Type *baseAddr,
- uint16 size,
- uint8 master
- )
- {
- baseAddr->BUF0CR = QuadSPI_BUF0CR_ADATSZ((uint32)size >> 3U)
- | QuadSPI_BUF0CR_MSTRID(master);
- }
- static inline void Qspi_Ip_SetAhbBuf1(QuadSPI_Type *baseAddr,
- uint16 size,
- uint8 master
- )
- {
- baseAddr->BUF1CR = QuadSPI_BUF1CR_ADATSZ((uint32)size >> 3U)
- | QuadSPI_BUF1CR_MSTRID(master);
- }
- static inline void Qspi_Ip_SetAhbBuf2(QuadSPI_Type *baseAddr,
- uint16 size,
- uint8 master
- )
- {
- baseAddr->BUF2CR = QuadSPI_BUF2CR_ADATSZ((uint32)size >> 3U)
- | QuadSPI_BUF2CR_MSTRID(master);
- }
- static inline void Qspi_Ip_SetAhbBuf3(QuadSPI_Type *baseAddr,
- uint16 size,
- uint8 master,
- boolean allMasters
- )
- {
- baseAddr->BUF3CR = QuadSPI_BUF3CR_ADATSZ((uint32)size >> 3U)
- | QuadSPI_BUF3CR_MSTRID(master)
- | QuadSPI_BUF3CR_ALLMST(allMasters? 1U : 0U);
- }
- static inline void Qspi_Ip_SetAhbBuf0Ind(QuadSPI_Type *baseAddr,
- uint32 index
- )
- {
- baseAddr->BUF0IND = index;
- }
- static inline void Qspi_Ip_SetAhbBuf1Ind(QuadSPI_Type *baseAddr,
- uint32 index
- )
- {
- baseAddr->BUF1IND = index;
- }
- static inline void Qspi_Ip_SetAhbBuf2Ind(QuadSPI_Type *baseAddr,
- uint32 index
- )
- {
- baseAddr->BUF2IND = index;
- }
- static inline void Qspi_Ip_SetIpAddr(QuadSPI_Type *baseAddr,
- uint32 addr
- )
- {
- baseAddr->SFAR = addr;
- }
- static inline void Qspi_Ip_SetAddrOptions(QuadSPI_Type *baseAddr,
- uint32 columnAddr,
- boolean wordAdressable
- )
- {
- baseAddr->SFACR = QuadSPI_SFACR_CAS(columnAddr)
- | QuadSPI_SFACR_WA(wordAdressable? 1U : 0U);
- }
- static inline void Qspi_Ip_SetRxCfg(QuadSPI_Type *baseAddr,
- Qspi_Ip_SampleDelayType delay,
- Qspi_Ip_SamplePhaseType clockPhase
- )
- {
- baseAddr->SMPR = QuadSPI_SMPR_FSPHS(clockPhase)
- | QuadSPI_SMPR_FSDLY(delay);
- }
- static inline boolean Qspi_Ip_GetBusyStatus(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->SR;
- regValue = (regValue & QuadSPI_SR_BUSY_MASK) >> QuadSPI_SR_BUSY_SHIFT;
- return (regValue != 0U)? TRUE : FALSE;
- }
- static inline uint32 Qspi_Ip_GetRxBufFill(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->RBSR;
- regValue = (regValue & QuadSPI_RBSR_RDBFL_MASK) >> QuadSPI_RBSR_RDBFL_SHIFT;
- return regValue;
- }
- static inline boolean Qspi_Ip_GetRxDataEvent(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->SR;
- regValue = (regValue & QuadSPI_SR_RXWE_MASK) >> QuadSPI_SR_RXWE_SHIFT;
- return (regValue != 0U)? TRUE : FALSE;
- }
- static inline uint32 Qspi_Ip_GetTxBufFill(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->TBSR;
- regValue = (regValue & QuadSPI_TBSR_TRBFL_MASK) >> QuadSPI_TBSR_TRBFL_SHIFT;
- return regValue;
- }
- static inline boolean Qspi_Ip_GetTxWatermarkAvailable(const QuadSPI_Type *baseAddr)
- {
- uint32 regValue = (uint32)baseAddr->SR;
- regValue = (regValue & QuadSPI_SR_TXWA_MASK) >> QuadSPI_SR_TXWA_SHIFT;
- return (regValue != 0U)? TRUE : FALSE;
- }
- static inline void Qspi_Ip_WriteTxData(QuadSPI_Type *baseAddr, uint32 data)
- {
- baseAddr->TBDR = data;
- }
- static inline uint32 Qspi_Ip_GetTxDataAddr(const QuadSPI_Type *baseAddr)
- {
- return (uint32)&(baseAddr->TBDR);
- }
- static inline uint32 Qspi_Ip_GetRxDataAddr(const QuadSPI_Type *baseAddr)
- {
- return (uint32)&(baseAddr->RBDR[0U]);
- }
- static inline void Qspi_Ip_EnableTxDmaReq(QuadSPI_Type *baseAddr)
- {
- baseAddr->RSER |= QuadSPI_RSER_TBFDE_MASK;
- }
- static inline void Qspi_Ip_EnableRxDmaReq(QuadSPI_Type *baseAddr)
- {
- baseAddr->RSER |= QuadSPI_RSER_RBDDE_MASK;
- }
- static inline void Qspi_Ip_DisableDmaReq(QuadSPI_Type *baseAddr)
- {
- baseAddr->RSER &= ~(QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK);
- }
- static inline void Qspi_Ip_RxPop(QuadSPI_Type *baseAddr)
- {
- baseAddr->FR = QuadSPI_FR_RBDF_MASK;
- }
- static inline void Qspi_Ip_SetRxWatermark(QuadSPI_Type *baseAddr,
- uint8 watermark
- )
- {
- uint32 regValue = (uint32)baseAddr->RBCT;
- regValue &= (uint32)(~((uint32)QuadSPI_RBCT_WMRK_MASK));
- regValue |= QuadSPI_RBCT_WMRK((uint32)watermark - 1U);
- baseAddr->RBCT = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetRxBufReadout(QuadSPI_Type *baseAddr,
- uint8 readout
- )
- {
- uint32 regValue = (uint32)baseAddr->RBCT;
- regValue &= (uint32)(~((uint32)QuadSPI_RBCT_RXBRD_MASK));
- regValue |= QuadSPI_RBCT_RXBRD(readout);
- baseAddr->RBCT = (uint32)regValue;
- }
- static inline void Qspi_Ip_SetTxWatermark(QuadSPI_Type *baseAddr,
- uint8 watermark
- )
- {
- uint32 regValue = (uint32)baseAddr->TBCT;
- regValue &= (uint32)(~((uint32)QuadSPI_TBCT_WMRK_MASK));
- regValue |= QuadSPI_TBCT_WMRK(watermark);
- baseAddr->TBCT = (uint32)regValue;
- }
- static inline void Qspi_Ip_EnableInt(QuadSPI_Type *baseAddr,
- uint32 mask
- )
- {
- baseAddr->RSER |= mask;
- }
- static inline void Qspi_Ip_DisableInt(QuadSPI_Type *baseAddr,
- uint32 mask
- )
- {
- baseAddr->RSER &= ~mask;
- }
- static inline void Qspi_Ip_ClearIntFlag(QuadSPI_Type *baseAddr,
- uint32 mask
- )
- {
- baseAddr->FR = mask;
- }
- #ifdef QuadSPI_MCR_SCLKCFG_MASK
- static inline void Qspi_Ip_SetClockOptions(QuadSPI_Type *baseAddr, uint8 option)
- {
- uint32 regValue = (uint32)baseAddr->MCR;
- regValue &= (uint32)(~QuadSPI_MCR_SCLKCFG_MASK);
- regValue |= QuadSPI_MCR_SCLKCFG(option);
- baseAddr->MCR = (uint32)regValue;
- }
- #endif
- #ifdef QuadSPI_SOCCR_SOCCFG_MASK
- static inline void Qspi_Ip_SetChipOptions(QuadSPI_Type *baseAddr, uint32 option)
- {
- baseAddr->SOCCR = option;
- }
- #endif
- #endif /* (QSPI_IP_MEM_INSTANCE_COUNT > 0) */
- #ifdef __cplusplus
- }
- #endif
- #endif /* QUADSPI_HW_ACCESS_H */
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