4G/code/BCU/BCUModel/DAM.h

#ifndef RTW_HEADER_DAM_h_
#define RTW_HEADER_DAM_h_
#ifndef DAM_COMMON_INCLUDES_
#define DAM_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif

#include "DAM_types.h"

#include "BCUCal.h"
#include "BCUDisp.h"

#ifndef DAM_MDLREF_HIDE_CHILD_

typedef struct {
  real32_T Gain;
  real32_T Gain1;
  real32_T Gain1_n;
  real32_T Gain2;
  real32_T Gain3;
  real32_T Gain4;
  real32_T Gain_m;
  real32_T Gain1_b;
  real32_T Product2;
  real32_T Product3;
  real32_T Product4;
  real32_T Product5;
  real32_T Merge;
  real32_T Merge1;
  real32_T Merge11;
  real32_T Merge12;
  real32_T Merge2;
  real32_T Merge3;
  real32_T Merge4;
  real32_T Merge5;
  real32_T Merge6;
  real32_T Merge7;
  uint16_T Merge13;
  uint16_T Merge8;
  uint16_T Merge9;
  chgCnctObj DataTypeConversion;
} B_DAM_c_T;

#endif

#ifndef DAM_MDLREF_HIDE_CHILD_

typedef struct {
  real32_T UnitDelay_DSTATE;
  real32_T UnitDelay1_DSTATE;
  real32_T UnitDelay4_DSTATE;
  real32_T UnitDelay5_DSTATE;
  real32_T UnitDelay2_DSTATE;
  real32_T UnitDelay3_DSTATE;
  real32_T UnitDelay6_DSTATE;
  real32_T UnitDelay7_DSTATE;
  real32_T UnitDelay_DSTATE_h;
  real32_T UnitDelay1_DSTATE_c;
  real32_T UnitDelay1_DSTATE_o;
  real32_T UnitDelay4_DSTATE_g;
  real32_T UnitDelay7_DSTATE_l;
  real32_T UnitDelay2_DSTATE_e;
  real32_T UnitDelay_DSTATE_d;
  real32_T UnitDelay1_DSTATE_p;
  uint8_T UnitDelay1_DSTATE_k;
  boolean_T UnitDelay_DSTATE_a;
  chrgSt UnitDelay_DSTATE_ac;
  int8_T If_ActiveSubsystem;
} DW_DAM_f_T;

#endif

#ifndef DAM_MDLREF_HIDE_CHILD_

struct tag_RTM_DAM_T {
  const char_T **errorStatus;
};

#endif

#ifndef DAM_MDLREF_HIDE_CHILD_

typedef struct {
  RT_MODEL_DAM_T rtm;
} MdlrefDW_DAM_T;

#endif

extern void DAM_Init(void);
extern void DAM_Disable(void);
extern void DAM(void);
extern void DAM_initialize(const char_T **rt_errorStatus);

#ifndef DAM_MDLREF_HIDE_CHILD_

extern MdlrefDW_DAM_T DAM_MdlrefDW;

#endif

#ifndef DAM_MDLREF_HIDE_CHILD_

extern B_DAM_c_T DAM_B;
extern DW_DAM_f_T DAM_DW;

#endif
#endif