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- #ifdef __cplusplus
- extern "C"{
- #endif
- #include "Std_Types.h"
- #include "Mcal.h"
- #include "OsIf.h"
- #include "SchM_Dio.h"
- #ifdef MCAL_TESTING_ENVIRONMENT
- #include "EUnit.h"
- #endif
- #define SCHM_DIO_AR_RELEASE_MAJOR_VERSION_C 4
- #define SCHM_DIO_AR_RELEASE_MINOR_VERSION_C 4
- #define SCHM_DIO_AR_RELEASE_REVISION_VERSION_C 0
- #define SCHM_DIO_SW_MAJOR_VERSION_C 1
- #define SCHM_DIO_SW_MINOR_VERSION_C 0
- #define SCHM_DIO_SW_PATCH_VERSION_C 0
- #ifdef MCAL_PLATFORM_ARM
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- #define ISR_STATE_MASK ((uint32)0x00000002UL)
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- #define ISR_STATE_MASK ((uint32)0x00000080UL)
- #else
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- #define ISR_STATE_MASK ((uint32)0x000000FFUL)
- #else
- #define ISR_STATE_MASK ((uint32)0x00000001UL)
- #endif
- #endif
- #else
- #ifdef MCAL_PLATFORM_S12
- #define ISR_STATE_MASK ((uint32)0x00000010UL)
- #else
- #define ISR_STATE_MASK ((uint32)0x00008000UL)
- #endif
- #endif
- #ifdef MCAL_PLATFORM_ARM
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)3)
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
- #else
- #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
- #endif
- #else
- #ifdef MCAL_PLATFORM_S12
- #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
- #else
- #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
- #endif
- #endif
- #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
- #include "Rte_MemMap.h"
- static volatile uint32 msr_DIO_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
- static volatile uint32 reentry_guard_DIO_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
- static volatile uint32 msr_DIO_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
- static volatile uint32 reentry_guard_DIO_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
- #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
- #include "Rte_MemMap.h"
- #ifndef _COSMIC_C_S32K1XX_
- uint32 Dio_schm_read_msr(void);
- #endif
- #define RTE_START_SEC_CODE
- #include "Rte_MemMap.h"
- #if (defined(_GREENHILLS_C_S32K1XX_) || defined(_CODEWARRIOR_C_S32K1XX_))
- #ifdef MCAL_PLATFORM_ARM
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- mrs x0, S3_3_c4_c2_1
- }
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- mrs r0, CPSR
- }
- #else
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- mrs r0, BASEPRI
- #else
- mrs r0, PRIMASK
- #endif
- }
- #endif
- #else
- #ifdef MCAL_PLATFORM_S12
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- tfr ccr, d6
- }
- #else
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- mfmsr r3
- }
- #endif
- #endif
- #endif
- #ifdef _DIABDATA_C_S32K1XX_
- #ifdef MCAL_PLATFORM_ARM
- uint32 Dio_schm_read_msr(void)
- {
- register uint32 reg_tmp;
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
- #else
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
- #else
- __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
- #endif
- #endif
- return (uint32)reg_tmp;
- }
- #else
- ASM_KEYWORD uint32 Dio_schm_read_msr(void)
- {
- mfmsr r3
- }
- #endif
- #endif
- #ifdef _COSMIC_C_S32K1XX_
- #ifdef MCAL_PLATFORM_S12
- #define Dio_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
- #else
- #define Dio_schm_read_msr() ASM_KEYWORD("mfmsr r3")
- #endif
- #endif
- #ifdef _HITECH_C_S32K1XX_
- uint32 Dio_schm_read_msr(void)
- {
- uint32 result;
- __asm volatile("mfmsr %0" : "=r" (result) :);
- return result;
- }
- #endif
-
- #ifdef _LINARO_C_S32K1XX_
- uint32 Dio_schm_read_msr(void)
- {
- register uint32 reg_tmp;
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
- #else
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
- #else
- __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
- #endif
- #endif
- return (uint32)reg_tmp;
- }
- #endif
- #ifdef _ARM_DS5_C_S32K1XX_
- uint32 Dio_schm_read_msr(void)
- {
- register uint32 reg_tmp;
- #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
- __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
- #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
- __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
- #else
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
- #else
- __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
- #endif
- #endif
- return (uint32)reg_tmp;
- }
- #endif
- #ifdef _IAR_C_S32K1XX_
- uint32 Dio_schm_read_msr(void)
- {
- register uint32 reg_tmp;
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
- #else
- __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
- #endif
- return (uint32)reg_tmp;
- }
- #endif
- #define RTE_STOP_SEC_CODE
- #include "Rte_MemMap.h"
- #define RTE_START_SEC_CODE
- #include "Rte_MemMap.h"
- void SchM_Enter_Dio_DIO_EXCLUSIVE_AREA_00(void)
- {
- uint32 u32CoreId = (uint32)OsIf_GetCoreID();
- if(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId])
- {
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- msr_DIO_EXCLUSIVE_AREA_00[u32CoreId] = OsIf_Trusted_Call_Return(Dio_schm_read_msr);
- #else
- msr_DIO_EXCLUSIVE_AREA_00[u32CoreId] = Dio_schm_read_msr();
- #endif
- if (ISR_ON(msr_DIO_EXCLUSIVE_AREA_00[u32CoreId]))
- {
- OsIf_SuspendAllInterrupts();
- #ifdef _ARM_DS5_C_S32K1XX_
- ASM_KEYWORD(" nop ");
- #endif
- }
- }
- reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId]++;
- }
- void SchM_Exit_Dio_DIO_EXCLUSIVE_AREA_00(void)
- {
- uint32 u32CoreId = (uint32)OsIf_GetCoreID();
- reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId]--;
- if ((ISR_ON(msr_DIO_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId]))
- {
- OsIf_ResumeAllInterrupts();
- #ifdef _ARM_DS5_C_S32K1XX_
- ASM_KEYWORD(" nop ");
- #endif
- }
- }
- void SchM_Enter_Dio_DIO_EXCLUSIVE_AREA_01(void)
- {
- uint32 u32CoreId = (uint32)OsIf_GetCoreID();
- if(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId])
- {
- #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
- msr_DIO_EXCLUSIVE_AREA_01[u32CoreId] = OsIf_Trusted_Call_Return(Dio_schm_read_msr);
- #else
- msr_DIO_EXCLUSIVE_AREA_01[u32CoreId] = Dio_schm_read_msr();
- #endif
- if (ISR_ON(msr_DIO_EXCLUSIVE_AREA_01[u32CoreId]))
- {
- OsIf_SuspendAllInterrupts();
- #ifdef _ARM_DS5_C_S32K1XX_
- ASM_KEYWORD(" nop ");
- #endif
- }
- }
- reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId]++;
- }
- void SchM_Exit_Dio_DIO_EXCLUSIVE_AREA_01(void)
- {
- uint32 u32CoreId = (uint32)OsIf_GetCoreID();
- reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId]--;
- if ((ISR_ON(msr_DIO_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId]))
- {
- OsIf_ResumeAllInterrupts();
- #ifdef _ARM_DS5_C_S32K1XX_
- ASM_KEYWORD(" nop ");
- #endif
- }
- }
- #ifdef MCAL_TESTING_ENVIRONMENT
- void SchM_Check_dio(void)
- {
- uint32 u32CoreId = (uint32)OsIf_GetCoreID();
- EU_ASSERT(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId]);
- reentry_guard_DIO_EXCLUSIVE_AREA_00[u32CoreId] = 0UL;
- EU_ASSERT(0UL == reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId]);
- reentry_guard_DIO_EXCLUSIVE_AREA_01[u32CoreId] = 0UL;
- }
- #endif
- #define RTE_STOP_SEC_CODE
- #include "Rte_MemMap.h"
- #ifdef __cplusplus
- }
- #endif
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