4G/S32K146_4G.mex

<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="S32K146" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_10 http://mcuxpresso.nxp.com/XSD/mex_configuration_10.xsd" uuid="4179bacd-df3b-49d1-b875-310026dec15f" version="10" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_10" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
   <common>
      <processor>S32K146</processor>
      <package>S32K146_LQFP144</package>
      <mcu_data>PlatformSDK_S32K1_2021_08</mcu_data>
      <cores selected="core0">
         <core name="Cortex-M4F" id="core0" description=""/>
      </cores>
      <description></description>
   </common>
   <preferences>
      <validate_boot_init_only>true</validate_boot_init_only>
      <generate_extended_information>false</generate_extended_information>
      <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
      <update_include_paths>true</update_include_paths>
   </preferences>
   <tools>
      <pins name="Pins" version="6.0" enabled="true" update_project_code="true">
         <pins_profile>
            <processor_version>0.0.0</processor_version>
         </pins_profile>
         <functions_list>
            <function name="BOARD_InitPins">
               <description>Configures pin routing and optionally pin electrical features.</description>
               <options>
                  <callFromInitBoot>true</callFromInitBoot>
                  <coreID>core0</coreID>
               </options>
               <dependencies/>
               <pins/>
            </function>
         </functions_list>
      </pins>
      <clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
         <generated_project_files>
            <file path="board/Clock_Ip_Cfg.c" update_enabled="true"/>
            <file path="board/Clock_Ip_Cfg.h" update_enabled="true"/>
            <file path="board/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
            <file path="board/Clock_Ip_PBcfg.c" update_enabled="true"/>
            <file path="board/Clock_Ip_PBcfg.h" update_enabled="true"/>
         </generated_project_files>
         <clocks_profile>
            <processor_version>0.0.0</processor_version>
         </clocks_profile>
         <clock_configurations>
            <clock_configuration name="BOARD_BootClockRUN">
               <description></description>
               <options/>
               <dependencies>
                  <dependency resourceType="PinSignal" resourceId="SOSC.EXTAL" description="&apos;External pin&apos; (Pins tool id: SOSC.EXTAL, Clocks tool id: SOSC.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
                     <feature name="routed" evaluation="">
                        <data>true</data>
                     </feature>
                     <feature name="direction" evaluation="">
                        <data>INPUT</data>
                     </feature>
                  </dependency>
                  <dependency resourceType="PinSignal" resourceId="SOSC.EXTAL" description="&apos;External pin&apos; (Pins tool id: SOSC.EXTAL, Clocks tool id: SOSC.EXTAL) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
                     <feature name="direction" evaluation="">
                        <data>INPUT</data>
                     </feature>
                  </dependency>
                  <dependency resourceType="PinSignal" resourceId=".rtc_clkin" description="&apos;RTC_CLKIN&apos; (Pins tool id: .rtc_clkin, Clocks tool id: RTC.RTC_CLKIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
                     <feature name="routed" evaluation="">
                        <data>true</data>
                     </feature>
                     <feature name="direction" evaluation="">
                        <data>INPUT</data>
                     </feature>
                  </dependency>
                  <dependency resourceType="PinSignal" resourceId=".rtc_clkin" description="&apos;RTC_CLKIN&apos; (Pins tool id: .rtc_clkin, Clocks tool id: RTC.RTC_CLKIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
                     <feature name="direction" evaluation="">
                        <data>INPUT</data>
                     </feature>
                  </dependency>
                  <dependency resourceType="SWComponent" resourceId="platform.driver.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
                     <feature name="enabled" evaluation="equal" configuration="core0">
                        <data>true</data>
                     </feature>
                  </dependency>
               </dependencies>
               <clock_sources>
                  <clock_source id="RTC.RTC_CLK_EXT_IN.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
                  <clock_source id="SOSC.SOSC.outFreq" value="8 MHz" locked="false" enabled="true"/>
               </clock_sources>
               <clock_outputs>
                  <clock_output id="ADC0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="ADC1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="BUS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="CLKOUT0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="CMP0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="CORE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="CRC0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="DMA0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="DMAMUX0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="EIM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="ERM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="EWM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FIRCDIV1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FIRCDIV2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FIRCOUT.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FLASH_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
                  <clock_output id="FLEXCAN0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FLEXCAN1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FLEXCAN2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTFC0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM3_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM4_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FTM5_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FlexIO0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="FlexIO_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPI2C0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPIT0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPO_128K_CLK.outFreq" value="128 kHz" locked="false" accuracy=""/>
                  <clock_output id="LPO_1K_CLK.outFreq" value="1 kHz" locked="false" accuracy=""/>
                  <clock_output id="LPO_32K_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
                  <clock_output id="LPO_CLK.outFreq" value="128 kHz" locked="false" accuracy=""/>
                  <clock_output id="LPSPI0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPSPI1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPSPI2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPTMR0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPUART0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPUART1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="LPUART2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="MPU0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="MSCM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PDB0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PDB1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PORTA_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PORTB_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PORTC_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PORTD_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="PORTE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="RTC0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="RTC_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="RTC_CLKIN.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
                  <clock_output id="SCGCLKOUT_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="SIRCDIV1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SIRCDIV2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SIRCOUT.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SOSCDIV1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SOSCDIV2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SOSCOUT.outFreq" value="8 MHz" locked="false" accuracy=""/>
                  <clock_output id="SPLLDIV1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="SPLLDIV2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
                  <clock_output id="SYS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
                  <clock_output id="TRACE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
               </clock_outputs>
               <clock_settings>
                  <setting id="DIVBUS.scale" value="1" locked="true"/>
                  <setting id="DIVCORE.scale" value="1" locked="true"/>
                  <setting id="DIVSLOW.scale" value="2" locked="true"/>
                  <setting id="HSRUN:DIVBUS.scale" value="1" locked="true"/>
                  <setting id="HSRUN:DIVCORE.scale" value="1" locked="true"/>
                  <setting id="HSRUN:DIVSLOW.scale" value="2" locked="true"/>
                  <setting id="PREDIV.scale" value="1" locked="true"/>
                  <setting id="RUN:DIVBUS.scale" value="1" locked="true"/>
                  <setting id="RUN:DIVCORE.scale" value="1" locked="true"/>
                  <setting id="RUN:DIVSLOW.scale" value="2" locked="true"/>
                  <setting id="SCG_SOSCCSR_SOSCEN_CFG" value="Enabled" locked="false"/>
                  <setting id="SCG_SPLLCSR_SPLLEN_CFG" value="Enabled" locked="false"/>
                  <setting id="SIRCDIV1.scale" value="1" locked="true"/>
                  <setting id="SIRCDIV2.scale" value="1" locked="true"/>
                  <setting id="SPLLDIV1.scale" value="2" locked="true"/>
                  <setting id="SPLLDIV2.scale" value="4" locked="true"/>
                  <setting id="SPLL_mul.scale" value="24" locked="true"/>
                  <setting id="VLPR:DIVBUS.scale" value="1" locked="true"/>
                  <setting id="VLPR:DIVCORE.scale" value="8" locked="true"/>
                  <setting id="VLPR:DIVSLOW.scale" value="4" locked="true"/>
                  <setting id="VLPR:SCSSEL.sel" value="SIRC" locked="false"/>
               </clock_settings>
               <called_from_default_init>true</called_from_default_init>
            </clock_configuration>
         </clock_configurations>
      </clocks>
      <ddr name="DDR" version="1.0" enabled="false" update_project_code="true">
         <components/>
      </ddr>
      <dcd name="DCD" version="1.0" enabled="false" update_project_code="true" isSelfTest="false">
         <dcdx_profile>
            <processor_version>N/A</processor_version>
         </dcdx_profile>
         <dcdx_configurations/>
      </dcd>
      <ivt name="IVT" version="1.0" enabled="false" update_project_code="true">
         <ivt_profile>
            <processor_version>N/A</processor_version>
         </ivt_profile>
      </ivt>
      <quadspi name="QuadSPI" version="1.0" enabled="false" update_project_code="true">
         <quadspi_profile>
            <processor_version>N/A</processor_version>
         </quadspi_profile>
      </quadspi>
      <periphs name="Peripherals" version="6.0" enabled="true" update_project_code="true">
         <peripherals_profile>
            <processor_version>0.0.0</processor_version>
         </peripherals_profile>
         <functional_groups>
            <functional_group name="BOARD_InitPeripherals" uuid="a6d43dcb-893a-49cd-9d9d-0bb26ff0f05b" called_from_default_init="true" id_prefix="" core="core0">
               <description></description>
               <options/>
               <dependencies/>
               <instances>
                  <instance name="osif_1" uuid="52db9b31-96c2-4a4f-9085-d663d14547cf" type="osif" type_id="osif" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
                     <config_set name="osif" quick_selection="dv_osif">
                        <setting name="OsIfMulticoreSupport" value="false"/>
                        <setting name="OsIfUserModeSupport" value="false"/>
                        <setting name="OsIfDevErrorDetect" value="true"/>
                        <setting name="OsIfUseSystemTimer" value="false"/>
                        <setting name="OsIfUseCustomTimer" value="false"/>
                        <setting name="OsIfInstanceId" value="255"/>
                        <setting name="OsIfOperatingSystemType" value="OsIfBaremetalType"/>
                        <setting name="OsIfCounterFreq" value="48000000"/>
                     </config_set>
                  </instance>
                  <instance name="Port_Ip_1" uuid="880cec75-8e44-42a4-a8f3-9c17761edc7e" type="Port_Ip" type_id="Port_Ip" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
                     <config_set name="Port_Ip">
                        <struct name="PortGeneral">
                           <setting name="PortCiPortIPDevErrorDetect" value="false"/>
                           <setting name="PortEnableUserModeSupport" value="false"/>
                        </struct>
                     </config_set>
                  </instance>
               </instances>
            </functional_group>
         </functional_groups>
         <components>
            <component name="system" uuid="e05613c2-332a-4263-93fa-7c424e4816c2" type_id="system">
               <config_set_global name="SystemModel">
                  <setting name="EcvdGenerationMethod" value="INDIVIDUAL"/>
                  <setting name="EcvdOutputPath" value=""/>
                  <setting name="EcvdGenerationTrigger" value="Generate Configuration"/>
               </config_set_global>
            </component>
         </components>
      </periphs>
   </tools>
</configuration>