S32K146_4G.mex 30 KB

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  1. <?xml version="1.0" encoding= "UTF-8" ?>
  2. <configuration name="S32K146" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_10 http://mcuxpresso.nxp.com/XSD/mex_configuration_10.xsd" uuid="4179bacd-df3b-49d1-b875-310026dec15f" version="10" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_10" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  3. <common>
  4. <processor>S32K146</processor>
  5. <package>S32K146_LQFP144</package>
  6. <mcu_data>PlatformSDK_S32K1_2021_08</mcu_data>
  7. <cores selected="core0">
  8. <core name="Cortex-M4F" id="core0" description=""/>
  9. </cores>
  10. <description></description>
  11. </common>
  12. <preferences>
  13. <validate_boot_init_only>true</validate_boot_init_only>
  14. <generate_extended_information>false</generate_extended_information>
  15. <generate_code_modified_registers_only>false</generate_code_modified_registers_only>
  16. <update_include_paths>true</update_include_paths>
  17. </preferences>
  18. <tools>
  19. <pins name="Pins" version="10.0" enabled="true" update_project_code="true">
  20. <pins_profile>
  21. <processor_version>0.0.0</processor_version>
  22. <power_domains/>
  23. </pins_profile>
  24. <functions_list>
  25. <function name="BOARD_InitPins">
  26. <description>Configures pin routing and optionally pin electrical features.</description>
  27. <options>
  28. <callFromInitBoot>true</callFromInitBoot>
  29. <coreID>core0</coreID>
  30. </options>
  31. <dependencies/>
  32. <pins/>
  33. </function>
  34. </functions_list>
  35. </pins>
  36. <clocks name="Clocks" version="8.0" enabled="true" update_project_code="true">
  37. <generated_project_files>
  38. <file path="board/Clock_Ip_Cfg.c" update_enabled="true"/>
  39. <file path="board/Clock_Ip_Cfg.h" update_enabled="true"/>
  40. <file path="board/Clock_Ip_Cfg_Defines.h" update_enabled="true"/>
  41. <file path="board/Clock_Ip_PBcfg.c" update_enabled="true"/>
  42. <file path="board/Clock_Ip_PBcfg.h" update_enabled="true"/>
  43. </generated_project_files>
  44. <clocks_profile>
  45. <processor_version>0.0.0</processor_version>
  46. </clocks_profile>
  47. <clock_configurations>
  48. <clock_configuration name="BOARD_BootClockRUN">
  49. <description></description>
  50. <options/>
  51. <dependencies>
  52. <dependency resourceType="PinSignal" resourceId="SOSC.EXTAL" description="&apos;External pin&apos; (Pins tool id: SOSC.EXTAL, Clocks tool id: SOSC.EXTAL) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
  53. <feature name="routed" evaluation="">
  54. <data>true</data>
  55. </feature>
  56. <feature name="direction" evaluation="">
  57. <data>INPUT</data>
  58. </feature>
  59. </dependency>
  60. <dependency resourceType="PinSignal" resourceId="SOSC.EXTAL" description="&apos;External pin&apos; (Pins tool id: SOSC.EXTAL, Clocks tool id: SOSC.EXTAL) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
  61. <feature name="direction" evaluation="">
  62. <data>INPUT</data>
  63. </feature>
  64. </dependency>
  65. <dependency resourceType="PinSignal" resourceId=".rtc_clkin" description="&apos;RTC_CLKIN&apos; (Pins tool id: .rtc_clkin, Clocks tool id: RTC.RTC_CLKIN) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
  66. <feature name="routed" evaluation="">
  67. <data>true</data>
  68. </feature>
  69. <feature name="direction" evaluation="">
  70. <data>INPUT</data>
  71. </feature>
  72. </dependency>
  73. <dependency resourceType="PinSignal" resourceId=".rtc_clkin" description="&apos;RTC_CLKIN&apos; (Pins tool id: .rtc_clkin, Clocks tool id: RTC.RTC_CLKIN) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
  74. <feature name="direction" evaluation="">
  75. <data>INPUT</data>
  76. </feature>
  77. </dependency>
  78. <dependency resourceType="SWComponent" resourceId="platform.driver.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
  79. <feature name="enabled" evaluation="equal" configuration="core0">
  80. <data>true</data>
  81. </feature>
  82. </dependency>
  83. </dependencies>
  84. <clock_sources>
  85. <clock_source id="RTC.RTC_CLK_EXT_IN.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
  86. <clock_source id="SOSC.SOSC.outFreq" value="8 MHz" locked="false" enabled="true"/>
  87. </clock_sources>
  88. <clock_outputs>
  89. <clock_output id="ADC0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  90. <clock_output id="ADC1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  91. <clock_output id="BUS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  92. <clock_output id="CLKOUT0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  93. <clock_output id="CMP0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  94. <clock_output id="CORE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  95. <clock_output id="CRC0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  96. <clock_output id="DMA0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  97. <clock_output id="DMAMUX0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  98. <clock_output id="EIM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  99. <clock_output id="ERM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  100. <clock_output id="EWM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  101. <clock_output id="FIRCDIV1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  102. <clock_output id="FIRCDIV2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  103. <clock_output id="FIRCOUT.outFreq" value="48 MHz" locked="false" accuracy=""/>
  104. <clock_output id="FLASH_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
  105. <clock_output id="FLEXCAN0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  106. <clock_output id="FLEXCAN1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  107. <clock_output id="FLEXCAN2_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  108. <clock_output id="FTFC0_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
  109. <clock_output id="FTM0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  110. <clock_output id="FTM1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  111. <clock_output id="FTM2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  112. <clock_output id="FTM3_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  113. <clock_output id="FTM4_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  114. <clock_output id="FTM5_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  115. <clock_output id="FlexIO0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  116. <clock_output id="FlexIO_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  117. <clock_output id="LPI2C0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  118. <clock_output id="LPIT0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  119. <clock_output id="LPO_128K_CLK.outFreq" value="128 kHz" locked="false" accuracy=""/>
  120. <clock_output id="LPO_1K_CLK.outFreq" value="1 kHz" locked="false" accuracy=""/>
  121. <clock_output id="LPO_32K_CLK.outFreq" value="32 kHz" locked="false" accuracy=""/>
  122. <clock_output id="LPO_CLK.outFreq" value="128 kHz" locked="false" accuracy=""/>
  123. <clock_output id="LPSPI0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  124. <clock_output id="LPSPI1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  125. <clock_output id="LPSPI2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  126. <clock_output id="LPTMR0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  127. <clock_output id="LPUART0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  128. <clock_output id="LPUART1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  129. <clock_output id="LPUART2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  130. <clock_output id="MPU0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  131. <clock_output id="MSCM0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  132. <clock_output id="PDB0_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  133. <clock_output id="PDB1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  134. <clock_output id="PORTA_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  135. <clock_output id="PORTB_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  136. <clock_output id="PORTC_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  137. <clock_output id="PORTD_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  138. <clock_output id="PORTE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  139. <clock_output id="RTC0_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  140. <clock_output id="RTC_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  141. <clock_output id="RTC_CLKIN.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
  142. <clock_output id="SCGCLKOUT_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  143. <clock_output id="SIRCDIV1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  144. <clock_output id="SIRCDIV2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  145. <clock_output id="SIRCOUT.outFreq" value="8 MHz" locked="false" accuracy=""/>
  146. <clock_output id="SOSCDIV1_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  147. <clock_output id="SOSCDIV2_CLK.outFreq" value="8 MHz" locked="false" accuracy=""/>
  148. <clock_output id="SOSCOUT.outFreq" value="8 MHz" locked="false" accuracy=""/>
  149. <clock_output id="SPLLDIV1_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  150. <clock_output id="SPLLDIV2_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
  151. <clock_output id="SYS_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  152. <clock_output id="TRACE_CLK.outFreq" value="48 MHz" locked="false" accuracy=""/>
  153. </clock_outputs>
  154. <clock_settings>
  155. <setting id="DIVBUS.scale" value="1" locked="true"/>
  156. <setting id="DIVCORE.scale" value="1" locked="true"/>
  157. <setting id="DIVSLOW.scale" value="2" locked="true"/>
  158. <setting id="HSRUN:DIVBUS.scale" value="1" locked="true"/>
  159. <setting id="HSRUN:DIVCORE.scale" value="1" locked="true"/>
  160. <setting id="HSRUN:DIVSLOW.scale" value="2" locked="true"/>
  161. <setting id="PREDIV.scale" value="1" locked="true"/>
  162. <setting id="RUN:DIVBUS.scale" value="1" locked="true"/>
  163. <setting id="RUN:DIVCORE.scale" value="1" locked="true"/>
  164. <setting id="RUN:DIVSLOW.scale" value="2" locked="true"/>
  165. <setting id="SCG_SOSCCSR_SOSCEN_CFG" value="Enabled" locked="false"/>
  166. <setting id="SCG_SPLLCSR_SPLLEN_CFG" value="Enabled" locked="false"/>
  167. <setting id="SIRCDIV1.scale" value="1" locked="true"/>
  168. <setting id="SIRCDIV2.scale" value="1" locked="true"/>
  169. <setting id="SPLLDIV1.scale" value="2" locked="true"/>
  170. <setting id="SPLLDIV2.scale" value="4" locked="true"/>
  171. <setting id="SPLL_mul.scale" value="24" locked="true"/>
  172. <setting id="VLPR:DIVBUS.scale" value="1" locked="true"/>
  173. <setting id="VLPR:DIVCORE.scale" value="8" locked="true"/>
  174. <setting id="VLPR:DIVSLOW.scale" value="4" locked="true"/>
  175. <setting id="VLPR:SCSSEL.sel" value="SIRC" locked="false"/>
  176. </clock_settings>
  177. <called_from_default_init>true</called_from_default_init>
  178. </clock_configuration>
  179. </clock_configurations>
  180. </clocks>
  181. <ddr name="DDR" version="1.0" enabled="false" update_project_code="true">
  182. <components/>
  183. </ddr>
  184. <dcd name="DCD" version="1.0" enabled="false" update_project_code="true" isSelfTest="false">
  185. <dcdx_profile>
  186. <processor_version>N/A</processor_version>
  187. </dcdx_profile>
  188. <dcdx_configurations/>
  189. </dcd>
  190. <ivt name="IVT" version="1.0" enabled="false" update_project_code="true">
  191. <ivt_profile>
  192. <processor_version>N/A</processor_version>
  193. </ivt_profile>
  194. </ivt>
  195. <quadspi name="QuadSPI" version="1.0" enabled="false" update_project_code="true">
  196. <quadspi_profile>
  197. <processor_version>N/A</processor_version>
  198. </quadspi_profile>
  199. </quadspi>
  200. <periphs name="Peripherals" version="10.0" enabled="true" update_project_code="true">
  201. <dependencies>
  202. <dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="工具链/IDE工程中未找到osif。工程不会被编译!" problem_level="2" source="Peripherals">
  203. <feature name="enabled" evaluation="equal">
  204. <data type="Boolean">true</data>
  205. </feature>
  206. </dependency>
  207. <dependency resourceType="SWComponent" resourceId="platform.driver.osif" description="工具链/IDE工程不支持osif版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
  208. <feature name="version" evaluation="equivalent">
  209. <data type="Version">1.0.0</data>
  210. </feature>
  211. </dependency>
  212. <dependency resourceType="SWComponent" resourceId="platform.driver.port_ip" description="工具链/IDE工程中未找到port_ip。工程不会被编译!" problem_level="2" source="Peripherals">
  213. <feature name="enabled" evaluation="equal">
  214. <data type="Boolean">true</data>
  215. </feature>
  216. </dependency>
  217. <dependency resourceType="SWComponent" resourceId="platform.driver.port_ip" description="工具链/IDE工程不支持port_ip版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
  218. <feature name="version" evaluation="equivalent">
  219. <data type="Version">1.0.0</data>
  220. </feature>
  221. </dependency>
  222. <dependency resourceType="SWComponent" resourceId="platform.driver.spi" description="工具链/IDE工程中未找到Spi。工程不会被编译!" problem_level="2" source="Peripherals">
  223. <feature name="enabled" evaluation="equal">
  224. <data type="Boolean">true</data>
  225. </feature>
  226. </dependency>
  227. <dependency resourceType="SWComponent" resourceId="platform.driver.spi" description="工具链/IDE工程不支持Spi版本。所需值: ${required_value}, 实际值: ${actual_value}. 工程可能没有被正确编译。" problem_level="1" source="Peripherals">
  228. <feature name="version" evaluation="equivalent">
  229. <data type="Version">1.0.0</data>
  230. </feature>
  231. </dependency>
  232. </dependencies>
  233. <peripherals_profile>
  234. <processor_version>0.0.0</processor_version>
  235. </peripherals_profile>
  236. <functional_groups>
  237. <functional_group name="BOARD_InitPeripherals" uuid="a6d43dcb-893a-49cd-9d9d-0bb26ff0f05b" called_from_default_init="true" id_prefix="" core="core0">
  238. <description></description>
  239. <options/>
  240. <dependencies/>
  241. <instances>
  242. <instance name="osif_1" uuid="52db9b31-96c2-4a4f-9085-d663d14547cf" type="osif" type_id="osif" mode="general" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
  243. <config_set name="osif" quick_selection="dv_osif">
  244. <setting name="OsIfMulticoreSupport" value="false"/>
  245. <setting name="OsIfUserModeSupport" value="false"/>
  246. <setting name="OsIfDevErrorDetect" value="true"/>
  247. <setting name="OsIfUseSystemTimer" value="false"/>
  248. <setting name="OsIfUseCustomTimer" value="false"/>
  249. <setting name="OsIfInstanceId" value="255"/>
  250. <setting name="OsIfOperatingSystemType" value="OsIfBaremetalType"/>
  251. <setting name="OsIfCounterFreq" value="48000000"/>
  252. </config_set>
  253. </instance>
  254. <instance name="Port_Ip_1" uuid="880cec75-8e44-42a4-a8f3-9c17761edc7e" type="Port_Ip" type_id="Port_Ip" mode="ip" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
  255. <config_set name="Port_Ip">
  256. <struct name="PortGeneral">
  257. <setting name="PortCiPortIPDevErrorDetect" value="false"/>
  258. <setting name="PortEnableUserModeSupport" value="false"/>
  259. </struct>
  260. </config_set>
  261. </instance>
  262. <instance name="Spi_1" uuid="d52e3268-a692-4da3-9090-3f7ee388dcfe" type="Spi" type_id="Spi" mode="autosar" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
  263. <config_set name="Spi" quick_selection="Default">
  264. <setting name="Name" value="Spi"/>
  265. <struct name="ConfigTimeSupport" quick_selection="Default">
  266. <setting name="POST_BUILD_VARIANT_USED" value="false"/>
  267. <setting name="IMPLEMENTATION_CONFIG_VARIANT" value="VARIANT-PRE-COMPILE"/>
  268. </struct>
  269. <array name="SpiDemEventParameterRefs"/>
  270. <struct name="SpiDriver" quick_selection="Default">
  271. <setting name="Name" value="SpiDriver"/>
  272. <array name="SpiMaxChannel">
  273. <setting name="0" value="0"/>
  274. </array>
  275. <array name="SpiMaxJob">
  276. <setting name="0" value="0"/>
  277. </array>
  278. <array name="SpiMaxSequence">
  279. <setting name="0" value="0"/>
  280. </array>
  281. <array name="SpiChannel">
  282. <struct name="0">
  283. <setting name="Name" value="SpiChannel_0"/>
  284. <setting name="SpiChannelId" value="0"/>
  285. <setting name="SpiChannelType" value="IB"/>
  286. <setting name="SpiDataWidth" value="8"/>
  287. <array name="SpiDefaultData">
  288. <setting name="0" value="1"/>
  289. </array>
  290. <setting name="SpiEbMaxLength" value="1"/>
  291. <setting name="SpiIbNBuffers" value="1"/>
  292. <setting name="SpiTransferStart" value="LSB"/>
  293. <setting name="SpiChannelHalfDuplexSupport" value="false"/>
  294. <setting name="SpiChannelHalfDuplexDirection" value="HALF_DUPLEX_TRANSMIT"/>
  295. <array name="SpiChannelEcucPartitionRef"/>
  296. </struct>
  297. </array>
  298. <array name="SpiExternalDevice">
  299. <struct name="0">
  300. <setting name="Name" value="SpiExternalDevice_0"/>
  301. <setting name="SpiBaudrate" value="100000"/>
  302. <setting name="SpiCsIdentifier" value="PCS0"/>
  303. <setting name="SpiCsPolarity" value="LOW"/>
  304. <array name="SpiCsSelection">
  305. <setting name="0" value="CS_VIA_PERIPHERAL_ENGINE"/>
  306. </array>
  307. <setting name="SpiDataShiftEdge" value="LEADING"/>
  308. <setting name="SpiEnableCs" value="true"/>
  309. <setting name="SpiHwUnit" value="CSIB0"/>
  310. <setting name="SpiShiftClockIdleLevel" value="HIGH"/>
  311. <setting name="SpiTimeClk2Cs" value="0.000001"/>
  312. <setting name="SpiTimeCs2Clk" value="0.000001"/>
  313. <setting name="SpiTimeCs2Cs" value="0.0000064"/>
  314. <setting name="SpiDeviceHalfDuplexSupport" value="false"/>
  315. <setting name="SpiTransferWidth" value="TRANSFER_1_BIT"/>
  316. <setting name="SpiHalfDuplexPinSelect" value="HALF_DUPLEX_SIN"/>
  317. <setting name="SpiCsContinous" value="TRUE"/>
  318. <array name="SpiDeviceEcucPartitionRef"/>
  319. </struct>
  320. </array>
  321. <array name="SpiJob">
  322. <struct name="0">
  323. <setting name="Name" value="SpiJob_0"/>
  324. <array name="SpiJobEndNotification">
  325. <setting name="0" value="NULL_PTR"/>
  326. </array>
  327. <array name="SpiJobStartNotification">
  328. <setting name="0" value="NULL_PTR"/>
  329. </array>
  330. <setting name="SpiJobId" value="0"/>
  331. <setting name="SpiJobPriority" value="0"/>
  332. <setting name="SpiDeviceAssignment" value="/Spi_1/Spi/SpiDriver/SpiExternalDevice_0"/>
  333. <array name="SpiChannelList">
  334. <struct name="0">
  335. <setting name="Name" value="SpiChannelList_0"/>
  336. <setting name="SpiChannelIndex" value="0"/>
  337. <setting name="SpiChannelAssignment" value="/Spi_1/Spi/SpiDriver/SpiChannel_0"/>
  338. </struct>
  339. </array>
  340. </struct>
  341. </array>
  342. <array name="SpiSequence">
  343. <struct name="0">
  344. <setting name="Name" value="SpiSequence_0"/>
  345. <setting name="SpiInterruptibleSequence" value="false"/>
  346. <array name="SpiSeqEndNotification">
  347. <setting name="0" value="NULL_PTR"/>
  348. </array>
  349. <setting name="SpiSequenceId" value="0"/>
  350. <setting name="SpiEnableDmaFastTransfer" value="false"/>
  351. <array name="SpiJobAssignment">
  352. <setting name="0" value="/Spi_1/Spi/SpiDriver/SpiJob_0"/>
  353. </array>
  354. </struct>
  355. </array>
  356. </struct>
  357. <struct name="SpiGeneral" quick_selection="Default">
  358. <setting name="Name" value="SpiGeneral"/>
  359. <setting name="SpiMulticoreSupport" value="false"/>
  360. <setting name="SpiCancelApi" value="true"/>
  361. <setting name="SpiChannelBuffersAllowed" value="0"/>
  362. <setting name="SpiDevErrorDetect" value="true"/>
  363. <setting name="SpiHwStatusApi" value="true"/>
  364. <setting name="SpiInterruptibleSeqAllowed" value="false"/>
  365. <setting name="SpiLevelDelivered" value="2"/>
  366. <array name="SpiMainFunctionPeriod">
  367. <setting name="0" value="0.01"/>
  368. </array>
  369. <setting name="SpiSupportConcurrentSyncTransmit" value="false"/>
  370. <setting name="SpiVersionInfoApi" value="true"/>
  371. <setting name="SpiGlobalDmaEnable" value="false"/>
  372. <setting name="SpiFlexioEnable" value="false"/>
  373. <setting name="SpiTimeoutMethod" value="OSIF_COUNTER_DUMMY"/>
  374. <setting name="SpiTransmitTimeout" value="50000"/>
  375. <array name="SpiEcucPartitionRef"/>
  376. <array name="SpiKernelEcucPartitionRef"/>
  377. <array name="SpiPhyUnit">
  378. <struct name="0">
  379. <setting name="Name" value="SpiPhyUnit_0"/>
  380. <setting name="SpiPhyUnitMapping" value="LPSPI_0"/>
  381. <setting name="SpiPinConfiguration" value="0"/>
  382. <setting name="SpiSamplePoint" value="0"/>
  383. <setting name="SpiPhyUnitClockRef" value=""/>
  384. <array name="SpiPhyUnitAlternateClockRef"/>
  385. <setting name="SpiPhyUnitMode" value="SPI_MASTER"/>
  386. <setting name="SpiPhyUnitSync" value="true"/>
  387. <setting name="SpiPhyUnitAsyncUseDma" value="false"/>
  388. <array name="SpiPhyTxDmaChannel"/>
  389. <array name="SpiPhyRxDmaChannel"/>
  390. <array name="SpiMaxDmaFastTransfer"/>
  391. <array name="SpiFlexioTxAndClkChannelsConfig"/>
  392. <array name="SpiFlexioRxAndCsChannelsConfig"/>
  393. </struct>
  394. </array>
  395. </struct>
  396. <struct name="SpiPublishedInformation" quick_selection="Default">
  397. <setting name="Name" value="SpiPublishedInformation"/>
  398. <setting name="SpiMaxHwUnit" value="0"/>
  399. </struct>
  400. <struct name="SpiAutosarExt" quick_selection="Default">
  401. <setting name="Name" value="SpiAutosarExt"/>
  402. <setting name="SpiEnableUserModeSupport" value="false"/>
  403. <setting name="SpiEnableDmaFastTransferSupport" value="false"/>
  404. <setting name="SpiHalfDuplexModeSupport" value="false"/>
  405. <setting name="SpiAllowBigSizeCollections" value="false"/>
  406. <setting name="SpiEnableHWUnitAsyncMode" value="true"/>
  407. <setting name="SpiJobStartNotificationEnable" value="false"/>
  408. <setting name="SpiDisableDemReportErrorStatus" value="false"/>
  409. </struct>
  410. <struct name="CommonPublishedInformation" quick_selection="Default">
  411. <setting name="Name" value="CommonPublishedInformation"/>
  412. <setting name="ModuleId" value="83"/>
  413. <setting name="VendorId" value="43"/>
  414. <array name="VendorApiInfix"/>
  415. <setting name="ArReleaseMajorVersion" value="4"/>
  416. <setting name="ArReleaseMinorVersion" value="4"/>
  417. <setting name="ArReleaseRevisionVersion" value="0"/>
  418. <setting name="SwMajorVersion" value="1"/>
  419. <setting name="SwMinorVersion" value="0"/>
  420. <setting name="SwPatchVersion" value="0"/>
  421. </struct>
  422. </config_set>
  423. </instance>
  424. </instances>
  425. </functional_group>
  426. </functional_groups>
  427. <components>
  428. <component name="system" uuid="e05613c2-332a-4263-93fa-7c424e4816c2" type_id="system">
  429. <config_set_global name="SystemModel">
  430. <setting name="EcvdGenerationMethod" value="INDIVIDUAL"/>
  431. <setting name="EcvdOutputPath" value=""/>
  432. <setting name="EcvdGenerationTrigger" value="Generate Configuration"/>
  433. </config_set_global>
  434. </component>
  435. </components>
  436. </periphs>
  437. </tools>
  438. </configuration>