IPA summary for Flexio_Uart_Ip_SetRxBuffer/54 is missing.
IPA summary for Flexio_Uart_Ip_SetTxBuffer/53 is missing.
IPA summary for Flexio_Uart_Ip_SetBaudRate/52 is missing.
IPA summary for Flexio_Uart_Ip_AbortTransferData/51 is missing.
IPA summary for Flexio_Uart_Ip_CompleteReceiveUsingDma/50 is missing.
IPA summary for Flexio_Uart_Ip_CompleteSendUsingDma/49 is missing.
IPA summary for Flexio_Uart_Ip_SyncReceive/48 is missing.
IPA summary for Flexio_Uart_Ip_AsyncReceive/47 is missing.
IPA summary for Flexio_Uart_Ip_SyncSend/46 is missing.
IPA summary for Flexio_Uart_Ip_GetStatus/45 is missing.
IPA summary for Flexio_Uart_Ip_AsyncSend/44 is missing.
IPA summary for Flexio_Uart_Ip_Deinit/43 is missing.
IPA summary for Flexio_Uart_Ip_GetBaudRate/42 is missing.
IPA summary for Flexio_Uart_Ip_Init/41 is missing.
IPA summary for Flexio_Uart_Ip_StartReceiveDataUsingDma/40 is missing.
IPA summary for Flexio_Uart_Ip_StartSendDataUsingDma/39 is missing.
IPA summary for Flexio_Uart_Ip_EnableReceiver/38 is missing.
IPA summary for Flexio_Uart_Ip_SetupReceiveData/37 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterInterrupt/36 is missing.
IPA summary for Flexio_Uart_Ip_CheckShifterErrorStatus/35 is missing.
IPA summary for Flexio_Uart_Ip_CheckRxOperation/34 is missing.
IPA summary for Flexio_Uart_Ip_ReadData/33 is missing.
IPA summary for Flexio_Uart_Ip_CheckCompleteTransferData/32 is missing.
IPA summary for Flexio_Uart_Ip_CheckTxOperation/31 is missing.
IPA summary for Flexio_Uart_Ip_WriteData/30 is missing.
IPA summary for Flexio_Uart_Ip_StopTransfer/29 is missing.
IPA summary for Flexio_Uart_Ip_EndTransfer/28 is missing.
IPA summary for Flexio_Uart_Ip_ConfigureRx/27 is missing.
IPA summary for Flexio_Uart_Ip_ConfigureTx/26 is missing.
IPA summary for Flexio_Uart_Ip_IrqHandler/25 is missing.
IPA summary for DevAssert/20 is missing.
IPA summary for Flexio_Uart_Ip_CheckTimeout/19 is missing.
IPA summary for Flexio_Uart_Ip_StartTimeout/18 is missing.
IPA summary for Flexio_Uart_Ip_GetShifterInterrupt/17 is missing.
IPA summary for Flexio_Uart_Ip_GetShifterErrorInterrupt/16 is missing.
IPA summary for Flexio_Uart_Ip_GetTimerInterrupt/15 is missing.
IPA summary for Flexio_Uart_Ip_ReadShifterBuffer/14 is missing.
IPA summary for Flexio_Uart_Ip_WriteShifterBuffer/13 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterStartBit/12 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterMode/11 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerMode/10 is missing.
IPA summary for Flexio_Uart_Ip_SetPinTimerControl/9 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerTrigger/8 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerControl/7 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerCondition/6 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerConfig/4 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerCompare/3 is missing.
IPA summary for Flexio_Uart_Ip_SetPinShifterControl/2 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterControl/1 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterConfig/0 is missing.

Flattening functions:
Overall time estimate: 0.000000 weighted by profile: 0.000000

Deciding on inlining of small functions.  Starting with size 0.

Reclaiming functions:
Reclaiming variables:
Clearing address taken flags:

Deciding on functions to be inlined into all callers and removing useless speculations:
Overall time estimate: 0.000000 weighted by profile: 0.000000

Why inlining failed?
function not considered for inlining              :      150 calls, 150.000000 freq, 0 count
function body not available                       :       67 calls, 67.000000 freq, 0 count
IPA summary for Flexio_Uart_Ip_SetRxBuffer/54 is missing.
IPA summary for Flexio_Uart_Ip_SetTxBuffer/53 is missing.
IPA summary for Flexio_Uart_Ip_SetBaudRate/52 is missing.
IPA summary for Flexio_Uart_Ip_AbortTransferData/51 is missing.
IPA summary for Flexio_Uart_Ip_CompleteReceiveUsingDma/50 is missing.
IPA summary for Flexio_Uart_Ip_CompleteSendUsingDma/49 is missing.
IPA summary for Flexio_Uart_Ip_SyncReceive/48 is missing.
IPA summary for Flexio_Uart_Ip_AsyncReceive/47 is missing.
IPA summary for Flexio_Uart_Ip_SyncSend/46 is missing.
IPA summary for Flexio_Uart_Ip_GetStatus/45 is missing.
IPA summary for Flexio_Uart_Ip_AsyncSend/44 is missing.
IPA summary for Flexio_Uart_Ip_Deinit/43 is missing.
IPA summary for Flexio_Uart_Ip_GetBaudRate/42 is missing.
IPA summary for Flexio_Uart_Ip_Init/41 is missing.
IPA summary for Flexio_Uart_Ip_StartReceiveDataUsingDma/40 is missing.
IPA summary for Flexio_Uart_Ip_StartSendDataUsingDma/39 is missing.
IPA summary for Flexio_Uart_Ip_EnableReceiver/38 is missing.
IPA summary for Flexio_Uart_Ip_SetupReceiveData/37 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterInterrupt/36 is missing.
IPA summary for Flexio_Uart_Ip_CheckShifterErrorStatus/35 is missing.
IPA summary for Flexio_Uart_Ip_CheckRxOperation/34 is missing.
IPA summary for Flexio_Uart_Ip_ReadData/33 is missing.
IPA summary for Flexio_Uart_Ip_CheckCompleteTransferData/32 is missing.
IPA summary for Flexio_Uart_Ip_CheckTxOperation/31 is missing.
IPA summary for Flexio_Uart_Ip_WriteData/30 is missing.
IPA summary for Flexio_Uart_Ip_StopTransfer/29 is missing.
IPA summary for Flexio_Uart_Ip_EndTransfer/28 is missing.
IPA summary for Flexio_Uart_Ip_ConfigureRx/27 is missing.
IPA summary for Flexio_Uart_Ip_ConfigureTx/26 is missing.
IPA summary for Flexio_Uart_Ip_IrqHandler/25 is missing.
IPA summary for DevAssert/20 is missing.
IPA summary for Flexio_Uart_Ip_CheckTimeout/19 is missing.
IPA summary for Flexio_Uart_Ip_StartTimeout/18 is missing.
IPA summary for Flexio_Uart_Ip_GetShifterInterrupt/17 is missing.
IPA summary for Flexio_Uart_Ip_GetShifterErrorInterrupt/16 is missing.
IPA summary for Flexio_Uart_Ip_GetTimerInterrupt/15 is missing.
IPA summary for Flexio_Uart_Ip_ReadShifterBuffer/14 is missing.
IPA summary for Flexio_Uart_Ip_WriteShifterBuffer/13 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterStartBit/12 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterMode/11 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerMode/10 is missing.
IPA summary for Flexio_Uart_Ip_SetPinTimerControl/9 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerTrigger/8 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerControl/7 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerCondition/6 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerConfig/4 is missing.
IPA summary for Flexio_Uart_Ip_SetTimerCompare/3 is missing.
IPA summary for Flexio_Uart_Ip_SetPinShifterControl/2 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterControl/1 is missing.
IPA summary for Flexio_Uart_Ip_SetShifterConfig/0 is missing.
Symbol table:

Dma_Ip_GetLogicChannelStatus/80 (Dma_Ip_GetLogicChannelStatus) @074dc8c0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 
  Calls: 
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07/79 (SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07) @074dc620
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 
  Calls: 
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07/78 (SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07) @074dc540
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncReceive/48 
  Calls: 
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06/77 (SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06) @074dc2a0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 
  Calls: 
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06/76 (SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06) @074dc1c0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_AsyncReceive/47 
  Calls: 
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05/75 (SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05) @074dc000
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 
  Calls: 
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05/74 (SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05) @074c5ee0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncSend/46 
  Calls: 
Dma_Ip_GetLogicChannelParam/73 (Dma_Ip_GetLogicChannelParam) @074c5c40
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_GetStatus/45 
  Calls: 
SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04/72 (SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04) @074c5a80
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 
  Calls: 
SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04/71 (SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04) @074c59a0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_AsyncSend/44 
  Calls: 
Flexio_Mcl_Ip_SetSoftwareReset/70 (Flexio_Mcl_Ip_SetSoftwareReset) @074c57e0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_Deinit/43 
  Calls: 
Dma_Ip_SetLogicChannelCommand/69 (Dma_Ip_SetLogicChannelCommand) @074c5380
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_AbortTransferData/51 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_StartSendDataUsingDma/39 
  Calls: 
Dma_Ip_SetLogicChannelTransferList/68 (Dma_Ip_SetLogicChannelTransferList) @074c52a0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_StartSendDataUsingDma/39 
  Calls: 
Flexio_Mcl_Ip_SetShifterErrorInterrupt/67 (Flexio_Mcl_Ip_SetShifterErrorInterrupt) @074afee0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SetShifterInterrupt/36 
  Calls: 
Flexio_Mcl_Ip_GetShifterErrorStatus/66 (Flexio_Mcl_Ip_GetShifterErrorStatus) @074afd20
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CheckShifterErrorStatus/35 
  Calls: 
Flexio_Mcl_Ip_SetShifterInterrupt/65 (Flexio_Mcl_Ip_SetShifterInterrupt) @074af700
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SetShifterInterrupt/36 Flexio_Uart_Ip_CheckCompleteTransferData/32 
  Calls: 
Flexio_Mcl_Ip_GetShifterStatus/64 (Flexio_Mcl_Ip_GetShifterStatus) @074af380
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: 
OsIf_GetElapsed/63 (OsIf_GetElapsed) @074a3b60
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CheckTimeout/19 
  Calls: 
OsIf_MicrosToTicks/62 (OsIf_MicrosToTicks) @074a39a0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_StartTimeout/18 
  Calls: 
OsIf_GetCounter/61 (OsIf_GetCounter) @074a38c0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_StartTimeout/18 
  Calls: 
Flexio_Mcl_Ip_GetTimerStatus/60 (Flexio_Mcl_Ip_GetTimerStatus) @074a3700
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_StopTransfer/29 
  Calls: 
Flexio_Mcl_Ip_SetShifterDMARequest/59 (Flexio_Mcl_Ip_SetShifterDMARequest) @074a3540
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_StartSendDataUsingDma/39 Flexio_Uart_Ip_EndTransfer/28 
  Calls: 
Flexio_Mcl_Ip_SetTimerInterrupt/58 (Flexio_Mcl_Ip_SetTimerInterrupt) @074a3460
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_EndTransfer/28 Flexio_Uart_Ip_EndTransfer/28 Flexio_Uart_Ip_CheckCompleteTransferData/32 
  Calls: 
Flexio_Mcl_Ip_ClearShifterErrorStatus/57 (Flexio_Mcl_Ip_ClearShifterErrorStatus) @06e1a8c0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_IrqHandler/25 Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_StopTransfer/29 Flexio_Uart_Ip_CheckShifterErrorStatus/35 
  Calls: 
Flexio_Mcl_Ip_ClearShifterStatus/56 (Flexio_Mcl_Ip_ClearShifterStatus) @06e1a7e0
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_EnableReceiver/38 Flexio_Uart_Ip_IrqHandler/25 Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_CheckTxOperation/31 Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: 
Flexio_Mcl_Ip_ClearTimerStatus/55 (Flexio_Mcl_Ip_ClearTimerStatus) @06e1a700
  Type: function
  Visibility: external public
  References: 
  Referring: 
  Availability: not_available
  Function flags:
  Called by: Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_IrqHandler/25 Flexio_Uart_Ip_CheckTxOperation/31 Flexio_Uart_Ip_CheckCompleteTransferData/32 
  Calls: 
Flexio_Uart_Ip_SetRxBuffer/54 (Flexio_Uart_Ip_SetRxBuffer) @06e1a2a0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_SetTxBuffer/53 (Flexio_Uart_Ip_SetTxBuffer) @06e1a000
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_SetBaudRate/52 (Flexio_Uart_Ip_SetBaudRate) @06e01a80
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_SetTimerCondition/6 Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 Flexio_Uart_Ip_SetTimerConfig/4 Flexio_Uart_Ip_SetTimerCondition/6 Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 Flexio_Uart_Ip_SetTimerConfig/4 Flexio_Uart_Ip_SetTimerCompare/3 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_AbortTransferData/51 (Flexio_Uart_Ip_AbortTransferData) @06e01380
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Dma_Ip_SetLogicChannelCommand/69 Flexio_Uart_Ip_StopTransfer/29 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_CompleteReceiveUsingDma/50 (Flexio_Uart_Ip_CompleteReceiveUsingDma) @06e01ee0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AbortTransferData/51 
  Calls: Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Mcl_Ip_GetTimerStatus/60 Flexio_Uart_Ip_StartTimeout/18 Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Mcl_Ip_SetShifterDMARequest/59 Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Uart_Ip_SetShifterInterrupt/36 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 DevAssert/20 Dma_Ip_SetLogicChannelTransferList/68 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 Dma_Ip_GetLogicChannelStatus/80 DevAssert/20 
   Indirect call
   Indirect call
   Indirect call
Flexio_Uart_Ip_CompleteSendUsingDma/49 (Flexio_Uart_Ip_CompleteSendUsingDma) @06e01c40
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AbortTransferData/51 
  Calls: Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Mcl_Ip_GetTimerStatus/60 Flexio_Uart_Ip_StartTimeout/18 Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Mcl_Ip_SetShifterDMARequest/59 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 DevAssert/20 Dma_Ip_SetLogicChannelTransferList/68 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 Dma_Ip_GetLogicChannelStatus/80 DevAssert/20 
   Indirect call
   Indirect call
   Indirect call
Flexio_Uart_Ip_SyncReceive/48 (Flexio_Uart_Ip_SyncReceive) @06e019a0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Mcl_Ip_ClearTimerStatus/55 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_ReadData/33 Flexio_Uart_Ip_CheckShifterErrorStatus/35 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Mcl_Ip_GetShifterStatus/64 Flexio_Uart_Ip_StartTimeout/18 Flexio_Uart_Ip_SetupReceiveData/37 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07/79 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07/79 SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07/78 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_AsyncReceive/47 (Flexio_Uart_Ip_AsyncReceive) @06e01620
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_SetShifterInterrupt/36 Flexio_Uart_Ip_EnableReceiver/38 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06/77 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06/77 SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06/76 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_SyncSend/46 (Flexio_Uart_Ip_SyncSend) @06e012a0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Mcl_Ip_ClearTimerStatus/55 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Mcl_Ip_GetShifterStatus/64 Flexio_Uart_Ip_WriteData/30 Flexio_Uart_Ip_StartTimeout/18 Flexio_Uart_Ip_SetTimerMode/10 Flexio_Uart_Ip_SetShifterInterrupt/36 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05/75 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05/75 SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05/74 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_GetStatus/45 (Flexio_Uart_Ip_GetStatus) @06ed0ee0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_Deinit/43 
  Calls: Dma_Ip_GetLogicChannelParam/73 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_AsyncSend/44 (Flexio_Uart_Ip_AsyncSend) @06ed08c0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_StartSendDataUsingDma/39 Flexio_Uart_Ip_SetShifterInterrupt/36 Flexio_Uart_Ip_SetTimerMode/10 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04/72 SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04/72 SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04/71 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_Deinit/43 (Flexio_Uart_Ip_Deinit) @06ed0e00
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apStateStructuresArray/24 (write)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Mcl_Ip_SetSoftwareReset/70 Flexio_Mcl_Ip_SetSoftwareReset/70 Flexio_Uart_Ip_SetShifterInterrupt/36 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Uart_Ip_GetStatus/45 Flexio_Uart_Ip_StartTimeout/18 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_GetBaudRate/42 (Flexio_Uart_Ip_GetBaudRate) @06ed0a80
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_Init/41 (Flexio_Uart_Ip_Init) @06ed07e0
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apStateStructuresArray/24 (write)Flexio_Uart_Ip_apUserConfig/23 (write)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 DevAssert/20 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_StartReceiveDataUsingDma/40 (Flexio_Uart_Ip_StartReceiveDataUsingDma) @06ed0460
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AsyncReceive/47 
  Calls: Flexio_Mcl_Ip_SetShifterDMARequest/59 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 DevAssert/20 Dma_Ip_SetLogicChannelTransferList/68 
Flexio_Uart_Ip_StartSendDataUsingDma/39 (Flexio_Uart_Ip_StartSendDataUsingDma) @06ed00e0
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AsyncSend/44 
  Calls: Flexio_Mcl_Ip_SetShifterDMARequest/59 DevAssert/20 Dma_Ip_SetLogicChannelCommand/69 DevAssert/20 Dma_Ip_SetLogicChannelTransferList/68 
Flexio_Uart_Ip_EnableReceiver/38 (Flexio_Uart_Ip_EnableReceiver) @07462b60
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_SetupReceiveData/37 
  Calls: Flexio_Uart_Ip_SetTimerMode/10 Flexio_Uart_Ip_SetShifterMode/11 Flexio_Mcl_Ip_ClearShifterStatus/56 
Flexio_Uart_Ip_SetupReceiveData/37 (Flexio_Uart_Ip_SetupReceiveData) @07462540
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_SyncReceive/48 
  Calls: Flexio_Uart_Ip_EnableReceiver/38 Flexio_Uart_Ip_SetShifterInterrupt/36 
Flexio_Uart_Ip_SetShifterInterrupt/36 (Flexio_Uart_Ip_SetShifterInterrupt) @07462000
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_SetupReceiveData/37 Flexio_Uart_Ip_EndTransfer/28 
  Calls: Flexio_Mcl_Ip_SetShifterErrorInterrupt/67 Flexio_Mcl_Ip_SetShifterInterrupt/65 
Flexio_Uart_Ip_CheckShifterErrorStatus/35 (Flexio_Uart_Ip_CheckShifterErrorStatus) @07462d20
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_SyncReceive/48 
  Calls: Flexio_Mcl_Ip_ClearShifterErrorStatus/57 Flexio_Mcl_Ip_GetShifterErrorStatus/66 
Flexio_Uart_Ip_CheckRxOperation/34 (Flexio_Uart_Ip_CheckRxOperation) @07462a80
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_IrqHandler/25 
  Calls: Flexio_Uart_Ip_StopTransfer/29 Flexio_Mcl_Ip_ClearShifterStatus/56 Flexio_Uart_Ip_ReadData/33 Flexio_Mcl_Ip_ClearShifterStatus/56 Flexio_Uart_Ip_GetShifterInterrupt/17 Flexio_Mcl_Ip_ClearShifterErrorStatus/57 Flexio_Uart_Ip_GetShifterErrorInterrupt/16 
   Indirect call
   Indirect call
   Indirect call
Flexio_Uart_Ip_ReadData/33 (Flexio_Uart_Ip_ReadData) @074627e0
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_CheckRxOperation/34 
  Calls: Flexio_Uart_Ip_ReadShifterBuffer/14 DevAssert/20 DevAssert/20 
Flexio_Uart_Ip_CheckCompleteTransferData/32 (Flexio_Uart_Ip_CheckCompleteTransferData) @07462460
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Mcl_Ip_SetShifterInterrupt/65 Flexio_Mcl_Ip_ClearTimerStatus/55 
   Indirect call
Flexio_Uart_Ip_CheckTxOperation/31 (Flexio_Uart_Ip_CheckTxOperation) @074621c0
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_IrqHandler/25 
  Calls: Flexio_Uart_Ip_CheckCompleteTransferData/32 Flexio_Uart_Ip_WriteData/30 Flexio_Mcl_Ip_ClearShifterStatus/56 Flexio_Uart_Ip_GetShifterInterrupt/17 Flexio_Uart_Ip_WriteShifterBuffer/13 Flexio_Uart_Ip_SetShifterStartBit/12 Flexio_Mcl_Ip_GetShifterStatus/64 Flexio_Uart_Ip_StopTransfer/29 Flexio_Mcl_Ip_ClearShifterStatus/56 Flexio_Mcl_Ip_ClearTimerStatus/55 Flexio_Uart_Ip_GetTimerInterrupt/15 
   Indirect call
Flexio_Uart_Ip_WriteData/30 (Flexio_Uart_Ip_WriteData) @0733dee0
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apUserConfig/23 (read)Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: Flexio_Uart_Ip_WriteShifterBuffer/13 DevAssert/20 
Flexio_Uart_Ip_StopTransfer/29 (Flexio_Uart_Ip_StopTransfer) @0733d700
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apUserConfig/23 (read)Flexio_Uart_Ip_apStateStructuresArray/24 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_AbortTransferData/51 Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: Flexio_Uart_Ip_SetShifterMode/11 Flexio_Uart_Ip_SetShifterStartBit/12 Flexio_Mcl_Ip_ClearShifterErrorStatus/57 Flexio_Uart_Ip_SetShifterMode/11 Flexio_Uart_Ip_SetTimerMode/10 Flexio_Uart_Ip_CheckTimeout/19 Flexio_Mcl_Ip_GetTimerStatus/60 Flexio_Uart_Ip_StartTimeout/18 Flexio_Uart_Ip_EndTransfer/28 
Flexio_Uart_Ip_EndTransfer/28 (Flexio_Uart_Ip_EndTransfer) @0733de00
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: Flexio_Uart_Ip_apStateStructuresArray/24 (read)Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_StopTransfer/29 
  Calls: Flexio_Mcl_Ip_SetShifterDMARequest/59 Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Mcl_Ip_SetTimerInterrupt/58 Flexio_Uart_Ip_SetShifterInterrupt/36 
Flexio_Uart_Ip_ConfigureRx/27 (Flexio_Uart_Ip_ConfigureRx) @0733db60
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_Init/41 
  Calls: Flexio_Uart_Ip_SetPinTimerControl/9 Flexio_Uart_Ip_SetTimerTrigger/8 Flexio_Uart_Ip_SetTimerControl/7 Flexio_Uart_Ip_SetTimerCondition/6 Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 Flexio_Uart_Ip_SetTimerConfig/4 Flexio_Uart_Ip_SetTimerCompare/3 Flexio_Uart_Ip_SetPinShifterControl/2 Flexio_Uart_Ip_SetShifterControl/1 Flexio_Uart_Ip_SetShifterConfig/0 
Flexio_Uart_Ip_ConfigureTx/26 (Flexio_Uart_Ip_ConfigureTx) @0733d8c0
  Type: function definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Function flags: body
  Called by: Flexio_Uart_Ip_Init/41 
  Calls: Flexio_Uart_Ip_SetPinTimerControl/9 Flexio_Uart_Ip_SetTimerTrigger/8 Flexio_Uart_Ip_SetTimerControl/7 Flexio_Uart_Ip_SetTimerCondition/6 Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 Flexio_Uart_Ip_SetTimerConfig/4 Flexio_Uart_Ip_SetTimerCompare/3 Flexio_Uart_Ip_SetPinShifterControl/2 Flexio_Uart_Ip_SetShifterControl/1 Flexio_Uart_Ip_SetShifterConfig/0 
Flexio_Uart_Ip_IrqHandler/25 (Flexio_Uart_Ip_IrqHandler) @0733d620
  Type: function definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: Flexio_Uart_Ip_apUserConfig/23 (read)
  Referring: 
  Availability: available
  Function flags: body
  Called by: 
  Calls: Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_CheckTxOperation/31 Flexio_Mcl_Ip_ClearShifterErrorStatus/57 Flexio_Mcl_Ip_ClearShifterStatus/56 Flexio_Mcl_Ip_ClearTimerStatus/55 
Flexio_Uart_Ip_apStateStructuresArray/24 (Flexio_Uart_Ip_apStateStructuresArray) @07335480
  Type: variable definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: Flexio_Uart_Ip_ReadData/33 (read)Flexio_Uart_Ip_CheckShifterErrorStatus/35 (read)Flexio_Uart_Ip_SetBaudRate/52 (read)Flexio_Uart_Ip_EndTransfer/28 (read)Flexio_Uart_Ip_SetTxBuffer/53 (read)Flexio_Uart_Ip_WriteData/30 (read)Flexio_Uart_Ip_StopTransfer/29 (read)Flexio_Uart_Ip_CheckCompleteTransferData/32 (read)Flexio_Uart_Ip_CheckTxOperation/31 (read)Flexio_Uart_Ip_CheckRxOperation/34 (read)Flexio_Uart_Ip_AbortTransferData/51 (read)Flexio_Uart_Ip_StartSendDataUsingDma/39 (read)Flexio_Uart_Ip_StartReceiveDataUsingDma/40 (read)Flexio_Uart_Ip_Init/41 (read)Flexio_Uart_Ip_AsyncSend/44 (read)Flexio_Uart_Ip_Init/41 (write)Flexio_Uart_Ip_GetBaudRate/42 (read)Flexio_Uart_Ip_GetStatus/45 (read)Flexio_Uart_Ip_Deinit/43 (write)Flexio_Uart_Ip_SyncSend/46 (read)Flexio_Uart_Ip_AsyncReceive/47 (read)Flexio_Uart_Ip_SyncReceive/48 (read)Flexio_Uart_Ip_CompleteSendUsingDma/49 (read)Flexio_Uart_Ip_CompleteReceiveUsingDma/50 (read)Flexio_Uart_Ip_Deinit/43 (read)Flexio_Uart_Ip_SetRxBuffer/54 (read)
  Availability: available
  Varpool flags:
Flexio_Uart_Ip_apUserConfig/23 (Flexio_Uart_Ip_apUserConfig) @073353f0
  Type: variable definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: 
  Referring: Flexio_Uart_Ip_CheckTxOperation/31 (read)Flexio_Uart_Ip_CheckCompleteTransferData/32 (read)Flexio_Uart_Ip_ReadData/33 (read)Flexio_Uart_Ip_CompleteReceiveUsingDma/50 (read)Flexio_Uart_Ip_EndTransfer/28 (read)Flexio_Uart_Ip_AbortTransferData/51 (read)Flexio_Uart_Ip_WriteData/30 (read)Flexio_Uart_Ip_StopTransfer/29 (read)Flexio_Uart_Ip_CheckRxOperation/34 (read)Flexio_Uart_Ip_IrqHandler/25 (read)Flexio_Uart_Ip_StartSendDataUsingDma/39 (read)Flexio_Uart_Ip_StartReceiveDataUsingDma/40 (read)Flexio_Uart_Ip_Init/41 (write)Flexio_Uart_Ip_AsyncSend/44 (read)Flexio_Uart_Ip_GetStatus/45 (read)Flexio_Uart_Ip_SyncSend/46 (read)Flexio_Uart_Ip_AsyncReceive/47 (read)Flexio_Uart_Ip_SyncReceive/48 (read)Flexio_Uart_Ip_CompleteSendUsingDma/49 (read)Flexio_Uart_Ip_SetBaudRate/52 (read)
  Availability: available
  Varpool flags:
Flexio_Uart_Ip_apBases/22 (Flexio_Uart_Ip_apBases) @07335360
  Type: variable definition analyzed
  Visibility: force_output no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: available
  Varpool flags: initialized read-only const-value-known
Flexio_Uart_Ip_apStateStructure/21 (Flexio_Uart_Ip_apStateStructure) @073352d0
  Type: variable definition analyzed
  Visibility: force_output externally_visible no_reorder public
  References: 
  Referring: 
  Availability: available
  Varpool flags:
DevAssert/20 (DevAssert) @06cf0620
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SetRxBuffer/54 Flexio_Uart_Ip_SetRxBuffer/54 Flexio_Uart_Ip_SetTxBuffer/53 Flexio_Uart_Ip_SetTxBuffer/53 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_AbortTransferData/51 Flexio_Uart_Ip_AbortTransferData/51 Flexio_Uart_Ip_AbortTransferData/51 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_AsyncReceive/47 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_GetStatus/45 Flexio_Uart_Ip_GetStatus/45 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_GetBaudRate/42 Flexio_Uart_Ip_GetBaudRate/42 Flexio_Uart_Ip_Init/41 Flexio_Uart_Ip_Init/41 Flexio_Uart_Ip_Init/41 Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_StartReceiveDataUsingDma/40 Flexio_Uart_Ip_StartSendDataUsingDma/39 Flexio_Uart_Ip_StartSendDataUsingDma/39 Flexio_Uart_Ip_ReadData/33 Flexio_Uart_Ip_ReadData/33 Flexio_Uart_Ip_WriteData/30 
  Calls: 
Flexio_Uart_Ip_CheckTimeout/19 (Flexio_Uart_Ip_CheckTimeout) @06cdbd20
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_StopTransfer/29 
  Calls: OsIf_GetElapsed/63 
Flexio_Uart_Ip_StartTimeout/18 (Flexio_Uart_Ip_StartTimeout) @06cdba80
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CompleteReceiveUsingDma/50 Flexio_Uart_Ip_CompleteSendUsingDma/49 Flexio_Uart_Ip_SyncReceive/48 Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_Deinit/43 Flexio_Uart_Ip_StopTransfer/29 
  Calls: OsIf_MicrosToTicks/62 OsIf_GetCounter/61 
Flexio_Uart_Ip_GetShifterInterrupt/17 (Flexio_Uart_Ip_GetShifterInterrupt) @06cdb7e0
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CheckRxOperation/34 Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: 
Flexio_Uart_Ip_GetShifterErrorInterrupt/16 (Flexio_Uart_Ip_GetShifterErrorInterrupt) @06cdb540
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CheckRxOperation/34 
  Calls: 
Flexio_Uart_Ip_GetTimerInterrupt/15 (Flexio_Uart_Ip_GetTimerInterrupt) @06cdb2a0
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CheckTxOperation/31 
  Calls: 
Flexio_Uart_Ip_ReadShifterBuffer/14 (Flexio_Uart_Ip_ReadShifterBuffer) @06cdb000
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ReadData/33 
  Calls: 
Flexio_Uart_Ip_WriteShifterBuffer/13 (Flexio_Uart_Ip_WriteShifterBuffer) @06c81d20
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CheckTxOperation/31 Flexio_Uart_Ip_WriteData/30 
  Calls: 
Flexio_Uart_Ip_SetShifterStartBit/12 (Flexio_Uart_Ip_SetShifterStartBit) @06c81a80
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_CheckTxOperation/31 Flexio_Uart_Ip_StopTransfer/29 
  Calls: 
Flexio_Uart_Ip_SetShifterMode/11 (Flexio_Uart_Ip_SetShifterMode) @06c81700
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_EnableReceiver/38 Flexio_Uart_Ip_StopTransfer/29 Flexio_Uart_Ip_StopTransfer/29 
  Calls: 
Flexio_Uart_Ip_SetTimerMode/10 (Flexio_Uart_Ip_SetTimerMode) @06c81380
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SyncSend/46 Flexio_Uart_Ip_AsyncSend/44 Flexio_Uart_Ip_EnableReceiver/38 Flexio_Uart_Ip_StopTransfer/29 
  Calls: 
Flexio_Uart_Ip_SetPinTimerControl/9 (Flexio_Uart_Ip_SetPinTimerControl) @06c81000
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerTrigger/8 (Flexio_Uart_Ip_SetTimerTrigger) @06c7ea80
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerControl/7 (Flexio_Uart_Ip_SetTimerControl) @06c7e540
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerCondition/6 (Flexio_Uart_Ip_SetTimerCondition) @06c7e1c0
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerStartStopBitConfig/5 (Flexio_Uart_Ip_SetTimerStartStopBitConfig) @06c78d20
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerConfig/4 (Flexio_Uart_Ip_SetTimerConfig) @06c788c0
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetTimerCompare/3 (Flexio_Uart_Ip_SetTimerCompare) @06c78380
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_SetBaudRate/52 Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetPinShifterControl/2 (Flexio_Uart_Ip_SetPinShifterControl) @06c780e0
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetShifterControl/1 (Flexio_Uart_Ip_SetShifterControl) @06c3cb60
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 
Flexio_Uart_Ip_SetShifterConfig/0 (Flexio_Uart_Ip_SetShifterConfig) @06c3c620
  Type: function definition analyzed
  Visibility: no_reorder prevailing_def_ironly
  References: 
  Referring: 
  Availability: local
  Function flags: body local
  Called by: Flexio_Uart_Ip_ConfigureRx/27 Flexio_Uart_Ip_ConfigureTx/26 
  Calls: 

;; Function Flexio_Uart_Ip_SetShifterConfig (Flexio_Uart_Ip_SetShifterConfig, funcdef_no=0, decl_uid=5823, cgraph_uid=1, symbol_order=0)

Flexio_Uart_Ip_SetShifterConfig (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterStartType Start, Flexio_Mcl_Ip_ShifterStopType Stop, Flexio_Mcl_Ip_ShifterSourceType Source)
{
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  long unsigned int _6;
  int _7;
  long unsigned int _8;

  <bb 2> :
  _1 = Start_9(D) & 3;
  _2 = Stop_10(D) << 4;
  _3 = _2 & 48;
  _4 = _1 | _3;
  _5 = Source_11(D) << 8;
  _6 = _5 & 256;
  _7 = (int) Shifter_12(D);
  _8 = _4 | _6;
  Base_14(D)->SHIFTCFG[_7] ={v} _8;
  return;

}



;; Function Flexio_Uart_Ip_SetShifterControl (Flexio_Uart_Ip_SetShifterControl, funcdef_no=1, decl_uid=5830, cgraph_uid=2, symbol_order=1)

Flexio_Uart_Ip_SetShifterControl (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterModeType Mode, uint8 Timer, Flexio_Mcl_Ip_TimerPolarityType TimerPolarity)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  int _5;
  long unsigned int _6;
  int _7;
  long unsigned int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  int _12;
  long unsigned int _13;
  int _14;
  long unsigned int _15;
  long unsigned int _16;
  long unsigned int _17;
  long unsigned int _18;
  long unsigned int _19;
  int _20;
  long unsigned int _21;

  <bb 2> :
  _1 = (int) Shifter_22(D);
  _2 ={v} Base_24(D)->SHIFTCTL[_1];
  _3 = _2 & 4294967288;
  _4 = Mode_25(D) & 7;
  _5 = (int) Shifter_22(D);
  _6 = _3 | _4;
  Base_24(D)->SHIFTCTL[_5] ={v} _6;
  _7 = (int) Shifter_22(D);
  _8 ={v} Base_24(D)->SHIFTCTL[_7];
  _9 = _8 & 4286578687;
  _10 = TimerPolarity_27(D) << 23;
  _11 = _10 & 8388608;
  _12 = (int) Shifter_22(D);
  _13 = _9 | _11;
  Base_24(D)->SHIFTCTL[_12] ={v} _13;
  _14 = (int) Shifter_22(D);
  _15 ={v} Base_24(D)->SHIFTCTL[_14];
  _16 = _15 & 4244635647;
  _17 = (long unsigned int) Timer_29(D);
  _18 = _17 << 24;
  _19 = _18 & 50331648;
  _20 = (int) Shifter_22(D);
  _21 = _16 | _19;
  Base_24(D)->SHIFTCTL[_20] ={v} _21;
  return;

}



;; Function Flexio_Uart_Ip_SetPinShifterControl (Flexio_Uart_Ip_SetPinShifterControl, funcdef_no=2, decl_uid=5837, cgraph_uid=3, symbol_order=2)

Flexio_Uart_Ip_SetPinShifterControl (struct FLEXIO_Type * Base, uint8 Shifter, uint8 Pin, Flexio_Mcl_Ip_PinPolarityType PinPolarity, Flexio_Mcl_Ip_PinConfigType PinConfig)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  int _6;
  long unsigned int _7;
  int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  long unsigned int _13;
  int _14;
  long unsigned int _15;
  int _16;
  long unsigned int _17;
  long unsigned int _18;
  long unsigned int _19;
  long unsigned int _20;
  int _21;
  long unsigned int _22;

  <bb 2> :
  _1 = (int) Shifter_23(D);
  _2 ={v} Base_25(D)->SHIFTCTL[_1];
  _3 = _2 & 4294967167;
  _4 = PinPolarity_26(D) << 7;
  _5 = _4 & 255;
  _6 = (int) Shifter_23(D);
  _7 = _3 | _5;
  Base_25(D)->SHIFTCTL[_6] ={v} _7;
  _8 = (int) Shifter_23(D);
  _9 ={v} Base_25(D)->SHIFTCTL[_8];
  _10 = _9 & 4294965503;
  _11 = (long unsigned int) Pin_28(D);
  _12 = _11 << 8;
  _13 = _12 & 1792;
  _14 = (int) Shifter_23(D);
  _15 = _10 | _13;
  Base_25(D)->SHIFTCTL[_14] ={v} _15;
  _16 = (int) Shifter_23(D);
  _17 ={v} Base_25(D)->SHIFTCTL[_16];
  _18 = _17 & 4294770687;
  _19 = PinConfig_30(D) << 16;
  _20 = _19 & 196608;
  _21 = (int) Shifter_23(D);
  _22 = _18 | _20;
  Base_25(D)->SHIFTCTL[_21] ={v} _22;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerCompare (Flexio_Uart_Ip_SetTimerCompare, funcdef_no=3, decl_uid=5842, cgraph_uid=4, symbol_order=3)

Flexio_Uart_Ip_SetTimerCompare (struct FLEXIO_Type * Base, uint8 Timer, uint16 Value)
{
  int _1;
  long unsigned int _2;

  <bb 2> :
  _1 = (int) Timer_3(D);
  _2 = (long unsigned int) Value_4(D);
  Base_6(D)->TIMCMP[_1] ={v} _2;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerConfig (Flexio_Uart_Ip_SetTimerConfig, funcdef_no=4, decl_uid=5849, cgraph_uid=5, symbol_order=4)

Flexio_Uart_Ip_SetTimerConfig (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerResetType Reset, Flexio_Uart_Ip_TimerDecrementType Decrement, Flexio_Mcl_Ip_TimerOutputType Output)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  int _6;
  long unsigned int _7;
  int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  int _13;
  long unsigned int _14;
  int _15;
  long unsigned int _16;
  long unsigned int _17;
  long unsigned int _18;
  long unsigned int _19;
  int _20;
  long unsigned int _21;

  <bb 2> :
  _1 = (int) Timer_22(D);
  _2 ={v} Base_24(D)->TIMCFG[_1];
  _3 = _2 & 4294508543;
  _4 = Reset_25(D) << 16;
  _5 = _4 & 458752;
  _6 = (int) Timer_22(D);
  _7 = _3 | _5;
  Base_24(D)->TIMCFG[_6] ={v} _7;
  _8 = (int) Timer_22(D);
  _9 ={v} Base_24(D)->TIMCFG[_8];
  _10 = _9 & 4291821567;
  _11 = Decrement_27(D) << 20;
  _12 = _11 & 3145728;
  _13 = (int) Timer_22(D);
  _14 = _10 | _12;
  Base_24(D)->TIMCFG[_13] ={v} _14;
  _15 = (int) Timer_22(D);
  _16 ={v} Base_24(D)->TIMCFG[_15];
  _17 = _16 & 4244635647;
  _18 = Output_29(D) << 24;
  _19 = _18 & 50331648;
  _20 = (int) Timer_22(D);
  _21 = _17 | _19;
  Base_24(D)->TIMCFG[_20] ={v} _21;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerStartStopBitConfig (Flexio_Uart_Ip_SetTimerStartStopBitConfig, funcdef_no=5, decl_uid=5855, cgraph_uid=6, symbol_order=5)

Flexio_Uart_Ip_SetTimerStartStopBitConfig (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerStartType Start, Flexio_Mcl_Ip_TimerStopType Stop)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  int _6;
  long unsigned int _7;
  int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  int _13;
  long unsigned int _14;

  <bb 2> :
  _1 = (int) Timer_15(D);
  _2 ={v} Base_17(D)->TIMCFG[_1];
  _3 = _2 & 4294967293;
  _4 = Start_18(D) << 1;
  _5 = _4 & 2;
  _6 = (int) Timer_15(D);
  _7 = _3 | _5;
  Base_17(D)->TIMCFG[_6] ={v} _7;
  _8 = (int) Timer_15(D);
  _9 ={v} Base_17(D)->TIMCFG[_8];
  _10 = _9 & 4294967247;
  _11 = Stop_20(D) << 4;
  _12 = _11 & 48;
  _13 = (int) Timer_15(D);
  _14 = _10 | _12;
  Base_17(D)->TIMCFG[_13] ={v} _14;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerCondition (Flexio_Uart_Ip_SetTimerCondition, funcdef_no=6, decl_uid=5861, cgraph_uid=7, symbol_order=6)

Flexio_Uart_Ip_SetTimerCondition (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerEnableType Enable, Flexio_Mcl_Ip_TimerDisableType Disable)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  int _6;
  long unsigned int _7;
  int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  int _13;
  long unsigned int _14;

  <bb 2> :
  _1 = (int) Timer_15(D);
  _2 ={v} Base_17(D)->TIMCFG[_1];
  _3 = _2 & 4294965503;
  _4 = Enable_18(D) << 8;
  _5 = _4 & 1792;
  _6 = (int) Timer_15(D);
  _7 = _3 | _5;
  Base_17(D)->TIMCFG[_6] ={v} _7;
  _8 = (int) Timer_15(D);
  _9 ={v} Base_17(D)->TIMCFG[_8];
  _10 = _9 & 4294938623;
  _11 = Disable_20(D) << 12;
  _12 = _11 & 28672;
  _13 = (int) Timer_15(D);
  _14 = _10 | _12;
  Base_17(D)->TIMCFG[_13] ={v} _14;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerControl (Flexio_Uart_Ip_SetTimerControl, funcdef_no=7, decl_uid=5866, cgraph_uid=8, symbol_order=7)

Flexio_Uart_Ip_SetTimerControl (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerModeType Mode)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  int _5;
  long unsigned int _6;

  <bb 2> :
  _1 = (int) Timer_7(D);
  _2 ={v} Base_9(D)->TIMCTL[_1];
  _3 = _2 & 4294967292;
  _4 = Mode_10(D) & 3;
  _5 = (int) Timer_7(D);
  _6 = _3 | _4;
  Base_9(D)->TIMCTL[_5] ={v} _6;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerTrigger (Flexio_Uart_Ip_SetTimerTrigger, funcdef_no=8, decl_uid=5873, cgraph_uid=9, symbol_order=8)

Flexio_Uart_Ip_SetTimerTrigger (struct FLEXIO_Type * Base, uint8 Timer, uint8 Trigger, Flexio_Mcl_Ip_TriggerPolarityType TriggerPolarity, Flexio_Mcl_Ip_TriggerSourceType TriggerSource)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  int _6;
  long unsigned int _7;
  int _8;
  long unsigned int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  int _13;
  long unsigned int _14;
  int _15;
  long unsigned int _16;
  long unsigned int _17;
  long unsigned int _18;
  long unsigned int _19;
  long unsigned int _20;
  int _21;
  long unsigned int _22;

  <bb 2> :
  _1 = (int) Timer_23(D);
  _2 ={v} Base_25(D)->TIMCTL[_1];
  _3 = _2 & 4290772991;
  _4 = TriggerSource_26(D) << 22;
  _5 = _4 & 4194304;
  _6 = (int) Timer_23(D);
  _7 = _3 | _5;
  Base_25(D)->TIMCTL[_6] ={v} _7;
  _8 = (int) Timer_23(D);
  _9 ={v} Base_25(D)->TIMCTL[_8];
  _10 = _9 & 4286578687;
  _11 = TriggerPolarity_28(D) << 23;
  _12 = _11 & 8388608;
  _13 = (int) Timer_23(D);
  _14 = _10 | _12;
  Base_25(D)->TIMCTL[_13] ={v} _14;
  _15 = (int) Timer_23(D);
  _16 ={v} Base_25(D)->TIMCTL[_15];
  _17 = _16 & 4043309055;
  _18 = (long unsigned int) Trigger_30(D);
  _19 = _18 << 24;
  _20 = _19 & 251658240;
  _21 = (int) Timer_23(D);
  _22 = _17 | _20;
  Base_25(D)->TIMCTL[_21] ={v} _22;
  return;

}



;; Function Flexio_Uart_Ip_SetPinTimerControl (Flexio_Uart_Ip_SetPinTimerControl, funcdef_no=9, decl_uid=5880, cgraph_uid=10, symbol_order=9)

Flexio_Uart_Ip_SetPinTimerControl (struct FLEXIO_Type * Base, uint8 Timer, uint8 Pin, Flexio_Mcl_Ip_PinPolarityType PinPolarity, Flexio_Mcl_Ip_PinConfigType PinConfig)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  long unsigned int _5;
  long unsigned int _6;
  int _7;
  long unsigned int _8;
  int _9;
  long unsigned int _10;
  long unsigned int _11;
  long unsigned int _12;
  long unsigned int _13;
  int _14;
  long unsigned int _15;
  int _16;
  long unsigned int _17;
  long unsigned int _18;
  long unsigned int _19;
  long unsigned int _20;
  int _21;
  long unsigned int _22;

  <bb 2> :
  _1 = (int) Timer_23(D);
  _2 ={v} Base_25(D)->TIMCTL[_1];
  _3 = _2 & 4294965503;
  _4 = (long unsigned int) Pin_26(D);
  _5 = _4 << 8;
  _6 = _5 & 1792;
  _7 = (int) Timer_23(D);
  _8 = _3 | _6;
  Base_25(D)->TIMCTL[_7] ={v} _8;
  _9 = (int) Timer_23(D);
  _10 ={v} Base_25(D)->TIMCTL[_9];
  _11 = _10 & 4294967167;
  _12 = PinPolarity_28(D) << 7;
  _13 = _12 & 255;
  _14 = (int) Timer_23(D);
  _15 = _11 | _13;
  Base_25(D)->TIMCTL[_14] ={v} _15;
  _16 = (int) Timer_23(D);
  _17 ={v} Base_25(D)->TIMCTL[_16];
  _18 = _17 & 4294770687;
  _19 = PinConfig_30(D) << 16;
  _20 = _19 & 196608;
  _21 = (int) Timer_23(D);
  _22 = _18 | _20;
  Base_25(D)->TIMCTL[_21] ={v} _22;
  return;

}



;; Function Flexio_Uart_Ip_SetTimerMode (Flexio_Uart_Ip_SetTimerMode, funcdef_no=10, decl_uid=5885, cgraph_uid=11, symbol_order=10)

Flexio_Uart_Ip_SetTimerMode (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerModeType Mode)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  int _5;
  long unsigned int _6;

  <bb 2> :
  _1 = (int) Timer_7(D);
  _2 ={v} Base_9(D)->TIMCTL[_1];
  _3 = _2 & 4294967292;
  _4 = Mode_10(D) & 3;
  _5 = (int) Timer_7(D);
  _6 = _3 | _4;
  Base_9(D)->TIMCTL[_5] ={v} _6;
  return;

}



;; Function Flexio_Uart_Ip_SetShifterMode (Flexio_Uart_Ip_SetShifterMode, funcdef_no=11, decl_uid=5890, cgraph_uid=12, symbol_order=11)

Flexio_Uart_Ip_SetShifterMode (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterModeType Mode)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  int _5;
  long unsigned int _6;

  <bb 2> :
  _1 = (int) Shifter_7(D);
  _2 ={v} Base_9(D)->SHIFTCTL[_1];
  _3 = _2 & 4294967288;
  _4 = Mode_10(D) & 7;
  _5 = (int) Shifter_7(D);
  _6 = _3 | _4;
  Base_9(D)->SHIFTCTL[_5] ={v} _6;
  return;

}



;; Function Flexio_Uart_Ip_SetShifterStartBit (Flexio_Uart_Ip_SetShifterStartBit, funcdef_no=12, decl_uid=5895, cgraph_uid=13, symbol_order=12)

Flexio_Uart_Ip_SetShifterStartBit (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterStartType Start)
{
  int _1;
  long unsigned int _2;
  long unsigned int _3;
  long unsigned int _4;
  int _5;
  long unsigned int _6;

  <bb 2> :
  _1 = (int) Shifter_7(D);
  _2 ={v} Base_9(D)->SHIFTCFG[_1];
  _3 = _2 & 4294967292;
  _4 = Start_10(D) & 3;
  _5 = (int) Shifter_7(D);
  _6 = _3 | _4;
  Base_9(D)->SHIFTCFG[_5] ={v} _6;
  return;

}



;; Function Flexio_Uart_Ip_WriteShifterBuffer (Flexio_Uart_Ip_WriteShifterBuffer, funcdef_no=13, decl_uid=5900, cgraph_uid=14, symbol_order=13)

Flexio_Uart_Ip_WriteShifterBuffer (struct FLEXIO_Type * Base, uint8 Shifter, uint32 Value)
{
  int _1;

  <bb 2> :
  _1 = (int) Shifter_2(D);
  Base_4(D)->SHIFTBUF[_1] ={v} Value_5(D);
  return;

}



;; Function Flexio_Uart_Ip_ReadShifterBuffer (Flexio_Uart_Ip_ReadShifterBuffer, funcdef_no=14, decl_uid=5904, cgraph_uid=15, symbol_order=14)

Flexio_Uart_Ip_ReadShifterBuffer (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 Data;
  uint32 D.6848;
  int _1;
  uint32 _6;

  <bb 2> :
  _1 = (int) Shifter_2(D);
  Data_5 ={v} Base_4(D)->SHIFTBUF[_1];
  _6 = Data_5;

  <bb 3> :
<L0>:
  return _6;

}



;; Function Flexio_Uart_Ip_GetTimerInterrupt (Flexio_Uart_Ip_GetTimerInterrupt, funcdef_no=15, decl_uid=5909, cgraph_uid=16, symbol_order=15)

Flexio_Uart_Ip_GetTimerInterrupt (const struct FLEXIO_Type * Base, uint8 Timer)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6831;
  int _1;
  long unsigned int _2;
  boolean _11;

  <bb 2> :
  RegValue_6 ={v} Base_5(D)->TIMIEN;
  _1 = (int) Timer_7(D);
  _2 = RegValue_6 >> _1;
  RegValue_8 = _2 & 1;
  if (RegValue_8 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus_10 = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus_9 = 0;

  <bb 5> :
  # RetStatus_3 = PHI <RetStatus_10(3), RetStatus_9(4)>
  _11 = RetStatus_3;

  <bb 6> :
<L3>:
  return _11;

}



;; Function Flexio_Uart_Ip_GetShifterErrorInterrupt (Flexio_Uart_Ip_GetShifterErrorInterrupt, funcdef_no=16, decl_uid=5915, cgraph_uid=17, symbol_order=16)

Flexio_Uart_Ip_GetShifterErrorInterrupt (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6879;
  int _1;
  long unsigned int _2;
  boolean _11;

  <bb 2> :
  RegValue_6 ={v} Base_5(D)->SHIFTEIEN;
  _1 = (int) Shifter_7(D);
  _2 = RegValue_6 >> _1;
  RegValue_8 = _2 & 1;
  if (RegValue_8 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus_10 = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus_9 = 0;

  <bb 5> :
  # RetStatus_3 = PHI <RetStatus_10(3), RetStatus_9(4)>
  _11 = RetStatus_3;

  <bb 6> :
<L3>:
  return _11;

}



;; Function Flexio_Uart_Ip_GetShifterInterrupt (Flexio_Uart_Ip_GetShifterInterrupt, funcdef_no=17, decl_uid=5921, cgraph_uid=18, symbol_order=17)

Flexio_Uart_Ip_GetShifterInterrupt (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6836;
  int _1;
  long unsigned int _2;
  boolean _11;

  <bb 2> :
  RegValue_6 ={v} Base_5(D)->SHIFTSIEN;
  _1 = (int) Shifter_7(D);
  _2 = RegValue_6 >> _1;
  RegValue_8 = _2 & 1;
  if (RegValue_8 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus_10 = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus_9 = 0;

  <bb 5> :
  # RetStatus_3 = PHI <RetStatus_10(3), RetStatus_9(4)>
  _11 = RetStatus_3;

  <bb 6> :
<L3>:
  return _11;

}



;; Function Flexio_Uart_Ip_StartTimeout (Flexio_Uart_Ip_StartTimeout, funcdef_no=18, decl_uid=5929, cgraph_uid=19, symbol_order=18)

Flexio_Uart_Ip_StartTimeout (uint32 * StartTimeOut, uint32 * TimeoutTicksOut, uint32 TimeoutUs, OsIf_CounterType OsifCounter)
{
  long unsigned int _1;
  long unsigned int _2;

  <bb 2> :
  _1 = OsIf_GetCounter (OsifCounter_4(D));
  *StartTimeOut_6(D) = _1;
  _2 = OsIf_MicrosToTicks (TimeoutUs_8(D), OsifCounter_4(D));
  *TimeoutTicksOut_10(D) = _2;
  return;

}



;; Function Flexio_Uart_Ip_CheckTimeout (Flexio_Uart_Ip_CheckTimeout, funcdef_no=19, decl_uid=5935, cgraph_uid=20, symbol_order=19)

Flexio_Uart_Ip_CheckTimeout (uint32 * StartTime, uint32 * ElapsedTicks, uint32 TimeoutTicks, OsIf_CounterType OsifCounter)
{
  uint32 CurrentElapsedTicks;
  boolean D.6794;
  long unsigned int _1;
  long unsigned int _2;
  long unsigned int _3;
  boolean _12;

  <bb 2> :
  CurrentElapsedTicks_8 = OsIf_GetElapsed (StartTime_5(D), OsifCounter_6(D));
  _1 = *ElapsedTicks_9(D);
  _2 = CurrentElapsedTicks_8 + _1;
  *ElapsedTicks_9(D) = _2;
  _3 = *ElapsedTicks_9(D);
  _12 = TimeoutTicks_11(D) <= _3;

  <bb 3> :
<L0>:
  return _12;

}



;; Function DevAssert (DevAssert, funcdef_no=20, decl_uid=6049, cgraph_uid=21, symbol_order=20)

DevAssert (volatile boolean x)
{
  _Bool x.1_1;

  <bb 2> :
  x.1_1 ={v} x;
  if (x.1_1 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  goto <bb 3>; [INV]

  <bb 4> :
  return;

}



;; Function Flexio_Uart_Ip_IrqHandler (Flexio_Uart_Ip_IrqHandler, funcdef_no=21, decl_uid=5942, cgraph_uid=22, symbol_order=25)

Flexio_Uart_Ip_IrqHandler (uint8 Channel, uint8 ShifterMaskFlag, uint8 ShifterErrorMaskFlag, uint8 TimerMaskFlag)
{
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  int _1;
  <unnamed type> _2;

  <bb 2> :
  _1 = (int) Channel_4(D);
  UartUserCfg_6 = Flexio_Uart_Ip_apUserConfig[_1];
  Base_7 = 1074110464B;
  if (UartUserCfg_6 == 0B)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base_7, Channel_4(D));
  Flexio_Mcl_Ip_ClearShifterStatus (Base_7, Channel_4(D));
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base_7, Channel_4(D));
  goto <bb 7>; [INV]

  <bb 4> :
  _2 = UartUserCfg_6->Direction;
  if (_2 == 1)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Uart_Ip_CheckTxOperation (Channel_4(D), ShifterMaskFlag_8(D), TimerMaskFlag_11(D));
  goto <bb 7>; [INV]

  <bb 6> :
  Flexio_Uart_Ip_CheckRxOperation (Channel_4(D), ShifterMaskFlag_8(D), ShifterErrorMaskFlag_9(D));

  <bb 7> :
  return;

}



;; Function Flexio_Uart_Ip_ConfigureTx (Flexio_Uart_Ip_ConfigureTx, funcdef_no=22, decl_uid=6462, cgraph_uid=23, symbol_order=26)

Flexio_Uart_Ip_ConfigureTx (const uint8 Channel, const Flexio_Uart_Ip_BitCountPerCharType BitCount, const uint8 Divider, const uint8 DataPin, const Flexio_Uart_Ip_TimerDecrementType TimerDec)
{
  uint16 Bits;
  struct FLEXIO_Type * Base;
  short unsigned int _1;
  short unsigned int _2;
  short unsigned int _3;
  short unsigned int _4;
  short unsigned int _5;
  unsigned char _6;
  unsigned char _7;

  <bb 2> :
  Base_8 = 1074110464B;
  Bits_10 = (uint16) BitCount_9(D);
  Flexio_Uart_Ip_SetShifterConfig (Base_8, Channel_12(D), 2, 3, 0);
  Flexio_Uart_Ip_SetShifterControl (Base_8, Channel_12(D), 2, Channel_12(D), 0);
  Flexio_Uart_Ip_SetPinShifterControl (Base_8, Channel_12(D), DataPin_15(D), 0, 3);
  _1 = Bits_10 << 1;
  _2 = _1 + 65535;
  _3 = _2 << 8;
  _4 = (short unsigned int) Divider_17(D);
  _5 = _3 + _4;
  Flexio_Uart_Ip_SetTimerCompare (Base_8, Channel_12(D), _5);
  Flexio_Uart_Ip_SetTimerConfig (Base_8, Channel_12(D), 0, TimerDec_19(D), 0);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base_8, Channel_12(D), 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base_8, Channel_12(D), 2, 2);
  Flexio_Uart_Ip_SetTimerControl (Base_8, Channel_12(D), 0);
  _6 = Channel_12(D) << 2;
  _7 = _6 + 1;
  Flexio_Uart_Ip_SetTimerTrigger (Base_8, Channel_12(D), _7, 1, 1);
  Flexio_Uart_Ip_SetPinTimerControl (Base_8, Channel_12(D), 0, 0, 0);
  return;

}



;; Function Flexio_Uart_Ip_ConfigureRx (Flexio_Uart_Ip_ConfigureRx, funcdef_no=23, decl_uid=6468, cgraph_uid=24, symbol_order=27)

Flexio_Uart_Ip_ConfigureRx (const uint8 Channel, const Flexio_Uart_Ip_BitCountPerCharType BitCount, const uint8 Divider, const uint8 DataPin, const Flexio_Uart_Ip_TimerDecrementType TimerDec)
{
  uint16 Bits;
  struct FLEXIO_Type * Base;
  short unsigned int _1;
  short unsigned int _2;
  short unsigned int _3;
  short unsigned int _4;
  short unsigned int _5;

  <bb 2> :
  Base_6 = 1074110464B;
  Bits_8 = (uint16) BitCount_7(D);
  Flexio_Uart_Ip_SetShifterConfig (Base_6, Channel_10(D), 2, 3, 0);
  Flexio_Uart_Ip_SetShifterControl (Base_6, Channel_10(D), 0, Channel_10(D), 1);
  Flexio_Uart_Ip_SetPinShifterControl (Base_6, Channel_10(D), DataPin_13(D), 0, 0);
  _1 = Bits_8 << 1;
  _2 = _1 + 65535;
  _3 = _2 << 8;
  _4 = (short unsigned int) Divider_15(D);
  _5 = _3 + _4;
  Flexio_Uart_Ip_SetTimerCompare (Base_6, Channel_10(D), _5);
  Flexio_Uart_Ip_SetTimerConfig (Base_6, Channel_10(D), 4, TimerDec_17(D), 2);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base_6, Channel_10(D), 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base_6, Channel_10(D), 4, 2);
  Flexio_Uart_Ip_SetTimerControl (Base_6, Channel_10(D), 0);
  Flexio_Uart_Ip_SetTimerTrigger (Base_6, Channel_10(D), 0, 0, 0);
  Flexio_Uart_Ip_SetPinTimerControl (Base_6, Channel_10(D), DataPin_13(D), 1, 0);
  return;

}



;; Function Flexio_Uart_Ip_EndTransfer (Flexio_Uart_Ip_EndTransfer, funcdef_no=24, decl_uid=6484, cgraph_uid=25, symbol_order=28)

Flexio_Uart_Ip_EndTransfer (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  <unnamed type> _3;
  int _4;
  unsigned int _5;
  unsigned char _6;
  int _7;
  unsigned int _8;
  unsigned char _9;
  int _10;
  unsigned int _11;
  unsigned char _12;

  <bb 2> :
  _1 = (int) Channel_14(D);
  UartState_16 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_14(D);
  UartUserCfg_17 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_18 = 1074110464B;
  _3 = UartUserCfg_17->DriverType;
  switch (_3) <default: <L2> [INV], case 0: <L0> [INV], case 1: <L1> [INV]>

  <bb 3> :
<L0>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_14(D), 0);
  _4 = (int) Channel_14(D);
  _5 = 1 << _4;
  _6 = (unsigned char) _5;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_18, _6, 0);
  goto <bb 6>; [INV]

  <bb 4> :
<L1>:
  _7 = (int) Channel_14(D);
  _8 = 1 << _7;
  _9 = (unsigned char) _8;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_18, _9, 0);
  _10 = (int) Channel_14(D);
  _11 = 1 << _10;
  _12 = (unsigned char) _11;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base_18, _12, 0);
  goto <bb 6>; [INV]

  <bb 5> :
<L2>:

  <bb 6> :
  UartState_16->RemainingBytes ={v} 0;
  UartState_16->DriverIdle ={v} 0;
  return;

}



;; Function Flexio_Uart_Ip_StopTransfer (Flexio_Uart_Ip_StopTransfer, funcdef_no=25, decl_uid=6470, cgraph_uid=26, symbol_order=29)

Flexio_Uart_Ip_StopTransfer (const uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  <unnamed type> _3;
  _Bool _4;
  _Bool _5;
  long unsigned int TimeoutTicks.0_6;
  _Bool _7;
  _Bool _8;
  <unnamed type> _9;

  <bb 2> :
  _1 = (int) Channel_13(D);
  UartUserCfg_15 = Flexio_Uart_Ip_apUserConfig[_1];
  Base_16 = 1074110464B;
  ElapsedTicks = 0;
  _2 = (int) Channel_13(D);
  UartState_18 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  Flexio_Uart_Ip_EndTransfer (Channel_13(D));
  _3 ={v} UartState_18->Status;
  if (_3 == 516)
    goto <bb 3>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 3> :
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 4> :
  _4 = Flexio_Mcl_Ip_GetTimerStatus (Base_16, Channel_13(D));
  _5 = ~_4;
  if (_5 != 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  TimeoutTicks.0_6 = TimeoutTicks;
  _7 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.0_6, 0);
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 6> :
  Flexio_Uart_Ip_SetTimerMode (Base_16, Channel_13(D), 0);
  Flexio_Uart_Ip_SetShifterMode (Base_16, Channel_13(D), 0);
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base_16, Channel_13(D));
  _9 = UartUserCfg_15->Direction;
  if (_9 == 1)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  Flexio_Uart_Ip_SetShifterStartBit (Base_16, Channel_13(D), 2);
  Flexio_Uart_Ip_SetShifterMode (Base_16, Channel_13(D), 2);

  <bb 8> :
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};
  return;

}



;; Function Flexio_Uart_Ip_WriteData (Flexio_Uart_Ip_WriteData, funcdef_no=26, decl_uid=6486, cgraph_uid=27, symbol_order=30)

Flexio_Uart_Ip_WriteData (const uint8 Channel)
{
  uint32 Data32b;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  const uint8 * _3;
  _Bool _4;
  <unnamed type> _5;
  const uint8 * _6;
  unsigned char _7;
  const uint8 * _8;
  const uint8 * _9;
  long unsigned int _10;
  long unsigned int _11;

  <bb 2> :
  Data32b_14 = 0;
  _1 = (int) Channel_15(D);
  UartUserCfg_17 = Flexio_Uart_Ip_apUserConfig[_1];
  _2 = (int) Channel_15(D);
  UartState_18 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = UartState_18->TxData;
  _4 = _3 != 0B;
  DevAssert (_4);
  Base_20 = 1074110464B;
  _5 = UartUserCfg_17->BitCount;
  if (_5 == 8)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _6 = UartState_18->TxData;
  _7 ={v} *_6;
  Data32b_21 = (uint32) _7;
  _8 = UartState_18->TxData;
  _9 = _8 + 1;
  UartState_18->TxData = _9;
  _10 ={v} UartState_18->RemainingBytes;
  _11 = _10 + 4294967295;
  UartState_18->RemainingBytes ={v} _11;

  <bb 4> :
  # Data32b_12 = PHI <Data32b_14(2), Data32b_21(3)>
  Flexio_Uart_Ip_WriteShifterBuffer (Base_20, Channel_15(D), Data32b_12);
  return;

}



;; Function Flexio_Uart_Ip_CheckTxOperation (Flexio_Uart_Ip_CheckTxOperation, funcdef_no=27, decl_uid=6474, cgraph_uid=28, symbol_order=31)

Flexio_Uart_Ip_CheckTxOperation (const uint8 Channel, const uint8 ShifterMaskFlag, const uint8 TimerMaskFlag)
{
  boolean IsReturn;
  uint32 ResourceMask;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  int _3;
  long unsigned int _4;
  long unsigned int _5;
  long unsigned int _6;
  _Bool _7;
  _Bool _8;
  _Bool _9;
  unsigned char _10;
  unsigned char _11;
  unsigned char _12;
  unsigned char _13;
  <unnamed type> _14;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _15;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _16;
  long unsigned int _17;
  void * _18;
  _Bool _19;
  long unsigned int _20;
  long unsigned int _21;
  long unsigned int _22;
  _Bool _23;
  _Bool _24;

  <bb 2> :
  _1 = (int) Channel_29(D);
  UartState_31 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_29(D);
  UartUserCfg_32 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_33 = 1074110464B;
  _3 = (int) Channel_29(D);
  ResourceMask_34 = 1 << _3;
  IsReturn_35 = 0;
  _4 ={v} UartState_31->RemainingBytes;
  if (_4 == 0)
    goto <bb 3>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 3> :
  _5 = (long unsigned int) TimerMaskFlag_41(D);
  _6 = ResourceMask_34 & _5;
  if (_6 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 4> :
  _7 = Flexio_Uart_Ip_GetTimerInterrupt (Base_33, Channel_29(D));
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base_33, Channel_29(D));
  IsReturn_44 = 1;

  <bb 6> :
  # IsReturn_25 = PHI <IsReturn_35(4), IsReturn_44(5)>
  _9 = ~IsReturn_25;
  if (_9 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 7> :
  _10 = UartState_31->TxFlush;
  _11 = _10;
  _12 = _11 + 255;
  UartState_31->TxFlush = _12;
  _13 = UartState_31->TxFlush;
  if (_13 == 0)
    goto <bb 8>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 8> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base_33, Channel_29(D));
  _14 ={v} UartState_31->Status;
  if (_14 == 2)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  UartState_31->Status ={v} 0;

  <bb 10> :
  Flexio_Uart_Ip_StopTransfer (Channel_29(D));
  _15 = UartUserCfg_32->Callback;
  if (_15 != 0B)
    goto <bb 11>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 11> :
  _16 = UartUserCfg_32->Callback;
  _17 = (long unsigned int) Channel_29(D);
  _18 = UartUserCfg_32->CallbackParam;
  _16 (_17, 2, _18);
  goto <bb 19>; [INV]

  <bb 12> :
  _19 = Flexio_Mcl_Ip_GetShifterStatus (Base_33, Channel_29(D));
  if (_19 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 13> :
  Flexio_Uart_Ip_SetShifterStartBit (Base_33, Channel_29(D), 3);
  Flexio_Uart_Ip_WriteShifterBuffer (Base_33, Channel_29(D), 4294967295);
  goto <bb 19>; [INV]

  <bb 14> :
  _20 = (long unsigned int) ShifterMaskFlag_36(D);
  _21 = ResourceMask_34 & _20;
  if (_21 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 15> :
  _22 ={v} UartState_31->RemainingBytes;
  if (_22 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 16> :
  _23 = Flexio_Uart_Ip_GetShifterInterrupt (Base_33, Channel_29(D));
  _24 = ~_23;
  if (_24 != 0)
    goto <bb 17>; [INV]
  else
    goto <bb 18>; [INV]

  <bb 17> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base_33, Channel_29(D));
  goto <bb 19>; [INV]

  <bb 18> :
  Flexio_Uart_Ip_WriteData (Channel_29(D));
  Flexio_Uart_Ip_CheckCompleteTransferData (Channel_29(D));

  <bb 19> :
  return;

}



;; Function Flexio_Uart_Ip_CheckCompleteTransferData (Flexio_Uart_Ip_CheckCompleteTransferData, funcdef_no=28, decl_uid=6496, cgraph_uid=29, symbol_order=32)

Flexio_Uart_Ip_CheckCompleteTransferData (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  long unsigned int _3;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _4;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _5;
  long unsigned int _6;
  void * _7;
  long unsigned int _8;
  <unnamed type> _9;
  int _10;
  unsigned int _11;
  unsigned char _12;
  int _13;
  unsigned int _14;
  unsigned char _15;

  <bb 2> :
  _1 = (int) Channel_18(D);
  UartState_20 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_18(D);
  UartUserCfg_21 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_22 = 1074110464B;
  _3 ={v} UartState_20->RemainingBytes;
  if (_3 == 0)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _4 = UartUserCfg_21->Callback;
  if (_4 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _5 = UartUserCfg_21->Callback;
  _6 = (long unsigned int) Channel_18(D);
  _7 = UartUserCfg_21->CallbackParam;
  _5 (_6, 1, _7);

  <bb 5> :
  _8 ={v} UartState_20->RemainingBytes;
  if (_8 == 0)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base_22, Channel_18(D));
  _9 = UartUserCfg_21->DriverType;
  if (_9 == 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _10 = (int) Channel_18(D);
  _11 = 1 << _10;
  _12 = (unsigned char) _11;
  Flexio_Mcl_Ip_SetShifterInterrupt (Base_22, _12, 0);
  _13 = (int) Channel_18(D);
  _14 = 1 << _13;
  _15 = (unsigned char) _14;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_22, _15, 1);

  <bb 8> :
  return;

}



;; Function Flexio_Uart_Ip_ReadData (Flexio_Uart_Ip_ReadData, funcdef_no=29, decl_uid=6476, cgraph_uid=30, symbol_order=33)

Flexio_Uart_Ip_ReadData (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  uint32 Data32b;
  const struct FLEXIO_Type * Base;
  int _1;
  int _2;
  long unsigned int _3;
  _Bool _4;
  volatile uint8 * _5;
  _Bool _6;
  <unnamed type> _7;
  long unsigned int _8;
  <unnamed type> _9;
  volatile uint8 * _10;
  unsigned char _11;
  volatile uint8 * _12;
  volatile uint8 * _13;
  long unsigned int _14;
  long unsigned int _15;

  <bb 2> :
  _1 = (int) Channel_17(D);
  UartState_19 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_17(D);
  UartUserCfg_20 = Flexio_Uart_Ip_apUserConfig[_2];
  _3 ={v} UartState_19->RemainingBytes;
  _4 = _3 != 0;
  DevAssert (_4);
  _5 = UartState_19->RxData;
  _6 = _5 != 0B;
  DevAssert (_6);
  Base_23 = 1074110464B;
  Data32b_25 = Flexio_Uart_Ip_ReadShifterBuffer (Base_23, Channel_17(D));
  _7 = UartUserCfg_20->BitCount;
  _8 = 32 - _7;
  Data32b_26 = Data32b_25 >> _8;
  _9 = UartUserCfg_20->BitCount;
  if (_9 == 8)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _10 = UartState_19->RxData;
  _11 = (unsigned char) Data32b_26;
  *_10 ={v} _11;
  _12 = UartState_19->RxData;
  _13 = _12 + 1;
  UartState_19->RxData = _13;
  _14 ={v} UartState_19->RemainingBytes;
  _15 = _14 + 4294967295;
  UartState_19->RemainingBytes ={v} _15;

  <bb 4> :
  return;

}



;; Function Flexio_Uart_Ip_CheckRxOperation (Flexio_Uart_Ip_CheckRxOperation, funcdef_no=30, decl_uid=6480, cgraph_uid=31, symbol_order=34)

Flexio_Uart_Ip_CheckRxOperation (const uint8 Channel, const uint8 ShifterMaskFlag, const uint8 ShifterErrMaskFlag)
{
  boolean IsReturn;
  uint32 ResourceMask;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  int _1;
  int _2;
  int _3;
  long unsigned int _4;
  long unsigned int _5;
  _Bool _6;
  _Bool _7;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _8;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _9;
  long unsigned int _10;
  void * _11;
  long unsigned int _12;
  long unsigned int _13;
  _Bool _14;
  _Bool _15;
  long unsigned int _16;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _17;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _18;
  long unsigned int _19;
  void * _20;
  long unsigned int _21;
  _Bool _22;
  <unnamed type> _23;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _24;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _25;
  long unsigned int _26;
  void * _27;

  <bb 2> :
  _1 = (int) Channel_32(D);
  UartState_34 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_32(D);
  UartUserCfg_35 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_36 = 1074110464B;
  _3 = (int) Channel_32(D);
  ResourceMask_37 = 1 << _3;
  IsReturn_38 = 0;
  _4 = (long unsigned int) ShifterErrMaskFlag_39(D);
  _5 = ResourceMask_37 & _4;
  if (_5 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 3> :
  _6 = Flexio_Uart_Ip_GetShifterErrorInterrupt (Base_36, Channel_32(D));
  _7 = ~_6;
  if (_7 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base_36, Channel_32(D));
  IsReturn_51 = 1;
  goto <bb 13>; [INV]

  <bb 5> :
  UartState_34->Status ={v} 514;
  UartState_34->RemainingBytes ={v} 0;
  _8 = UartUserCfg_35->Callback;
  if (_8 != 0B)
    goto <bb 6>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 6> :
  _9 = UartUserCfg_35->Callback;
  _10 = (long unsigned int) Channel_32(D);
  _11 = UartUserCfg_35->CallbackParam;
  _9 (_10, 3, _11);
  goto <bb 13>; [INV]

  <bb 7> :
  _12 = (long unsigned int) ShifterMaskFlag_40(D);
  _13 = ResourceMask_37 & _12;
  if (_13 != 0)
    goto <bb 8>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 8> :
  _14 = Flexio_Uart_Ip_GetShifterInterrupt (Base_36, Channel_32(D));
  _15 = ~_14;
  if (_15 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base_36, Channel_32(D));
  IsReturn_45 = 1;
  goto <bb 13>; [INV]

  <bb 10> :
  Flexio_Uart_Ip_ReadData (Channel_32(D));
  _16 ={v} UartState_34->RemainingBytes;
  if (_16 == 0)
    goto <bb 11>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 11> :
  _17 = UartUserCfg_35->Callback;
  if (_17 != 0B)
    goto <bb 12>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 12> :
  _18 = UartUserCfg_35->Callback;
  _19 = (long unsigned int) Channel_32(D);
  _20 = UartUserCfg_35->CallbackParam;
  _18 (_19, 0, _20);

  <bb 13> :
  # IsReturn_28 = PHI <IsReturn_38(5), IsReturn_38(7), IsReturn_38(10), IsReturn_51(4), IsReturn_38(6), IsReturn_45(9), IsReturn_38(12), IsReturn_38(11)>
  _21 ={v} UartState_34->RemainingBytes;
  if (_21 == 0)
    goto <bb 14>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 14> :
  _22 = ~IsReturn_28;
  if (_22 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 15> :
  _23 ={v} UartState_34->Status;
  if (_23 == 2)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  UartState_34->Status ={v} 0;

  <bb 17> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base_36, Channel_32(D));
  Flexio_Uart_Ip_StopTransfer (Channel_32(D));
  _24 = UartUserCfg_35->Callback;
  if (_24 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _25 = UartUserCfg_35->Callback;
  _26 = (long unsigned int) Channel_32(D);
  _27 = UartUserCfg_35->CallbackParam;
  _25 (_26, 2, _27);

  <bb 19> :
  return;

}



;; Function Flexio_Uart_Ip_CheckShifterErrorStatus (Flexio_Uart_Ip_CheckShifterErrorStatus, funcdef_no=31, decl_uid=6500, cgraph_uid=32, symbol_order=35)

Flexio_Uart_Ip_CheckShifterErrorStatus (const uint8 Channel)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  int _1;
  _Bool _2;

  <bb 2> :
  Base_4 = 1074110464B;
  _1 = (int) Channel_5(D);
  UartState_7 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = Flexio_Mcl_Ip_GetShifterErrorStatus (Base_4, Channel_5(D));
  if (_2 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  UartState_7->Status ={v} 1;
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base_4, Channel_5(D));

  <bb 4> :
  return;

}



;; Function Flexio_Uart_Ip_SetShifterInterrupt (Flexio_Uart_Ip_SetShifterInterrupt, funcdef_no=32, decl_uid=6503, cgraph_uid=33, symbol_order=36)

Flexio_Uart_Ip_SetShifterInterrupt (const uint8 Channel, boolean Enable)
{
  struct FLEXIO_Type * Base;
  int _1;
  unsigned int _2;
  unsigned char _3;
  int _4;
  unsigned int _5;
  unsigned char _6;

  <bb 2> :
  Base_7 = 1074110464B;
  _1 = (int) Channel_8(D);
  _2 = 1 << _1;
  _3 = (unsigned char) _2;
  Flexio_Mcl_Ip_SetShifterInterrupt (Base_7, _3, Enable_10(D));
  _4 = (int) Channel_8(D);
  _5 = 1 << _4;
  _6 = (unsigned char) _5;
  Flexio_Mcl_Ip_SetShifterErrorInterrupt (Base_7, _6, Enable_10(D));
  return;

}



;; Function Flexio_Uart_Ip_SetupReceiveData (Flexio_Uart_Ip_SetupReceiveData, funcdef_no=33, decl_uid=6498, cgraph_uid=34, symbol_order=37)

Flexio_Uart_Ip_SetupReceiveData (const uint8 Channel)
{
  <bb 2> :
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_2(D), 0);
  Flexio_Uart_Ip_EnableReceiver (Channel_2(D));
  return;

}



;; Function Flexio_Uart_Ip_EnableReceiver (Flexio_Uart_Ip_EnableReceiver, funcdef_no=34, decl_uid=6482, cgraph_uid=35, symbol_order=38)

Flexio_Uart_Ip_EnableReceiver (const uint8 Channel)
{
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base_1 = 1074110464B;
  Flexio_Mcl_Ip_ClearShifterStatus (Base_1, Channel_3(D));
  Flexio_Uart_Ip_SetShifterMode (Base_1, Channel_3(D), 1);
  Flexio_Uart_Ip_SetTimerMode (Base_1, Channel_3(D), 1);
  return;

}



;; Function Flexio_Uart_Ip_StartSendDataUsingDma (Flexio_Uart_Ip_StartSendDataUsingDma, funcdef_no=35, decl_uid=6490, cgraph_uid=36, symbol_order=39)

Flexio_Uart_Ip_StartSendDataUsingDma (uint8 Channel, const uint8 * TxData, uint32 TxSize)
{
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UserConfig;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6883;
  int _1;
  int _2;
  long unsigned int TxData.2_3;
  int _4;
  volatile uint32_t * _5;
  long unsigned int _6;
  unsigned char _7;
  long unsigned int _8;
  _Bool _9;
  unsigned char _10;
  long unsigned int _11;
  _Bool _12;
  int _13;
  unsigned int _14;
  unsigned char _15;
  Flexio_Uart_Ip_StatusType _53;

  <bb 2> :
  _1 = (int) Channel_16(D);
  UartState_18 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_16(D);
  UserConfig_19 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_20 = 1074110464B;
  DmaTransferList[0].Param = 0;
  TxData.2_3 = (long unsigned int) TxData_22(D);
  DmaTransferList[0].Value = TxData.2_3;
  DmaTransferList[1].Param = 5;
  _4 = (int) Channel_16(D);
  _5 = &Base_20->SHIFTBUF[_4];
  _6 = (long unsigned int) _5;
  DmaTransferList[1].Value = _6;
  DmaTransferList[2].Param = 1;
  DmaTransferList[2].Value = 1;
  DmaTransferList[3].Param = 6;
  DmaTransferList[3].Value = 0;
  DmaTransferList[4].Param = 18;
  DmaTransferList[4].Value = TxSize_31(D);
  DmaTransferList[5].Param = 15;
  DmaTransferList[5].Value = 1;
  DmaTransferList[6].Param = 8;
  DmaTransferList[6].Value = 0;
  DmaTransferList[7].Param = 3;
  DmaTransferList[7].Value = 0;
  DmaTransferList[8].Param = 21;
  DmaTransferList[8].Value = 1;
  DmaTransferList[9].Param = 23;
  DmaTransferList[9].Value = 1;
  UartState_18->TxData = TxData_22(D);
  UartState_18->RemainingBytes ={v} 0;
  UartState_18->Status ={v} 2;
  _7 = UserConfig_19->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus_47 = Dma_Ip_SetLogicChannelTransferList (_8, &DmaTransferList, 10);
  _9 = DmaReturnStatus_47 == 0;
  DevAssert (_9);
  _10 = UserConfig_19->DmaChannel;
  _11 = (long unsigned int) _10;
  DmaReturnStatus_50 = Dma_Ip_SetLogicChannelCommand (_11, 0);
  _12 = DmaReturnStatus_50 == 0;
  DevAssert (_12);
  _13 = (int) Channel_16(D);
  _14 = 1 << _13;
  _15 = (unsigned char) _14;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base_20, _15, 1);
  _53 = 0;
  DmaTransferList ={v} {CLOBBER};

  <bb 3> :
<L1>:
  return _53;

}



;; Function Flexio_Uart_Ip_StartReceiveDataUsingDma (Flexio_Uart_Ip_StartReceiveDataUsingDma, funcdef_no=36, decl_uid=6494, cgraph_uid=37, symbol_order=40)

Flexio_Uart_Ip_StartReceiveDataUsingDma (uint8 Channel, uint8 * RxBuff, uint32 RxSize)
{
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UserConfig;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6886;
  int _1;
  int _2;
  int _3;
  volatile uint32_t * _4;
  long unsigned int _5;
  long unsigned int _6;
  long unsigned int RxBuff.3_7;
  unsigned char _8;
  long unsigned int _9;
  _Bool _10;
  unsigned char _11;
  long unsigned int _12;
  _Bool _13;
  int _14;
  unsigned int _15;
  unsigned char _16;
  Flexio_Uart_Ip_StatusType _54;

  <bb 2> :
  _1 = (int) Channel_17(D);
  UartState_19 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel_17(D);
  UserConfig_20 = Flexio_Uart_Ip_apUserConfig[_2];
  Base_21 = 1074110464B;
  DmaTransferList[0].Param = 0;
  _3 = (int) Channel_17(D);
  _4 = &Base_21->SHIFTBUF[_3];
  _5 = (long unsigned int) _4;
  _6 = _5 + 3;
  DmaTransferList[0].Value = _6;
  DmaTransferList[1].Param = 5;
  RxBuff.3_7 = (long unsigned int) RxBuff_25(D);
  DmaTransferList[1].Value = RxBuff.3_7;
  DmaTransferList[2].Param = 1;
  DmaTransferList[2].Value = 0;
  DmaTransferList[3].Param = 6;
  DmaTransferList[3].Value = 1;
  DmaTransferList[4].Param = 18;
  DmaTransferList[4].Value = RxSize_32(D);
  DmaTransferList[5].Param = 15;
  DmaTransferList[5].Value = 1;
  DmaTransferList[6].Param = 8;
  DmaTransferList[6].Value = 0;
  DmaTransferList[7].Param = 3;
  DmaTransferList[7].Value = 0;
  DmaTransferList[8].Param = 21;
  DmaTransferList[8].Value = 1;
  DmaTransferList[9].Param = 23;
  DmaTransferList[9].Value = 1;
  UartState_19->RxData = RxBuff_25(D);
  UartState_19->RemainingBytes ={v} 0;
  UartState_19->Status ={v} 2;
  _8 = UserConfig_20->DmaChannel;
  _9 = (long unsigned int) _8;
  DmaReturnStatus_48 = Dma_Ip_SetLogicChannelTransferList (_9, &DmaTransferList, 10);
  _10 = DmaReturnStatus_48 == 0;
  DevAssert (_10);
  _11 = UserConfig_20->DmaChannel;
  _12 = (long unsigned int) _11;
  DmaReturnStatus_51 = Dma_Ip_SetLogicChannelCommand (_12, 0);
  _13 = DmaReturnStatus_51 == 0;
  DevAssert (_13);
  _14 = (int) Channel_17(D);
  _15 = 1 << _14;
  _16 = (unsigned char) _15;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base_21, _16, 1);
  _54 = 0;
  DmaTransferList ={v} {CLOBBER};

  <bb 3> :
<L1>:
  return _54;

}



;; Function Flexio_Uart_Ip_Init (Flexio_Uart_Ip_Init, funcdef_no=37, decl_uid=5967, cgraph_uid=38, symbol_order=41)

Flexio_Uart_Ip_Init (const uint8 Channel, const struct Flexio_Uart_Ip_UserConfigType * UserConfig)
{
  struct Flexio_Uart_Ip_StateStructureType * UartStatePtr;
  int _1;
  struct Flexio_Uart_Ip_StateStructureType * _2;
  _Bool _3;
  _Bool _4;
  long unsigned int _5;
  long unsigned int _6;
  _Bool _7;
  int _8;
  struct Flexio_Uart_Ip_StateStructureType * _9;
  int _10;
  long unsigned int _11;
  <unnamed type> _12;
  <unnamed type> _13;
  unsigned char _14;
  unsigned char _15;
  <unnamed type> _16;
  <unnamed type> _17;
  unsigned char _18;
  unsigned char _19;
  <unnamed type> _20;

  <bb 2> :
  UartStatePtr_24 = UserConfig_23(D)->StateStruct;
  _1 = (int) Channel_25(D);
  _2 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _3 = _2 == 0B;
  DevAssert (_3);
  _4 = Channel_25(D) <= 3;
  DevAssert (_4);
  _5 = (long unsigned int) Channel_25(D);
  _6 = UserConfig_23(D)->Channel;
  _7 = _5 == _6;
  DevAssert (_7);
  _8 = (int) Channel_25(D);
  _9 = UserConfig_23(D)->StateStruct;
  Flexio_Uart_Ip_apStateStructuresArray[_8] = _9;
  _10 = (int) Channel_25(D);
  Flexio_Uart_Ip_apUserConfig[_10] = UserConfig_23(D);
  UartStatePtr_24->RxData = 0B;
  UartStatePtr_24->TxData = 0B;
  UartStatePtr_24->RemainingBytes ={v} 0;
  _11 = UserConfig_23(D)->BaudRate;
  UartStatePtr_24->BaudRate = _11;
  UartStatePtr_24->Status ={v} 0;
  UartStatePtr_24->DriverIdle ={v} 0;
  _12 = UserConfig_23(D)->Direction;
  if (_12 == 1)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _13 = UserConfig_23(D)->BitCount;
  _14 = UserConfig_23(D)->Divider;
  _15 = UserConfig_23(D)->DataPin;
  _16 = UserConfig_23(D)->TimerDec;
  Flexio_Uart_Ip_ConfigureTx (Channel_25(D), _13, _14, _15, _16);
  goto <bb 5>; [INV]

  <bb 4> :
  _17 = UserConfig_23(D)->BitCount;
  _18 = UserConfig_23(D)->Divider;
  _19 = UserConfig_23(D)->DataPin;
  _20 = UserConfig_23(D)->TimerDec;
  Flexio_Uart_Ip_ConfigureRx (Channel_25(D), _17, _18, _19, _20);

  <bb 5> :
  return;

}



;; Function Flexio_Uart_Ip_GetBaudRate (Flexio_Uart_Ip_GetBaudRate, funcdef_no=38, decl_uid=5972, cgraph_uid=39, symbol_order=42)

Flexio_Uart_Ip_GetBaudRate (const uint8 Channel, uint32 * BaudRate)
{
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  _Bool _1;
  _Bool _2;
  int _3;
  long unsigned int _4;

  <bb 2> :
  _1 = Channel_5(D) <= 3;
  DevAssert (_1);
  _2 = BaudRate_8(D) != 0B;
  DevAssert (_2);
  _3 = (int) Channel_5(D);
  UartState_10 = Flexio_Uart_Ip_apStateStructuresArray[_3];
  _4 = UartState_10->BaudRate;
  *BaudRate_8(D) = _4;
  return;

}



;; Function Flexio_Uart_Ip_Deinit (Flexio_Uart_Ip_Deinit, funcdef_no=39, decl_uid=5969, cgraph_uid=40, symbol_order=43)

Flexio_Uart_Ip_Deinit (const uint8 Channel)
{
  struct FLEXIO_Type * Base;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  _Bool _1;
  int _2;
  struct Flexio_Uart_Ip_StateStructureType * _3;
  _Bool _4;
  <unnamed type> _5;
  long unsigned int TimeoutTicks.4_6;
  _Bool _7;
  _Bool _8;
  int _9;

  <bb 2> :
  _1 = Channel_12(D) <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  Base_16 = 1074110464B;
  _2 = (int) Channel_12(D);
  _3 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _4 = _3 != 0B;
  DevAssert (_4);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 3> :
  _5 = Flexio_Uart_Ip_GetStatus (Channel_12(D), 0B);
  if (_5 == 2)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  TimeoutTicks.4_6 = TimeoutTicks;
  _7 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.4_6, 0);
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 5> :
  _9 = (int) Channel_12(D);
  Flexio_Uart_Ip_apStateStructuresArray[_9] = 0B;
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_12(D), 0);
  Flexio_Mcl_Ip_SetSoftwareReset (Base_16, 1);
  Flexio_Mcl_Ip_SetSoftwareReset (Base_16, 0);
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};
  return;

}



;; Function Flexio_Uart_Ip_AsyncSend (Flexio_Uart_Ip_AsyncSend, funcdef_no=40, decl_uid=5980, cgraph_uid=41, symbol_order=44)

Flexio_Uart_Ip_AsyncSend (const uint8 Channel, const uint8 * TxBuff, const uint32 TxSize)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType D.6905;
  unsigned char iftmp.6;
  int iftmp.5;
  _Bool _1;
  int _2;
  int _3;
  _Bool _4;
  _Bool _5;
  _Bool _6;
  <unnamed type> _7;
  _Bool _8;
  <unnamed type> _9;
  long unsigned int _10;
  _Bool _11;
  _Bool _12;
  <unnamed type> _13;
  int iftmp.5_15;
  unsigned char iftmp.6_16;
  int iftmp.5_30;
  int iftmp.5_31;
  unsigned char iftmp.6_40;
  unsigned char iftmp.6_41;
  Flexio_Uart_Ip_StatusType _50;

  <bb 2> :
  _1 = Channel_18(D) <= 3;
  DevAssert (_1);
  _2 = (int) Channel_18(D);
  UartState_21 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_18(D);
  UartUserCfg_22 = Flexio_Uart_Ip_apUserConfig[_3];
  RetStatus_23 = 1;
  _4 = UartState_21 != 0B;
  DevAssert (_4);
  _5 = TxBuff_25(D) != 0B;
  DevAssert (_5);
  _6 = TxSize_27(D) != 0;
  DevAssert (_6);
  _7 = UartUserCfg_22->Direction;
  _8 = _7 == 1;
  DevAssert (_8);
  _9 = UartUserCfg_22->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = TxSize_27(D) & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.5_31 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.5_30 = 0;

  <bb 6> :
  # iftmp.5_15 = PHI <iftmp.5_31(4), iftmp.5_30(5)>
  _11 = (_Bool) iftmp.5_15;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04 ();
  _12 ={v} UartState_21->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04 ();
  RetStatus_49 = 2;
  goto <bb 15>; [INV]

  <bb 8> :
  UartState_21->DriverIdle ={v} 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04 ();
  Base_36 = 1074110464B;
  UartState_21->TxData = TxBuff_25(D);
  UartState_21->RemainingBytes ={v} TxSize_27(D);
  UartState_21->Status ={v} 2;
  if (TxSize_27(D) == 1)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  iftmp.6_41 = 1;
  goto <bb 11>; [INV]

  <bb 10> :
  iftmp.6_40 = 2;

  <bb 11> :
  # iftmp.6_16 = PHI <iftmp.6_41(9), iftmp.6_40(10)>
  UartState_21->TxFlush = iftmp.6_16;
  Flexio_Uart_Ip_SetTimerMode (Base_36, Channel_18(D), 1);
  _13 = UartUserCfg_22->DriverType;
  switch (_13) <default: <L11> [INV], case 0: <L9> [INV], case 1: <L10> [INV]>

  <bb 12> :
<L9>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_18(D), 1);
  RetStatus_47 = 0;
  goto <bb 15>; [INV]

  <bb 13> :
<L10>:
  RetStatus_45 = Flexio_Uart_Ip_StartSendDataUsingDma (Channel_18(D), TxBuff_25(D), TxSize_27(D));
  goto <bb 15>; [INV]

  <bb 14> :
<L11>:

  <bb 15> :
  # RetStatus_14 = PHI <RetStatus_49(7), RetStatus_47(12), RetStatus_45(13), RetStatus_23(14)>
  _50 = RetStatus_14;

  <bb 16> :
<L14>:
  return _50;

}



;; Function Flexio_Uart_Ip_GetStatus (Flexio_Uart_Ip_GetStatus, funcdef_no=41, decl_uid=5997, cgraph_uid=42, symbol_order=45)

Flexio_Uart_Ip_GetStatus (const uint8 Channel, uint32 * BytesRemaining)
{
  const Dma_Ip_LogicChannelInfoParamType DmaLogicChnParam;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6915;
  _Bool _1;
  int _2;
  int _3;
  _Bool _4;
  _Bool _5;
  <unnamed type> _6;
  long unsigned int _7;
  unsigned char _8;
  long unsigned int _9;
  Flexio_Uart_Ip_StatusType _22;

  <bb 2> :
  _1 = Channel_11(D) <= 3;
  DevAssert (_1);
  _2 = (int) Channel_11(D);
  UartState_14 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_11(D);
  UartUserCfg_15 = Flexio_Uart_Ip_apUserConfig[_3];
  DmaLogicChnParam_16 = 3;
  _4 = UartState_14 != 0B;
  DevAssert (_4);
  if (BytesRemaining_18(D) != 0B)
    goto <bb 3>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 3> :
  _5 ={v} UartState_14->DriverIdle;
  if (_5 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 4> :
  _6 = UartUserCfg_15->DriverType;
  if (_6 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  _7 ={v} UartState_14->RemainingBytes;
  *BytesRemaining_18(D) = _7;
  goto <bb 8>; [INV]

  <bb 6> :
  _8 = UartUserCfg_15->DmaChannel;
  _9 = (long unsigned int) _8;
  Dma_Ip_GetLogicChannelParam (_9, DmaLogicChnParam_16, BytesRemaining_18(D));
  goto <bb 8>; [INV]

  <bb 7> :
  *BytesRemaining_18(D) = 0;

  <bb 8> :
  _22 ={v} UartState_14->Status;

  <bb 9> :
<L8>:
  return _22;

}



;; Function Flexio_Uart_Ip_SyncSend (Flexio_Uart_Ip_SyncSend, funcdef_no=42, decl_uid=5985, cgraph_uid=43, symbol_order=46)

Flexio_Uart_Ip_SyncSend (const uint8 Channel, const uint8 * TxBuff, const uint32 TxSize, const uint32 Timeout)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType D.6935;
  unsigned char iftmp.8;
  int iftmp.7;
  _Bool _1;
  _Bool _2;
  _Bool _3;
  int _4;
  int _5;
  _Bool _6;
  <unnamed type> _7;
  _Bool _8;
  <unnamed type> _9;
  long unsigned int _10;
  _Bool _11;
  _Bool _12;
  _Bool _13;
  _Bool _14;
  long unsigned int TimeoutTicks.9_15;
  _Bool _16;
  _Bool _17;
  long unsigned int _18;
  long unsigned int TimeoutTicks.10_19;
  _Bool _20;
  _Bool _21;
  long unsigned int TimeoutTicks.11_22;
  _Bool _23;
  <unnamed type> _24;
  int iftmp.7_26;
  unsigned char iftmp.8_27;
  int iftmp.7_48;
  int iftmp.7_49;
  unsigned char iftmp.8_58;
  unsigned char iftmp.8_59;
  Flexio_Uart_Ip_StatusType _76;

  <bb 2> :
  _1 = Channel_34(D) <= 3;
  DevAssert (_1);
  _2 = TxBuff_37(D) != 0B;
  DevAssert (_2);
  _3 = TxSize_39(D) != 0;
  DevAssert (_3);
  ElapsedTicks = 0;
  RetStatus_42 = 1;
  _4 = (int) Channel_34(D);
  UartState_43 = Flexio_Uart_Ip_apStateStructuresArray[_4];
  _5 = (int) Channel_34(D);
  UartUserCfg_44 = Flexio_Uart_Ip_apUserConfig[_5];
  Base_45 = 1074110464B;
  _6 = UartState_43 != 0B;
  DevAssert (_6);
  _7 = UartUserCfg_44->Direction;
  _8 = _7 == 1;
  DevAssert (_8);
  _9 = UartUserCfg_44->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = TxSize_39(D) & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.7_49 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.7_48 = 0;

  <bb 6> :
  # iftmp.7_26 = PHI <iftmp.7_49(4), iftmp.7_48(5)>
  _11 = (_Bool) iftmp.7_26;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05 ();
  _12 ={v} UartState_43->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05 ();
  RetStatus_75 = 2;
  goto <bb 22>; [INV]

  <bb 8> :
  UartState_43->DriverIdle ={v} 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05 ();
  UartState_43->TxData = TxBuff_37(D);
  UartState_43->RemainingBytes ={v} TxSize_39(D);
  UartState_43->Status ={v} 2;
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_34(D), 0);
  if (TxSize_39(D) == 1)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  iftmp.8_59 = 1;
  goto <bb 11>; [INV]

  <bb 10> :
  iftmp.8_58 = 2;

  <bb 11> :
  # iftmp.8_27 = PHI <iftmp.8_59(9), iftmp.8_58(10)>
  UartState_43->TxFlush = iftmp.8_27;
  Flexio_Uart_Ip_SetTimerMode (Base_45, Channel_34(D), 1);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, Timeout_62(D), 0);
  goto <bb 15>; [INV]

  <bb 12> :
  Flexio_Uart_Ip_WriteData (Channel_34(D));

  <bb 13> :
  _13 = Flexio_Mcl_Ip_GetShifterStatus (Base_45, Channel_34(D));
  _14 = ~_13;
  if (_14 != 0)
    goto <bb 14>; [INV]
  else
    goto <bb 15>; [INV]

  <bb 14> :
  TimeoutTicks.9_15 = TimeoutTicks;
  _16 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.9_15, 0);
  _17 = ~_16;
  if (_17 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 15>; [INV]

  <bb 15> :
  _18 ={v} UartState_43->RemainingBytes;
  if (_18 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  TimeoutTicks.10_19 = TimeoutTicks;
  _20 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.10_19, 0);
  _21 = ~_20;
  if (_21 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 17> :
  TimeoutTicks.11_22 = TimeoutTicks;
  _23 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.11_22, 0);
  if (_23 != 0)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  UartState_43->Status ={v} 518;

  <bb 19> :
  _24 ={v} UartState_43->Status;
  if (_24 == 2)
    goto <bb 20>; [INV]
  else
    goto <bb 21>; [INV]

  <bb 20> :
  UartState_43->Status ={v} 0;

  <bb 21> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base_45, Channel_34(D));
  UartState_43->DriverIdle ={v} 0;
  RetStatus_73 ={v} UartState_43->Status;

  <bb 22> :
  # RetStatus_25 = PHI <RetStatus_75(7), RetStatus_73(21)>
  _76 = RetStatus_25;
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};

  <bb 23> :
<L23>:
  return _76;

}



;; Function Flexio_Uart_Ip_AsyncReceive (Flexio_Uart_Ip_AsyncReceive, funcdef_no=43, decl_uid=5989, cgraph_uid=44, symbol_order=47)

Flexio_Uart_Ip_AsyncReceive (const uint8 Channel, uint8 * RxBuff, const uint32 RxSize)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6946;
  int iftmp.12;
  _Bool _1;
  int _2;
  int _3;
  _Bool _4;
  _Bool _5;
  _Bool _6;
  <unnamed type> _7;
  _Bool _8;
  <unnamed type> _9;
  long unsigned int _10;
  _Bool _11;
  _Bool _12;
  <unnamed type> _13;
  int iftmp.12_15;
  int iftmp.12_29;
  int iftmp.12_30;
  Flexio_Uart_Ip_StatusType _45;

  <bb 2> :
  _1 = Channel_17(D) <= 3;
  DevAssert (_1);
  _2 = (int) Channel_17(D);
  UartState_20 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_17(D);
  UartUserCfg_21 = Flexio_Uart_Ip_apUserConfig[_3];
  RetStatus_22 = 1;
  _4 = UartState_20 != 0B;
  DevAssert (_4);
  _5 = RxBuff_24(D) != 0B;
  DevAssert (_5);
  _6 = RxSize_26(D) != 0;
  DevAssert (_6);
  _7 = UartUserCfg_21->Direction;
  _8 = _7 == 0;
  DevAssert (_8);
  _9 = UartUserCfg_21->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = RxSize_26(D) & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.12_30 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.12_29 = 0;

  <bb 6> :
  # iftmp.12_15 = PHI <iftmp.12_30(4), iftmp.12_29(5)>
  _11 = (_Bool) iftmp.12_15;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06 ();
  _12 ={v} UartState_20->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06 ();
  RetStatus_44 = 2;
  goto <bb 12>; [INV]

  <bb 8> :
  UartState_20->DriverIdle ={v} 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06 ();
  UartState_20->RxData = RxBuff_24(D);
  UartState_20->RemainingBytes ={v} RxSize_26(D);
  UartState_20->Status ={v} 2;
  Flexio_Uart_Ip_EnableReceiver (Channel_17(D));
  _13 = UartUserCfg_21->DriverType;
  switch (_13) <default: <L8> [INV], case 0: <L6> [INV], case 1: <L7> [INV]>

  <bb 9> :
<L6>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_17(D), 1);
  RetStatus_42 = 0;
  goto <bb 12>; [INV]

  <bb 10> :
<L7>:
  RetStatus_40 = Flexio_Uart_Ip_StartReceiveDataUsingDma (Channel_17(D), RxBuff_24(D), RxSize_26(D));
  goto <bb 12>; [INV]

  <bb 11> :
<L8>:

  <bb 12> :
  # RetStatus_14 = PHI <RetStatus_44(7), RetStatus_42(9), RetStatus_40(10), RetStatus_22(11)>
  _45 = RetStatus_14;

  <bb 13> :
<L11>:
  return _45;

}



;; Function Flexio_Uart_Ip_SyncReceive (Flexio_Uart_Ip_SyncReceive, funcdef_no=44, decl_uid=5994, cgraph_uid=45, symbol_order=48)

Flexio_Uart_Ip_SyncReceive (const uint8 Channel, uint8 * RxBuff, const uint32 RxSize, const uint32 Timeout)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  struct FLEXIO_Type * Base;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6965;
  int iftmp.13;
  _Bool _1;
  _Bool _2;
  _Bool _3;
  int _4;
  int _5;
  _Bool _6;
  <unnamed type> _7;
  _Bool _8;
  <unnamed type> _9;
  long unsigned int _10;
  _Bool _11;
  _Bool _12;
  _Bool _13;
  _Bool _14;
  long unsigned int TimeoutTicks.14_15;
  _Bool _16;
  _Bool _17;
  <unnamed type> _18;
  long unsigned int _19;
  long unsigned int TimeoutTicks.15_20;
  _Bool _21;
  _Bool _22;
  <unnamed type> _23;
  long unsigned int TimeoutTicks.16_24;
  _Bool _25;
  int iftmp.13_27;
  int iftmp.13_48;
  int iftmp.13_49;
  Flexio_Uart_Ip_StatusType _73;

  <bb 2> :
  _1 = Channel_34(D) <= 3;
  DevAssert (_1);
  _2 = RxBuff_37(D) != 0B;
  DevAssert (_2);
  _3 = RxSize_39(D) != 0;
  DevAssert (_3);
  ElapsedTicks = 0;
  Base_42 = 1074110464B;
  RetStatus_43 = 1;
  _4 = (int) Channel_34(D);
  UartState_44 = Flexio_Uart_Ip_apStateStructuresArray[_4];
  _5 = (int) Channel_34(D);
  UartUserCfg_45 = Flexio_Uart_Ip_apUserConfig[_5];
  _6 = UartState_44 != 0B;
  DevAssert (_6);
  _7 = UartUserCfg_45->Direction;
  _8 = _7 == 0;
  DevAssert (_8);
  _9 = UartUserCfg_45->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = RxSize_39(D) & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.13_49 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.13_48 = 0;

  <bb 6> :
  # iftmp.13_27 = PHI <iftmp.13_49(4), iftmp.13_48(5)>
  _11 = (_Bool) iftmp.13_27;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07 ();
  _12 ={v} UartState_44->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07 ();
  RetStatus_72 = 2;
  goto <bb 22>; [INV]

  <bb 8> :
  UartState_44->DriverIdle ={v} 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07 ();
  UartState_44->RxData = RxBuff_37(D);
  UartState_44->RemainingBytes ={v} RxSize_39(D);
  UartState_44->Status ={v} 2;
  Flexio_Uart_Ip_SetupReceiveData (Channel_34(D));
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, Timeout_58(D), 0);
  goto <bb 15>; [INV]

  <bb 9> :

  <bb 10> :
  _13 = Flexio_Mcl_Ip_GetShifterStatus (Base_42, Channel_34(D));
  _14 = ~_13;
  if (_14 != 0)
    goto <bb 11>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 11> :
  TimeoutTicks.14_15 = TimeoutTicks;
  _16 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.14_15, 0);
  _17 = ~_16;
  if (_17 != 0)
    goto <bb 10>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 12> :
  Flexio_Uart_Ip_CheckShifterErrorStatus (Channel_34(D));
  _18 ={v} UartState_44->Status;
  if (_18 == 1)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  goto <bb 17>; [INV]

  <bb 14> :
  Flexio_Uart_Ip_ReadData (Channel_34(D));

  <bb 15> :
  _19 ={v} UartState_44->RemainingBytes;
  if (_19 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  TimeoutTicks.15_20 = TimeoutTicks;
  _21 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.15_20, 0);
  _22 = ~_21;
  if (_22 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 17> :
  _23 ={v} UartState_44->Status;
  if (_23 == 2)
    goto <bb 18>; [INV]
  else
    goto <bb 21>; [INV]

  <bb 18> :
  TimeoutTicks.16_24 = TimeoutTicks;
  _25 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.16_24, 0);
  if (_25 != 0)
    goto <bb 19>; [INV]
  else
    goto <bb 20>; [INV]

  <bb 19> :
  UartState_44->Status ={v} 518;
  goto <bb 21>; [INV]

  <bb 20> :
  UartState_44->Status ={v} 0;

  <bb 21> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base_42, Channel_34(D));
  UartState_44->DriverIdle ={v} 0;
  RetStatus_70 ={v} UartState_44->Status;

  <bb 22> :
  # RetStatus_26 = PHI <RetStatus_72(7), RetStatus_70(21)>
  _73 = RetStatus_26;
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};

  <bb 23> :
<L23>:
  return _73;

}



;; Function Flexio_Uart_Ip_CompleteSendUsingDma (Flexio_Uart_Ip_CompleteSendUsingDma, funcdef_no=45, decl_uid=5999, cgraph_uid=46, symbol_order=49)

Flexio_Uart_Ip_CompleteSendUsingDma (uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  struct Dma_Ip_LogicChannelStatusType DmaStatus;
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  _Bool _1;
  int _2;
  int _3;
  unsigned char _4;
  long unsigned int _5;
  <unnamed type> _6;
  unsigned char _7;
  long unsigned int _8;
  _Bool _9;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _10;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _11;
  long unsigned int _12;
  void * _13;
  <unnamed type> _14;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _15;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _16;
  long unsigned int _17;
  void * _18;
  long unsigned int _19;
  <unnamed type> _20;
  const uint8 * _21;
  long unsigned int _22;
  long unsigned int _23;
  unsigned char _24;
  long unsigned int _25;
  _Bool _26;
  unsigned char _27;
  long unsigned int _28;
  _Bool _29;
  int _30;
  unsigned int _31;
  unsigned char _32;
  int _33;
  unsigned int _34;
  unsigned char _35;
  _Bool _36;
  _Bool _37;
  long unsigned int TimeoutTicks.17_38;
  _Bool _39;
  _Bool _40;
  long unsigned int TimeoutTicks.18_41;
  _Bool _42;
  <unnamed type> _43;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _44;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _45;
  long unsigned int _46;
  void * _47;

  <bb 2> :
  _1 = Channel_54(D) <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  _2 = (int) Channel_54(D);
  UartState_58 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_54(D);
  UartUserCfg_59 = Flexio_Uart_Ip_apUserConfig[_3];
  Base_60 = 1074110464B;
  _4 = UartUserCfg_59->DmaChannel;
  _5 = (long unsigned int) _4;
  Dma_Ip_GetLogicChannelStatus (_5, &DmaStatus);
  _6 = DmaStatus.ChStateValue;
  if (_6 == 4)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _7 = UartUserCfg_59->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus_63 = Dma_Ip_SetLogicChannelCommand (_8, 4);
  _9 = DmaReturnStatus_63 == 0;
  DevAssert (_9);
  UartState_58->Status ={v} 1;
  _10 = UartUserCfg_59->Callback;
  if (_10 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _11 = UartUserCfg_59->Callback;
  _12 = (long unsigned int) Channel_54(D);
  _13 = UartUserCfg_59->CallbackParam;
  _11 (_12, 3, _13);

  <bb 5> :
  _14 ={v} UartState_58->Status;
  if (_14 == 2)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  _15 = UartUserCfg_59->Callback;
  if (_15 != 0B)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _16 = UartUserCfg_59->Callback;
  _17 = (long unsigned int) Channel_54(D);
  _18 = UartUserCfg_59->CallbackParam;
  _16 (_17, 1, _18);

  <bb 8> :
  _19 ={v} UartState_58->RemainingBytes;
  if (_19 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 9> :
  _20 ={v} UartState_58->Status;
  if (_20 != 1)
    goto <bb 10>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 10> :
  DmaTransferList[0].Param = 0;
  _21 = UartState_58->TxData;
  _22 = (long unsigned int) _21;
  DmaTransferList[0].Value = _22;
  DmaTransferList[1].Param = 18;
  _23 ={v} UartState_58->RemainingBytes;
  DmaTransferList[1].Value = _23;
  _24 = UartUserCfg_59->DmaChannel;
  _25 = (long unsigned int) _24;
  DmaReturnStatus_73 = Dma_Ip_SetLogicChannelTransferList (_25, &DmaTransferList, 2);
  _26 = DmaReturnStatus_73 == 0;
  DevAssert (_26);
  UartState_58->RemainingBytes ={v} 0;
  _27 = UartUserCfg_59->DmaChannel;
  _28 = (long unsigned int) _27;
  DmaReturnStatus_77 = Dma_Ip_SetLogicChannelCommand (_28, 0);
  _29 = DmaReturnStatus_77 == 0;
  DevAssert (_29);
  goto <bb 19>; [INV]

  <bb 11> :
  _30 = (int) Channel_54(D);
  _31 = 1 << _30;
  _32 = (unsigned char) _31;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base_60, _32, 0);
  _33 = (int) Channel_54(D);
  _34 = 1 << _33;
  _35 = (unsigned char) _34;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_60, _35, 0);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 12> :
  _36 = Flexio_Mcl_Ip_GetTimerStatus (Base_60, Channel_54(D));
  _37 = ~_36;
  if (_37 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  TimeoutTicks.17_38 = TimeoutTicks;
  _39 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.17_38, 0);
  _40 = ~_39;
  if (_40 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 14> :
  TimeoutTicks.18_41 = TimeoutTicks;
  _42 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.18_41, 0);
  if (_42 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  UartState_58->Status ={v} 1;

  <bb 16> :
  UartState_58->DriverIdle ={v} 0;
  _43 ={v} UartState_58->Status;
  if (_43 == 2)
    goto <bb 17>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 17> :
  UartState_58->Status ={v} 0;
  _44 = UartUserCfg_59->Callback;
  if (_44 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _45 = UartUserCfg_59->Callback;
  _46 = (long unsigned int) Channel_54(D);
  _47 = UartUserCfg_59->CallbackParam;
  _45 (_46, 2, _47);

  <bb 19> :
  DmaTransferList ={v} {CLOBBER};
  DmaStatus ={v} {CLOBBER};
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};
  return;

}



;; Function Flexio_Uart_Ip_CompleteReceiveUsingDma (Flexio_Uart_Ip_CompleteReceiveUsingDma, funcdef_no=46, decl_uid=6001, cgraph_uid=47, symbol_order=50)

Flexio_Uart_Ip_CompleteReceiveUsingDma (uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  struct Dma_Ip_LogicChannelStatusType DmaStatus;
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  _Bool _1;
  int _2;
  int _3;
  unsigned char _4;
  long unsigned int _5;
  <unnamed type> _6;
  unsigned char _7;
  long unsigned int _8;
  _Bool _9;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _10;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _11;
  long unsigned int _12;
  void * _13;
  <unnamed type> _14;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _15;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _16;
  long unsigned int _17;
  void * _18;
  long unsigned int _19;
  <unnamed type> _20;
  volatile uint8 * _21;
  long unsigned int _22;
  long unsigned int _23;
  unsigned char _24;
  long unsigned int _25;
  _Bool _26;
  unsigned char _27;
  long unsigned int _28;
  _Bool _29;
  int _30;
  unsigned int _31;
  unsigned char _32;
  int _33;
  unsigned int _34;
  unsigned char _35;
  int _36;
  unsigned int _37;
  unsigned char _38;
  _Bool _39;
  _Bool _40;
  long unsigned int TimeoutTicks.19_41;
  _Bool _42;
  _Bool _43;
  long unsigned int TimeoutTicks.20_44;
  _Bool _45;
  <unnamed type> _46;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _47;
  void (*<T4b9>) (const uint32, const Flexio_Uart_Ip_EventType, void *) _48;
  long unsigned int _49;
  void * _50;

  <bb 2> :
  _1 = Channel_57(D) <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  _2 = (int) Channel_57(D);
  UartState_61 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_57(D);
  UartUserCfg_62 = Flexio_Uart_Ip_apUserConfig[_3];
  Base_63 = 1074110464B;
  _4 = UartUserCfg_62->DmaChannel;
  _5 = (long unsigned int) _4;
  Dma_Ip_GetLogicChannelStatus (_5, &DmaStatus);
  _6 = DmaStatus.ChStateValue;
  if (_6 == 4)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _7 = UartUserCfg_62->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus_66 = Dma_Ip_SetLogicChannelCommand (_8, 4);
  _9 = DmaReturnStatus_66 == 0;
  DevAssert (_9);
  UartState_61->Status ={v} 1;
  _10 = UartUserCfg_62->Callback;
  if (_10 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _11 = UartUserCfg_62->Callback;
  _12 = (long unsigned int) Channel_57(D);
  _13 = UartUserCfg_62->CallbackParam;
  _11 (_12, 3, _13);

  <bb 5> :
  _14 ={v} UartState_61->Status;
  if (_14 == 2)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  _15 = UartUserCfg_62->Callback;
  if (_15 != 0B)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _16 = UartUserCfg_62->Callback;
  _17 = (long unsigned int) Channel_57(D);
  _18 = UartUserCfg_62->CallbackParam;
  _16 (_17, 0, _18);

  <bb 8> :
  _19 ={v} UartState_61->RemainingBytes;
  if (_19 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 9> :
  _20 ={v} UartState_61->Status;
  if (_20 != 1)
    goto <bb 10>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 10> :
  DmaTransferList[0].Param = 5;
  _21 = UartState_61->RxData;
  _22 = (long unsigned int) _21;
  DmaTransferList[0].Value = _22;
  DmaTransferList[1].Param = 18;
  _23 ={v} UartState_61->RemainingBytes;
  DmaTransferList[1].Value = _23;
  _24 = UartUserCfg_62->DmaChannel;
  _25 = (long unsigned int) _24;
  DmaReturnStatus_76 = Dma_Ip_SetLogicChannelTransferList (_25, &DmaTransferList, 2);
  _26 = DmaReturnStatus_76 == 0;
  DevAssert (_26);
  UartState_61->RemainingBytes ={v} 0;
  _27 = UartUserCfg_62->DmaChannel;
  _28 = (long unsigned int) _27;
  DmaReturnStatus_80 = Dma_Ip_SetLogicChannelCommand (_28, 0);
  _29 = DmaReturnStatus_80 == 0;
  DevAssert (_29);
  goto <bb 19>; [INV]

  <bb 11> :
  Flexio_Uart_Ip_SetShifterInterrupt (Channel_57(D), 0);
  _30 = (int) Channel_57(D);
  _31 = 1 << _30;
  _32 = (unsigned char) _31;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_63, _32, 0);
  _33 = (int) Channel_57(D);
  _34 = 1 << _33;
  _35 = (unsigned char) _34;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base_63, _35, 0);
  _36 = (int) Channel_57(D);
  _37 = 1 << _36;
  _38 = (unsigned char) _37;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base_63, _38, 0);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 12> :
  _39 = Flexio_Mcl_Ip_GetTimerStatus (Base_63, Channel_57(D));
  _40 = ~_39;
  if (_40 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  TimeoutTicks.19_41 = TimeoutTicks;
  _42 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.19_41, 0);
  _43 = ~_42;
  if (_43 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 14> :
  TimeoutTicks.20_44 = TimeoutTicks;
  _45 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.20_44, 0);
  if (_45 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  UartState_61->Status ={v} 1;

  <bb 16> :
  UartState_61->DriverIdle ={v} 0;
  _46 ={v} UartState_61->Status;
  if (_46 == 2)
    goto <bb 17>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 17> :
  UartState_61->Status ={v} 0;
  _47 = UartUserCfg_62->Callback;
  if (_47 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _48 = UartUserCfg_62->Callback;
  _49 = (long unsigned int) Channel_57(D);
  _50 = UartUserCfg_62->CallbackParam;
  _48 (_49, 2, _50);

  <bb 19> :
  DmaTransferList ={v} {CLOBBER};
  DmaStatus ={v} {CLOBBER};
  StartTime ={v} {CLOBBER};
  TimeoutTicks ={v} {CLOBBER};
  ElapsedTicks ={v} {CLOBBER};
  return;

}



;; Function Flexio_Uart_Ip_AbortTransferData (Flexio_Uart_Ip_AbortTransferData, funcdef_no=47, decl_uid=6003, cgraph_uid=48, symbol_order=51)

Flexio_Uart_Ip_AbortTransferData (const uint8 Channel)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7015;
  _Bool _1;
  int _2;
  int _3;
  _Bool _4;
  _Bool _5;
  _Bool _6;
  _Bool _7;
  <unnamed type> _8;
  unsigned char _9;
  long unsigned int _10;
  <unnamed type> _11;
  Flexio_Uart_Ip_StatusType _30;

  <bb 2> :
  _1 = Channel_15(D) <= 3;
  DevAssert (_1);
  RetStatus_18 = 1;
  _2 = (int) Channel_15(D);
  UartState_19 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel_15(D);
  UartUserCfg_20 = Flexio_Uart_Ip_apUserConfig[_3];
  _4 = UartState_19 != 0B;
  DevAssert (_4);
  _5 = UartUserCfg_20 != 0B;
  DevAssert (_5);
  _6 ={v} UartState_19->DriverIdle;
  _7 = ~_6;
  if (_7 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus_29 = 0;
  goto <bb 10>; [INV]

  <bb 4> :
  UartState_19->Status ={v} 516;
  _8 = UartUserCfg_20->DriverType;
  if (_8 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Uart_Ip_StopTransfer (Channel_15(D));
  goto <bb 9>; [INV]

  <bb 6> :
  _9 = UartUserCfg_20->DmaChannel;
  _10 = (long unsigned int) _9;
  Dma_Ip_SetLogicChannelCommand (_10, 1);
  _11 = UartUserCfg_20->Direction;
  if (_11 == 1)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  Flexio_Uart_Ip_CompleteSendUsingDma (Channel_15(D));
  goto <bb 9>; [INV]

  <bb 8> :
  Flexio_Uart_Ip_CompleteReceiveUsingDma (Channel_15(D));

  <bb 9> :
  RetStatus_28 = 0;

  <bb 10> :
  # RetStatus_12 = PHI <RetStatus_29(3), RetStatus_28(9)>
  _30 = RetStatus_12;

  <bb 11> :
<L9>:
  return _30;

}



;; Function Flexio_Uart_Ip_SetBaudRate (Flexio_Uart_Ip_SetBaudRate, funcdef_no=48, decl_uid=5976, cgraph_uid=49, symbol_order=52)

Flexio_Uart_Ip_SetBaudRate (const uint8 Channel, const Flexio_Uart_Ip_BaudrateType DesiredBaudrate, const uint32 ClockFrequency)
{
  uint16 BitCountValue;
  sint32 Divider;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType Status;
  Flexio_Uart_Ip_TimerDecrementType TimerDecrement;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7040;
  int iftmp.30;
  int iftmp.23;
  _Bool _1;
  _Bool _2;
  int _3;
  int _4;
  <unnamed type> _5;
  _Bool _6;
  _Bool _7;
  <unnamed type> _8;
  long int ClockFrequency.21_9;
  long int DesiredBaudrate.22_10;
  long int _11;
  long int _12;
  _Bool _13;
  long unsigned int Divider.24_14;
  long unsigned int _15;
  long unsigned int _16;
  long unsigned int _17;
  long int ClockFrequency.25_18;
  long int DesiredBaudrate.26_19;
  long int _20;
  long int _21;
  long unsigned int Divider.27_22;
  long unsigned int _23;
  long unsigned int _24;
  long unsigned int _25;
  long int ClockFrequency.28_26;
  long int DesiredBaudrate.29_27;
  long int _28;
  long int _29;
  _Bool _30;
  long unsigned int Divider.31_31;
  long unsigned int _32;
  long unsigned int _33;
  long unsigned int _34;
  short unsigned int _35;
  short unsigned int _36;
  short unsigned int _37;
  unsigned char _38;
  short unsigned int _39;
  short unsigned int _40;
  <unnamed type> _41;
  int iftmp.23_45;
  int iftmp.30_46;
  int iftmp.30_66;
  int iftmp.30_67;
  int iftmp.23_72;
  int iftmp.23_73;
  Flexio_Uart_Ip_StatusType _85;

  <bb 2> :
  _1 = Channel_50(D) <= 3;
  DevAssert (_1);
  _2 = ClockFrequency_53(D) != 0;
  DevAssert (_2);
  _3 = (int) Channel_50(D);
  UartState_55 = Flexio_Uart_Ip_apStateStructuresArray[_3];
  _4 = (int) Channel_50(D);
  UartUserCfg_56 = Flexio_Uart_Ip_apUserConfig[_4];
  Base_57 = 1074110464B;
  _5 = UartUserCfg_56->BitCount;
  BitCountValue_58 = (uint16) _5;
  _6 = UartState_55 != 0B;
  DevAssert (_6);
  _7 ={v} UartState_55->DriverIdle;
  if (_7 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  Status_84 = 2;
  goto <bb 22>; [INV]

  <bb 4> :
  _8 = UartUserCfg_56->TimerDec;
  if (_8 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 5> :
  TimerDecrement_70 = 0;
  ClockFrequency.21_9 = (long int) ClockFrequency_53(D);
  DesiredBaudrate.22_10 = (long int) DesiredBaudrate_60(D);
  _11 = DesiredBaudrate.22_10 * 2;
  _12 = ClockFrequency.21_9 / _11;
  Divider_71 = _12 + -1;
  if (Divider_71 <= 255)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  if (Divider_71 >= 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  iftmp.23_72 = 1;
  goto <bb 9>; [INV]

  <bb 8> :
  iftmp.23_73 = 0;

  <bb 9> :
  # iftmp.23_45 = PHI <iftmp.23_72(7), iftmp.23_73(8)>
  _13 = (_Bool) iftmp.23_45;
  DevAssert (_13);
  Divider.24_14 = (long unsigned int) Divider_71;
  _15 = Divider.24_14 + 1;
  _16 = _15 * 2;
  _17 = ClockFrequency_53(D) / _16;
  UartState_55->BaudRate = _17;
  goto <bb 18>; [INV]

  <bb 10> :
  ClockFrequency.25_18 = (long int) ClockFrequency_53(D);
  DesiredBaudrate.26_19 = (long int) DesiredBaudrate_60(D);
  _20 = DesiredBaudrate.26_19 * 32;
  _21 = ClockFrequency.25_18 / _20;
  Divider_61 = _21 + -1;
  if (Divider_61 <= 255)
    goto <bb 11>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 11> :
  if (Divider_61 >= 0)
    goto <bb 12>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 12> :
  TimerDecrement_62 = 4;
  Divider.27_22 = (long unsigned int) Divider_61;
  _23 = Divider.27_22 + 1;
  _24 = _23 * 32;
  _25 = ClockFrequency_53(D) / _24;
  UartState_55->BaudRate = _25;
  goto <bb 18>; [INV]

  <bb 13> :
  TimerDecrement_64 = 5;
  ClockFrequency.28_26 = (long int) ClockFrequency_53(D);
  DesiredBaudrate.29_27 = (long int) DesiredBaudrate_60(D);
  _28 = DesiredBaudrate.29_27 * 512;
  _29 = ClockFrequency.28_26 / _28;
  Divider_65 = _29 + -1;
  if (Divider_65 <= 255)
    goto <bb 14>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 14> :
  if (Divider_65 >= 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  iftmp.30_66 = 1;
  goto <bb 17>; [INV]

  <bb 16> :
  iftmp.30_67 = 0;

  <bb 17> :
  # iftmp.30_46 = PHI <iftmp.30_66(15), iftmp.30_67(16)>
  _30 = (_Bool) iftmp.30_46;
  DevAssert (_30);
  Divider.31_31 = (long unsigned int) Divider_65;
  _32 = Divider.31_31 + 1;
  _33 = _32 * 512;
  _34 = ClockFrequency_53(D) / _33;
  UartState_55->BaudRate = _34;

  <bb 18> :
  # TimerDecrement_42 = PHI <TimerDecrement_70(9), TimerDecrement_62(12), TimerDecrement_64(17)>
  # Divider_44 = PHI <Divider_71(9), Divider_61(12), Divider_65(17)>
  _35 = BitCountValue_58 << 1;
  _36 = _35 + 65535;
  _37 = _36 << 8;
  _38 = (unsigned char) Divider_44;
  _39 = (short unsigned int) _38;
  _40 = _37 + _39;
  Flexio_Uart_Ip_SetTimerCompare (Base_57, Channel_50(D), _40);
  _41 = UartUserCfg_56->Direction;
  if (_41 == 1)
    goto <bb 19>; [INV]
  else
    goto <bb 20>; [INV]

  <bb 19> :
  Flexio_Uart_Ip_SetTimerConfig (Base_57, Channel_50(D), 0, TimerDecrement_42, 0);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base_57, Channel_50(D), 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base_57, Channel_50(D), 2, 2);
  goto <bb 21>; [INV]

  <bb 20> :
  Flexio_Uart_Ip_SetTimerConfig (Base_57, Channel_50(D), 4, TimerDecrement_42, 2);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base_57, Channel_50(D), 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base_57, Channel_50(D), 4, 2);

  <bb 21> :
  Status_83 = 0;

  <bb 22> :
  # Status_43 = PHI <Status_84(3), Status_83(21)>
  _85 = Status_43;

  <bb 23> :
<L21>:
  return _85;

}



;; Function Flexio_Uart_Ip_SetTxBuffer (Flexio_Uart_Ip_SetTxBuffer, funcdef_no=49, decl_uid=6007, cgraph_uid=50, symbol_order=53)

Flexio_Uart_Ip_SetTxBuffer (const uint8 Channel, const uint8 * TxData, const uint32 TxSize)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7042;
  _Bool _1;
  _Bool _2;
  int _3;
  Flexio_Uart_Ip_StatusType _13;

  <bb 2> :
  _1 = TxData_4(D) != 0B;
  DevAssert (_1);
  _2 = TxSize_7(D) != 0;
  DevAssert (_2);
  _3 = (int) Channel_9(D);
  UartState_10 = Flexio_Uart_Ip_apStateStructuresArray[_3];
  UartState_10->TxData = TxData_4(D);
  UartState_10->RemainingBytes ={v} TxSize_7(D);
  _13 = 0;

  <bb 3> :
<L0>:
  return _13;

}



;; Function Flexio_Uart_Ip_SetRxBuffer (Flexio_Uart_Ip_SetRxBuffer, funcdef_no=50, decl_uid=6011, cgraph_uid=51, symbol_order=54)

Flexio_Uart_Ip_SetRxBuffer (const uint8 Channel, uint8 * RxData, const uint32 RxSize)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7044;
  _Bool _1;
  _Bool _2;
  int _3;
  Flexio_Uart_Ip_StatusType _13;

  <bb 2> :
  _1 = RxData_4(D) != 0B;
  DevAssert (_1);
  _2 = RxSize_7(D) != 0;
  DevAssert (_2);
  _3 = (int) Channel_9(D);
  UartState_10 = Flexio_Uart_Ip_apStateStructuresArray[_3];
  UartState_10->RxData = RxData_4(D);
  UartState_10->RemainingBytes ={v} RxSize_7(D);
  _13 = 0;

  <bb 3> :
<L0>:
  return _13;

}


