Flexio_Uart_Ip_SetRxBuffer (const uint8 Channel, uint8 * RxData, const uint32 RxSize)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7044;

  <bb 2> :
  _1 = RxData != 0B;
  DevAssert (_1);
  _2 = RxSize != 0;
  DevAssert (_2);
  _3 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_3];
  UartState->RxData = RxData;
  UartState->RemainingBytes = RxSize;
  D.7044 = 0;

  <bb 3> :
<L0>:
  return D.7044;

}


Flexio_Uart_Ip_SetTxBuffer (const uint8 Channel, const uint8 * TxData, const uint32 TxSize)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7042;

  <bb 2> :
  _1 = TxData != 0B;
  DevAssert (_1);
  _2 = TxSize != 0;
  DevAssert (_2);
  _3 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_3];
  UartState->TxData = TxData;
  UartState->RemainingBytes = TxSize;
  D.7042 = 0;

  <bb 3> :
<L0>:
  return D.7042;

}


Flexio_Uart_Ip_SetBaudRate (const uint8 Channel, const Flexio_Uart_Ip_BaudrateType DesiredBaudrate, const uint32 ClockFrequency)
{
  uint16 BitCountValue;
  sint32 Divider;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType Status;
  Flexio_Uart_Ip_TimerDecrementType TimerDecrement;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7040;
  int iftmp.30;
  int iftmp.23;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = ClockFrequency != 0;
  DevAssert (_2);
  _3 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_3];
  _4 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_4];
  Base = 1074110464B;
  _5 = UartUserCfg->BitCount;
  BitCountValue = (uint16) _5;
  _6 = UartState != 0B;
  DevAssert (_6);
  _7 = UartState->DriverIdle;
  if (_7 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  Status = 2;
  goto <bb 22>; [INV]

  <bb 4> :
  _8 = UartUserCfg->TimerDec;
  if (_8 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 5> :
  TimerDecrement = 0;
  ClockFrequency.21_9 = (long int) ClockFrequency;
  DesiredBaudrate.22_10 = (long int) DesiredBaudrate;
  _11 = DesiredBaudrate.22_10 * 2;
  _12 = ClockFrequency.21_9 / _11;
  Divider = _12 + -1;
  if (Divider <= 255)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  if (Divider >= 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  iftmp.23 = 1;
  goto <bb 9>; [INV]

  <bb 8> :
  iftmp.23 = 0;

  <bb 9> :
  _13 = (_Bool) iftmp.23;
  DevAssert (_13);
  Divider.24_14 = (long unsigned int) Divider;
  _15 = Divider.24_14 + 1;
  _16 = _15 * 2;
  _17 = ClockFrequency / _16;
  UartState->BaudRate = _17;
  goto <bb 18>; [INV]

  <bb 10> :
  ClockFrequency.25_18 = (long int) ClockFrequency;
  DesiredBaudrate.26_19 = (long int) DesiredBaudrate;
  _20 = DesiredBaudrate.26_19 * 32;
  _21 = ClockFrequency.25_18 / _20;
  Divider = _21 + -1;
  if (Divider <= 255)
    goto <bb 11>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 11> :
  if (Divider >= 0)
    goto <bb 12>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 12> :
  TimerDecrement = 4;
  Divider.27_22 = (long unsigned int) Divider;
  _23 = Divider.27_22 + 1;
  _24 = _23 * 32;
  _25 = ClockFrequency / _24;
  UartState->BaudRate = _25;
  goto <bb 18>; [INV]

  <bb 13> :
  TimerDecrement = 5;
  ClockFrequency.28_26 = (long int) ClockFrequency;
  DesiredBaudrate.29_27 = (long int) DesiredBaudrate;
  _28 = DesiredBaudrate.29_27 * 512;
  _29 = ClockFrequency.28_26 / _28;
  Divider = _29 + -1;
  if (Divider <= 255)
    goto <bb 14>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 14> :
  if (Divider >= 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  iftmp.30 = 1;
  goto <bb 17>; [INV]

  <bb 16> :
  iftmp.30 = 0;

  <bb 17> :
  _30 = (_Bool) iftmp.30;
  DevAssert (_30);
  Divider.31_31 = (long unsigned int) Divider;
  _32 = Divider.31_31 + 1;
  _33 = _32 * 512;
  _34 = ClockFrequency / _33;
  UartState->BaudRate = _34;

  <bb 18> :
  _35 = BitCountValue << 1;
  _36 = _35 + 65535;
  _37 = _36 << 8;
  _38 = (unsigned char) Divider;
  _39 = (short unsigned int) _38;
  _40 = _37 + _39;
  Flexio_Uart_Ip_SetTimerCompare (Base, Channel, _40);
  _41 = UartUserCfg->Direction;
  if (_41 == 1)
    goto <bb 19>; [INV]
  else
    goto <bb 20>; [INV]

  <bb 19> :
  Flexio_Uart_Ip_SetTimerConfig (Base, Channel, 0, TimerDecrement, 0);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base, Channel, 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base, Channel, 2, 2);
  goto <bb 21>; [INV]

  <bb 20> :
  Flexio_Uart_Ip_SetTimerConfig (Base, Channel, 4, TimerDecrement, 2);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base, Channel, 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base, Channel, 4, 2);

  <bb 21> :
  Status = 0;

  <bb 22> :
  D.7040 = Status;

  <bb 23> :
<L21>:
  return D.7040;

}


Flexio_Uart_Ip_AbortTransferData (const uint8 Channel)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.7015;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  RetStatus = 1;
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  _4 = UartState != 0B;
  DevAssert (_4);
  _5 = UartUserCfg != 0B;
  DevAssert (_5);
  _6 = UartState->DriverIdle;
  _7 = ~_6;
  if (_7 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus = 0;
  goto <bb 10>; [INV]

  <bb 4> :
  UartState->Status = 516;
  _8 = UartUserCfg->DriverType;
  if (_8 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Uart_Ip_StopTransfer (Channel);
  goto <bb 9>; [INV]

  <bb 6> :
  _9 = UartUserCfg->DmaChannel;
  _10 = (long unsigned int) _9;
  Dma_Ip_SetLogicChannelCommand (_10, 1);
  _11 = UartUserCfg->Direction;
  if (_11 == 1)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  Flexio_Uart_Ip_CompleteSendUsingDma (Channel);
  goto <bb 9>; [INV]

  <bb 8> :
  Flexio_Uart_Ip_CompleteReceiveUsingDma (Channel);

  <bb 9> :
  RetStatus = 0;

  <bb 10> :
  D.7015 = RetStatus;

  <bb 11> :
<L9>:
  return D.7015;

}


Flexio_Uart_Ip_CompleteReceiveUsingDma (uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  struct Dma_Ip_LogicChannelStatusType DmaStatus;
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  Base = 1074110464B;
  _4 = UartUserCfg->DmaChannel;
  _5 = (long unsigned int) _4;
  Dma_Ip_GetLogicChannelStatus (_5, &DmaStatus);
  _6 = DmaStatus.ChStateValue;
  if (_6 == 4)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _7 = UartUserCfg->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_8, 4);
  _9 = DmaReturnStatus == 0;
  DevAssert (_9);
  UartState->Status = 1;
  _10 = UartUserCfg->Callback;
  if (_10 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _11 = UartUserCfg->Callback;
  _12 = (long unsigned int) Channel;
  _13 = UartUserCfg->CallbackParam;
  _11 (_12, 3, _13);

  <bb 5> :
  _14 = UartState->Status;
  if (_14 == 2)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  _15 = UartUserCfg->Callback;
  if (_15 != 0B)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _16 = UartUserCfg->Callback;
  _17 = (long unsigned int) Channel;
  _18 = UartUserCfg->CallbackParam;
  _16 (_17, 0, _18);

  <bb 8> :
  _19 = UartState->RemainingBytes;
  if (_19 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 9> :
  _20 = UartState->Status;
  if (_20 != 1)
    goto <bb 10>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 10> :
  DmaTransferList[0].Param = 5;
  _21 = UartState->RxData;
  _22 = (long unsigned int) _21;
  DmaTransferList[0].Value = _22;
  DmaTransferList[1].Param = 18;
  _23 = UartState->RemainingBytes;
  DmaTransferList[1].Value = _23;
  _24 = UartUserCfg->DmaChannel;
  _25 = (long unsigned int) _24;
  DmaReturnStatus = Dma_Ip_SetLogicChannelTransferList (_25, &DmaTransferList, 2);
  _26 = DmaReturnStatus == 0;
  DevAssert (_26);
  UartState->RemainingBytes = 0;
  _27 = UartUserCfg->DmaChannel;
  _28 = (long unsigned int) _27;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_28, 0);
  _29 = DmaReturnStatus == 0;
  DevAssert (_29);
  goto <bb 19>; [INV]

  <bb 11> :
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 0);
  _30 = (int) Channel;
  _31 = 1 << _30;
  _32 = (unsigned char) _31;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _32, 0);
  _33 = (int) Channel;
  _34 = 1 << _33;
  _35 = (unsigned char) _34;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base, _35, 0);
  _36 = (int) Channel;
  _37 = 1 << _36;
  _38 = (unsigned char) _37;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _38, 0);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 12> :
  _39 = Flexio_Mcl_Ip_GetTimerStatus (Base, Channel);
  _40 = ~_39;
  if (_40 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  TimeoutTicks.19_41 = TimeoutTicks;
  _42 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.19_41, 0);
  _43 = ~_42;
  if (_43 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 14> :
  TimeoutTicks.20_44 = TimeoutTicks;
  _45 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.20_44, 0);
  if (_45 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  UartState->Status = 1;

  <bb 16> :
  UartState->DriverIdle = 0;
  _46 = UartState->Status;
  if (_46 == 2)
    goto <bb 17>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 17> :
  UartState->Status = 0;
  _47 = UartUserCfg->Callback;
  if (_47 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _48 = UartUserCfg->Callback;
  _49 = (long unsigned int) Channel;
  _50 = UartUserCfg->CallbackParam;
  _48 (_49, 2, _50);

  <bb 19> :
  DmaTransferList = {CLOBBER};
  DmaStatus = {CLOBBER};
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};
  return;

}


Flexio_Uart_Ip_CompleteSendUsingDma (uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  struct Dma_Ip_LogicChannelStatusType DmaStatus;
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  Base = 1074110464B;
  _4 = UartUserCfg->DmaChannel;
  _5 = (long unsigned int) _4;
  Dma_Ip_GetLogicChannelStatus (_5, &DmaStatus);
  _6 = DmaStatus.ChStateValue;
  if (_6 == 4)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _7 = UartUserCfg->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_8, 4);
  _9 = DmaReturnStatus == 0;
  DevAssert (_9);
  UartState->Status = 1;
  _10 = UartUserCfg->Callback;
  if (_10 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _11 = UartUserCfg->Callback;
  _12 = (long unsigned int) Channel;
  _13 = UartUserCfg->CallbackParam;
  _11 (_12, 3, _13);

  <bb 5> :
  _14 = UartState->Status;
  if (_14 == 2)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  _15 = UartUserCfg->Callback;
  if (_15 != 0B)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _16 = UartUserCfg->Callback;
  _17 = (long unsigned int) Channel;
  _18 = UartUserCfg->CallbackParam;
  _16 (_17, 1, _18);

  <bb 8> :
  _19 = UartState->RemainingBytes;
  if (_19 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 9> :
  _20 = UartState->Status;
  if (_20 != 1)
    goto <bb 10>; [INV]
  else
    goto <bb 11>; [INV]

  <bb 10> :
  DmaTransferList[0].Param = 0;
  _21 = UartState->TxData;
  _22 = (long unsigned int) _21;
  DmaTransferList[0].Value = _22;
  DmaTransferList[1].Param = 18;
  _23 = UartState->RemainingBytes;
  DmaTransferList[1].Value = _23;
  _24 = UartUserCfg->DmaChannel;
  _25 = (long unsigned int) _24;
  DmaReturnStatus = Dma_Ip_SetLogicChannelTransferList (_25, &DmaTransferList, 2);
  _26 = DmaReturnStatus == 0;
  DevAssert (_26);
  UartState->RemainingBytes = 0;
  _27 = UartUserCfg->DmaChannel;
  _28 = (long unsigned int) _27;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_28, 0);
  _29 = DmaReturnStatus == 0;
  DevAssert (_29);
  goto <bb 19>; [INV]

  <bb 11> :
  _30 = (int) Channel;
  _31 = 1 << _30;
  _32 = (unsigned char) _31;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base, _32, 0);
  _33 = (int) Channel;
  _34 = 1 << _33;
  _35 = (unsigned char) _34;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _35, 0);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 12> :
  _36 = Flexio_Mcl_Ip_GetTimerStatus (Base, Channel);
  _37 = ~_36;
  if (_37 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  TimeoutTicks.17_38 = TimeoutTicks;
  _39 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.17_38, 0);
  _40 = ~_39;
  if (_40 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 14> :
  TimeoutTicks.18_41 = TimeoutTicks;
  _42 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.18_41, 0);
  if (_42 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 16>; [INV]

  <bb 15> :
  UartState->Status = 1;

  <bb 16> :
  UartState->DriverIdle = 0;
  _43 = UartState->Status;
  if (_43 == 2)
    goto <bb 17>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 17> :
  UartState->Status = 0;
  _44 = UartUserCfg->Callback;
  if (_44 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _45 = UartUserCfg->Callback;
  _46 = (long unsigned int) Channel;
  _47 = UartUserCfg->CallbackParam;
  _45 (_46, 2, _47);

  <bb 19> :
  DmaTransferList = {CLOBBER};
  DmaStatus = {CLOBBER};
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};
  return;

}


Flexio_Uart_Ip_SyncReceive (const uint8 Channel, uint8 * RxBuff, const uint32 RxSize, const uint32 Timeout)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  struct FLEXIO_Type * Base;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6965;
  int iftmp.13;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = RxBuff != 0B;
  DevAssert (_2);
  _3 = RxSize != 0;
  DevAssert (_3);
  ElapsedTicks = 0;
  Base = 1074110464B;
  RetStatus = 1;
  _4 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_4];
  _5 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_5];
  _6 = UartState != 0B;
  DevAssert (_6);
  _7 = UartUserCfg->Direction;
  _8 = _7 == 0;
  DevAssert (_8);
  _9 = UartUserCfg->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = RxSize & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.13 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.13 = 0;

  <bb 6> :
  _11 = (_Bool) iftmp.13;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_07 ();
  _12 = UartState->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07 ();
  RetStatus = 2;
  goto <bb 22>; [INV]

  <bb 8> :
  UartState->DriverIdle = 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_07 ();
  UartState->RxData = RxBuff;
  UartState->RemainingBytes = RxSize;
  UartState->Status = 2;
  Flexio_Uart_Ip_SetupReceiveData (Channel);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, Timeout, 0);
  goto <bb 15>; [INV]

  <bb 9> :

  <bb 10> :
  _13 = Flexio_Mcl_Ip_GetShifterStatus (Base, Channel);
  _14 = ~_13;
  if (_14 != 0)
    goto <bb 11>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 11> :
  TimeoutTicks.14_15 = TimeoutTicks;
  _16 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.14_15, 0);
  _17 = ~_16;
  if (_17 != 0)
    goto <bb 10>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 12> :
  Flexio_Uart_Ip_CheckShifterErrorStatus (Channel);
  _18 = UartState->Status;
  if (_18 == 1)
    goto <bb 13>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 13> :
  goto <bb 17>; [INV]

  <bb 14> :
  Flexio_Uart_Ip_ReadData (Channel);

  <bb 15> :
  _19 = UartState->RemainingBytes;
  if (_19 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  TimeoutTicks.15_20 = TimeoutTicks;
  _21 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.15_20, 0);
  _22 = ~_21;
  if (_22 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 17> :
  _23 = UartState->Status;
  if (_23 == 2)
    goto <bb 18>; [INV]
  else
    goto <bb 21>; [INV]

  <bb 18> :
  TimeoutTicks.16_24 = TimeoutTicks;
  _25 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.16_24, 0);
  if (_25 != 0)
    goto <bb 19>; [INV]
  else
    goto <bb 20>; [INV]

  <bb 19> :
  UartState->Status = 518;
  goto <bb 21>; [INV]

  <bb 20> :
  UartState->Status = 0;

  <bb 21> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base, Channel);
  UartState->DriverIdle = 0;
  RetStatus = UartState->Status;

  <bb 22> :
  D.6965 = RetStatus;
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};

  <bb 23> :
<L23>:
  return D.6965;

}


Flexio_Uart_Ip_AsyncReceive (const uint8 Channel, uint8 * RxBuff, const uint32 RxSize)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6946;
  int iftmp.12;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  RetStatus = 1;
  _4 = UartState != 0B;
  DevAssert (_4);
  _5 = RxBuff != 0B;
  DevAssert (_5);
  _6 = RxSize != 0;
  DevAssert (_6);
  _7 = UartUserCfg->Direction;
  _8 = _7 == 0;
  DevAssert (_8);
  _9 = UartUserCfg->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = RxSize & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.12 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.12 = 0;

  <bb 6> :
  _11 = (_Bool) iftmp.12;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_06 ();
  _12 = UartState->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06 ();
  RetStatus = 2;
  goto <bb 12>; [INV]

  <bb 8> :
  UartState->DriverIdle = 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_06 ();
  UartState->RxData = RxBuff;
  UartState->RemainingBytes = RxSize;
  UartState->Status = 2;
  Flexio_Uart_Ip_EnableReceiver (Channel);
  _13 = UartUserCfg->DriverType;
  switch (_13) <default: <L8> [INV], case 0: <L6> [INV], case 1: <L7> [INV]>

  <bb 9> :
<L6>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 1);
  RetStatus = 0;
  goto <bb 12>; [INV]

  <bb 10> :
<L7>:
  RetStatus = Flexio_Uart_Ip_StartReceiveDataUsingDma (Channel, RxBuff, RxSize);
  goto <bb 12>; [INV]

  <bb 11> :
<L8>:

  <bb 12> :
  D.6946 = RetStatus;

  <bb 13> :
<L11>:
  return D.6946;

}


Flexio_Uart_Ip_SyncSend (const uint8 Channel, const uint8 * TxBuff, const uint32 TxSize, const uint32 Timeout)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType D.6935;
  unsigned char iftmp.8;
  int iftmp.7;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = TxBuff != 0B;
  DevAssert (_2);
  _3 = TxSize != 0;
  DevAssert (_3);
  ElapsedTicks = 0;
  RetStatus = 1;
  _4 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_4];
  _5 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_5];
  Base = 1074110464B;
  _6 = UartState != 0B;
  DevAssert (_6);
  _7 = UartUserCfg->Direction;
  _8 = _7 == 1;
  DevAssert (_8);
  _9 = UartUserCfg->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = TxSize & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.7 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.7 = 0;

  <bb 6> :
  _11 = (_Bool) iftmp.7;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_05 ();
  _12 = UartState->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05 ();
  RetStatus = 2;
  goto <bb 22>; [INV]

  <bb 8> :
  UartState->DriverIdle = 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_05 ();
  UartState->TxData = TxBuff;
  UartState->RemainingBytes = TxSize;
  UartState->Status = 2;
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 0);
  if (TxSize == 1)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  iftmp.8 = 1;
  goto <bb 11>; [INV]

  <bb 10> :
  iftmp.8 = 2;

  <bb 11> :
  UartState->TxFlush = iftmp.8;
  Flexio_Uart_Ip_SetTimerMode (Base, Channel, 1);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, Timeout, 0);
  goto <bb 15>; [INV]

  <bb 12> :
  Flexio_Uart_Ip_WriteData (Channel);

  <bb 13> :
  _13 = Flexio_Mcl_Ip_GetShifterStatus (Base, Channel);
  _14 = ~_13;
  if (_14 != 0)
    goto <bb 14>; [INV]
  else
    goto <bb 15>; [INV]

  <bb 14> :
  TimeoutTicks.9_15 = TimeoutTicks;
  _16 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.9_15, 0);
  _17 = ~_16;
  if (_17 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 15>; [INV]

  <bb 15> :
  _18 = UartState->RemainingBytes;
  if (_18 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  TimeoutTicks.10_19 = TimeoutTicks;
  _20 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.10_19, 0);
  _21 = ~_20;
  if (_21 != 0)
    goto <bb 12>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 17> :
  TimeoutTicks.11_22 = TimeoutTicks;
  _23 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.11_22, 0);
  if (_23 != 0)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  UartState->Status = 518;

  <bb 19> :
  _24 = UartState->Status;
  if (_24 == 2)
    goto <bb 20>; [INV]
  else
    goto <bb 21>; [INV]

  <bb 20> :
  UartState->Status = 0;

  <bb 21> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base, Channel);
  UartState->DriverIdle = 0;
  RetStatus = UartState->Status;

  <bb 22> :
  D.6935 = RetStatus;
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};

  <bb 23> :
<L23>:
  return D.6935;

}


Flexio_Uart_Ip_GetStatus (const uint8 Channel, uint32 * BytesRemaining)
{
  const Dma_Ip_LogicChannelInfoParamType DmaLogicChnParam;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6915;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  DmaLogicChnParam = 3;
  _4 = UartState != 0B;
  DevAssert (_4);
  if (BytesRemaining != 0B)
    goto <bb 3>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 3> :
  _5 = UartState->DriverIdle;
  if (_5 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 4> :
  _6 = UartUserCfg->DriverType;
  if (_6 == 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  _7 = UartState->RemainingBytes;
  *BytesRemaining = _7;
  goto <bb 8>; [INV]

  <bb 6> :
  _8 = UartUserCfg->DmaChannel;
  _9 = (long unsigned int) _8;
  Dma_Ip_GetLogicChannelParam (_9, DmaLogicChnParam, BytesRemaining);
  goto <bb 8>; [INV]

  <bb 7> :
  *BytesRemaining = 0;

  <bb 8> :
  D.6915 = UartState->Status;

  <bb 9> :
<L8>:
  return D.6915;

}


Flexio_Uart_Ip_AsyncSend (const uint8 Channel, const uint8 * TxBuff, const uint32 TxSize)
{
  Flexio_Uart_Ip_StatusType RetStatus;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;
  Flexio_Uart_Ip_StatusType D.6905;
  unsigned char iftmp.6;
  int iftmp.5;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_3];
  RetStatus = 1;
  _4 = UartState != 0B;
  DevAssert (_4);
  _5 = TxBuff != 0B;
  DevAssert (_5);
  _6 = TxSize != 0;
  DevAssert (_6);
  _7 = UartUserCfg->Direction;
  _8 = _7 == 1;
  DevAssert (_8);
  _9 = UartUserCfg->BitCount;
  if (_9 <= 8)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  _10 = TxSize & 1;
  if (_10 == 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  iftmp.5 = 1;
  goto <bb 6>; [INV]

  <bb 5> :
  iftmp.5 = 0;

  <bb 6> :
  _11 = (_Bool) iftmp.5;
  DevAssert (_11);
  SchM_Enter_Uart_UART_EXCLUSIVE_AREA_04 ();
  _12 = UartState->DriverIdle;
  if (_12 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04 ();
  RetStatus = 2;
  goto <bb 15>; [INV]

  <bb 8> :
  UartState->DriverIdle = 1;
  SchM_Exit_Uart_UART_EXCLUSIVE_AREA_04 ();
  Base = 1074110464B;
  UartState->TxData = TxBuff;
  UartState->RemainingBytes = TxSize;
  UartState->Status = 2;
  if (TxSize == 1)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  iftmp.6 = 1;
  goto <bb 11>; [INV]

  <bb 10> :
  iftmp.6 = 2;

  <bb 11> :
  UartState->TxFlush = iftmp.6;
  Flexio_Uart_Ip_SetTimerMode (Base, Channel, 1);
  _13 = UartUserCfg->DriverType;
  switch (_13) <default: <L11> [INV], case 0: <L9> [INV], case 1: <L10> [INV]>

  <bb 12> :
<L9>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 1);
  RetStatus = 0;
  goto <bb 15>; [INV]

  <bb 13> :
<L10>:
  RetStatus = Flexio_Uart_Ip_StartSendDataUsingDma (Channel, TxBuff, TxSize);
  goto <bb 15>; [INV]

  <bb 14> :
<L11>:

  <bb 15> :
  D.6905 = RetStatus;

  <bb 16> :
<L14>:
  return D.6905;

}


Flexio_Uart_Ip_Deinit (const uint8 Channel)
{
  struct FLEXIO_Type * Base;
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  ElapsedTicks = 0;
  Base = 1074110464B;
  _2 = (int) Channel;
  _3 = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _4 = _3 != 0B;
  DevAssert (_4);
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 3> :
  _5 = Flexio_Uart_Ip_GetStatus (Channel, 0B);
  if (_5 == 2)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  TimeoutTicks.4_6 = TimeoutTicks;
  _7 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.4_6, 0);
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 5> :
  _9 = (int) Channel;
  Flexio_Uart_Ip_apStateStructuresArray[_9] = 0B;
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 0);
  Flexio_Mcl_Ip_SetSoftwareReset (Base, 1);
  Flexio_Mcl_Ip_SetSoftwareReset (Base, 0);
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};
  return;

}


Flexio_Uart_Ip_GetBaudRate (const uint8 Channel, uint32 * BaudRate)
{
  const struct Flexio_Uart_Ip_StateStructureType * UartState;

  <bb 2> :
  _1 = Channel <= 3;
  DevAssert (_1);
  _2 = BaudRate != 0B;
  DevAssert (_2);
  _3 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_3];
  _4 = UartState->BaudRate;
  *BaudRate = _4;
  return;

}


Flexio_Uart_Ip_Init (const uint8 Channel, const struct Flexio_Uart_Ip_UserConfigType * UserConfig)
{
  struct Flexio_Uart_Ip_StateStructureType * UartStatePtr;

  <bb 2> :
  UartStatePtr = UserConfig->StateStruct;
  _1 = (int) Channel;
  _2 = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _3 = _2 == 0B;
  DevAssert (_3);
  _4 = Channel <= 3;
  DevAssert (_4);
  _5 = (long unsigned int) Channel;
  _6 = UserConfig->Channel;
  _7 = _5 == _6;
  DevAssert (_7);
  _8 = (int) Channel;
  _9 = UserConfig->StateStruct;
  Flexio_Uart_Ip_apStateStructuresArray[_8] = _9;
  _10 = (int) Channel;
  Flexio_Uart_Ip_apUserConfig[_10] = UserConfig;
  UartStatePtr->RxData = 0B;
  UartStatePtr->TxData = 0B;
  UartStatePtr->RemainingBytes = 0;
  _11 = UserConfig->BaudRate;
  UartStatePtr->BaudRate = _11;
  UartStatePtr->Status = 0;
  UartStatePtr->DriverIdle = 0;
  _12 = UserConfig->Direction;
  if (_12 == 1)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _13 = UserConfig->BitCount;
  _14 = UserConfig->Divider;
  _15 = UserConfig->DataPin;
  _16 = UserConfig->TimerDec;
  Flexio_Uart_Ip_ConfigureTx (Channel, _13, _14, _15, _16);
  goto <bb 5>; [INV]

  <bb 4> :
  _17 = UserConfig->BitCount;
  _18 = UserConfig->Divider;
  _19 = UserConfig->DataPin;
  _20 = UserConfig->TimerDec;
  Flexio_Uart_Ip_ConfigureRx (Channel, _17, _18, _19, _20);

  <bb 5> :
  return;

}


Flexio_Uart_Ip_StartReceiveDataUsingDma (uint8 Channel, uint8 * RxBuff, uint32 RxSize)
{
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UserConfig;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6886;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UserConfig = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  DmaTransferList[0].Param = 0;
  _3 = (int) Channel;
  _4 = &Base->SHIFTBUF[_3];
  _5 = (long unsigned int) _4;
  _6 = _5 + 3;
  DmaTransferList[0].Value = _6;
  DmaTransferList[1].Param = 5;
  RxBuff.3_7 = (long unsigned int) RxBuff;
  DmaTransferList[1].Value = RxBuff.3_7;
  DmaTransferList[2].Param = 1;
  DmaTransferList[2].Value = 0;
  DmaTransferList[3].Param = 6;
  DmaTransferList[3].Value = 1;
  DmaTransferList[4].Param = 18;
  DmaTransferList[4].Value = RxSize;
  DmaTransferList[5].Param = 15;
  DmaTransferList[5].Value = 1;
  DmaTransferList[6].Param = 8;
  DmaTransferList[6].Value = 0;
  DmaTransferList[7].Param = 3;
  DmaTransferList[7].Value = 0;
  DmaTransferList[8].Param = 21;
  DmaTransferList[8].Value = 1;
  DmaTransferList[9].Param = 23;
  DmaTransferList[9].Value = 1;
  UartState->RxData = RxBuff;
  UartState->RemainingBytes = 0;
  UartState->Status = 2;
  _8 = UserConfig->DmaChannel;
  _9 = (long unsigned int) _8;
  DmaReturnStatus = Dma_Ip_SetLogicChannelTransferList (_9, &DmaTransferList, 10);
  _10 = DmaReturnStatus == 0;
  DevAssert (_10);
  _11 = UserConfig->DmaChannel;
  _12 = (long unsigned int) _11;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_12, 0);
  _13 = DmaReturnStatus == 0;
  DevAssert (_13);
  _14 = (int) Channel;
  _15 = 1 << _14;
  _16 = (unsigned char) _15;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base, _16, 1);
  D.6886 = 0;
  DmaTransferList = {CLOBBER};

  <bb 3> :
<L1>:
  return D.6886;

}


Flexio_Uart_Ip_StartSendDataUsingDma (uint8 Channel, const uint8 * TxData, uint32 TxSize)
{
  Dma_Ip_ReturnType DmaReturnStatus;
  struct Dma_Ip_LogicChannelTransferListType DmaTransferList[10];
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UserConfig;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  Flexio_Uart_Ip_StatusType D.6883;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UserConfig = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  DmaTransferList[0].Param = 0;
  TxData.2_3 = (long unsigned int) TxData;
  DmaTransferList[0].Value = TxData.2_3;
  DmaTransferList[1].Param = 5;
  _4 = (int) Channel;
  _5 = &Base->SHIFTBUF[_4];
  _6 = (long unsigned int) _5;
  DmaTransferList[1].Value = _6;
  DmaTransferList[2].Param = 1;
  DmaTransferList[2].Value = 1;
  DmaTransferList[3].Param = 6;
  DmaTransferList[3].Value = 0;
  DmaTransferList[4].Param = 18;
  DmaTransferList[4].Value = TxSize;
  DmaTransferList[5].Param = 15;
  DmaTransferList[5].Value = 1;
  DmaTransferList[6].Param = 8;
  DmaTransferList[6].Value = 0;
  DmaTransferList[7].Param = 3;
  DmaTransferList[7].Value = 0;
  DmaTransferList[8].Param = 21;
  DmaTransferList[8].Value = 1;
  DmaTransferList[9].Param = 23;
  DmaTransferList[9].Value = 1;
  UartState->TxData = TxData;
  UartState->RemainingBytes = 0;
  UartState->Status = 2;
  _7 = UserConfig->DmaChannel;
  _8 = (long unsigned int) _7;
  DmaReturnStatus = Dma_Ip_SetLogicChannelTransferList (_8, &DmaTransferList, 10);
  _9 = DmaReturnStatus == 0;
  DevAssert (_9);
  _10 = UserConfig->DmaChannel;
  _11 = (long unsigned int) _10;
  DmaReturnStatus = Dma_Ip_SetLogicChannelCommand (_11, 0);
  _12 = DmaReturnStatus == 0;
  DevAssert (_12);
  _13 = (int) Channel;
  _14 = 1 << _13;
  _15 = (unsigned char) _14;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base, _15, 1);
  D.6883 = 0;
  DmaTransferList = {CLOBBER};

  <bb 3> :
<L1>:
  return D.6883;

}


Flexio_Uart_Ip_EnableReceiver (const uint8 Channel)
{
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base = 1074110464B;
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  Flexio_Uart_Ip_SetShifterMode (Base, Channel, 1);
  Flexio_Uart_Ip_SetTimerMode (Base, Channel, 1);
  return;

}


Flexio_Uart_Ip_SetupReceiveData (const uint8 Channel)
{
  <bb 2> :
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 0);
  Flexio_Uart_Ip_EnableReceiver (Channel);
  return;

}


Flexio_Uart_Ip_SetShifterInterrupt (const uint8 Channel, boolean Enable)
{
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base = 1074110464B;
  _1 = (int) Channel;
  _2 = 1 << _1;
  _3 = (unsigned char) _2;
  Flexio_Mcl_Ip_SetShifterInterrupt (Base, _3, Enable);
  _4 = (int) Channel;
  _5 = 1 << _4;
  _6 = (unsigned char) _5;
  Flexio_Mcl_Ip_SetShifterErrorInterrupt (Base, _6, Enable);
  return;

}


Flexio_Uart_Ip_CheckShifterErrorStatus (const uint8 Channel)
{
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base = 1074110464B;
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = Flexio_Mcl_Ip_GetShifterErrorStatus (Base, Channel);
  if (_2 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  UartState->Status = 1;
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base, Channel);

  <bb 4> :
  return;

}


Flexio_Uart_Ip_CheckRxOperation (const uint8 Channel, const uint8 ShifterMaskFlag, const uint8 ShifterErrMaskFlag)
{
  boolean IsReturn;
  uint32 ResourceMask;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  _3 = (int) Channel;
  ResourceMask = 1 << _3;
  IsReturn = 0;
  _4 = (long unsigned int) ShifterErrMaskFlag;
  _5 = ResourceMask & _4;
  if (_5 != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 7>; [INV]

  <bb 3> :
  _6 = Flexio_Uart_Ip_GetShifterErrorInterrupt (Base, Channel);
  _7 = ~_6;
  if (_7 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base, Channel);
  IsReturn = 1;
  goto <bb 13>; [INV]

  <bb 5> :
  UartState->Status = 514;
  UartState->RemainingBytes = 0;
  _8 = UartUserCfg->Callback;
  if (_8 != 0B)
    goto <bb 6>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 6> :
  _9 = UartUserCfg->Callback;
  _10 = (long unsigned int) Channel;
  _11 = UartUserCfg->CallbackParam;
  _9 (_10, 3, _11);
  goto <bb 13>; [INV]

  <bb 7> :
  _12 = (long unsigned int) ShifterMaskFlag;
  _13 = ResourceMask & _12;
  if (_13 != 0)
    goto <bb 8>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 8> :
  _14 = Flexio_Uart_Ip_GetShifterInterrupt (Base, Channel);
  _15 = ~_14;
  if (_15 != 0)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  IsReturn = 1;
  goto <bb 13>; [INV]

  <bb 10> :
  Flexio_Uart_Ip_ReadData (Channel);
  _16 = UartState->RemainingBytes;
  if (_16 == 0)
    goto <bb 11>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 11> :
  _17 = UartUserCfg->Callback;
  if (_17 != 0B)
    goto <bb 12>; [INV]
  else
    goto <bb 13>; [INV]

  <bb 12> :
  _18 = UartUserCfg->Callback;
  _19 = (long unsigned int) Channel;
  _20 = UartUserCfg->CallbackParam;
  _18 (_19, 0, _20);

  <bb 13> :
  _21 = UartState->RemainingBytes;
  if (_21 == 0)
    goto <bb 14>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 14> :
  _22 = ~IsReturn;
  if (_22 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 15> :
  _23 = UartState->Status;
  if (_23 == 2)
    goto <bb 16>; [INV]
  else
    goto <bb 17>; [INV]

  <bb 16> :
  UartState->Status = 0;

  <bb 17> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  Flexio_Uart_Ip_StopTransfer (Channel);
  _24 = UartUserCfg->Callback;
  if (_24 != 0B)
    goto <bb 18>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 18> :
  _25 = UartUserCfg->Callback;
  _26 = (long unsigned int) Channel;
  _27 = UartUserCfg->CallbackParam;
  _25 (_26, 2, _27);

  <bb 19> :
  return;

}


Flexio_Uart_Ip_ReadData (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  uint32 Data32b;
  const struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_2];
  _3 = UartState->RemainingBytes;
  _4 = _3 != 0;
  DevAssert (_4);
  _5 = UartState->RxData;
  _6 = _5 != 0B;
  DevAssert (_6);
  Base = 1074110464B;
  Data32b = Flexio_Uart_Ip_ReadShifterBuffer (Base, Channel);
  _7 = UartUserCfg->BitCount;
  _8 = 32 - _7;
  Data32b = Data32b >> _8;
  _9 = UartUserCfg->BitCount;
  if (_9 == 8)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _10 = UartState->RxData;
  _11 = (unsigned char) Data32b;
  *_10 = _11;
  _12 = UartState->RxData;
  _13 = _12 + 1;
  UartState->RxData = _13;
  _14 = UartState->RemainingBytes;
  _15 = _14 + 4294967295;
  UartState->RemainingBytes = _15;

  <bb 4> :
  return;

}


Flexio_Uart_Ip_CheckCompleteTransferData (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  _3 = UartState->RemainingBytes;
  if (_3 == 0)
    goto <bb 3>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 3> :
  _4 = UartUserCfg->Callback;
  if (_4 != 0B)
    goto <bb 4>; [INV]
  else
    goto <bb 5>; [INV]

  <bb 4> :
  _5 = UartUserCfg->Callback;
  _6 = (long unsigned int) Channel;
  _7 = UartUserCfg->CallbackParam;
  _5 (_6, 1, _7);

  <bb 5> :
  _8 = UartState->RemainingBytes;
  if (_8 == 0)
    goto <bb 6>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 6> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base, Channel);
  _9 = UartUserCfg->DriverType;
  if (_9 == 0)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  _10 = (int) Channel;
  _11 = 1 << _10;
  _12 = (unsigned char) _11;
  Flexio_Mcl_Ip_SetShifterInterrupt (Base, _12, 0);
  _13 = (int) Channel;
  _14 = 1 << _13;
  _15 = (unsigned char) _14;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _15, 1);

  <bb 8> :
  return;

}


Flexio_Uart_Ip_CheckTxOperation (const uint8 Channel, const uint8 ShifterMaskFlag, const uint8 TimerMaskFlag)
{
  boolean IsReturn;
  uint32 ResourceMask;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  _3 = (int) Channel;
  ResourceMask = 1 << _3;
  IsReturn = 0;
  _4 = UartState->RemainingBytes;
  if (_4 == 0)
    goto <bb 3>; [INV]
  else
    goto <bb 14>; [INV]

  <bb 3> :
  _5 = (long unsigned int) TimerMaskFlag;
  _6 = ResourceMask & _5;
  if (_6 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 4> :
  _7 = Flexio_Uart_Ip_GetTimerInterrupt (Base, Channel);
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base, Channel);
  IsReturn = 1;

  <bb 6> :
  _9 = ~IsReturn;
  if (_9 != 0)
    goto <bb 7>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 7> :
  _10 = UartState->TxFlush;
  _11 = _10;
  _12 = _11 + 255;
  UartState->TxFlush = _12;
  _13 = UartState->TxFlush;
  if (_13 == 0)
    goto <bb 8>; [INV]
  else
    goto <bb 12>; [INV]

  <bb 8> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  _14 = UartState->Status;
  if (_14 == 2)
    goto <bb 9>; [INV]
  else
    goto <bb 10>; [INV]

  <bb 9> :
  UartState->Status = 0;

  <bb 10> :
  Flexio_Uart_Ip_StopTransfer (Channel);
  _15 = UartUserCfg->Callback;
  if (_15 != 0B)
    goto <bb 11>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 11> :
  _16 = UartUserCfg->Callback;
  _17 = (long unsigned int) Channel;
  _18 = UartUserCfg->CallbackParam;
  _16 (_17, 2, _18);
  goto <bb 19>; [INV]

  <bb 12> :
  _19 = Flexio_Mcl_Ip_GetShifterStatus (Base, Channel);
  if (_19 != 0)
    goto <bb 13>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 13> :
  Flexio_Uart_Ip_SetShifterStartBit (Base, Channel, 3);
  Flexio_Uart_Ip_WriteShifterBuffer (Base, Channel, 4294967295);
  goto <bb 19>; [INV]

  <bb 14> :
  _20 = (long unsigned int) ShifterMaskFlag;
  _21 = ResourceMask & _20;
  if (_21 != 0)
    goto <bb 15>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 15> :
  _22 = UartState->RemainingBytes;
  if (_22 != 0)
    goto <bb 16>; [INV]
  else
    goto <bb 19>; [INV]

  <bb 16> :
  _23 = Flexio_Uart_Ip_GetShifterInterrupt (Base, Channel);
  _24 = ~_23;
  if (_24 != 0)
    goto <bb 17>; [INV]
  else
    goto <bb 18>; [INV]

  <bb 17> :
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  goto <bb 19>; [INV]

  <bb 18> :
  Flexio_Uart_Ip_WriteData (Channel);
  Flexio_Uart_Ip_CheckCompleteTransferData (Channel);

  <bb 19> :
  return;

}


Flexio_Uart_Ip_WriteData (const uint8 Channel)
{
  uint32 Data32b;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct FLEXIO_Type * Base;

  <bb 2> :
  Data32b = 0;
  _1 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_1];
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  _3 = UartState->TxData;
  _4 = _3 != 0B;
  DevAssert (_4);
  Base = 1074110464B;
  _5 = UartUserCfg->BitCount;
  if (_5 == 8)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  _6 = UartState->TxData;
  _7 = *_6;
  Data32b = (uint32) _7;
  _8 = UartState->TxData;
  _9 = _8 + 1;
  UartState->TxData = _9;
  _10 = UartState->RemainingBytes;
  _11 = _10 + 4294967295;
  UartState->RemainingBytes = _11;

  <bb 4> :
  Flexio_Uart_Ip_WriteShifterBuffer (Base, Channel, Data32b);
  return;

}


Flexio_Uart_Ip_StopTransfer (const uint8 Channel)
{
  uint32 ElapsedTicks;
  uint32 TimeoutTicks;
  uint32 StartTime;
  const struct Flexio_Uart_Ip_StateStructureType * UartState;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_1];
  Base = 1074110464B;
  ElapsedTicks = 0;
  _2 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_2];
  Flexio_Uart_Ip_EndTransfer (Channel);
  _3 = UartState->Status;
  if (_3 == 516)
    goto <bb 3>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 3> :
  Flexio_Uart_Ip_StartTimeout (&StartTime, &TimeoutTicks, 500000, 0);

  <bb 4> :
  _4 = Flexio_Mcl_Ip_GetTimerStatus (Base, Channel);
  _5 = ~_4;
  if (_5 != 0)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  TimeoutTicks.0_6 = TimeoutTicks;
  _7 = Flexio_Uart_Ip_CheckTimeout (&StartTime, &ElapsedTicks, TimeoutTicks.0_6, 0);
  _8 = ~_7;
  if (_8 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 6> :
  Flexio_Uart_Ip_SetTimerMode (Base, Channel, 0);
  Flexio_Uart_Ip_SetShifterMode (Base, Channel, 0);
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base, Channel);
  _9 = UartUserCfg->Direction;
  if (_9 == 1)
    goto <bb 7>; [INV]
  else
    goto <bb 8>; [INV]

  <bb 7> :
  Flexio_Uart_Ip_SetShifterStartBit (Base, Channel, 2);
  Flexio_Uart_Ip_SetShifterMode (Base, Channel, 2);

  <bb 8> :
  StartTime = {CLOBBER};
  TimeoutTicks = {CLOBBER};
  ElapsedTicks = {CLOBBER};
  return;

}


Flexio_Uart_Ip_EndTransfer (const uint8 Channel)
{
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;
  struct Flexio_Uart_Ip_StateStructureType * UartState;
  struct FLEXIO_Type * Base;

  <bb 2> :
  _1 = (int) Channel;
  UartState = Flexio_Uart_Ip_apStateStructuresArray[_1];
  _2 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_2];
  Base = 1074110464B;
  _3 = UartUserCfg->DriverType;
  switch (_3) <default: <L2> [INV], case 0: <L0> [INV], case 1: <L1> [INV]>

  <bb 3> :
<L0>:
  Flexio_Uart_Ip_SetShifterInterrupt (Channel, 0);
  _4 = (int) Channel;
  _5 = 1 << _4;
  _6 = (unsigned char) _5;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _6, 0);
  goto <bb 6>; [INV]

  <bb 4> :
<L1>:
  _7 = (int) Channel;
  _8 = 1 << _7;
  _9 = (unsigned char) _8;
  Flexio_Mcl_Ip_SetTimerInterrupt (Base, _9, 0);
  _10 = (int) Channel;
  _11 = 1 << _10;
  _12 = (unsigned char) _11;
  Flexio_Mcl_Ip_SetShifterDMARequest (Base, _12, 0);
  goto <bb 6>; [INV]

  <bb 5> :
<L2>:

  <bb 6> :
  UartState->RemainingBytes = 0;
  UartState->DriverIdle = 0;
  return;

}


Flexio_Uart_Ip_ConfigureRx (const uint8 Channel, const Flexio_Uart_Ip_BitCountPerCharType BitCount, const uint8 Divider, const uint8 DataPin, const Flexio_Uart_Ip_TimerDecrementType TimerDec)
{
  uint16 Bits;
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base = 1074110464B;
  Bits = (uint16) BitCount;
  Flexio_Uart_Ip_SetShifterConfig (Base, Channel, 2, 3, 0);
  Flexio_Uart_Ip_SetShifterControl (Base, Channel, 0, Channel, 1);
  Flexio_Uart_Ip_SetPinShifterControl (Base, Channel, DataPin, 0, 0);
  _1 = Bits << 1;
  _2 = _1 + 65535;
  _3 = _2 << 8;
  _4 = (short unsigned int) Divider;
  _5 = _3 + _4;
  Flexio_Uart_Ip_SetTimerCompare (Base, Channel, _5);
  Flexio_Uart_Ip_SetTimerConfig (Base, Channel, 4, TimerDec, 2);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base, Channel, 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base, Channel, 4, 2);
  Flexio_Uart_Ip_SetTimerControl (Base, Channel, 0);
  Flexio_Uart_Ip_SetTimerTrigger (Base, Channel, 0, 0, 0);
  Flexio_Uart_Ip_SetPinTimerControl (Base, Channel, DataPin, 1, 0);
  return;

}


Flexio_Uart_Ip_ConfigureTx (const uint8 Channel, const Flexio_Uart_Ip_BitCountPerCharType BitCount, const uint8 Divider, const uint8 DataPin, const Flexio_Uart_Ip_TimerDecrementType TimerDec)
{
  uint16 Bits;
  struct FLEXIO_Type * Base;

  <bb 2> :
  Base = 1074110464B;
  Bits = (uint16) BitCount;
  Flexio_Uart_Ip_SetShifterConfig (Base, Channel, 2, 3, 0);
  Flexio_Uart_Ip_SetShifterControl (Base, Channel, 2, Channel, 0);
  Flexio_Uart_Ip_SetPinShifterControl (Base, Channel, DataPin, 0, 3);
  _1 = Bits << 1;
  _2 = _1 + 65535;
  _3 = _2 << 8;
  _4 = (short unsigned int) Divider;
  _5 = _3 + _4;
  Flexio_Uart_Ip_SetTimerCompare (Base, Channel, _5);
  Flexio_Uart_Ip_SetTimerConfig (Base, Channel, 0, TimerDec, 0);
  Flexio_Uart_Ip_SetTimerStartStopBitConfig (Base, Channel, 1, 2);
  Flexio_Uart_Ip_SetTimerCondition (Base, Channel, 2, 2);
  Flexio_Uart_Ip_SetTimerControl (Base, Channel, 0);
  _6 = Channel << 2;
  _7 = _6 + 1;
  Flexio_Uart_Ip_SetTimerTrigger (Base, Channel, _7, 1, 1);
  Flexio_Uart_Ip_SetPinTimerControl (Base, Channel, 0, 0, 0);
  return;

}


Flexio_Uart_Ip_IrqHandler (uint8 Channel, uint8 ShifterMaskFlag, uint8 ShifterErrorMaskFlag, uint8 TimerMaskFlag)
{
  struct FLEXIO_Type * Base;
  const struct Flexio_Uart_Ip_UserConfigType * UartUserCfg;

  <bb 2> :
  _1 = (int) Channel;
  UartUserCfg = Flexio_Uart_Ip_apUserConfig[_1];
  Base = 1074110464B;
  if (UartUserCfg == 0B)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  Flexio_Mcl_Ip_ClearTimerStatus (Base, Channel);
  Flexio_Mcl_Ip_ClearShifterStatus (Base, Channel);
  Flexio_Mcl_Ip_ClearShifterErrorStatus (Base, Channel);
  goto <bb 7>; [INV]

  <bb 4> :
  _2 = UartUserCfg->Direction;
  if (_2 == 1)
    goto <bb 5>; [INV]
  else
    goto <bb 6>; [INV]

  <bb 5> :
  Flexio_Uart_Ip_CheckTxOperation (Channel, ShifterMaskFlag, TimerMaskFlag);
  goto <bb 7>; [INV]

  <bb 6> :
  Flexio_Uart_Ip_CheckRxOperation (Channel, ShifterMaskFlag, ShifterErrorMaskFlag);

  <bb 7> :
  return;

}


DevAssert (volatile boolean x)
{
  <bb 2> :
  x.1_1 = x;
  if (x.1_1 != 0)
    goto <bb 4>; [INV]
  else
    goto <bb 3>; [INV]

  <bb 3> :
  goto <bb 3>; [INV]

  <bb 4> :
  return;

}


Flexio_Uart_Ip_CheckTimeout (uint32 * StartTime, uint32 * ElapsedTicks, uint32 TimeoutTicks, OsIf_CounterType OsifCounter)
{
  uint32 CurrentElapsedTicks;
  boolean D.6794;

  <bb 2> :
  CurrentElapsedTicks = OsIf_GetElapsed (StartTime, OsifCounter);
  _1 = *ElapsedTicks;
  _2 = CurrentElapsedTicks + _1;
  *ElapsedTicks = _2;
  _3 = *ElapsedTicks;
  D.6794 = TimeoutTicks <= _3;

  <bb 3> :
<L0>:
  return D.6794;

}


Flexio_Uart_Ip_StartTimeout (uint32 * StartTimeOut, uint32 * TimeoutTicksOut, uint32 TimeoutUs, OsIf_CounterType OsifCounter)
{
  <bb 2> :
  _1 = OsIf_GetCounter (OsifCounter);
  *StartTimeOut = _1;
  _2 = OsIf_MicrosToTicks (TimeoutUs, OsifCounter);
  *TimeoutTicksOut = _2;
  return;

}


Flexio_Uart_Ip_GetShifterInterrupt (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6836;

  <bb 2> :
  RegValue = Base->SHIFTSIEN;
  _1 = (int) Shifter;
  _2 = RegValue >> _1;
  RegValue = _2 & 1;
  if (RegValue != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus = 0;

  <bb 5> :
  D.6836 = RetStatus;

  <bb 6> :
<L3>:
  return D.6836;

}


Flexio_Uart_Ip_GetShifterErrorInterrupt (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6879;

  <bb 2> :
  RegValue = Base->SHIFTEIEN;
  _1 = (int) Shifter;
  _2 = RegValue >> _1;
  RegValue = _2 & 1;
  if (RegValue != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus = 0;

  <bb 5> :
  D.6879 = RetStatus;

  <bb 6> :
<L3>:
  return D.6879;

}


Flexio_Uart_Ip_GetTimerInterrupt (const struct FLEXIO_Type * Base, uint8 Timer)
{
  uint32 RegValue;
  boolean RetStatus;
  boolean D.6831;

  <bb 2> :
  RegValue = Base->TIMIEN;
  _1 = (int) Timer;
  _2 = RegValue >> _1;
  RegValue = _2 & 1;
  if (RegValue != 0)
    goto <bb 3>; [INV]
  else
    goto <bb 4>; [INV]

  <bb 3> :
  RetStatus = 1;
  goto <bb 5>; [INV]

  <bb 4> :
  RetStatus = 0;

  <bb 5> :
  D.6831 = RetStatus;

  <bb 6> :
<L3>:
  return D.6831;

}


Flexio_Uart_Ip_ReadShifterBuffer (const struct FLEXIO_Type * Base, uint8 Shifter)
{
  uint32 Data;
  uint32 D.6848;

  <bb 2> :
  _1 = (int) Shifter;
  Data = Base->SHIFTBUF[_1];
  D.6848 = Data;

  <bb 3> :
<L0>:
  return D.6848;

}


Flexio_Uart_Ip_WriteShifterBuffer (struct FLEXIO_Type * Base, uint8 Shifter, uint32 Value)
{
  <bb 2> :
  _1 = (int) Shifter;
  Base->SHIFTBUF[_1] = Value;
  return;

}


Flexio_Uart_Ip_SetShifterStartBit (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterStartType Start)
{
  <bb 2> :
  _1 = (int) Shifter;
  _2 = Base->SHIFTCFG[_1];
  _3 = _2 & 4294967292;
  _4 = Start & 3;
  _5 = (int) Shifter;
  _6 = _3 | _4;
  Base->SHIFTCFG[_5] = _6;
  return;

}


Flexio_Uart_Ip_SetShifterMode (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterModeType Mode)
{
  <bb 2> :
  _1 = (int) Shifter;
  _2 = Base->SHIFTCTL[_1];
  _3 = _2 & 4294967288;
  _4 = Mode & 7;
  _5 = (int) Shifter;
  _6 = _3 | _4;
  Base->SHIFTCTL[_5] = _6;
  return;

}


Flexio_Uart_Ip_SetTimerMode (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerModeType Mode)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCTL[_1];
  _3 = _2 & 4294967292;
  _4 = Mode & 3;
  _5 = (int) Timer;
  _6 = _3 | _4;
  Base->TIMCTL[_5] = _6;
  return;

}


Flexio_Uart_Ip_SetPinTimerControl (struct FLEXIO_Type * Base, uint8 Timer, uint8 Pin, Flexio_Mcl_Ip_PinPolarityType PinPolarity, Flexio_Mcl_Ip_PinConfigType PinConfig)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCTL[_1];
  _3 = _2 & 4294965503;
  _4 = (long unsigned int) Pin;
  _5 = _4 << 8;
  _6 = _5 & 1792;
  _7 = (int) Timer;
  _8 = _3 | _6;
  Base->TIMCTL[_7] = _8;
  _9 = (int) Timer;
  _10 = Base->TIMCTL[_9];
  _11 = _10 & 4294967167;
  _12 = PinPolarity << 7;
  _13 = _12 & 255;
  _14 = (int) Timer;
  _15 = _11 | _13;
  Base->TIMCTL[_14] = _15;
  _16 = (int) Timer;
  _17 = Base->TIMCTL[_16];
  _18 = _17 & 4294770687;
  _19 = PinConfig << 16;
  _20 = _19 & 196608;
  _21 = (int) Timer;
  _22 = _18 | _20;
  Base->TIMCTL[_21] = _22;
  return;

}


Flexio_Uart_Ip_SetTimerTrigger (struct FLEXIO_Type * Base, uint8 Timer, uint8 Trigger, Flexio_Mcl_Ip_TriggerPolarityType TriggerPolarity, Flexio_Mcl_Ip_TriggerSourceType TriggerSource)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCTL[_1];
  _3 = _2 & 4290772991;
  _4 = TriggerSource << 22;
  _5 = _4 & 4194304;
  _6 = (int) Timer;
  _7 = _3 | _5;
  Base->TIMCTL[_6] = _7;
  _8 = (int) Timer;
  _9 = Base->TIMCTL[_8];
  _10 = _9 & 4286578687;
  _11 = TriggerPolarity << 23;
  _12 = _11 & 8388608;
  _13 = (int) Timer;
  _14 = _10 | _12;
  Base->TIMCTL[_13] = _14;
  _15 = (int) Timer;
  _16 = Base->TIMCTL[_15];
  _17 = _16 & 4043309055;
  _18 = (long unsigned int) Trigger;
  _19 = _18 << 24;
  _20 = _19 & 251658240;
  _21 = (int) Timer;
  _22 = _17 | _20;
  Base->TIMCTL[_21] = _22;
  return;

}


Flexio_Uart_Ip_SetTimerControl (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerModeType Mode)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCTL[_1];
  _3 = _2 & 4294967292;
  _4 = Mode & 3;
  _5 = (int) Timer;
  _6 = _3 | _4;
  Base->TIMCTL[_5] = _6;
  return;

}


Flexio_Uart_Ip_SetTimerCondition (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerEnableType Enable, Flexio_Mcl_Ip_TimerDisableType Disable)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCFG[_1];
  _3 = _2 & 4294965503;
  _4 = Enable << 8;
  _5 = _4 & 1792;
  _6 = (int) Timer;
  _7 = _3 | _5;
  Base->TIMCFG[_6] = _7;
  _8 = (int) Timer;
  _9 = Base->TIMCFG[_8];
  _10 = _9 & 4294938623;
  _11 = Disable << 12;
  _12 = _11 & 28672;
  _13 = (int) Timer;
  _14 = _10 | _12;
  Base->TIMCFG[_13] = _14;
  return;

}


Flexio_Uart_Ip_SetTimerStartStopBitConfig (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerStartType Start, Flexio_Mcl_Ip_TimerStopType Stop)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCFG[_1];
  _3 = _2 & 4294967293;
  _4 = Start << 1;
  _5 = _4 & 2;
  _6 = (int) Timer;
  _7 = _3 | _5;
  Base->TIMCFG[_6] = _7;
  _8 = (int) Timer;
  _9 = Base->TIMCFG[_8];
  _10 = _9 & 4294967247;
  _11 = Stop << 4;
  _12 = _11 & 48;
  _13 = (int) Timer;
  _14 = _10 | _12;
  Base->TIMCFG[_13] = _14;
  return;

}


Flexio_Uart_Ip_SetTimerConfig (struct FLEXIO_Type * Base, uint8 Timer, Flexio_Mcl_Ip_TimerResetType Reset, Flexio_Uart_Ip_TimerDecrementType Decrement, Flexio_Mcl_Ip_TimerOutputType Output)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = Base->TIMCFG[_1];
  _3 = _2 & 4294508543;
  _4 = Reset << 16;
  _5 = _4 & 458752;
  _6 = (int) Timer;
  _7 = _3 | _5;
  Base->TIMCFG[_6] = _7;
  _8 = (int) Timer;
  _9 = Base->TIMCFG[_8];
  _10 = _9 & 4291821567;
  _11 = Decrement << 20;
  _12 = _11 & 3145728;
  _13 = (int) Timer;
  _14 = _10 | _12;
  Base->TIMCFG[_13] = _14;
  _15 = (int) Timer;
  _16 = Base->TIMCFG[_15];
  _17 = _16 & 4244635647;
  _18 = Output << 24;
  _19 = _18 & 50331648;
  _20 = (int) Timer;
  _21 = _17 | _19;
  Base->TIMCFG[_20] = _21;
  return;

}


Flexio_Uart_Ip_SetTimerCompare (struct FLEXIO_Type * Base, uint8 Timer, uint16 Value)
{
  <bb 2> :
  _1 = (int) Timer;
  _2 = (long unsigned int) Value;
  Base->TIMCMP[_1] = _2;
  return;

}


Flexio_Uart_Ip_SetPinShifterControl (struct FLEXIO_Type * Base, uint8 Shifter, uint8 Pin, Flexio_Mcl_Ip_PinPolarityType PinPolarity, Flexio_Mcl_Ip_PinConfigType PinConfig)
{
  <bb 2> :
  _1 = (int) Shifter;
  _2 = Base->SHIFTCTL[_1];
  _3 = _2 & 4294967167;
  _4 = PinPolarity << 7;
  _5 = _4 & 255;
  _6 = (int) Shifter;
  _7 = _3 | _5;
  Base->SHIFTCTL[_6] = _7;
  _8 = (int) Shifter;
  _9 = Base->SHIFTCTL[_8];
  _10 = _9 & 4294965503;
  _11 = (long unsigned int) Pin;
  _12 = _11 << 8;
  _13 = _12 & 1792;
  _14 = (int) Shifter;
  _15 = _10 | _13;
  Base->SHIFTCTL[_14] = _15;
  _16 = (int) Shifter;
  _17 = Base->SHIFTCTL[_16];
  _18 = _17 & 4294770687;
  _19 = PinConfig << 16;
  _20 = _19 & 196608;
  _21 = (int) Shifter;
  _22 = _18 | _20;
  Base->SHIFTCTL[_21] = _22;
  return;

}


Flexio_Uart_Ip_SetShifterControl (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterModeType Mode, uint8 Timer, Flexio_Mcl_Ip_TimerPolarityType TimerPolarity)
{
  <bb 2> :
  _1 = (int) Shifter;
  _2 = Base->SHIFTCTL[_1];
  _3 = _2 & 4294967288;
  _4 = Mode & 7;
  _5 = (int) Shifter;
  _6 = _3 | _4;
  Base->SHIFTCTL[_5] = _6;
  _7 = (int) Shifter;
  _8 = Base->SHIFTCTL[_7];
  _9 = _8 & 4286578687;
  _10 = TimerPolarity << 23;
  _11 = _10 & 8388608;
  _12 = (int) Shifter;
  _13 = _9 | _11;
  Base->SHIFTCTL[_12] = _13;
  _14 = (int) Shifter;
  _15 = Base->SHIFTCTL[_14];
  _16 = _15 & 4244635647;
  _17 = (long unsigned int) Timer;
  _18 = _17 << 24;
  _19 = _18 & 50331648;
  _20 = (int) Shifter;
  _21 = _16 | _19;
  Base->SHIFTCTL[_20] = _21;
  return;

}


Flexio_Uart_Ip_SetShifterConfig (struct FLEXIO_Type * Base, uint8 Shifter, Flexio_Mcl_Ip_ShifterStartType Start, Flexio_Mcl_Ip_ShifterStopType Stop, Flexio_Mcl_Ip_ShifterSourceType Source)
{
  <bb 2> :
  _1 = Start & 3;
  _2 = Stop << 4;
  _3 = _2 & 48;
  _4 = _1 | _3;
  _5 = Source << 8;
  _6 = _5 & 256;
  _7 = (int) Shifter;
  _8 = _4 | _6;
  Base->SHIFTCFG[_7] = _8;
  return;

}


