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@@ -174,15 +174,15 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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{
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0U, /* clkConfigId */
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- 1U, /* ircoscsCount */
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+ 2U, /* ircoscsCount */
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1U, /* xoscsCount */
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- 0U, /* pllsCount */
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- 20U, /* selectorsCount */
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- 14U, /* dividersCount */
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+ 1U, /* pllsCount */
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+ 28U, /* selectorsCount */
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+ 20U, /* dividersCount */
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0U, /* dividerTriggersCount */
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0U, /* fracDivsCount */
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4U, /* extClksCount */
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- 32U, /* gatesCount */
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+ 40U, /* gatesCount */
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0U, /* pcfsCount */
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0U, /* cmusCount */
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0U, /* configureFrequenciesCount */
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@@ -199,14 +199,16 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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0U, /* Ircosc enable in STOP mode */
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},
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#endif
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+ #if CLOCK_IRCOSCS_NO > 1U
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{
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- RESERVED_CLK, /* Clock name associated to Ircosc */
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- 0U, /* Enable ircosc */
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- 0U, /* Enable regulator */
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+ FIRC_CLK, /* Clock name associated to Ircosc */
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+ 1U, /* Enable ircosc */
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+ 0U, /* Enable regulator */
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0U, /* Ircosc range */
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- 0U, /* Ircosc enable in VLP mode */
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- 0U, /* Ircosc enable in STOP mode */
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+ 0U, /* Ircosc enable in VLP mode */
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+ 0U, /* Ircosc enable in STOP mode */
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},
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+ #endif
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},
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/* XOSC initialization. */
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@@ -214,10 +216,10 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_XOSCS_NO > 0U
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{
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SOSC_CLK, /* Clock name associated to xosc */
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- 8000000U, /* External oscillator frequency. */
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+ 16000000U, /* External oscillator frequency. */
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1U, /* Enable xosc. */
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0U, /* Startup stabilization time. */
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- 0U, /* XOSC bypass option */
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+ 0U, /* XOSC bypass option */
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0U, /* Comparator enable */
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0U, /* Crystal overdrive protection */
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0U, /* High gain value */
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@@ -229,23 +231,23 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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/* PLL initialization. */
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{
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- #if CLOCK_PLLS_NO > 0U
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- {
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- RESERVED_CLK, /* name */
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- 0U, /* enable */
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- RESERVED_CLK, /* inputReference */
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- 0U, /* Bypass */
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- 0U, /* predivider */
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- 0U, /* numeratorFracLoopDiv */
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- 0U, /* mulFactorDiv */
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- 0U, /* modulation */
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- 0U, /* Modulaton type: Spread spectrum modulation bypassed */
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- 0U, /* modulationPeriod */
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- 0U, /* incrementStep */
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- 0U, /* sigmaDelta */
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- 0U, /* ditherControl */
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- 0U, /* ditherControlValue */
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- 0U, /* Monitor type */
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+ #if CLOCK_PLLS_NO > 0U
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+ {
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+ SPLL_CLK, /*!< name; */
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+ 1U, /*!< enable; */
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+ SOSC_CLK, /*!< inputReference */
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+ 0U, /*!< bypass; */
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+ 2U, /*!< predivider; */
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+ 0U, /*!< numeratorFracLoopDiv; */
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+ 24U, /*!< mulFactorDiv; */
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+ 0U, /*!< modulation; */
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+ 0U, /*!< modulationType; */
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+ 0U, /*!< modulationPeriod; */
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+ 1U, /* incrementStep */
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+ 0U, /*!< sigmaDelta; */
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+ 0U, /*!< ditherControl; */
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+ 0U, /*!< ditherControlValue; */
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+ FEATURE_CLOCK_IP_HAS_MONITOR_DISABLE, /*!< Monitor type */
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},
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#endif
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@@ -257,7 +259,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_SELECTORS_NO > 0U
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{
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SCS_RUN_CLK, /* Clock name associated to selector */
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- FIRC_CLK, /* Name of the selected input source */
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+ SPLL_CLK, /* Name of the selected input source */
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},
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#endif
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@@ -271,168 +273,184 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_SELECTORS_NO > 2U
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{
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SCS_HSRUN_CLK, /* Clock name associated to selector */
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- FIRC_CLK, /* Name of the selected input source */
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+ SPLL_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 3U
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{
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SCG_CLKOUT_CLK, /* Clock name associated to selector */
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- SLOW_CLK, /* Name of the selected input source */
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+ SPLL_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 4U
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{
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- FTM0_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ RTC_CLK, /* Clock name associated to selector */
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+ SOSCDIV1_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 5U
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{
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- FTM1_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ LPO_CLK, /* Clock name associated to selector */
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+ LPO_128K_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 6U
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{
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- FTM2_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ TRACE_CLK, /* Clock name associated to selector */
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+ CORE_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 7U
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{
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- FTM3_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ CLKOUT0_CLK, /* Clock name associated to selector */
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+ SCG_CLKOUT_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 8U
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{
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- ADC1_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ FTM0_EXT_CLK, /* Clock name associated to selector */
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+ TCLK0_REF_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 9U
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{
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- LPSPI0_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ FTM1_EXT_CLK, /* Clock name associated to selector */
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+ TCLK0_REF_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 10U
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{
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- LPSPI1_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ FTM2_EXT_CLK, /* Clock name associated to selector */
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+ TCLK0_REF_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 11U
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{
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- LPSPI2_CLK, /* Clock name associated to selector */
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- CLOCK_IS_OFF, /* Name of the selected input source */
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+ FTM3_EXT_CLK, /* Clock name associated to selector */
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+ TCLK0_REF_CLK, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 12U
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{
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- LPIT0_CLK, /* Clock name associated to selector */
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+ FTM0_CLK, /* Clock name associated to selector */
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CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 13U
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{
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- ADC0_CLK, /* Clock name associated to selector */
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+ FTM1_CLK, /* Clock name associated to selector */
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CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 14U
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{
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- FlexIO_CLK, /* Clock name associated to selector */
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- SIRCDIV2_CLK, /* Name of the selected input source */
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+ FTM2_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 15U
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{
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- LPI2C0_CLK, /* Clock name associated to selector */
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+ FTM3_CLK, /* Clock name associated to selector */
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CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 16U
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{
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- LPUART0_CLK, /* Clock name associated to selector */
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- SIRCDIV2_CLK, /* Name of the selected input source */
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+ ADC1_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 17U
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{
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- LPUART1_CLK, /* Clock name associated to selector */
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- SIRCDIV2_CLK, /* Name of the selected input source */
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+ LPSPI0_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 18U
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{
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- LPUART2_CLK, /* Clock name associated to selector */
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- SIRCDIV2_CLK, /* Name of the selected input source */
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+ LPSPI1_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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#if CLOCK_SELECTORS_NO > 19U
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{
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- LPTMR0_CLK, /* Clock name associated to selector */
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+ LPSPI2_CLK, /* Clock name associated to selector */
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CLOCK_IS_OFF, /* Name of the selected input source */
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},
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#endif
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+ #if CLOCK_SELECTORS_NO > 20U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPIT0_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 21U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ ADC0_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 22U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ FlexIO_CLK, /* Clock name associated to selector */
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+ SIRCDIV2_CLK, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 23U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPI2C0_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 24U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPUART0_CLK, /* Clock name associated to selector */
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+ SOSCDIV2_CLK, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 25U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPUART1_CLK, /* Clock name associated to selector */
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+ SOSCDIV2_CLK, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 26U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPUART2_CLK, /* Clock name associated to selector */
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+ SOSCDIV2_CLK, /* Name of the selected input source */
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},
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+ #endif
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+ #if CLOCK_SELECTORS_NO > 27U
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{
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- RESERVED_CLK, /* Clock name associated to selector */
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- RESERVED_CLK, /* Name of the selected input source */
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+ LPTMR0_CLK, /* Clock name associated to selector */
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+ CLOCK_IS_OFF, /* Name of the selected input source */
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},
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+ #endif
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},
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@@ -461,7 +479,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 2U
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{
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- SOSCDIV1_CLK,
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+ FIRCDIV1_CLK,
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1U,
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{
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0U,
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@@ -471,8 +489,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 3U
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{
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- SOSCDIV2_CLK,
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- 1U,
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+ FIRCDIV2_CLK,
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+ 2U,
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{
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0U,
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}
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@@ -481,8 +499,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 4U
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{
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- CORE_RUN_CLK,
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- 1U,
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+ SOSCDIV1_CLK,
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+ 2U,
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{
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0U,
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}
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@@ -491,7 +509,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 5U
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{
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- CORE_VLPR_CLK,
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+ SOSCDIV2_CLK,
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8U,
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{
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0U,
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@@ -501,7 +519,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 6U
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{
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- CORE_HSRUN_CLK,
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+ SPLLDIV1_CLK,
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1U,
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{
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0U,
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@@ -511,8 +529,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 7U
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{
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- BUS_RUN_CLK,
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- 1U,
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+ SPLLDIV2_CLK,
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+ 2U,
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{
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0U,
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}
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@@ -521,8 +539,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 8U
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{
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- BUS_VLPR_CLK,
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- 8U,
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+ CORE_RUN_CLK,
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+ 2U,
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{
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0U,
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}
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@@ -531,8 +549,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 9U
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{
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- BUS_HSRUN_CLK,
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- 1U,
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+ CORE_VLPR_CLK,
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+ 4U,
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{
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0U,
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}
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@@ -541,7 +559,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 10U
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{
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- SLOW_RUN_CLK,
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+ CORE_HSRUN_CLK,
|
|
|
2U,
|
|
|
{
|
|
|
0U,
|
|
@@ -551,8 +569,8 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 11U
|
|
|
{
|
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|
- SLOW_VLPR_CLK,
|
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|
- 4U,
|
|
|
+ BUS_RUN_CLK,
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|
+ 2U,
|
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|
{
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0U,
|
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|
}
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|
@@ -561,7 +579,7 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 12U
|
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|
{
|
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|
- SLOW_HSRUN_CLK,
|
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|
+ BUS_VLPR_CLK,
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|
2U,
|
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|
{
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|
0U,
|
|
@@ -571,61 +589,73 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_DIVIDERS_NO > 13U
|
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|
{
|
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|
- LPTMR0_CLK,
|
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|
- 1U,
|
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|
+ BUS_HSRUN_CLK,
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|
+ 2U,
|
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|
{
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- 1U,
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|
+ 0U,
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|
}
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|
},
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#endif
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+ #if CLOCK_DIVIDERS_NO > 14U
|
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|
{
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|
- RESERVED_CLK,
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|
- 0U,
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|
+ SLOW_RUN_CLK,
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|
+ 4U,
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|
{
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0U,
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|
- },
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|
+ }
|
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|
},
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|
+ #endif
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+ #if CLOCK_DIVIDERS_NO > 15U
|
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|
{
|
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|
- RESERVED_CLK,
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|
- 0U,
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|
+ SLOW_VLPR_CLK,
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|
+ 4U,
|
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|
{
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|
0U,
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- },
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|
+ }
|
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|
},
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|
+ #endif
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|
+ #if CLOCK_DIVIDERS_NO > 16U
|
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|
{
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|
- RESERVED_CLK,
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|
- 0U,
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|
+ SLOW_HSRUN_CLK,
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|
+ 4U,
|
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|
{
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|
0U,
|
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|
- },
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|
+ }
|
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|
},
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|
+ #endif
|
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+ #if CLOCK_DIVIDERS_NO > 17U
|
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|
{
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|
- RESERVED_CLK,
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|
- 0U,
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|
+ CLKOUT0_CLK,
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|
+ 4U,
|
|
|
{
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|
0U,
|
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|
- },
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|
+ }
|
|
|
},
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|
+ #endif
|
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+ #if CLOCK_DIVIDERS_NO > 18U
|
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|
{
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|
- RESERVED_CLK,
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|
- 0U,
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|
+ LPTMR0_CLK,
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|
+ 1U,
|
|
|
{
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|
- 0U,
|
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|
- },
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|
+ 1U,
|
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|
+ }
|
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|
},
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|
+ #endif
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|
+ #if CLOCK_DIVIDERS_NO > 19U
|
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|
{
|
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|
- RESERVED_CLK,
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|
- 0U,
|
|
|
+ TRACE_CLK,
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|
+ 1U,
|
|
|
{
|
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|
- 0U,
|
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|
- },
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|
+ 1U,
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|
+ }
|
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},
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+ #endif
|
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|
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|
},
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|
@@ -655,21 +685,21 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_EXT_CLKS_NO > 0U
|
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|
{
|
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|
TCLK0_REF_CLK,
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|
- 32000U,
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|
+ 0U,
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|
},
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|
#endif
|
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|
#if CLOCK_EXT_CLKS_NO > 1U
|
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|
{
|
|
|
TCLK1_REF_CLK,
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|
- 32000U,
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|
+ 0U,
|
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|
},
|
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|
#endif
|
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|
#if CLOCK_EXT_CLKS_NO > 2U
|
|
|
{
|
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|
TCLK2_REF_CLK,
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|
- 32000U,
|
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|
+ 0U,
|
|
|
},
|
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|
#endif
|
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|
@@ -687,228 +717,244 @@ const Clock_Ip_ClockConfigType Mcu_aClockConfigPB_VS_0[1U] = {
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#if CLOCK_GATES_NO > 0U
|
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|
{
|
|
|
- ADC0_CLK, /*!< name; */
|
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|
+ LPO_32K_CLK, /*!< name; */
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|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
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|
#if CLOCK_GATES_NO > 1U
|
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|
{
|
|
|
- ADC1_CLK, /*!< name; */
|
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|
+ LPO_1K_CLK, /*!< name; */
|
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|
1U, /*!< enable; */
|
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|
},
|
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|
#endif
|
|
|
#if CLOCK_GATES_NO > 2U
|
|
|
{
|
|
|
- CMP0_CLK, /*!< name; */
|
|
|
+ ADC0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
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|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 3U
|
|
|
{
|
|
|
- CRC0_CLK, /*!< name; */
|
|
|
+ ADC1_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
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|
},
|
|
|
#endif
|
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|
#if CLOCK_GATES_NO > 4U
|
|
|
{
|
|
|
- DMAMUX0_CLK, /*!< name; */
|
|
|
+ CLKOUT0_CLK, /*!< name; */
|
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|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 5U
|
|
|
{
|
|
|
- EWM0_CLK, /*!< name; */
|
|
|
+ CMP0_CLK, /*!< name; */
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|
|
1U, /*!< enable; */
|
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|
},
|
|
|
#endif
|
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|
#if CLOCK_GATES_NO > 6U
|
|
|
{
|
|
|
- FLEXCAN0_CLK, /*!< name; */
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|
|
+ CRC0_CLK, /*!< name; */
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|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 7U
|
|
|
{
|
|
|
- FLEXCAN1_CLK, /*!< name; */
|
|
|
+ DMA0_CLK, /*!< name; */
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|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 8U
|
|
|
{
|
|
|
- FLEXCAN2_CLK, /*!< name; */
|
|
|
+ DMAMUX0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 9U
|
|
|
{
|
|
|
- FlexIO_CLK, /*!< name; */
|
|
|
+ EIM0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 10U
|
|
|
{
|
|
|
- FTFC_CLK, /*!< name; */
|
|
|
+ ERM0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 11U
|
|
|
{
|
|
|
- FTM0_CLK, /*!< name; */
|
|
|
+ EWM0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 12U
|
|
|
{
|
|
|
- FTM1_CLK, /*!< name; */
|
|
|
+ FLEXCAN0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 13U
|
|
|
{
|
|
|
- FTM2_CLK, /*!< name; */
|
|
|
+ FLEXCAN1_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 14U
|
|
|
{
|
|
|
- FTM3_CLK, /*!< name; */
|
|
|
+ FLEXCAN2_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 15U
|
|
|
{
|
|
|
- LPI2C0_CLK, /*!< name; */
|
|
|
+ FlexIO_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 16U
|
|
|
{
|
|
|
- LPIT0_CLK, /*!< name; */
|
|
|
+ FTFC_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 17U
|
|
|
{
|
|
|
- LPSPI0_CLK, /*!< name; */
|
|
|
+ FTM0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 18U
|
|
|
{
|
|
|
- LPSPI1_CLK, /*!< name; */
|
|
|
+ FTM1_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 19U
|
|
|
{
|
|
|
- LPSPI2_CLK, /*!< name; */
|
|
|
+ FTM2_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 20U
|
|
|
{
|
|
|
- LPTMR0_CLK, /*!< name; */
|
|
|
+ FTM3_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 21U
|
|
|
{
|
|
|
- LPUART0_CLK, /*!< name; */
|
|
|
+ LPI2C0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 22U
|
|
|
{
|
|
|
- LPUART1_CLK, /*!< name; */
|
|
|
+ LPIT0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 23U
|
|
|
{
|
|
|
- LPUART2_CLK, /*!< name; */
|
|
|
+ LPSPI0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 24U
|
|
|
{
|
|
|
- PDB0_CLK, /*!< name; */
|
|
|
+ LPSPI1_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 25U
|
|
|
{
|
|
|
- PDB1_CLK, /*!< name; */
|
|
|
+ LPSPI2_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 26U
|
|
|
{
|
|
|
- PORTA_CLK, /*!< name; */
|
|
|
+ LPTMR0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 27U
|
|
|
{
|
|
|
- PORTB_CLK, /*!< name; */
|
|
|
+ LPUART0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 28U
|
|
|
{
|
|
|
- PORTC_CLK, /*!< name; */
|
|
|
+ LPUART1_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 29U
|
|
|
{
|
|
|
- PORTD_CLK, /*!< name; */
|
|
|
+ LPUART2_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 30U
|
|
|
{
|
|
|
- PORTE_CLK, /*!< name; */
|
|
|
+ MPU0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
#if CLOCK_GATES_NO > 31U
|
|
|
{
|
|
|
- RTC0_CLK, /*!< name; */
|
|
|
+ MSCM0_CLK, /*!< name; */
|
|
|
1U, /*!< enable; */
|
|
|
},
|
|
|
#endif
|
|
|
+ #if CLOCK_GATES_NO > 32U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PDB0_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 33U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PDB1_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 34U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PORTA_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 35U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PORTB_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 36U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PORTC_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 37U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PORTD_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 38U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ PORTE_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
+ #if CLOCK_GATES_NO > 39U
|
|
|
{
|
|
|
- RESERVED_CLK, /* name */
|
|
|
- 0U, /* enable */
|
|
|
+ RTC0_CLK, /*!< name; */
|
|
|
+ 1U, /*!< enable; */
|
|
|
},
|
|
|
+ #endif
|
|
|
},
|
|
|
|
|
|
/* PCFS initialization. */
|