/*==================================================================================================
*   Project              : RTD AUTOSAR 4.4
*   Platform             : CORTEXM
*   Peripheral           : DMA,CACHE,TRGMUX,FLEXIO
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
*
*   (c) Copyright 2020-2021 NXP Semiconductors
*   All Rights Reserved.
*
*   NXP Confidential. This software is owned or controlled by NXP and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifndef DMA_IP_CFG_H_
#define DMA_IP_CFG_H_

#ifdef __cplusplus
extern "C"
{
#endif

/*==================================================================================================
                                         INCLUDE FILES
 1) system and project includes
 2) needed interfaces from external units
 3) internal and external interfaces from this unit
==================================================================================================*/
#include "Dma_Ip_Types.h"
#include "Dma_Ip_VS_0_PBcfg.h"

/*==================================================================================================
                               SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define DMA_IP_CFG_VENDOR_ID_H                       43
#define DMA_IP_CFG_AR_RELEASE_MAJOR_VERSION_H        4
#define DMA_IP_CFG_AR_RELEASE_MINOR_VERSION_H        4
#define DMA_IP_CFG_AR_RELEASE_REVISION_VERSION_H     0
#define DMA_IP_CFG_SW_MAJOR_VERSION_H                1
#define DMA_IP_CFG_SW_MINOR_VERSION_H                0
#define DMA_IP_CFG_SW_PATCH_VERSION_H                0

/*==================================================================================================
                                      FILE VERSION CHECKS
==================================================================================================*/
/* Check if header file and Dma_Ip_Types.h file are of the same vendor */
#if (DMA_IP_CFG_VENDOR_ID_H != DMA_IP_TYPES_VENDOR_ID_H)
    #error "Dma_Ip_Cfg.h and Dma_Ip_Types.h have different vendor ids"
#endif

/* Check if header file and Dma_Ip_Types.h file are of the same Autosar version */
#if ((DMA_IP_CFG_AR_RELEASE_MAJOR_VERSION_H != DMA_IP_TYPES_AR_RELEASE_MAJOR_VERSION_H) || \
     (DMA_IP_CFG_AR_RELEASE_MINOR_VERSION_H != DMA_IP_TYPES_AR_RELEASE_MINOR_VERSION_H) || \
     (DMA_IP_CFG_AR_RELEASE_REVISION_VERSION_H != DMA_IP_TYPES_AR_RELEASE_REVISION_VERSION_H) \
    )
    #error "AutoSar Version Numbers of Dma_Ip_Cfg.h and Dma_Ip_Types.h are different"
#endif

/* Check if header file and Dma_Ip_Types.h file are of the same Software version */
#if ((DMA_IP_CFG_SW_MAJOR_VERSION_H != DMA_IP_TYPES_SW_MAJOR_VERSION_H) || \
     (DMA_IP_CFG_SW_MINOR_VERSION_H != DMA_IP_TYPES_SW_MINOR_VERSION_H) || \
     (DMA_IP_CFG_SW_PATCH_VERSION_H != DMA_IP_TYPES_SW_PATCH_VERSION_H) \
    )
    #error "Software Version Numbers of Dma_Ip_Cfg.h and Dma_Ip_Types.h are different"
#endif

/* Check if header file and Dma_Ip_VS_0_PBcfg.h file are of the same vendor */
#if (DMA_IP_CFG_VENDOR_ID_H != DMA_IP_VS_0_PBCFG_VENDOR_ID_H)
    #error "Dma_Ip_Cfg.h and Dma_Ip_VS_0_PBcfg.h have different vendor ids"
#endif

/* Check if header file and Dma_Ip_VS_0_PBcfg.h file are of the same Autosar version */
#if ((DMA_IP_CFG_AR_RELEASE_MAJOR_VERSION_H != DMA_IP_VS_0_PBCFG_AR_RELEASE_MAJOR_VERSION_H) || \
     (DMA_IP_CFG_AR_RELEASE_MINOR_VERSION_H != DMA_IP_VS_0_PBCFG_AR_RELEASE_MINOR_VERSION_H) || \
     (DMA_IP_CFG_AR_RELEASE_REVISION_VERSION_H != DMA_IP_VS_0_PBCFG_AR_RELEASE_REVISION_VERSION_H) \
    )
    #error "AutoSar Version Numbers of Dma_Ip_Cfg.h and Dma_Ip_VS_0_PBcfg.h are different"
#endif

/* Check if header file and Dma_Ip_VS_0_PBcfg.h file are of the same Software version */
#if ((DMA_IP_CFG_SW_MAJOR_VERSION_H != DMA_IP_VS_0_PBCFG_SW_MAJOR_VERSION_H) || \
     (DMA_IP_CFG_SW_MINOR_VERSION_H != DMA_IP_VS_0_PBCFG_SW_MINOR_VERSION_H) || \
     (DMA_IP_CFG_SW_PATCH_VERSION_H != DMA_IP_VS_0_PBCFG_SW_PATCH_VERSION_H) \
    )
    #error "Software Version Numbers of Dma_Ip_Cfg.h and Dma_Ip_VS_0_PBcfg.h are different"
#endif




/*******************************************************************************
 * Definitions
 ******************************************************************************/
/* Number Of Configured Logic Instances */
#define MCL_ENABLE_USER_MODE_SUPPORT    STD_OFF

#if (MCL_ENABLE_USER_MODE_SUPPORT == STD_ON)
#define MCL_DMA_REG_PROT_AVAILABLE
#endif

#define DMA_IP_NOF_CFG_LOGIC_INSTANCES   ((uint32)1U)


/* Logic Instance 0 */
#define DMA_LOGIC_INST_0    ((uint32)0U)

/* Number Of Configured Logic Channels */
#define DMA_IP_NOF_CFG_LOGIC_CHANNELS   ((uint32)6U)

/* Logic Channel 0 */
#define DMA_LOGIC_CH_UART0_TX      ((uint8)0U)


/* Logic Channel 1 */
#define DMA_LOGIC_CH_UART0_RX      ((uint8)1U)


/* Logic Channel 2 */
#define DMA_LOGIC_CH_UART1_TX      ((uint8)2U)


/* Logic Channel 3 */
#define DMA_LOGIC_CH_UART1_RX      ((uint8)3U)


/* Logic Channel 4 */
#define DMA_LOGIC_CH_UART2_TX      ((uint8)4U)


/* Logic Channel 5 */
#define DMA_LOGIC_CH_UART2_RX      ((uint8)5U)



#define MCL_START_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

/* DMA Initialization Structure */
extern const Dma_Ip_InitType Dma_Ip_xDmaInitPB_VS_0;

extern const Dma_Ip_LogicChannelConfigType Dma_Ip_xLogicChannelResetConfig;

extern const Dma_Ip_LogicInstanceConfigType Dma_Ip_xLogicInstanceResetConfig;

#define MCL_STOP_SEC_CONFIG_DATA_UNSPECIFIED
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

#define MCL_START_SEC_CODE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"

/* DMA IRQ Handlers */

ISR(Dma0_Ch0_IRQHandler);
ISR(Dma0_Ch1_IRQHandler);
ISR(Dma0_Ch2_IRQHandler);
ISR(Dma0_Ch3_IRQHandler);
ISR(Dma0_Ch4_IRQHandler);
ISR(Dma0_Ch5_IRQHandler);
ISR(Dma0_Ch6_IRQHandler);
ISR(Dma0_Ch7_IRQHandler);
ISR(Dma0_Ch8_IRQHandler);
ISR(Dma0_Ch9_IRQHandler);
ISR(Dma0_Ch10_IRQHandler);
ISR(Dma0_Ch11_IRQHandler);
ISR(Dma0_Ch12_IRQHandler);
ISR(Dma0_Ch13_IRQHandler);
ISR(Dma0_Ch14_IRQHandler);
ISR(Dma0_Ch15_IRQHandler);

/* DMA Error IRQ Handlers */
ISR(Dma0_Error_IrqHandler);

#define MCL_STOP_SEC_CODE
/* @violates @ref Mcl_Dma_h_REF_1 MISRA 2012 Required Directive 4.10, Precautions shall be taken in order to prevent the contents of a header file being included more than once. */
#include "Mcl_MemMap.h"


#ifdef __cplusplus
}
#endif

#endif /* DMA_IP_CFG_H_ */

/*==================================================================================================
 *                                        END OF FILE
==================================================================================================*/