-nostartfiles
--entry=Reset_Handler
-ggdb3
-T
"D:/1_WorkFiles/2_Software/11.Communicator/workspace/S32K144_Project_CAN_UART_DIO_WithFreeRTOS/Project_Settings/Linker_Files/linker_flash_s32k144.ld"
-Wl,-Map,"S32K144_Project_CAN_UART_DIO_WithFreeRTOS.map"
-n
-mcpu=cortex-m4
-mthumb
-mlittle-endian
-mfloat-abi=hard
-mfpu=fpv4-sp-d16
-specs=nano.specs
-specs=nosys.specs
--sysroot="C:/NXP/S32DS.3.4/S32DS/build_tools/gcc_v9.2/gcc-9.2-arm32-eabi/arm-none-eabi/newlib"
"./FreeRTOS/Source/croutine.o"
"./FreeRTOS/Source/event_groups.o"
"./FreeRTOS/Source/list.o"
"./FreeRTOS/Source/queue.o"
"./FreeRTOS/Source/stream_buffer.o"
"./FreeRTOS/Source/tasks.o"
"./FreeRTOS/Source/timers.o"
"./FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o"
"./FreeRTOS/Source/portable/MemMang/heap_4.o"
"./Project_Settings/Startup_Code/Vector_Table.o"
"./Project_Settings/Startup_Code/exceptions.o"
"./Project_Settings/Startup_Code/nvic.o"
"./Project_Settings/Startup_Code/startup.o"
"./Project_Settings/Startup_Code/startup_cm4.o"
"./Project_Settings/Startup_Code/system.o"
"./RTD/src/CDD_Mcl.o"
"./RTD/src/CDD_Mcl_Ipw.o"
"./RTD/src/Cache_Ip.o"
"./RTD/src/Can.o"
"./RTD/src/Can_Ipw.o"
"./RTD/src/Can_Irq.o"
"./RTD/src/Clock_Ip.o"
"./RTD/src/Clock_Ip_Data.o"
"./RTD/src/Clock_Ip_Divider.o"
"./RTD/src/Clock_Ip_DividerTrigger.o"
"./RTD/src/Clock_Ip_ExtOsc.o"
"./RTD/src/Clock_Ip_FracDiv.o"
"./RTD/src/Clock_Ip_Frequency.o"
"./RTD/src/Clock_Ip_Gate.o"
"./RTD/src/Clock_Ip_IntOsc.o"
"./RTD/src/Clock_Ip_Irq.o"
"./RTD/src/Clock_Ip_Monitor.o"
"./RTD/src/Clock_Ip_Pll.o"
"./RTD/src/Clock_Ip_ProgFreqSwitch.o"
"./RTD/src/Clock_Ip_Selector.o"
"./RTD/src/Clock_Ip_Specific.o"
"./RTD/src/Det.o"
"./RTD/src/Det_stub.o"
"./RTD/src/Dio.o"
"./RTD/src/Dio_Ipw.o"
"./RTD/src/Dma_Ip.o"
"./RTD/src/Dma_Ip_Driver_State.o"
"./RTD/src/Dma_Ip_Hw_Access.o"
"./RTD/src/Dma_Ip_Irq.o"
"./RTD/src/Dma_Ip_Multicore.o"
"./RTD/src/EcuM.o"
"./RTD/src/FlexCAN_Ip.o"
"./RTD/src/FlexCAN_Ip_HwAccess.o"
"./RTD/src/FlexCAN_Ip_Irq.o"
"./RTD/src/Flexio_Mcl_Ip.o"
"./RTD/src/Flexio_Mcl_Ip_HwAccess.o"
"./RTD/src/Flexio_Mcl_Ip_Irq.o"
"./RTD/src/Flexio_Uart_Ip.o"
"./RTD/src/Flexio_Uart_Ip_Irq.o"
"./RTD/src/Ftm_Mcl_Ip.o"
"./RTD/src/Gpio_Dio_Ip.o"
"./RTD/src/IntCtrl_Ip.o"
"./RTD/src/Lpuart_Uart_Ip.o"
"./RTD/src/Lpuart_Uart_Ip_Irq.o"
"./RTD/src/Mcu.o"
"./RTD/src/Mcu_Dem_Wrapper.o"
"./RTD/src/Mcu_IPW.o"
"./RTD/src/Mcu_IPW_Irq.o"
"./RTD/src/OsIf_Timer.o"
"./RTD/src/OsIf_Timer_System.o"
"./RTD/src/Os_counter_api.o"
"./RTD/src/Os_multicore.o"
"./RTD/src/Platform.o"
"./RTD/src/Platform_Ipw.o"
"./RTD/src/Port.o"
"./RTD/src/Port_Ci_Port_Ip.o"
"./RTD/src/Port_Ipw.o"
"./RTD/src/Power_Ip.o"
"./RTD/src/Power_Ip_CMU.o"
"./RTD/src/Power_Ip_CortexM4.o"
"./RTD/src/Power_Ip_PCC.o"
"./RTD/src/Power_Ip_PMC.o"
"./RTD/src/Power_Ip_PMC_Irq.o"
"./RTD/src/Power_Ip_Private.o"
"./RTD/src/Power_Ip_RCM.o"
"./RTD/src/Power_Ip_RCM_Irq.o"
"./RTD/src/Power_Ip_SCG.o"
"./RTD/src/Power_Ip_SIM.o"
"./RTD/src/Power_Ip_SMC.o"
"./RTD/src/Ram_Ip.o"
"./RTD/src/SchM_Can.o"
"./RTD/src/SchM_Dio.o"
"./RTD/src/SchM_Mcl.o"
"./RTD/src/SchM_Mcu.o"
"./RTD/src/SchM_Port.o"
"./RTD/src/SchM_Uart.o"
"./RTD/src/System_Ip.o"
"./RTD/src/Trgmux_Ip.o"
"./RTD/src/Uart.o"
"./RTD/src/Uart_Ipw.o"
"./board/Clock_Ip_Cfg.o"
"./board/Clock_Ip_PBcfg.o"
"./board/Port_Ci_Port_Ip_Cfg.o"
"./generate/src/CDD_Mcl_Cfg.o"
"./generate/src/CDD_Mcl_VS_0_PBcfg.o"
"./generate/src/Can_Ipw_VS_0_PBcfg.o"
"./generate/src/Can_VS_0_PBcfg.o"
"./generate/src/Clock_Ip_Cfg.o"
"./generate/src/Clock_Ip_VS_0_PBcfg.o"
"./generate/src/Dio_Cfg.o"
"./generate/src/Dma_Ip_Cfg.o"
"./generate/src/Dma_Ip_VS_0_PBcfg.o"
"./generate/src/FlexCAN_Ip_VS_0_PBcfg.o"
"./generate/src/Flexio_Mcl_Ip_VS_0_PBcfg.o"
"./generate/src/Flexio_Uart_Ip_VS_0_PBcfg.o"
"./generate/src/IntCtrl_Ip_Cfg.o"
"./generate/src/Lpuart_Uart_Ip_VS_0_PBcfg.o"
"./generate/src/Mcu_Cfg.o"
"./generate/src/Mcu_VS_0_PBcfg.o"
"./generate/src/OsIf_Cfg.o"
"./generate/src/Platform_Cfg.o"
"./generate/src/Platform_Ipw_Cfg.o"
"./generate/src/Port_Cfg.o"
"./generate/src/Port_Ci_Port_Ip_VS_0_PBcfg.o"
"./generate/src/Port_VS_0_PBcfg.o"
"./generate/src/Power_Ip_Cfg.o"
"./generate/src/Power_Ip_VS_0_PBcfg.o"
"./generate/src/Ram_Ip_Cfg.o"
"./generate/src/Ram_Ip_VS_0_PBcfg.o"
"./generate/src/Trgmux_Ip_Cfg.o"
"./generate/src/Trgmux_Ip_VS_0_PBcfg.o"
"./generate/src/Uart_Ipw_VS_0_PBcfg.o"
"./generate/src/Uart_VS_0_PBcfg.o"
"./src/main.o"
-lc
-lm
-lgcc