System_Ip_CfgDefines.h 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103
  1. /*==================================================================================================
  2. * Project : RTD AUTOSAR 4.4
  3. * Platform : CORTEXM
  4. * Peripheral :
  5. * Dependencies : none
  6. *
  7. * Autosar Version : 4.4.0
  8. * Autosar Revision : ASR_REL_4_4_REV_0000
  9. * Autosar Conf.Variant :
  10. * SW Version : 1.0.0
  11. * Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
  12. *
  13. * (c) Copyright 2020-2021 NXP Semiconductors
  14. * All Rights Reserved.
  15. *
  16. * NXP Confidential. This software is owned or controlled by NXP and may only be
  17. * used strictly in accordance with the applicable license terms. By expressly
  18. * accepting such terms or by downloading, installing, activating and/or otherwise
  19. * using the software, you are agreeing that you have read, and that you agree to
  20. * comply with and are bound by, such license terms. If you do not agree to be
  21. * bound by the applicable license terms, then you may not retain, install,
  22. * activate or otherwise use the software.
  23. ==================================================================================================*/
  24. #ifndef SYSTEM_IP_CFG_DEFINES_H_
  25. #define SYSTEM_IP_CFG_DEFINES_H_
  26. /**
  27. * @file
  28. *
  29. * @addtogroup System_Ip
  30. * @{
  31. */
  32. /*==================================================================================================
  33. * INCLUDE FILES
  34. ==================================================================================================*/
  35. #include "StandardTypes.h"
  36. #include "System_Ip_DeviceRegisters.h"
  37. /*==================================================================================================
  38. * SOURCE FILE VERSION INFORMATION
  39. ==================================================================================================*/
  40. #define PLATFORM_SYSTEM_IP_CFG_DEFINES_TYPES_VENDOR_ID 43
  41. #define PLATFORM_SYSTEM_IP_CFG_DEFINES_SW_MAJOR_VERSION 1
  42. #define PLATFORM_SYSTEM_IP_CFG_DEFINES_SW_MINOR_VERSION 0
  43. #define PLATFORM_SYSTEM_IP_CFG_DEFINES_SW_PATCH_VERSION 0
  44. #include "S32K144.h"
  45. /*==================================================================================================
  46. * LOCAL MACROS
  47. ==================================================================================================*/
  48. /* Arm Coretex M4 */
  49. #define SYSTEM_IP_ARM_CORTEXM4 (STD_ON)
  50. /*==================================================================================================
  51. * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
  52. ==================================================================================================*/
  53. #if (SYSTEM_IP_ARM_CORTEXM4 == STD_ON)
  54. /**
  55. * @brief Enumeration listing available core-related interrupt requests
  56. * defined per each platform.
  57. * @implements System_Ip_IrqType_typedef
  58. */
  59. typedef enum
  60. {
  61. #ifdef FPU_INPUT_DENORMAL_IRQ_SUPPORTED
  62. /** @brief FPU Input Denormal Interrupt */
  63. FPU_INPUT_DENORMAL_IRQ = MCM_ISCR_FIDCE_SHIFT,
  64. #endif
  65. #ifdef FPU_INEXACT_IRQ_SUPPORTED
  66. /** @brief FPU Inexact Interrupt */
  67. FPU_INEXACT_IRQ = MCM_ISCR_FIXCE_SHIFT,
  68. #endif
  69. #ifdef FPU_UNDERFLOW_IRQ_SUPPORTED
  70. /** @brief FPU Underflow Interrupt */
  71. FPU_UNDERFLOW_IRQ = MCM_ISCR_FUFCE_SHIFT,
  72. #endif
  73. #ifdef FPU_OVERFLOW_IRQ_SUPPORTED
  74. /** @brief FPU Overflow Interrupt */
  75. FPU_OVERFLOW_IRQ = MCM_ISCR_FOFCE_SHIFT,
  76. #endif
  77. #ifdef FPU_DIVIDE_BY_ZERO_IRQ_SUPPORTED
  78. /** @brief FPU Divide-by-Zero Interrupt */
  79. FPU_DIVIDE_BY_ZERO_IRQ = MCM_ISCR_FDZCE_SHIFT,
  80. #endif
  81. #ifdef FPU_INVALID_OPERATION_IRQ_SUPPORTED
  82. /** @brief FPU Invalid Operation Interrupt */
  83. FPU_INVALID_OPERATION_IRQ = MCM_ISCR_FIOCE_SHIFT,
  84. #endif
  85. #ifdef TCM_WRITE_ABORT_IRQ_SUPPORTED
  86. /** @brief TCM Write Abort Interrupt */
  87. TCM_WRITE_ABORT_IRQ = MCM_ISCR_WABE_SHIFT
  88. #endif
  89. }System_Ip_IrqType;
  90. #endif
  91. #endif /* SYSTEM_IP_CFG_DEFINES_H_ */
  92. /** @} */