system.c.080i.single-use 3.2 KB

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  1. __attribute__((section (".systeminit")))
  2. SystemInit ()
  3. {
  4. struct S32_SCB_Type * _1;
  5. long unsigned int _2;
  6. struct S32_SCB_Type * _3;
  7. long unsigned int _4;
  8. struct S32_SCB_Type * _5;
  9. long unsigned int _6;
  10. struct S32_SCB_Type * _7;
  11. long unsigned int _8;
  12. struct S32_SCB_Type * _9;
  13. long unsigned int _10;
  14. struct S32_SCB_Type * _11;
  15. long unsigned int _12;
  16. struct AIPS_Type * _13;
  17. struct AIPS_Type * _14;
  18. struct AIPS_Type * _15;
  19. struct AIPS_Type * _16;
  20. struct AIPS_Type * _17;
  21. struct AIPS_Type * _18;
  22. struct AIPS_Type * _19;
  23. struct AIPS_Type * _20;
  24. struct AIPS_Type * _21;
  25. struct AIPS_Type * _22;
  26. struct AIPS_Type * _23;
  27. struct AIPS_Type * _24;
  28. struct AIPS_Type * _25;
  29. struct AIPS_Type * _26;
  30. struct AIPS_Type * _27;
  31. struct AIPS_Type * _28;
  32. <bb 2> :
  33. _1 = 3758153728B;
  34. _2 ={v} _1->CPACR;
  35. _3 = 3758153728B;
  36. _4 = _2 | 15728640;
  37. _3->CPACR ={v} _4;
  38. __asm__ __volatile__("dsb");
  39. __asm__ __volatile__("isb");
  40. _5 = 3758153728B;
  41. _6 ={v} _5->CCR;
  42. _7 = 3758153728B;
  43. _8 = _6 | 1;
  44. _7->CCR ={v} _8;
  45. _9 = 3758153728B;
  46. _10 ={v} _9->SHPR3;
  47. _11 = 3758153728B;
  48. _12 = _10 & 4278255615;
  49. _11->SHPR3 ={v} _12;
  50. _13 = 1073741824B;
  51. _13->MPRA ={v} 2004318071;
  52. _14 = 1073741824B;
  53. _14->PACRA ={v} 0;
  54. _15 = 1073741824B;
  55. _15->PACRB ={v} 0;
  56. _16 = 1073741824B;
  57. _16->PACRD ={v} 0;
  58. _17 = 1073741824B;
  59. _17->OPACR[0] ={v} 0;
  60. _18 = 1073741824B;
  61. _18->OPACR[1] ={v} 0;
  62. _19 = 1073741824B;
  63. _19->OPACR[2] ={v} 0;
  64. _20 = 1073741824B;
  65. _20->OPACR[3] ={v} 0;
  66. _21 = 1073741824B;
  67. _21->OPACR[4] ={v} 0;
  68. _22 = 1073741824B;
  69. _22->OPACR[5] ={v} 0;
  70. _23 = 1073741824B;
  71. _23->OPACR[6] ={v} 0;
  72. _24 = 1073741824B;
  73. _24->OPACR[7] ={v} 0;
  74. _25 = 1073741824B;
  75. _25->OPACR[8] ={v} 0;
  76. _26 = 1073741824B;
  77. _26->OPACR[9] ={v} 0;
  78. _27 = 1073741824B;
  79. _27->OPACR[10] ={v} 0;
  80. _28 = 1073741824B;
  81. _28->OPACR[11] ={v} 0;
  82. __asm__ __volatile__("dsb");
  83. __asm__ __volatile__("isb");
  84. sys_m4_cache_init (0);
  85. return;
  86. }
  87. Sys_GetCoreID ()
  88. {
  89. uint8 D.6226;
  90. uint8 _1;
  91. <bb 2> :
  92. _1 = 0;
  93. <bb 3> :
  94. <L0>:
  95. return _1;
  96. }
  97. default_interrupt_routine ()
  98. {
  99. <bb 2> :
  100. goto <bb 2>; [INV]
  101. }
  102. startup_go_to_user_mode ()
  103. {
  104. <bb 2> :
  105. return;
  106. }
  107. sys_m4_cache_init (uint8 cache)
  108. {
  109. uint8 RetValue;
  110. uint8 D.6224;
  111. struct LMEM_Type * _1;
  112. struct LMEM_Type * _2;
  113. long unsigned int _3;
  114. struct LMEM_Type * _4;
  115. long unsigned int _5;
  116. struct LMEM_Type * _6;
  117. long unsigned int _7;
  118. long unsigned int _8;
  119. struct LMEM_Type * _9;
  120. long unsigned int _10;
  121. struct LMEM_Type * _11;
  122. long unsigned int _12;
  123. uint8 _22;
  124. <bb 2> :
  125. RetValue_15 = 0;
  126. if (cache_16(D) == 0)
  127. goto <bb 3>; [INV]
  128. else
  129. goto <bb 6>; [INV]
  130. <bb 3> :
  131. _1 = 3758628864B;
  132. _1->PCCCR ={v} 83886080;
  133. _2 = 3758628864B;
  134. _3 ={v} _2->PCCCR;
  135. _4 = 3758628864B;
  136. _5 = _3 | 2147483648;
  137. _4->PCCCR ={v} _5;
  138. <bb 4> :
  139. _6 = 3758628864B;
  140. _7 ={v} _6->PCCCR;
  141. _8 = _7 & 2147483648;
  142. if (_8 == 2147483648)
  143. goto <bb 4>; [INV]
  144. else
  145. goto <bb 5>; [INV]
  146. <bb 5> :
  147. _9 = 3758628864B;
  148. _10 ={v} _9->PCCCR;
  149. _11 = 3758628864B;
  150. _12 = _10 | 1;
  151. _11->PCCCR ={v} _12;
  152. goto <bb 7>; [INV]
  153. <bb 6> :
  154. RetValue_17 = 1;
  155. <bb 7> :
  156. # RetValue_13 = PHI <RetValue_15(5), RetValue_17(6)>
  157. _22 = RetValue_13;
  158. <bb 8> :
  159. <L6>:
  160. return _22;
  161. }