Dma_Ip_Cfg_DeviceRegistersV2.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. /*==================================================================================================
  2. * Project : RTD AUTOSAR 4.4
  3. * Platform : CORTEXM
  4. * Peripheral : DMA,CACHE,TRGMUX,FLEXIO
  5. * Dependencies : none
  6. *
  7. * Autosar Version : 4.4.0
  8. * Autosar Revision : ASR_REL_4_4_REV_0000
  9. * Autosar Conf.Variant :
  10. * SW Version : 1.0.0
  11. * Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
  12. *
  13. * (c) Copyright 2020-2021 NXP Semiconductors
  14. * All Rights Reserved.
  15. *
  16. * NXP Confidential. This software is owned or controlled by NXP and may only be
  17. * used strictly in accordance with the applicable license terms. By expressly
  18. * accepting such terms or by downloading, installing, activating and/or otherwise
  19. * using the software, you are agreeing that you have read, and that you agree to
  20. * comply with and are bound by, such license terms. If you do not agree to be
  21. * bound by the applicable license terms, then you may not retain, install,
  22. * activate or otherwise use the software.
  23. ==================================================================================================*/
  24. /* Prevention from multiple including the same header */
  25. #ifndef DMA_IP_CFG_DEVICE_REGISTERS_V2_H_
  26. #define DMA_IP_CFG_DEVICE_REGISTERS_V2_H_
  27. /**
  28. * @file Dma_Ip_Cfg_DeviceRegistersV2.h
  29. *
  30. * @version 1.0.0
  31. *
  32. * @brief AUTOSAR Mcl - Dma Ip Cfg Device Register V2 header file.
  33. * @details Contains common register information and specific register information for
  34. * DMA Hardware Version 2.
  35. *
  36. * @addtogroup DMA_IP_DRIVER DMA IP Driver
  37. * @{
  38. */
  39. #ifdef __cplusplus
  40. extern "C"
  41. {
  42. #endif
  43. /*==================================================================================================
  44. INCLUDE FILES
  45. 1) system and project includes
  46. 2) needed interfaces from external units
  47. 3) internal and external interfaces from this unit
  48. ==================================================================================================*/
  49. #include "Mcal.h"
  50. #include "BasicTypes.h"
  51. #include "S32K144_DMAMUX.h"
  52. #include "S32K144_DMA.h"
  53. /*==================================================================================================
  54. SOURCE FILE VERSION INFORMATION
  55. ==================================================================================================*/
  56. #define DMA_IP_CFG_DEVICEREGISTERSV2_VENDOR_ID_H 43
  57. #define DMA_IP_CFG_DEVICEREGISTERSV2_AR_RELEASE_MAJOR_VERSION_H 4
  58. #define DMA_IP_CFG_DEVICEREGISTERSV2_AR_RELEASE_MINOR_VERSION_H 4
  59. #define DMA_IP_CFG_DEVICEREGISTERSV2_AR_RELEASE_REVISION_VERSION_H 0
  60. #define DMA_IP_CFG_DEVICEREGISTERSV2_SW_MAJOR_VERSION_H 1
  61. #define DMA_IP_CFG_DEVICEREGISTERSV2_SW_MINOR_VERSION_H 0
  62. #define DMA_IP_CFG_DEVICEREGISTERSV2_SW_PATCH_VERSION_H 0
  63. /*==================================================================================================
  64. FILE VERSION CHECKS
  65. ==================================================================================================*/
  66. #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
  67. /* Check if header file and Mcal header file are of the same Autosar version */
  68. #if ((DMA_IP_CFG_DEVICEREGISTERSV2_AR_RELEASE_MAJOR_VERSION_H != MCAL_AR_RELEASE_MAJOR_VERSION) || \
  69. (DMA_IP_CFG_DEVICEREGISTERSV2_AR_RELEASE_MINOR_VERSION_H != MCAL_AR_RELEASE_MINOR_VERSION))
  70. #error "AutoSar Version Numbers of Dma_Ip_Cfg_DeviceRegisters.h and Mcal.h are different"
  71. #endif
  72. #endif
  73. /*==================================================================================================
  74. DEFINES AND MACROS
  75. ==================================================================================================*/
  76. /*-----------------------------------------------/
  77. / SOC SPECIFIC DMAMUX INSTANCES /
  78. /-----------------------------------------------*/
  79. #define DMA_IP_DMAMUX_BASE_PTRS IP_DMAMUX_BASE_PTRS
  80. #define DMA_IP_HWV2_DMAMUX_NOF_INST ((uint32)DMAMUX_INSTANCE_COUNT)
  81. /*-----------------------------------------------/
  82. / SOC SPECIFIC DMAMUX CHANNELS /
  83. /-----------------------------------------------*/
  84. #define DMA_IP_HWV2_DMAMUX_NOF_CHANNELS ((uint32)DMAMUX_CHCFG_COUNT)
  85. #define DMA_IP_HWV2_DMAMUX_REG_INDEX_CONV(x) ((uint32)(x))
  86. /*-----------------------------------------------/
  87. / SOC SPECIFIC DMA INSTANCES /
  88. /-----------------------------------------------*/
  89. #define DMA_IP_BASE (IP_DMA_BASE)
  90. #define DMA_IP_PTR ((Dma_Ip_Hwv2InstRegType *)DMA_IP_BASE)
  91. #define DMA_IP_DMA_HWV2_BASE_PTRS { DMA_IP_PTR }
  92. #define DMA_IP_HWV2_DMA_MP_GRPRI_COUNT DMA_IP_MP_GRPRI_COUNT
  93. #define DMA_IP_HWV2_DMA_NOF_INST DMA_INSTANCE_COUNT /* Total number of hardware instances */
  94. #define DMA_IP_HWV2_PRIOLVL_REG_INDEX_CONV(x) ((uint32)(x) ^ 3U)
  95. /*-----------------------------------------------/
  96. / SOC SPECIFIC DMA CHANNELS /
  97. /-----------------------------------------------*/
  98. #define DMA_IP_TCD_BASE (IP_DMA_BASE + 4096U)
  99. #define DMA_IP_TCD_PTR ((Dma_Ip_Hwv2TcdArrayType *)DMA_IP_TCD_BASE)
  100. #define DMA_IP_TCD_HWV2_BASE_PTRS { DMA_IP_TCD_PTR }
  101. #define DMA_IP_TCD_RESERVED (0U) /* Reserved space between hardware TCDs */
  102. #define DMA_IP_HWV2_TCD_NOF_CH DMA_TCD_COUNT /* Number of hardware channels */
  103. #define DMA_IP_HWV2_TCD_NOF_INST DMA_INSTANCE_COUNT /* Number of hardware TCD instances */
  104. /*-----------------------------------------------/
  105. / SOC SPECIFIC DMA TOTAL CHANNELS /
  106. /-----------------------------------------------*/
  107. #define DMA_IP_NOF_HWV2_CH (DMA_IP_HWV2_TCD_NOF_INST * DMA_IP_HWV2_TCD_NOF_CH) /* Total number of hardware channels of all instances */
  108. /*-----------------------------------------------/
  109. / SOC SPECIFIC DMA TCD ALIGNMENT /
  110. /-----------------------------------------------*/
  111. #define DMA_IP_TCD_NOT_ALIGNED STD_OFF
  112. /*==================================================================================================
  113. COMMON DMA REGISTER PROTECTION
  114. ==================================================================================================*/
  115. /*-----------------------------------------------/
  116. / DMA REGISTER PROTECTION SIZE /
  117. /-----------------------------------------------*/
  118. #define DMA_IP_REG_PROT_SIZE ((uint32)0x4U)
  119. /*-----------------------------------------------/
  120. / DMA BASE REGISTER ADDRESS /
  121. /-----------------------------------------------*/
  122. #define DMA_IP_BASE_ADDR(instIdx) ((uint32)IP_DMA_BASE)
  123. #define DMA_IP_CSR_BASE_ADDR(instIdx) \
  124. ((uint32)(DMA_IP_BASE_ADDR(instIdx)))
  125. /*-----------------------------------------------/
  126. / DMAMUX BASE REGISTER ADDRESS /
  127. /-----------------------------------------------*/
  128. #define DMA_IP_DMAMUX_BASE_ADDR(instIdx) \
  129. ((uint32)(((instIdx)>0UL) ? \
  130. (DMAMUX_1_BASE) : (DMAMUX_0_BASE)))
  131. /*==================================================================================================
  132. DMA MP STRUCTURE
  133. ==================================================================================================*/
  134. typedef struct {
  135. __IO uint32_t reg_CR; /**< Control Register, offset: 0x0 */
  136. __I uint32_t reg_ES; /**< Error Status Register, offset: 0x4 */
  137. uint8_t RESERVED_0[4];
  138. __IO uint32_t reg_ERQ; /**< Enable Request Register, offset: 0xC */
  139. uint8_t RESERVED_1[4];
  140. __IO uint32_t reg_EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
  141. __O uint8_t reg_CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
  142. __O uint8_t reg_SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
  143. __O uint8_t reg_CERQ; /**< Clear Enable Request Register, offset: 0x1A */
  144. __O uint8_t reg_SERQ; /**< Set Enable Request Register, offset: 0x1B */
  145. __O uint8_t reg_CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
  146. __O uint8_t reg_SSRT; /**< Set START Bit Register, offset: 0x1D */
  147. __O uint8_t reg_CERR; /**< Clear Error Register, offset: 0x1E */
  148. __O uint8_t reg_CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
  149. uint8_t RESERVED_2[4];
  150. __IO uint32_t reg_INT; /**< Interrupt Request Register, offset: 0x24 */
  151. uint8_t RESERVED_3[4];
  152. __IO uint32_t reg_ERR; /**< Error Register, offset: 0x2C */
  153. uint8_t RESERVED_4[4];
  154. __I uint32_t reg_HRS; /**< Hardware Request Status Register, offset: 0x34 */
  155. uint8_t RESERVED_5[12];
  156. __IO uint32_t reg_EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
  157. uint8_t RESERVED_6[184];
  158. __IO uint8_t reg_DCHPRI[DMA_DCHPRI_COUNT]; /**< Channel n Priority Register, array offset: 0x100, array step: 0x1 */
  159. uint8_t RESERVED_7[3824];
  160. } Dma_Ip_Hwv2InstRegType;
  161. /*==================================================================================================
  162. TCD STRUCTURE
  163. ==================================================================================================*/
  164. typedef struct {
  165. uint32 reg_SADDR; /**< @brief TCD Source Address, array offset: 0x20, array step: 0x1000 */
  166. uint16 reg_SOFF; /**< @brief TCD Signed Source Address Offset, array offset: 0x24, array step: 0x1000 */
  167. uint16 reg_ATTR; /**< @brief TCD Transfer Attributes, array offset: 0x26, array step: 0x1000 */
  168. union { /* offset: 0x28, array step: 0x1000 */
  169. uint32 reg_MLOFFNO; /**< @brief TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */
  170. uint32 reg_MLOFFYES; /**< @brief TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x28, array step: 0x1000 */
  171. } reg_NBYTES;
  172. uint32 reg_SLAST; /**< @brief TCD Last Source Address Adjustment / Store reg_DADDR Address Register, array offset: 0x2C, array step: 0x1000 */
  173. uint32 reg_DADDR; /**< @brief TCD Destination Address, array offset: 0x30, array step: 0x1000 */
  174. uint16 reg_DOFF; /**< @brief TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x1000 */
  175. union { /* offset: 0x36, array step: 0x1000 */
  176. uint16 reg_ELINKNO; /**< @brief TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x36, array step: 0x1000 */
  177. uint16 reg_ELINKYES; /**< @brief TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x36, array step: 0x1000 */
  178. } reg_CITER;
  179. uint32 reg_DLAST_SGA; /**< @brief TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x38, array step: 0x1000 */
  180. uint16 reg_CSR; /**< @brief TCD Control and Status Register, array offset: 0x3C, array step: 0x1000 */
  181. union { /* offset: 0x3E, array step: 0x1000 */
  182. uint16 reg_ELINKNO; /**< @brief TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x3E, array step: 0x1000 */
  183. uint16 reg_ELINKYES; /**< @brief TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x3E, array step: 0x1000 */
  184. } reg_BITER;
  185. } Dma_Ip_TcdRegType, Dma_Ip_SwTcdRegType;
  186. typedef struct {
  187. Dma_Ip_TcdRegType tTcdReg;
  188. } Dma_Ip_Hwv2ChTcdRegType;
  189. #if (DMA_IP_TCD_NOT_ALIGNED == STD_OFF)
  190. typedef struct {
  191. struct {
  192. Dma_Ip_Hwv2ChTcdRegType tChTcdReg;
  193. } TCD_RSV[DMA_IP_HWV2_TCD_NOF_CH];
  194. } Dma_Ip_Hwv2TcdArrayType;
  195. #endif
  196. /*==================================================================================================
  197. DMAMUX CH STRUCTURE
  198. ==================================================================================================*/
  199. typedef uint8 Dma_Ip_MuxRegType;
  200. #ifdef __cplusplus
  201. }
  202. #endif
  203. /** @} */
  204. #endif /* #ifndef DMA_IP_CFG_DEVICE_REGISTERS_V2_H_ */
  205. /*==================================================================================================
  206. * END OF FILE
  207. ==================================================================================================*/