Ram_Ip_Cfg_Defines.h 3.9 KB

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  1. /*==================================================================================================
  2. * Project : RTD AUTOSAR 4.4
  3. * Platform : CORTEXM
  4. * Peripheral :
  5. * Dependencies : none
  6. *
  7. * Autosar Version : 4.4.0
  8. * Autosar Revision : ASR_REL_4_4_REV_0000
  9. * Autosar Conf.Variant :
  10. * SW Version : 1.0.0
  11. * Build Version : S32K1_RTD_1_0_0_HF01_D2109_ASR_REL_4_4_REV_0000_20210907
  12. *
  13. * (c) Copyright 2020-2021 NXP Semiconductors
  14. * All Rights Reserved.
  15. *
  16. * NXP Confidential. This software is owned or controlled by NXP and may only be
  17. * used strictly in accordance with the applicable license terms. By expressly
  18. * accepting such terms or by downloading, installing, activating and/or otherwise
  19. * using the software, you are agreeing that you have read, and that you agree to
  20. * comply with and are bound by, such license terms. If you do not agree to be
  21. * bound by the applicable license terms, then you may not retain, install,
  22. * activate or otherwise use the software.
  23. ==================================================================================================*/
  24. /**
  25. * @file Ram_Ip_Cfg_Defines.h
  26. * @version 1.0.0
  27. *
  28. * @brief AUTOSAR Mcu - Post-Build(PB) configuration file code template.
  29. * @details Code template for Post-Build(PB) configuration file generation.
  30. *
  31. * @addtogroup RAM_DRIVER_CONFIGURATION Ram Ip Driver
  32. * @{
  33. */
  34. #ifndef RAM_IP_CFG_DEFINES_H
  35. #define RAM_IP_CFG_DEFINES_H
  36. #ifdef __cplusplus
  37. extern "C"{
  38. #endif
  39. /*==================================================================================================
  40. INCLUDE FILES
  41. 1) system and project includes
  42. 2) needed interfaces from external units
  43. 3) internal and external interfaces from this unit
  44. ==================================================================================================*/
  45. /*==================================================================================================
  46. SOURCE FILE VERSION INFORMATION
  47. ==================================================================================================*/
  48. #define RAM_IP_CFG_DEFINES_VENDOR_ID 43
  49. #define RAM_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION 4
  50. #define RAM_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION 4
  51. #define RAM_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION 0
  52. #define RAM_IP_CFG_DEFINES_SW_MAJOR_VERSION 1
  53. #define RAM_IP_CFG_DEFINES_SW_MINOR_VERSION 0
  54. #define RAM_IP_CFG_DEFINES_SW_PATCH_VERSION 0
  55. /*==================================================================================================
  56. * FILE VERSION CHECKS
  57. ==================================================================================================*/
  58. /*==================================================================================================
  59. DEFINES AND MACROS
  60. ==================================================================================================*/
  61. /**
  62. * @brief Pre-processor switch to enable/disable the API Ram_Ip_GetRamState.
  63. */
  64. #define RAM_IP_GET_RAM_STATE_API (STD_OFF)
  65. /**
  66. * @brief HW sseries used.
  67. */
  68. #define RAM_IP_S32K1
  69. /*==================================================================================================
  70. ENUMS
  71. ==================================================================================================*/
  72. /*==================================================================================================
  73. STRUCTURES AND OTHER TYPEDEFS
  74. ==================================================================================================*/
  75. #ifdef __cplusplus
  76. }
  77. #endif
  78. #endif /* #ifndef RAM_IP_CFG_DEFINES_H */
  79. /** @} */