|
@@ -6,16 +6,16 @@ const uint16_T blcc_T_close = 125U;
|
|
|
const uint16_T blcc_T_open = 100U;
|
|
|
const uint16_T blcc_V_low = 10U;
|
|
|
|
|
|
-const uint16_T cmnc_Q_ratedCp = 500U;
|
|
|
-const uint16_T cmnc_num_cellUNum = 20U;
|
|
|
-const uint16_T cmnc_num_modTNum = 4U;
|
|
|
-const uint16_T cmnc_tm_parkTime = 1800U;
|
|
|
+const uint16_T cmnc_Q_ratedCp = 500U;
|
|
|
+const uint16_T cmnc_num_cellUNum = 20U;
|
|
|
+const uint16_T cmnc_num_modTNum = 4U;
|
|
|
+const uint16_T cmnc_tm_parkTime = 300U;
|
|
|
const uint16_T cmnm_F_polar[13] = {1152U, 4862U, 12567U, 20299U, 23334U, 226124U, 23075U, 17084U, 14510U, 15551U, 17127U, 17475U, 20043U};
|
|
|
-const uint16_T cmnm_R_ohm[13] = {2364U, 2284U, 2234U, 2166U, 2128U, 2111U, 2090U, 2077U, 2077U, 2072U, 2085U, 2090U, 2077U};
|
|
|
-const uint16_T cmnm_R_polar[13] = {4955U, 2073U, 1504U, 1197U, 1098U, 1072U, 1141U, 1700U, 1637U, 1626U, 1496U, 1486U, 1436U};
|
|
|
-const uint16_T cmnm_V_ocv[13] = {3327U, 3453U, 3487U, 3563U, 3617U, 3652U, 3700U, 3791U, 3897U, 4006U, 4129U, 4197U, 4276U};
|
|
|
-const uint16_T cmnm_pct_soc[13] = {0U, 50U, 100U, 200U, 300U, 400U, 500U, 600U, 700U, 800U, 900U, 950U, 1000U};
|
|
|
-const uint16_T cmnc_V_chrgFul = 4200U;
|
|
|
+const uint16_T cmnm_R_ohm[13] = {2364U, 2284U, 2234U, 2166U, 2128U, 2111U, 2090U, 2077U, 2077U, 2072U, 2085U, 2090U, 2077U};
|
|
|
+const uint16_T cmnm_R_polar[13] = {4955U, 2073U, 1504U, 1197U, 1098U, 1072U, 1141U, 1700U, 1637U, 1626U, 1496U, 1486U, 1436U};
|
|
|
+const uint16_T cmnm_V_ocv[13] = {3327U, 3453U, 3487U, 3563U, 3617U, 3652U, 3700U, 3791U, 3897U, 4006U, 4129U, 4197U, 4276U};
|
|
|
+const uint16_T cmnm_pct_soc[13] = {0U, 50U, 100U, 200U, 300U, 400U, 500U, 600U, 700U, 800U, 900U, 950U, 1000U};
|
|
|
+const uint16_T cmnc_V_chrgFul = 4200U;
|
|
|
const uint16_T cmnm_R_voloffset[28] = {0, 0, 0, 0, 0,
|
|
|
0, 770, 0, 0, 0,
|
|
|
0, 0, 0, 540, 0,
|
|
@@ -89,15 +89,15 @@ const uint16_T sfmc_flg_cellUDiffThrFlt2 = 300U;
|
|
|
const uint16_T sfmc_flg_cellUDiffThrRec1 = 250U;
|
|
|
const uint16_T sfmc_flg_cellUDiffThrRec2 = 250U;
|
|
|
|
|
|
-const uint16_T sohc_Q_countThr = 60U;
|
|
|
+const uint16_T sohc_Q_countThr = 10U;
|
|
|
const uint16_T sohc_Q_updateDeltThr = 200U;
|
|
|
const uint16_T sohc_pct_low = 300U;
|
|
|
const uint16_T sohc_pct_up = 500U;
|
|
|
|
|
|
const uint16_T socc_pct_battSocLow = 0U;
|
|
|
-const uint16_T socc_pct_battSocUp = 930U;
|
|
|
+const uint16_T socc_pct_battSocUp = 930U;
|
|
|
const int16_T socm_I_chrgCor[3] = {50, 100, 150};
|
|
|
-const int16_T socm_I_disChrgCor[3] = {-240, -160, -100};
|
|
|
+const int16_T socm_I_disChrgCor[3] = {-240, -160, -100};
|
|
|
const uint16_T socm_V_chrgCor[3] = {4160U, 4175U, 4188U};
|
|
|
const uint16_T socm_V_disChrgCor[3] = {3238U, 3319U, 3369U};
|
|
|
const uint16_T socc_pct_chrgCor = 910;
|