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@@ -1,2036 +1,689 @@
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-/*
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- * File: SOC.c
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- *
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- * Code generated for Simulink model 'SOC'.
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- *
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- * Model version : 1.51
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- * Simulink Coder version : 9.4 (R2020b) 29-Jul-2020
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- * C/C++ source code generated on : Thu Sep 9 17:18:48 2021
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- *
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- * Target selection: ert.tlc
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- * Embedded hardware selection: Intel->x86-64 (Windows64)
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- * Code generation objectives: Unspecified
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- * Validation result: Not run
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- */
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-
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#include "SOC.h"
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-#include "SOC_private.h"
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-#include "div_nde_s32_floor.h"
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-#include "div_repeat_s16s32_floor.h"
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-#include "div_repeat_u32.h"
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#include "look1_is16lu16n16tu16_binlcase.h"
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#include "look1_iu16lu16n16tu16_binlcase.h"
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-#include "mul_u32_hiSR_near.h"
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-
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-MdlrefDW_SOC_T SOC_MdlrefDW;
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-
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-/* Block signals (default storage) */
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-B_SOC_c_T SOC_B;
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-
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-/* Block states (default storage) */
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-DW_SOC_f_T SOC_DW;
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-
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-/* Previous zero-crossings (trigger) states */
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-ZCE_SOC_T SOC_PrevZCX;
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-
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-/*
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- * Output and update for atomic system:
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- * '<S21>/MATLAB Function'
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- * '<S30>/MATLAB Function'
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- */
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-void SOC_MATLABFunction(real_T rtu_x, real_T *rty_y)
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-{
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- *rty_y = ((((((-2.8104E-13 * pow(rtu_x, 7.0) + 1.0283E-10 * pow(rtu_x, 6.0)) +
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- -1.5072E-8 * pow(rtu_x, 5.0)) + 1.1295E-6 * pow(rtu_x, 4.0)) +
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- -4.588E-5 * pow(rtu_x, 3.0)) + rtu_x * rtu_x * 0.000993) +
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- -0.010548 * rtu_x) + 0.04876;
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-}
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-
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-/*
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- * Output and update for action system:
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- * '<S37>/If Action Subsystem'
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- * '<S42>/If Action Subsystem'
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- */
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-void SOC_IfActionSubsystem(uint16_T rtu_SOC, uint16_T rtu_SOCfit, uint16_T
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- *rty_Out1, uint16_T rtp_m)
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-{
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- int32_T tmp;
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- /* MinMax: '<S38>/Min1' incorporates:
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- * Constant: '<S38>/Constant4'
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- * Sum: '<S38>/Add4'
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- */
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- tmp = (int16_T)(rtu_SOC - rtu_SOCfit);
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- if (tmp >= rtp_m) {
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- tmp = rtp_m;
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- }
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- /* Sum: '<S38>/Add3' incorporates:
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- * MinMax: '<S38>/Min1'
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- */
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- *rty_Out1 = (uint16_T)((uint32_T)(uint16_T)tmp + rtu_SOCfit);
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-}
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-
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-/*
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- * Output and update for action system:
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- * '<S37>/If Action Subsystem1'
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- * '<S42>/If Action Subsystem1'
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- */
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-void SOC_IfActionSubsystem1(uint16_T rtu_SOC, uint16_T rtu_SOCfit, uint16_T
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- *rty_Out1)
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-{
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- int16_T rtb_Add4_o;
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-
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- /* Sum: '<S39>/Add4' */
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- rtb_Add4_o = (int16_T)(rtu_SOC - rtu_SOCfit);
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-
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- /* MinMax: '<S39>/Min1' incorporates:
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- * Constant: '<S39>/Constant4'
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- * Sum: '<S39>/Add4'
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- */
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- if (rtb_Add4_o <= -1) {
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- rtb_Add4_o = -1;
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- }
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+boolean_T FirstRun_SOC;
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- /* End of MinMax: '<S39>/Min1' */
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- /* Sum: '<S39>/Add3' */
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- *rty_Out1 = (uint16_T)(rtb_Add4_o + rtu_SOCfit);
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-}
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-
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-/* System initialize for referenced model: 'SOC' */
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+//---------------SOC初始化-----------------------------------------------
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void SOC_Init(void)
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-{
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- /* Start for If: '<S7>/If' */
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- SOC_DW.If_ActiveSubsystem = -1;
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-
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- /* InitializeConditions for UnitDelay: '<S1>/FirstDelay' */
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- SOC_DW.FirstDelay_DSTATE = true;
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-
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- /* InitializeConditions for UnitDelay: '<S14>/Frist' */
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- SOC_DW.Frist_DSTATE = true;
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-
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- /* InitializeConditions for UnitDelay: '<S23>/Frist' */
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- SOC_DW.Frist_DSTATE_h = true;
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-
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- /* InitializeConditions for UnitDelay: '<S12>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE[0] = 1000.0;
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-
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- /* InitializeConditions for UnitDelay: '<S13>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE_m[0] = 1000.0;
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-
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- /* InitializeConditions for UnitDelay: '<S12>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE[1] = 0.0;
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-
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- /* InitializeConditions for UnitDelay: '<S13>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE_m[1] = 0.0;
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-
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- /* InitializeConditions for UnitDelay: '<S12>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE[2] = 0.0;
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-
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- /* InitializeConditions for UnitDelay: '<S13>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE_m[2] = 0.0;
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-
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- /* InitializeConditions for UnitDelay: '<S12>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE[3] = 1000.0;
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-
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- /* InitializeConditions for UnitDelay: '<S13>/P_Delay' */
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- SOC_DW.P_Delay_DSTATE_m[3] = 1000.0;
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-
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- /* InitializeConditions for UnitDelay: '<S4>/ ' */
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- SOC_DW._DSTATE = 10;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/First_Delay' */
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- SOC_DW.First_Delay_DSTATE = true;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/ihd_st_chrgSta_Delay' */
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- SOC_DW.ihd_st_chrgSta_Delay_DSTATE = 1U;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/Unit Delay7' */
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- SOC_DW.UnitDelay7_DSTATE = 10U;
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-
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- /* InitializeConditions for UnitDelay: '<S35>/Time_Delay' */
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- SOC_DW.Time_Delay_DSTATE = 1U;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/socd_pct_battSoc0_Delay' */
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- SOC_DW.socd_pct_battSoc0_Delay_DSTATE = 10U;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/First_Delay1' */
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- SOC_DW.First_Delay1_DSTATE = true;
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-
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- /* InitializeConditions for UnitDelay: '<S6>/socd_pct_bcusocDelay' */
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- SOC_DW.socd_pct_bcusocDelay_DSTATE = 10U;
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-
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- /* InitializeConditions for Switch: '<S6>/Switch2' incorporates:
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- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
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- */
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- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE = 10U;
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-
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- /* SystemInitialize for IfAction SubSystem: '<S7>/chrgCCV' */
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- /* InitializeConditions for UnitDelay: '<S59>/Time_Delay' */
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- SOC_DW.Time_Delay_DSTATE_g = 1U;
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+{
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+ FirstRun_SOC = true;
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- /* InitializeConditions for UnitDelay: '<S57>/socn_pct_estsoc_Delay' */
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- SOC_DW.socn_pct_estsoc_Delay_DSTATE = 10U;
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-
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- /* InitializeConditions for UnitDelay: '<S58>/Time_Delay' */
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- SOC_DW.Time_Delay_DSTATE_f = 1U;
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-
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- /* End of SystemInitialize for SubSystem: '<S7>/chrgCCV' */
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-
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- /* SystemInitialize for IfAction SubSystem: '<S7>/disChrgCCV' */
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- /* InitializeConditions for UnitDelay: '<S61>/Time_Delay' */
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- SOC_DW.Time_Delay_DSTATE_e = 1U;
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-
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- /* End of SystemInitialize for SubSystem: '<S7>/disChrgCCV' */
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-
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- /* SystemInitialize for IfAction SubSystem: '<S7>/If Action Subsystem' */
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- /* InitializeConditions for UnitDelay: '<S52>/Unit Delay1' */
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- SOC_DW.UnitDelay1_DSTATE = true;
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-
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- /* InitializeConditions for UnitDelay: '<S53>/Unit Delay1' */
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- SOC_DW.UnitDelay1_DSTATE_p = true;
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-
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- /* End of SystemInitialize for SubSystem: '<S7>/If Action Subsystem' */
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-
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- /* SystemInitialize for IfAction SubSystem: '<S6>/Subsystem2' */
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- /* InitializeConditions for UnitDelay: '<S37>/socfit_Delay' */
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- SOC_DW.socfit_Delay_DSTATE_n = 2000U;
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- SOC_DW.fulFLg_reset_DSTATE=0;
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- SOC_DW.overFlg_reset_DSTATE=0;
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- SOC_DW.lowFLg_Delay_DSTATE=0;
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-
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- /* End of SystemInitialize for SubSystem: '<S6>/Subsystem2' */
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-}
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-
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-/* Disable for referenced model: 'SOC' */
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-void SOC_Disable(void)
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-{
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- /* Disable for If: '<S7>/If' */
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- SOC_DW.If_ActiveSubsystem = -1;
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}
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+//-------------------------------------------------------------------------
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-/* Output and update for referenced model: 'SOC' */
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void SOC(void)
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{
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- real_T rtb_MatrixConcatenate[4];
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- real_T rtb_P_Delay[4];
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- real_T tmp[4];
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- real_T rtb_Divide[2];
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- real_T rtb_Product2_i[2];
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- real_T rtb_TmpSignalConversionAtProduc[2];
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- real_T tmp_0[2];
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- real_T P_Delay_DSTATE_tmp_0;
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- real_T rtb_Abs;
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- real_T rtb_Add1;
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- real_T rtb_Add1_h;
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- real_T rtb_Add1_tmp_tmp;
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- real_T rtb_Add_l;
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- real_T rtb_Divide_d;
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- real_T rtb_Gain1_m;
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- real_T rtb_MathFunction;
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- real_T rtb_TmpSignalConversionAtProd_0;
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- real_T tmp_1;
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- int32_T P_Delay_DSTATE_tmp;
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- int32_T i;
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- uint32_T tmp_2;
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- int16_T rtb_Add1_a;
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- int16_T rtb_Saturation_k;
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- uint16_T rtb_Merge;
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- uint16_T rtb_socd_pct_bcuSoc0_Delay;
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- uint16_T rtb_uDLookupTable3;
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- int8_T rtPrevAction;
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- boolean_T rtb_LogicalOperator1_j;
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-
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- /* Outputs for Enabled SubSystem: '<S1>/Inti_correct' incorporates:
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- * EnablePort: '<S5>/Enable'
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- */
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- /* Outputs for Enabled SubSystem: '<S1>/EEcheck' incorporates:
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- * EnablePort: '<S2>/Enable'
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- */
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- /* UnitDelay: '<S1>/FirstDelay' */
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- if (SOC_DW.FirstDelay_DSTATE) {
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- /* If: '<S2>/If' incorporates:
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- * Inport: '<Root>/socd_pct_battSocEi'
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- * Inport: '<Root>/socd_pct_bcuSocEi'
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- * Logic: '<S10>/Logical Operator'
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- * RelationalOperator: '<S10>/Relational Operator'
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- * RelationalOperator: '<S10>/Relational Operator1'
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- */
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- if ((socd_pct_battSocEi > 1000) || (socd_pct_bcuSocEi > 1000)) {
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- /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem' incorporates:
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- * ActionPort: '<S8>/Action Port'
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- */
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- /* Lookup_n-D: '<S8>/OCV-SOC' incorporates:
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- * Inport: '<Root>/sfmd_V_cellUAvrg'
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- */
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- SOC_B.Switch = look1_iu16lu16n16tu16_binlcase(sfmd_V_cellUAvrg,
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- (&(cmnm_V_ocv[0])), (&(cmnm_pct_soc[0])), 12U);
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-
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- /* Merge: '<S2>/socn_pct_bcuSocEE_Merge' incorporates:
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- * Lookup_n-D: '<S8>/OCV-SOC'
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- * SignalConversion: '<S8>/Signal Conversion1'
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- */
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- SOC_B.socn_pct_bcuSocEE_Merge = SOC_B.Switch;
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-
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- /* End of Outputs for SubSystem: '<S2>/If Action Subsystem' */
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- } else {
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- /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem1' incorporates:
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- * ActionPort: '<S9>/Action Port'
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- */
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- /* Lookup_n-D: '<S8>/OCV-SOC' incorporates:
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- * Inport: '<S9>/socd_pct_battSocEi'
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- * Merge: '<S2>/socn_pct_battSocEE_Merge'
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- */
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- SOC_B.Switch = socd_pct_battSocEi;
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-
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- /* Merge: '<S2>/socn_pct_bcuSocEE_Merge' incorporates:
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- * Inport: '<S9>/socd_pct_bcuSocEi'
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- */
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- SOC_B.socn_pct_bcuSocEE_Merge = socd_pct_bcuSocEi;
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-
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- /* End of Outputs for SubSystem: '<S2>/If Action Subsystem1' */
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+ static uint16_T socn_pct_battSocEE;
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+ static uint16_T socn_pct_bcuSocEE;
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+ static uint16_T socn_Q_cap;
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+ //
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+ uint16_T EKFSOCMin;
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+ uint16_T EKFSOCMax;
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+ boolean_T socn_flg_ekfInvalidMin;
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+ boolean_T socn_flg_ekfInvalidMax;
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+ boolean_T socn_flg_ekfInvalid;
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+ real_T ocv;
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+ real_T Ro;
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+ real_T Rp;
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+ real_T C;
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+ real_T deltU;
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+ real_T A[4];
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+ real_T B[2];
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+ real_T H[2];
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+ real_T K[2];
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+ real_T P1[4];
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+ static real_T P_Min_Delay[4];
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+ static real_T P_Max_Delay[4];
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+ real_T soc1;
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+ static real_T soc_Min_Delay;
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+ static real_T soc_Max_Delay;
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+ real_T Up1;
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+ static real_T Up_Min_Delay;
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+ static real_T Up_Max_Delay;
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+ real_T docv;
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+ real_T Q;
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+ real_T battcurr;
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+ real_T UL;
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+ uint16_T factor;
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+ uint32_T temp;
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+ //
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+ static real_T ahDelay;
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+ int16_T ahSoc;
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+ //
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+ static uint16_T ekfInvalidCntl;
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+ static boolean_T onceFlg_est;
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+ static int16_T ahSoc0_est;
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+ static uint16_T ekfSoc0_est;
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+ //
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+ static boolean_T overFlg;
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+ static boolean_T fulFlg;
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+ static uint16_T overCntl;
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+ static uint16_T fulCntl;
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+ static boolean_T onceFlg_utrckOver;
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+ static int16_T ahSoc0_utrckOver;
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+ static uint16_T estSoc0_utrckOver;
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+ static uint16_T Soc_Delay;
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+ static boolean_T lowFlg;
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+ static uint16_T lowCntl;
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+ static boolean_T onceFlg_utrckLow;
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+ static int16_T ahSoc0_utrckLow;
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+ static uint16_T estSoc0_utrckLow;
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+ uint16_T socn_pct_utrackSoc;
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+ uint16_T socTemp;
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+ static uint16_T chrgCntl;
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+ static uint16_T disChrgCntl;
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+ //
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+ static uint16_T socd_pct_battSoc_Delay;
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+ //
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+ static uint16_T statCntl;
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+ static boolean_T statFlg;
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+ static uint8_T ihd_st_chrgSta_Delay;
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+ static uint16_T socn_pct_utrackSoc_Delay;
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+ static uint16_T socd_pct_battSoc0;
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+ static uint16_T socd_pct_bcuSoc0;
|
|
|
+ static uint16_T socd_pct_bcuSoc_Delay;
|
|
|
+ uint16_T delSOC;
|
|
|
+ uint16_T bcuSoc;
|
|
|
+ int16_T coinSoc;
|
|
|
+ uint16_T x[3];
|
|
|
+ uint16_T y[3];
|
|
|
+ boolean_T Flg;
|
|
|
+ static uint16_T SocFitChrg_Delay;
|
|
|
+ static uint16_T SocFitdisChrg_Delay;
|
|
|
+ static boolean_T onceFlg_chrg;
|
|
|
+ static boolean_T onceFlg_dischrg;
|
|
|
+ uint16_T SocFitChrg;
|
|
|
+ uint16_T SocFitdisChrg;
|
|
|
+ //
|
|
|
+
|
|
|
+ if(FirstRun_SOC)
|
|
|
+ {
|
|
|
+ onceFlg_est = true;
|
|
|
+ ekfInvalidCntl = 0;
|
|
|
+ overCntl = 0;
|
|
|
+ fulCntl = 0;
|
|
|
+ lowCntl = 0;
|
|
|
+ overFlg = false;
|
|
|
+ fulFlg = false;
|
|
|
+ lowFlg = false;
|
|
|
+ onceFlg_utrckOver = true;
|
|
|
+ onceFlg_utrckLow = true;
|
|
|
+ ihd_st_chrgSta_Delay = 0;
|
|
|
+ socn_pct_utrackSoc_Delay = 0;
|
|
|
+ onceFlg_chrg = true;
|
|
|
+ onceFlg_dischrg = true;
|
|
|
+ socd_pct_battSoc_Delay = 0;
|
|
|
}
|
|
|
-
|
|
|
- /* End of If: '<S2>/If' */
|
|
|
-
|
|
|
- /* Switch: '<S5>/Switch' incorporates:
|
|
|
- * Constant: '<S5>/Constant'
|
|
|
- * Inport: '<Root>/ihd_tm_packTime'
|
|
|
- * RelationalOperator: '<S5>/Relational Operator'
|
|
|
- */
|
|
|
- if (ihd_tm_parkTime > cmnc_tm_parkTime) {
|
|
|
- /* Lookup_n-D: '<S8>/OCV-SOC' incorporates:
|
|
|
- * Inport: '<Root>/sfmd_V_cellUAvrg'
|
|
|
- * Lookup_n-D: '<S5>/OCV-SOC'
|
|
|
- * Switch: '<S5>/Switch'
|
|
|
- */
|
|
|
- SOC_B.Switch = look1_iu16lu16n16tu16_binlcase(sfmd_V_cellUAvrg,
|
|
|
- (&(cmnm_V_ocv[0])), (&(cmnm_pct_soc[0])), 12U);
|
|
|
+
|
|
|
+ //=====================================================================
|
|
|
+ ////////////////////////初始值获取//////////////////////////////////////
|
|
|
+ //=====================================================================
|
|
|
+ if(FirstRun_SOC)
|
|
|
+ { //
|
|
|
+ if ((socd_pct_battSocEi > 1000) || (socd_pct_bcuSocEi > 1000) || (socd_pct_bcuSocEi == 0 && socd_pct_battSocEi == 0))
|
|
|
+ {
|
|
|
+ socn_pct_battSocEE = look1_iu16lu16n16tu16_binlcase(sfmd_V_cellUAvrg,(&(cmnm_V_ocv[0])), (&(cmnm_pct_soc[0])), 12U);
|
|
|
+ socn_pct_bcuSocEE = look1_iu16lu16n16tu16_binlcase(sfmd_V_cellUAvrg,(&(cmnm_V_ocv[0])), (&(cmnm_pct_soc[0])), 12U);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socn_pct_battSocEE = socd_pct_battSocEi;
|
|
|
+ socn_pct_bcuSocEE = socd_pct_bcuSocEi;
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if (ihd_tm_parkTime > cmnc_tm_parkTime)
|
|
|
+ {
|
|
|
+ socn_pct_battSocEE = look1_iu16lu16n16tu16_binlcase(sfmd_V_cellUAvrg,(&(cmnm_V_ocv[0])), (&(cmnm_pct_soc[0])), 12U);
|
|
|
+ }
|
|
|
+ socn_Q_cap = (uint16_T)((uint16_T)((uint32_T)sohd_pct_bcuSoh *cmnc_Q_ratedCp / 2000U) << 1);
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S5>/Switch' */
|
|
|
-
|
|
|
- /* Product: '<S5>/Divide' incorporates:
|
|
|
- * Constant: '<S5>/Constant2'
|
|
|
- * Inport: '<Root>/sohd_pct_bcuSoh'
|
|
|
- * Product: '<S5>/Product'
|
|
|
- */
|
|
|
- SOC_B.Divide = (uint16_T)((uint16_T)((uint32_T)sohd_pct_bcuSoh *
|
|
|
- cmnc_Q_ratedCp / 2000U) << 1);
|
|
|
- }
|
|
|
-
|
|
|
- /* End of UnitDelay: '<S1>/FirstDelay' */
|
|
|
- /* End of Outputs for SubSystem: '<S1>/EEcheck' */
|
|
|
- /* End of Outputs for SubSystem: '<S1>/Inti_correct' */
|
|
|
-
|
|
|
- /* Switch: '<S14>/Switch' incorporates:
|
|
|
- * UnitDelay: '<S14>/Frist'
|
|
|
- */
|
|
|
- if (SOC_DW.Frist_DSTATE) {
|
|
|
- /* Switch: '<S14>/Switch' incorporates:
|
|
|
- * Switch: '<S5>/Switch'
|
|
|
- */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE = (real_T)SOC_B.Switch * 0.1;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S14>/Switch' */
|
|
|
-
|
|
|
- /* Product: '<S20>/Divide2' incorporates:
|
|
|
- * Constant: '<S20>/Constant'
|
|
|
- * Inport: '<Root>/sfmd_I_curr'
|
|
|
- * Product: '<S19>/Product'
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S28>/Product'
|
|
|
- * Product: '<S28>/Product2'
|
|
|
- * Product: '<S29>/Divide2'
|
|
|
- */
|
|
|
- rtb_Add1_tmp_tmp = (real_T)sfmd_I_curr * 0.1;
|
|
|
- rtb_Add1_h = rtb_Add1_tmp_tmp / 36000.0;
|
|
|
-
|
|
|
- /* Sum: '<S20>/Add1' incorporates:
|
|
|
- * Gain: '<S20>/Gain4'
|
|
|
- * Product: '<S20>/Divide'
|
|
|
- * Product: '<S20>/Divide2'
|
|
|
- * Product: '<S5>/Divide'
|
|
|
- */
|
|
|
- rtb_Add1 = rtb_Add1_h / ((real_T)SOC_B.Divide * 0.1) * 100.0 +
|
|
|
- SOC_DW.SOCk_Delay_DSTATE;
|
|
|
-
|
|
|
- /* MATLAB Function: '<S21>/MATLAB Function' */
|
|
|
- SOC_MATLABFunction(rtb_Add1, &rtb_Add_l);
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S21>/Math Function1' incorporates:
|
|
|
- * Constant: '<S21>/Constant'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProduc[0] = rtb_Add_l;
|
|
|
- rtb_TmpSignalConversionAtProduc[1] = 1.0;
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S21>/Matrix Concatenate' */
|
|
|
- rtb_MatrixConcatenate[0] = 1.0;
|
|
|
- rtb_MatrixConcatenate[1] = 0.0;
|
|
|
-
|
|
|
- /* DataTypeConversion: '<S20>/Data Type Conversion' incorporates:
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table3'
|
|
|
- */
|
|
|
- tmp_1 = fmod(floor(rtb_Add1 / 0.1), 65536.0);
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(tmp_1 < 0.0 ? (int32_T)(uint16_T)-(int16_T)
|
|
|
- (uint16_T)-tmp_1 : (int32_T)(uint16_T)tmp_1);
|
|
|
-
|
|
|
- /* Gain: '<S20>/Gain1' incorporates:
|
|
|
- * DataTypeConversion: '<S20>/Data Type Conversion3'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table3'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table4'
|
|
|
- */
|
|
|
- rtb_Add1 = (real_T)look1_iu16lu16n16tu16_binlcase(rtb_uDLookupTable3,
|
|
|
- (&(cmnm_pct_soc[0])), (&(cmnm_R_polar[0])), 12U) * 0.001 * 0.001;
|
|
|
-
|
|
|
- /* Math: '<S21>/Math Function' incorporates:
|
|
|
- * Constant: '<S21>/Constant1'
|
|
|
- * DataTypeConversion: '<S20>/Data Type Conversion4'
|
|
|
- * Gain: '<S20>/Gain5'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table3'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table5'
|
|
|
- * Product: '<S20>/Divide1'
|
|
|
- * Product: '<S21>/Divide1'
|
|
|
- *
|
|
|
- * About '<S21>/Math Function':
|
|
|
- * Operator: exp
|
|
|
- */
|
|
|
- rtb_MathFunction = exp(-0.1 / ((real_T)look1_iu16lu16n16tu16_binlcase
|
|
|
- (rtb_uDLookupTable3, (&(cmnm_pct_soc[0])), (&(cmnm_F_polar[0])), 12U) *
|
|
|
- 0.001 * 1000.0 * rtb_Add1));
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S21>/Matrix Concatenate' incorporates:
|
|
|
- * Constant: '<S21>/Constant3'
|
|
|
- */
|
|
|
- rtb_MatrixConcatenate[2] = 0.0;
|
|
|
- rtb_MatrixConcatenate[3] = rtb_MathFunction;
|
|
|
-
|
|
|
- /* Product: '<S16>/Product' incorporates:
|
|
|
- * Math: '<S16>/Math Function1'
|
|
|
- * SignalConversion generated from: '<S21>/Matrix Concatenate'
|
|
|
- * UnitDelay: '<S12>/P_Delay'
|
|
|
- */
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- tmp[i] = 0.0;
|
|
|
- tmp[i] += SOC_DW.P_Delay_DSTATE[i];
|
|
|
- tmp[i + 2] = 0.0;
|
|
|
- tmp[i + 2] += SOC_DW.P_Delay_DSTATE[i + 2] * rtb_MathFunction;
|
|
|
- }
|
|
|
-
|
|
|
- /* Product: '<S17>/Product1' */
|
|
|
- rtb_TmpSignalConversionAtProd_0 = 0.0;
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- /* Sum: '<S16>/Add' incorporates:
|
|
|
- * Concatenate: '<S21>/Matrix Concatenate'
|
|
|
- * Constant: '<S12>/Constant'
|
|
|
- * Product: '<S16>/Product'
|
|
|
- * UnitDelay: '<S13>/P_Delay'
|
|
|
- */
|
|
|
- tmp_1 = rtb_MatrixConcatenate[i + 2];
|
|
|
- P_Delay_DSTATE_tmp_0 = tmp_1 * tmp[1] + rtb_MatrixConcatenate[i] * tmp[0];
|
|
|
- rtb_P_Delay[i] = P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
-
|
|
|
- /* Product: '<S17>/Product1' incorporates:
|
|
|
- * Constant: '<S12>/Constant'
|
|
|
- * SignalConversion generated from: '<S21>/Math Function1'
|
|
|
- * Sum: '<S16>/Add'
|
|
|
- */
|
|
|
- rtb_Divide_d = (P_Delay_DSTATE_tmp_0 + 0.001) * rtb_Add_l;
|
|
|
-
|
|
|
- /* Sum: '<S16>/Add' incorporates:
|
|
|
- * Concatenate: '<S21>/Matrix Concatenate'
|
|
|
- * Constant: '<S12>/Constant'
|
|
|
- * Product: '<S16>/Product'
|
|
|
- * UnitDelay: '<S13>/P_Delay'
|
|
|
- */
|
|
|
- P_Delay_DSTATE_tmp_0 = tmp_1 * tmp[3] + rtb_MatrixConcatenate[i] * tmp[2];
|
|
|
- rtb_P_Delay[i + 2] = P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
- rtb_Divide_d += P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
-
|
|
|
- /* Product: '<S17>/Product1' incorporates:
|
|
|
- * Product: '<S17>/Product'
|
|
|
- * SignalConversion generated from: '<S19>/Product2'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProd_0 += rtb_TmpSignalConversionAtProduc[i] *
|
|
|
- rtb_Divide_d;
|
|
|
- rtb_Divide[i] = rtb_Divide_d;
|
|
|
- }
|
|
|
-
|
|
|
- /* Product: '<S17>/Divide' incorporates:
|
|
|
- * Constant: '<S12>/Constant1'
|
|
|
- * Product: '<S17>/Product'
|
|
|
- * Product: '<S17>/Product1'
|
|
|
- * Sum: '<S17>/Add'
|
|
|
- */
|
|
|
- rtb_Divide[0] /= rtb_TmpSignalConversionAtProd_0 + 0.5;
|
|
|
-
|
|
|
- /* Product: '<S17>/Divide' incorporates:
|
|
|
- * Constant: '<S12>/Constant1'
|
|
|
- * Product: '<S17>/Product'
|
|
|
- * Product: '<S17>/Product1'
|
|
|
- * Sum: '<S17>/Add'
|
|
|
- */
|
|
|
- k2 = rtb_Divide[1] / (rtb_TmpSignalConversionAtProd_0 + 0.5);
|
|
|
-
|
|
|
- /* Sum: '<S15>/Add' incorporates:
|
|
|
- * Product: '<S15>/Product1'
|
|
|
- * Product: '<S17>/Divide'
|
|
|
- * SignalConversion generated from: '<S21>/Math Function1'
|
|
|
- */
|
|
|
- tmp_1 = 1.0 - rtb_Divide[0] * rtb_Add_l;
|
|
|
- rtb_Add_l = 0.0 - k2 * rtb_Add_l;
|
|
|
- rtb_TmpSignalConversionAtProd_0 = 0.0 - rtb_Divide[0];
|
|
|
-
|
|
|
- /* Product: '<S15>/Product' incorporates:
|
|
|
- * Sum: '<S15>/Add'
|
|
|
- * UnitDelay: '<S12>/P_Delay'
|
|
|
- * UnitDelay: '<S13>/P_Delay'
|
|
|
- */
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- P_Delay_DSTATE_tmp = i << 1;
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp] = 0.0;
|
|
|
- P_Delay_DSTATE_tmp_0 = rtb_P_Delay[P_Delay_DSTATE_tmp];
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp] += P_Delay_DSTATE_tmp_0 * tmp_1;
|
|
|
- rtb_Divide_d = rtb_P_Delay[P_Delay_DSTATE_tmp + 1];
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp] += rtb_Divide_d *
|
|
|
- rtb_TmpSignalConversionAtProd_0;
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp + 1] = 0.0;
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp + 1] += P_Delay_DSTATE_tmp_0 *
|
|
|
- rtb_Add_l;
|
|
|
- SOC_DW.P_Delay_DSTATE[P_Delay_DSTATE_tmp + 1] += rtb_Divide_d * (1.0 - k2);
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Product: '<S15>/Product' */
|
|
|
-
|
|
|
- /* Switch: '<S23>/Switch' incorporates:
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- */
|
|
|
- if (SOC_DW.Frist_DSTATE_h) {
|
|
|
- /* Sum: '<S19>/Add' incorporates:
|
|
|
- * Switch: '<S5>/Switch'
|
|
|
- */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE_e = (real_T)SOC_B.Switch * 0.1;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S23>/Switch' */
|
|
|
-
|
|
|
- /* Product: '<S29>/Divide' incorporates:
|
|
|
- * Gain: '<S30>/Gain'
|
|
|
- * Product: '<S30>/Divide2'
|
|
|
- * Product: '<S5>/Divide'
|
|
|
- */
|
|
|
- rtb_Divide_d = (real_T)SOC_B.Divide * 0.1;
|
|
|
-
|
|
|
- /* Sum: '<S29>/Add1' incorporates:
|
|
|
- * Gain: '<S29>/Gain4'
|
|
|
- * Product: '<S29>/Divide'
|
|
|
- */
|
|
|
- rtb_Add1_h = rtb_Add1_h / rtb_Divide_d * 100.0 + SOC_DW.SOCk_Delay_DSTATE_e;
|
|
|
-
|
|
|
- /* MATLAB Function: '<S30>/MATLAB Function' */
|
|
|
- SOC_MATLABFunction(rtb_Add1_h, &rtb_Add_l);
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S30>/Math Function1' incorporates:
|
|
|
- * Constant: '<S30>/Constant'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProduc[0] = rtb_Add_l;
|
|
|
- rtb_TmpSignalConversionAtProduc[1] = 1.0;
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S30>/Matrix Concatenate' */
|
|
|
- rtb_P_Delay[0] = 1.0;
|
|
|
- rtb_P_Delay[1] = 0.0;
|
|
|
-
|
|
|
- /* DataTypeConversion: '<S29>/Data Type Conversion' incorporates:
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- */
|
|
|
- tmp_1 = fmod(floor(rtb_Add1_h / 0.1), 65536.0);
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = (uint16_T)(tmp_1 < 0.0 ? (int32_T)(uint16_T)
|
|
|
- -(int16_T)(uint16_T)-tmp_1 : (int32_T)(uint16_T)tmp_1);
|
|
|
-
|
|
|
- /* Gain: '<S29>/Gain1' incorporates:
|
|
|
- * DataTypeConversion: '<S29>/Data Type Conversion3'
|
|
|
- * Lookup_n-D: '<S29>/1-D Lookup Table4'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_Gain1_m = (real_T)look1_iu16lu16n16tu16_binlcase
|
|
|
- (rtb_socd_pct_bcuSoc0_Delay, (&(cmnm_pct_soc[0])), (&(cmnm_R_polar[0])), 12U)
|
|
|
- * 0.001 * 0.001;
|
|
|
-
|
|
|
- /* Math: '<S30>/Math Function' incorporates:
|
|
|
- * Constant: '<S30>/Constant1'
|
|
|
- * DataTypeConversion: '<S29>/Data Type Conversion4'
|
|
|
- * Gain: '<S29>/Gain5'
|
|
|
- * Lookup_n-D: '<S29>/1-D Lookup Table5'
|
|
|
- * Product: '<S29>/Divide1'
|
|
|
- * Product: '<S30>/Divide1'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- *
|
|
|
- * About '<S30>/Math Function':
|
|
|
- * Operator: exp
|
|
|
- */
|
|
|
- rtb_Abs = exp(-0.1 / ((real_T)look1_iu16lu16n16tu16_binlcase
|
|
|
- (rtb_socd_pct_bcuSoc0_Delay, (&(cmnm_pct_soc[0])),
|
|
|
- (&(cmnm_F_polar[0])), 12U) * 0.001 * 1000.0 * rtb_Gain1_m));
|
|
|
-
|
|
|
- /* SignalConversion generated from: '<S30>/Matrix Concatenate' incorporates:
|
|
|
- * Constant: '<S30>/Constant3'
|
|
|
- */
|
|
|
- rtb_P_Delay[2] = 0.0;
|
|
|
- rtb_P_Delay[3] = rtb_Abs;
|
|
|
-
|
|
|
- /* Product: '<S25>/Product' incorporates:
|
|
|
- * Math: '<S25>/Math Function1'
|
|
|
- * SignalConversion generated from: '<S30>/Matrix Concatenate'
|
|
|
- * UnitDelay: '<S13>/P_Delay'
|
|
|
- */
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- tmp[i] = 0.0;
|
|
|
- tmp[i] += SOC_DW.P_Delay_DSTATE_m[i];
|
|
|
- tmp[i + 2] = 0.0;
|
|
|
- tmp[i + 2] += SOC_DW.P_Delay_DSTATE_m[i + 2] * rtb_Abs;
|
|
|
- }
|
|
|
-
|
|
|
- /* Product: '<S26>/Product1' */
|
|
|
- rtb_TmpSignalConversionAtProd_0 = 0.0;
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- /* Sum: '<S25>/Add' incorporates:
|
|
|
- * Concatenate: '<S30>/Matrix Concatenate'
|
|
|
- * Constant: '<S13>/Constant'
|
|
|
- * Product: '<S25>/Product'
|
|
|
- */
|
|
|
- tmp_1 = rtb_P_Delay[i + 2];
|
|
|
- P_Delay_DSTATE_tmp_0 = tmp_1 * tmp[1] + rtb_P_Delay[i] * tmp[0];
|
|
|
- rtb_MatrixConcatenate[i] = P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
-
|
|
|
- /* Product: '<S26>/Product1' incorporates:
|
|
|
- * Constant: '<S13>/Constant'
|
|
|
- * SignalConversion generated from: '<S30>/Math Function1'
|
|
|
- * Sum: '<S25>/Add'
|
|
|
- */
|
|
|
- rtb_Add1_h = (P_Delay_DSTATE_tmp_0 + 0.001) * rtb_Add_l;
|
|
|
-
|
|
|
- /* Sum: '<S25>/Add' incorporates:
|
|
|
- * Concatenate: '<S30>/Matrix Concatenate'
|
|
|
- * Constant: '<S13>/Constant'
|
|
|
- * Product: '<S25>/Product'
|
|
|
- */
|
|
|
- P_Delay_DSTATE_tmp_0 = tmp_1 * tmp[3] + rtb_P_Delay[i] * tmp[2];
|
|
|
- rtb_MatrixConcatenate[i + 2] = P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
- rtb_Add1_h += P_Delay_DSTATE_tmp_0 + 0.001;
|
|
|
-
|
|
|
- /* Product: '<S26>/Product1' incorporates:
|
|
|
- * Product: '<S26>/Product'
|
|
|
- * SignalConversion generated from: '<S19>/Product2'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProd_0 += rtb_TmpSignalConversionAtProduc[i] *
|
|
|
- rtb_Add1_h;
|
|
|
- rtb_Product2_i[i] = rtb_Add1_h;
|
|
|
- }
|
|
|
-
|
|
|
- /* Product: '<S26>/Divide' incorporates:
|
|
|
- * Constant: '<S13>/Constant1'
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S26>/Product'
|
|
|
- * Product: '<S26>/Product1'
|
|
|
- * Sum: '<S26>/Add'
|
|
|
- */
|
|
|
- rtb_Product2_i[0] /= rtb_TmpSignalConversionAtProd_0 + 0.5;
|
|
|
- rtb_Add1_h = rtb_Product2_i[1] / (rtb_TmpSignalConversionAtProd_0 + 0.5);
|
|
|
-
|
|
|
- /* Sum: '<S24>/Add' incorporates:
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S24>/Product1'
|
|
|
- * SignalConversion generated from: '<S30>/Math Function1'
|
|
|
- */
|
|
|
- tmp[0] = 1.0 - rtb_Product2_i[0] * rtb_Add_l;
|
|
|
- tmp[1] = 0.0 - rtb_Add1_h * rtb_Add_l;
|
|
|
- tmp[2] = 0.0 - rtb_Product2_i[0];
|
|
|
- tmp[3] = 1.0 - rtb_Add1_h;
|
|
|
-
|
|
|
- /* Switch: '<S23>/Switch1' incorporates:
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- */
|
|
|
- if (SOC_DW.Frist_DSTATE_h) {
|
|
|
- /* SignalConversion generated from: '<S28>/Product1' incorporates:
|
|
|
- * Constant: '<S23>/Up'
|
|
|
- */
|
|
|
- SOC_DW.Up_Delay_DSTATE = 0.0;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S23>/Switch1' */
|
|
|
-
|
|
|
- /* Product: '<S28>/Product2' incorporates:
|
|
|
- * Constant: '<S30>/Constant4'
|
|
|
- * Constant: '<S30>/Constant5'
|
|
|
- * Gain: '<S30>/Gain'
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S30>/Divide2'
|
|
|
- * Product: '<S30>/Product'
|
|
|
- * Sum: '<S30>/Add'
|
|
|
- */
|
|
|
- tmp_1 = 0.1 / rtb_Divide_d * 0.027777777777777776 * rtb_Add1_tmp_tmp;
|
|
|
- tmp_0[0] = tmp_1;
|
|
|
- tmp_0[1] = (1.0 - rtb_Abs) * rtb_Gain1_m * rtb_Add1_tmp_tmp;
|
|
|
- for (i = 0; i < 2; i++) {
|
|
|
- /* Product: '<S24>/Product' incorporates:
|
|
|
- * Sum: '<S25>/Add'
|
|
|
- * UnitDelay: '<S13>/P_Delay'
|
|
|
- */
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i] = 0.0;
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i] += tmp[i] * rtb_MatrixConcatenate[0];
|
|
|
- rtb_Add_l = tmp[i + 2];
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i] += rtb_Add_l * rtb_MatrixConcatenate[1];
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i + 2] = 0.0;
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i + 2] += tmp[i] * rtb_MatrixConcatenate[2];
|
|
|
- SOC_DW.P_Delay_DSTATE_m[i + 2] += rtb_Add_l * rtb_MatrixConcatenate[3];
|
|
|
-
|
|
|
- /* Sum: '<S28>/Add1' incorporates:
|
|
|
- * Concatenate: '<S30>/Matrix Concatenate'
|
|
|
- * Product: '<S28>/Product1'
|
|
|
- * SignalConversion generated from: '<S28>/Product1'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProduc[i] = (rtb_P_Delay[i + 2] *
|
|
|
- SOC_DW.Up_Delay_DSTATE + rtb_P_Delay[i] * SOC_DW.SOCk_Delay_DSTATE_e) +
|
|
|
- tmp_0[i];
|
|
|
- }
|
|
|
-
|
|
|
- /* Lookup_n-D: '<S29>/1-D Lookup Table2' incorporates:
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_Merge = look1_iu16lu16n16tu16_binlcase(rtb_socd_pct_bcuSoc0_Delay,
|
|
|
- (&(cmnm_pct_soc[0])), (&(cmnm_V_ocv[0])), 12U);
|
|
|
-
|
|
|
- /* Lookup_n-D: '<S29>/1-D Lookup Table3' incorporates:
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = look1_iu16lu16n16tu16_binlcase
|
|
|
- (rtb_socd_pct_bcuSoc0_Delay, (&(cmnm_pct_soc[0])), (&(cmnm_R_ohm[0])), 12U);
|
|
|
-
|
|
|
- /* Sum: '<S27>/Add1' incorporates:
|
|
|
- * DataTypeConversion: '<S29>/Data Type Conversion1'
|
|
|
- * DataTypeConversion: '<S29>/Data Type Conversion2'
|
|
|
- * Gain: '<S29>/Gain2'
|
|
|
- * Inport: '<Root>/sfmd_V_cellUMax'
|
|
|
- * Product: '<S28>/Product'
|
|
|
- * Sum: '<S13>/Add'
|
|
|
- * Sum: '<S28>/Add'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcuSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_Add_l = (real_T)sfmd_V_cellUMax * 0.001 - (((real_T)
|
|
|
- rtb_socd_pct_bcuSoc0_Delay * 0.001 * 0.001 * rtb_Add1_tmp_tmp + (real_T)
|
|
|
- rtb_Merge * 0.001) + rtb_TmpSignalConversionAtProduc[1]);
|
|
|
-
|
|
|
- /* Sum: '<S27>/Add' incorporates:
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S27>/Product'
|
|
|
- * Sum: '<S27>/Add1'
|
|
|
- */
|
|
|
- rtb_Product2_i[0] = rtb_Product2_i[0] * rtb_Add_l +
|
|
|
- rtb_TmpSignalConversionAtProduc[0];
|
|
|
-
|
|
|
- /* Switch: '<S14>/Switch1' incorporates:
|
|
|
- * Constant: '<S14>/Up'
|
|
|
- * UnitDelay: '<S14>/Frist'
|
|
|
- */
|
|
|
- if (SOC_DW.Frist_DSTATE) {
|
|
|
- SOC_DW.Up_Delay_DSTATE_h = 0.0;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S14>/Switch1' */
|
|
|
-
|
|
|
- /* DataTypeConversion: '<S20>/Data Type Conversion1' incorporates:
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table2'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table3'
|
|
|
- */
|
|
|
- OCV = (real_T)look1_iu16lu16n16tu16_binlcase(rtb_uDLookupTable3,
|
|
|
- (&(cmnm_pct_soc[0])), (&(cmnm_V_ocv[0])), 12U) * 0.001;
|
|
|
-
|
|
|
- /* Lookup_n-D: '<S20>/1-D Lookup Table3' */
|
|
|
- rtb_uDLookupTable3 = look1_iu16lu16n16tu16_binlcase(rtb_uDLookupTable3,
|
|
|
- (&(cmnm_pct_soc[0])), (&(cmnm_R_ohm[0])), 12U);
|
|
|
-
|
|
|
- /* Sum: '<S19>/Add1' incorporates:
|
|
|
- * Constant: '<S21>/Constant5'
|
|
|
- * Product: '<S19>/Product1'
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S21>/Product'
|
|
|
- * SignalConversion generated from: '<S21>/Matrix Concatenate'
|
|
|
- * Sum: '<S21>/Add'
|
|
|
- */
|
|
|
- rtb_Add1 = (1.0 - rtb_MathFunction) * rtb_Add1 * rtb_Add1_tmp_tmp +
|
|
|
- rtb_MathFunction * SOC_DW.Up_Delay_DSTATE_h;
|
|
|
-
|
|
|
- /* Sum: '<S18>/Add1' incorporates:
|
|
|
- * DataTypeConversion: '<S20>/Data Type Conversion2'
|
|
|
- * Gain: '<S20>/Gain2'
|
|
|
- * Inport: '<Root>/sfmd_V_cellUMin'
|
|
|
- * Lookup_n-D: '<S20>/1-D Lookup Table3'
|
|
|
- * Product: '<S19>/Product'
|
|
|
- * Sum: '<S12>/Add'
|
|
|
- * Sum: '<S19>/Add'
|
|
|
- * Sum: '<S19>/Add1'
|
|
|
- */
|
|
|
- deltaU = (real_T)sfmd_V_cellUMin * 0.001 - (((real_T)rtb_uDLookupTable3 *
|
|
|
- 0.001 * 0.001 * rtb_Add1_tmp_tmp + OCV) + rtb_Add1);
|
|
|
-
|
|
|
- /* Sum: '<S18>/Add' incorporates:
|
|
|
- * Product: '<S17>/Divide'
|
|
|
- * Product: '<S18>/Product'
|
|
|
- * SignalConversion generated from: '<S19>/Product1'
|
|
|
- * Sum: '<S18>/Add1'
|
|
|
- * Sum: '<S19>/Add1'
|
|
|
- */
|
|
|
- rtb_TmpSignalConversionAtProduc[0] = (tmp_1 + SOC_DW.SOCk_Delay_DSTATE) +
|
|
|
- rtb_Divide[0] * deltaU;
|
|
|
-
|
|
|
- /* Sum: '<S19>/Add' incorporates:
|
|
|
- * Saturate: '<S12>/Saturation'
|
|
|
- * Saturate: '<S13>/Saturation'
|
|
|
- */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE_e = (real_T)socc_pct_battSocLow * 0.1;
|
|
|
-
|
|
|
- /* Saturate: '<S12>/Saturation' incorporates:
|
|
|
- * Saturate: '<S13>/Saturation'
|
|
|
- */
|
|
|
- rtb_Add1_tmp_tmp = (real_T)socc_pct_battSocUp * 0.1;
|
|
|
- if (rtb_TmpSignalConversionAtProduc[0] > rtb_Add1_tmp_tmp) {
|
|
|
- /* Switch: '<S14>/Switch' */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE = rtb_Add1_tmp_tmp;
|
|
|
- } else if (rtb_TmpSignalConversionAtProduc[0] < SOC_DW.SOCk_Delay_DSTATE_e) {
|
|
|
- /* Switch: '<S14>/Switch' */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE = SOC_DW.SOCk_Delay_DSTATE_e;
|
|
|
- } else {
|
|
|
- /* Switch: '<S14>/Switch' */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE = rtb_TmpSignalConversionAtProduc[0];
|
|
|
- }
|
|
|
-
|
|
|
- /* DataTypeConversion: '<S3>/Data Type Conversion' incorporates:
|
|
|
- * UnitDelay: '<S12>/SOCk_Delay'
|
|
|
- */
|
|
|
- rtb_MathFunction = SOC_DW.SOCk_Delay_DSTATE / 0.1;
|
|
|
- tmp_1 = fabs(rtb_MathFunction);
|
|
|
- if (tmp_1 < 4.503599627370496E+15) {
|
|
|
- if (tmp_1 >= 0.5) {
|
|
|
- rtb_MathFunction = floor(rtb_MathFunction + 0.5);
|
|
|
- } else {
|
|
|
- rtb_MathFunction = 0.0;
|
|
|
+ //printf("1---- battSocEi:%d,bcuSocEi:%d,battSocEE:%d,bcuSocEE:%d\n",socd_pct_battSocEi,socd_pct_bcuSocEi,socn_pct_battSocEE,socn_pct_bcuSocEE);
|
|
|
+ //======================================================================
|
|
|
+ ////////////////////////EKFSOC//////////////////////////////////////////
|
|
|
+ //======================================================================
|
|
|
+ battcurr = (real_T)sfmd_I_curr * 0.1;
|
|
|
+ Q = (real_T) socn_Q_cap * 0.1;
|
|
|
+
|
|
|
+ //-------------------------EKFmin---------------------------------------
|
|
|
+ if (FirstRun_SOC)
|
|
|
+ {
|
|
|
+ soc_Min_Delay = (real_T)socn_pct_battSocEE * 0.1;
|
|
|
+ Up_Min_Delay = 0;
|
|
|
+ P_Min_Delay[0]=1000;
|
|
|
+ P_Min_Delay[1]=0;
|
|
|
+ P_Min_Delay[2]=0;
|
|
|
+ P_Min_Delay[3]=1000;
|
|
|
}
|
|
|
- }
|
|
|
-
|
|
|
- tmp_1 = fmod(rtb_MathFunction, 65536.0);
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(tmp_1 < 0.0 ? (int32_T)(uint16_T)-(int16_T)
|
|
|
- (uint16_T)-tmp_1 : (int32_T)(uint16_T)tmp_1);
|
|
|
-
|
|
|
- /* End of DataTypeConversion: '<S3>/Data Type Conversion' */
|
|
|
-
|
|
|
- /* Saturate: '<S13>/Saturation' */
|
|
|
- if (rtb_Product2_i[0] > rtb_Add1_tmp_tmp) {
|
|
|
- /* Sum: '<S19>/Add' */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE_e = rtb_Add1_tmp_tmp;
|
|
|
- } else {
|
|
|
- if (rtb_Product2_i[0] >= SOC_DW.SOCk_Delay_DSTATE_e) {
|
|
|
- /* Sum: '<S19>/Add' */
|
|
|
- SOC_DW.SOCk_Delay_DSTATE_e = rtb_Product2_i[0];
|
|
|
+ //参数查表
|
|
|
+ ocv = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Min_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_V_ocv[0])), 12U) * 0.001;
|
|
|
+ Ro = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Min_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_R_ohm[0])), 12U) * 0.001 * 0.001;
|
|
|
+ Rp = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Min_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_R_polar[0])), 12U) * 0.001 * 0.001;
|
|
|
+ C = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Min_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_F_polar[0])), 12U) * 0.001 * 1000;
|
|
|
+ A[0] = 1;
|
|
|
+ A[1] = 0;
|
|
|
+ A[2] = 0;
|
|
|
+ A[3] = exp(-0.1/( Rp * C));
|
|
|
+
|
|
|
+ B[0] = 0.1/Q/3600 * 100;
|
|
|
+ B[1] = Rp * (1- exp(-0.1/(Rp * C)));
|
|
|
+
|
|
|
+ docvmath(soc_Min_Delay ,&docv);
|
|
|
+ H[0] = docv;
|
|
|
+ H[1] = 1;
|
|
|
+
|
|
|
+ //先验
|
|
|
+ soc1 = soc_Min_Delay * A[0] + B[0] * battcurr;
|
|
|
+ Up1 = Up_Min_Delay * A[3] + B[1] * battcurr;
|
|
|
+ UL= ocv + battcurr * Ro + Up1;
|
|
|
+ P1[0] = P_Min_Delay[0] + 0.002;
|
|
|
+ P1[1] = P_Min_Delay[1] * A[3] +0.002;
|
|
|
+ P1[2] = P_Min_Delay[2] * A[3] +0.002;
|
|
|
+ P1[3] = P_Min_Delay[3] * A[3] * A[3] +0.002;
|
|
|
+
|
|
|
+ //增益
|
|
|
+ K[0] = (P1[0] * H[0] + P1[2])/( H[0] * P1[0] * H[0] + P1[1] * H[0] + H[0] * P1[2] + P1[3] +0.5 );
|
|
|
+ K[1] = (P1[1] * H[0] + P1[3])/( H[0] * P1[0] * H[0] + P1[1] * H[0] + H[0] * P1[2] + P1[3] +0.5 );
|
|
|
+
|
|
|
+ //后验
|
|
|
+ deltU = (real_T)sfmd_V_cellUMin * 0.001 - UL;
|
|
|
+ soc_Min_Delay = soc1 + K[0] * deltU;
|
|
|
+ if (soc_Min_Delay < (real_T)socc_pct_battSocLow * 0.1)
|
|
|
+ {
|
|
|
+ soc_Min_Delay= (real_T)socc_pct_battSocLow * 0.1;
|
|
|
}
|
|
|
- }
|
|
|
-
|
|
|
- /* DataTypeConversion: '<S3>/Data Type Conversion1' incorporates:
|
|
|
- * UnitDelay: '<S13>/SOCk_Delay'
|
|
|
- */
|
|
|
- rtb_MathFunction = SOC_DW.SOCk_Delay_DSTATE_e / 0.1;
|
|
|
- tmp_1 = fabs(rtb_MathFunction);
|
|
|
- if (tmp_1 < 4.503599627370496E+15) {
|
|
|
- if (tmp_1 >= 0.5) {
|
|
|
- rtb_MathFunction = floor(rtb_MathFunction + 0.5);
|
|
|
- } else {
|
|
|
- rtb_MathFunction = 0.0;
|
|
|
+ if (soc_Min_Delay > (real_T)socc_pct_battSocUp * 0.1)
|
|
|
+ {
|
|
|
+ soc_Min_Delay= (real_T)socc_pct_battSocUp * 0.1;
|
|
|
}
|
|
|
- }
|
|
|
-
|
|
|
- tmp_1 = fmod(rtb_MathFunction, 65536.0);
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = (uint16_T)(tmp_1 < 0.0 ? (int32_T)(uint16_T)
|
|
|
- -(int16_T)(uint16_T)-tmp_1 : (int32_T)(uint16_T)tmp_1);
|
|
|
-
|
|
|
- /* End of DataTypeConversion: '<S3>/Data Type Conversion1' */
|
|
|
-
|
|
|
- /* Switch: '<S11>/Switch' incorporates:
|
|
|
- * Constant: '<S11>/Constant6'
|
|
|
- * DataTypeConversion: '<S3>/Data Type Conversion'
|
|
|
- * DataTypeConversion: '<S3>/Data Type Conversion1'
|
|
|
- * RelationalOperator: '<S11>/Relational Operator'
|
|
|
- * RelationalOperator: '<S11>/Relational Operator1'
|
|
|
- * Switch: '<S11>/Switch1'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- */
|
|
|
- if (rtb_socd_pct_bcuSoc0_Delay >= 800) {
|
|
|
- rtb_Merge = 100U;
|
|
|
- } else if (200 >= rtb_uDLookupTable3) {
|
|
|
- /* UnitDelay: '<S32>/socd_flg_EEsave_Delay' incorporates:
|
|
|
- * Constant: '<S11>/Constant8'
|
|
|
- * Switch: '<S11>/Switch1'
|
|
|
- */
|
|
|
- rtb_Merge = 0U;
|
|
|
- } else {
|
|
|
- /* Product: '<S11>/Divide' incorporates:
|
|
|
- * Constant: '<S11>/Constant1'
|
|
|
- * Constant: '<S11>/Constant2'
|
|
|
- * Constant: '<S11>/Constant3'
|
|
|
- * DataTypeConversion: '<S3>/Data Type Conversion'
|
|
|
- * Sum: '<S11>/Add2'
|
|
|
- * Sum: '<S11>/Add3'
|
|
|
- * Sum: '<S11>/Add4'
|
|
|
- * Sum: '<S11>/Add5'
|
|
|
- * Switch: '<S11>/Switch1'
|
|
|
- */
|
|
|
- i = (uint16_T)((uint16_T)(800 - (uint16_T)(rtb_socd_pct_bcuSoc0_Delay -
|
|
|
- rtb_uDLookupTable3)) - 200);
|
|
|
- rtb_Merge = (uint16_T)(((uint16_T)((uint32_T)i == 0U ? MAX_uint32_T :
|
|
|
- ((uint32_T)(rtb_uDLookupTable3 - 200) << 6) / i) * 25U) >> 4);
|
|
|
-
|
|
|
- /* MinMax: '<S11>/Max' incorporates:
|
|
|
- * Product: '<S11>/Divide'
|
|
|
- * Switch: '<S11>/Switch1'
|
|
|
- */
|
|
|
- if (rtb_Merge <= 0) {
|
|
|
- /* UnitDelay: '<S32>/socd_flg_EEsave_Delay' incorporates:
|
|
|
- * Constant: '<S11>/Constant4'
|
|
|
- */
|
|
|
- rtb_Merge = 0U;
|
|
|
+
|
|
|
+ Up_Min_Delay = Up1 + K[1] * deltU;
|
|
|
+ //Up_Min_Delay = (Up_Min_Delay > 0 ? Up_Min_Delay : 0);
|
|
|
+
|
|
|
+ //P更新
|
|
|
+ P_Min_Delay[0] = (1 - K[0] * H[0]) * P1[0] -K[0]* P1[1];
|
|
|
+ P_Min_Delay[1] = -K[1] * H[0] * P1[0] + P1[1] * (1 - K[1]);
|
|
|
+ P_Min_Delay[2] = (1 - K[0] * H[0]) * P1[2] -K[0]* P1[3];
|
|
|
+ P_Min_Delay[3] = -K[1] * H[0] * P1[2] + P1[3] * (1 - K[1]);
|
|
|
+
|
|
|
+ //输出
|
|
|
+ EKFSOCMin = (uint16_T) (soc_Min_Delay * 10);
|
|
|
+ socn_flg_ekfInvalidMin= (deltU > 0.005)||(deltU < -0.005);
|
|
|
+ //printf("2----socmin:%f,Up:%f,U1:%d,sfmd_V_cellUMin:%d,deltU:%f,flg:%d,soc1:%f,K[0]:%f,K[1]:%f\n",soc_Min_Delay,Up_Min_Delay,ihv_V_cellU[0],sfmd_V_cellUMin,deltU,socn_flg_ekfInvalidMin,soc1,K[0],K[1]);
|
|
|
+ //------------------------EKFSOCmax-----------------------------------
|
|
|
+
|
|
|
+ if (FirstRun_SOC)
|
|
|
+ {
|
|
|
+ soc_Max_Delay = (real_T)socn_pct_battSocEE * 0.1;
|
|
|
+ Up_Max_Delay = 0;
|
|
|
+ P_Max_Delay[0]=1000;
|
|
|
+ P_Max_Delay[1]=0;
|
|
|
+ P_Max_Delay[2]=0;
|
|
|
+ P_Max_Delay[3]=1000;
|
|
|
}
|
|
|
-
|
|
|
- /* End of MinMax: '<S11>/Max' */
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S11>/Switch' */
|
|
|
-
|
|
|
- /* Sum: '<S11>/Add' incorporates:
|
|
|
- * Constant: '<S11>/Constant'
|
|
|
- * DataTypeConversion: '<S3>/Data Type Conversion'
|
|
|
- * DataTypeConversion: '<S3>/Data Type Conversion1'
|
|
|
- * Product: '<S11>/Product'
|
|
|
- * Product: '<S11>/Product1'
|
|
|
- * Sum: '<S11>/Add1'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- */
|
|
|
- tmp_2 = mul_u32_hiSR_near((uint32_T)(uint16_T)(100 - rtb_Merge) *
|
|
|
- rtb_uDLookupTable3, 2748779069U, 1U) + mul_u32_hiSR_near((uint32_T)
|
|
|
- rtb_socd_pct_bcuSoc0_Delay * rtb_Merge, 2748779069U, 1U);
|
|
|
-
|
|
|
- /* Sum: '<S11>/Add' */
|
|
|
- socd_pct_ekfSoc = (uint16_T)(((tmp_2 & 16U) != 0U) + (tmp_2 >> 5));
|
|
|
-
|
|
|
- /* Sum: '<S4>/Add' incorporates:
|
|
|
- * Inport: '<Root>/sfmd_I_curr'
|
|
|
- * UnitDelay: '<S4>/ '
|
|
|
- */
|
|
|
- SOC_DW._DSTATE += sfmd_I_curr;
|
|
|
-
|
|
|
- /* Sum: '<S4>/Add1' incorporates:
|
|
|
- * Constant: '<S4>/Constant1'
|
|
|
- * Product: '<S4>/Divide'
|
|
|
- * Product: '<S4>/Divide1'
|
|
|
- * Product: '<S4>/Divide2'
|
|
|
- * Product: '<S5>/Divide'
|
|
|
- * Sum: '<S4>/Add'
|
|
|
- * Switch: '<S5>/Switch'
|
|
|
- * UnitDelay: '<S4>/ '
|
|
|
- */
|
|
|
- rtb_Add1_a = (int16_T)((int16_T)(((((int16_T)((div_repeat_s16s32_floor
|
|
|
- (div_nde_s32_floor(SOC_DW._DSTATE, 36000), SOC_B.Divide, 9U) * 125) >> 6) *
|
|
|
- 25) >> 5) * 5243) >> 12) + SOC_B.Switch);
|
|
|
-
|
|
|
- /* Outputs for Atomic SubSystem: '<S7>/Time++' */
|
|
|
- /* Sum: '<S49>/Add' incorporates:
|
|
|
- * Constant: '<S49>/Constant'
|
|
|
- * UnitDelay: '<S49>/Time_reset'
|
|
|
- */
|
|
|
- SOC_DW.Time_reset_DSTATE++;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S7>/Time++' */
|
|
|
-
|
|
|
- /* If: '<S7>/If' incorporates:
|
|
|
- * Inport: '<Root>/ihd_st_workStat'
|
|
|
- * Inport: '<S48>/socn_pct_socekf'
|
|
|
- * Inport: '<S56>/in'
|
|
|
- * Inport: '<S60>/in'
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Sum: '<S11>/Add'
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- * UnitDelay: '<S49>/Time_reset'
|
|
|
- */
|
|
|
- rtPrevAction = SOC_DW.If_ActiveSubsystem;
|
|
|
- if ((ihd_st_workStat == 2) && (SOC_DW.Time_reset_DSTATE >= 20)) {
|
|
|
- SOC_DW.If_ActiveSubsystem = 0;
|
|
|
- } else if ((ihd_st_workStat != 2) && (SOC_DW.Time_reset_DSTATE >= 20)) {
|
|
|
- SOC_DW.If_ActiveSubsystem = 1;
|
|
|
- } else {
|
|
|
- SOC_DW.If_ActiveSubsystem = 2;
|
|
|
- }
|
|
|
-
|
|
|
- switch (SOC_DW.If_ActiveSubsystem) {
|
|
|
- case 0:
|
|
|
- if (SOC_DW.If_ActiveSubsystem != rtPrevAction) {
|
|
|
- /* InitializeConditions for IfAction SubSystem: '<S7>/chrgCCV' incorporates:
|
|
|
- * ActionPort: '<S50>/Action Port'
|
|
|
- */
|
|
|
- /* InitializeConditions for If: '<S7>/If' incorporates:
|
|
|
- * UnitDelay: '<S50>/fulFLg_reset'
|
|
|
- * UnitDelay: '<S50>/overFlg_reset'
|
|
|
- * UnitDelay: '<S57>/socn_pct_estsoc_Delay'
|
|
|
- * UnitDelay: '<S58>/Time_Delay'
|
|
|
- * UnitDelay: '<S59>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE_g = 1U;
|
|
|
- SOC_DW.overFlg_reset_DSTATE = false;
|
|
|
- SOC_DW.socn_pct_estsoc_Delay_DSTATE = 10U;
|
|
|
- SOC_DW.Time_Delay_DSTATE_f = 1U;
|
|
|
- SOC_DW.fulFLg_reset_DSTATE = false;
|
|
|
-
|
|
|
- /* End of InitializeConditions for SubSystem: '<S7>/chrgCCV' */
|
|
|
+ // 参数查表
|
|
|
+ ocv = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Max_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_V_ocv[0])), 12U) * 0.001;
|
|
|
+ Ro = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Max_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_R_ohm[0])), 12U) * 0.001 * 0.001;
|
|
|
+ Rp = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Max_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_R_polar[0])), 12U) * 0.001 * 0.001;
|
|
|
+ C = (real_T)look1_iu16lu16n16tu16_binlcase((uint16_T)(soc_Max_Delay * 10),(&(cmnm_pct_soc[0])), (&(cmnm_F_polar[0])), 12U) * 0.001 * 1000;
|
|
|
+ A[0] = 1;
|
|
|
+ A[1] = 0;
|
|
|
+ A[2] = 0;
|
|
|
+ A[3] = exp(-0.1/( Rp * C));
|
|
|
+
|
|
|
+ B[0] = 0.1/Q/3600 * 100;
|
|
|
+ B[1] = Rp * (1- exp(-0.1/(Rp * C)));
|
|
|
+
|
|
|
+ docvmath(soc_Max_Delay ,&docv);
|
|
|
+ H[0] = docv;
|
|
|
+ H[1] = 1;
|
|
|
+
|
|
|
+ //先验
|
|
|
+ soc1 = soc_Max_Delay * A[0] + B[0] * battcurr;
|
|
|
+ Up1 = Up_Max_Delay * A[3] + B[1] * battcurr;
|
|
|
+ UL= ocv + battcurr * Ro + Up1;
|
|
|
+ P1[0] = P_Max_Delay[0] + 0.002;
|
|
|
+ P1[1] = P_Max_Delay[1] * A[3] +0.002;
|
|
|
+ P1[2] = P_Max_Delay[2] * A[3] +0.002;
|
|
|
+ P1[3] = P_Max_Delay[3] * A[3] * A[3] +0.002;
|
|
|
+
|
|
|
+ //增益
|
|
|
+ K[0] = (P1[0] * H[0] + P1[2])/( H[0] * P1[0] * H[0] + P1[1] * H[0] + H[0] * P1[2] + P1[3] +0.5 );
|
|
|
+ K[1] = (P1[1] * H[0] + P1[3])/( H[0] * P1[0] * H[0] + P1[1] * H[0] + H[0] * P1[2] + P1[3] +0.5 );
|
|
|
+
|
|
|
+ //后验
|
|
|
+ deltU = (real_T)sfmd_V_cellUMax * 0.001 - UL;
|
|
|
+ soc_Max_Delay = soc1 + K[0] * deltU;
|
|
|
+ if (soc_Max_Delay <(real_T)socc_pct_battSocLow * 0.1)
|
|
|
+ {
|
|
|
+ soc_Max_Delay= (real_T)socc_pct_battSocLow * 0.1;
|
|
|
}
|
|
|
-
|
|
|
- /* Outputs for IfAction SubSystem: '<S7>/chrgCCV' incorporates:
|
|
|
- * ActionPort: '<S50>/Action Port'
|
|
|
- */
|
|
|
- /* Saturate: '<S59>/Saturation' incorporates:
|
|
|
- * Constant: '<S59>/Constant'
|
|
|
- * Sum: '<S59>/Add'
|
|
|
- * UnitDelay: '<S59>/Time_Delay'
|
|
|
- */
|
|
|
- if ((uint16_T)(SOC_DW.Time_Delay_DSTATE_g + 1U) < 60000) {
|
|
|
- rtb_Merge = (uint16_T)(SOC_DW.Time_Delay_DSTATE_g + 1U);
|
|
|
- } else {
|
|
|
- rtb_Merge = 60000U;
|
|
|
+ if (soc_Max_Delay > (real_T)socc_pct_battSocUp * 0.1)
|
|
|
+ {
|
|
|
+ soc_Max_Delay= (real_T)socc_pct_battSocUp * 0.1;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Saturate: '<S59>/Saturation' */
|
|
|
-
|
|
|
- /* Product: '<S59>/Product' incorporates:
|
|
|
- * Inport: '<Root>/sfmd_I_curr'
|
|
|
- * Inport: '<Root>/sfmd_V_cellUMax'
|
|
|
- * Lookup_n-D: '<S50>/1-D Lookup Table'
|
|
|
- * RelationalOperator: '<S50>/Relational Operator'
|
|
|
- * UnitDelay: '<S59>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE_g = (uint16_T)(sfmd_V_cellUMax >=
|
|
|
- look1_is16lu16n16tu16_binlcase(sfmd_I_curr, (&(socm_I_chrgCor[0])),
|
|
|
- (&(socm_V_chrgCor[0])), 3U) ? (int32_T)rtb_Merge : 0);
|
|
|
-
|
|
|
- /* Logic: '<S50>/Logical Operator1' incorporates:
|
|
|
- * Constant: '<S59>/para'
|
|
|
- * RelationalOperator: '<S59>/Relational Operator1'
|
|
|
- * UnitDelay: '<S50>/overFlg_reset'
|
|
|
- */
|
|
|
- rtb_LogicalOperator1_j = ((rtb_Merge > 20) || SOC_DW.overFlg_reset_DSTATE);
|
|
|
-
|
|
|
- /* Outputs for Triggered SubSystem: '<S50>/Subsystem2' incorporates:
|
|
|
- * TriggerPort: '<S56>/Trigger'
|
|
|
- */
|
|
|
- if (rtb_LogicalOperator1_j && (SOC_PrevZCX.Subsystem2_Trig_ZCE_k != 1)) {
|
|
|
- SOC_B.in_c = rtb_Add1_a;
|
|
|
+ Up_Max_Delay = Up1 + K[1] * deltU;
|
|
|
+ //Up_Max_Delay = (Up_Max_Delay > 0 ? Up_Max_Delay : 0);
|
|
|
+
|
|
|
+ //P更新
|
|
|
+ P_Max_Delay[0] = (1 - K[0] * H[0]) * P1[0] -K[0]* P1[1];
|
|
|
+ P_Max_Delay[1] = -K[1] * H[0] * P1[0] + P1[1] * (1 - K[1]);
|
|
|
+ P_Max_Delay[2] = (1 - K[0] * H[0]) * P1[2] -K[0]* P1[3];
|
|
|
+ P_Max_Delay[3] = -K[1] * H[0] * P1[2] + P1[3] * (1 - K[1]);
|
|
|
+ //输出
|
|
|
+ EKFSOCMax = (uint16_T) (soc_Max_Delay * 10);
|
|
|
+ socn_flg_ekfInvalidMax= (deltU > 0.005)||(deltU < -0.005);
|
|
|
+ //printf("3----socmax:%f,Up:%f,sfmd_V_cellUMax:%d,deltU:%f,flg:%d\n",soc_Max_Delay,Up_Max_Delay,sfmd_V_cellUMax,deltU,socn_flg_ekfInvalidMax);
|
|
|
+ //-----------------------EKFSOC----------------------------------------
|
|
|
+ socn_flg_ekfInvalid = socn_flg_ekfInvalidMax || socn_flg_ekfInvalidMin;
|
|
|
+ if(EKFSOCMax > 800)
|
|
|
+ {
|
|
|
+ factor=100;
|
|
|
}
|
|
|
-
|
|
|
- SOC_PrevZCX.Subsystem2_Trig_ZCE_k = rtb_LogicalOperator1_j;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S50>/Subsystem2' */
|
|
|
-
|
|
|
- /* Switch: '<S50>/Switch' incorporates:
|
|
|
- * Constant: '<S50>/Constant'
|
|
|
- * Inport: '<S56>/in'
|
|
|
- * Saturate: '<S50>/Saturation'
|
|
|
- * Sum: '<S11>/Add'
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- * Sum: '<S50>/Add1'
|
|
|
- * Sum: '<S50>/Add2'
|
|
|
- */
|
|
|
- if (rtb_LogicalOperator1_j) {
|
|
|
- rtb_Merge = (uint16_T)((int16_T)(rtb_Add1_a - SOC_B.in_c) + 950);
|
|
|
- } else if (socd_pct_ekfSoc < 950) {
|
|
|
- /* Saturate: '<S50>/Saturation' incorporates:
|
|
|
- * Sum: '<S11>/Add'
|
|
|
- */
|
|
|
- rtb_Merge = socd_pct_ekfSoc;
|
|
|
- } else {
|
|
|
- rtb_Merge = 950U;
|
|
|
+ else if(EKFSOCMin<200)
|
|
|
+ {
|
|
|
+ factor=0;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S50>/Switch' */
|
|
|
-
|
|
|
- /* Sum: '<S57>/Add4' incorporates:
|
|
|
- * Saturate: '<S57>/Saturation'
|
|
|
- * UnitDelay: '<S57>/socn_pct_estsoc_Delay'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(rtb_Merge - SOC_DW.socn_pct_estsoc_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Saturate: '<S57>/Saturation' */
|
|
|
- if (rtb_Saturation_k > 1000) {
|
|
|
- rtb_Saturation_k = 1000;
|
|
|
- } else {
|
|
|
- if (rtb_Saturation_k < 0) {
|
|
|
- rtb_Saturation_k = 0;
|
|
|
- }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ factor=(uint16_T)(((uint16_T)(( (uint32_T) (EKFSOCMin - 200) << 6) / (800 - (EKFSOCMax-EKFSOCMin) - 200)) * 25U) >> 4);
|
|
|
}
|
|
|
-
|
|
|
- /* End of Saturate: '<S57>/Saturation' */
|
|
|
-
|
|
|
- /* Sum: '<S57>/Add3' incorporates:
|
|
|
- * Saturate: '<S57>/Saturation'
|
|
|
- * UnitDelay: '<S57>/socn_pct_estsoc_Delay'
|
|
|
- */
|
|
|
- SOC_DW.socn_pct_estsoc_Delay_DSTATE += rtb_Saturation_k;
|
|
|
-
|
|
|
- /* Saturate: '<S58>/Saturation' incorporates:
|
|
|
- * Constant: '<S58>/Constant'
|
|
|
- * Sum: '<S58>/Add'
|
|
|
- * UnitDelay: '<S58>/Time_Delay'
|
|
|
- */
|
|
|
- if ((uint16_T)(SOC_DW.Time_Delay_DSTATE_f + 1U) < 60000) {
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(SOC_DW.Time_Delay_DSTATE_f + 1U);
|
|
|
- } else {
|
|
|
- rtb_uDLookupTable3 = 60000U;
|
|
|
+ socd_pct_ekfSoc = (uint16_T)( ( (1 - (real_T)(factor * 0.01)) * (real_T) (EKFSOCMin * 0.1) + (real_T)(factor * 0.01) * (real_T)( EKFSOCMax * 0.1) ) * 10);
|
|
|
+ if (socd_pct_ekfSoc < socc_pct_battSocLow)
|
|
|
+ {
|
|
|
+ socd_pct_ekfSoc= socc_pct_battSocLow ;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Saturate: '<S58>/Saturation' */
|
|
|
-
|
|
|
- /* UnitDelay: '<S50>/fulFLg_reset' incorporates:
|
|
|
- * UnitDelay: '<S50>/overFlg_reset'
|
|
|
- */
|
|
|
- SOC_DW.overFlg_reset_DSTATE = SOC_DW.fulFLg_reset_DSTATE;
|
|
|
-
|
|
|
- /* Logic: '<S50>/Logical Operator' incorporates:
|
|
|
- * Constant: '<S58>/para'
|
|
|
- * RelationalOperator: '<S58>/Relational Operator1'
|
|
|
- * UnitDelay: '<S50>/fulFLg_reset'
|
|
|
- * UnitDelay: '<S50>/overFlg_reset'
|
|
|
- */
|
|
|
- SOC_DW.fulFLg_reset_DSTATE = ((rtb_uDLookupTable3 > 20) ||
|
|
|
- SOC_DW.overFlg_reset_DSTATE);
|
|
|
-
|
|
|
- /* Switch: '<S50>/Switch6' incorporates:
|
|
|
- * Constant: '<S50>/Constant14'
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Saturate: '<S50>/unFul'
|
|
|
- * Sum: '<S57>/Add3'
|
|
|
- * UnitDelay: '<S50>/fulFLg_reset'
|
|
|
- * UnitDelay: '<S57>/socn_pct_estsoc_Delay'
|
|
|
- */
|
|
|
- if (SOC_DW.fulFLg_reset_DSTATE) {
|
|
|
- rtb_Merge = 1000U;
|
|
|
- } else if (SOC_DW.socn_pct_estsoc_Delay_DSTATE < 999) {
|
|
|
- /* Saturate: '<S50>/unFul' incorporates:
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Sum: '<S57>/Add3'
|
|
|
- * UnitDelay: '<S57>/socn_pct_estsoc_Delay'
|
|
|
- */
|
|
|
- rtb_Merge = SOC_DW.socn_pct_estsoc_Delay_DSTATE;
|
|
|
- } else {
|
|
|
- rtb_Merge = 999U;
|
|
|
+ if (socd_pct_ekfSoc > socc_pct_battSocUp)
|
|
|
+ {
|
|
|
+ socd_pct_ekfSoc= socc_pct_battSocUp ;
|
|
|
}
|
|
|
|
|
|
- /* End of Switch: '<S50>/Switch6' */
|
|
|
-
|
|
|
- /* Product: '<S58>/Product' incorporates:
|
|
|
- * Constant: '<S50>/Constant1'
|
|
|
- * Inport: '<Root>/sfmd_V_cellUMax'
|
|
|
- * RelationalOperator: '<S50>/Relational Operator1'
|
|
|
- * UnitDelay: '<S58>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE_f = (uint16_T)(sfmd_V_cellUMax >= socc_V_chrgFulV ?
|
|
|
- (int32_T)rtb_uDLookupTable3 : 0);
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S50>/overFlg_reset' */
|
|
|
- SOC_DW.overFlg_reset_DSTATE = rtb_LogicalOperator1_j;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S7>/chrgCCV' */
|
|
|
- break;
|
|
|
-
|
|
|
- case 1:
|
|
|
- if (SOC_DW.If_ActiveSubsystem != rtPrevAction) {
|
|
|
- /* InitializeConditions for IfAction SubSystem: '<S7>/disChrgCCV' incorporates:
|
|
|
- * ActionPort: '<S51>/Action Port'
|
|
|
- */
|
|
|
- /* InitializeConditions for If: '<S7>/If' incorporates:
|
|
|
- * Logic: '<S51>/Logical Operator'
|
|
|
- * UnitDelay: '<S51>/lowFLg_Delay'
|
|
|
- * UnitDelay: '<S61>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE_e = 1U;
|
|
|
- SOC_DW.lowFLg_Delay_DSTATE = false;
|
|
|
-
|
|
|
- /* End of InitializeConditions for SubSystem: '<S7>/disChrgCCV' */
|
|
|
+ //printf("4----factor:%d,socd_pct_ekfSoc:%d,EKFSOCMax:%d,EKFSOCMin:%d,\n",factor,socd_pct_ekfSoc,EKFSOCMax,EKFSOCMin);
|
|
|
+ //======================================================================
|
|
|
+ ////////////////////////AhSOC//////////////////////////////////////////
|
|
|
+ //======================================================================
|
|
|
+ if (FirstRun_SOC)
|
|
|
+ {
|
|
|
+ ahDelay = (real_T)(socn_pct_battSocEE * 0.1);
|
|
|
}
|
|
|
-
|
|
|
- /* Outputs for IfAction SubSystem: '<S7>/disChrgCCV' incorporates:
|
|
|
- * ActionPort: '<S51>/Action Port'
|
|
|
- */
|
|
|
- /* Saturate: '<S61>/Saturation' incorporates:
|
|
|
- * Constant: '<S61>/Constant'
|
|
|
- * Sum: '<S61>/Add'
|
|
|
- * UnitDelay: '<S61>/Time_Delay'
|
|
|
- */
|
|
|
- if ((uint16_T)(SOC_DW.Time_Delay_DSTATE_e + 1U) < 60000) {
|
|
|
- rtb_Merge = (uint16_T)(SOC_DW.Time_Delay_DSTATE_e + 1U);
|
|
|
- } else {
|
|
|
- rtb_Merge = 60000U;
|
|
|
+ else
|
|
|
+ {
|
|
|
+ ahDelay = ahDelay + battcurr / (real_T)(cmnc_Q_ratedCp *0.1) /360.0;
|
|
|
+ }
|
|
|
+ ahSoc =(int16_T)(ahDelay *10);
|
|
|
+ if (ahSoc >= socc_pct_battSocUp)
|
|
|
+ {
|
|
|
+ socd_pct_ahSoc = socc_pct_battSocUp;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Saturate: '<S61>/Saturation' */
|
|
|
-
|
|
|
- /* Product: '<S61>/Product' incorporates:
|
|
|
- * Inport: '<Root>/sfmd_I_curr'
|
|
|
- * Inport: '<Root>/sfmd_V_cellUMin'
|
|
|
- * Lookup_n-D: '<S51>/1-D Lookup Table'
|
|
|
- * RelationalOperator: '<S51>/Relational Operator'
|
|
|
- * UnitDelay: '<S61>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE_e = (uint16_T)(sfmd_V_cellUMin <=
|
|
|
- look1_is16lu16n16tu16_binlcase(sfmd_I_curr, (&(socm_I_disChrgCor[0])),
|
|
|
- (&(socm_V_disChrgCor[0])), 2U) ? (int32_T)rtb_Merge : 0);
|
|
|
-
|
|
|
- /* Logic: '<S51>/Logical Operator' incorporates:
|
|
|
- * Constant: '<S61>/para'
|
|
|
- * RelationalOperator: '<S61>/Relational Operator1'
|
|
|
- * UnitDelay: '<S51>/lowFLg_Delay'
|
|
|
- */
|
|
|
- SOC_DW.lowFLg_Delay_DSTATE = ((rtb_Merge > 20) || SOC_DW.lowFLg_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Outputs for Triggered SubSystem: '<S51>/Subsystem2' incorporates:
|
|
|
- * TriggerPort: '<S60>/Trigger'
|
|
|
- */
|
|
|
- if (SOC_DW.lowFLg_Delay_DSTATE && (SOC_PrevZCX.Subsystem2_Trig_ZCE != 1)) {
|
|
|
- SOC_B.in_d = rtb_Add1_a;
|
|
|
+ else if (ahSoc <= socc_pct_battSocLow)
|
|
|
+ {
|
|
|
+ socd_pct_ahSoc = socc_pct_battSocLow;
|
|
|
}
|
|
|
-
|
|
|
- SOC_PrevZCX.Subsystem2_Trig_ZCE = SOC_DW.lowFLg_Delay_DSTATE;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S51>/Subsystem2' */
|
|
|
-
|
|
|
- /* Switch: '<S51>/Switch1' incorporates:
|
|
|
- * Inport: '<S60>/in'
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Saturate: '<S51>/Saturation'
|
|
|
- * Sum: '<S11>/Add'
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- */
|
|
|
- if (SOC_DW.lowFLg_Delay_DSTATE) {
|
|
|
- /* Sum: '<S51>/Add2' incorporates:
|
|
|
- * Constant: '<S51>/Constant1'
|
|
|
- * Sum: '<S51>/Add1'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)((int16_T)(rtb_Add1_a - SOC_B.in_d) + 50);
|
|
|
-
|
|
|
- /* Saturate: '<S51>/Saturation1' incorporates:
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Sum: '<S51>/Add2'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k > 0) {
|
|
|
- rtb_Merge = (uint16_T)rtb_Saturation_k;
|
|
|
- } else {
|
|
|
- rtb_Merge = 0U;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Saturate: '<S51>/Saturation1' */
|
|
|
- } else if (socd_pct_ekfSoc > 1000) {
|
|
|
- /* Saturate: '<S51>/Saturation' incorporates:
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- */
|
|
|
- rtb_Merge = 1000U;
|
|
|
- } else if (socd_pct_ekfSoc < 50) {
|
|
|
- /* Saturate: '<S51>/Saturation' incorporates:
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- */
|
|
|
- rtb_Merge = 50U;
|
|
|
- } else {
|
|
|
- rtb_Merge = socd_pct_ekfSoc;
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socd_pct_ahSoc = (uint16_T)ahSoc;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S51>/Switch1' */
|
|
|
- /* End of Outputs for SubSystem: '<S7>/disChrgCCV' */
|
|
|
- break;
|
|
|
-
|
|
|
- default:
|
|
|
- /* Outputs for IfAction SubSystem: '<S7>/If Action Subsystem2' incorporates:
|
|
|
- * ActionPort: '<S48>/Action Port'
|
|
|
- */
|
|
|
- rtb_Merge = socd_pct_ekfSoc;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S7>/If Action Subsystem2' */
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of If: '<S7>/If' */
|
|
|
-
|
|
|
- /* If: '<S7>/If1' incorporates:
|
|
|
- * Abs: '<S12>/Abs'
|
|
|
- * Abs: '<S13>/Abs'
|
|
|
- * Constant: '<S12>/Constant2'
|
|
|
- * Constant: '<S13>/Constant2'
|
|
|
- * Inport: '<S54>/in'
|
|
|
- * Inport: '<S55>/in'
|
|
|
- * Logic: '<S3>/Logical Operator'
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * RelationalOperator: '<S12>/Relational Operator'
|
|
|
- * RelationalOperator: '<S13>/Relational Operator'
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- * UnitDelay: '<S52>/Unit Delay1'
|
|
|
- * UnitDelay: '<S53>/Unit Delay1'
|
|
|
- */
|
|
|
- if ((fabs(deltaU) > 0.005) || (fabs(rtb_Add_l) > 0.005)) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S7>/If Action Subsystem' incorporates:
|
|
|
- * ActionPort: '<S46>/Action Port'
|
|
|
- */
|
|
|
- /* Outputs for Enabled SubSystem: '<S52>/Subsystem3' incorporates:
|
|
|
- * EnablePort: '<S54>/Enable'
|
|
|
- */
|
|
|
- if (SOC_DW.UnitDelay1_DSTATE) {
|
|
|
- SOC_B.in_f = rtb_Add1_a;
|
|
|
+ // printf("5----ahDelay:%f,ahSoc:%d,battcurr:%f,sfmd_I_curr:%d\n",ahDelay,ahSoc,battcurr,sfmd_I_curr);
|
|
|
+ //======================================================================
|
|
|
+ ///////////////////////estSOC//////////////////////////////////////////
|
|
|
+ //======================================================================
|
|
|
+ if(!socn_flg_ekfInvalid)
|
|
|
+ {
|
|
|
+ ekfInvalidCntl = ( (ekfInvalidCntl + 1) > 60000 ? 60000 :(ekfInvalidCntl + 1));
|
|
|
}
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S52>/Subsystem3' */
|
|
|
-
|
|
|
- /* Outputs for Enabled SubSystem: '<S53>/Subsystem3' incorporates:
|
|
|
- * EnablePort: '<S55>/Enable'
|
|
|
- */
|
|
|
- if (SOC_DW.UnitDelay1_DSTATE_p) {
|
|
|
- SOC_B.in = rtb_Merge;
|
|
|
+ else
|
|
|
+ {
|
|
|
+ ekfInvalidCntl = 0;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S53>/Subsystem3' */
|
|
|
-
|
|
|
- /* Sum: '<S46>/Add1' incorporates:
|
|
|
- * Inport: '<S54>/in'
|
|
|
- * Inport: '<S55>/in'
|
|
|
- * Merge: '<S7>/Merge'
|
|
|
- * Sum: '<S46>/Add'
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- * UnitDelay: '<S52>/Unit Delay1'
|
|
|
- * UnitDelay: '<S53>/Unit Delay1'
|
|
|
- */
|
|
|
- rtb_Merge = (uint16_T)((int16_T)(rtb_Add1_a - SOC_B.in_f) + SOC_B.in);
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S52>/Unit Delay1' incorporates:
|
|
|
- * Constant: '<S52>/Constant1'
|
|
|
- */
|
|
|
- SOC_DW.UnitDelay1_DSTATE = false;
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S53>/Unit Delay1' incorporates:
|
|
|
- * Constant: '<S53>/Constant1'
|
|
|
- */
|
|
|
- SOC_DW.UnitDelay1_DSTATE_p = false;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S7>/If Action Subsystem' */
|
|
|
- }
|
|
|
-
|
|
|
- /* End of If: '<S7>/If1' */
|
|
|
-
|
|
|
- /* Saturate: '<S7>/Saturation' incorporates:
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- */
|
|
|
- if (rtb_Merge > socc_pct_battSocUp) {
|
|
|
- /* Saturate: '<S7>/Saturation' */
|
|
|
- socd_pct_battSoc = socc_pct_battSocUp;
|
|
|
- } else if (rtb_Merge < socc_pct_battSocLow) {
|
|
|
- /* Saturate: '<S7>/Saturation' */
|
|
|
- socd_pct_battSoc = socc_pct_battSocLow;
|
|
|
- } else {
|
|
|
- /* Saturate: '<S7>/Saturation' */
|
|
|
- socd_pct_battSoc = rtb_Merge;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Saturate: '<S7>/Saturation' */
|
|
|
-
|
|
|
- /* UnitDelay: '<S6>/First_Delay' incorporates:
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE_h = SOC_DW.First_Delay_DSTATE;
|
|
|
-
|
|
|
- /* Sum: '<S6>/Add' incorporates:
|
|
|
- * Abs: '<S32>/Abs1'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * UnitDelay: '<S6>/Unit Delay7'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(socd_pct_battSoc - SOC_DW.UnitDelay7_DSTATE);
|
|
|
-
|
|
|
- /* Abs: '<S6>/Abs' incorporates:
|
|
|
- * Abs: '<S32>/Abs1'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k < 0) {
|
|
|
- rtb_Saturation_k = (int16_T)-rtb_Saturation_k;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Abs: '<S6>/Abs' */
|
|
|
-
|
|
|
- /* RelationalOperator: '<S6>/Relational Operator6' incorporates:
|
|
|
- * Abs: '<S32>/Abs1'
|
|
|
- * UnitDelay: '<S14>/Frist'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE = (rtb_Saturation_k > 20);
|
|
|
-
|
|
|
- /* Saturate: '<S35>/Saturation' incorporates:
|
|
|
- * Constant: '<S35>/Constant'
|
|
|
- * Sum: '<S35>/Add'
|
|
|
- * UnitDelay: '<S35>/Time_Delay'
|
|
|
- */
|
|
|
- if ((uint16_T)(SOC_DW.Time_Delay_DSTATE + 1U) < 60000) {
|
|
|
- rtb_Merge = (uint16_T)(SOC_DW.Time_Delay_DSTATE + 1U);
|
|
|
- } else {
|
|
|
- rtb_Merge = 60000U;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Saturate: '<S35>/Saturation' */
|
|
|
-
|
|
|
- /* Logic: '<S6>/Logical Operator' incorporates:
|
|
|
- * Constant: '<S35>/para'
|
|
|
- * Constant: '<S6>/Constant3'
|
|
|
- * Constant: '<S6>/Constant4'
|
|
|
- * Constant: '<S6>/Constant5'
|
|
|
- * Constant: '<S6>/Constant6'
|
|
|
- * Inport: '<Root>/ihd_st_workStat'
|
|
|
- * Logic: '<S6>/Logical Operator1'
|
|
|
- * Logic: '<S6>/Logical Operator2'
|
|
|
- * RelationalOperator: '<S35>/Relational Operator1'
|
|
|
- * RelationalOperator: '<S6>/Relational Operator1'
|
|
|
- * RelationalOperator: '<S6>/Relational Operator2'
|
|
|
- * RelationalOperator: '<S6>/Relational Operator3'
|
|
|
- * RelationalOperator: '<S6>/Relational Operator4'
|
|
|
- * UnitDelay: '<S14>/Frist'
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- * UnitDelay: '<S6>/ihd_st_chrgSta_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE_h = (SOC_DW.Frist_DSTATE_h ||
|
|
|
- ((SOC_DW.ihd_st_chrgSta_Delay_DSTATE == 2) && (ihd_st_workStat != 2)) ||
|
|
|
- ((SOC_DW.ihd_st_chrgSta_Delay_DSTATE != 2) && (ihd_st_workStat == 2)) ||
|
|
|
- SOC_DW.Frist_DSTATE || (rtb_Merge > 20));
|
|
|
-
|
|
|
- /* Switch: '<S6>/Switch1' incorporates:
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- if (SOC_DW.Frist_DSTATE_h) {
|
|
|
- SOC_DW.socd_pct_battSoc0_Delay_DSTATE = socd_pct_battSoc;
|
|
|
-
|
|
|
- /* Switch: '<S6>/Switch4' incorporates:
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * UnitDelay: '<S6>/First_Delay1'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- if (SOC_DW.First_Delay1_DSTATE) {
|
|
|
- /* Switch: '<S6>/Switch2' incorporates:
|
|
|
- * Merge: '<S2>/socn_pct_bcuSocEE_Merge'
|
|
|
- */
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE = SOC_B.socn_pct_bcuSocEE_Merge;
|
|
|
- } else {
|
|
|
- /* Switch: '<S6>/Switch2' incorporates:
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcusocDelay'
|
|
|
- */
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE = SOC_DW.socd_pct_bcusocDelay_DSTATE;
|
|
|
+
|
|
|
+ if (ekfInvalidCntl < 200)
|
|
|
+ {
|
|
|
+ if (onceFlg_est)
|
|
|
+ {
|
|
|
+ ahSoc0_est = ahSoc;
|
|
|
+ ekfSoc0_est = socd_pct_ekfSoc;
|
|
|
+ }
|
|
|
+ socd_pct_estSoc = (((int16_T)(ahSoc - ahSoc0_est) + ekfSoc0_est)>0 ? (uint16_T)((int16_T)(ahSoc - ahSoc0_est) + ekfSoc0_est) : 0);
|
|
|
+ onceFlg_est = false;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S6>/Switch4' */
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S6>/Switch1' */
|
|
|
-
|
|
|
- /* If: '<S6>/If' incorporates:
|
|
|
- * Constant: '<S6>/Constant1'
|
|
|
- * Inport: '<Root>/ihd_st_workStat'
|
|
|
- * RelationalOperator: '<S41>/Relational Operator11'
|
|
|
- * RelationalOperator: '<S41>/Relational Operator12'
|
|
|
- * RelationalOperator: '<S6>/Relational Operator7'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- if (ihd_st_workStat == 2) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S6>/Subsystem2' incorporates:
|
|
|
- * ActionPort: '<S33>/Action Port'
|
|
|
- */
|
|
|
- /* Switch: '<S36>/Switch7' incorporates:
|
|
|
- * RelationalOperator: '<S36>/Relational Operator11'
|
|
|
- * RelationalOperator: '<S36>/Relational Operator12'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- if (socd_pct_battSoc <= SOC_DW.socd_pct_battSoc0_Delay_DSTATE) {
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE;
|
|
|
- } else if (socd_pct_battSoc >= 1000) {
|
|
|
- /* Switch: '<S36>/Switch7' incorporates:
|
|
|
- * Constant: '<S33>/Constant8'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = 1000U;
|
|
|
- } else {
|
|
|
- /* Sum: '<S33>/Add4' incorporates:
|
|
|
- * Sum: '<S33>/Add3'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(SOC_DW.socd_pct_battSoc0_Delay_DSTATE -
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Abs: '<S33>/Abs4' incorporates:
|
|
|
- * Sum: '<S33>/Add3'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k < 0) {
|
|
|
- rtb_Saturation_k = (int16_T)-rtb_Saturation_k;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Abs: '<S33>/Abs4' */
|
|
|
-
|
|
|
- /* MinMax: '<S33>/Max8' incorporates:
|
|
|
- * Constant: '<S33>/Constant23'
|
|
|
- * Sum: '<S33>/Add3'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- */
|
|
|
- if (50 < rtb_Saturation_k) {
|
|
|
- rtb_Saturation_k = 50;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S33>/Max8' */
|
|
|
-
|
|
|
- /* MinMax: '<S33>/Max6' incorporates:
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- */
|
|
|
- if (SOC_DW.socd_pct_battSoc0_Delay_DSTATE >
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE) {
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_battSoc0_Delay_DSTATE;
|
|
|
- } else {
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S33>/Max6' */
|
|
|
-
|
|
|
- /* MinMax: '<S33>/Max7' incorporates:
|
|
|
- * Sum: '<S33>/Add3'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- */
|
|
|
- i = (int16_T)(rtb_Saturation_k + rtb_uDLookupTable3);
|
|
|
- if (999 < i) {
|
|
|
- rtb_uDLookupTable3 = 999U;
|
|
|
- } else {
|
|
|
- rtb_uDLookupTable3 = (uint16_T)i;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S33>/Max7' */
|
|
|
-
|
|
|
- /* Switch: '<S36>/Switch9' incorporates:
|
|
|
- * MinMax: '<S33>/Max7'
|
|
|
- * RelationalOperator: '<S36>/Relational Operator13'
|
|
|
- * Switch: '<S36>/Switch8'
|
|
|
- */
|
|
|
- if (socd_pct_battSoc > rtb_uDLookupTable3) {
|
|
|
- /* Switch: '<S36>/Switch7' incorporates:
|
|
|
- * Constant: '<S33>/Constant8'
|
|
|
- * Constant: '<S33>/Constant9'
|
|
|
- * Product: '<S36>/Divide1'
|
|
|
- * Product: '<S36>/Product1'
|
|
|
- * Sum: '<S36>/Add10'
|
|
|
- * Sum: '<S36>/Add11'
|
|
|
- * Sum: '<S36>/Add8'
|
|
|
- * Sum: '<S36>/Add9'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(((((uint16_T)(((uint16_T)div_repeat_u32
|
|
|
- ((uint32_T)(uint16_T)(socd_pct_battSoc - rtb_uDLookupTable3) * (1000 -
|
|
|
- rtb_uDLookupTable3), (uint16_T)(1000 - rtb_uDLookupTable3), 3U) * 5U) >>
|
|
|
- 2) * 52429U) >> 4) + ((uint32_T)rtb_uDLookupTable3 << 15)) >> 15);
|
|
|
- } else {
|
|
|
- /* Sum: '<S36>/Add6' incorporates:
|
|
|
- * Sum: '<S36>/Add5'
|
|
|
- */
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = (uint16_T)(rtb_uDLookupTable3 -
|
|
|
- SOC_DW.socd_pct_battSoc0_Delay_DSTATE);
|
|
|
-
|
|
|
- /* MinMax: '<S36>/Max' incorporates:
|
|
|
- * Constant: '<S36>/Constant'
|
|
|
- * Sum: '<S36>/Add5'
|
|
|
- */
|
|
|
- if (1 > rtb_socd_pct_bcuSoc0_Delay) {
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = 1U;
|
|
|
+ else
|
|
|
+ {
|
|
|
+ onceFlg_est = true;
|
|
|
+ socd_pct_estSoc = socd_pct_ekfSoc;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (socd_pct_estSoc >= socc_pct_battSocUp)
|
|
|
+ {
|
|
|
+ socd_pct_estSoc = socc_pct_battSocUp;
|
|
|
+ }
|
|
|
+ if (socd_pct_estSoc <= socc_pct_battSocLow)
|
|
|
+ {
|
|
|
+ socd_pct_estSoc = socc_pct_battSocLow;
|
|
|
+ }
|
|
|
+ //printf("6----ahSoc0_est:%d,ekfSoc0_est:%d,socd_pct_estSoc:%d\n",ahSoc0_est,ekfSoc0_est,socd_pct_estSoc);
|
|
|
+ //======================================================================
|
|
|
+ ////////////////////////UtrackSOC//////////////////////////////////////////
|
|
|
+ //======================================================================
|
|
|
+ if (ihd_st_workStat == 2)
|
|
|
+ {
|
|
|
+ disChrgCntl=0;
|
|
|
+ chrgCntl = ((chrgCntl+1) >60000 ? 60000 : (chrgCntl+1));
|
|
|
+ lowCntl=0;
|
|
|
+ lowFlg = 0;
|
|
|
+ if(sfmd_V_cellUMax >= look1_is16lu16n16tu16_binlcase(sfmd_I_curr, (&(socm_I_chrgCor[0])),(&(socm_V_chrgCor[0])), 3U))
|
|
|
+ {
|
|
|
+ overCntl = ( (overCntl + 1) > 60000 ? 60000 : (overCntl + 1));
|
|
|
}
|
|
|
-
|
|
|
- /* End of MinMax: '<S36>/Max' */
|
|
|
-
|
|
|
- /* Switch: '<S36>/Switch7' incorporates:
|
|
|
- * Product: '<S36>/Divide'
|
|
|
- * Product: '<S36>/Product'
|
|
|
- * Sum: '<S36>/Add4'
|
|
|
- * Sum: '<S36>/Add5'
|
|
|
- * Sum: '<S36>/Add7'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(((((uint16_T)(((uint16_T)div_repeat_u32
|
|
|
- ((uint32_T)(uint16_T)(socd_pct_battSoc -
|
|
|
- SOC_DW.socd_pct_battSoc0_Delay_DSTATE) * (uint16_T)(rtb_uDLookupTable3
|
|
|
- - SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE), rtb_socd_pct_bcuSoc0_Delay,
|
|
|
- 3U) * 5U) >> 2) * 52429U) >> 4) + ((uint32_T)
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE << 15)) >> 15);
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S36>/Switch9' */
|
|
|
+ else
|
|
|
+ {
|
|
|
+ overCntl=0;
|
|
|
+ }
|
|
|
+ if(overCntl > 20 || overFlg)
|
|
|
+ {
|
|
|
+ overFlg = 1;
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if(sfmd_V_cellUMax >= socc_V_chrgFulV)
|
|
|
+ {
|
|
|
+ fulCntl = ( (fulCntl + 1) > 60000 ? 60000 : (fulCntl + 1));
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ fulCntl=0;
|
|
|
+ }
|
|
|
+ if(fulCntl > 20 || fulFlg)
|
|
|
+ {
|
|
|
+ fulFlg = 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ //
|
|
|
+ if (overFlg)
|
|
|
+ {
|
|
|
+ if (onceFlg_utrckOver)
|
|
|
+ {
|
|
|
+ ahSoc0_utrckOver = ahSoc;
|
|
|
+ estSoc0_utrckOver = socd_pct_estSoc;
|
|
|
+ }
|
|
|
+ estSoc0_utrckOver = (estSoc0_utrckOver > 950 ? estSoc0_utrckOver : 950);
|
|
|
+ socTemp = (uint16_T)((int16_T)(ahSoc - ahSoc0_utrckOver) + estSoc0_utrckOver);
|
|
|
+ onceFlg_utrckOver = false;
|
|
|
+ }
|
|
|
+ else if (chrgCntl >20)
|
|
|
+ {
|
|
|
+
|
|
|
+ onceFlg_utrckOver = true;
|
|
|
+ socTemp = (socd_pct_estSoc > 950 ? 950 : socd_pct_estSoc);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socTemp = socd_pct_estSoc;
|
|
|
+ }
|
|
|
+
|
|
|
+ socn_pct_utrackSoc = Soc_Delay + ( (int16_T) (socTemp - Soc_Delay) > 0 ? (socTemp - Soc_Delay) :0);
|
|
|
+ Soc_Delay = socn_pct_utrackSoc;
|
|
|
+ socn_pct_utrackSoc =(socn_pct_utrackSoc > 999 ? 999 : socn_pct_utrackSoc);
|
|
|
+ if (fulFlg)
|
|
|
+ {
|
|
|
+ socn_pct_utrackSoc= 1000;
|
|
|
+ }
|
|
|
+
|
|
|
+ //printf("7----overCntl:%d,overFlg:%d,fulCntl:%d,fulFlg:%d,ahSoc0_utrckOver:%d,estSoc0_utrckOver:%d,socn_pct_utrackSoc:%d\n",overCntl,overFlg,fulCntl,fulFlg,ahSoc0_utrckOver,estSoc0_utrckOver,socn_pct_utrackSoc);
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S36>/Switch7' */
|
|
|
-
|
|
|
- /* Saturate: '<S33>/Saturation1' incorporates:
|
|
|
- * Switch: '<S36>/Switch7'
|
|
|
- */
|
|
|
- if (rtb_uDLookupTable3 >= 999) {
|
|
|
- rtb_uDLookupTable3 = 999U;
|
|
|
+ else
|
|
|
+ { chrgCntl=0;
|
|
|
+ disChrgCntl = ((disChrgCntl+1) >60000 ? 60000 : (disChrgCntl+1));
|
|
|
+ Soc_Delay = 0;
|
|
|
+ overCntl = 0;
|
|
|
+ overFlg = 0;
|
|
|
+ fulFlg = 0;
|
|
|
+ fulCntl = 0;
|
|
|
+ if(sfmd_V_cellUMin <=look1_is16lu16n16tu16_binlcase(sfmd_I_curr, (&(socm_I_disChrgCor[0])),(&(socm_V_disChrgCor[0])), 2U))
|
|
|
+ {
|
|
|
+ lowCntl = ( (lowCntl + 1) > 60000 ? 60000 : (lowCntl + 1));
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ lowCntl=0;
|
|
|
+ }
|
|
|
+ if(lowCntl > 20 || lowFlg)
|
|
|
+ {
|
|
|
+ lowFlg = 1;
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if (lowFlg)
|
|
|
+ {
|
|
|
+ if (onceFlg_utrckLow)
|
|
|
+ {
|
|
|
+ ahSoc0_utrckLow = ahSoc;
|
|
|
+ estSoc0_utrckLow = socd_pct_estSoc;
|
|
|
+ }
|
|
|
+ estSoc0_utrckLow = (estSoc0_utrckLow < 50 ? estSoc0_utrckLow : 50);
|
|
|
+ socn_pct_utrackSoc = (((int16_T)(ahSoc - ahSoc0_utrckLow) + estSoc0_utrckLow)>0 ? (uint16_T)((int16_T)(ahSoc - ahSoc0_utrckLow) + estSoc0_utrckLow) : 0);
|
|
|
+ onceFlg_utrckLow = false;
|
|
|
+ }
|
|
|
+ else if(disChrgCntl > 20)
|
|
|
+ {
|
|
|
+ onceFlg_utrckLow = true;
|
|
|
+ socn_pct_utrackSoc = (socd_pct_estSoc < 50 ? 50 :socd_pct_estSoc);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socn_pct_utrackSoc = socd_pct_estSoc;
|
|
|
+ }
|
|
|
+ // printf("8----lowCntl:%d,lowFlg:%d,ahSoc0_utrckLow:%d,estSoc0_utrckLow:%d,socn_pct_utrackSoc:%d\n",lowCntl,lowFlg,ahSoc0_utrckLow,estSoc0_utrckLow,socn_pct_utrackSoc);
|
|
|
}
|
|
|
-
|
|
|
- /* End of Saturate: '<S33>/Saturation1' */
|
|
|
-
|
|
|
- /* Sum: '<S37>/Add6' incorporates:
|
|
|
- * Saturate: '<S33>/Saturation1'
|
|
|
- * UnitDelay: '<S37>/socfit_Delay'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(rtb_uDLookupTable3 -
|
|
|
- SOC_DW.socfit_Delay_DSTATE_n);
|
|
|
-
|
|
|
- /* Switch: '<S37>/Switch' incorporates:
|
|
|
- * If: '<S37>/If'
|
|
|
- * Logic: '<S37>/Logical Operator'
|
|
|
- * RelationalOperator: '<S37>/Relational Operator'
|
|
|
- * RelationalOperator: '<S37>/Relational Operator1'
|
|
|
- * RelationalOperator: '<S37>/Relational Operator2'
|
|
|
- * Sum: '<S37>/Add6'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k > 1) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S37>/If Action Subsystem' incorporates:
|
|
|
- * ActionPort: '<S38>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S37>/If' incorporates:
|
|
|
- * UnitDelay: '<S37>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_IfActionSubsystem(rtb_uDLookupTable3, SOC_DW.socfit_Delay_DSTATE_n,
|
|
|
- &SOC_DW.socfit_Delay_DSTATE_n, 1);
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S37>/If Action Subsystem' */
|
|
|
- } else if ((rtb_Saturation_k < -1) && (rtb_Saturation_k > -1000)) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S37>/If Action Subsystem1' incorporates:
|
|
|
- * ActionPort: '<S39>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S37>/If' incorporates:
|
|
|
- * UnitDelay: '<S37>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_IfActionSubsystem1(rtb_uDLookupTable3, SOC_DW.socfit_Delay_DSTATE_n,
|
|
|
- &SOC_DW.socfit_Delay_DSTATE_n);
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S37>/If Action Subsystem1' */
|
|
|
- } else {
|
|
|
- /* Outputs for IfAction SubSystem: '<S37>/If Action Subsystem2' incorporates:
|
|
|
- * ActionPort: '<S40>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S37>/If' incorporates:
|
|
|
- * Inport: '<S40>/In1'
|
|
|
- * Merge: '<S37>/Merge'
|
|
|
- * Saturate: '<S33>/Saturation1'
|
|
|
- * UnitDelay: '<S37>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_DW.socfit_Delay_DSTATE_n = rtb_uDLookupTable3;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S37>/If Action Subsystem2' */
|
|
|
+ //===================================================================
|
|
|
+ //------------------EEsave
|
|
|
+ //==================================================================
|
|
|
+ socd_pct_battSoc = socn_pct_utrackSoc;
|
|
|
+ socd_pct_battSocEo = socn_pct_utrackSoc;
|
|
|
+ if ( (int16_T)(socd_pct_battSoc - socd_pct_battSoc_Delay) > 10 || (int16_T)(socd_pct_battSoc - socd_pct_battSoc_Delay) <- 10 )
|
|
|
+ {
|
|
|
+ socd_flg_EEsave =1;
|
|
|
+ socd_pct_battSoc_Delay = socd_pct_battSoc;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socd_flg_EEsave=0;
|
|
|
+ }
|
|
|
+
|
|
|
+ //=====================================================================
|
|
|
+ //////////////////////////////BCUSOC///////////////////////////////////
|
|
|
+ //=====================================================================
|
|
|
+
|
|
|
+
|
|
|
+ if(sfmd_I_curr < 100 && sfmd_I_curr > -100)
|
|
|
+ {
|
|
|
+ statCntl= (statCntl >60000 ? 60000 :statCntl);
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S37>/Switch' */
|
|
|
-
|
|
|
- /* Switch: '<S33>/Switch6' incorporates:
|
|
|
- * Constant: '<S33>/Constant14'
|
|
|
- * Merge: '<S37>/Merge'
|
|
|
- * Merge: '<S6>/Merge'
|
|
|
- * UnitDelay: '<S37>/socfit_Delay'
|
|
|
- * UnitDelay: '<S50>/fulFLg_reset'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcusocDelay'
|
|
|
- */
|
|
|
- if (SOC_DW.fulFLg_reset_DSTATE) {
|
|
|
- SOC_DW.socd_pct_bcusocDelay_DSTATE = 1000U;
|
|
|
- } else {
|
|
|
- SOC_DW.socd_pct_bcusocDelay_DSTATE = SOC_DW.socfit_Delay_DSTATE_n;
|
|
|
+ else
|
|
|
+ {
|
|
|
+ statCntl=0;
|
|
|
}
|
|
|
-
|
|
|
- /* End of Switch: '<S33>/Switch6' */
|
|
|
- /* End of Outputs for SubSystem: '<S6>/Subsystem2' */
|
|
|
- } else {
|
|
|
- /* Outputs for IfAction SubSystem: '<S6>/Subsystem3' incorporates:
|
|
|
- * ActionPort: '<S34>/Action Port'
|
|
|
- */
|
|
|
- if (socd_pct_battSoc <= 0) {
|
|
|
- /* Switch: '<S41>/Switch7' incorporates:
|
|
|
- * Constant: '<S34>/Constant30'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = 0U;
|
|
|
- } else if (socd_pct_battSoc >= SOC_DW.socd_pct_battSoc0_Delay_DSTATE) {
|
|
|
- /* Switch: '<S41>/Switch7' incorporates:
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE;
|
|
|
- } else {
|
|
|
- /* Sum: '<S34>/Add4' incorporates:
|
|
|
- * Sum: '<S34>/Add2'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(SOC_DW.socd_pct_battSoc0_Delay_DSTATE -
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Abs: '<S34>/Abs4' incorporates:
|
|
|
- * Sum: '<S34>/Add2'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k < 0) {
|
|
|
- rtb_Saturation_k = (int16_T)-rtb_Saturation_k;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Abs: '<S34>/Abs4' */
|
|
|
-
|
|
|
- /* MinMax: '<S34>/Max4' incorporates:
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- if (SOC_DW.socd_pct_battSoc0_Delay_DSTATE <
|
|
|
- SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE) {
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_battSoc0_Delay_DSTATE;
|
|
|
- } else {
|
|
|
- rtb_uDLookupTable3 = SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S34>/Max4' */
|
|
|
-
|
|
|
- /* MinMax: '<S34>/Max8' incorporates:
|
|
|
- * Constant: '<S34>/Constant23'
|
|
|
- * Sum: '<S34>/Add2'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- */
|
|
|
- if (50 < rtb_Saturation_k) {
|
|
|
- rtb_Saturation_k = 50;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S34>/Max8' */
|
|
|
-
|
|
|
- /* MinMax: '<S34>/Max2' incorporates:
|
|
|
- * Sum: '<S34>/Add2'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- */
|
|
|
- i = (int16_T)(rtb_uDLookupTable3 - rtb_Saturation_k);
|
|
|
- if (i > 1) {
|
|
|
- rtb_uDLookupTable3 = (uint16_T)i;
|
|
|
- } else {
|
|
|
- rtb_uDLookupTable3 = 1U;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of MinMax: '<S34>/Max2' */
|
|
|
-
|
|
|
- /* Switch: '<S41>/Switch9' incorporates:
|
|
|
- * MinMax: '<S34>/Max2'
|
|
|
- * RelationalOperator: '<S41>/Relational Operator13'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- */
|
|
|
- if (socd_pct_battSoc > rtb_uDLookupTable3) {
|
|
|
- /* Sum: '<S41>/Add10' incorporates:
|
|
|
- * Product: '<S41>/Divide1'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = (uint16_T)
|
|
|
- (SOC_DW.socd_pct_battSoc0_Delay_DSTATE - rtb_uDLookupTable3);
|
|
|
-
|
|
|
- /* MinMax: '<S41>/Max1' incorporates:
|
|
|
- * Constant: '<S41>/Constant1'
|
|
|
- * Product: '<S41>/Divide1'
|
|
|
- */
|
|
|
- if (1 > rtb_socd_pct_bcuSoc0_Delay) {
|
|
|
- rtb_socd_pct_bcuSoc0_Delay = 1U;
|
|
|
+ statFlg = statCntl > 20 || statFlg;
|
|
|
+
|
|
|
+ Flg= (FirstRun_SOC ||((ihd_st_chrgSta_Delay == 2) && (ihd_st_workStat != 2)) ||((ihd_st_chrgSta_Delay!= 2) && (ihd_st_workStat == 2))
|
|
|
+ || ((int16_T)(socn_pct_utrackSoc -socn_pct_utrackSoc_Delay) > 20 ||(int16_T)(socn_pct_utrackSoc -socn_pct_utrackSoc_Delay) <- 20 )||statFlg);
|
|
|
+ ihd_st_chrgSta_Delay = ihd_st_workStat;
|
|
|
+ socn_pct_utrackSoc_Delay = socn_pct_utrackSoc;
|
|
|
+ //
|
|
|
+ if(Flg)
|
|
|
+ {
|
|
|
+ socd_pct_battSoc0 = socd_pct_battSoc;
|
|
|
+ if(FirstRun_SOC)
|
|
|
+ {
|
|
|
+ socd_pct_bcuSoc0 = socn_pct_bcuSocEE;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socd_pct_bcuSoc0 = socd_pct_bcuSoc_Delay;
|
|
|
}
|
|
|
-
|
|
|
- /* End of MinMax: '<S41>/Max1' */
|
|
|
-
|
|
|
- /* Switch: '<S41>/Switch7' incorporates:
|
|
|
- * Product: '<S41>/Divide1'
|
|
|
- * Product: '<S41>/Product1'
|
|
|
- * Sum: '<S41>/Add11'
|
|
|
- * Sum: '<S41>/Add8'
|
|
|
- * Sum: '<S41>/Add9'
|
|
|
- * Switch: '<S6>/Switch2'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(((((uint16_T)(((uint16_T)div_repeat_u32
|
|
|
- ((uint32_T)(uint16_T)(socd_pct_battSoc - rtb_uDLookupTable3) *
|
|
|
- (uint16_T)(SOC_DW.socd_pct_bcuSoc0_Delay_DSTATE - rtb_uDLookupTable3),
|
|
|
- rtb_socd_pct_bcuSoc0_Delay, 3U) * 5U) >> 2) * 52429U) >> 4) +
|
|
|
- ((uint32_T)rtb_uDLookupTable3 << 15)) >> 15);
|
|
|
- } else {
|
|
|
- /* Switch: '<S41>/Switch7' incorporates:
|
|
|
- * Product: '<S41>/Divide'
|
|
|
- * Product: '<S41>/Product'
|
|
|
- * Sum: '<S41>/Add4'
|
|
|
- * Sum: '<S41>/Add5'
|
|
|
- * Sum: '<S41>/Add6'
|
|
|
- * Sum: '<S41>/Add7'
|
|
|
- */
|
|
|
- rtb_uDLookupTable3 = (uint16_T)(((uint16_T)(((uint16_T)div_repeat_u32
|
|
|
- ((uint32_T)socd_pct_battSoc * rtb_uDLookupTable3, rtb_uDLookupTable3,
|
|
|
- 3U) * 5U) >> 2) * 52429U) >> 19);
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S41>/Switch9' */
|
|
|
}
|
|
|
-
|
|
|
- /* Sum: '<S42>/Add6' incorporates:
|
|
|
- * RelationalOperator: '<S41>/Relational Operator12'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * Switch: '<S41>/Switch8'
|
|
|
- * Switch: '<S6>/Switch1'
|
|
|
- * UnitDelay: '<S42>/socfit_Delay'
|
|
|
- * UnitDelay: '<S6>/socd_pct_battSoc0_Delay'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(rtb_uDLookupTable3 - SOC_DW.socfit_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Switch: '<S42>/Switch' incorporates:
|
|
|
- * If: '<S42>/If'
|
|
|
- * Logic: '<S42>/Logical Operator'
|
|
|
- * RelationalOperator: '<S42>/Relational Operator'
|
|
|
- * RelationalOperator: '<S42>/Relational Operator1'
|
|
|
- * RelationalOperator: '<S42>/Relational Operator2'
|
|
|
- * Sum: '<S42>/Add6'
|
|
|
- */
|
|
|
- if (rtb_Saturation_k > 1) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S42>/If Action Subsystem' incorporates:
|
|
|
- * ActionPort: '<S43>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S42>/If' incorporates:
|
|
|
- * UnitDelay: '<S42>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_IfActionSubsystem(rtb_uDLookupTable3, SOC_DW.socfit_Delay_DSTATE,
|
|
|
- &SOC_DW.socfit_Delay_DSTATE, 1);
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S42>/If Action Subsystem' */
|
|
|
- } else if ((rtb_Saturation_k < -1) && (rtb_Saturation_k > -1000)) {
|
|
|
- /* Outputs for IfAction SubSystem: '<S42>/If Action Subsystem1' incorporates:
|
|
|
- * ActionPort: '<S44>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S42>/If' incorporates:
|
|
|
- * UnitDelay: '<S42>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_IfActionSubsystem1(rtb_uDLookupTable3, SOC_DW.socfit_Delay_DSTATE,
|
|
|
- &SOC_DW.socfit_Delay_DSTATE);
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S42>/If Action Subsystem1' */
|
|
|
- } else {
|
|
|
- /* Outputs for IfAction SubSystem: '<S42>/If Action Subsystem2' incorporates:
|
|
|
- * ActionPort: '<S45>/Action Port'
|
|
|
- */
|
|
|
- /* If: '<S42>/If' incorporates:
|
|
|
- * Inport: '<S45>/In1'
|
|
|
- * Merge: '<S42>/Merge'
|
|
|
- * Switch: '<S41>/Switch7'
|
|
|
- * UnitDelay: '<S42>/socfit_Delay'
|
|
|
- */
|
|
|
- SOC_DW.socfit_Delay_DSTATE = rtb_uDLookupTable3;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S42>/If Action Subsystem2' */
|
|
|
+ //printf("9------socd_pct_battSoc:%d\n",socd_pct_battSoc);
|
|
|
+ //printf("9----statCntl:%d,statFlg:%d,Flg:%d,socd_pct_bcuSoc0:%d,socd_pct_bcuSoc0:%d\n",statCntl,statFlg,Flg,socd_pct_bcuSoc0,socd_pct_bcuSoc0);
|
|
|
+ //
|
|
|
+ if(ihd_st_workStat == 2)
|
|
|
+ {
|
|
|
+ delSOC = ((int16_T) (socd_pct_battSoc0 - socd_pct_bcuSoc0) > 0 ? (socd_pct_battSoc0 - socd_pct_bcuSoc0) : (socd_pct_bcuSoc0 - socd_pct_battSoc0));
|
|
|
+ coinSoc = (int16_T)(socd_pct_battSoc0 > socd_pct_bcuSoc0 ? socd_pct_battSoc0 : socd_pct_bcuSoc0) + (delSOC > 50 ? 50 : delSOC);
|
|
|
+
|
|
|
+ x[0] = socd_pct_battSoc0;
|
|
|
+ x[1] = (coinSoc> 1000 ? 1000 : (uint16_T)coinSoc);;
|
|
|
+ x[2] = 1000;
|
|
|
+ y[0] = socd_pct_bcuSoc0;
|
|
|
+ y[1] = (coinSoc> 1000 ? 1000 : (uint16_T)coinSoc);;
|
|
|
+ y[2] = 1000;
|
|
|
+
|
|
|
+ SOC_LookUp( socd_pct_battSoc, &x[0], &y[0], &bcuSoc);
|
|
|
+
|
|
|
+
|
|
|
+ //
|
|
|
+ onceFlg_dischrg = true;
|
|
|
+ if (onceFlg_chrg)
|
|
|
+ {
|
|
|
+ SocFitChrg_Delay = 2000;
|
|
|
+ }
|
|
|
+ //printf("onceFlg_chrg:%d,SocFitChrg_Delay:%d\n",onceFlg_chrg,SocFitChrg_Delay);
|
|
|
+ onceFlg_chrg =false;
|
|
|
+ if ((int16_T)(bcuSoc - SocFitChrg_Delay ) > 1)
|
|
|
+ {
|
|
|
+ SOCfit_IfActionSubsystem1( bcuSoc, SocFitChrg_Delay, &SocFitChrg, 1);
|
|
|
+ }
|
|
|
+ if ((int16_T)(bcuSoc - SocFitChrg_Delay ) <-1 && (int16_T)(bcuSoc - SocFitChrg_Delay ) > -1000)
|
|
|
+ {
|
|
|
+ SOCfit_IfActionSubsystem2( bcuSoc, SocFitChrg_Delay, &SocFitChrg, 1);
|
|
|
+ }
|
|
|
+ if (((int16_T)(bcuSoc - SocFitChrg_Delay ) <=1 &&(int16_T)(bcuSoc - SocFitChrg_Delay ) >=-1 )||((int16_T)(bcuSoc - SocFitChrg_Delay ) <=-1000))
|
|
|
+ {
|
|
|
+
|
|
|
+ SocFitChrg = bcuSoc;
|
|
|
+ }
|
|
|
+ SocFitChrg_Delay = SocFitChrg;
|
|
|
+
|
|
|
+ //
|
|
|
+ if (fulFlg)
|
|
|
+ {
|
|
|
+ socd_pct_bcuSoc =1000;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ socd_pct_bcuSoc =(SocFitChrg > 999 ? 999 : SocFitChrg);
|
|
|
+ }
|
|
|
+ //printf("10-----x:[%d-%d-%d],y:[%d-%d-%d],bcusoc:%d,SocFitChrg:%d,socd_pct_bcuSoc:%d\n",x[0],x[1],x[2],y[0],y[1],y[2],bcuSoc,SocFitChrg,socd_pct_bcuSoc);
|
|
|
}
|
|
|
+ else
|
|
|
+ {
|
|
|
+
|
|
|
+ //
|
|
|
+ delSOC = ((int16_T) (socd_pct_battSoc0 - socd_pct_bcuSoc0) > 0 ? (socd_pct_battSoc0 - socd_pct_bcuSoc0) : (socd_pct_bcuSoc0 - socd_pct_battSoc0));
|
|
|
+ coinSoc =(int16_T)((socd_pct_battSoc0 < socd_pct_bcuSoc0 ? socd_pct_battSoc0 : socd_pct_bcuSoc0) - (delSOC > 50 ? 50 : delSOC));
|
|
|
+
|
|
|
+ x[0] = 0;
|
|
|
+ x[1] = (coinSoc > 0 ? (uint16_T)coinSoc : 0);
|
|
|
+ x[2] = socd_pct_battSoc0;
|
|
|
+ y[0] = 0;
|
|
|
+ y[1] = (coinSoc > 0 ? (uint16_T)coinSoc : 0);
|
|
|
+ y[2] = socd_pct_bcuSoc0;
|
|
|
+ SOC_LookUp( socd_pct_battSoc, &x[0], &y[0], &bcuSoc);
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
+ //
|
|
|
+ onceFlg_chrg = true;
|
|
|
+ if (onceFlg_dischrg)
|
|
|
+ {
|
|
|
+ SocFitdisChrg_Delay = 2000;
|
|
|
+ }
|
|
|
+ onceFlg_dischrg =false;
|
|
|
|
|
|
- /* End of Switch: '<S42>/Switch' */
|
|
|
-
|
|
|
- /* SignalConversion: '<S42>/Signal Conversion' incorporates:
|
|
|
- * Merge: '<S42>/Merge'
|
|
|
- * Merge: '<S6>/Merge'
|
|
|
- * UnitDelay: '<S42>/socfit_Delay'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcusocDelay'
|
|
|
- */
|
|
|
- SOC_DW.socd_pct_bcusocDelay_DSTATE = SOC_DW.socfit_Delay_DSTATE;
|
|
|
-
|
|
|
- /* End of Outputs for SubSystem: '<S6>/Subsystem3' */
|
|
|
- }
|
|
|
-
|
|
|
- /* End of If: '<S6>/If' */
|
|
|
-
|
|
|
- /* Abs: '<S6>/Abs2' incorporates:
|
|
|
- * Inport: '<Root>/sfmd_I_curr'
|
|
|
- */
|
|
|
- if (sfmd_I_curr < 0) {
|
|
|
- rtb_Saturation_k = (int16_T)-sfmd_I_curr;
|
|
|
- } else {
|
|
|
- rtb_Saturation_k = sfmd_I_curr;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Abs: '<S6>/Abs2' */
|
|
|
-
|
|
|
- /* RelationalOperator: '<S6>/Relational Operator8' incorporates:
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE_h = (rtb_Saturation_k < 10);
|
|
|
-
|
|
|
- /* Product: '<S35>/Product' incorporates:
|
|
|
- * UnitDelay: '<S23>/Frist'
|
|
|
- * UnitDelay: '<S35>/Time_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Time_Delay_DSTATE = (uint16_T)(SOC_DW.Frist_DSTATE_h ? (int32_T)
|
|
|
- rtb_Merge : 0);
|
|
|
-
|
|
|
- /* Sum: '<S32>/Add1' incorporates:
|
|
|
- * Abs: '<S32>/Abs1'
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- */
|
|
|
- rtb_Saturation_k = (int16_T)(socd_pct_battSoc -
|
|
|
- SOC_DW.socd_flg_EEsave_Delay_DSTATE);
|
|
|
-
|
|
|
- /* Abs: '<S32>/Abs1' */
|
|
|
- if (rtb_Saturation_k < 0) {
|
|
|
- rtb_Saturation_k = (int16_T)-rtb_Saturation_k;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Abs: '<S32>/Abs1' */
|
|
|
-
|
|
|
- /* RelationalOperator: '<S32>/Relational Operator7' incorporates:
|
|
|
- * Abs: '<S32>/Abs1'
|
|
|
- * Constant: '<S32>/Constant19'
|
|
|
- */
|
|
|
- socd_flg_EEsave = ((real_T)rtb_Saturation_k * 0.1 > 1.0);
|
|
|
-
|
|
|
- /* Switch: '<S32>/Switch6' incorporates:
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- * UnitDelay: '<S32>/socd_flg_EEsave_Delay'
|
|
|
- */
|
|
|
- if (socd_flg_EEsave) {
|
|
|
- SOC_DW.socd_flg_EEsave_Delay_DSTATE = socd_pct_battSoc;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Switch: '<S32>/Switch6' */
|
|
|
-
|
|
|
- /* SignalConversion: '<S6>/Signal Conversion1' incorporates:
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- */
|
|
|
- socd_pct_battSocEo = socd_pct_battSoc;
|
|
|
-
|
|
|
- /* Saturate: '<S1>/Saturation' incorporates:
|
|
|
- * Sum: '<S4>/Add1'
|
|
|
- */
|
|
|
- if (rtb_Add1_a >= 1000) {
|
|
|
- /* Saturate: '<S1>/Saturation' */
|
|
|
- socd_pct_ahSoc = 1000U;
|
|
|
- } else if (rtb_Add1_a <= 0) {
|
|
|
- /* Saturate: '<S1>/Saturation' */
|
|
|
- socd_pct_ahSoc = 0U;
|
|
|
- } else {
|
|
|
- /* Saturate: '<S1>/Saturation' */
|
|
|
- socd_pct_ahSoc = (uint16_T)rtb_Add1_a;
|
|
|
- }
|
|
|
-
|
|
|
- /* End of Saturate: '<S1>/Saturation' */
|
|
|
-
|
|
|
- /* SignalConversion: '<S12>/Signal Conversion2' */
|
|
|
- k1 = rtb_Divide[0];
|
|
|
-
|
|
|
- /* SignalConversion: '<S6>/Signal Conversion2' incorporates:
|
|
|
- * Merge: '<S6>/Merge'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcusocDelay'
|
|
|
- */
|
|
|
- socd_pct_bcuSoc = SOC_DW.socd_pct_bcusocDelay_DSTATE;
|
|
|
-
|
|
|
- /* SignalConversion: '<S6>/Signal Conversion3' incorporates:
|
|
|
- * Merge: '<S6>/Merge'
|
|
|
- * UnitDelay: '<S6>/socd_pct_bcusocDelay'
|
|
|
- */
|
|
|
- socd_pct_bcuSocEo = SOC_DW.socd_pct_bcusocDelay_DSTATE;
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S1>/FirstDelay' incorporates:
|
|
|
- * Constant: '<S1>/Constant'
|
|
|
- */
|
|
|
- SOC_DW.FirstDelay_DSTATE = false;
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S14>/Frist' incorporates:
|
|
|
- * Constant: '<S14>/Constant'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE = false;
|
|
|
-
|
|
|
- /* Update for UnitDelay: '<S23>/Frist' incorporates:
|
|
|
- * Constant: '<S23>/Constant'
|
|
|
- */
|
|
|
- SOC_DW.Frist_DSTATE_h = false;
|
|
|
-
|
|
|
- /* Update for SignalConversion generated from: '<S28>/Product1' incorporates:
|
|
|
- * Product: '<S19>/Product2'
|
|
|
- * Product: '<S27>/Product'
|
|
|
- * Sum: '<S27>/Add'
|
|
|
- * Sum: '<S27>/Add1'
|
|
|
- * UnitDelay: '<S13>/Up_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Up_Delay_DSTATE = rtb_Add1_h * rtb_Add_l +
|
|
|
- rtb_TmpSignalConversionAtProduc[1];
|
|
|
+
|
|
|
+ if ((int16_T)(bcuSoc - SocFitdisChrg_Delay ) > 1)
|
|
|
+ {
|
|
|
+ SOCfit_IfActionSubsystem1( bcuSoc, SocFitdisChrg_Delay, &SocFitdisChrg, 1);
|
|
|
+ }
|
|
|
+ if ((int16_T)(bcuSoc - SocFitdisChrg_Delay ) <-1 && (int16_T)(bcuSoc - SocFitdisChrg_Delay ) > -1000)
|
|
|
+ {
|
|
|
+ SOCfit_IfActionSubsystem2( bcuSoc, SocFitdisChrg_Delay, &SocFitdisChrg, 1);
|
|
|
+ }
|
|
|
+ if (((int16_T)(bcuSoc - SocFitdisChrg_Delay ) <=1 &&(int16_T)(bcuSoc - SocFitdisChrg_Delay ) >=-1 )||((int16_T)(bcuSoc - SocFitdisChrg_Delay ) <=-1000))
|
|
|
+ {
|
|
|
|
|
|
- /* Update for Switch: '<S14>/Switch1' incorporates:
|
|
|
- * Product: '<S18>/Product'
|
|
|
- * Sum: '<S18>/Add'
|
|
|
- * Sum: '<S18>/Add1'
|
|
|
- * UnitDelay: '<S12>/Up_Delay'
|
|
|
- */
|
|
|
- SOC_DW.Up_Delay_DSTATE_h = rtb_Add1 + k2 * deltaU;
|
|
|
+ SocFitdisChrg = bcuSoc;
|
|
|
+ }
|
|
|
+ SocFitdisChrg_Delay = SocFitdisChrg;
|
|
|
|
|
|
- /* Update for UnitDelay: '<S6>/First_Delay' incorporates:
|
|
|
- * Constant: '<S6>/Constant2'
|
|
|
- */
|
|
|
- SOC_DW.First_Delay_DSTATE = false;
|
|
|
|
|
|
- /* Update for UnitDelay: '<S6>/ihd_st_chrgSta_Delay' incorporates:
|
|
|
- * Inport: '<Root>/ihd_st_workStat'
|
|
|
- */
|
|
|
- SOC_DW.ihd_st_chrgSta_Delay_DSTATE = ihd_st_workStat;
|
|
|
+ socd_pct_bcuSoc = SocFitdisChrg;
|
|
|
+ //printf("11-----x:[%d-%d-%d],y:[%d-%d-%d],bcusoc:%d,socd_pct_bcuSoc:%d\n",x[0],x[1],x[2],y[0],y[1],y[2],bcuSoc,socd_pct_bcuSoc);
|
|
|
+
|
|
|
+ }
|
|
|
+ //
|
|
|
+ socd_pct_bcuSocEo = socd_pct_bcuSoc;
|
|
|
+ socd_pct_bcuSoc_Delay = socd_pct_bcuSoc;
|
|
|
+ FirstRun_SOC= false;
|
|
|
+
|
|
|
+}
|
|
|
|
|
|
- /* Update for UnitDelay: '<S6>/Unit Delay7' incorporates:
|
|
|
- * Saturate: '<S7>/Saturation'
|
|
|
- */
|
|
|
- SOC_DW.UnitDelay7_DSTATE = socd_pct_battSoc;
|
|
|
|
|
|
- /* Update for UnitDelay: '<S6>/First_Delay1' incorporates:
|
|
|
- * Constant: '<S6>/Constant12'
|
|
|
- */
|
|
|
- SOC_DW.First_Delay1_DSTATE = false;
|
|
|
+//-------------------------------------------------------------------------
|
|
|
+void docvmath(real_T soc ,real_T *docv)
|
|
|
+{
|
|
|
+ *docv = ((((((-2.8104E-13 * pow(soc, 7.0) + 1.0283E-10 * pow(soc, 6.0)) +
|
|
|
+ -1.5072E-8 * pow(soc, 5.0)) + 1.1295E-6 * pow(soc, 4.0)) +
|
|
|
+ -4.588E-5 * pow(soc, 3.0)) + soc * soc * 0.000993) +
|
|
|
+ -0.010548 * soc) + 0.04876;
|
|
|
}
|
|
|
-
|
|
|
-/* Model initialize function */
|
|
|
-void SOC_initialize(const char_T **rt_errorStatus)
|
|
|
+////
|
|
|
+void SOC_LookUp(uint16_T battsoc, uint16_T x[], uint16_T y[],uint16_T *bcusoc)
|
|
|
{
|
|
|
- RT_MODEL_SOC_T *const SOC_M = &(SOC_MdlrefDW.rtm);
|
|
|
-
|
|
|
- /* Registration code */
|
|
|
+ //
|
|
|
+ if (battsoc <= x[0])
|
|
|
+ {
|
|
|
+ *bcusoc = y[0];
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if (battsoc >= x[2])
|
|
|
+ {
|
|
|
+ *bcusoc = y[2];
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if (battsoc > x[0] && battsoc < x[1]) //(x-x0)*(y1-y0)/(x1-x0)+y0
|
|
|
+ {
|
|
|
|
|
|
- /* initialize error status */
|
|
|
- rtmSetErrorStatusPointer(SOC_M, rt_errorStatus);
|
|
|
- SOC_PrevZCX.Subsystem2_Trig_ZCE_k = POS_ZCSIG;
|
|
|
- SOC_PrevZCX.Subsystem2_Trig_ZCE = POS_ZCSIG;
|
|
|
+ *bcusoc = (uint16_T) ((real_T)((battsoc - x[0]) * 0.1) * (real_T)((y[1] - y[0]) * 0.1) /(real_T)((x[1] - x[0]) * 0.1) * 10)+ y[0];
|
|
|
+ //*bcusoc = (uint16_T)(((((uint16_T)(((uint16_T)div_repeat_u32((uint32_T)(uint16_T)(battsoc - x[0]) * (y[1] - y[0]),(uint16_T)(x[1] - x[0]), 3U) * 5U)>> 2) * 52429U) >> 4) + ((uint32_T)y[0] << 15)) >>15);
|
|
|
+ }
|
|
|
+ //
|
|
|
+ if (battsoc >= x[1] && battsoc < x[2]) //(x-x1)*(y2-y1)/(x2-x1)+y1
|
|
|
+ {
|
|
|
+ *bcusoc = (uint16_T) ((real_T)((battsoc - x[1]) * 0.1) * (real_T)((y[2] - y[1]) * 0.1) /(real_T)((x[2] - x[1]) * 0.1) * 10)+ y[1];
|
|
|
+ //*bcusoc = (uint16_T)(((((uint16_T)(((uint16_T)div_repeat_u32((uint32_T)(uint16_T)(battsoc - x[1]) * (y[2] - y[1]),(uint16_T)(x[2] - x[1]), 3U) * 5U)>> 2) * 52429U) >> 4) + ((uint32_T)y[1] << 15)) >>15);
|
|
|
+ }
|
|
|
}
|
|
|
+//-------------------------------------------------------------------------
|
|
|
|
|
|
-/*
|
|
|
- * File trailer for generated code.
|
|
|
- *
|
|
|
- * [EOF]
|
|
|
- */
|
|
|
+void SOCfit_IfActionSubsystem1(uint16_T SOC, uint16_T SOCfit_Delay, uint16_T *SOCfit, uint16_T m)
|
|
|
+{
|
|
|
+ if ((int16_T)(SOC - SOCfit_Delay) > m)
|
|
|
+ {
|
|
|
+ *SOCfit=SOCfit_Delay+m;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ *SOCfit=SOC;
|
|
|
+ }
|
|
|
+}
|
|
|
+//-------------------------------------------------------------------------
|
|
|
+void SOCfit_IfActionSubsystem2(uint16_T SOC, uint16_T SOCfit_Delay, uint16_T *SOCfit, uint16_T m)
|
|
|
+{
|
|
|
+ if ((int16_T)(SOC - SOCfit_Delay) < -m)
|
|
|
+ {
|
|
|
+ *SOCfit=SOCfit_Delay-m;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ *SOCfit=SOC;
|
|
|
+ }
|
|
|
+}
|