模型集成，没有优化参数

ARMCC/Makefile

@@ -10,22 +10,46 @@ THIRDPARTY_WAKAAMA_ENABLE   = n
 THIRDPARTY_ERCOAP_ENABLE    = y
 THIRDPARTY_TINYDTLS_ENABLE  = y
 THIRDPARTY_MBEDTLS_ENABLE   = y
-
+IQMATH_ENABLE = y
 CFLAGS_INC        +=  -I ../inc
 
 
 obj-y             += PLAT/project/$(TARGET)/apps/qx_app/src/app.o \
-		     		PLAT/project/$(TARGET)/apps/qx_app/src/bsp_custom.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/hal_module_adapter.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/sensor.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppSignal.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppFunc.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskMain.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskTcp.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskControl.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskUart.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskCan.o \
-					PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskGps.o 
-include $(TOP)/PLAT/tools/scripts/Makefile.rules
+PLAT/project/$(TARGET)/apps/qx_app/src/bsp_custom.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/hal_module_adapter.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/sensor.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppSignal.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppFunc.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskMain.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskTcp.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskControl.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskUart.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskCan.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/AppTaskGps.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/BCU.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/SOH.o \
+PLAT/project/$(TARGET)/apps/qx_app/src/SOC.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/BLC.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/div_nde_s32_floor.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/look1_is16lu16n16tu16_binlcase.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/look1_iu16lu16n16tu16_binlcase.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/LookUp_U16_U16.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_s32_loSR_sat.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_s32_sat.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_ssu32_sat.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_us32_sat.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_wide_s32.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_wide_u32.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_wide_su32.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/look1_binlxpw.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/INTERPOLATE_U16_U16.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_u32_hiSR.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/div_repeat_s16s32_floor.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/BINARYSEARCH_U16.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/div_nzp_repeat_u32.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/div_nzp_repeat_u32_ceiling.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/const_params.o \
+	PLAT/project/$(TARGET)/apps/qx_app/src/mul_u32_hiSR_near.o
+include $(TOP)/PLAT/tools/scripts/Makefile.rules 
 #enable wdt
 CFLAGS += -DWDT_FEATURE_ENABLE=1

inc/AppConfig.h

@@ -99,6 +99,15 @@ typedef struct _AppDataType
     UINT8  RelayControl;                //继电器控制
     UINT8  BattLock;                    //电池锁定状态
     UINT8  BattStolenFlag;              //电池被盗状态
+    UINT32 blcv_Q_totalCpE[28];         //累计均衡容量 读取量 数组最大28
+    UINT16 blcv_Q_reqCpE[28];           //均衡需求容量 读取量 数组最大28
+    UINT16 socd_pct_bcuSocE;            //电池显示SOC 读取量；
+    UINT16 socd_pct_battSocE;           //电池真实SOC 读取量；
+    UINT16 sohd_tm_chrgStartStatE;      //充电前静置时间读取量；
+    UINT8  sohd_flg_chrgEndE;           //充电结束标志位读取量；
+    UINT16 sohv_V_chrgStartStatE[28];   //充电开始时刻的单体电压（数组）读取量；
+    UINT16 sohd_Q_chrgE;                //充入容量读取量；
+    UINT16 sohv_Q_packCapArrE[10];     //10次整包容量（数组）读取量；
 }AppDataBody;
 typedef struct _AppDataHeader
 {

inc/AppSignal.h

@@ -11,6 +11,7 @@
 #include "AppConfig.h"
 #include "osasys.h"
 #include "queue.h"
+#include "bsp_custom.h"
 //declear the bool vars
 extern volatile BOOL NB_Fota_update_flag;
 extern volatile BOOL BMS_Fota_update_flag;
@@ -68,6 +69,7 @@ extern UINT8   PadInterrupt ;
 extern UINT16	battCellU[28];
 extern UINT16	minCellVol;
 extern UINT16	maxCellVol;
+extern UINT16   avrgCellVol;
 extern UINT16	battPackVol;
 extern UINT16	battI;
 extern UINT16	nbHwVersion;

inc/BCU.h

@@ -0,0 +1,207 @@
+/*
+ * File: BCU.h
+ *
+ * Code generated for Simulink model 'BCU'.
+ *
+ * Model version                  : 1.13
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:42 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BCU_h_
+#define RTW_HEADER_BCU_h_
+#ifndef BCU_COMMON_INCLUDES_
+#define BCU_COMMON_INCLUDES_
+#include "rtwtypes.h"
+#include "commontypedef.h"
+#include "AppSignal.h"
+#endif                                 /* BCU_COMMON_INCLUDES_ */
+
+#include "BCU_types.h"
+#define PROC_BCU_TASK_STACK_SIZE           (2048)
+typedef enum
+{
+    PROCESS_STATE_INIT = 0,
+    PROCESS_STATE_IDLE,
+    PROCESS_STATE_WORK,
+    PROCESS_STATE_SLEEP
+}process_Bcu;
+/* Child system includes */
+#include "SOH.h"
+#include "SOC.h"
+#include "BLC.h"
+
+/* Macros for accessing real-time model data structure */
+#ifndef rtmGetErrorStatus
+#define rtmGetErrorStatus(rtm)         ((rtm)->errorStatus)
+#endif
+
+#ifndef rtmSetErrorStatus
+#define rtmSetErrorStatus(rtm, val)    ((rtm)->errorStatus = (val))
+#endif
+
+#ifndef rtmGetErrorStatusPointer
+#define rtmGetErrorStatusPointer(rtm)  ((const char_T **)(&((rtm)->errorStatus)))
+#endif
+
+/* Block states (default storage) for system '<Root>' */
+typedef struct {
+  MdlrefDW_SOH_T SOH_InstanceData;     /* '<Root>/SOH' */
+  MdlrefDW_SOC_T SOC_InstanceData;     /* '<Root>/SOC' */
+  MdlrefDW_BLC_T BLC_InstanceData;     /* '<Root>/BLC' */
+} DW_BCU_T;
+
+/* Real-time Model Data Structure */
+struct tag_RTM_BCU_T {
+  const char_T *errorStatus;
+};
+
+/* Block states (default storage) */
+extern DW_BCU_T BCU_DW;
+
+/* Model entry point functions */
+extern void BCU_initialize(void);
+extern void BCU_step(void);
+extern void BCU_terminate(void);
+
+/* Exported data declaration */
+
+/* Declaration for custom storage class: ExportToFile */
+extern uint16_T blcv_Q_reqCpEi[28];    /* '<Root>/blcv_Q_reqCpEi' */
+
+/* ������������ ��ȡ�������飩�� */
+extern uint16_T blcv_Q_reqCpEo[28];    /* '<Root>/BLC' */
+
+/* ������������ д���������飩�� */
+extern uint32_T blcv_Q_totalCpEi[28];  /* '<Root>/blcv_Q_totalCpEi' */
+
+/* �ۼƾ������� ��ȡ�������飩�� */
+extern uint32_T blcv_Q_totalCpEo[28];  /* '<Root>/BLC' */
+
+/* �ۼƾ������� д���������飩�� */
+extern boolean_T blcv_flg_excute[28];  /* '<Root>/BLC' */
+
+/* ����ִ�������־λ �����飩 */
+extern int16_T ihd_I_curr;             /* '<Root>/ihd_I_curr' */
+
+/* ��ذ������� */
+extern int16_T ihd_T_bdtemp;           /* '<Root>/Constant' */
+extern int16_T ihd_T_modTMax;          /* '<Root>/ihd_T_modTMax' */
+
+/* ģ���¶���� */
+extern int16_T ihd_T_modTMin;          /* '<Root>/ihd_T_modTMin' */
+
+/* ģ���¶���С */
+extern uint16_T ihd_V_cellUAvrg;       /* '<Root>/ihd_V_cellUAvrg' */
+
+/* ��ص����ѹƽ���� */
+extern uint16_T ihd_V_cellUMax;        /* '<Root>/ihd_V_cellUMax' */
+
+/* ��ص����ѹ��� */
+extern uint16_T ihd_V_cellUMin;        /* '<Root>/ihd_V_cellUMin' */
+
+/* ��ص����ѹ��С�� */
+extern uint8_T ihd_st_fault;           /* '<Root>/ihd_st_fault' */
+
+/* ���ϵȼ� */
+extern uint8_T ihd_st_workStat;        /* '<Root>/ihd_st_workStat' */
+
+/* ��ع���״̬�� */
+extern uint32_T ihd_tm_parkTime;       /* '<Root>/ihd_tm_packTime' */
+
+/* פ��ʱ�䣻 */
+extern int16_T ihv_T_modT[6];          /* '<Root>/ihv_T_modT' */
+
+/* ģ���¶ȣ����飩 */
+extern uint16_T ihv_V_cellU[28];       /* '<Root>/ihv_V_cellU' */
+
+/* ��ص����ѹ�����飩�� */
+extern uint16_T socd_pct_ahSoc;        /* '<Root>/SOC' */
+
+/* ��ʱSOC�� */
+extern uint16_T socd_pct_battSoc;      /* '<Root>/SOC' */
+
+/* �����ʵSOC�� */
+extern uint16_T socd_pct_battSocEi;    /* '<Root>/socd_pct_battSocEi' */
+
+/* �����ʵSOC ��ȡ���� */
+extern uint16_T socd_pct_battSocEo;    /* '<Root>/SOC' */
+
+/* �����ʵSOC д������ */
+extern uint16_T socd_pct_bcuSoc;       /* '<Root>/SOC' */
+
+/* �����ʾSOC�� */
+extern uint16_T socd_pct_bcuSocEi;     /* '<Root>/socd_pct_bcuSocEi' */
+
+/* �����ʾSOC��ȡ���� */
+extern uint16_T socd_pct_bcuSocEo;     /* '<Root>/SOC' */
+
+/* �����ʾSOCд������ */
+extern uint16_T sohd_Q_chrgEi;         /* '<Root>/sohd_Q_chrgEi ' */
+
+/* ����������ȡ���� */
+extern uint16_T sohd_Q_chrgEo;         /* '<Root>/SOH' */
+
+/* ������������� */
+extern boolean_T sohd_flg_chrgEndEi;   /* '<Root>/sohd_flg_chrgEndEi ' */
+
+/* ��������־λ��ȡ���� */
+extern boolean_T sohd_flg_chrgEndEo;   /* '<Root>/SOH' */
+
+/* ��������־λд������ */
+extern uint16_T sohd_pct_bcuSoh;       /* '<Root>/SOH' */
+
+/* ���SOH�� */
+extern uint16_T sohd_tm_chrgStartStatEi;/* '<Root>/sohd_tm_chrgStartStatEi ' */
+
+/* ���ǰ����ʱ���ȡ���� */
+extern uint16_T sohd_tm_chrgStartStatEo;/* '<Root>/SOH' */
+
+/* ���ǰ����ʱ��д������ */
+extern uint16_T sohv_Q_cellCap[28];    /* '<Root>/SOH' */
+
+/* ������������� */
+extern uint16_T sohv_Q_packCapArrEi[10];/* '<Root>/sohv_Q_packCapArrEi ' */
+
+/* 10���������������飩��ȡ���� */
+extern uint16_T sohv_Q_packCapArrEo[10];/* '<Root>/SOH' */
+
+/* 10���������������飩д������ */
+extern uint16_T sohv_V_chrgStartStatEi[28];/* '<Root>/sohv_V_chrgStartStatEi ' */
+
+/* ��翪ʼʱ�̵ĵ����ѹ�����飩��ȡ���� */
+extern uint16_T sohv_V_chrgStartStatEo[28];/* '<Root>/SOH' */
+
+/* ��翪ʼʱ�̵ĵ����ѹ�����飩д������ */
+
+/* Real-time Model object */
+extern RT_MODEL_BCU_T *const BCU_M;
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model.  The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model.  For example,
+ *
+ * hilite_system('<S3>')    - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'BCU'
+ */
+#endif                                 /* RTW_HEADER_BCU_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BCU_private.h

@@ -0,0 +1,72 @@
+/*
+ * File: BCU_private.h
+ *
+ * Code generated for Simulink model 'BCU'.
+ *
+ * Model version                  : 1.13
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:42 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BCU_private_h_
+#define RTW_HEADER_BCU_private_h_
+#include "rtwtypes.h"
+#ifndef UCHAR_MAX
+#include <limits.h>
+#endif
+
+#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
+#error Code was generated for compiler with different sized uchar/char. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
+#error Code was generated for compiler with different sized ushort/short. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized uint/int. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized ulong/long. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+#endif                                 /* RTW_HEADER_BCU_private_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BCU_types.h

@@ -0,0 +1,30 @@
+/*
+ * File: BCU_types.h
+ *
+ * Code generated for Simulink model 'BCU'.
+ *
+ * Model version                  : 1.13
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:42 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BCU_types_h_
+#define RTW_HEADER_BCU_types_h_
+
+/* Model Code Variants */
+
+/* Forward declaration for rtModel */
+typedef struct tag_RTM_BCU_T RT_MODEL_BCU_T;
+
+#endif                                 /* RTW_HEADER_BCU_types_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BINARYSEARCH_U16.h

@@ -0,0 +1,24 @@
+/*
+ * File: BINARYSEARCH_U16.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_BINARYSEARCH_U16_h_
+#define RTW_HEADER_BINARYSEARCH_U16_h_
+#include "rtwtypes.h"
+
+void BINARYSEARCH_U16(uint32_T *piLeft, uint32_T *piRght, uint16_T u, const
+                      uint16_T *pData, uint32_T iHi);
+
+#endif                                 /* RTW_HEADER_BINARYSEARCH_U16_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BLC.h

@@ -0,0 +1,153 @@
+/*
+ * File: BLC.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:13 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BLC_h_
+#define RTW_HEADER_BLC_h_
+#include <string.h>
+#ifndef BLC_COMMON_INCLUDES_
+#define BLC_COMMON_INCLUDES_
+#include "rtwtypes.h"
+#endif                                 /* BLC_COMMON_INCLUDES_ */
+
+#include "BLC_types.h"
+
+/* Block signals for model 'BLC' */
+typedef struct {
+  uint32_T Merge1[28];                 /* '<S2>/Merge1' */
+  uint16_T blcn_Q_reqCpNow_j[28];      /* '<S6>/Chart' */
+  uint16_T blcn_Q_impleCp[28];         /* '<S5>/Chart' */
+  uint16_T Merge[28];                  /* '<S2>/Merge' */
+  boolean_T blcn_flg_stop[28];         /* '<S7>/Chart' */
+  boolean_T blcn_flg_blcable[28];      /* '<S5>/Chart' */
+  boolean_T blcn_flg_pause[28];        /* '<S4>/Chart' */
+} B_BLC_c_T;
+
+/* Block states (default storage) for model 'BLC' */
+typedef struct {
+  uint32_T blcCap[28];                 /* '<S5>/Chart' */
+  uint16_T UnitDelay_DSTATE[28];       /* '<S1>/Unit Delay' */
+  uint16_T QL;                         /* '<S6>/Chart1' */
+  boolean_T UnitDelay1_DSTATE;         /* '<S1>/Unit Delay1' */
+  uint8_T i_close;                     /* '<S4>/Chart' */
+  uint8_T i_open;                      /* '<S4>/Chart' */
+  boolean_T FristFlg;                  /* '<S6>/Chart1' */
+  boolean_T FristFlg_b;                /* '<S6>/Chart' */
+} DW_BLC_f_T;
+
+/* Real-time Model Data Structure */
+struct tag_RTM_BLC_T {
+  const char_T **errorStatus;
+};
+
+typedef struct {
+  B_BLC_c_T rtb;
+  DW_BLC_f_T rtdw;
+  RT_MODEL_BLC_T rtm;
+} MdlrefDW_BLC_T;
+
+/* Model reference registration function */
+extern void BLC_initialize(const char_T **rt_errorStatus, RT_MODEL_BLC_T *const
+  BLC_M);
+extern void BLC_Init(DW_BLC_f_T *localDW);
+extern void BLC(B_BLC_c_T *localB, DW_BLC_f_T *localDW);
+
+/* Exported data declaration */
+
+/* Declaration for custom storage class: ExportToFile */
+extern uint16_T blcv_Q_reqCpEi[28];
+
+/* 均衡需求容量 读取量（数组）； */
+extern uint16_T blcv_Q_reqCpEo[28];    /* '<S5>/Add' */
+
+/* 均衡需求容量 写入量（数组）； */
+extern uint32_T blcv_Q_totalCpEi[28];
+
+/* 累计均衡容量 读取量（数组）； */
+extern uint32_T blcv_Q_totalCpEo[28];  /* '<S5>/Add1' */
+
+/* 累计均衡容量 写入量（数组）； */
+extern boolean_T blcv_flg_excute[28];  /* '<S5>/Chart' */
+
+/* 均衡执行请求标志位 （数组） */
+extern int16_T ihd_T_bdtemp;
+extern uint16_T ihd_V_cellUMin;
+
+/* 电池单体电压最小； */
+extern uint8_T ihd_st_fault;
+
+/* 故障等级 */
+extern uint32_T ihd_tm_parkTime;
+
+/* 驻车时间； */
+extern uint16_T ihv_V_cellU[28];
+
+/* 电池单体电压（数组）； */
+extern uint16_T sohv_Q_cellCap[28];
+
+/* 充入容量写入量； */
+
+/*-
+ * These blocks were eliminated from the model due to optimizations:
+ *
+ * Block '<S1>/Display' : Unused code path elimination
+ * Block '<S1>/Display1' : Unused code path elimination
+ * Block '<S1>/Display2' : Unused code path elimination
+ * Block '<S1>/Display3' : Unused code path elimination
+ * Block '<S1>/Display4' : Unused code path elimination
+ * Block '<S3>/Display' : Unused code path elimination
+ * Block '<S5>/Display' : Unused code path elimination
+ * Block '<S5>/Scope' : Unused code path elimination
+ * Block '<S6>/Display' : Unused code path elimination
+ * Block '<S6>/Display2' : Unused code path elimination
+ */
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model.  The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model.  For example,
+ *
+ * hilite_system('<S3>')    - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'BLC'
+ * '<S1>'   : 'BLC/Subsystem'
+ * '<S2>'   : 'BLC/Subsystem/EE'
+ * '<S3>'   : 'BLC/Subsystem/Enalbe'
+ * '<S4>'   : 'BLC/Subsystem/pause'
+ * '<S5>'   : 'BLC/Subsystem/record'
+ * '<S6>'   : 'BLC/Subsystem/reqCpNow_Count'
+ * '<S7>'   : 'BLC/Subsystem/stop'
+ * '<S8>'   : 'BLC/Subsystem/EE/If Action Subsystem'
+ * '<S9>'   : 'BLC/Subsystem/EE/If Action Subsystem1'
+ * '<S10>'  : 'BLC/Subsystem/EE/Subsystem'
+ * '<S11>'  : 'BLC/Subsystem/pause/Chart'
+ * '<S12>'  : 'BLC/Subsystem/record/Chart'
+ * '<S13>'  : 'BLC/Subsystem/reqCpNow_Count/Chart'
+ * '<S14>'  : 'BLC/Subsystem/reqCpNow_Count/Chart1'
+ * '<S15>'  : 'BLC/Subsystem/stop/Chart'
+ */
+#endif                                 /* RTW_HEADER_BLC_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BLC_private.h

@@ -0,0 +1,105 @@
+/*
+ * File: BLC_private.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:13 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BLC_private_h_
+#define RTW_HEADER_BLC_private_h_
+#include "rtwtypes.h"
+#ifndef UCHAR_MAX
+#include <limits.h>
+#endif
+
+#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
+#error Code was generated for compiler with different sized uchar/char. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
+#error Code was generated for compiler with different sized ushort/short. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized uint/int. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized ulong/long. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+/* Macros for accessing real-time model data structure */
+#ifndef rtmGetErrorStatus
+#define rtmGetErrorStatus(rtm)         (*((rtm)->errorStatus))
+#endif
+
+#ifndef rtmSetErrorStatus
+#define rtmSetErrorStatus(rtm, val)    (*((rtm)->errorStatus) = (val))
+#endif
+
+#ifndef rtmGetErrorStatusPointer
+#define rtmGetErrorStatusPointer(rtm)  (rtm)->errorStatus
+#endif
+
+#ifndef rtmSetErrorStatusPointer
+#define rtmSetErrorStatusPointer(rtm, val) ((rtm)->errorStatus = (val))
+#endif
+
+extern const uint16_T rtCP_pooled_neXCembKU1Do[13];
+extern const uint16_T rtCP_pooled_Pg3wA7d95Txu[13];
+
+#define rtCP_uDLookupTable1_bp01Data   rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S6>/1-D Lookup Table1'
+                                                                  */
+#define rtCP_uDLookupTable_bp01Data    rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S6>/1-D Lookup Table'
+                                                                  */
+#define rtCP_uDLookupTable1_tableData  rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S6>/1-D Lookup Table1'
+                                                                  */
+#define rtCP_uDLookupTable_tableData   rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S6>/1-D Lookup Table'
+                                                                  */
+#endif                                 /* RTW_HEADER_BLC_private_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/BLC_types.h

@@ -0,0 +1,30 @@
+/*
+ * File: BLC_types.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:13 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_BLC_types_h_
+#define RTW_HEADER_BLC_types_h_
+
+/* Model Code Variants */
+
+/* Forward declaration for rtModel */
+typedef struct tag_RTM_BLC_T RT_MODEL_BLC_T;
+
+#endif                                 /* RTW_HEADER_BLC_types_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/INTERPOLATE_U16_U16.h

@@ -0,0 +1,24 @@
+/*
+ * File: INTERPOLATE_U16_U16.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_INTERPOLATE_U16_U16_h_
+#define RTW_HEADER_INTERPOLATE_U16_U16_h_
+#include "rtwtypes.h"
+
+void INTERPOLATE_U16_U16(uint16_T *pY, uint16_T yL, uint16_T yR, uint16_T x,
+  uint16_T xL, uint16_T xR);
+
+#endif                                 /* RTW_HEADER_INTERPOLATE_U16_U16_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/LookUp_U16_U16.h

@@ -0,0 +1,24 @@
+/*
+ * File: LookUp_U16_U16.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_LookUp_U16_U16_h_
+#define RTW_HEADER_LookUp_U16_U16_h_
+#include "rtwtypes.h"
+
+void LookUp_U16_U16(uint16_T *pY, const uint16_T *pYData, uint16_T u, const
+                    uint16_T *pUData, uint32_T iHi);
+
+#endif                                 /* RTW_HEADER_LookUp_U16_U16_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOC.h

@@ -0,0 +1,212 @@
+/*
+ * File: SOC.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOC_h_
+#define RTW_HEADER_SOC_h_
+#include <math.h>
+#ifndef SOC_COMMON_INCLUDES_
+#define SOC_COMMON_INCLUDES_
+#include "rtwtypes.h"
+#endif                                 /* SOC_COMMON_INCLUDES_ */
+
+#include "SOC_types.h"
+
+/* Block signals for model 'SOC' */
+typedef struct {
+  uint16_T Switch;                     /* '<S5>/Switch' */
+  uint16_T Divide;                     /* '<S5>/Divide' */
+  uint16_T Merge;                      /* '<S2>/Merge' */
+  uint16_T Merge1;                     /* '<S2>/Merge1' */
+} B_SOC_c_T;
+
+/* Block states (default storage) for model 'SOC' */
+typedef struct {
+  real_T UnitDelay_DSTATE;             /* '<S11>/Unit Delay' */
+  real_T UnitDelay_DSTATE_c;           /* '<S14>/Unit Delay' */
+  real_T UnitDelay1_DSTATE[4];         /* '<S11>/Unit Delay1' */
+  real_T UnitDelay_DSTATE_o;           /* '<S12>/Unit Delay' */
+  real_T UnitDelay_DSTATE_e;           /* '<S23>/Unit Delay' */
+  real_T UnitDelay1_DSTATE_j[4];       /* '<S12>/Unit Delay1' */
+  real_T UnitDelay2_DSTATE;            /* '<S12>/Unit Delay2' */
+  real_T UnitDelay1_DSTATE_h;          /* '<S23>/Unit Delay1' */
+  real_T UnitDelay3_DSTATE[2];         /* '<S12>/Unit Delay3' */
+  real_T UnitDelay2_DSTATE_k;          /* '<S11>/Unit Delay2' */
+  real_T UnitDelay1_DSTATE_l;          /* '<S14>/Unit Delay1' */
+  real_T UnitDelay3_DSTATE_g[2];       /* '<S11>/Unit Delay3' */
+  real_T Divide_DWORK4;                /* '<S17>/Divide' */
+  real_T Divide_DWORK4_c;              /* '<S26>/Divide' */
+  int32_T UnitDelay1_DSTATE_b;         /* '<S4>/Unit Delay1' */
+  uint16_T UnitDelay_DSTATE_i;         /* '<S33>/Unit Delay' */
+  uint16_T UnitDelay_DSTATE_l;         /* '<S45>/Unit Delay' */
+  uint16_T UnitDelay_DSTATE_h;         /* '<S43>/Unit Delay' */
+  uint16_T UnitDelay7_DSTATE;          /* '<S6>/Unit Delay7' */
+  uint16_T UnitDelay3_DSTATE_l;        /* '<S6>/Unit Delay3' */
+  uint16_T UnitDelay6_DSTATE;          /* '<S6>/Unit Delay6' */
+  uint16_T UnitDelay4_DSTATE;          /* '<S6>/Unit Delay4' */
+  uint16_T UnitDelay3_DSTATE_p;        /* '<S32>/Unit Delay3' */
+  uint16_T UnitDelay1_DSTATE_o;        /* '<S44>/Unit Delay1' */
+  uint16_T UnitDelay1_DSTATE_i;        /* '<S42>/Unit Delay1' */
+  uint16_T UnitDelay_DSTATE_b;         /* '<S41>/Unit Delay' */
+  uint8_T UnitDelay_DSTATE_m;          /* '<S38>/Unit Delay' */
+  uint8_T UnitDelay1_DSTATE_a;         /* '<S6>/Unit Delay1' */
+  uint8_T UnitDelay2_DSTATE_d;         /* '<S6>/Unit Delay2' */
+  boolean_T UnitDelay_DSTATE_et;       /* '<S1>/Unit Delay' */
+  boolean_T UnitDelay1_DSTATE_c;       /* '<S1>/Unit Delay1' */
+  boolean_T UnitDelay_DSTATE_j;        /* '<S6>/Unit Delay' */
+  boolean_T UnitDelay5_DSTATE;         /* '<S6>/Unit Delay5' */
+  boolean_T UnitDelay_DSTATE_cu;       /* '<S44>/Unit Delay' */
+  boolean_T UnitDelay_DSTATE_iz;       /* '<S42>/Unit Delay' */
+} DW_SOC_f_T;
+
+/* Real-time Model Data Structure */
+struct tag_RTM_SOC_T {
+  const char_T **errorStatus;
+};
+
+typedef struct {
+  B_SOC_c_T rtb;
+  DW_SOC_f_T rtdw;
+  RT_MODEL_SOC_T rtm;
+} MdlrefDW_SOC_T;
+
+/* Model reference registration function */
+extern void SOC_initialize(const char_T **rt_errorStatus, RT_MODEL_SOC_T *const
+  SOC_M);
+extern void SOC_MATLABFunction(real_T rtu_x, real_T *rty_y);
+extern void SOC_Init(DW_SOC_f_T *localDW);
+extern void SOC(B_SOC_c_T *localB, DW_SOC_f_T *localDW);
+
+/* Exported data declaration */
+
+/* Declaration for custom storage class: ExportToFile */
+extern int16_T ihd_I_curr;
+
+/* 电池包电流； */
+extern uint16_T ihd_V_cellUAvrg;
+
+/* 电池单体电压平均； */
+extern uint16_T ihd_V_cellUMax;
+
+/* 电池单体电压最大； */
+extern uint16_T ihd_V_cellUMin;
+
+/* 电池单体电压最小； */
+extern uint8_T ihd_st_workStat;
+
+/* 电池工作状态； */
+extern uint32_T ihd_tm_parkTime;
+
+/* 驻车时间； */
+extern uint16_T socd_pct_ahSoc;        /* '<S4>/Saturation' */
+
+/* 安时SOC； */
+extern uint16_T socd_pct_battSoc;      /* '<S6>/Signal Conversion' */
+
+/* 电池真实SOC； */
+extern uint16_T socd_pct_battSocEi;
+
+/* 电池真实SOC 读取量； */
+extern uint16_T socd_pct_battSocEo;    /* '<S6>/Signal Conversion1' */
+
+/* 电池真实SOC 写入量； */
+extern uint16_T socd_pct_bcuSoc;       /* '<S6>/Signal Conversion2' */
+
+/* 电池显示SOC； */
+extern uint16_T socd_pct_bcuSocEi;
+
+/* 电池显示SOC读取量； */
+extern uint16_T socd_pct_bcuSocEo;     /* '<S6>/Signal Conversion3' */
+
+/* 电池显示SOC写入量； */
+extern uint16_T sohd_pct_bcuSoh;
+
+/* 电池SOH； */
+
+/*-
+ * These blocks were eliminated from the model due to optimizations:
+ *
+ * Block '<S18>/Display' : Unused code path elimination
+ * Block '<S27>/Display' : Unused code path elimination
+ * Block '<S4>/Scope' : Unused code path elimination
+ */
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model.  The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model.  For example,
+ *
+ * hilite_system('<S3>')    - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'SOC'
+ * '<S1>'   : 'SOC/SOC'
+ * '<S2>'   : 'SOC/SOC/EEcheck'
+ * '<S3>'   : 'SOC/SOC/EKF'
+ * '<S4>'   : 'SOC/SOC/EKF1'
+ * '<S5>'   : 'SOC/SOC/Inti_correct'
+ * '<S6>'   : 'SOC/SOC/bcusoc'
+ * '<S7>'   : 'SOC/SOC/estSOC'
+ * '<S8>'   : 'SOC/SOC/EEcheck/If Action Subsystem'
+ * '<S9>'   : 'SOC/SOC/EEcheck/If Action Subsystem1'
+ * '<S10>'  : 'SOC/SOC/EEcheck/Subsystem'
+ * '<S11>'  : 'SOC/SOC/EKF/EFKmax'
+ * '<S12>'  : 'SOC/SOC/EKF/EFKmin'
+ * '<S13>'  : 'SOC/SOC/EKF/EKF'
+ * '<S14>'  : 'SOC/SOC/EKF/EFKmax/初始'
+ * '<S15>'  : 'SOC/SOC/EKF/EFKmax/协方差更新'
+ * '<S16>'  : 'SOC/SOC/EKF/EFKmax/协方差计算'
+ * '<S17>'  : 'SOC/SOC/EKF/EFKmax/卡尔曼增益'
+ * '<S18>'  : 'SOC/SOC/EKF/EFKmax/状态修正'
+ * '<S19>'  : 'SOC/SOC/EKF/EFKmax/状态更新'
+ * '<S20>'  : 'SOC/SOC/EKF/EFKmax/电池参数'
+ * '<S21>'  : 'SOC/SOC/EKF/EFKmax/矩阵计算'
+ * '<S22>'  : 'SOC/SOC/EKF/EFKmax/矩阵计算/MATLAB Function'
+ * '<S23>'  : 'SOC/SOC/EKF/EFKmin/初始'
+ * '<S24>'  : 'SOC/SOC/EKF/EFKmin/协方差更新'
+ * '<S25>'  : 'SOC/SOC/EKF/EFKmin/协方差计算'
+ * '<S26>'  : 'SOC/SOC/EKF/EFKmin/卡尔曼增益'
+ * '<S27>'  : 'SOC/SOC/EKF/EFKmin/状态修正'
+ * '<S28>'  : 'SOC/SOC/EKF/EFKmin/状态更新'
+ * '<S29>'  : 'SOC/SOC/EKF/EFKmin/电池参数'
+ * '<S30>'  : 'SOC/SOC/EKF/EFKmin/矩阵计算'
+ * '<S31>'  : 'SOC/SOC/EKF/EFKmin/矩阵计算/MATLAB Function'
+ * '<S32>'  : 'SOC/SOC/bcusoc/SOCfit'
+ * '<S33>'  : 'SOC/SOC/bcusoc/keep'
+ * '<S34>'  : 'SOC/SOC/bcusoc/SOCfit/If Action Subsystem'
+ * '<S35>'  : 'SOC/SOC/bcusoc/SOCfit/If Action Subsystem1'
+ * '<S36>'  : 'SOC/SOC/bcusoc/SOCfit/If Action Subsystem2'
+ * '<S37>'  : 'SOC/SOC/estSOC/If Action Subsystem2'
+ * '<S38>'  : 'SOC/SOC/estSOC/Time++'
+ * '<S39>'  : 'SOC/SOC/estSOC/chrgCCV'
+ * '<S40>'  : 'SOC/SOC/estSOC/disChrgCCV'
+ * '<S41>'  : 'SOC/SOC/estSOC/chrgCCV/Subsystem'
+ * '<S42>'  : 'SOC/SOC/estSOC/chrgCCV/Subsystem2'
+ * '<S43>'  : 'SOC/SOC/estSOC/chrgCCV/keep'
+ * '<S44>'  : 'SOC/SOC/estSOC/disChrgCCV/Subsystem2'
+ * '<S45>'  : 'SOC/SOC/estSOC/disChrgCCV/keep'
+ */
+#endif                                 /* RTW_HEADER_SOC_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOC_private.h

@@ -0,0 +1,174 @@
+/*
+ * File: SOC_private.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOC_private_h_
+#define RTW_HEADER_SOC_private_h_
+#include "rtwtypes.h"
+#ifndef UCHAR_MAX
+#include <limits.h>
+#endif
+
+#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
+#error Code was generated for compiler with different sized uchar/char. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
+#error Code was generated for compiler with different sized ushort/short. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized uint/int. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized ulong/long. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+/* Macros for accessing real-time model data structure */
+#ifndef rtmGetErrorStatus
+#define rtmGetErrorStatus(rtm)         (*((rtm)->errorStatus))
+#endif
+
+#ifndef rtmSetErrorStatus
+#define rtmSetErrorStatus(rtm, val)    (*((rtm)->errorStatus) = (val))
+#endif
+
+#ifndef rtmGetErrorStatusPointer
+#define rtmGetErrorStatusPointer(rtm)  (rtm)->errorStatus
+#endif
+
+#ifndef rtmSetErrorStatusPointer
+#define rtmSetErrorStatusPointer(rtm, val) ((rtm)->errorStatus = (val))
+#endif
+
+extern const real_T rtCP_pooled_2yqyybnjRkAg[13];
+extern const real_T rtCP_pooled_Hq33G5zkPPgT[13];
+extern const real_T rtCP_pooled_4Oms9Dl3djxK[13];
+extern const real_T rtCP_pooled_ygMHmGen2OIb[13];
+extern const real_T rtCP_pooled_6SXVB9Ymnskr[13];
+extern const int16_T rtCP_pooled_5IPKsXGYnKyg[4];
+extern const int16_T rtCP_pooled_9BXJPVWA4BJI[3];
+extern const uint16_T rtCP_pooled_neXCembKU1Do[13];
+extern const uint16_T rtCP_pooled_qce4hcBQN8fp[4];
+extern const uint16_T rtCP_pooled_J4vL4j1Fk1zG[3];
+extern const uint16_T rtCP_pooled_Pg3wA7d95Txu[13];
+
+#define rtCP_SOCRp_tableData           rtCP_pooled_2yqyybnjRkAg  /* Computed Parameter: rtCP_SOCRp_tableData
+                                                                  * Referenced by: '<S20>/SOC-Rp'
+                                                                  */
+#define rtCP_SOCRp_bp01Data            rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCRp_bp01Data
+                                                                  * Referenced by: '<S20>/SOC-Rp'
+                                                                  */
+#define rtCP_SOCC_tableData            rtCP_pooled_4Oms9Dl3djxK  /* Computed Parameter: rtCP_SOCC_tableData
+                                                                  * Referenced by: '<S20>/SOC-C'
+                                                                  */
+#define rtCP_SOCC_bp01Data             rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCC_bp01Data
+                                                                  * Referenced by: '<S20>/SOC-C'
+                                                                  */
+#define rtCP_SOCRp_tableData_b         rtCP_pooled_2yqyybnjRkAg  /* Computed Parameter: rtCP_SOCRp_tableData_b
+                                                                  * Referenced by: '<S29>/SOC-Rp'
+                                                                  */
+#define rtCP_SOCRp_bp01Data_a          rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCRp_bp01Data_a
+                                                                  * Referenced by: '<S29>/SOC-Rp'
+                                                                  */
+#define rtCP_SOCC_tableData_l          rtCP_pooled_4Oms9Dl3djxK  /* Computed Parameter: rtCP_SOCC_tableData_l
+                                                                  * Referenced by: '<S29>/SOC-C'
+                                                                  */
+#define rtCP_SOCC_bp01Data_o           rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCC_bp01Data_o
+                                                                  * Referenced by: '<S29>/SOC-C'
+                                                                  */
+#define rtCP_SOCOCV_tableData          rtCP_pooled_ygMHmGen2OIb  /* Computed Parameter: rtCP_SOCOCV_tableData
+                                                                  * Referenced by: '<S29>/SOC-OCV'
+                                                                  */
+#define rtCP_SOCOCV_bp01Data           rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCOCV_bp01Data
+                                                                  * Referenced by: '<S29>/SOC-OCV'
+                                                                  */
+#define rtCP_SOCRo_tableData           rtCP_pooled_6SXVB9Ymnskr  /* Computed Parameter: rtCP_SOCRo_tableData
+                                                                  * Referenced by: '<S29>/SOC-Ro'
+                                                                  */
+#define rtCP_SOCRo_bp01Data            rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCRo_bp01Data
+                                                                  * Referenced by: '<S29>/SOC-Ro'
+                                                                  */
+#define rtCP_SOCOCV_tableData_c        rtCP_pooled_ygMHmGen2OIb  /* Computed Parameter: rtCP_SOCOCV_tableData_c
+                                                                  * Referenced by: '<S20>/SOC-OCV'
+                                                                  */
+#define rtCP_SOCOCV_bp01Data_a         rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCOCV_bp01Data_a
+                                                                  * Referenced by: '<S20>/SOC-OCV'
+                                                                  */
+#define rtCP_SOCRo_tableData_n         rtCP_pooled_6SXVB9Ymnskr  /* Computed Parameter: rtCP_SOCRo_tableData_n
+                                                                  * Referenced by: '<S20>/SOC-Ro'
+                                                                  */
+#define rtCP_SOCRo_bp01Data_c          rtCP_pooled_Hq33G5zkPPgT  /* Computed Parameter: rtCP_SOCRo_bp01Data_c
+                                                                  * Referenced by: '<S20>/SOC-Ro'
+                                                                  */
+#define rtCP_uDLookupTable_bp01Data    rtCP_pooled_5IPKsXGYnKyg  /* Expression: socm_I_chrgCor
+                                                                  * Referenced by: '<S39>/1-D Lookup Table'
+                                                                  */
+#define rtCP_uDLookupTable_bp01Data_g  rtCP_pooled_9BXJPVWA4BJI  /* Expression: socm_I_disChrgCor
+                                                                  * Referenced by: '<S40>/1-D Lookup Table'
+                                                                  */
+#define rtCP_OCVSOC_bp01Data           rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S8>/OCV-SOC'
+                                                                  */
+#define rtCP_OCVSOC_bp01Data_b         rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S5>/OCV-SOC'
+                                                                  */
+#define rtCP_uDLookupTable_tableData   rtCP_pooled_qce4hcBQN8fp  /* Expression: socm_V_chrgCor
+                                                                  * Referenced by: '<S39>/1-D Lookup Table'
+                                                                  */
+#define rtCP_uDLookupTable_tableData_b rtCP_pooled_J4vL4j1Fk1zG  /* Expression: socm_V_disChrgCor
+                                                                  * Referenced by: '<S40>/1-D Lookup Table'
+                                                                  */
+#define rtCP_OCVSOC_tableData          rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S8>/OCV-SOC'
+                                                                  */
+#define rtCP_OCVSOC_tableData_b        rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S5>/OCV-SOC'
+                                                                  */
+#endif                                 /* RTW_HEADER_SOC_private_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOC_types.h

@@ -0,0 +1,30 @@
+/*
+ * File: SOC_types.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOC_types_h_
+#define RTW_HEADER_SOC_types_h_
+
+/* Model Code Variants */
+
+/* Forward declaration for rtModel */
+typedef struct tag_RTM_SOC_T RT_MODEL_SOC_T;
+
+#endif                                 /* RTW_HEADER_SOC_types_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOH.h

@@ -0,0 +1,164 @@
+/*
+ * File: SOH.h
+ *
+ * Code generated for Simulink model 'SOH'.
+ *
+ * Model version                  : 1.14
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:32 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOH_h_
+#define RTW_HEADER_SOH_h_
+#ifndef SOH_COMMON_INCLUDES_
+#define SOH_COMMON_INCLUDES_
+#include "rtwtypes.h"
+#endif                                 /* SOH_COMMON_INCLUDES_ */
+
+#include "SOH_types.h"
+
+/* Block signals for model 'SOH' */
+typedef struct {
+  uint16_T Divide1[28];                /* '<S13>/Divide1' */
+  uint16_T Add2;                       /* '<S13>/Add2' */
+  uint16_T Qavrg;                      /* '<S3>/Chart' */
+  uint16_T sohn_Q_packCapArrEo[10];    /* '<S3>/Chart' */
+  uint16_T Divide1_c;                  /* '<S11>/Divide1' */
+} B_SOH_c_T;
+
+/* Block states (default storage) for model 'SOH' */
+typedef struct {
+  int32_T UnitDelay_DSTATE;            /* '<S11>/Unit Delay' */
+  uint16_T UnitDelay2_DSTATE;          /* '<S6>/Unit Delay2' */
+  uint16_T UnitDelay1_DSTATE;          /* '<S7>/Unit Delay1' */
+  uint16_T UnitDelay_DSTATE_o;         /* '<S9>/Unit Delay' */
+  uint16_T UnitDelay1_DSTATE_i[28];    /* '<S6>/Unit Delay1' */
+  uint8_T UnitDelay_DSTATE_e;          /* '<S6>/Unit Delay' */
+  uint8_T UnitDelay_DSTATE_g;          /* '<S7>/Unit Delay' */
+  uint8_T UnitDelay_DSTATE_gh;         /* '<S8>/Unit Delay' */
+  boolean_T UnitDelay3_DSTATE;         /* '<S10>/Unit Delay3' */
+  boolean_T UnitDelay1_DSTATE_m;       /* '<S4>/Unit Delay1' */
+  boolean_T flg;                       /* '<S3>/Chart' */
+} DW_SOH_f_T;
+
+/* Real-time Model Data Structure */
+struct tag_RTM_SOH_T {
+  const char_T **errorStatus;
+};
+
+typedef struct {
+  B_SOH_c_T rtb;
+  DW_SOH_f_T rtdw;
+  RT_MODEL_SOH_T rtm;
+} MdlrefDW_SOH_T;
+
+/* Model reference registration function */
+extern void SOH_initialize(const char_T **rt_errorStatus, RT_MODEL_SOH_T *const
+  SOH_M);
+extern void SOH_Init(DW_SOH_f_T *localDW);
+extern void SOH(B_SOH_c_T *localB, DW_SOH_f_T *localDW);
+
+/* Exported data declaration */
+
+/* Declaration for custom storage class: ExportToFile */
+extern int16_T ihd_I_curr;
+
+/* 电池包电流； */
+extern uint8_T ihd_st_workStat;
+
+/* 电池工作状态； */
+extern uint32_T ihd_tm_parkTime;
+
+/* 驻车时间； */
+extern uint16_T ihv_V_cellU[28];
+
+/* 电池单体电压（数组）； */
+extern uint16_T sohd_Q_chrgEi;
+
+/* 充入容量读取量； */
+extern uint16_T sohd_Q_chrgEo;         /* '<S8>/Resettable Subsystem' */
+
+/* 充入容量写入量； */
+extern boolean_T sohd_flg_chrgEndEi;
+
+/* 充电结束标志位读取量； */
+extern boolean_T sohd_flg_chrgEndEo;   /* '<S7>/Switch' */
+
+/* 充电结束标志位写入量； */
+extern uint16_T sohd_pct_bcuSoh;       /* '<S3>/Saturation' */
+
+/* 电池SOH； */
+extern uint16_T sohd_tm_chrgStartStatEi;
+
+/* 充电前静置时间读取量； */
+extern uint16_T sohd_tm_chrgStartStatEo;/* '<S6>/Saturation' */
+
+/* 充电前静置时间写入量； */
+extern uint16_T sohv_Q_cellCap[28];    /* '<S3>/Subsystem' */
+
+/* 充入容量写入量； */
+extern uint16_T sohv_Q_packCapArrEi[10];
+
+/* 10次整包容量（数组）读取量； */
+extern uint16_T sohv_Q_packCapArrEo[10];/* '<S3>/Chart' */
+
+/* 10次整包容量（数组）写入量； */
+extern uint16_T sohv_V_chrgStartStatEi[28];
+
+/* 充电开始时刻的单体电压（数组）读取量； */
+extern uint16_T sohv_V_chrgStartStatEo[28];/* '<S6>/Switch' */
+
+/* 充电开始时刻的单体电压（数组）写入量； */
+
+/*-
+ * These blocks were eliminated from the model due to optimizations:
+ *
+ * Block '<S7>/Scope' : Unused code path elimination
+ * Block '<S7>/Scope1' : Unused code path elimination
+ * Block '<S9>/Saturation' : Eliminated Saturate block
+ */
+
+/*-
+ * The generated code includes comments that allow you to trace directly
+ * back to the appropriate location in the model.  The basic format
+ * is <system>/block_name, where system is the system number (uniquely
+ * assigned by Simulink) and block_name is the name of the block.
+ *
+ * Use the MATLAB hilite_system command to trace the generated code back
+ * to the model.  For example,
+ *
+ * hilite_system('<S3>')    - opens system 3
+ * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
+ *
+ * Here is the system hierarchy for this model
+ *
+ * '<Root>' : 'SOH'
+ * '<S1>'   : 'SOH/Subsystem4'
+ * '<S2>'   : 'SOH/Subsystem4/Chrgmation'
+ * '<S3>'   : 'SOH/Subsystem4/Conut'
+ * '<S4>'   : 'SOH/Subsystem4/CountEn'
+ * '<S5>'   : 'SOH/Subsystem4/EEDeal'
+ * '<S6>'   : 'SOH/Subsystem4/Chrgmation/ChrgBe'
+ * '<S7>'   : 'SOH/Subsystem4/Chrgmation/ChrgEnd'
+ * '<S8>'   : 'SOH/Subsystem4/Chrgmation/Chrging'
+ * '<S9>'   : 'SOH/Subsystem4/Chrgmation/ChrgBe/Resettable Subsystem'
+ * '<S10>'  : 'SOH/Subsystem4/Chrgmation/ChrgBe/keep'
+ * '<S11>'  : 'SOH/Subsystem4/Chrgmation/Chrging/Resettable Subsystem'
+ * '<S12>'  : 'SOH/Subsystem4/Conut/Chart'
+ * '<S13>'  : 'SOH/Subsystem4/Conut/Subsystem'
+ * '<S14>'  : 'SOH/Subsystem4/EEDeal/EECkeck'
+ * '<S15>'  : 'SOH/Subsystem4/EEDeal/FalseAction'
+ * '<S16>'  : 'SOH/Subsystem4/EEDeal/TureAction'
+ */
+#endif                                 /* RTW_HEADER_SOH_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOH_private.h

@@ -0,0 +1,105 @@
+/*
+ * File: SOH_private.h
+ *
+ * Code generated for Simulink model 'SOH'.
+ *
+ * Model version                  : 1.14
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:32 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOH_private_h_
+#define RTW_HEADER_SOH_private_h_
+#include "rtwtypes.h"
+#ifndef UCHAR_MAX
+#include <limits.h>
+#endif
+
+#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) )
+#error Code was generated for compiler with different sized uchar/char. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
+#error Code was generated for compiler with different sized ushort/short. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized uint/int. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) )
+#error Code was generated for compiler with different sized ulong/long. \
+Consider adjusting Test hardware word size settings on the \
+Hardware Implementation pane to match your compiler word sizes as \
+defined in limits.h of the compiler. Alternatively, you can \
+select the Test hardware is the same as production hardware option and \
+select the Enable portable word sizes option on the Code Generation > \
+Verification pane for ERT based targets, which will disable the \
+preprocessor word size checks.
+#endif
+
+/* Macros for accessing real-time model data structure */
+#ifndef rtmGetErrorStatus
+#define rtmGetErrorStatus(rtm)         (*((rtm)->errorStatus))
+#endif
+
+#ifndef rtmSetErrorStatus
+#define rtmSetErrorStatus(rtm, val)    (*((rtm)->errorStatus) = (val))
+#endif
+
+#ifndef rtmGetErrorStatusPointer
+#define rtmGetErrorStatusPointer(rtm)  (rtm)->errorStatus
+#endif
+
+#ifndef rtmSetErrorStatusPointer
+#define rtmSetErrorStatusPointer(rtm, val) ((rtm)->errorStatus = (val))
+#endif
+
+extern const uint16_T rtCP_pooled_neXCembKU1Do[13];
+extern const uint16_T rtCP_pooled_Pg3wA7d95Txu[13];
+
+#define rtCP_uDLookupTable1_bp01Data   rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S13>/1-D Lookup Table1'
+                                                                  */
+#define rtCP_uDLookupTable2_bp01Data   rtCP_pooled_neXCembKU1Do  /* Expression: cmnm_V_ocv
+                                                                  * Referenced by: '<S13>/1-D Lookup Table2'
+                                                                  */
+#define rtCP_uDLookupTable1_tableData  rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S13>/1-D Lookup Table1'
+                                                                  */
+#define rtCP_uDLookupTable2_tableData  rtCP_pooled_Pg3wA7d95Txu  /* Expression: cmnm_pct_soc
+                                                                  * Referenced by: '<S13>/1-D Lookup Table2'
+                                                                  */
+#endif                                 /* RTW_HEADER_SOH_private_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/SOH_types.h

@@ -0,0 +1,30 @@
+/*
+ * File: SOH_types.h
+ *
+ * Code generated for Simulink model 'SOH'.
+ *
+ * Model version                  : 1.14
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:32 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#ifndef RTW_HEADER_SOH_types_h_
+#define RTW_HEADER_SOH_types_h_
+
+/* Model Code Variants */
+
+/* Forward declaration for rtModel */
+typedef struct tag_RTM_SOH_T RT_MODEL_SOH_T;
+
+#endif                                 /* RTW_HEADER_SOH_types_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/app.h

@@ -26,6 +26,7 @@
 #include "ec_tcpip_api.h"
 #include "hal_module_adapter.h"
 #include "timers.h"
+#include "BCU.h"
 #ifndef  APP_H
 #define  APP_H
 #ifdef __cplusplus

inc/bsp_custom.h

@@ -6,6 +6,7 @@ extern "C" {
 #endif
 
 #include "bsp.h"
+#include "IQmathLib.h"
 #include "hal_module_adapter.h"
 #define getbit(x,y)     ((x) >> (y)&1)                        //获取x的第y位的数值
 #define setbit(x,y)     x|=(1<<y)                             //x的第y位置1

inc/div_nde_s32_floor.h

@@ -0,0 +1,23 @@
+/*
+ * File: div_nde_s32_floor.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_div_nde_s32_floor_h_
+#define RTW_HEADER_div_nde_s32_floor_h_
+#include "rtwtypes.h"
+
+extern int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator);
+
+#endif                                 /* RTW_HEADER_div_nde_s32_floor_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/div_nzp_repeat_u32.h

@@ -0,0 +1,24 @@
+/*
+ * File: div_nzp_repeat_u32.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_div_nzp_repeat_u32_h_
+#define RTW_HEADER_div_nzp_repeat_u32_h_
+#include "rtwtypes.h"
+
+extern uint32_T div_nzp_repeat_u32(uint32_T numerator, uint32_T denominator,
+  uint32_T nRepeatSub);
+
+#endif                                 /* RTW_HEADER_div_nzp_repeat_u32_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/div_nzp_repeat_u32_ceiling.h

@@ -0,0 +1,24 @@
+/*
+ * File: div_nzp_repeat_u32_ceiling.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_div_nzp_repeat_u32_ceiling_h_
+#define RTW_HEADER_div_nzp_repeat_u32_ceiling_h_
+#include "rtwtypes.h"
+
+extern uint32_T div_nzp_repeat_u32_ceiling(uint32_T numerator, uint32_T
+  denominator, uint32_T nRepeatSub);
+
+#endif                            /* RTW_HEADER_div_nzp_repeat_u32_ceiling_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/div_repeat_s16s32_floor.h

@@ -0,0 +1,24 @@
+/*
+ * File: div_repeat_s16s32_floor.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_div_repeat_s16s32_floor_h_
+#define RTW_HEADER_div_repeat_s16s32_floor_h_
+#include "rtwtypes.h"
+
+extern int16_T div_repeat_s16s32_floor(int32_T numerator, int32_T denominator,
+  uint32_T nRepeatSub);
+
+#endif                               /* RTW_HEADER_div_repeat_s16s32_floor_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/look1_binlxpw.h

@@ -0,0 +1,24 @@
+/*
+ * File: look1_binlxpw.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_look1_binlxpw_h_
+#define RTW_HEADER_look1_binlxpw_h_
+#include "rtwtypes.h"
+
+extern real_T look1_binlxpw(real_T u0, const real_T bp0[], const real_T table[],
+  uint32_T maxIndex);
+
+#endif                                 /* RTW_HEADER_look1_binlxpw_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/look1_is16lu16n16tu16_binlcase.h

@@ -0,0 +1,24 @@
+/*
+ * File: look1_is16lu16n16tu16_binlcase.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_look1_is16lu16n16tu16_binlcase_h_
+#define RTW_HEADER_look1_is16lu16n16tu16_binlcase_h_
+#include "rtwtypes.h"
+
+extern uint16_T look1_is16lu16n16tu16_binlcase(int16_T u0, const int16_T bp0[],
+  const uint16_T table[], uint32_T maxIndex);
+
+#endif                        /* RTW_HEADER_look1_is16lu16n16tu16_binlcase_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/look1_iu16lu16n16tu16_binlcase.h

@@ -0,0 +1,24 @@
+/*
+ * File: look1_iu16lu16n16tu16_binlcase.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_look1_iu16lu16n16tu16_binlcase_h_
+#define RTW_HEADER_look1_iu16lu16n16tu16_binlcase_h_
+#include "rtwtypes.h"
+
+extern uint16_T look1_iu16lu16n16tu16_binlcase(uint16_T u0, const uint16_T bp0[],
+  const uint16_T table[], uint32_T maxIndex);
+
+#endif                        /* RTW_HEADER_look1_iu16lu16n16tu16_binlcase_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_s32_loSR_sat.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_s32_loSR_sat.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_s32_loSR_sat_h_
+#define RTW_HEADER_mul_s32_loSR_sat_h_
+#include "rtwtypes.h"
+
+extern int32_T mul_s32_loSR_sat(int32_T a, int32_T b, uint32_T aShift);
+
+#endif                                 /* RTW_HEADER_mul_s32_loSR_sat_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_s32_sat.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_s32_sat.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_s32_sat_h_
+#define RTW_HEADER_mul_s32_sat_h_
+#include "rtwtypes.h"
+
+extern int32_T mul_s32_sat(int32_T a, int32_T b);
+
+#endif                                 /* RTW_HEADER_mul_s32_sat_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_ssu32_sat.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_ssu32_sat.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_ssu32_sat_h_
+#define RTW_HEADER_mul_ssu32_sat_h_
+#include "rtwtypes.h"
+
+extern int32_T mul_ssu32_sat(int32_T a, uint32_T b);
+
+#endif                                 /* RTW_HEADER_mul_ssu32_sat_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_u32_hiSR.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_u32_hiSR.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_u32_hiSR_h_
+#define RTW_HEADER_mul_u32_hiSR_h_
+#include "rtwtypes.h"
+
+extern uint32_T mul_u32_hiSR(uint32_T a, uint32_T b, uint32_T aShift);
+
+#endif                                 /* RTW_HEADER_mul_u32_hiSR_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_u32_hiSR_near.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_u32_hiSR_near.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ */
+
+#ifndef RTW_HEADER_mul_u32_hiSR_near_h_
+#define RTW_HEADER_mul_u32_hiSR_near_h_
+#include "rtwtypes.h"
+
+extern uint32_T mul_u32_hiSR_near(uint32_T a, uint32_T b, uint32_T aShift);
+
+#endif                                 /* RTW_HEADER_mul_u32_hiSR_near_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_us32_sat.h

@@ -0,0 +1,23 @@
+/*
+ * File: mul_us32_sat.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_us32_sat_h_
+#define RTW_HEADER_mul_us32_sat_h_
+#include "rtwtypes.h"
+
+extern uint32_T mul_us32_sat(int32_T a, int32_T b);
+
+#endif                                 /* RTW_HEADER_mul_us32_sat_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_wide_s32.h

@@ -0,0 +1,24 @@
+/*
+ * File: mul_wide_s32.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_wide_s32_h_
+#define RTW_HEADER_mul_wide_s32_h_
+#include "rtwtypes.h"
+
+extern void mul_wide_s32(int32_T in0, int32_T in1, uint32_T *ptrOutBitsHi,
+  uint32_T *ptrOutBitsLo);
+
+#endif                                 /* RTW_HEADER_mul_wide_s32_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_wide_su32.h

@@ -0,0 +1,24 @@
+/*
+ * File: mul_wide_su32.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_wide_su32_h_
+#define RTW_HEADER_mul_wide_su32_h_
+#include "rtwtypes.h"
+
+extern void mul_wide_su32(int32_T in0, uint32_T in1, uint32_T *ptrOutBitsHi,
+  uint32_T *ptrOutBitsLo);
+
+#endif                                 /* RTW_HEADER_mul_wide_su32_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/mul_wide_u32.h

@@ -0,0 +1,24 @@
+/*
+ * File: mul_wide_u32.h
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#ifndef RTW_HEADER_mul_wide_u32_h_
+#define RTW_HEADER_mul_wide_u32_h_
+#include "rtwtypes.h"
+
+extern void mul_wide_u32(uint32_T in0, uint32_T in1, uint32_T *ptrOutBitsHi,
+  uint32_T *ptrOutBitsLo);
+
+#endif                                 /* RTW_HEADER_mul_wide_u32_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/rtGetInf.h

@@ -0,0 +1,28 @@
+/*
+ * File: rtGetInf.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_rtGetInf_h_
+#define RTW_HEADER_rtGetInf_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+#include "rt_nonfinite.h"
+
+extern real_T rtGetInf(void);
+extern real32_T rtGetInfF(void);
+extern real_T rtGetMinusInf(void);
+extern real32_T rtGetMinusInfF(void);
+
+#endif                                 /* RTW_HEADER_rtGetInf_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/rtGetNaN.h

@@ -0,0 +1,26 @@
+/*
+ * File: rtGetNaN.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_rtGetNaN_h_
+#define RTW_HEADER_rtGetNaN_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+#include "rt_nonfinite.h"
+
+extern real_T rtGetNaN(void);
+extern real32_T rtGetNaNF(void);
+
+#endif                                 /* RTW_HEADER_rtGetNaN_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/rt_nonfinite.h

@@ -0,0 +1,54 @@
+/*
+ * File: rt_nonfinite.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_rt_nonfinite_h_
+#define RTW_HEADER_rt_nonfinite_h_
+#include <stddef.h>
+#include "rtwtypes.h"
+
+extern real_T rtInf;
+extern real_T rtMinusInf;
+extern real_T rtNaN;
+extern real32_T rtInfF;
+extern real32_T rtMinusInfF;
+extern real32_T rtNaNF;
+extern void rt_InitInfAndNaN(size_t realSize);
+extern boolean_T rtIsInf(real_T value);
+extern boolean_T rtIsInfF(real32_T value);
+extern boolean_T rtIsNaN(real_T value);
+extern boolean_T rtIsNaNF(real32_T value);
+typedef struct {
+  struct {
+    uint32_T wordH;
+    uint32_T wordL;
+  } words;
+} BigEndianIEEEDouble;
+
+typedef struct {
+  struct {
+    uint32_T wordL;
+    uint32_T wordH;
+  } words;
+} LittleEndianIEEEDouble;
+
+typedef struct {
+  union {
+    real32_T wordLreal;
+    uint32_T wordLuint;
+  } wordL;
+} IEEESingle;
+
+#endif                                 /* RTW_HEADER_rt_nonfinite_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/rt_powd_snf.h

@@ -0,0 +1,23 @@
+/*
+ * File: rt_powd_snf.h
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#ifndef RTW_HEADER_rt_powd_snf_h_
+#define RTW_HEADER_rt_powd_snf_h_
+#include "rtwtypes.h"
+
+extern real_T rt_powd_snf(real_T u0, real_T u1);
+
+#endif                                 /* RTW_HEADER_rt_powd_snf_h_ */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

inc/rtwtypes.h

@@ -0,0 +1,141 @@
+#ifndef RTWTYPES_H
+#define RTWTYPES_H
+
+/* Logical type definitions */
+#if (!defined(__cplusplus))
+#ifndef false
+#define false                          (0U)
+#endif
+
+#ifndef true
+#define true                           (1U)
+#endif
+#endif
+
+/*=======================================================================*
+ * Target hardware information
+ *   Device type: Intel->x86-64 (Windows64)
+ *   Number of bits:     char:   8    short:   16    int:  32
+ *                       long:  32
+ *                       native word size:  64
+ *   Byte ordering: LittleEndian
+ *   Signed integer division rounds to: Zero
+ *   Shift right on a signed integer as arithmetic shift: on
+ *=======================================================================*/
+
+/*=======================================================================*
+ * Fixed width word size data types:                                     *
+ *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
+ *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
+ *   real32_T, real64_T           - 32 and 64 bit floating point numbers *
+ *=======================================================================*/
+typedef signed char int8_T;
+typedef unsigned char uint8_T;
+typedef short int16_T;
+typedef unsigned short uint16_T;
+typedef int int32_T;
+typedef unsigned int uint32_T;
+typedef float real32_T;
+typedef double real64_T;
+
+/*===========================================================================*
+ * Generic type definitions: boolean_T, char_T, byte_T, int_T, uint_T,       *
+ *                           real_T, time_T, ulong_T.                        *
+ *===========================================================================*/
+typedef double real_T;
+typedef double time_T;
+typedef unsigned char boolean_T;
+typedef int int_T;
+typedef unsigned int uint_T;
+typedef unsigned long ulong_T;
+typedef char char_T;
+typedef unsigned char uchar_T;
+typedef char_T byte_T;
+
+/*===========================================================================*
+ * Complex number type definitions                                           *
+ *===========================================================================*/
+#define CREAL_T
+
+typedef struct {
+  real32_T re;
+  real32_T im;
+} creal32_T;
+
+typedef struct {
+  real64_T re;
+  real64_T im;
+} creal64_T;
+
+typedef struct {
+  real_T re;
+  real_T im;
+} creal_T;
+
+#define CINT8_T
+
+typedef struct {
+  int8_T re;
+  int8_T im;
+} cint8_T;
+
+#define CUINT8_T
+
+typedef struct {
+  uint8_T re;
+  uint8_T im;
+} cuint8_T;
+
+#define CINT16_T
+
+typedef struct {
+  int16_T re;
+  int16_T im;
+} cint16_T;
+
+#define CUINT16_T
+
+typedef struct {
+  uint16_T re;
+  uint16_T im;
+} cuint16_T;
+
+#define CINT32_T
+
+typedef struct {
+  int32_T re;
+  int32_T im;
+} cint32_T;
+
+#define CUINT32_T
+
+typedef struct {
+  uint32_T re;
+  uint32_T im;
+} cuint32_T;
+
+/*=======================================================================*
+ * Min and Max:                                                          *
+ *   int8_T, int16_T, int32_T     - signed 8, 16, or 32 bit integers     *
+ *   uint8_T, uint16_T, uint32_T  - unsigned 8, 16, or 32 bit integers   *
+ *=======================================================================*/
+#define MAX_int8_T                     ((int8_T)(127))
+#define MIN_int8_T                     ((int8_T)(-128))
+#define MAX_uint8_T                    ((uint8_T)(255U))
+#define MAX_int16_T                    ((int16_T)(32767))
+#define MIN_int16_T                    ((int16_T)(-32768))
+#define MAX_uint16_T                   ((uint16_T)(65535U))
+#define MAX_int32_T                    ((int32_T)(2147483647))
+#define MIN_int32_T                    ((int32_T)(-2147483647-1))
+#define MAX_uint32_T                   ((uint32_T)(0xFFFFFFFFU))
+
+/* Block D-Work pointer type */
+typedef void * pointer_T;
+
+#endif                                 /* RTWTYPES_H */
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/AppFunc.c

@@ -505,7 +505,12 @@ BOOL uartBattInfoDecode(UINT8* dataPtr)
     UINT8 	TEMP_NUM = 0;
     UINT16 	Batt_current;
 	UINT8 	BATT_CELL_VOL_NUM = 0,BATT_TEMP_NUM = 0;
+	UINT32  Battsumvoltage = 0;
 	BATT_CELL_VOL_NUM =  (dataPtr[(0x00)*2] << 8) | (dataPtr[(0x00)*2 + 1]);
+	if(BATT_CELL_VOL_NUM==0)
+	{
+		return FALSE;
+	}
 	BATT_TEMP_NUM = ((dataPtr[(0x01)*2] << 8) | (dataPtr[(0x01)*2 + 1]))-BMS_OTHER_TEMP;
 	if(AppNVMData.BattCellCount!=BATT_CELL_VOL_NUM || AppNVMData.BattTempCount!=BATT_TEMP_NUM )
 	{
@@ -516,6 +521,7 @@ BOOL uartBattInfoDecode(UINT8* dataPtr)
     for(i=0;i<BATT_CELL_VOL_NUM;i++)
     {
 		battCellU[i] = (dataPtr[(0x02+i)*2] << 8) | dataPtr[(0x02+i)*2 + 1];
+		Battsumvoltage = Battsumvoltage + battCellU[i];
     }
     battWorkState = (dataPtr[(0x03+BATT_CELL_VOL_NUM)*2+1])&0x03;//电池状态(原始数据)，0表示静置，1表示放电，2表示充电
     TEMP_NUM = BATT_TEMP_NUM + BMS_OTHER_TEMP;
@@ -523,6 +529,7 @@ BOOL uartBattInfoDecode(UINT8* dataPtr)
     {
 	    battCellTemp[i] = dataPtr[(0x06+BATT_CELL_VOL_NUM+i)*2+1];
     }
+	avrgCellVol = Battsumvoltage/BATT_CELL_VOL_NUM;
     MOSTemp = dataPtr[(0x06+BATT_CELL_VOL_NUM+BATT_TEMP_NUM)*2+1];
    	packTemp = dataPtr[(0x06+BATT_CELL_VOL_NUM+BATT_TEMP_NUM+1)*2+1];
     
@@ -574,6 +581,10 @@ BOOL uartBattInfoDecode(UINT8* dataPtr)
 		AppNVMData.BmsHwVersion = bmsHwVersion;
 		AppNVMData.BmsSwVersion = bmsSwVersion;
 	}
+	#ifdef USING_PRINTF1
+		printf("[%d]-%x\n",__LINE__,(dataPtr[(0x09+BATT_CELL_VOL_NUM+TEMP_NUM)*2+1]));
+		printf("[%d]-%x\n",__LINE__,(dataPtr[(0x1B+BATT_CELL_VOL_NUM+TEMP_NUM)*2]));
+	#endif
     temp = ((dataPtr[(0x09+BATT_CELL_VOL_NUM+TEMP_NUM)*2+1])>>1)&0x03;    
     battMOSSwitchState = ((temp&0x01)<<1)|((temp&0x02)>>1);	
     if(AppDataInfo.BattLock==TRUE)
@@ -1141,7 +1152,16 @@ static void setDefaultAppDataInfo(void)
     AppDataInfo.SysReStartCount = 0;
 	AppDataInfo.RelayControl = 0;
 	AppDataInfo.BattLock = 0;
-	AppDataInfo.BattStolenFlag = 0;
+	AppDataInfo.BattStolenFlag = 0;    
+	memset(&AppDataInfo.blcv_Q_totalCpE, 0x00, 28);          
+	memset(&AppDataInfo.blcv_Q_reqCpE, 0x00, 28);
+    AppDataInfo.socd_pct_bcuSocE = 0;            
+    AppDataInfo.socd_pct_battSocE = 0;           
+    AppDataInfo.sohd_tm_chrgStartStatE = 0;      
+    AppDataInfo.sohd_flg_chrgEndE = 0;            
+	memset(&AppDataInfo.sohv_V_chrgStartStatE, 0x00, 28);
+    AppDataInfo. sohd_Q_chrgE = 0;                
+	memset(&AppDataInfo.sohv_Q_packCapArrE, 300, 10);   
     return;
 }
 /***********************************************************************************************************************

src/AppSignal.c

@@ -64,11 +64,11 @@ UINT8   BattWorkStateDelay = 0;     //电池工作状态（延时处理后的）
 
 UINT8   PadInterrupt = 0x00;           //每个bit代表一个中断标志
 
-
 /**declear the uint16 vars**/
 UINT16	battCellU[28] = {0xFFFF};    //电池包单体电压
 UINT16	minCellVol = 0xFFFF;    //最小单体电压
 UINT16	maxCellVol = 0xFFFF;    //最大单体电压
+UINT16  avrgCellVol = 0xFFFF;   //平均单体电压 
 UINT16	battPackVol = 0xFFFF;   //电池总压
 UINT16	battI = 0xFFFF;         //电池总电流
 UINT16	nbHwVersion = 0xFFFF;   //数据模块硬件状态

src/AppTaskMain.c

@@ -56,7 +56,7 @@ static void MainTask(void* arg)
         Error_Mutex = osMutexNew(NULL);
     }
     LoadAppConfig();
-    LoadAppData();
+    
     if(Wakeup_source ==0)
     {
         AppDataInfo.appDataModify = TRUE;
@@ -69,6 +69,7 @@ static void MainTask(void* arg)
         {
             case PROCESS_STATE_IDLE:
             {
+                LoadAppData();
                 PROC_APP_STATE_SWITCH(IDLE);
                 xTimerStart(work_timer, 0);
                 PROC_MAIN_STATE_SWITCH(PROCESS_STATE_WORK);

src/AppTaskUart.c

@@ -79,9 +79,6 @@ static void UartTask(void* arg)
 				Uart_Cmd_Control(UartWriteCmdHandle,UartWriteData,UartAnswerData);//电池锁定，继电器锁定，加热控制
                 if(TimeCounter%10==0 && gProcess_app==WORK)
                 {
-                    #ifdef USING_PRINTF1
-                        printf("[%d]BattLock:%X,BattLockState:%X\n",__LINE__,AppDataInfo.BattLock,(UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1])&0x03);    
-                    #endif
                     if(osMessageQueueGet(UartWriteCmdHandle,&UartWriteData,0,0)==osOK&&UartRecvFlag==1)
                     {
                         PROC_UART_STATE_SWITCH(PROCESS_UART_STATE_WRITE);
@@ -124,7 +121,7 @@ static void UartTask(void* arg)
 				Uart_Read_Msg.CRC_L = CRC_chk_buffer;
 				Uart_Read_Msg.CRC_H = CRC_chk_buffer>>8;
 				Uart_Recv_LEN = Uart_DataRecv_func(Uart_Read_Msg,(UINT8*)(UartAnswerData.Header));
-                #ifdef USING_PRINTF1
+                #ifdef USING_PRINTF
 					printf("[%d]Uart_Recv_buffer-%d: ",__LINE__,Uart_Recv_LEN);
                 #endif
                 if(Uart_Recv_LEN>5)
@@ -231,6 +228,9 @@ static UINT8 Uart_WriteCmd_func(UartWriteData_S UartWriteData)
             CRC_chk_buffer = crc_chk((UINT8 *)&Uart_Write_Msg,sizeof(Uart_Write_Msg)-2);
             Uart_Write_Msg.CRC_L = CRC_chk_buffer;
             Uart_Write_Msg.CRC_H = CRC_chk_buffer>>8;
+			#ifdef USING_PRINTF
+				printf("try to lock or unlock\n");
+			#endif
             break;
         }
 		case 0x02://是否加热
@@ -247,6 +247,9 @@ static UINT8 Uart_WriteCmd_func(UartWriteData_S UartWriteData)
             CRC_chk_buffer = crc_chk((UINT8 *)&Uart_Write_Msg,sizeof(Uart_Write_Msg)-2);
             Uart_Write_Msg.CRC_L = CRC_chk_buffer;
             Uart_Write_Msg.CRC_H = CRC_chk_buffer>>8;
+			#ifdef USING_PRINTF
+				printf("try to heat or unheat\n");
+			#endif
             break;
 		}
 		case 0x04://是否继电器控制
@@ -263,6 +266,9 @@ static UINT8 Uart_WriteCmd_func(UartWriteData_S UartWriteData)
             CRC_chk_buffer = crc_chk((UINT8 *)&Uart_Write_Msg,sizeof(Uart_Write_Msg)-2);
             Uart_Write_Msg.CRC_L = CRC_chk_buffer;
             Uart_Write_Msg.CRC_H = CRC_chk_buffer>>8;
+			#ifdef USING_PRINTF
+				printf("try to relay control\n");
+			#endif
             break;
 		}
         default:
@@ -331,9 +337,6 @@ void Uart_Cmd_Control(QueueHandle_t UartWriteCmdHandle,UartWriteData_S UartWrite
 	}
 	if(battWorkState ==0x00 && AppDataInfo.BattLock==TRUE && ((UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1])&0x03)!=0x02)//try to lock lock the discharge 
 	{
-		#ifdef USING_PRINTF
-			printf("try to lock\n");
-		#endif
 		UartWriteData.WriteCmd = 0x01;
 		UartWriteData.Data[0] = 0x00|(UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2]);
 		UartWriteData.Data[1] = 0x02;
@@ -341,23 +344,19 @@ void Uart_Cmd_Control(QueueHandle_t UartWriteCmdHandle,UartWriteData_S UartWrite
 	}
 	else if (battWorkState ==0x00 && AppDataInfo.BattLock==FALSE && ((UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1])&0x03)!=0x03 ) // try to unlock
 	{
-		#ifdef USING_PRINTF
-			printf("try to unlock\n");
-		#endif
 		UartWriteData.WriteCmd = 0x01;
 		UartWriteData.Data[0] = 0x00|(UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2]);
 		UartWriteData.Data[1] = 0x03;
 		osMessageQueuePut(UartWriteCmdHandle,&UartWriteData,0,0);
 	}
-
-	if(AppDataInfo.RelayControl==TRUE && ((UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2])&0x80)==0x00)//继电器断开
+	if(AppDataInfo.RelayControl==TRUE && getbit((UartAnswerData.data[(0x09+AppNVMData.BattCellCount+AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1]),0)==0x00)//继电器断开
 	{
 		UartWriteData.WriteCmd = 0x04;
 		UartWriteData.Data[0] = 0x80;
 		UartWriteData.Data[1] = 0x00|(UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1]);
 		osMessageQueuePut(UartWriteCmdHandle,&UartWriteData,0,0);
 	}
-	else if(AppDataInfo.RelayControl==FALSE && ((UartAnswerData.data[(0x1B+AppNVMData.BattCellCount + AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2])&0x80)==0x80)//继电器闭合
+	else if(AppDataInfo.RelayControl==FALSE && getbit((UartAnswerData.data[(0x09+AppNVMData.BattCellCount+AppNVMData.BattTempCount + BMS_OTHER_TEMP)*2+1]),0)==0x01)//继电器闭合
 	{
 		UartWriteData.WriteCmd = 0x04;
 		UartWriteData.Data[0] = 0x00;

src/BCU.c

@@ -0,0 +1,375 @@
+/*
+ * File: BCU.c
+ *
+ * Code generated for Simulink model 'BCU'.
+ *
+ * Model version                  : 1.13
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:42 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#include "BCU.h"
+#include "BCU_private.h"
+static StaticTask_t                 gProcess_Bcu_Task_t;
+static UINT8                        gProcess_Bcu_TaskStack[PROC_BCU_TASK_STACK_SIZE];
+static osThreadId_t                 BcuTaskId = NULL;
+static process_Bcu 		    gProcess_Bcu_Task;
+#define PROC_BCU_STATE_SWITCH(a)  (gProcess_Bcu_Task = a)
+/* Block states (default storage) */
+DW_BCU_T BCU_DW;
+
+/* Real-time model */
+static RT_MODEL_BCU_T BCU_M_;
+RT_MODEL_BCU_T *const BCU_M = &BCU_M_;
+/* Model step function */
+  /* Exported data definition */
+  /* Definition for custom storage class: ExportToFile */
+  uint16_T blcv_Q_reqCpEi[28];           /* '<Root>/blcv_Q_reqCpEi' */
+
+  /* ������������ ��ȡ�������飩�� */
+  uint16_T blcv_Q_reqCpEo[28];           /* '<Root>/BLC' */
+
+  /* ������������ д���������飩�� */
+  uint32_T blcv_Q_totalCpEi[28];         /* '<Root>/blcv_Q_totalCpEi' */
+
+  /* �ۼƾ������� ��ȡ�������飩�� */
+  uint32_T blcv_Q_totalCpEo[28];         /* '<Root>/BLC' */
+
+  /* �ۼƾ������� д���������飩�� */
+  boolean_T blcv_flg_excute[28];         /* '<Root>/BLC' */
+
+  /* ����ִ�������־λ �����飩 */
+  int16_T ihd_I_curr;                    /* '<Root>/ihd_I_curr' */
+
+  /* ��ذ������� */
+  int16_T ihd_T_bdtemp;                  /* '<Root>/Constant' */
+  int16_T ihd_T_modTMax;                 /* '<Root>/ihd_T_modTMax' */
+
+  /* ģ���¶���� */
+  int16_T ihd_T_modTMin;                 /* '<Root>/ihd_T_modTMin' */
+
+  /* ģ���¶���С */
+  uint16_T ihd_V_cellUAvrg;              /* '<Root>/ihd_V_cellUAvrg' */
+
+  /* ��ص����ѹƽ���� */
+  uint16_T ihd_V_cellUMax;               /* '<Root>/ihd_V_cellUMax' */
+
+  /* ��ص����ѹ��� */
+  uint16_T ihd_V_cellUMin;               /* '<Root>/ihd_V_cellUMin' */
+
+  /* ��ص����ѹ��С�� */
+  uint8_T ihd_st_fault;                  /* '<Root>/ihd_st_fault' */
+
+  /* ���ϵȼ� */
+  uint8_T ihd_st_workStat;               /* '<Root>/ihd_st_workStat' */
+
+  /* ��ع���״̬�� */
+  uint32_T ihd_tm_parkTime;              /* '<Root>/ihd_tm_packTime' */
+
+  /* פ��ʱ�䣻 */
+  int16_T ihv_T_modT[6];                 /* '<Root>/ihv_T_modT' */
+
+  /* ģ���¶ȣ����飩 */
+  uint16_T ihv_V_cellU[28];              /* '<Root>/ihv_V_cellU' */
+
+  /* ��ص����ѹ�����飩�� */
+  uint16_T socd_pct_ahSoc;               /* '<Root>/SOC' */
+
+  /* ��ʱSOC�� */
+  uint16_T socd_pct_battSoc;             /* '<Root>/SOC' */
+
+  /* �����ʵSOC�� */
+  uint16_T socd_pct_battSocEi;           /* '<Root>/socd_pct_battSocEi' */
+
+  /* �����ʵSOC ��ȡ���� */
+  uint16_T socd_pct_battSocEo;           /* '<Root>/SOC' */
+
+  /* �����ʵSOC д������ */
+  uint16_T socd_pct_bcuSoc;              /* '<Root>/SOC' */
+
+  /* �����ʾSOC�� */
+  uint16_T socd_pct_bcuSocEi;            /* '<Root>/socd_pct_bcuSocEi' */
+
+  /* �����ʾSOC��ȡ���� */
+  uint16_T socd_pct_bcuSocEo;            /* '<Root>/SOC' */
+
+  /* �����ʾSOCд������ */
+  uint16_T sohd_Q_chrgEi;                /* '<Root>/sohd_Q_chrgEi ' */
+
+  /* ����������ȡ���� */
+  uint16_T sohd_Q_chrgEo;                /* '<Root>/SOH' */
+
+  /* ������������� */
+  boolean_T sohd_flg_chrgEndEi;          /* '<Root>/sohd_flg_chrgEndEi ' */
+
+  /* ��������־λ��ȡ���� */
+  boolean_T sohd_flg_chrgEndEo;          /* '<Root>/SOH' */
+
+  /* ��������־λд������ */
+  uint16_T sohd_pct_bcuSoh;              /* '<Root>/SOH' */
+
+  /* ���SOH�� */
+  uint16_T sohd_tm_chrgStartStatEi;      /* '<Root>/sohd_tm_chrgStartStatEi ' */
+
+  /* ���ǰ����ʱ���ȡ���� */
+  uint16_T sohd_tm_chrgStartStatEo;      /* '<Root>/SOH' */
+
+  /* ���ǰ����ʱ��д������ */
+  uint16_T sohv_Q_cellCap[28];           /* '<Root>/SOH' */
+
+  /* ������������� */
+  uint16_T sohv_Q_packCapArrEi[10];      /* '<Root>/sohv_Q_packCapArrEi ' */
+
+  /* 10���������������飩��ȡ���� */
+  uint16_T sohv_Q_packCapArrEo[10];      /* '<Root>/SOH' */
+
+  /* 10���������������飩д������ */
+  uint16_T sohv_V_chrgStartStatEi[28];   /* '<Root>/sohv_V_chrgStartStatEi ' */
+
+  /* ��翪ʼʱ�̵ĵ����ѹ�����飩��ȡ���� */
+  uint16_T sohv_V_chrgStartStatEo[28];   /* '<Root>/SOH' */
+
+void BCU_step(void)
+{
+  osDelay(1000);
+  PROC_BCU_STATE_SWITCH(PROCESS_STATE_INIT);
+  while (TRUE)
+  {
+    switch(gProcess_Bcu_Task)
+    {
+      case PROCESS_STATE_INIT:
+      {   
+        memcpy(&blcv_Q_totalCpEi,&AppDataInfo.blcv_Q_totalCpE, 28);       
+        memcpy(&blcv_Q_reqCpEi,&AppDataInfo.blcv_Q_reqCpE, 28);    
+        socd_pct_bcuSocEi = AppDataInfo.socd_pct_bcuSocE;           
+        socd_pct_battSocEi = AppDataInfo.socd_pct_battSocE;         
+        sohd_tm_chrgStartStatEi = AppDataInfo.sohd_tm_chrgStartStatE;     
+        sohd_flg_chrgEndEi = AppDataInfo.sohd_flg_chrgEndE;            
+        memcpy(&sohv_V_chrgStartStatEi,&AppDataInfo.sohv_V_chrgStartStatE, 28);
+        sohd_Q_chrgEi = AppDataInfo. sohd_Q_chrgE;                 
+        memcpy(&sohv_Q_packCapArrEi,&AppDataInfo.sohv_Q_packCapArrE, 10);
+        BCU_initialize();
+        PROC_BCU_STATE_SWITCH(PROCESS_STATE_IDLE);
+        break;
+      }
+      case PROCESS_STATE_IDLE:
+      {
+        while (TRUE)
+        {
+          osDelay(100);
+          if(gProcess_app!=LISTEN)
+          {
+            PROC_BCU_STATE_SWITCH(PROCESS_STATE_WORK);
+            break;
+          }
+          else
+          {
+            PROC_BCU_STATE_SWITCH(PROCESS_STATE_SLEEP);
+            break;
+          }
+        }
+        break;
+      }
+      case PROCESS_STATE_WORK:
+      {
+        while (TRUE)
+        {
+          osDelay(100);
+          if(gProcess_app==LISTEN)
+          {
+            PROC_BCU_STATE_SWITCH(PROCESS_STATE_SLEEP);
+            break;
+          }
+          ihd_I_curr = battI;
+          ihd_V_cellUMax = maxCellVol;
+          ihd_V_cellUMin = minCellVol;
+          ihd_V_cellUAvrg = avrgCellVol;
+          memcpy(battCellU,ihv_V_cellU,AppNVMData.BattCellCount);
+          memcpy(battCellTemp,ihv_T_modT,AppNVMData.BattTempCount);
+          ihd_T_modTMax = maxCellTemp;
+          ihd_T_modTMin = minCellTemp;
+          ihd_st_workStat  = BattWorkStateDelay;
+          ihd_st_fault = 0;
+          #ifdef USING_PRINTF1
+            printf("[%d]-%d-Begin:\n",__LINE__,TimeCounter);
+          #endif
+          /* ModelReference: '<Root>/SOH' incorporates:
+          *  Inport: '<Root>/ihd_I_curr'
+          *  Inport: '<Root>/ihd_st_workStat'
+          *  Inport: '<Root>/ihd_tm_packTime'
+          *  Inport: '<Root>/ihv_V_cellU'
+          *  Inport: '<Root>/sohd_Q_chrgEi '
+          *  Inport: '<Root>/sohd_flg_chrgEndEi '
+          *  Inport: '<Root>/sohd_tm_chrgStartStatEi '
+          *  Inport: '<Root>/sohv_Q_packCapArrEi '
+          *  Inport: '<Root>/sohv_V_chrgStartStatEi '
+          */
+          SOH(&(BCU_DW.SOH_InstanceData.rtb), &(BCU_DW.SOH_InstanceData.rtdw));
+
+          /* ModelReference: '<Root>/SOC' incorporates:
+          *  Inport: '<Root>/ihd_I_curr'
+          *  Inport: '<Root>/ihd_V_cellUAvrg'
+          *  Inport: '<Root>/ihd_V_cellUMax'
+          *  Inport: '<Root>/ihd_V_cellUMin'
+          *  Inport: '<Root>/ihd_st_workStat'
+          *  Inport: '<Root>/ihd_tm_packTime'
+          *  Inport: '<Root>/socd_pct_battSocEi'
+          *  Inport: '<Root>/socd_pct_bcuSocEi'
+          */
+          SOC(&(BCU_DW.SOC_InstanceData.rtb), &(BCU_DW.SOC_InstanceData.rtdw));
+          /* Constant: '<Root>/Constant' */
+          ihd_T_bdtemp = 400;
+          /* ModelReference: '<Root>/BLC' incorporates:
+          *  Inport: '<Root>/blcv_Q_reqCpEi'
+          *  Inport: '<Root>/blcv_Q_totalCpEi'
+          *  Inport: '<Root>/ihd_V_cellUMin'
+          *  Inport: '<Root>/ihd_st_fault'
+          *  Inport: '<Root>/ihd_tm_packTime'
+          *  Inport: '<Root>/ihv_V_cellU'
+          */
+          BLC(&(BCU_DW.BLC_InstanceData.rtb), &(BCU_DW.BLC_InstanceData.rtdw));
+          #ifdef USING_PRINTF
+            printf("[%d]-%d-End:\n",__LINE__,TimeCounter);
+            printf("[%d]-battI:%d,maxCellTemp:%d,minCellTemp:%d,avrgCellVol:%d\n",__LINE__,battI,maxCellTemp,minCellTemp,avrgCellVol);
+            printf("[%d]-socd_pct_bcuSoc:%d,socd_pct_ahSoc:%d,socd_pct_battSoc:%d,sohd_pct_bcuSoh:%d\n",__LINE__,socd_pct_bcuSoc,socd_pct_ahSoc,socd_pct_battSoc,sohd_pct_bcuSoh);
+          #endif
+        }
+        break;
+      }
+      case PROCESS_STATE_SLEEP:
+      {
+        memcpy(&AppDataInfo.blcv_Q_totalCpE,&blcv_Q_totalCpEo, 28);       
+        memcpy(&AppDataInfo.blcv_Q_reqCpE,&blcv_Q_reqCpEo, 28);    
+        AppDataInfo.socd_pct_bcuSocE =  socd_pct_bcuSocEo;  
+        AppDataInfo.socd_pct_battSocE = socd_pct_battSocEo;
+        AppDataInfo.sohd_tm_chrgStartStatE = sohd_tm_chrgStartStatEo;
+        AppDataInfo.sohd_flg_chrgEndE = sohd_flg_chrgEndEo;     
+        memcpy(&AppDataInfo.sohv_V_chrgStartStatE,&sohv_V_chrgStartStatEo, 28);
+        AppDataInfo. sohd_Q_chrgE = sohd_Q_chrgEo;           
+        memcpy(&AppDataInfo.sohv_Q_packCapArrE,&sohv_Q_packCapArrEo, 10);
+        AppDataInfo.appDataModify = TRUE;
+        while (TRUE)
+        {
+          osDelay(100);
+          if(gProcess_app!=LISTEN)
+          {
+            PROC_BCU_STATE_SWITCH(PROCESS_STATE_INIT);
+            break;
+          }
+        }
+        break;
+      }
+      default:
+      {
+        PROC_BCU_STATE_SWITCH(PROCESS_STATE_INIT);
+        break;
+      }
+    }
+  }
+}
+
+/* Model initialize function */
+void BCU_initialize(void)
+{
+  /* Registration code */
+
+  /* block I/O */
+
+  /* custom signals */
+  {
+    int32_T i;
+    for (i = 0; i < 28; i++) {
+      sohv_Q_cellCap[i] = 300U;
+    }
+  }
+
+  sohd_pct_bcuSoh = 1000U;
+
+  {
+    int32_T i;
+    for (i = 0; i < 10; i++) {
+      sohv_Q_packCapArrEo[i] = 300U;
+    }
+  }
+
+  /* external inputs */
+  {
+    int32_T i;
+    for (i = 0; i < 10; i++) {
+      sohv_Q_packCapArrEi[i] = 300U;
+    }
+  }
+
+  /* Model Initialize function for ModelReference Block: '<Root>/BLC' */
+  BLC_initialize(rtmGetErrorStatusPointer(BCU_M), &(BCU_DW.BLC_InstanceData.rtm));
+
+  /* Model Initialize function for ModelReference Block: '<Root>/SOC' */
+  SOC_initialize(rtmGetErrorStatusPointer(BCU_M), &(BCU_DW.SOC_InstanceData.rtm));
+
+  /* Model Initialize function for ModelReference Block: '<Root>/SOH' */
+  SOH_initialize(rtmGetErrorStatusPointer(BCU_M), &(BCU_DW.SOH_InstanceData.rtm));
+
+  /* SystemInitialize for ModelReference: '<Root>/SOH' incorporates:
+   *  Inport: '<Root>/ihd_I_curr'
+   *  Inport: '<Root>/ihd_st_workStat'
+   *  Inport: '<Root>/ihd_tm_packTime'
+   *  Inport: '<Root>/ihv_V_cellU'
+   *  Inport: '<Root>/sohd_Q_chrgEi '
+   *  Inport: '<Root>/sohd_flg_chrgEndEi '
+   *  Inport: '<Root>/sohd_tm_chrgStartStatEi '
+   *  Inport: '<Root>/sohv_Q_packCapArrEi '
+   *  Inport: '<Root>/sohv_V_chrgStartStatEi '
+   */
+  SOH_Init(&(BCU_DW.SOH_InstanceData.rtdw));
+
+  /* SystemInitialize for ModelReference: '<Root>/SOC' incorporates:
+   *  Inport: '<Root>/ihd_I_curr'
+   *  Inport: '<Root>/ihd_V_cellUAvrg'
+   *  Inport: '<Root>/ihd_V_cellUMax'
+   *  Inport: '<Root>/ihd_V_cellUMin'
+   *  Inport: '<Root>/ihd_st_workStat'
+   *  Inport: '<Root>/ihd_tm_packTime'
+   *  Inport: '<Root>/socd_pct_battSocEi'
+   *  Inport: '<Root>/socd_pct_bcuSocEi'
+   */
+  SOC_Init(&(BCU_DW.SOC_InstanceData.rtdw));
+
+  /* SystemInitialize for ModelReference: '<Root>/BLC' incorporates:
+   *  Inport: '<Root>/blcv_Q_reqCpEi'
+   *  Inport: '<Root>/blcv_Q_totalCpEi'
+   *  Inport: '<Root>/ihd_V_cellUMin'
+   *  Inport: '<Root>/ihd_st_fault'
+   *  Inport: '<Root>/ihd_tm_packTime'
+   *  Inport: '<Root>/ihv_V_cellU'
+   */
+  BLC_Init(&(BCU_DW.BLC_InstanceData.rtdw));
+}
+
+/* Model terminate function */
+void BCU_terminate(void)
+{
+  /* (no terminate code required) */
+}
+void AppTaskBcuInit(void *arg)
+{
+    osThreadAttr_t task_attr;
+    memset(&task_attr,0,sizeof(task_attr));
+    memset(gProcess_Bcu_TaskStack, 0xA5, PROC_BCU_TASK_STACK_SIZE);
+    task_attr.name = "Bcu_Task";
+    task_attr.stack_mem = gProcess_Bcu_TaskStack;
+    task_attr.stack_size = PROC_BCU_TASK_STACK_SIZE;
+    task_attr.priority = osPriorityBelowNormal7;
+    task_attr.cb_mem = &gProcess_Bcu_Task_t;
+    task_attr.cb_size = sizeof(StaticTask_t);
+    BcuTaskId = osThreadNew(BCU_step, NULL, &task_attr);
+}
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/BINARYSEARCH_U16.c

@@ -0,0 +1,50 @@
+/*
+ * File: BINARYSEARCH_U16.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "BINARYSEARCH_U16.h"
+
+/* Lookup Binary Search Utility BINARYSEARCH_U16 */
+void BINARYSEARCH_U16(uint32_T *piLeft, uint32_T *piRght, uint16_T u, const
+                      uint16_T *pData, uint32_T iHi)
+{
+  /* Find the location of current input value in the data table. */
+  *piLeft = 0U;
+  *piRght = iHi;
+  if (u <= pData[0] ) {
+    /* Less than or equal to the smallest point in the table. */
+    *piRght = 0U;
+  } else if (u >= pData[iHi] ) {
+    /* Greater than or equal to the largest point in the table. */
+    *piLeft = iHi;
+  } else {
+    uint32_T i;
+
+    /* Do a binary search. */
+    while (( *piRght - *piLeft ) > 1U ) {
+      /* Get the average of the left and right indices using to Floor rounding. */
+      i = (*piLeft + *piRght) >> 1;
+
+      /* Move either the right index or the left index so that */
+      /*  LeftDataPoint <= CurrentValue < RightDataPoint */
+      if (u < pData[i] ) {
+        *piRght = i;
+      } else {
+        *piLeft = i;
+      }
+    }
+  }
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/BLC.c

@@ -0,0 +1,368 @@
+/*
+ * File: BLC.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:13 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#include "BLC.h"
+#include "BLC_private.h"
+#include "look1_iu16lu16n16tu16_binlcase.h"
+#include "mul_s32_loSR_sat.h"
+#include "mul_s32_sat.h"
+#include "mul_ssu32_sat.h"
+#include "mul_u32_hiSR.h"
+#include "mul_us32_sat.h"
+
+/* System initialize for referenced model: 'BLC' */
+void BLC_Init(DW_BLC_f_T *localDW)
+{
+  /* InitializeConditions for UnitDelay: '<S1>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE = true;
+
+  /* SystemInitialize for Chart: '<S6>/Chart' */
+  localDW->FristFlg_b = true;
+
+  /* SystemInitialize for Chart: '<S6>/Chart1' */
+  localDW->FristFlg = true;
+}
+
+/* Output and update for referenced model: 'BLC' */
+void BLC(B_BLC_c_T *localB, DW_BLC_f_T *localDW)
+{
+  int32_T i_0;
+  int32_T q1;
+  uint32_T tmp;
+  uint32_T tmp_1;
+  uint16_T rtb_uDLookupTable[28];
+  uint16_T rtb_uDLookupTable1;
+  uint16_T tmp_0;
+  uint8_T i;
+  boolean_T rtb_RelationalOperator1;
+
+  /* Chart: '<S4>/Chart' incorporates:
+   *  Constant: '<S4>/Constant2'
+   *  Inport: '<Root>/ihd_T_bdtemp'
+   */
+  if (ihd_T_bdtemp > 600) {
+    i_0 = localDW->i_close + 1;
+    if (localDW->i_close + 1 > 255) {
+      i_0 = 255;
+    }
+
+    localDW->i_close = (uint8_T)i_0;
+  } else {
+    localDW->i_close = 0U;
+  }
+
+  if (localDW->i_close > 10) {
+    localDW->i_close = 11U;
+    for (i = 0U; i < 28; i++) {
+      localB->blcn_flg_pause[i] = true;
+    }
+  }
+
+  if (ihd_T_bdtemp < 850) {
+    i_0 = localDW->i_open + 1;
+    if (localDW->i_open + 1 > 255) {
+      i_0 = 255;
+    }
+
+    localDW->i_open = (uint8_T)i_0;
+  } else {
+    localDW->i_open = 0U;
+  }
+
+  if (localDW->i_open > 10) {
+    localDW->i_open = 11U;
+    for (i = 0U; i < 28; i++) {
+      localB->blcn_flg_pause[i] = false;
+    }
+  }
+
+  /* End of Chart: '<S4>/Chart' */
+
+  /* Chart: '<S7>/Chart' incorporates:
+   *  Constant: '<S7>/Constant2'
+   *  UnitDelay: '<S1>/Unit Delay'
+   */
+  for (i = 0U; i < 28; i++) {
+    if ((int32_T)(blcv_Q_reqCpEo[i] * 16777U) > 0) {
+      localB->blcn_flg_stop[i] = false;
+    } else {
+      localB->blcn_flg_stop[i] = true;
+    }
+  }
+
+  /* End of Chart: '<S7>/Chart' */
+
+  /* RelationalOperator: '<S3>/Relational Operator1?' incorporates:
+   *  Inport: '<Root>/ihd_st_fault'
+   */
+  rtb_RelationalOperator1 = (ihd_st_fault < 1);
+
+  /* Chart: '<S5>/Chart' incorporates:
+   *  Constant: '<S5>/Constant1'
+   *  Constant: '<S5>/Constant2'
+   *  Inport: '<Root>/ihv_V_cellU'
+   */
+  for (i = 0U; i < 28; i++) {
+    if (rtb_RelationalOperator1 && (!localB->blcn_flg_pause[i]) &&
+        (!localB->blcn_flg_stop[i])) {
+      localB->blcn_flg_blcable[i] = true;
+      i_0 = (int32_T)mul_u32_hiSR(localDW->blcCap[i], 3435973837U, 3U);
+      q1 = (int32_T)(ihv_V_cellU[i] / 1000U);
+      if ((i_0 < 0) && (q1 < MIN_int32_T - i_0)) {
+        i_0 = MIN_int32_T;
+      } else if ((i_0 > 0) && (q1 > MAX_int32_T - i_0)) {
+        i_0 = MAX_int32_T;
+      } else {
+        i_0 += q1;
+      }
+
+      localDW->blcCap[i] = mul_us32_sat(i_0, 10);
+      tmp_1 = localDW->blcCap[i] / 36000U;
+      if (tmp_1 > 65535U) {
+        tmp_1 = 65535U;
+      }
+
+      localB->blcn_Q_impleCp[i] = (uint16_T)tmp_1;
+    } else {
+      localB->blcn_flg_blcable[i] = false;
+    }
+  }
+
+  /* End of Chart: '<S5>/Chart' */
+
+  /* RelationalOperator: '<S3>/Relational Operator' incorporates:
+   *  Inport: '<Root>/ihd_tm_packTime'
+   */
+  rtb_RelationalOperator1 = (ihd_tm_parkTime >= 1800U);
+
+  /* Lookup_n-D: '<S6>/1-D Lookup Table1' incorporates:
+   *  Inport: '<Root>/ihd_V_cellUMin'
+   */
+  rtb_uDLookupTable1 = look1_iu16lu16n16tu16_binlcase(ihd_V_cellUMin,
+    rtCP_uDLookupTable1_bp01Data, rtCP_uDLookupTable1_tableData, 12U);
+
+  /* Lookup_n-D: '<S6>/1-D Lookup Table' incorporates:
+   *  Inport: '<Root>/ihv_V_cellU'
+   */
+  for (i_0 = 0; i_0 < 28; i_0++) {
+    rtb_uDLookupTable[i_0] = look1_iu16lu16n16tu16_binlcase(ihv_V_cellU[i_0],
+      rtCP_uDLookupTable_bp01Data, rtCP_uDLookupTable_tableData, 12U);
+  }
+
+  /* End of Lookup_n-D: '<S6>/1-D Lookup Table' */
+
+  /* Chart: '<S6>/Chart' incorporates:
+   *  Constant: '<S6>/Constant1'
+   *  Constant: '<S6>/Constant2'
+   *  Inport: '<Root>/ihd_V_cellUMin'
+   *  Inport: '<Root>/ihv_V_cellU'
+   *  Lookup_n-D: '<S6>/1-D Lookup Table'
+   *  Lookup_n-D: '<S6>/1-D Lookup Table1'
+   */
+  i = 0U;
+  if (localDW->FristFlg_b && rtb_RelationalOperator1) {
+    while (i < 28) {
+      if (ihv_V_cellU[i] - ihd_V_cellUMin > 10) {
+        i_0 = mul_s32_sat(mul_ssu32_sat(rtb_uDLookupTable[i] -
+          rtb_uDLookupTable1, 300U) / 100, 10);
+        if (i_0 < 0) {
+          i_0 = 0;
+        } else {
+          if (i_0 > 65535) {
+            i_0 = 65535;
+          }
+        }
+
+        localB->blcn_Q_reqCpNow_j[i] = (uint16_T)i_0;
+      }
+
+      i++;
+    }
+  }
+
+  localDW->FristFlg_b = false;
+
+  /* End of Chart: '<S6>/Chart' */
+
+  /* Chart: '<S6>/Chart1' incorporates:
+   *  Constant: '<S6>/Constant3'
+   *  Inport: '<Root>/sohv_Q_cellCap'
+   *  Lookup_n-D: '<S6>/1-D Lookup Table'
+   */
+  i = 0U;
+  if (localDW->FristFlg && rtb_RelationalOperator1) {
+    rtb_uDLookupTable1 = 65000U;
+    while (i < 28) {
+      tmp_1 = (uint32_T)sohv_Q_cellCap[i] * rtb_uDLookupTable[i];
+      tmp = tmp_1;
+      if (tmp_1 > 2147483647U) {
+        tmp = 2147483647U;
+      }
+
+      if ((int32_T)tmp / 100 < (int32_T)((rtb_uDLookupTable1 * 52429U) >> 19)) {
+        if (tmp_1 > 2147483647U) {
+          tmp_1 = 2147483647U;
+        }
+
+        i_0 = mul_s32_sat((int32_T)tmp_1 / 100, 10);
+        if (i_0 < 0) {
+          i_0 = 0;
+        } else {
+          if (i_0 > 65535) {
+            i_0 = 65535;
+          }
+        }
+
+        rtb_uDLookupTable1 = (uint16_T)i_0;
+        i_0 = mul_s32_loSR_sat((sohv_Q_cellCap[i] << 6) - (int32_T)(((uint16_T)
+          i_0 * 41943U) >> 16), 25, 4U);
+        if (i_0 < 0) {
+          i_0 = 0;
+        } else {
+          if (i_0 > 65535) {
+            i_0 = 65535;
+          }
+        }
+
+        localDW->QL = (uint16_T)i_0;
+      }
+
+      i++;
+    }
+  }
+
+  localDW->FristFlg = false;
+
+  /* End of Chart: '<S6>/Chart1' */
+
+  /* Outputs for Enabled SubSystem: '<S1>/EE' incorporates:
+   *  EnablePort: '<S2>/Enable'
+   */
+  /* UnitDelay: '<S1>/Unit Delay1' */
+  if (localDW->UnitDelay1_DSTATE) {
+    /* MinMax: '<S10>/Min' incorporates:
+     *  Inport: '<Root>/blcv_Q_reqCpEi'
+     */
+    rtb_uDLookupTable1 = blcv_Q_reqCpEi[0];
+    for (i_0 = 0; i_0 < 27; i_0++) {
+      tmp_0 = blcv_Q_reqCpEi[i_0 + 1];
+      if (rtb_uDLookupTable1 <= tmp_0) {
+        rtb_uDLookupTable1 = tmp_0;
+      }
+    }
+
+    /* If: '<S2>/If' incorporates:
+     *  Constant: '<S10>/Constant'
+     *  MinMax: '<S10>/Min'
+     *  RelationalOperator: '<S10>/Relational Operator'
+     */
+    if ((real_T)rtb_uDLookupTable1 * 0.001 < 65.0) {
+      /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem1' incorporates:
+       *  ActionPort: '<S9>/Action Port'
+       */
+      /* Merge: '<S2>/Merge1' incorporates:
+       *  Inport: '<Root>/blcv_Q_totalCpEi'
+       *  Inport: '<S9>/blcv_Q_totalCpEi'
+       */
+      memcpy(&localB->Merge1[0], (&(blcv_Q_totalCpEi[0])), 28U * sizeof(uint32_T));
+      for (i_0 = 0; i_0 < 28; i_0++) {
+        /* Merge: '<S2>/Merge' incorporates:
+         *  Inport: '<Root>/blcv_Q_reqCpEi'
+         *  Inport: '<S9>/blcv_Q_reqCpEi'
+         */
+        localB->Merge[i_0] = blcv_Q_reqCpEi[i_0];
+      }
+
+      /* End of Outputs for SubSystem: '<S2>/If Action Subsystem1' */
+    } else {
+      /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem' incorporates:
+       *  ActionPort: '<S8>/Action Port'
+       */
+      /* Merge: '<S2>/Merge1' incorporates:
+       *  SignalConversion generated from: '<S8>/blcv_Q_totalCpEE1'
+       */
+      memset(&localB->Merge1[0], 0, 28U * sizeof(uint32_T));
+      for (i_0 = 0; i_0 < 28; i_0++) {
+        /* Merge: '<S2>/Merge' incorporates:
+         *  SignalConversion generated from: '<S8>/blcv_Q_reqCpEE1'
+         */
+        localB->Merge[i_0] = 0U;
+      }
+
+      /* End of Outputs for SubSystem: '<S2>/If Action Subsystem' */
+    }
+
+    /* End of If: '<S2>/If' */
+  }
+
+  /* End of UnitDelay: '<S1>/Unit Delay1' */
+  /* End of Outputs for SubSystem: '<S1>/EE' */
+  for (i_0 = 0; i_0 < 28; i_0++) {
+    /* Switch: '<S6>/Switch' incorporates:
+     *  Merge: '<S2>/Merge'
+     */
+    if (rtb_RelationalOperator1) {
+      /* Saturate: '<S6>/Saturation' incorporates:
+       *  Switch: '<S6>/Switch'
+       */
+      rtb_uDLookupTable1 = localB->blcn_Q_reqCpNow_j[i_0];
+      if (rtb_uDLookupTable1 < 30000) {
+        blcv_Q_reqCpEo[i_0] = rtb_uDLookupTable1;
+      } else {
+        blcv_Q_reqCpEo[i_0] = 30000U;
+      }
+
+      /* End of Saturate: '<S6>/Saturation' */
+    } else {
+      blcv_Q_reqCpEo[i_0] = localB->Merge[i_0];
+    }
+
+    /* End of Switch: '<S6>/Switch' */
+
+    /* Sum: '<S5>/Add' incorporates:
+     *  Switch: '<S6>/Switch'
+     */
+    blcv_Q_reqCpEo[i_0] = (uint16_T)(blcv_Q_reqCpEo[i_0] -
+      localB->blcn_Q_impleCp[i_0]);
+
+    /* Sum: '<S5>/Add1' incorporates:
+     *  Merge: '<S2>/Merge1'
+     */
+    blcv_Q_totalCpEo[i_0] = localB->Merge1[i_0] + localB->blcn_Q_impleCp[i_0];
+
+    /* SignalConversion generated from: '<S5>/Chart' */
+    blcv_flg_excute[i_0] = localB->blcn_flg_blcable[i_0];
+  }
+
+  /* Update for UnitDelay: '<S1>/Unit Delay1' incorporates:
+   *  Constant: '<S1>/Constant'
+   */
+  localDW->UnitDelay1_DSTATE = false;
+}
+
+/* Model initialize function */
+void BLC_initialize(const char_T **rt_errorStatus, RT_MODEL_BLC_T *const BLC_M)
+{
+  /* Registration code */
+
+  /* initialize error status */
+  rtmSetErrorStatusPointer(BLC_M, rt_errorStatus);
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/INTERPOLATE_U16_U16.c

@@ -0,0 +1,65 @@
+/*
+ * File: INTERPOLATE_U16_U16.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "INTERPOLATE_U16_U16.h"
+
+/* Lookup Interpolation INTERPOLATE_U16_U16 */
+void INTERPOLATE_U16_U16(uint16_T *pY, uint16_T yL, uint16_T yR, uint16_T x,
+  uint16_T xL, uint16_T xR)
+{
+  uint32_T bigProd;
+  uint16_T yDiff;
+  uint16_T xNum;
+  uint16_T xDen;
+  *pY = yL;
+
+  /* If x is not strictly between xR and xL
+   * then an interpolation calculation is not necessary x == xL
+   * or not valid.  The invalid situation is expected when the input
+   * is beyond the left or right end of the table.  The design is
+   * that yL holds the correct value for *pY
+   * in invalid situations.
+   */
+  if ((xR > xL) && (x > xL) ) {
+    xDen = xR;
+    xDen = (uint16_T)((uint32_T)xDen - (uint32_T)xL);
+    xNum = x;
+    xNum = (uint16_T)((uint32_T)xNum - (uint32_T)xL);
+    if (yR >= yL ) {
+      yDiff = yR;
+      yDiff = (uint16_T)((uint32_T)yDiff - (uint32_T)yL);
+    } else {
+      yDiff = yL;
+      yDiff = (uint16_T)((uint32_T)yDiff - (uint32_T)yR);
+    }
+
+    bigProd = (uint32_T)yDiff * (uint32_T)xNum;
+
+    {
+      uint32_T rtb_u32_tmp;
+      rtb_u32_tmp = xDen;
+      yDiff = (uint16_T)(rtb_u32_tmp == 0U ? MAX_uint32_T : bigProd /
+                         rtb_u32_tmp);
+    }
+
+    if (yR >= yL ) {
+      *pY = (uint16_T)((uint32_T)*pY + (uint32_T)yDiff);
+    } else {
+      *pY = (uint16_T)((uint32_T)*pY - (uint32_T)yDiff);
+    }
+  }
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/LookUp_U16_U16.c

@@ -0,0 +1,31 @@
+/*
+ * File: LookUp_U16_U16.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "BINARYSEARCH_U16.h"
+#include "INTERPOLATE_U16_U16.h"
+#include "LookUp_U16_U16.h"
+
+/* Lookup Utility LookUp_U16_U16 */
+void LookUp_U16_U16(uint16_T *pY, const uint16_T *pYData, uint16_T u, const
+                    uint16_T *pUData, uint32_T iHi)
+{
+  uint32_T iLeft;
+  uint32_T iRght;
+  BINARYSEARCH_U16( &(iLeft), &(iRght), u, pUData, iHi);
+  INTERPOLATE_U16_U16( pY, pYData[iLeft], pYData[iRght], u, pUData[iLeft],
+                      pUData[iRght]);
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/SOC.c

@@ -0,0 +1,1446 @@
+/*
+ * File: SOC.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#include "SOC.h"
+#include "SOC_private.h"
+#include "LookUp_U16_U16.h"
+#include "div_nde_s32_floor.h"
+#include "div_repeat_s16s32_floor.h"
+#include "look1_binlxpw.h"
+#include "look1_is16lu16n16tu16_binlcase.h"
+#include "look1_iu16lu16n16tu16_binlcase.h"
+#include "mul_u32_hiSR_near.h"
+
+/*
+ * Output and update for atomic system:
+ *    '<S21>/MATLAB Function'
+ *    '<S30>/MATLAB Function'
+ */
+void SOC_MATLABFunction(real_T rtu_x, real_T *rty_y)
+{
+  *rty_y = ((((((-2.8104E-13 * pow(rtu_x, 7.0) + 1.0283E-10 * pow(rtu_x, 6.0)) +
+                -1.5072E-8 * pow(rtu_x, 5.0)) + 1.1295E-6 * pow(rtu_x, 4.0)) +
+              -4.588E-5 * pow(rtu_x, 3.0)) + rtu_x * rtu_x * 0.000993) +
+            -0.010548 * rtu_x) + 0.04876;
+}
+
+/* System initialize for referenced model: 'SOC' */
+void SOC_Init(DW_SOC_f_T *localDW)
+{
+  /* InitializeConditions for UnitDelay: '<S1>/Unit Delay' */
+  localDW->UnitDelay_DSTATE_et = true;
+
+  /* InitializeConditions for UnitDelay: '<S1>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_c = true;
+
+  /* InitializeConditions for UnitDelay: '<S11>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE[0] = 1.0E-6;
+
+  /* InitializeConditions for UnitDelay: '<S12>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_j[0] = 1.0E-6;
+
+  /* InitializeConditions for UnitDelay: '<S11>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE[1] = 0.0;
+
+  /* InitializeConditions for UnitDelay: '<S12>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_j[1] = 0.0;
+
+  /* InitializeConditions for UnitDelay: '<S11>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE[2] = 0.0;
+
+  /* InitializeConditions for UnitDelay: '<S12>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_j[2] = 0.0;
+
+  /* InitializeConditions for UnitDelay: '<S11>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE[3] = 1.0E-6;
+
+  /* InitializeConditions for UnitDelay: '<S12>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_j[3] = 1.0E-6;
+
+  /* InitializeConditions for UnitDelay: '<S6>/Unit Delay' */
+  localDW->UnitDelay_DSTATE_j = true;
+
+  /* InitializeConditions for UnitDelay: '<S6>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_a = 1U;
+
+  /* InitializeConditions for UnitDelay: '<S6>/Unit Delay2' */
+  localDW->UnitDelay2_DSTATE_d = 1U;
+
+  /* InitializeConditions for UnitDelay: '<S6>/Unit Delay5' */
+  localDW->UnitDelay5_DSTATE = true;
+
+  /* InitializeConditions for UnitDelay: '<S32>/Unit Delay3' */
+  localDW->UnitDelay3_DSTATE_p = 2000U;
+}
+
+/* Output and update for referenced model: 'SOC' */
+void SOC(B_SOC_c_T *localB, DW_SOC_f_T *localDW)
+{
+  /* local block i/o variables */
+  uint16_T rtb_Saturation_l;
+  uint16_T rtb_LookupTableDynamic1;
+  uint16_T rtb_LookupTableDynamic;
+  uint16_T rtb_TmpSignalConversionAtLookup[2];
+  uint16_T rtb_TmpSignalConversionAtLook_h[2];
+  uint16_T rtb_TmpSignalConversionAtLook_g[2];
+  uint16_T rtb_TmpSignalConversionAtLook_j[2];
+  real_T rtb_Add_mp[4];
+  real_T rtb_MatrixConcatenate[4];
+  real_T tmp[4];
+  real_T rtb_Divide[2];
+  real_T rtb_Divide_n[2];
+  real_T rtb_UnitDelay3[2];
+  real_T tmp_0[2];
+  real_T rtb_Add1;
+  real_T rtb_Add1_b;
+  real_T rtb_Add1_tmp;
+  real_T rtb_Add_d;
+  real_T rtb_Divide_a;
+  real_T rtb_Gain1;
+  real_T rtb_Gain1_p;
+  real_T rtb_MathFunction;
+  real_T rtb_Product_ie;
+  real_T rtb_UnitDelay3_0;
+  real_T tmp_1;
+  real_T tmp_2;
+  int32_T UnitDelay1_DSTATE_tmp;
+  int32_T i;
+  uint32_T tmp_3;
+  int16_T rtb_Saturation_n;
+  uint16_T rtb_DataTypeConversion;
+  uint16_T rtb_DataTypeConversion1;
+  uint16_T rtb_Saturation_j;
+  boolean_T rtb_RelationalOperator1_ii;
+  boolean_T rtb_RelationalOperator1_m;
+
+  /* Outputs for Enabled SubSystem: '<S1>/EEcheck' incorporates:
+   *  EnablePort: '<S2>/Enable'
+   */
+  /* UnitDelay: '<S1>/Unit Delay' */
+  if (localDW->UnitDelay_DSTATE_et) {
+    /* If: '<S2>/If' incorporates:
+     *  Inport: '<Root>/socd_pct_battSocEi'
+     *  Inport: '<Root>/socd_pct_bcuSocEi'
+     *  Logic: '<S10>/Logical Operator'
+     *  RelationalOperator: '<S10>/Relational Operator'
+     *  RelationalOperator: '<S10>/Relational Operator1'
+     */
+    if ((socd_pct_battSocEi > 1000) || (socd_pct_bcuSocEi > 1000)) {
+      /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem' incorporates:
+       *  ActionPort: '<S8>/Action Port'
+       */
+      /* Lookup_n-D: '<S8>/OCV-SOC' incorporates:
+       *  Inport: '<Root>/ihd_V_cellUAvrg'
+       */
+      localB->Merge = look1_iu16lu16n16tu16_binlcase(ihd_V_cellUAvrg,
+        rtCP_OCVSOC_bp01Data, rtCP_OCVSOC_tableData, 12U);
+
+      /* Merge: '<S2>/Merge1' incorporates:
+       *  Lookup_n-D: '<S8>/OCV-SOC'
+       *  SignalConversion: '<S8>/Signal Conversion1'
+       */
+      localB->Merge1 = localB->Merge;
+
+      /* End of Outputs for SubSystem: '<S2>/If Action Subsystem' */
+    } else {
+      /* Outputs for IfAction SubSystem: '<S2>/If Action Subsystem1' incorporates:
+       *  ActionPort: '<S9>/Action Port'
+       */
+      /* Lookup_n-D: '<S8>/OCV-SOC' incorporates:
+       *  Inport: '<S9>/socd_pct_battSocEi'
+       *  Merge: '<S2>/Merge'
+       */
+      localB->Merge = socd_pct_battSocEi;
+
+      /* Merge: '<S2>/Merge1' incorporates:
+       *  Inport: '<S9>/socd_pct_bcuSocEi'
+       */
+      localB->Merge1 = socd_pct_bcuSocEi;
+
+      /* End of Outputs for SubSystem: '<S2>/If Action Subsystem1' */
+    }
+
+    /* End of If: '<S2>/If' */
+  }
+
+  /* End of UnitDelay: '<S1>/Unit Delay' */
+  /* End of Outputs for SubSystem: '<S1>/EEcheck' */
+
+  /* Outputs for Enabled SubSystem: '<S1>/Inti_correct' incorporates:
+   *  EnablePort: '<S5>/Enable'
+   */
+  /* UnitDelay: '<S1>/Unit Delay1' */
+  if (localDW->UnitDelay1_DSTATE_c) {
+    /* Switch: '<S5>/Switch' incorporates:
+     *  Inport: '<Root>/ihd_tm_packTime'
+     *  RelationalOperator: '<S5>/Relational Operator'
+     */
+    if (ihd_tm_parkTime > 1800U) {
+      /* Switch: '<S5>/Switch' incorporates:
+       *  Inport: '<Root>/ihd_V_cellUAvrg'
+       *  Lookup_n-D: '<S5>/OCV-SOC'
+       */
+      localB->Switch = look1_iu16lu16n16tu16_binlcase(ihd_V_cellUAvrg,
+        rtCP_OCVSOC_bp01Data_b, rtCP_OCVSOC_tableData_b, 12U);
+    } else {
+      /* Switch: '<S5>/Switch' incorporates:
+       *  Merge: '<S2>/Merge'
+       */
+      localB->Switch = localB->Merge;
+    }
+
+    /* End of Switch: '<S5>/Switch' */
+
+    /* Product: '<S5>/Divide' incorporates:
+     *  Constant: '<S5>/Constant2'
+     *  Inport: '<Root>/sohd_pct_bcuSoh'
+     *  Product: '<S5>/Product'
+     */
+    localB->Divide = (uint16_T)((int32_T)(sohd_pct_bcuSoh * 300U / 2000U) << 1);
+  }
+
+  /* End of UnitDelay: '<S1>/Unit Delay1' */
+  /* End of Outputs for SubSystem: '<S1>/Inti_correct' */
+
+  /* Switch: '<S14>/Switch' incorporates:
+   *  UnitDelay: '<S14>/Unit Delay'
+   */
+  if (localDW->UnitDelay_DSTATE_c <= 0.0) {
+    /* Switch: '<S14>/Switch' incorporates:
+     *  Switch: '<S5>/Switch'
+     */
+    localDW->UnitDelay_DSTATE = (real_T)localB->Switch * 0.1;
+  }
+
+  /* End of Switch: '<S14>/Switch' */
+
+  /* Sum: '<S20>/Add1' incorporates:
+   *  Constant: '<S20>/Constant'
+   *  Gain: '<S20>/Gain4'
+   *  Inport: '<Root>/ihd_I_curr'
+   *  Product: '<S20>/Divide'
+   *  Product: '<S20>/Divide2'
+   *  Product: '<S5>/Divide'
+   *  Sum: '<S29>/Add1'
+   */
+  rtb_Add1_tmp = (real32_T)ihd_I_curr * 0.1F / 36000.0F / ((real32_T)
+    localB->Divide * 0.1F) * 100.0F;
+  rtb_Add1 = rtb_Add1_tmp + localDW->UnitDelay_DSTATE;
+
+  /* MATLAB Function: '<S21>/MATLAB Function' */
+  SOC_MATLABFunction(rtb_Add1, &rtb_Add_d);
+
+  /* SignalConversion generated from: '<S21>/Math Function1' incorporates:
+   *  Constant: '<S21>/Constant'
+   */
+  rtb_UnitDelay3[0] = rtb_Add_d;
+  rtb_UnitDelay3[1] = 1.0;
+
+  /* SignalConversion generated from: '<S21>/Matrix Concatenate' */
+  rtb_MatrixConcatenate[0] = 1.0;
+  rtb_MatrixConcatenate[1] = 0.0;
+
+  /* Gain: '<S20>/Gain1' incorporates:
+   *  Lookup_n-D: '<S20>/SOC-Rp'
+   *  Sum: '<S20>/Add1'
+   */
+  rtb_Gain1 = 0.001 * look1_binlxpw(rtb_Add1, rtCP_SOCRp_bp01Data,
+    rtCP_SOCRp_tableData, 12U);
+
+  /* Math: '<S21>/Math Function' incorporates:
+   *  Constant: '<S21>/Constant1'
+   *  Gain: '<S20>/Gain5'
+   *  Lookup_n-D: '<S20>/SOC-C'
+   *  Product: '<S20>/Divide1'
+   *  Product: '<S21>/Divide1'
+   *  Sum: '<S20>/Add1'
+   *
+   * About '<S21>/Math Function':
+   *  Operator: exp
+   */
+  rtb_MathFunction = exp(-0.1 / (rtb_Gain1 / (1000.0 * look1_binlxpw(rtb_Add1,
+    rtCP_SOCC_bp01Data, rtCP_SOCC_tableData, 12U))));
+
+  /* SignalConversion generated from: '<S21>/Matrix Concatenate' incorporates:
+   *  Constant: '<S21>/Constant3'
+   */
+  rtb_MatrixConcatenate[2] = 0.0;
+  rtb_MatrixConcatenate[3] = rtb_MathFunction;
+
+  /* Product: '<S16>/Product' incorporates:
+   *  Math: '<S16>/Math Function1'
+   *  SignalConversion generated from: '<S21>/Matrix Concatenate'
+   *  UnitDelay: '<S11>/Unit Delay1'
+   */
+  for (i = 0; i < 2; i++) {
+    tmp[i] = 0.0;
+    tmp[i] += localDW->UnitDelay1_DSTATE[i];
+    tmp[i + 2] = 0.0;
+    tmp[i + 2] += localDW->UnitDelay1_DSTATE[i + 2] * rtb_MathFunction;
+  }
+
+  /* Product: '<S17>/Product1' */
+  rtb_UnitDelay3_0 = 0.0;
+  for (i = 0; i < 2; i++) {
+    /* Sum: '<S16>/Add' incorporates:
+     *  Concatenate: '<S21>/Matrix Concatenate'
+     *  Constant: '<S11>/Constant'
+     *  Product: '<S16>/Product'
+     *  Sum: '<S24>/Add'
+     */
+    tmp_2 = rtb_MatrixConcatenate[i + 2];
+    tmp_1 = tmp_2 * tmp[1] + rtb_MatrixConcatenate[i] * tmp[0];
+    rtb_Add_mp[i] = tmp_1 + 0.001;
+
+    /* Product: '<S17>/Product1' incorporates:
+     *  Constant: '<S11>/Constant'
+     *  SignalConversion generated from: '<S21>/Math Function1'
+     *  Sum: '<S16>/Add'
+     */
+    rtb_Divide_a = (tmp_1 + 0.001) * rtb_Add_d;
+
+    /* Sum: '<S16>/Add' incorporates:
+     *  Concatenate: '<S21>/Matrix Concatenate'
+     *  Constant: '<S11>/Constant'
+     *  Product: '<S16>/Product'
+     *  Sum: '<S24>/Add'
+     */
+    tmp_1 = tmp_2 * tmp[3] + rtb_MatrixConcatenate[i] * tmp[2];
+    rtb_Add_mp[i + 2] = tmp_1 + 0.001;
+    rtb_Divide_a += tmp_1 + 0.001;
+
+    /* Product: '<S17>/Product1' incorporates:
+     *  Product: '<S17>/Product'
+     *  UnitDelay: '<S11>/Unit Delay3'
+     */
+    rtb_UnitDelay3_0 += rtb_UnitDelay3[i] * rtb_Divide_a;
+    rtb_Divide[i] = rtb_Divide_a;
+  }
+
+  /* Product: '<S17>/Divide' incorporates:
+   *  Constant: '<S11>/Constant1'
+   *  Product: '<S17>/Product'
+   *  Product: '<S17>/Product1'
+   *  Sum: '<S17>/Add'
+   */
+  rtb_Divide[0] /= rtb_UnitDelay3_0 + 0.5;
+  rtb_Divide_a = rtb_Divide[1] / (rtb_UnitDelay3_0 + 0.5);
+
+  /* Sum: '<S15>/Add' incorporates:
+   *  Product: '<S15>/Product1'
+   *  Product: '<S17>/Divide'
+   *  SignalConversion generated from: '<S21>/Math Function1'
+   */
+  tmp_1 = 1.0 - rtb_Divide[0] * rtb_Add_d;
+  tmp_2 = 0.0 - rtb_Divide_a * rtb_Add_d;
+  rtb_Add_d = 0.0 - rtb_Divide[0];
+
+  /* Product: '<S15>/Product' incorporates:
+   *  Sum: '<S15>/Add'
+   *  Sum: '<S24>/Add'
+   *  UnitDelay: '<S11>/Unit Delay1'
+   */
+  for (i = 0; i < 2; i++) {
+    UnitDelay1_DSTATE_tmp = i << 1;
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp] = 0.0;
+    rtb_UnitDelay3_0 = rtb_Add_mp[UnitDelay1_DSTATE_tmp];
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp] += rtb_UnitDelay3_0 *
+      tmp_1;
+    rtb_Add1_b = rtb_Add_mp[UnitDelay1_DSTATE_tmp + 1];
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp] += rtb_Add1_b * rtb_Add_d;
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp + 1] = 0.0;
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp + 1] += rtb_UnitDelay3_0 *
+      tmp_2;
+    localDW->UnitDelay1_DSTATE[UnitDelay1_DSTATE_tmp + 1] += rtb_Add1_b * (1.0 -
+      rtb_Divide_a);
+  }
+
+  /* End of Product: '<S15>/Product' */
+
+  /* Switch: '<S23>/Switch' incorporates:
+   *  UnitDelay: '<S23>/Unit Delay'
+   */
+  if (localDW->UnitDelay_DSTATE_e <= 0.0) {
+    /* Switch: '<S23>/Switch' incorporates:
+     *  Switch: '<S5>/Switch'
+     */
+    localDW->UnitDelay_DSTATE_o = (real_T)localB->Switch * 0.1;
+  }
+
+  /* End of Switch: '<S23>/Switch' */
+
+  /* Sum: '<S29>/Add1' */
+  rtb_Add1_b = rtb_Add1_tmp + localDW->UnitDelay_DSTATE_o;
+
+  /* MATLAB Function: '<S30>/MATLAB Function' */
+  SOC_MATLABFunction(rtb_Add1_b, &rtb_Add_d);
+
+  /* SignalConversion generated from: '<S30>/Math Function1' incorporates:
+   *  Constant: '<S30>/Constant'
+   */
+  rtb_UnitDelay3[0] = rtb_Add_d;
+  rtb_UnitDelay3[1] = 1.0;
+
+  /* SignalConversion generated from: '<S30>/Matrix Concatenate' */
+  rtb_Add_mp[0] = 1.0;
+  rtb_Add_mp[1] = 0.0;
+
+  /* Gain: '<S29>/Gain1' incorporates:
+   *  Lookup_n-D: '<S29>/SOC-Rp'
+   *  Sum: '<S29>/Add1'
+   */
+  rtb_Gain1_p = 0.001 * look1_binlxpw(rtb_Add1_b, rtCP_SOCRp_bp01Data_a,
+    rtCP_SOCRp_tableData_b, 12U);
+
+  /* Math: '<S30>/Math Function' incorporates:
+   *  Constant: '<S30>/Constant1'
+   *  Gain: '<S29>/Gain5'
+   *  Lookup_n-D: '<S29>/SOC-C'
+   *  Product: '<S29>/Divide1'
+   *  Product: '<S30>/Divide1'
+   *  Sum: '<S29>/Add1'
+   *
+   * About '<S30>/Math Function':
+   *  Operator: exp
+   */
+  rtb_Product_ie = exp(-0.1 / (rtb_Gain1_p / (1000.0 * look1_binlxpw(rtb_Add1_b,
+    rtCP_SOCC_bp01Data_o, rtCP_SOCC_tableData_l, 12U))));
+
+  /* SignalConversion generated from: '<S30>/Matrix Concatenate' incorporates:
+   *  Constant: '<S30>/Constant3'
+   */
+  rtb_Add_mp[2] = 0.0;
+  rtb_Add_mp[3] = rtb_Product_ie;
+
+  /* Product: '<S25>/Product' incorporates:
+   *  Math: '<S25>/Math Function1'
+   *  SignalConversion generated from: '<S30>/Matrix Concatenate'
+   *  UnitDelay: '<S12>/Unit Delay1'
+   */
+  for (i = 0; i < 2; i++) {
+    tmp[i] = 0.0;
+    tmp[i] += localDW->UnitDelay1_DSTATE_j[i];
+    tmp[i + 2] = 0.0;
+    tmp[i + 2] += localDW->UnitDelay1_DSTATE_j[i + 2] * rtb_Product_ie;
+  }
+
+  /* Product: '<S26>/Product1' */
+  rtb_UnitDelay3_0 = 0.0;
+  for (i = 0; i < 2; i++) {
+    /* Sum: '<S25>/Add' incorporates:
+     *  Concatenate: '<S30>/Matrix Concatenate'
+     *  Constant: '<S12>/Constant'
+     *  Product: '<S25>/Product'
+     */
+    tmp_2 = rtb_Add_mp[i + 2];
+    tmp_1 = tmp_2 * tmp[1] + rtb_Add_mp[i] * tmp[0];
+    rtb_MatrixConcatenate[i] = tmp_1 + 0.001;
+
+    /* Product: '<S26>/Product1' incorporates:
+     *  Constant: '<S12>/Constant'
+     *  SignalConversion generated from: '<S30>/Math Function1'
+     *  Sum: '<S25>/Add'
+     */
+    rtb_Add1_tmp = (tmp_1 + 0.001) * rtb_Add_d;
+
+    /* Sum: '<S25>/Add' incorporates:
+     *  Concatenate: '<S30>/Matrix Concatenate'
+     *  Constant: '<S12>/Constant'
+     *  Product: '<S25>/Product'
+     */
+    tmp_1 = tmp_2 * tmp[3] + rtb_Add_mp[i] * tmp[2];
+    rtb_MatrixConcatenate[i + 2] = tmp_1 + 0.001;
+    rtb_Add1_tmp += tmp_1 + 0.001;
+
+    /* Product: '<S26>/Product1' incorporates:
+     *  Product: '<S26>/Product'
+     *  UnitDelay: '<S11>/Unit Delay3'
+     */
+    rtb_UnitDelay3_0 += rtb_UnitDelay3[i] * rtb_Add1_tmp;
+    rtb_Divide_n[i] = rtb_Add1_tmp;
+  }
+
+  /* Product: '<S26>/Divide' incorporates:
+   *  Constant: '<S12>/Constant1'
+   *  Product: '<S26>/Product'
+   *  Product: '<S26>/Product1'
+   *  Sum: '<S26>/Add'
+   */
+  rtb_Divide_n[0] /= rtb_UnitDelay3_0 + 0.5;
+  rtb_Add1_tmp = rtb_Divide_n[1] / (rtb_UnitDelay3_0 + 0.5);
+
+  /* Sum: '<S24>/Add' incorporates:
+   *  Product: '<S24>/Product1'
+   *  Product: '<S26>/Divide'
+   *  SignalConversion generated from: '<S30>/Math Function1'
+   */
+  tmp[0] = 1.0 - rtb_Divide_n[0] * rtb_Add_d;
+  tmp[1] = 0.0 - rtb_Add1_tmp * rtb_Add_d;
+  tmp[2] = 0.0 - rtb_Divide_n[0];
+  tmp[3] = 1.0 - rtb_Add1_tmp;
+
+  /* Switch: '<S23>/Switch1' incorporates:
+   *  UnitDelay: '<S23>/Unit Delay1'
+   */
+  if (localDW->UnitDelay1_DSTATE_h <= 0.0) {
+    /* SignalConversion generated from: '<S28>/Product1' incorporates:
+     *  Constant: '<S23>/Up'
+     */
+    localDW->UnitDelay2_DSTATE = 0.0;
+  }
+
+  /* End of Switch: '<S23>/Switch1' */
+
+  /* Product: '<S28>/Product2' incorporates:
+   *  Constant: '<S30>/Constant4'
+   *  Constant: '<S30>/Constant5'
+   *  Gain: '<S30>/Gain'
+   *  Inport: '<Root>/ihd_I_curr'
+   *  Product: '<S19>/Product'
+   *  Product: '<S19>/Product2'
+   *  Product: '<S28>/Product'
+   *  Product: '<S30>/Divide2'
+   *  Product: '<S30>/Product'
+   *  Product: '<S5>/Divide'
+   *  Sum: '<S30>/Add'
+   */
+  tmp_2 = (real_T)ihd_I_curr * 0.1;
+  tmp_1 = 0.1 / ((real_T)localB->Divide * 0.1) * 0.027777777777777776 * tmp_2;
+  tmp_0[0] = tmp_1;
+  tmp_0[1] = (1.0 - rtb_Product_ie) * rtb_Gain1_p * tmp_2;
+  for (i = 0; i < 2; i++) {
+    /* Product: '<S24>/Product' incorporates:
+     *  Sum: '<S25>/Add'
+     *  UnitDelay: '<S12>/Unit Delay1'
+     */
+    localDW->UnitDelay1_DSTATE_j[i] = 0.0;
+    localDW->UnitDelay1_DSTATE_j[i] += tmp[i] * rtb_MatrixConcatenate[0];
+    rtb_Add_d = tmp[i + 2];
+    localDW->UnitDelay1_DSTATE_j[i] += rtb_Add_d * rtb_MatrixConcatenate[1];
+    localDW->UnitDelay1_DSTATE_j[i + 2] = 0.0;
+    localDW->UnitDelay1_DSTATE_j[i + 2] += tmp[i] * rtb_MatrixConcatenate[2];
+    localDW->UnitDelay1_DSTATE_j[i + 2] += rtb_Add_d * rtb_MatrixConcatenate[3];
+
+    /* Sum: '<S28>/Add1' incorporates:
+     *  Concatenate: '<S30>/Matrix Concatenate'
+     *  Product: '<S28>/Product1'
+     *  SignalConversion generated from: '<S28>/Product1'
+     */
+    rtb_UnitDelay3[i] = (rtb_Add_mp[i + 2] * localDW->UnitDelay2_DSTATE +
+                         rtb_Add_mp[i] * localDW->UnitDelay_DSTATE_o) + tmp_0[i];
+  }
+
+  /* Sum: '<S27>/Add1' incorporates:
+   *  Gain: '<S29>/Gain2'
+   *  Inport: '<Root>/ihd_V_cellUMin'
+   *  Lookup_n-D: '<S29>/SOC-OCV'
+   *  Lookup_n-D: '<S29>/SOC-Ro'
+   *  Product: '<S28>/Product'
+   *  Sum: '<S28>/Add'
+   *  Sum: '<S29>/Add1'
+   */
+  rtb_Add_d = (real_T)ihd_V_cellUMin * 0.001 - ((0.001 * look1_binlxpw
+    (rtb_Add1_b, rtCP_SOCRo_bp01Data, rtCP_SOCRo_tableData, 12U) * tmp_2 +
+    look1_binlxpw(rtb_Add1_b, rtCP_SOCOCV_bp01Data, rtCP_SOCOCV_tableData, 12U))
+    + rtb_UnitDelay3[1]);
+
+  /* Sum: '<S27>/Add' incorporates:
+   *  Product: '<S27>/Product'
+   *  UnitDelay: '<S12>/Unit Delay3'
+   */
+  localDW->UnitDelay3_DSTATE[0] = localDW->UnitDelay3_DSTATE[0] * rtb_Add_d +
+    rtb_UnitDelay3[0];
+  localDW->UnitDelay3_DSTATE[1] = localDW->UnitDelay3_DSTATE[1] * rtb_Add_d +
+    rtb_UnitDelay3[1];
+
+  /* Switch: '<S14>/Switch1' incorporates:
+   *  Constant: '<S14>/Up'
+   *  UnitDelay: '<S14>/Unit Delay1'
+   */
+  if (localDW->UnitDelay1_DSTATE_l <= 0.0) {
+    localDW->UnitDelay2_DSTATE_k = 0.0;
+  }
+
+  /* End of Switch: '<S14>/Switch1' */
+
+  /* Sum: '<S19>/Add1' incorporates:
+   *  Constant: '<S21>/Constant5'
+   *  Product: '<S19>/Product1'
+   *  Product: '<S19>/Product2'
+   *  Product: '<S21>/Product'
+   *  SignalConversion generated from: '<S21>/Matrix Concatenate'
+   *  Sum: '<S21>/Add'
+   */
+  rtb_UnitDelay3_0 = (1.0 - rtb_MathFunction) * rtb_Gain1 * tmp_2 +
+    rtb_MathFunction * localDW->UnitDelay2_DSTATE_k;
+
+  /* Sum: '<S18>/Add1' incorporates:
+   *  Gain: '<S20>/Gain2'
+   *  Inport: '<Root>/ihd_V_cellUMax'
+   *  Lookup_n-D: '<S20>/SOC-OCV'
+   *  Lookup_n-D: '<S20>/SOC-Ro'
+   *  Product: '<S19>/Product'
+   *  Sum: '<S19>/Add'
+   *  Sum: '<S20>/Add1'
+   */
+  rtb_Add1 = (real_T)ihd_V_cellUMax * 0.001 - ((0.001 * look1_binlxpw(rtb_Add1,
+    rtCP_SOCRo_bp01Data_c, rtCP_SOCRo_tableData_n, 12U) * tmp_2 + look1_binlxpw
+    (rtb_Add1, rtCP_SOCOCV_bp01Data_a, rtCP_SOCOCV_tableData_c, 12U)) +
+    rtb_UnitDelay3_0);
+
+  /* Sum: '<S18>/Add' incorporates:
+   *  Product: '<S18>/Product'
+   *  SignalConversion generated from: '<S19>/Product1'
+   *  Sum: '<S19>/Add1'
+   *  UnitDelay: '<S11>/Unit Delay3'
+   */
+  localDW->UnitDelay3_DSTATE_g[0] = (tmp_1 + localDW->UnitDelay_DSTATE) +
+    localDW->UnitDelay3_DSTATE_g[0] * rtb_Add1;
+  localDW->UnitDelay3_DSTATE_g[1] = localDW->UnitDelay3_DSTATE_g[1] * rtb_Add1 +
+    rtb_UnitDelay3_0;
+
+  /* Saturate: '<S33>/Saturation' incorporates:
+   *  Constant: '<S33>/Constant'
+   *  Sum: '<S33>/Add'
+   *  UnitDelay: '<S33>/Unit Delay'
+   */
+  if ((uint16_T)(localDW->UnitDelay_DSTATE_i + 1U) < 60000) {
+    rtb_Saturation_j = (uint16_T)(localDW->UnitDelay_DSTATE_i + 1U);
+  } else {
+    rtb_Saturation_j = 60000U;
+  }
+
+  /* End of Saturate: '<S33>/Saturation' */
+
+  /* RelationalOperator: '<S33>/Relational Operator1' incorporates:
+   *  Constant: '<S33>/para'
+   */
+  rtb_RelationalOperator1_ii = (rtb_Saturation_j >= 20);
+
+  /* Saturate: '<S11>/Saturation' */
+  if (localDW->UnitDelay3_DSTATE_g[0] > 100.0) {
+    /* Switch: '<S14>/Switch' */
+    localDW->UnitDelay_DSTATE = 100.0;
+  } else if (localDW->UnitDelay3_DSTATE_g[0] < 0.0) {
+    /* Switch: '<S14>/Switch' */
+    localDW->UnitDelay_DSTATE = 0.0;
+  } else {
+    /* Switch: '<S14>/Switch' */
+    localDW->UnitDelay_DSTATE = localDW->UnitDelay3_DSTATE_g[0];
+  }
+
+  /* End of Saturate: '<S11>/Saturation' */
+
+  /* DataTypeConversion: '<S3>/Data Type Conversion1' incorporates:
+   *  UnitDelay: '<S11>/Unit Delay'
+   */
+  rtb_Add1 = localDW->UnitDelay_DSTATE / 0.1;
+  rtb_Gain1 = fabs(rtb_Add1);
+  if (rtb_Gain1 < 4.503599627370496E+15) {
+    if (rtb_Gain1 >= 0.5) {
+      rtb_Add1 = floor(rtb_Add1 + 0.5);
+    } else {
+      rtb_Add1 = 0.0;
+    }
+  }
+
+  tmp_2 = fmod(rtb_Add1, 65536.0);
+  rtb_DataTypeConversion1 = (uint16_T)(tmp_2 < 0.0 ? (int32_T)(uint16_T)
+    -(int16_T)(uint16_T)-tmp_2 : (int32_T)(uint16_T)tmp_2);
+
+  /* End of DataTypeConversion: '<S3>/Data Type Conversion1' */
+
+  /* Saturate: '<S12>/Saturation' */
+  if (localDW->UnitDelay3_DSTATE[0] > 100.0) {
+    /* Switch: '<S23>/Switch' */
+    localDW->UnitDelay_DSTATE_o = 100.0;
+  } else if (localDW->UnitDelay3_DSTATE[0] < 0.0) {
+    /* Switch: '<S23>/Switch' */
+    localDW->UnitDelay_DSTATE_o = 0.0;
+  } else {
+    /* Switch: '<S23>/Switch' */
+    localDW->UnitDelay_DSTATE_o = localDW->UnitDelay3_DSTATE[0];
+  }
+
+  /* End of Saturate: '<S12>/Saturation' */
+
+  /* DataTypeConversion: '<S3>/Data Type Conversion' incorporates:
+   *  UnitDelay: '<S12>/Unit Delay'
+   */
+  rtb_Add1 = localDW->UnitDelay_DSTATE_o / 0.1;
+  rtb_Gain1 = fabs(rtb_Add1);
+  if (rtb_Gain1 < 4.503599627370496E+15) {
+    if (rtb_Gain1 >= 0.5) {
+      rtb_Add1 = floor(rtb_Add1 + 0.5);
+    } else {
+      rtb_Add1 = 0.0;
+    }
+  }
+
+  tmp_2 = fmod(rtb_Add1, 65536.0);
+  rtb_DataTypeConversion = (uint16_T)(tmp_2 < 0.0 ? (int32_T)(uint16_T)-(int16_T)
+    (uint16_T)-tmp_2 : (int32_T)(uint16_T)tmp_2);
+
+  /* End of DataTypeConversion: '<S3>/Data Type Conversion' */
+
+  /* Switch: '<S13>/Switch' incorporates:
+   *  DataTypeConversion: '<S3>/Data Type Conversion'
+   *  DataTypeConversion: '<S3>/Data Type Conversion1'
+   *  RelationalOperator: '<S13>/Relational Operator'
+   *  RelationalOperator: '<S13>/Relational Operator1'
+   *  Switch: '<S13>/Switch1'
+   */
+  if (rtb_DataTypeConversion1 >= 800) {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Constant: '<S13>/Constant6'
+     *  Sum: '<S4>/Add1'
+     */
+    socd_pct_ahSoc = 100U;
+  } else if (200 >= rtb_DataTypeConversion) {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Constant: '<S13>/Constant8'
+     *  Sum: '<S4>/Add1'
+     *  Switch: '<S13>/Switch1'
+     */
+    socd_pct_ahSoc = 0U;
+  } else {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Constant: '<S13>/Constant2'
+     *  Constant: '<S13>/Constant3'
+     *  DataTypeConversion: '<S3>/Data Type Conversion'
+     *  Sum: '<S13>/Add3'
+     *  Sum: '<S13>/Add4'
+     *  Sum: '<S13>/Add5'
+     *  Switch: '<S13>/Switch1'
+     */
+    i = (uint16_T)((uint16_T)(800 - (uint16_T)(rtb_DataTypeConversion1 -
+      rtb_DataTypeConversion)) - 200);
+
+    /* Product: '<S13>/Divide' incorporates:
+     *  Constant: '<S13>/Constant1'
+     *  DataTypeConversion: '<S3>/Data Type Conversion'
+     *  Sum: '<S13>/Add2'
+     *  Switch: '<S13>/Switch1'
+     */
+    socd_pct_ahSoc = (uint16_T)(((uint16_T)((uint32_T)i == 0U ? MAX_uint32_T :
+      ((uint32_T)(rtb_DataTypeConversion - 200) << 6) / i) * 25U) >> 4);
+
+    /* MinMax: '<S13>/Max' incorporates:
+     *  Product: '<S13>/Divide'
+     *  Switch: '<S13>/Switch1'
+     */
+    if (socd_pct_ahSoc <= 0) {
+      /* Sum: '<S4>/Add1' incorporates:
+       *  Constant: '<S13>/Constant4'
+       */
+      socd_pct_ahSoc = 0U;
+    }
+
+    /* End of MinMax: '<S13>/Max' */
+  }
+
+  /* End of Switch: '<S13>/Switch' */
+
+  /* Sum: '<S13>/Add' incorporates:
+   *  Constant: '<S13>/Constant'
+   *  DataTypeConversion: '<S3>/Data Type Conversion'
+   *  DataTypeConversion: '<S3>/Data Type Conversion1'
+   *  Product: '<S13>/Product'
+   *  Product: '<S13>/Product1'
+   *  Sum: '<S13>/Add1'
+   *  Sum: '<S4>/Add1'
+   */
+  tmp_3 = mul_u32_hiSR_near((uint32_T)(uint16_T)(100 - socd_pct_ahSoc) *
+    rtb_DataTypeConversion, 2748779069U, 1U) + mul_u32_hiSR_near((uint32_T)
+    rtb_DataTypeConversion1 * socd_pct_ahSoc, 2748779069U, 1U);
+
+  /* Sum: '<S13>/Add' */
+  rtb_Saturation_l = (uint16_T)(((tmp_3 & 16U) != 0U) + (tmp_3 >> 5));
+
+  /* Saturate: '<S38>/Saturation1' incorporates:
+   *  Constant: '<S38>/Constant'
+   *  Sum: '<S38>/Add'
+   *  UnitDelay: '<S38>/Unit Delay'
+   */
+  if ((uint8_T)(localDW->UnitDelay_DSTATE_m + 1U) < 30) {
+    localDW->UnitDelay_DSTATE_m++;
+  } else {
+    localDW->UnitDelay_DSTATE_m = 30U;
+  }
+
+  /* End of Saturate: '<S38>/Saturation1' */
+
+  /* If: '<S7>/If' incorporates:
+   *  Inport: '<Root>/ihd_st_workStat'
+   *  UnitDelay: '<S38>/Unit Delay'
+   */
+  if ((ihd_st_workStat == 2) && (localDW->UnitDelay_DSTATE_m >= 20)) {
+    /* Outputs for IfAction SubSystem: '<S7>/chrgCCV' incorporates:
+     *  ActionPort: '<S39>/Action Port'
+     */
+    /* Saturate: '<S43>/Saturation' incorporates:
+     *  Constant: '<S43>/Constant'
+     *  Sum: '<S43>/Add'
+     *  UnitDelay: '<S43>/Unit Delay'
+     */
+    if ((uint16_T)(localDW->UnitDelay_DSTATE_h + 1U) < 60000) {
+      rtb_DataTypeConversion1 = (uint16_T)(localDW->UnitDelay_DSTATE_h + 1U);
+    } else {
+      rtb_DataTypeConversion1 = 60000U;
+    }
+
+    /* End of Saturate: '<S43>/Saturation' */
+
+    /* Product: '<S43>/Product' incorporates:
+     *  Inport: '<Root>/ihd_I_curr'
+     *  Inport: '<Root>/ihd_V_cellUMax'
+     *  Lookup_n-D: '<S39>/1-D Lookup Table'
+     *  RelationalOperator: '<S39>/Relational Operator'
+     *  UnitDelay: '<S43>/Unit Delay'
+     */
+    localDW->UnitDelay_DSTATE_h = (uint16_T)(ihd_V_cellUMax >=
+      look1_is16lu16n16tu16_binlcase(ihd_I_curr, rtCP_uDLookupTable_bp01Data,
+      rtCP_uDLookupTable_tableData, 3U) ? (int32_T)rtb_DataTypeConversion1 : 0);
+
+    /* RelationalOperator: '<S43>/Relational Operator1' incorporates:
+     *  Constant: '<S43>/para'
+     */
+    rtb_RelationalOperator1_m = (rtb_DataTypeConversion1 >= 20);
+
+    /* Switch: '<S42>/Switch' incorporates:
+     *  Logic: '<S42>/Logical Operator'
+     *  RelationalOperator: '<S42>/Relational Operator'
+     *  RelationalOperator: '<S42>/Relational Operator1'
+     *  Sum: '<S13>/Add'
+     *  UnitDelay: '<S42>/Unit Delay'
+     *  UnitDelay: '<S42>/Unit Delay1'
+     */
+    if ((!localDW->UnitDelay_DSTATE_iz) && rtb_RelationalOperator1_m) {
+      localDW->UnitDelay1_DSTATE_i = rtb_Saturation_l;
+    }
+
+    /* End of Switch: '<S42>/Switch' */
+
+    /* Switch: '<S39>/Switch' incorporates:
+     *  Saturate: '<S39>/Saturation'
+     *  Sum: '<S13>/Add'
+     */
+    if (rtb_RelationalOperator1_m) {
+      /* Sum: '<S13>/Add' incorporates:
+       *  Constant: '<S39>/Constant'
+       *  Sum: '<S39>/Add1'
+       *  Sum: '<S39>/Add2'
+       *  Switch: '<S42>/Switch'
+       *  UnitDelay: '<S42>/Unit Delay1'
+       */
+      rtb_Saturation_l = (uint16_T)((int16_T)(rtb_Saturation_l -
+        localDW->UnitDelay1_DSTATE_i) + 950);
+    } else {
+      if (rtb_Saturation_l >= 950) {
+        /* Sum: '<S13>/Add' incorporates:
+         *  Saturate: '<S39>/Saturation'
+         */
+        rtb_Saturation_l = 950U;
+      }
+    }
+
+    /* End of Switch: '<S39>/Switch' */
+
+    /* Sum: '<S41>/Add4' incorporates:
+     *  Saturate: '<S41>/Saturation'
+     *  UnitDelay: '<S41>/Unit Delay'
+     */
+    rtb_Saturation_n = (int16_T)(rtb_Saturation_l - localDW->UnitDelay_DSTATE_b);
+
+    /* Saturate: '<S41>/Saturation' */
+    if (rtb_Saturation_n > 1000) {
+      rtb_Saturation_n = 1000;
+    } else {
+      if (rtb_Saturation_n < 0) {
+        rtb_Saturation_n = 0;
+      }
+    }
+
+    /* End of Saturate: '<S41>/Saturation' */
+
+    /* Sum: '<S41>/Add3' incorporates:
+     *  Saturate: '<S41>/Saturation'
+     *  UnitDelay: '<S41>/Unit Delay'
+     */
+    localDW->UnitDelay_DSTATE_b += rtb_Saturation_n;
+
+    /* Sum: '<S13>/Add' incorporates:
+     *  Merge: '<S7>/Merge'
+     *  SignalConversion generated from: '<S39>/socn_pct_estSoc'
+     *  Sum: '<S41>/Add3'
+     *  UnitDelay: '<S41>/Unit Delay'
+     */
+    rtb_Saturation_l = localDW->UnitDelay_DSTATE_b;
+
+    /* Update for UnitDelay: '<S42>/Unit Delay' */
+    localDW->UnitDelay_DSTATE_iz = rtb_RelationalOperator1_m;
+
+    /* End of Outputs for SubSystem: '<S7>/chrgCCV' */
+  } else {
+    if ((ihd_st_workStat != 2) && (localDW->UnitDelay_DSTATE_m >= 20)) {
+      /* Outputs for IfAction SubSystem: '<S7>/disChrgCCV' incorporates:
+       *  ActionPort: '<S40>/Action Port'
+       */
+      /* Saturate: '<S45>/Saturation' incorporates:
+       *  Constant: '<S45>/Constant'
+       *  Sum: '<S45>/Add'
+       *  UnitDelay: '<S45>/Unit Delay'
+       */
+      if ((uint16_T)(localDW->UnitDelay_DSTATE_l + 1U) < 60000) {
+        rtb_DataTypeConversion1 = (uint16_T)(localDW->UnitDelay_DSTATE_l + 1U);
+      } else {
+        rtb_DataTypeConversion1 = 60000U;
+      }
+
+      /* End of Saturate: '<S45>/Saturation' */
+
+      /* Product: '<S45>/Product' incorporates:
+       *  Inport: '<Root>/ihd_I_curr'
+       *  Inport: '<Root>/ihd_V_cellUMin'
+       *  Lookup_n-D: '<S40>/1-D Lookup Table'
+       *  RelationalOperator: '<S40>/Relational Operator'
+       *  UnitDelay: '<S45>/Unit Delay'
+       */
+      localDW->UnitDelay_DSTATE_l = (uint16_T)(ihd_V_cellUMin <=
+        look1_is16lu16n16tu16_binlcase(ihd_I_curr, rtCP_uDLookupTable_bp01Data_g,
+        rtCP_uDLookupTable_tableData_b, 2U) ? (int32_T)rtb_DataTypeConversion1 :
+        0);
+
+      /* RelationalOperator: '<S45>/Relational Operator1' incorporates:
+       *  Constant: '<S45>/para'
+       */
+      rtb_RelationalOperator1_m = (rtb_DataTypeConversion1 >= 20);
+
+      /* Switch: '<S44>/Switch' incorporates:
+       *  Logic: '<S44>/Logical Operator'
+       *  RelationalOperator: '<S44>/Relational Operator'
+       *  RelationalOperator: '<S44>/Relational Operator1'
+       *  Sum: '<S13>/Add'
+       *  UnitDelay: '<S44>/Unit Delay'
+       *  UnitDelay: '<S44>/Unit Delay1'
+       */
+      if ((!localDW->UnitDelay_DSTATE_cu) && rtb_RelationalOperator1_m) {
+        localDW->UnitDelay1_DSTATE_o = rtb_Saturation_l;
+      }
+
+      /* End of Switch: '<S44>/Switch' */
+
+      /* Switch: '<S40>/Switch1' incorporates:
+       *  Saturate: '<S40>/Saturation'
+       *  Sum: '<S13>/Add'
+       */
+      if (rtb_RelationalOperator1_m) {
+        /* Sum: '<S13>/Add' incorporates:
+         *  Constant: '<S40>/Constant1'
+         *  Merge: '<S7>/Merge'
+         *  Sum: '<S40>/Add1'
+         *  Sum: '<S40>/Add2'
+         *  Switch: '<S44>/Switch'
+         *  UnitDelay: '<S44>/Unit Delay1'
+         */
+        rtb_Saturation_l = (uint16_T)((int16_T)(rtb_Saturation_l -
+          localDW->UnitDelay1_DSTATE_o) + 50);
+      } else if (rtb_Saturation_l > 1000) {
+        /* Sum: '<S13>/Add' incorporates:
+         *  Merge: '<S7>/Merge'
+         *  Saturate: '<S40>/Saturation'
+         */
+        rtb_Saturation_l = 1000U;
+      } else {
+        if (rtb_Saturation_l < 50) {
+          /* Sum: '<S13>/Add' incorporates:
+           *  Merge: '<S7>/Merge'
+           *  Saturate: '<S40>/Saturation'
+           */
+          rtb_Saturation_l = 50U;
+        }
+      }
+
+      /* End of Switch: '<S40>/Switch1' */
+
+      /* Update for UnitDelay: '<S44>/Unit Delay' */
+      localDW->UnitDelay_DSTATE_cu = rtb_RelationalOperator1_m;
+
+      /* End of Outputs for SubSystem: '<S7>/disChrgCCV' */
+    }
+  }
+
+  /* End of If: '<S7>/If' */
+
+  /* Switch: '<S6>/Switch' */
+  if (rtb_RelationalOperator1_ii || (!(rtb_Saturation_l < 1000))) {
+    /* Sum: '<S13>/Add' incorporates:
+     *  Saturate: '<S6>/Saturation'
+     */
+    rtb_Saturation_l = 1000U;
+  }
+
+  /* End of Switch: '<S6>/Switch' */
+
+  /* Sum: '<S6>/Add' incorporates:
+   *  Product: '<S4>/Divide1'
+   *  Saturate: '<S6>/Saturation'
+   *  UnitDelay: '<S6>/Unit Delay7'
+   */
+  rtb_Saturation_n = (int16_T)(rtb_Saturation_l - localDW->UnitDelay7_DSTATE);
+
+  /* Abs: '<S6>/Abs' incorporates:
+   *  Product: '<S4>/Divide1'
+   */
+  if (rtb_Saturation_n < 0) {
+    rtb_Saturation_n = (int16_T)-rtb_Saturation_n;
+  }
+
+  /* End of Abs: '<S6>/Abs' */
+
+  /* Switch: '<S6>/Switch1' incorporates:
+   *  Constant: '<S6>/Constant3'
+   *  Constant: '<S6>/Constant4'
+   *  Constant: '<S6>/Constant5'
+   *  Constant: '<S6>/Constant6'
+   *  Inport: '<Root>/ihd_st_workStat'
+   *  Logic: '<S6>/Logical Operator'
+   *  Logic: '<S6>/Logical Operator1'
+   *  Logic: '<S6>/Logical Operator2'
+   *  Product: '<S4>/Divide1'
+   *  RelationalOperator: '<S6>/Relational Operator1'
+   *  RelationalOperator: '<S6>/Relational Operator2'
+   *  RelationalOperator: '<S6>/Relational Operator3'
+   *  RelationalOperator: '<S6>/Relational Operator4'
+   *  RelationalOperator: '<S6>/Relational Operator6'
+   *  Saturate: '<S6>/Saturation'
+   *  Switch: '<S6>/Switch2'
+   *  UnitDelay: '<S6>/Unit Delay'
+   *  UnitDelay: '<S6>/Unit Delay1'
+   *  UnitDelay: '<S6>/Unit Delay2'
+   *  UnitDelay: '<S6>/Unit Delay3'
+   */
+  if (localDW->UnitDelay_DSTATE_j || ((localDW->UnitDelay1_DSTATE_a == 2) &&
+       (ihd_st_workStat != 2)) || ((localDW->UnitDelay2_DSTATE_d != 2) &&
+       (ihd_st_workStat == 2)) || (rtb_Saturation_n > 20)) {
+    localDW->UnitDelay3_DSTATE_l = rtb_Saturation_l;
+
+    /* Switch: '<S6>/Switch4' incorporates:
+     *  Merge: '<S2>/Merge1'
+     *  Saturate: '<S6>/Saturation'
+     *  Switch: '<S6>/Switch1'
+     *  Switch: '<S6>/Switch2'
+     *  UnitDelay: '<S6>/Unit Delay3'
+     *  UnitDelay: '<S6>/Unit Delay4'
+     *  UnitDelay: '<S6>/Unit Delay5'
+     *  UnitDelay: '<S6>/Unit Delay6'
+     */
+    if (localDW->UnitDelay5_DSTATE) {
+      localDW->UnitDelay4_DSTATE = localB->Merge1;
+    } else {
+      localDW->UnitDelay4_DSTATE = localDW->UnitDelay6_DSTATE;
+    }
+
+    /* End of Switch: '<S6>/Switch4' */
+  }
+
+  /* End of Switch: '<S6>/Switch1' */
+
+  /* Switch: '<S6>/Switch3' incorporates:
+   *  Constant: '<S6>/Constant7'
+   *  Inport: '<Root>/ihd_st_workStat'
+   *  RelationalOperator: '<S6>/Relational Operator5'
+   *  S-Function (sfix_look1_dyn): '<S6>/Lookup Table Dynamic'
+   *  S-Function (sfix_look1_dyn): '<S6>/Lookup Table Dynamic1'
+   */
+  if (ihd_st_workStat == 2) {
+    /* MinMax: '<S6>/Max3' incorporates:
+     *  Switch: '<S6>/Switch2'
+     *  UnitDelay: '<S6>/Unit Delay4'
+     */
+    if (localDW->UnitDelay4_DSTATE < 999) {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' */
+      rtb_TmpSignalConversionAtLook_g[0] = localDW->UnitDelay4_DSTATE;
+    } else {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' incorporates:
+       *  Constant: '<S6>/Constant18'
+       */
+      rtb_TmpSignalConversionAtLook_g[0] = 999U;
+    }
+
+    /* End of MinMax: '<S6>/Max3' */
+
+    /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' incorporates:
+     *  Constant: '<S6>/Constant8'
+     */
+    rtb_TmpSignalConversionAtLook_g[1] = 1000U;
+
+    /* MinMax: '<S6>/Max2' incorporates:
+     *  Switch: '<S6>/Switch1'
+     *  UnitDelay: '<S6>/Unit Delay3'
+     */
+    if (localDW->UnitDelay3_DSTATE_l < 999) {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' */
+      rtb_TmpSignalConversionAtLook_j[0] = localDW->UnitDelay3_DSTATE_l;
+    } else {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' incorporates:
+       *  Constant: '<S6>/Constant17'
+       */
+      rtb_TmpSignalConversionAtLook_j[0] = 999U;
+    }
+
+    /* End of MinMax: '<S6>/Max2' */
+
+    /* SignalConversion generated from: '<S6>/Lookup Table Dynamic' incorporates:
+     *  Constant: '<S6>/Constant9'
+     */
+    rtb_TmpSignalConversionAtLook_j[1] = 1000U;
+
+    /* S-Function (sfix_look1_dyn): '<S6>/Lookup Table Dynamic' */
+    /* Dynamic Look-Up Table Block: '<S6>/Lookup Table Dynamic'
+     * Input0  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Input1  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Input2  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Output0 Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Lookup Method: Linear_Endpoint
+     *
+     */
+    LookUp_U16_U16( &(rtb_LookupTableDynamic), &rtb_TmpSignalConversionAtLook_g
+                   [0], rtb_Saturation_l, &rtb_TmpSignalConversionAtLook_j[0],
+                   1U);
+    rtb_DataTypeConversion1 = rtb_LookupTableDynamic;
+  } else {
+    /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' incorporates:
+     *  Constant: '<S6>/Constant10'
+     */
+    rtb_TmpSignalConversionAtLookup[0] = 0U;
+
+    /* MinMax: '<S6>/Max1' incorporates:
+     *  Switch: '<S6>/Switch2'
+     *  UnitDelay: '<S6>/Unit Delay4'
+     */
+    if (localDW->UnitDelay4_DSTATE > 10) {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' */
+      rtb_TmpSignalConversionAtLookup[1] = localDW->UnitDelay4_DSTATE;
+    } else {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' incorporates:
+       *  Constant: '<S6>/Constant15'
+       */
+      rtb_TmpSignalConversionAtLookup[1] = 10U;
+    }
+
+    /* End of MinMax: '<S6>/Max1' */
+
+    /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' incorporates:
+     *  Constant: '<S6>/Constant11'
+     */
+    rtb_TmpSignalConversionAtLook_h[0] = 0U;
+
+    /* MinMax: '<S6>/Max' incorporates:
+     *  Switch: '<S6>/Switch1'
+     *  UnitDelay: '<S6>/Unit Delay3'
+     */
+    if (localDW->UnitDelay3_DSTATE_l > 10) {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' */
+      rtb_TmpSignalConversionAtLook_h[1] = localDW->UnitDelay3_DSTATE_l;
+    } else {
+      /* SignalConversion generated from: '<S6>/Lookup Table Dynamic1' incorporates:
+       *  Constant: '<S6>/Constant14'
+       */
+      rtb_TmpSignalConversionAtLook_h[1] = 10U;
+    }
+
+    /* End of MinMax: '<S6>/Max' */
+
+    /* S-Function (sfix_look1_dyn): '<S6>/Lookup Table Dynamic1' */
+    /* Dynamic Look-Up Table Block: '<S6>/Lookup Table Dynamic1'
+     * Input0  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Input1  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Input2  Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Output0 Data Type:  Fixed Point    U16  2^-4  FSlope 1.6
+     * Lookup Method: Linear_Endpoint
+     *
+     */
+    LookUp_U16_U16( &(rtb_LookupTableDynamic1),
+                   &rtb_TmpSignalConversionAtLookup[0], rtb_Saturation_l,
+                   &rtb_TmpSignalConversionAtLook_h[0], 1U);
+    rtb_DataTypeConversion1 = rtb_LookupTableDynamic1;
+  }
+
+  /* End of Switch: '<S6>/Switch3' */
+
+  /* Sum: '<S32>/Add6' incorporates:
+   *  Switch: '<S6>/Switch3'
+   *  UnitDelay: '<S32>/Unit Delay3'
+   */
+  rtb_Saturation_n = (int16_T)(rtb_DataTypeConversion1 -
+    localDW->UnitDelay3_DSTATE_p);
+
+  /* Switch: '<S32>/Switch' incorporates:
+   *  If: '<S32>/If'
+   *  Logic: '<S32>/Logical Operator'
+   *  RelationalOperator: '<S32>/Relational Operator'
+   *  RelationalOperator: '<S32>/Relational Operator1'
+   *  RelationalOperator: '<S32>/Relational Operator2'
+   *  Sum: '<S32>/Add6'
+   */
+  if (rtb_Saturation_n > 1) {
+    /* Outputs for IfAction SubSystem: '<S32>/If Action Subsystem' incorporates:
+     *  ActionPort: '<S34>/Action Port'
+     */
+    /* If: '<S32>/If' incorporates:
+     *  Merge: '<S32>/Merge'
+     *  MinMax: '<S34>/Min1'
+     *  Sum: '<S34>/Add3'
+     *  Sum: '<S34>/Add4'
+     *  Switch: '<S6>/Switch3'
+     *  UnitDelay: '<S32>/Unit Delay3'
+     */
+    i = (int16_T)(rtb_DataTypeConversion1 - localDW->UnitDelay3_DSTATE_p);
+    if (i >= 1) {
+      i = 1;
+    }
+
+    localDW->UnitDelay3_DSTATE_p = (uint16_T)((uint32_T)(uint16_T)i +
+      localDW->UnitDelay3_DSTATE_p);
+
+    /* End of Outputs for SubSystem: '<S32>/If Action Subsystem' */
+  } else if ((rtb_Saturation_n < -1) && (rtb_Saturation_n > -1000)) {
+    /* Outputs for IfAction SubSystem: '<S32>/If Action Subsystem1' incorporates:
+     *  ActionPort: '<S35>/Action Port'
+     */
+    /* If: '<S32>/If' incorporates:
+     *  Constant: '<S35>/Constant4'
+     *  Merge: '<S32>/Merge'
+     *  MinMax: '<S35>/Min1'
+     *  Sum: '<S35>/Add3'
+     *  Sum: '<S35>/Add4'
+     *  Switch: '<S6>/Switch3'
+     *  UnitDelay: '<S32>/Unit Delay3'
+     */
+    rtb_Saturation_n = (int16_T)(rtb_DataTypeConversion1 -
+      localDW->UnitDelay3_DSTATE_p);
+    if (rtb_Saturation_n <= -1) {
+      rtb_Saturation_n = -1;
+    }
+
+    localDW->UnitDelay3_DSTATE_p += rtb_Saturation_n;
+
+    /* End of Outputs for SubSystem: '<S32>/If Action Subsystem1' */
+  } else {
+    /* Outputs for IfAction SubSystem: '<S32>/If Action Subsystem2' incorporates:
+     *  ActionPort: '<S36>/Action Port'
+     */
+    /* If: '<S32>/If' incorporates:
+     *  Inport: '<S36>/In1'
+     *  Merge: '<S32>/Merge'
+     *  Switch: '<S6>/Switch3'
+     *  UnitDelay: '<S32>/Unit Delay3'
+     */
+    localDW->UnitDelay3_DSTATE_p = rtb_DataTypeConversion1;
+
+    /* End of Outputs for SubSystem: '<S32>/If Action Subsystem2' */
+  }
+
+  /* End of Switch: '<S32>/Switch' */
+
+  /* SignalConversion: '<S6>/Signal Conversion' incorporates:
+   *  Saturate: '<S6>/Saturation'
+   */
+  socd_pct_battSoc = rtb_Saturation_l;
+
+  /* SignalConversion: '<S6>/Signal Conversion1' incorporates:
+   *  Saturate: '<S6>/Saturation'
+   */
+  socd_pct_battSocEo = rtb_Saturation_l;
+
+  /* Switch: '<S6>/Switch5' */
+  if (rtb_RelationalOperator1_ii) {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Constant: '<S6>/Constant13'
+     *  Sum: '<S4>/Add1'
+     */
+    socd_pct_ahSoc = 1000U;
+  } else {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Merge: '<S32>/Merge'
+     *  Sum: '<S4>/Add1'
+     *  UnitDelay: '<S32>/Unit Delay3'
+     */
+    socd_pct_ahSoc = localDW->UnitDelay3_DSTATE_p;
+  }
+
+  /* End of Switch: '<S6>/Switch5' */
+
+  /* Saturate: '<S6>/Saturation1' incorporates:
+   *  Sum: '<S4>/Add1'
+   *  UnitDelay: '<S6>/Unit Delay6'
+   */
+  if (socd_pct_ahSoc < 1000) {
+    localDW->UnitDelay6_DSTATE = socd_pct_ahSoc;
+  } else {
+    localDW->UnitDelay6_DSTATE = 1000U;
+  }
+
+  /* End of Saturate: '<S6>/Saturation1' */
+
+  /* SignalConversion: '<S6>/Signal Conversion2' incorporates:
+   *  Saturate: '<S6>/Saturation1'
+   *  UnitDelay: '<S6>/Unit Delay6'
+   */
+  socd_pct_bcuSoc = localDW->UnitDelay6_DSTATE;
+
+  /* SignalConversion: '<S6>/Signal Conversion3' incorporates:
+   *  Saturate: '<S6>/Saturation1'
+   *  UnitDelay: '<S6>/Unit Delay6'
+   */
+  socd_pct_bcuSocEo = localDW->UnitDelay6_DSTATE;
+
+  /* Product: '<S33>/Product' incorporates:
+   *  Inport: '<Root>/ihd_V_cellUMax'
+   *  RelationalOperator: '<S6>/Relational Operator'
+   *  UnitDelay: '<S33>/Unit Delay'
+   */
+  localDW->UnitDelay_DSTATE_i = (uint16_T)(ihd_V_cellUMax >= 4200 ? (int32_T)
+    rtb_Saturation_j : 0);
+
+  /* Sum: '<S4>/Add' incorporates:
+   *  Inport: '<Root>/ihd_I_curr'
+   *  UnitDelay: '<S4>/Unit Delay1'
+   */
+  localDW->UnitDelay1_DSTATE_b += ihd_I_curr;
+
+  /* Product: '<S13>/Divide' incorporates:
+   *  Constant: '<S4>/Constant1'
+   *  Product: '<S4>/Divide'
+   *  Product: '<S4>/Divide1'
+   *  Product: '<S5>/Divide'
+   *  Sum: '<S4>/Add'
+   *  Sum: '<S4>/Add1'
+   *  Switch: '<S5>/Switch'
+   *  UnitDelay: '<S4>/Unit Delay1'
+   */
+  socd_pct_ahSoc = (uint16_T)((int16_T)((div_repeat_s16s32_floor
+    (div_nde_s32_floor(localDW->UnitDelay1_DSTATE_b, 360), localB->Divide, 3U) *
+    5) >> 2) + localB->Switch);
+
+  /* Saturate: '<S4>/Saturation' incorporates:
+   *  Sum: '<S4>/Add1'
+   */
+  if (socd_pct_ahSoc >= 1000) {
+    /* Product: '<S13>/Divide' incorporates:
+     *  Saturate: '<S4>/Saturation'
+     */
+    socd_pct_ahSoc = 1000U;
+  }
+
+  /* End of Saturate: '<S4>/Saturation' */
+
+  /* Update for UnitDelay: '<S1>/Unit Delay' incorporates:
+   *  Constant: '<S1>/Constant'
+   */
+  localDW->UnitDelay_DSTATE_et = false;
+
+  /* Update for UnitDelay: '<S1>/Unit Delay1' incorporates:
+   *  Constant: '<S1>/Constant1'
+   */
+  localDW->UnitDelay1_DSTATE_c = false;
+
+  /* Update for UnitDelay: '<S14>/Unit Delay' incorporates:
+   *  Constant: '<S14>/Constant'
+   */
+  localDW->UnitDelay_DSTATE_c = 1.0;
+
+  /* Update for UnitDelay: '<S23>/Unit Delay' incorporates:
+   *  Constant: '<S23>/Constant'
+   */
+  localDW->UnitDelay_DSTATE_e = 1.0;
+
+  /* Update for SignalConversion generated from: '<S28>/Product1' incorporates:
+   *  UnitDelay: '<S12>/Unit Delay2'
+   */
+  localDW->UnitDelay2_DSTATE = localDW->UnitDelay3_DSTATE[1];
+
+  /* Update for UnitDelay: '<S23>/Unit Delay1' incorporates:
+   *  Constant: '<S23>/Constant1'
+   */
+  localDW->UnitDelay1_DSTATE_h = 1.0;
+
+  /* Update for Switch: '<S14>/Switch1' incorporates:
+   *  UnitDelay: '<S11>/Unit Delay2'
+   */
+  localDW->UnitDelay2_DSTATE_k = localDW->UnitDelay3_DSTATE_g[1];
+
+  /* Update for UnitDelay: '<S14>/Unit Delay1' incorporates:
+   *  Constant: '<S14>/Constant1'
+   */
+  localDW->UnitDelay1_DSTATE_l = 1.0;
+
+  /* Update for UnitDelay: '<S12>/Unit Delay3' incorporates:
+   *  Product: '<S26>/Divide'
+   */
+  localDW->UnitDelay3_DSTATE[0] = rtb_Divide_n[0];
+
+  /* Update for UnitDelay: '<S11>/Unit Delay3' incorporates:
+   *  Product: '<S17>/Divide'
+   */
+  localDW->UnitDelay3_DSTATE_g[0] = rtb_Divide[0];
+
+  /* Update for UnitDelay: '<S12>/Unit Delay3' */
+  localDW->UnitDelay3_DSTATE[1] = rtb_Add1_tmp;
+
+  /* Update for UnitDelay: '<S11>/Unit Delay3' */
+  localDW->UnitDelay3_DSTATE_g[1] = rtb_Divide_a;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay' incorporates:
+   *  Constant: '<S6>/Constant2'
+   */
+  localDW->UnitDelay_DSTATE_j = false;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay1' incorporates:
+   *  Inport: '<Root>/ihd_st_workStat'
+   */
+  localDW->UnitDelay1_DSTATE_a = ihd_st_workStat;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay2' incorporates:
+   *  Inport: '<Root>/ihd_st_workStat'
+   */
+  localDW->UnitDelay2_DSTATE_d = ihd_st_workStat;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay7' incorporates:
+   *  Saturate: '<S6>/Saturation'
+   */
+  localDW->UnitDelay7_DSTATE = rtb_Saturation_l;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay5' incorporates:
+   *  Constant: '<S6>/Constant12'
+   */
+  localDW->UnitDelay5_DSTATE = false;
+}
+
+/* Model initialize function */
+void SOC_initialize(const char_T **rt_errorStatus, RT_MODEL_SOC_T *const SOC_M)
+{
+  /* Registration code */
+
+  /* initialize error status */
+  rtmSetErrorStatusPointer(SOC_M, rt_errorStatus);
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/SOH.c

@@ -0,0 +1,530 @@
+/*
+ * File: SOH.c
+ *
+ * Code generated for Simulink model 'SOH'.
+ *
+ * Model version                  : 1.14
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:32 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#include "SOH.h"
+#include "SOH_private.h"
+#include "div_nde_s32_floor.h"
+#include "look1_iu16lu16n16tu16_binlcase.h"
+
+/* System initialize for referenced model: 'SOH' */
+void SOH_Init(DW_SOH_f_T *localDW)
+{
+  /* InitializeConditions for UnitDelay: '<S4>/Unit Delay1' */
+  localDW->UnitDelay1_DSTATE_m = true;
+
+  /* SystemInitialize for Chart: '<S3>/Chart' */
+  localDW->flg = true;
+}
+
+/* Output and update for referenced model: 'SOH' */
+void SOH(B_SOH_c_T *localB, DW_SOH_f_T *localDW)
+{
+  int32_T i_0;
+  int32_T tmp;
+  uint32_T tmp_1;
+  int16_T tmp_0;
+  uint16_T rtb_Divide2[28];
+  uint16_T rtb_Merge1[28];
+  uint16_T rtb_Merge3[10];
+  uint16_T rtb_Divide2_i;
+  uint16_T rtb_Merge2;
+  uint16_T tmp_2;
+  uint8_T i;
+  boolean_T rtb_RelationalOperator2;
+  boolean_T rtb_RelationalOperator_e;
+
+  /* Logic: '<S6>/Logical Operator' incorporates:
+   *  Constant: '<S6>/Constant'
+   *  Constant: '<S6>/Constant1'
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   *  RelationalOperator: '<S6>/Relational Operator'
+   *  RelationalOperator: '<S6>/Relational Operator1'
+   *  UnitDelay: '<S6>/Unit Delay'
+   */
+  rtb_RelationalOperator_e = ((localDW->UnitDelay_DSTATE_e != 2) &&
+    (ihd_st_workStat == 2));
+  for (i_0 = 0; i_0 < 28; i_0++) {
+    /* Switch: '<S6>/Switch' */
+    if (rtb_RelationalOperator_e) {
+      /* Switch: '<S6>/Switch' incorporates:
+       *  Inport: '<Root>/ihv_V_cellU'
+       */
+      sohv_V_chrgStartStatEo[i_0] = ihv_V_cellU[i_0];
+    } else {
+      /* Switch: '<S6>/Switch' incorporates:
+       *  Product: '<S13>/Divide3'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      sohv_V_chrgStartStatEo[i_0] = localDW->UnitDelay1_DSTATE_i[i_0];
+    }
+
+    /* End of Switch: '<S6>/Switch' */
+  }
+
+  /* Abs: '<S6>/Abs' incorporates:
+   *  Inport: '<Root>/ihd_I_curr'
+   */
+  if (ihd_I_curr < 0) {
+    tmp_0 = (int16_T)-ihd_I_curr;
+  } else {
+    tmp_0 = ihd_I_curr;
+  }
+
+  /* End of Abs: '<S6>/Abs' */
+
+  /* RelationalOperator: '<S6>/Relational Operator2' */
+  rtb_RelationalOperator2 = (tmp_0 >= 20);
+
+  /* Outputs for Resettable SubSystem: '<S6>/Resettable Subsystem' incorporates:
+   *  ResetPort: '<S9>/Reset'
+   */
+  if (rtb_RelationalOperator2) {
+    /* InitializeConditions for UnitDelay: '<S9>/Unit Delay' */
+    localDW->UnitDelay_DSTATE_o = 0U;
+  }
+
+  /* Sum: '<S9>/Add' incorporates:
+   *  Constant: '<S9>/Constant'
+   *  UnitDelay: '<S9>/Unit Delay'
+   */
+  localDW->UnitDelay_DSTATE_o++;
+
+  /* End of Outputs for SubSystem: '<S6>/Resettable Subsystem' */
+
+  /* Switch: '<S10>/Switch3' incorporates:
+   *  UnitDelay: '<S10>/Unit Delay3'
+   */
+  localDW->UnitDelay3_DSTATE = (rtb_RelationalOperator2 ||
+    localDW->UnitDelay3_DSTATE);
+
+  /* Switch: '<S6>/Switch2' incorporates:
+   *  Constant: '<S9>/Constant1'
+   *  Product: '<S9>/Divide'
+   *  Sum: '<S6>/Add'
+   *  UnitDelay: '<S6>/Unit Delay2'
+   *  UnitDelay: '<S9>/Unit Delay'
+   */
+  if (rtb_RelationalOperator_e) {
+    /* Switch: '<S6>/Switch1' incorporates:
+     *  Constant: '<S6>/Constant3'
+     *  Inport: '<Root>/ihd_tm_parkTime'
+     *  UnitDelay: '<S10>/Unit Delay3'
+     */
+    if (localDW->UnitDelay3_DSTATE) {
+      tmp_1 = 0U;
+    } else {
+      tmp_1 = ihd_tm_parkTime;
+    }
+
+    /* End of Switch: '<S6>/Switch1' */
+
+    /* Outputs for Resettable SubSystem: '<S6>/Resettable Subsystem' incorporates:
+     *  ResetPort: '<S9>/Reset'
+     */
+    localDW->UnitDelay2_DSTATE = (uint16_T)(localDW->UnitDelay_DSTATE_o / 10U +
+      tmp_1);
+
+    /* End of Outputs for SubSystem: '<S6>/Resettable Subsystem' */
+  }
+
+  /* End of Switch: '<S6>/Switch2' */
+
+  /* Saturate: '<S6>/Saturation' incorporates:
+   *  UnitDelay: '<S6>/Unit Delay2'
+   */
+  sohd_tm_chrgStartStatEo = localDW->UnitDelay2_DSTATE;
+
+  /* If: '<S5>/If' incorporates:
+   *  Inport: '<Root>/sohd_Q_chrgEi '
+   *  Inport: '<Root>/sohd_flg_chrgEndEi '
+   *  Inport: '<Root>/sohv_Q_packCapArrEi '
+   *  Inport: '<Root>/sohv_V_chrgStartStatEi '
+   *  Inport: '<S16>/sohd_Q_chrgEi '
+   *  Inport: '<S16>/sohd_flg_chrgEndEi '
+   *  Inport: '<S16>/sohv_Q_packCapArrEi '
+   *  Inport: '<S16>/sohv_V_chrgStartStatEi '
+   *  Merge: '<S5>/Merge1'
+   *  Merge: '<S5>/Merge2'
+   *  Merge: '<S5>/Merge3'
+   *  RelationalOperator: '<S14>/Relational Operator2'
+   */
+  if (sohd_Q_chrgEi < 300) {
+    /* Outputs for IfAction SubSystem: '<S5>/TureAction' incorporates:
+     *  ActionPort: '<S16>/Action Port'
+     */
+    rtb_RelationalOperator_e = sohd_flg_chrgEndEi;
+    for (i_0 = 0; i_0 < 28; i_0++) {
+      rtb_Merge1[i_0] = sohv_V_chrgStartStatEi[i_0];
+    }
+
+    rtb_Merge2 = sohd_Q_chrgEi;
+    for (i_0 = 0; i_0 < 10; i_0++) {
+      rtb_Merge3[i_0] = sohv_Q_packCapArrEi[i_0];
+    }
+
+    /* End of Outputs for SubSystem: '<S5>/TureAction' */
+  } else {
+    /* Outputs for IfAction SubSystem: '<S5>/FalseAction' incorporates:
+     *  ActionPort: '<S15>/Action Port'
+     */
+    /* SignalConversion generated from: '<S15>/sohn_V_chrgStartStatEE1' incorporates:
+     *  Merge: '<S5>/Merge1'
+     */
+    for (i_0 = 0; i_0 < 28; i_0++) {
+      rtb_Merge1[i_0] = 0U;
+    }
+
+    /* End of SignalConversion generated from: '<S15>/sohn_V_chrgStartStatEE1' */
+
+    /* Product: '<S15>/Product' incorporates:
+     *  Constant: '<S15>/Constant2'
+     *  Constant: '<S15>/Constant5'
+     *  Merge: '<S5>/Merge3'
+     */
+    for (i_0 = 0; i_0 < 10; i_0++) {
+      rtb_Merge3[i_0] = 299U;
+    }
+
+    /* End of Product: '<S15>/Product' */
+
+    /* SignalConversion generated from: '<S15>/sohn_flg_chrgEndEE1' incorporates:
+     *  Constant: '<S15>/Constant'
+     */
+    rtb_RelationalOperator_e = false;
+
+    /* SignalConversion generated from: '<S15>/sohn_Q_chrgEE1' incorporates:
+     *  Constant: '<S15>/Constant3'
+     *  Merge: '<S5>/Merge2'
+     */
+    rtb_Merge2 = 0U;
+
+    /* End of Outputs for SubSystem: '<S5>/FalseAction' */
+  }
+
+  /* End of If: '<S5>/If' */
+
+  /* Logic: '<S4>/Logical Operator' incorporates:
+   *  Inport: '<Root>/ihd_tm_parkTime'
+   *  Merge: '<S5>/Merge2'
+   *  RelationalOperator: '<S4>/Relational Operator'
+   *  RelationalOperator: '<S4>/Relational Operator1'
+   *  UnitDelay: '<S4>/Unit Delay1'
+   */
+  rtb_RelationalOperator_e = ((ihd_tm_parkTime >= 1800U) &&
+    rtb_RelationalOperator_e && (rtb_Merge2 >= 150) &&
+    localDW->UnitDelay1_DSTATE_m);
+
+  /* Outputs for Enabled SubSystem: '<S3>/Subsystem' incorporates:
+   *  EnablePort: '<S13>/Enable'
+   */
+  if (rtb_RelationalOperator_e) {
+    for (i_0 = 0; i_0 < 28; i_0++) {
+      /* Lookup_n-D: '<S13>/1-D Lookup Table1' incorporates:
+       *  Merge: '<S5>/Merge1'
+       *  Product: '<S13>/Divide3'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      localDW->UnitDelay1_DSTATE_i[i_0] = look1_iu16lu16n16tu16_binlcase
+        (rtb_Merge1[i_0], rtCP_uDLookupTable1_bp01Data,
+         rtCP_uDLookupTable1_tableData, 12U);
+
+      /* Lookup_n-D: '<S13>/1-D Lookup Table2' incorporates:
+       *  Inport: '<Root>/ihv_V_cellU'
+       */
+      rtb_Divide2_i = look1_iu16lu16n16tu16_binlcase(ihv_V_cellU[i_0],
+        rtCP_uDLookupTable2_bp01Data, rtCP_uDLookupTable2_tableData, 12U);
+
+      /* Product: '<S13>/Divide4' incorporates:
+       *  Product: '<S13>/Divide2'
+       *  Product: '<S13>/Divide3'
+       *  Sum: '<S13>/Add'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      localDW->UnitDelay1_DSTATE_i[i_0] = (uint16_T)((((uint32_T)(uint16_T)
+        (rtb_Divide2_i - localDW->UnitDelay1_DSTATE_i[i_0]) << 6) / 125U * 125U)
+        >> 6);
+
+      /* Product: '<S13>/Divide1' incorporates:
+       *  Product: '<S13>/Divide3'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      tmp = localDW->UnitDelay1_DSTATE_i[i_0];
+
+      /* Product: '<S13>/Divide1' incorporates:
+       *  Merge: '<S5>/Merge2'
+       */
+      localB->Divide1[i_0] = (uint16_T)(((uint16_T)((uint32_T)tmp == 0U ?
+        MAX_uint32_T : ((uint32_T)rtb_Merge2 << 9) / tmp) * 125U) >> 6);
+
+      /* Product: '<S13>/Divide5' */
+      rtb_Divide2_i = (uint16_T)((((uint32_T)rtb_Divide2_i << 6) / 125U * 125U) >>
+        6);
+
+      /* Product: '<S13>/Divide3' incorporates:
+       *  Constant: '<S13>/Constant3'
+       *  Product: '<S13>/Divide1'
+       *  Sum: '<S13>/Add1'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      localDW->UnitDelay1_DSTATE_i[i_0] = (uint16_T)(((uint16_T)(((uint32_T)
+        (uint16_T)(1000 - rtb_Divide2_i) * localB->Divide1[i_0]) >> 10) * 16777U)
+        >> 14);
+
+      /* Lookup_n-D: '<S13>/1-D Lookup Table2' incorporates:
+       *  Product: '<S13>/Divide1'
+       *  Product: '<S13>/Divide2'
+       */
+      rtb_Divide2[i_0] = (uint16_T)(((uint16_T)(((uint32_T)localB->Divide1[i_0] *
+        rtb_Divide2_i) >> 10) * 16777U) >> 14);
+    }
+
+    /* MinMax: '<S13>/Min1' incorporates:
+     *  Product: '<S13>/Divide2'
+     */
+    rtb_Merge2 = rtb_Divide2[0];
+
+    /* MinMax: '<S13>/Min' incorporates:
+     *  Product: '<S13>/Divide3'
+     *  UnitDelay: '<S6>/Unit Delay1'
+     */
+    rtb_Divide2_i = localDW->UnitDelay1_DSTATE_i[0];
+    for (i_0 = 0; i_0 < 27; i_0++) {
+      /* MinMax: '<S13>/Min1' incorporates:
+       *  Product: '<S13>/Divide2'
+       */
+      tmp_2 = rtb_Divide2[i_0 + 1];
+      if (rtb_Merge2 >= tmp_2) {
+        rtb_Merge2 = tmp_2;
+      }
+
+      /* MinMax: '<S13>/Min' incorporates:
+       *  Product: '<S13>/Divide3'
+       *  UnitDelay: '<S6>/Unit Delay1'
+       */
+      tmp_2 = localDW->UnitDelay1_DSTATE_i[i_0 + 1];
+      if (rtb_Divide2_i >= tmp_2) {
+        rtb_Divide2_i = tmp_2;
+      }
+    }
+
+    /* Sum: '<S13>/Add2' incorporates:
+     *  MinMax: '<S13>/Min'
+     *  MinMax: '<S13>/Min1'
+     */
+    localB->Add2 = (uint16_T)((uint32_T)rtb_Divide2_i + rtb_Merge2);
+  }
+
+  /* End of Outputs for SubSystem: '<S3>/Subsystem' */
+  for (i_0 = 0; i_0 < 28; i_0++) {
+    /* SignalConversion generated from: '<S3>/Subsystem' incorporates:
+     *  Product: '<S13>/Divide1'
+     */
+    sohv_Q_cellCap[i_0] = localB->Divide1[i_0];
+  }
+
+  /* Chart: '<S3>/Chart' incorporates:
+   *  Merge: '<S5>/Merge3'
+   *  Sum: '<S13>/Add2'
+   */
+  i = 0U;
+  if (localDW->flg) {
+    for (i_0 = 0; i_0 < 10; i_0++) {
+      localB->sohn_Q_packCapArrEo[i_0] = rtb_Merge3[i_0];
+    }
+
+    tmp = rtb_Merge3[9] - localB->Add2;
+    if (tmp < 0) {
+      tmp = -tmp;
+    }
+
+    if (rtb_RelationalOperator_e && (tmp < 50)) {
+      while (i < 9) {
+        localB->sohn_Q_packCapArrEo[i] = rtb_Merge3[i + 1];
+        i++;
+      }
+
+      localB->sohn_Q_packCapArrEo[9] = localB->Add2;
+    }
+
+    i = 0U;
+    rtb_Merge2 = 0U;
+    while (i < 10) {
+      tmp = rtb_Merge2 + localB->sohn_Q_packCapArrEo[i];
+      if (tmp > 65535) {
+        tmp = 65535;
+      }
+
+      rtb_Merge2 = (uint16_T)tmp;
+      i++;
+    }
+
+    localB->Qavrg = (uint16_T)(rtb_Merge2 / 10U);
+  }
+
+  localDW->flg = false;
+
+  /* End of Chart: '<S3>/Chart' */
+  for (i_0 = 0; i_0 < 10; i_0++) {
+    /* SignalConversion generated from: '<S3>/Chart' */
+    sohv_Q_packCapArrEo[i_0] = localB->sohn_Q_packCapArrEo[i_0];
+  }
+
+  /* UnitDelay: '<S7>/Unit Delay1' incorporates:
+   *  Product: '<S3>/Divide'
+   *  Product: '<S3>/Product'
+   */
+  sohd_pct_bcuSoh = (uint16_T)((((uint32_T)(uint16_T)(((uint16_T)((localB->Qavrg
+    * 125U) >> 1) * 52429U) >> 15) << 1) / 75U * 5U) >> 2);
+
+  /* Saturate: '<S3>/Saturation' incorporates:
+   *  UnitDelay: '<S7>/Unit Delay1'
+   */
+  if (sohd_pct_bcuSoh >= 1000) {
+    /* Saturate: '<S3>/Saturation' */
+    sohd_pct_bcuSoh = 1000U;
+  }
+
+  /* End of Saturate: '<S3>/Saturation' */
+
+  /* UnitDelay: '<S7>/Unit Delay' incorporates:
+   *  UnitDelay: '<S6>/Unit Delay'
+   */
+  localDW->UnitDelay_DSTATE_e = localDW->UnitDelay_DSTATE_g;
+
+  /* Switch: '<S7>/Switch' incorporates:
+   *  Constant: '<S7>/Constant'
+   *  Constant: '<S7>/Constant1'
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   *  Logic: '<S7>/Logical Operator'
+   *  RelationalOperator: '<S7>/Relational Operator'
+   *  RelationalOperator: '<S7>/Relational Operator1'
+   *  UnitDelay: '<S6>/Unit Delay'
+   *  UnitDelay: '<S7>/Unit Delay1'
+   */
+  sohd_flg_chrgEndEo = (((localDW->UnitDelay_DSTATE_e == 2) && (ihd_st_workStat
+    != 2)) || (localDW->UnitDelay1_DSTATE != 0));
+
+  /* UnitDelay: '<S8>/Unit Delay' incorporates:
+   *  UnitDelay: '<S6>/Unit Delay'
+   */
+  localDW->UnitDelay_DSTATE_e = localDW->UnitDelay_DSTATE_gh;
+
+  /* Outputs for Enabled SubSystem: '<S8>/Resettable Subsystem' incorporates:
+   *  EnablePort: '<S11>/Enable'
+   */
+  /* RelationalOperator: '<S8>/Relational Operator1' incorporates:
+   *  Constant: '<S8>/Constant1'
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   */
+  if (ihd_st_workStat == 2) {
+    /* Sum: '<S11>/Add' incorporates:
+     *  Inport: '<Root>/ihd_I_curr'
+     *  UnitDelay: '<S11>/Unit Delay'
+     */
+    i_0 = ihd_I_curr * 10 + localDW->UnitDelay_DSTATE;
+
+    /* Product: '<S11>/Divide1' incorporates:
+     *  Product: '<S11>/Divide'
+     *  Sum: '<S11>/Add'
+     */
+    localB->Divide1_c = (uint16_T)(((uint16_T)(((uint32_T)div_nde_s32_floor(i_0,
+      200) << 1) / 4500U) * 5U) >> 2);
+
+    /* Logic: '<S11>/Logical Operator' incorporates:
+     *  Constant: '<S8>/Constant2'
+     *  RelationalOperator: '<S8>/Relational Operator2'
+     *  UnitDelay: '<S4>/Unit Delay1'
+     *  UnitDelay: '<S6>/Unit Delay'
+     */
+    localDW->UnitDelay1_DSTATE_m = (localDW->UnitDelay_DSTATE_e == 2);
+
+    /* Product: '<S11>/Product' incorporates:
+     *  Sum: '<S11>/Add'
+     *  UnitDelay: '<S11>/Unit Delay'
+     *  UnitDelay: '<S4>/Unit Delay1'
+     */
+    localDW->UnitDelay_DSTATE = localDW->UnitDelay1_DSTATE_m ? i_0 : 0;
+  }
+
+  /* End of RelationalOperator: '<S8>/Relational Operator1' */
+  /* End of Outputs for SubSystem: '<S8>/Resettable Subsystem' */
+
+  /* SignalConversion generated from: '<S8>/Resettable Subsystem' incorporates:
+   *  Product: '<S11>/Divide1'
+   */
+  sohd_Q_chrgEo = localB->Divide1_c;
+
+  /* Update for UnitDelay: '<S6>/Unit Delay1' incorporates:
+   *  Switch: '<S6>/Switch'
+   */
+  for (i_0 = 0; i_0 < 28; i_0++) {
+    localDW->UnitDelay1_DSTATE_i[i_0] = sohv_V_chrgStartStatEo[i_0];
+  }
+
+  /* End of Update for UnitDelay: '<S6>/Unit Delay1' */
+
+  /* Update for UnitDelay: '<S6>/Unit Delay' incorporates:
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   */
+  localDW->UnitDelay_DSTATE_e = ihd_st_workStat;
+
+  /* Update for UnitDelay: '<S4>/Unit Delay1' incorporates:
+   *  Constant: '<S4>/Constant2'
+   */
+  localDW->UnitDelay1_DSTATE_m = false;
+
+  /* Update for UnitDelay: '<S7>/Unit Delay' incorporates:
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   */
+  localDW->UnitDelay_DSTATE_g = ihd_st_workStat;
+
+  /* Abs: '<S7>/Abs' incorporates:
+   *  Inport: '<Root>/ihd_I_curr'
+   */
+  if (ihd_I_curr < 0) {
+    tmp_0 = (int16_T)-ihd_I_curr;
+  } else {
+    tmp_0 = ihd_I_curr;
+  }
+
+  /* End of Abs: '<S7>/Abs' */
+
+  /* Update for UnitDelay: '<S7>/Unit Delay1' incorporates:
+   *  Logic: '<S7>/Logical Operator1'
+   *  Product: '<S7>/Product'
+   *  RelationalOperator: '<S7>/Relational Operator3'
+   */
+  localDW->UnitDelay1_DSTATE = (uint16_T)(sohd_flg_chrgEndEo ? tmp_0 < 20 : 0);
+
+  /* Update for UnitDelay: '<S8>/Unit Delay' incorporates:
+   *  Inport: '<Root>/ihd_st_ChrgStat '
+   */
+  localDW->UnitDelay_DSTATE_gh = ihd_st_workStat;
+}
+
+/* Model initialize function */
+void SOH_initialize(const char_T **rt_errorStatus, RT_MODEL_SOH_T *const SOH_M)
+{
+  /* Registration code */
+
+  /* initialize error status */
+  rtmSetErrorStatusPointer(SOH_M, rt_errorStatus);
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/app.c

@@ -16,6 +16,7 @@ void appInit(void *arg)
     AppTaskGpsInit(arg);
     AppTaskUartInit(arg);
     AppTaskCanInit(arg);
+    AppTaskBcuInit(arg);
 }
 void main_entry(void) 
 {

src/const_params.c

@@ -0,0 +1,56 @@
+/*
+ * const_params.c
+ *
+ * Code generation for model "SOC".
+ *
+ * Model version              : 1.24
+ * Simulink Coder version : 9.4 (R2020b) 29-Jul-2020
+ * C source code generated on : Thu Aug 12 17:54:23 2021
+ */
+#include "rtwtypes.h"
+
+extern const real_T rtCP_pooled_2yqyybnjRkAg[13];
+const real_T rtCP_pooled_2yqyybnjRkAg[13] = { 1.8, 1.1, 7.4, 1.5,
+  1.2000000000000002, 1.1, 1.2000000000000002, 1.3, 1.2000000000000002,
+  1.2000000000000002, 1.1, 1.2000000000000002, 1.0 } ;
+
+extern const real_T rtCP_pooled_4Oms9Dl3djxK[13];
+const real_T rtCP_pooled_4Oms9Dl3djxK[13] = { 3.88, 5.0600000000000005, 4.45,
+  10.8, 12.89, 12.99, 14.33, 10.75, 9.38, 10.34, 10.59, 11.950000000000001,
+  11.51 } ;
+
+extern const int16_T rtCP_pooled_5IPKsXGYnKyg[4];
+const int16_T rtCP_pooled_5IPKsXGYnKyg[4] = { 50, 100, 200, 400 } ;
+
+extern const real_T rtCP_pooled_6SXVB9Ymnskr[13];
+const real_T rtCP_pooled_6SXVB9Ymnskr[13] = { 2.2, 2.0, 2.0, 1.9000000000000001,
+  1.8, 1.8, 1.8, 1.7000000000000002, 1.7000000000000002, 1.7000000000000002,
+  1.7000000000000002, 1.8, 1.8 } ;
+
+extern const int16_T rtCP_pooled_9BXJPVWA4BJI[3];
+const int16_T rtCP_pooled_9BXJPVWA4BJI[3] = { -400, -200, -100 } ;
+
+extern const real_T rtCP_pooled_Hq33G5zkPPgT[13];
+const real_T rtCP_pooled_Hq33G5zkPPgT[13] = { 0.0, 5.0, 10.0, 20.0, 30.0, 40.0,
+  50.0, 60.0, 70.0, 80.0, 90.0, 95.0, 100.0 } ;
+
+extern const uint16_T rtCP_pooled_J4vL4j1Fk1zG[3];
+const uint16_T rtCP_pooled_J4vL4j1Fk1zG[3] = { 3100U, 3270U, 3380U } ;
+
+extern const uint16_T rtCP_pooled_P4rYfkzHqAVr[4];
+const uint16_T rtCP_pooled_P4rYfkzHqAVr[4] = { 4126U, 4128U, 4132U, 4137U } ;
+
+extern const uint16_T rtCP_pooled_Pg3wA7d95Txu[13];
+const uint16_T rtCP_pooled_Pg3wA7d95Txu[13] = { 0U, 50U, 100U, 200U, 300U, 400U,
+  500U, 600U, 700U, 800U, 900U, 950U, 1000U } ;
+
+extern const uint16_T rtCP_pooled_neXCembKU1Do[13];
+const uint16_T rtCP_pooled_neXCembKU1Do[13] = { 3311U, 3411U, 3476U, 3553U,
+  3610U, 3638U, 3674U, 3758U, 3845U, 3942U, 4051U, 4106U, 4175U } ;
+
+extern const uint16_T rtCP_pooled_qce4hcBQN8fp[4];
+const uint16_T rtCP_pooled_qce4hcBQN8fp[4] = { 4125U, 4128U, 4132U, 4137U } ;
+
+extern const real_T rtCP_pooled_ygMHmGen2OIb[13];
+const real_T rtCP_pooled_ygMHmGen2OIb[13] = { 3.311, 3.411, 3.476, 3.553, 3.61,
+  3.638, 3.674, 3.758, 3.845, 3.942, 4.051, 4.106, 4.175 } ;

src/div_nde_s32_floor.c

@@ -0,0 +1,24 @@
+/*
+ * File: div_nde_s32_floor.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "div_nde_s32_floor.h"
+
+int32_T div_nde_s32_floor(int32_T numerator, int32_T denominator)
+{
+  return (((numerator < 0) != (denominator < 0)) && (numerator % denominator !=
+           0) ? -1 : 0) + numerator / denominator;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/div_nzp_repeat_u32.c

@@ -0,0 +1,39 @@
+/*
+ * File: div_nzp_repeat_u32.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "div_nzp_repeat_u32.h"
+
+uint32_T div_nzp_repeat_u32(uint32_T numerator, uint32_T denominator, uint32_T
+  nRepeatSub)
+{
+  uint32_T iRepeatSub;
+  uint32_T quotient;
+  boolean_T numeratorExtraBit;
+  quotient = numerator / denominator;
+  numerator %= denominator;
+  for (iRepeatSub = 0U; iRepeatSub < nRepeatSub; iRepeatSub++) {
+    numeratorExtraBit = (numerator >= 2147483648U);
+    numerator <<= 1U;
+    quotient <<= 1U;
+    if (numeratorExtraBit || (numerator >= denominator)) {
+      quotient++;
+      numerator -= denominator;
+    }
+  }
+
+  return quotient;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/div_nzp_repeat_u32_ceiling.c

@@ -0,0 +1,43 @@
+/*
+ * File: div_nzp_repeat_u32_ceiling.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "div_nzp_repeat_u32_ceiling.h"
+
+uint32_T div_nzp_repeat_u32_ceiling(uint32_T numerator, uint32_T denominator,
+  uint32_T nRepeatSub)
+{
+  uint32_T iRepeatSub;
+  uint32_T quotient;
+  boolean_T numeratorExtraBit;
+  quotient = numerator / denominator;
+  numerator %= denominator;
+  for (iRepeatSub = 0U; iRepeatSub < nRepeatSub; iRepeatSub++) {
+    numeratorExtraBit = (numerator >= 2147483648U);
+    numerator <<= 1U;
+    quotient <<= 1U;
+    if (numeratorExtraBit || (numerator >= denominator)) {
+      quotient++;
+      numerator -= denominator;
+    }
+  }
+
+  if (numerator > 0U) {
+    quotient++;
+  }
+
+  return quotient;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/div_repeat_s16s32_floor.c

@@ -0,0 +1,47 @@
+/*
+ * File: div_repeat_s16s32_floor.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "div_nzp_repeat_u32.h"
+#include "div_nzp_repeat_u32_ceiling.h"
+#include "div_repeat_s16s32_floor.h"
+
+int16_T div_repeat_s16s32_floor(int32_T numerator, int32_T denominator, uint32_T
+  nRepeatSub)
+{
+  uint32_T absDenominator;
+  uint32_T absNumerator;
+  int16_T quotient;
+  if (denominator == 0) {
+    quotient = (int16_T)(numerator >= 0 ? 32767 : -32768);
+
+    /* Divide by zero handler */
+  } else {
+    absNumerator = numerator < 0 ? ~(uint32_T)numerator + 1U : (uint32_T)
+      numerator;
+    absDenominator = denominator < 0 ? ~(uint32_T)denominator + 1U : (uint32_T)
+      denominator;
+    if ((numerator < 0) != (denominator < 0)) {
+      quotient = (int16_T)-(int32_T)div_nzp_repeat_u32_ceiling(absNumerator,
+        absDenominator, nRepeatSub);
+    } else {
+      quotient = (int16_T)div_nzp_repeat_u32(absNumerator, absDenominator,
+        nRepeatSub);
+    }
+  }
+
+  return quotient;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/ert_main.c

@@ -0,0 +1,104 @@
+/*
+ * File: ert_main.c
+ *
+ * Code generated for Simulink model 'BCU'.
+ *
+ * Model version                  : 1.13
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:42 2021
+ *
+ * Target selection: ert.tlc
+ * Embedded hardware selection: Intel->x86-64 (Windows64)
+ * Code generation objectives: Unspecified
+ * Validation result: Not run
+ */
+
+#include <stddef.h>
+#include <stdio.h>              /* This ert_main.c example uses printf/fflush */
+#include "BCU.h"                       /* Model's header file */
+#include "rtwtypes.h"
+
+/*
+ * Associating rt_OneStep with a real-time clock or interrupt service routine
+ * is what makes the generated code "real-time".  The function rt_OneStep is
+ * always associated with the base rate of the model.  Subrates are managed
+ * by the base rate from inside the generated code.  Enabling/disabling
+ * interrupts and floating point context switches are target specific.  This
+ * example code indicates where these should take place relative to executing
+ * the generated code step function.  Overrun behavior should be tailored to
+ * your application needs.  This example simply sets an error status in the
+ * real-time model and returns from rt_OneStep.
+ */
+void rt_OneStep(void);
+void rt_OneStep(void)
+{
+  static boolean_T OverrunFlag = false;
+
+  /* Disable interrupts here */
+
+  /* Check for overrun */
+  if (OverrunFlag) {
+    rtmSetErrorStatus(BCU_M, "Overrun");
+    return;
+  }
+
+  OverrunFlag = true;
+
+  /* Save FPU context here (if necessary) */
+  /* Re-enable timer or interrupt here */
+  /* Set model inputs here */
+
+  /* Step the model */
+  BCU_step();
+
+  /* Get model outputs here */
+
+  /* Indicate task complete */
+  OverrunFlag = false;
+
+  /* Disable interrupts here */
+  /* Restore FPU context here (if necessary) */
+  /* Enable interrupts here */
+}
+
+/*
+ * The example "main" function illustrates what is required by your
+ * application code to initialize, execute, and terminate the generated code.
+ * Attaching rt_OneStep to a real-time clock is target specific.  This example
+ * illustrates how you do this relative to initializing the model.
+ */
+int_T main(int_T argc, const char *argv[])
+{
+  /* Unused arguments */
+  (void)(argc);
+  (void)(argv);
+
+  /* Initialize model */
+  BCU_initialize();
+
+  /* Attach rt_OneStep to a timer or interrupt service routine with
+   * period 0.1 seconds (the model's base sample time) here.  The
+   * call syntax for rt_OneStep is
+   *
+   *  rt_OneStep();
+   */
+  printf("Warning: The simulation will run forever. "
+         "Generated ERT main won't simulate model step behavior. "
+         "To change this behavior select the 'MAT-file logging' option.\n");
+  fflush((NULL));
+  while (rtmGetErrorStatus(BCU_M) == (NULL)) {
+    /*  Perform other application tasks here */
+  }
+
+  /* Disable rt_OneStep() here */
+
+  /* Terminate model */
+  BCU_terminate();
+  return 0;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/look1_binlxpw.c

@@ -0,0 +1,75 @@
+/*
+ * File: look1_binlxpw.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "look1_binlxpw.h"
+
+real_T look1_binlxpw(real_T u0, const real_T bp0[], const real_T table[],
+                     uint32_T maxIndex)
+{
+  real_T frac;
+  real_T yL_0d0;
+  uint32_T bpIdx;
+  uint32_T iLeft;
+  uint32_T iRght;
+
+  /* Column-major Lookup 1-D
+     Search method: 'binary'
+     Use previous index: 'off'
+     Interpolation method: 'Linear point-slope'
+     Extrapolation method: 'Linear'
+     Use last breakpoint for index at or above upper limit: 'off'
+     Remove protection against out-of-range input in generated code: 'off'
+   */
+  /* Prelookup - Index and Fraction
+     Index Search method: 'binary'
+     Extrapolation method: 'Linear'
+     Use previous index: 'off'
+     Use last breakpoint for index at or above upper limit: 'off'
+     Remove protection against out-of-range input in generated code: 'off'
+   */
+  if (u0 <= bp0[0U]) {
+    iLeft = 0U;
+    frac = (u0 - bp0[0U]) / (bp0[1U] - bp0[0U]);
+  } else if (u0 < bp0[maxIndex]) {
+    /* Binary Search */
+    bpIdx = maxIndex >> 1U;
+    iLeft = 0U;
+    iRght = maxIndex;
+    while (iRght - iLeft > 1U) {
+      if (u0 < bp0[bpIdx]) {
+        iRght = bpIdx;
+      } else {
+        iLeft = bpIdx;
+      }
+
+      bpIdx = (iRght + iLeft) >> 1U;
+    }
+
+    frac = (u0 - bp0[iLeft]) / (bp0[iLeft + 1U] - bp0[iLeft]);
+  } else {
+    iLeft = maxIndex - 1U;
+    frac = (u0 - bp0[maxIndex - 1U]) / (bp0[maxIndex] - bp0[maxIndex - 1U]);
+  }
+
+  /* Column-major Interpolation 1-D
+     Interpolation method: 'Linear point-slope'
+     Use last breakpoint for index at or above upper limit: 'off'
+     Overflow mode: 'portable wrapping'
+   */
+  yL_0d0 = table[iLeft];
+  return (table[iLeft + 1U] - yL_0d0) * frac + yL_0d0;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/look1_is16lu16n16tu16_binlcase.c

@@ -0,0 +1,96 @@
+/*
+ * File: look1_is16lu16n16tu16_binlcase.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "look1_is16lu16n16tu16_binlcase.h"
+
+uint16_T look1_is16lu16n16tu16_binlcase(int16_T u0, const int16_T bp0[], const
+  uint16_T table[], uint32_T maxIndex)
+{
+  uint32_T bpIdx;
+  uint32_T iLeft;
+  uint32_T iRght;
+  int16_T bpLeftVar;
+  uint16_T frac;
+  uint16_T y;
+  uint16_T yL_0d0;
+  uint16_T yR_0d0;
+
+  /* Column-major Lookup 1-D
+     Search method: 'binary'
+     Use previous index: 'off'
+     Interpolation method: 'Linear point-slope'
+     Extrapolation method: 'Clip'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Remove protection against out-of-range input in generated code: 'off'
+     Rounding mode: 'simplest'
+   */
+  /* Prelookup - Index and Fraction
+     Index Search method: 'binary'
+     Extrapolation method: 'Clip'
+     Use previous index: 'off'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Remove protection against out-of-range input in generated code: 'off'
+     Rounding mode: 'simplest'
+   */
+  if (u0 <= bp0[0U]) {
+    iLeft = 0U;
+    frac = 0U;
+  } else if (u0 < bp0[maxIndex]) {
+    /* Binary Search */
+    bpIdx = maxIndex >> 1U;
+    iLeft = 0U;
+    iRght = maxIndex;
+    while (iRght - iLeft > 1U) {
+      if (u0 < bp0[bpIdx]) {
+        iRght = bpIdx;
+      } else {
+        iLeft = bpIdx;
+      }
+
+      bpIdx = (iRght + iLeft) >> 1U;
+    }
+
+    bpLeftVar = bp0[iLeft];
+    frac = (uint16_T)(((uint32_T)(uint16_T)(u0 - bpLeftVar) << 16) / (uint16_T)
+                      (bp0[iLeft + 1U] - bpLeftVar));
+  } else {
+    iLeft = maxIndex;
+    frac = 0U;
+  }
+
+  /* Column-major Interpolation 1-D
+     Interpolation method: 'Linear point-slope'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Rounding mode: 'simplest'
+     Overflow mode: 'wrapping'
+   */
+  if (iLeft == maxIndex) {
+    y = table[iLeft];
+  } else {
+    yR_0d0 = table[iLeft + 1U];
+    yL_0d0 = table[iLeft];
+    if (yR_0d0 >= yL_0d0) {
+      y = (uint16_T)((uint32_T)(uint16_T)(((uint32_T)(uint16_T)((uint32_T)yR_0d0
+        - yL_0d0) * frac) >> 16) + yL_0d0);
+    } else {
+      y = (uint16_T)((uint32_T)yL_0d0 - (uint16_T)(((uint32_T)(uint16_T)
+        ((uint32_T)yL_0d0 - yR_0d0) * frac) >> 16));
+    }
+  }
+
+  return y;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/look1_iu16lu16n16tu16_binlcase.c

@@ -0,0 +1,95 @@
+/*
+ * File: look1_iu16lu16n16tu16_binlcase.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "look1_iu16lu16n16tu16_binlcase.h"
+
+uint16_T look1_iu16lu16n16tu16_binlcase(uint16_T u0, const uint16_T bp0[], const
+  uint16_T table[], uint32_T maxIndex)
+{
+  uint32_T bpIdx;
+  uint32_T iLeft;
+  uint32_T iRght;
+  uint16_T frac;
+  uint16_T y;
+  uint16_T yL_0d0;
+  uint16_T yR_0d0;
+
+  /* Column-major Lookup 1-D
+     Search method: 'binary'
+     Use previous index: 'off'
+     Interpolation method: 'Linear point-slope'
+     Extrapolation method: 'Clip'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Remove protection against out-of-range input in generated code: 'off'
+     Rounding mode: 'simplest'
+   */
+  /* Prelookup - Index and Fraction
+     Index Search method: 'binary'
+     Extrapolation method: 'Clip'
+     Use previous index: 'off'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Remove protection against out-of-range input in generated code: 'off'
+     Rounding mode: 'simplest'
+   */
+  if (u0 <= bp0[0U]) {
+    iLeft = 0U;
+    frac = 0U;
+  } else if (u0 < bp0[maxIndex]) {
+    /* Binary Search */
+    bpIdx = maxIndex >> 1U;
+    iLeft = 0U;
+    iRght = maxIndex;
+    while (iRght - iLeft > 1U) {
+      if (u0 < bp0[bpIdx]) {
+        iRght = bpIdx;
+      } else {
+        iLeft = bpIdx;
+      }
+
+      bpIdx = (iRght + iLeft) >> 1U;
+    }
+
+    frac = bp0[iLeft];
+    frac = (uint16_T)(((uint32_T)(uint16_T)((uint32_T)u0 - frac) << 16) /
+                      (uint16_T)((uint32_T)bp0[iLeft + 1U] - frac));
+  } else {
+    iLeft = maxIndex;
+    frac = 0U;
+  }
+
+  /* Column-major Interpolation 1-D
+     Interpolation method: 'Linear point-slope'
+     Use last breakpoint for index at or above upper limit: 'on'
+     Rounding mode: 'simplest'
+     Overflow mode: 'wrapping'
+   */
+  if (iLeft == maxIndex) {
+    y = table[iLeft];
+  } else {
+    yR_0d0 = table[iLeft + 1U];
+    yL_0d0 = table[iLeft];
+    if (yR_0d0 >= yL_0d0) {
+      y = (uint16_T)((uint32_T)(uint16_T)(((uint32_T)(uint16_T)((uint32_T)yR_0d0
+        - yL_0d0) * frac) >> 16) + yL_0d0);
+    } else {
+      y = (uint16_T)((uint32_T)yL_0d0 - (uint16_T)(((uint32_T)(uint16_T)
+        ((uint32_T)yL_0d0 - yR_0d0) * frac) >> 16));
+    }
+  }
+
+  return y;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_s32_loSR_sat.c

@@ -0,0 +1,39 @@
+/*
+ * File: mul_s32_loSR_sat.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_s32.h"
+#include "mul_s32_loSR_sat.h"
+
+int32_T mul_s32_loSR_sat(int32_T a, int32_T b, uint32_T aShift)
+{
+  int32_T result;
+  uint32_T u32_chi;
+  uint32_T u32_clo;
+  mul_wide_s32(a, b, &u32_chi, &u32_clo);
+  u32_clo = u32_chi << /*MW:OvBitwiseOk*/ (32U - aShift) | u32_clo >> aShift;
+  u32_chi = (uint32_T)((int32_T)u32_chi >> aShift);
+  if (((int32_T)u32_chi > 0) || ((u32_chi == 0U) && (u32_clo >= 2147483648U))) {
+    result = MAX_int32_T;
+  } else if (((int32_T)u32_chi < -1) || (((int32_T)u32_chi == -1) && (u32_clo <
+               2147483648U))) {
+    result = MIN_int32_T;
+  } else {
+    result = (int32_T)u32_clo;
+  }
+
+  return result;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_s32_sat.c

@@ -0,0 +1,37 @@
+/*
+ * File: mul_s32_sat.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_s32.h"
+#include "mul_s32_sat.h"
+
+int32_T mul_s32_sat(int32_T a, int32_T b)
+{
+  int32_T result;
+  uint32_T u32_chi;
+  uint32_T u32_clo;
+  mul_wide_s32(a, b, &u32_chi, &u32_clo);
+  if (((int32_T)u32_chi > 0) || ((u32_chi == 0U) && (u32_clo >= 2147483648U))) {
+    result = MAX_int32_T;
+  } else if (((int32_T)u32_chi < -1) || (((int32_T)u32_chi == -1) && (u32_clo <
+               2147483648U))) {
+    result = MIN_int32_T;
+  } else {
+    result = (int32_T)u32_clo;
+  }
+
+  return result;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_ssu32_sat.c

@@ -0,0 +1,37 @@
+/*
+ * File: mul_ssu32_sat.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_su32.h"
+#include "mul_ssu32_sat.h"
+
+int32_T mul_ssu32_sat(int32_T a, uint32_T b)
+{
+  int32_T result;
+  uint32_T u32_chi;
+  uint32_T u32_clo;
+  mul_wide_su32(a, b, &u32_chi, &u32_clo);
+  if (((int32_T)u32_chi > 0) || ((u32_chi == 0U) && (u32_clo >= 2147483648U))) {
+    result = MAX_int32_T;
+  } else if (((int32_T)u32_chi < -1) || (((int32_T)u32_chi == -1) && (u32_clo <
+               2147483648U))) {
+    result = MIN_int32_T;
+  } else {
+    result = (int32_T)u32_clo;
+  }
+
+  return result;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_u32_hiSR.c

@@ -0,0 +1,27 @@
+/*
+ * File: mul_u32_hiSR.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_u32.h"
+#include "mul_u32_hiSR.h"
+
+uint32_T mul_u32_hiSR(uint32_T a, uint32_T b, uint32_T aShift)
+{
+  uint32_T u32_chi;
+  uint32_T u32_clo;
+  mul_wide_u32(a, b, &u32_chi, &u32_clo);
+  return u32_chi >> aShift;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_u32_hiSR_near.c

@@ -0,0 +1,27 @@
+/*
+ * File: mul_u32_hiSR_near.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.24
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Thu Aug 12 17:54:23 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_u32.h"
+#include "mul_u32_hiSR_near.h"
+
+uint32_T mul_u32_hiSR_near(uint32_T a, uint32_T b, uint32_T aShift)
+{
+  uint32_T u32_chi;
+  uint32_T u32_clo;
+  mul_wide_u32(a, b, &u32_chi, &u32_clo);
+  return ((1U << (aShift - 1U) & u32_chi) != 0U) + (u32_chi >> aShift);
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_us32_sat.c

@@ -0,0 +1,35 @@
+/*
+ * File: mul_us32_sat.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_s32.h"
+#include "mul_us32_sat.h"
+
+uint32_T mul_us32_sat(int32_T a, int32_T b)
+{
+  uint32_T result;
+  uint32_T u32_chi;
+  mul_wide_s32(a, b, &u32_chi, &result);
+  if ((int32_T)u32_chi >= 0) {
+    if (u32_chi) {
+      result = MAX_uint32_T;
+    }
+  } else {
+    result = 0U;
+  }
+
+  return result;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_wide_s32.c

@@ -0,0 +1,64 @@
+/*
+ * File: mul_wide_s32.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_s32.h"
+
+void mul_wide_s32(int32_T in0, int32_T in1, uint32_T *ptrOutBitsHi, uint32_T
+                  *ptrOutBitsLo)
+{
+  uint32_T absIn0;
+  uint32_T absIn1;
+  uint32_T in0Hi;
+  uint32_T in0Lo;
+  uint32_T in1Hi;
+  uint32_T productHiLo;
+  uint32_T productLoHi;
+  absIn0 = in0 < 0 ? ~(uint32_T)in0 + 1U : (uint32_T)in0;
+  absIn1 = in1 < 0 ? ~(uint32_T)in1 + 1U : (uint32_T)in1;
+  in0Hi = absIn0 >> 16U;
+  in0Lo = absIn0 & 65535U;
+  in1Hi = absIn1 >> 16U;
+  absIn0 = absIn1 & 65535U;
+  productHiLo = in0Hi * absIn0;
+  productLoHi = in0Lo * in1Hi;
+  absIn0 *= in0Lo;
+  absIn1 = 0U;
+  in0Lo = (productLoHi << /*MW:OvBitwiseOk*/ 16U) + /*MW:OvCarryOk*/ absIn0;
+  if (in0Lo < absIn0) {
+    absIn1 = 1U;
+  }
+
+  absIn0 = in0Lo;
+  in0Lo += /*MW:OvCarryOk*/ productHiLo << /*MW:OvBitwiseOk*/ 16U;
+  if (in0Lo < absIn0) {
+    absIn1++;
+  }
+
+  absIn0 = (((productLoHi >> 16U) + (productHiLo >> 16U)) + in0Hi * in1Hi) +
+    absIn1;
+  if ((in0 != 0) && ((in1 != 0) && ((in0 > 0) != (in1 > 0)))) {
+    absIn0 = ~absIn0;
+    in0Lo = ~in0Lo;
+    in0Lo++;
+    if (in0Lo == 0U) {
+      absIn0++;
+    }
+  }
+
+  *ptrOutBitsHi = absIn0;
+  *ptrOutBitsLo = in0Lo;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_wide_su32.c

@@ -0,0 +1,63 @@
+/*
+ * File: mul_wide_su32.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_su32.h"
+
+void mul_wide_su32(int32_T in0, uint32_T in1, uint32_T *ptrOutBitsHi, uint32_T
+                   *ptrOutBitsLo)
+{
+  uint32_T absIn0;
+  uint32_T in0Hi;
+  uint32_T in1Hi;
+  uint32_T in1Lo;
+  uint32_T outBitsLo;
+  uint32_T productHiLo;
+  uint32_T productLoHi;
+  absIn0 = in0 < 0 ? ~(uint32_T)in0 + 1U : (uint32_T)in0;
+  in0Hi = absIn0 >> 16U;
+  absIn0 &= 65535U;
+  in1Hi = in1 >> 16U;
+  in1Lo = in1 & 65535U;
+  productHiLo = in0Hi * in1Lo;
+  productLoHi = absIn0 * in1Hi;
+  absIn0 *= in1Lo;
+  in1Lo = 0U;
+  outBitsLo = (productLoHi << /*MW:OvBitwiseOk*/ 16U) + /*MW:OvCarryOk*/ absIn0;
+  if (outBitsLo < absIn0) {
+    in1Lo = 1U;
+  }
+
+  absIn0 = outBitsLo;
+  outBitsLo += /*MW:OvCarryOk*/ productHiLo << /*MW:OvBitwiseOk*/ 16U;
+  if (outBitsLo < absIn0) {
+    in1Lo++;
+  }
+
+  absIn0 = (((productLoHi >> 16U) + (productHiLo >> 16U)) + in0Hi * in1Hi) +
+    in1Lo;
+  if ((in1 != 0U) && (in0 < 0)) {
+    absIn0 = ~absIn0;
+    outBitsLo = ~outBitsLo;
+    outBitsLo++;
+    if (outBitsLo == 0U) {
+      absIn0++;
+    }
+  }
+
+  *ptrOutBitsHi = absIn0;
+  *ptrOutBitsLo = outBitsLo;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/mul_wide_u32.c

@@ -0,0 +1,52 @@
+/*
+ * File: mul_wide_u32.c
+ *
+ * Code generated for Simulink model 'BLC'.
+ *
+ * Model version                  : 1.20
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:44:57 2021
+ */
+
+#include "rtwtypes.h"
+#include "mul_wide_u32.h"
+
+void mul_wide_u32(uint32_T in0, uint32_T in1, uint32_T *ptrOutBitsHi, uint32_T
+                  *ptrOutBitsLo)
+{
+  uint32_T in0Hi;
+  uint32_T in0Lo;
+  uint32_T in1Hi;
+  uint32_T in1Lo;
+  uint32_T outBitsLo;
+  uint32_T productHiLo;
+  uint32_T productLoHi;
+  in0Hi = in0 >> 16U;
+  in0Lo = in0 & 65535U;
+  in1Hi = in1 >> 16U;
+  in1Lo = in1 & 65535U;
+  productHiLo = in0Hi * in1Lo;
+  productLoHi = in0Lo * in1Hi;
+  in0Lo *= in1Lo;
+  in1Lo = 0U;
+  outBitsLo = (productLoHi << /*MW:OvBitwiseOk*/ 16U) + /*MW:OvCarryOk*/ in0Lo;
+  if (outBitsLo < in0Lo) {
+    in1Lo = 1U;
+  }
+
+  in0Lo = outBitsLo;
+  outBitsLo += /*MW:OvCarryOk*/ productHiLo << /*MW:OvBitwiseOk*/ 16U;
+  if (outBitsLo < in0Lo) {
+    in1Lo++;
+  }
+
+  *ptrOutBitsHi = (((productLoHi >> 16U) + (productHiLo >> 16U)) + in0Hi * in1Hi)
+    + in1Lo;
+  *ptrOutBitsLo = outBitsLo;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/rtGetInf.c

@@ -0,0 +1,92 @@
+/*
+ * File: rtGetInf.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+/*
+ * Abstract:
+ *      Function to initialize non-finite, Inf
+ */
+#include "rtGetInf.h"
+#define NumBitsPerChar                 8U
+
+/*
+ * Initialize rtInf needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetInf(void)
+{
+  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+  real_T inf = 0.0;
+  if (bitsPerReal == 32U) {
+    inf = rtGetInfF();
+  } else {
+    union {
+      LittleEndianIEEEDouble bitVal;
+      real_T fltVal;
+    } tmpVal;
+
+    tmpVal.bitVal.words.wordH = 0x7FF00000U;
+    tmpVal.bitVal.words.wordL = 0x00000000U;
+    inf = tmpVal.fltVal;
+  }
+
+  return inf;
+}
+
+/*
+ * Initialize rtInfF needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetInfF(void)
+{
+  IEEESingle infF;
+  infF.wordL.wordLuint = 0x7F800000U;
+  return infF.wordL.wordLreal;
+}
+
+/*
+ * Initialize rtMinusInf needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetMinusInf(void)
+{
+  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+  real_T minf = 0.0;
+  if (bitsPerReal == 32U) {
+    minf = rtGetMinusInfF();
+  } else {
+    union {
+      LittleEndianIEEEDouble bitVal;
+      real_T fltVal;
+    } tmpVal;
+
+    tmpVal.bitVal.words.wordH = 0xFFF00000U;
+    tmpVal.bitVal.words.wordL = 0x00000000U;
+    minf = tmpVal.fltVal;
+  }
+
+  return minf;
+}
+
+/*
+ * Initialize rtMinusInfF needed by the generated code.
+ * Inf is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetMinusInfF(void)
+{
+  IEEESingle minfF;
+  minfF.wordL.wordLuint = 0xFF800000U;
+  return minfF.wordL.wordLreal;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/rtGetNaN.c

@@ -0,0 +1,58 @@
+/*
+ * File: rtGetNaN.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+/*
+ * Abstract:
+ *      Function to initialize non-finite, NaN
+ */
+#include "rtGetNaN.h"
+#define NumBitsPerChar                 8U
+
+/*
+ * Initialize rtNaN needed by the generated code.
+ * NaN is initialized as non-signaling. Assumes IEEE.
+ */
+real_T rtGetNaN(void)
+{
+  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+  real_T nan = 0.0;
+  if (bitsPerReal == 32U) {
+    nan = rtGetNaNF();
+  } else {
+    union {
+      LittleEndianIEEEDouble bitVal;
+      real_T fltVal;
+    } tmpVal;
+
+    tmpVal.bitVal.words.wordH = 0xFFF80000U;
+    tmpVal.bitVal.words.wordL = 0x00000000U;
+    nan = tmpVal.fltVal;
+  }
+
+  return nan;
+}
+
+/*
+ * Initialize rtNaNF needed by the generated code.
+ * NaN is initialized as non-signaling. Assumes IEEE.
+ */
+real32_T rtGetNaNF(void)
+{
+  IEEESingle nanF = { { 0 } };
+
+  nanF.wordL.wordLuint = 0xFFC00000U;
+  return nanF.wordL.wordLreal;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/rt_nonfinite.c

@@ -0,0 +1,90 @@
+/*
+ * File: rt_nonfinite.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+/*
+ * Abstract:
+ *      Function to initialize non-finites,
+ *      (Inf, NaN and -Inf).
+ */
+#include "rt_nonfinite.h"
+#include "rtGetNaN.h"
+#include "rtGetInf.h"
+#define NumBitsPerChar                 8U
+
+real_T rtInf;
+real_T rtMinusInf;
+real_T rtNaN;
+real32_T rtInfF;
+real32_T rtMinusInfF;
+real32_T rtNaNF;
+
+/*
+ * Initialize the rtInf, rtMinusInf, and rtNaN needed by the
+ * generated code. NaN is initialized as non-signaling. Assumes IEEE.
+ */
+void rt_InitInfAndNaN(size_t realSize)
+{
+  (void) (realSize);
+  rtNaN = rtGetNaN();
+  rtNaNF = rtGetNaNF();
+  rtInf = rtGetInf();
+  rtInfF = rtGetInfF();
+  rtMinusInf = rtGetMinusInf();
+  rtMinusInfF = rtGetMinusInfF();
+}
+
+/* Test if value is infinite */
+boolean_T rtIsInf(real_T value)
+{
+  return (boolean_T)((value==rtInf || value==rtMinusInf) ? 1U : 0U);
+}
+
+/* Test if single-precision value is infinite */
+boolean_T rtIsInfF(real32_T value)
+{
+  return (boolean_T)(((value)==rtInfF || (value)==rtMinusInfF) ? 1U : 0U);
+}
+
+/* Test if value is not a number */
+boolean_T rtIsNaN(real_T value)
+{
+  boolean_T result = (boolean_T) 0;
+  size_t bitsPerReal = sizeof(real_T) * (NumBitsPerChar);
+  if (bitsPerReal == 32U) {
+    result = rtIsNaNF((real32_T)value);
+  } else {
+    union {
+      LittleEndianIEEEDouble bitVal;
+      real_T fltVal;
+    } tmpVal;
+
+    tmpVal.fltVal = value;
+    result = (boolean_T)((tmpVal.bitVal.words.wordH & 0x7FF00000) == 0x7FF00000 &&
+                         ( (tmpVal.bitVal.words.wordH & 0x000FFFFF) != 0 ||
+                          (tmpVal.bitVal.words.wordL != 0) ));
+  }
+
+  return result;
+}
+
+/* Test if single-precision value is not a number */
+boolean_T rtIsNaNF(real32_T value)
+{
+  IEEESingle tmp;
+  tmp.wordL.wordLreal = value;
+  return (boolean_T)( (tmp.wordL.wordLuint & 0x7F800000) == 0x7F800000 &&
+                     (tmp.wordL.wordLuint & 0x007FFFFF) != 0 );
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */

src/rt_powd_snf.c

@@ -0,0 +1,68 @@
+/*
+ * File: rt_powd_snf.c
+ *
+ * Code generated for Simulink model 'SOC'.
+ *
+ * Model version                  : 1.15
+ * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
+ * C/C++ source code generated on : Wed Aug 11 09:45:09 2021
+ */
+
+#include "rtwtypes.h"
+#include "rtGetNaN.h"
+#include "rt_nonfinite.h"
+#include "rtGetInf.h"
+#include <math.h>
+#include "rt_powd_snf.h"
+
+real_T rt_powd_snf(real_T u0, real_T u1)
+{
+  real_T tmp;
+  real_T tmp_0;
+  real_T y;
+  if (rtIsNaN(u0) || rtIsNaN(u1)) {
+    y = (rtNaN);
+  } else {
+    tmp = fabs(u0);
+    tmp_0 = fabs(u1);
+    if (rtIsInf(u1)) {
+      if (tmp == 1.0) {
+        y = 1.0;
+      } else if (tmp > 1.0) {
+        if (u1 > 0.0) {
+          y = (rtInf);
+        } else {
+          y = 0.0;
+        }
+      } else if (u1 > 0.0) {
+        y = 0.0;
+      } else {
+        y = (rtInf);
+      }
+    } else if (tmp_0 == 0.0) {
+      y = 1.0;
+    } else if (tmp_0 == 1.0) {
+      if (u1 > 0.0) {
+        y = u0;
+      } else {
+        y = 1.0 / u0;
+      }
+    } else if (u1 == 2.0) {
+      y = u0 * u0;
+    } else if ((u1 == 0.5) && (u0 >= 0.0)) {
+      y = sqrt(u0);
+    } else if ((u0 < 0.0) && (u1 > floor(u1))) {
+      y = (rtNaN);
+    } else {
+      y = pow(u0, u1);
+    }
+  }
+
+  return y;
+}
+
+/*
+ * File trailer for generated code.
+ *
+ * [EOF]
+ */