NB_APP_Code/inc/BLC.h

/*
 * File: BLC.h
 *
 * Code generated for Simulink model 'BLC'.
 *
 * Model version                  : 1.24
 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
 * C/C++ source code generated on : Thu Aug 12 17:54:13 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef RTW_HEADER_BLC_h_
#define RTW_HEADER_BLC_h_
#include <string.h>
#ifndef BLC_COMMON_INCLUDES_
#define BLC_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* BLC_COMMON_INCLUDES_ */

#include "BLC_types.h"

/* Block signals for model 'BLC' */
typedef struct {
  uint32_T Merge1[28];                 /* '<S2>/Merge1' */
  uint16_T blcn_Q_reqCpNow_j[28];      /* '<S6>/Chart' */
  uint16_T blcn_Q_impleCp[28];         /* '<S5>/Chart' */
  uint16_T Merge[28];                  /* '<S2>/Merge' */
  boolean_T blcn_flg_stop[28];         /* '<S7>/Chart' */
  boolean_T blcn_flg_blcable[28];      /* '<S5>/Chart' */
  boolean_T blcn_flg_pause[28];        /* '<S4>/Chart' */
} B_BLC_c_T;

/* Block states (default storage) for model 'BLC' */
typedef struct {
  uint32_T blcCap[28];                 /* '<S5>/Chart' */
  uint16_T UnitDelay_DSTATE[28];       /* '<S1>/Unit Delay' */
  uint16_T QL;                         /* '<S6>/Chart1' */
  boolean_T UnitDelay1_DSTATE;         /* '<S1>/Unit Delay1' */
  uint8_T i_close;                     /* '<S4>/Chart' */
  uint8_T i_open;                      /* '<S4>/Chart' */
  boolean_T FristFlg;                  /* '<S6>/Chart1' */
  boolean_T FristFlg_b;                /* '<S6>/Chart' */
} DW_BLC_f_T;

/* Real-time Model Data Structure */
struct tag_RTM_BLC_T {
  const char_T **errorStatus;
};

typedef struct {
  B_BLC_c_T rtb;
  DW_BLC_f_T rtdw;
  RT_MODEL_BLC_T rtm;
} MdlrefDW_BLC_T;

/* Model reference registration function */
extern void BLC_initialize(const char_T **rt_errorStatus, RT_MODEL_BLC_T *const
  BLC_M);
extern void BLC_Init(DW_BLC_f_T *localDW);
extern void BLC(B_BLC_c_T *localB, DW_BLC_f_T *localDW);

/* Exported data declaration */

/* Declaration for custom storage class: ExportToFile */
extern uint16_T blcv_Q_reqCpEi[28];

/* 均衡需求容量 读取量（数组）； */
extern uint16_T blcv_Q_reqCpEo[28];    /* '<S5>/Add' */

/* 均衡需求容量 写入量（数组）； */
extern uint32_T blcv_Q_totalCpEi[28];

/* 累计均衡容量 读取量（数组）； */
extern uint32_T blcv_Q_totalCpEo[28];  /* '<S5>/Add1' */

/* 累计均衡容量 写入量（数组）； */
extern boolean_T blcv_flg_excute[28];  /* '<S5>/Chart' */

/* 均衡执行请求标志位 （数组） */
extern int16_T ihd_T_bdtemp;
extern uint16_T ihd_V_cellUMin;

/* 电池单体电压最小； */
extern uint8_T ihd_st_fault;

/* 故障等级 */
extern uint32_T ihd_tm_parkTime;

/* 驻车时间； */
extern uint16_T ihv_V_cellU[28];

/* 电池单体电压（数组）； */
extern uint16_T sohv_Q_cellCap[28];

/* 充入容量写入量； */

/*-
 * These blocks were eliminated from the model due to optimizations:
 *
 * Block '<S1>/Display' : Unused code path elimination
 * Block '<S1>/Display1' : Unused code path elimination
 * Block '<S1>/Display2' : Unused code path elimination
 * Block '<S1>/Display3' : Unused code path elimination
 * Block '<S1>/Display4' : Unused code path elimination
 * Block '<S3>/Display' : Unused code path elimination
 * Block '<S5>/Display' : Unused code path elimination
 * Block '<S5>/Scope' : Unused code path elimination
 * Block '<S6>/Display' : Unused code path elimination
 * Block '<S6>/Display2' : Unused code path elimination
 */

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'BLC'
 * '<S1>'   : 'BLC/Subsystem'
 * '<S2>'   : 'BLC/Subsystem/EE'
 * '<S3>'   : 'BLC/Subsystem/Enalbe'
 * '<S4>'   : 'BLC/Subsystem/pause'
 * '<S5>'   : 'BLC/Subsystem/record'
 * '<S6>'   : 'BLC/Subsystem/reqCpNow_Count'
 * '<S7>'   : 'BLC/Subsystem/stop'
 * '<S8>'   : 'BLC/Subsystem/EE/If Action Subsystem'
 * '<S9>'   : 'BLC/Subsystem/EE/If Action Subsystem1'
 * '<S10>'  : 'BLC/Subsystem/EE/Subsystem'
 * '<S11>'  : 'BLC/Subsystem/pause/Chart'
 * '<S12>'  : 'BLC/Subsystem/record/Chart'
 * '<S13>'  : 'BLC/Subsystem/reqCpNow_Count/Chart'
 * '<S14>'  : 'BLC/Subsystem/reqCpNow_Count/Chart1'
 * '<S15>'  : 'BLC/Subsystem/stop/Chart'
 */
#endif                                 /* RTW_HEADER_BLC_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */