NB_APP_Code/inc/EmbeddedCoder_inc/SOC.h

/*
 * File: SOC.h
 *
 * Code generated for Simulink model 'SOC'.
 *
 * Model version                  : 1.51
 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
 * C/C++ source code generated on : Thu Sep  9 17:18:48 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef RTW_HEADER_SOC_h_
#define RTW_HEADER_SOC_h_
#include <math.h>
#ifndef SOC_COMMON_INCLUDES_
#define SOC_COMMON_INCLUDES_
#include "rtwtypes.h"
#include "zero_crossing_types.h"
#endif                                 /* SOC_COMMON_INCLUDES_ */

#include "SOC_types.h"

/* Includes for objects with custom storage classes. */
#include "BCUCal.h"
#include "BCUDisp.h"

/* Block signals for model 'SOC' */
#ifndef SOC_MDLREF_HIDE_CHILD_

typedef struct {
  uint16_T in;                         /* '<S55>/in' */
  uint16_T Switch;                     /* '<S5>/Switch' */
  uint16_T Divide;                     /* '<S5>/Divide' */
  uint16_T socn_pct_bcuSocEE_Merge;    /* '<S2>/socn_pct_bcuSocEE_Merge' */
  int16_T in_f;                        /* '<S54>/in' */
  int16_T in_d;                        /* '<S60>/in' */
  int16_T in_c;                        /* '<S56>/in' */
} B_SOC_c_T;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

/* Block states (default storage) for model 'SOC' */
#ifndef SOC_MDLREF_HIDE_CHILD_

typedef struct {
  real_T SOCk_Delay_DSTATE;            /* '<S12>/SOCk_Delay' */
  real_T P_Delay_DSTATE[4];            /* '<S12>/P_Delay' */
  real_T SOCk_Delay_DSTATE_e;          /* '<S13>/SOCk_Delay' */
  real_T P_Delay_DSTATE_m[4];          /* '<S13>/P_Delay' */
  real_T Up_Delay_DSTATE;              /* '<S13>/Up_Delay' */
  real_T Up_Delay_DSTATE_h;            /* '<S12>/Up_Delay' */
  real_T Divide_DWORK4;                /* '<S17>/Divide' */
  real_T Divide_DWORK4_h;              /* '<S26>/Divide' */
  int32_T _DSTATE;                     /* '<S4>/  ' */
  uint16_T Time_Delay_DSTATE;          /* '<S35>/Time_Delay' */
  uint16_T Time_Delay_DSTATE_e;        /* '<S61>/Time_Delay' */
  uint16_T Time_Delay_DSTATE_g;        /* '<S59>/Time_Delay' */
  uint16_T Time_Delay_DSTATE_f;        /* '<S58>/Time_Delay' */
  uint16_T UnitDelay7_DSTATE;          /* '<S6>/Unit Delay7' */
  uint16_T socd_pct_battSoc0_Delay_DSTATE;/* '<S6>/socd_pct_battSoc0_Delay' */
  uint16_T socd_pct_bcusocDelay_DSTATE;/* '<S6>/socd_pct_bcusocDelay' */
  uint16_T socd_pct_bcuSoc0_Delay_DSTATE;/* '<S6>/socd_pct_bcuSoc0_Delay' */
  uint16_T socd_flg_EEsave_Delay_DSTATE;/* '<S32>/socd_flg_EEsave_Delay' */
  uint16_T socn_pct_estsoc_Delay_DSTATE;/* '<S57>/socn_pct_estsoc_Delay' */
  uint16_T socfit_Delay_DSTATE;        /* '<S42>/socfit_Delay' */
  uint16_T socfit_Delay_DSTATE_n;      /* '<S37>/socfit_Delay' */
  uint8_T ihd_st_chrgSta_Delay_DSTATE; /* '<S6>/ihd_st_chrgSta_Delay' */
  uint8_T Time_reset_DSTATE;           /* '<S49>/Time_reset' */
  boolean_T FirstDelay_DSTATE;         /* '<S1>/FirstDelay' */
  boolean_T Frist_DSTATE;              /* '<S14>/Frist' */
  boolean_T Frist_DSTATE_h;            /* '<S23>/Frist' */
  boolean_T First_Delay_DSTATE;        /* '<S6>/First_Delay' */
  boolean_T First_Delay1_DSTATE;       /* '<S6>/First_Delay1' */
  boolean_T UnitDelay1_DSTATE;         /* '<S52>/Unit Delay1' */
  boolean_T UnitDelay1_DSTATE_p;       /* '<S53>/Unit Delay1' */
  boolean_T lowFLg_Delay_DSTATE;       /* '<S51>/lowFLg_Delay' */
  boolean_T overFlg_reset_DSTATE;      /* '<S50>/overFlg_reset' */
  boolean_T fulFLg_reset_DSTATE;       /* '<S50>/fulFLg_reset' */
  int8_T If_ActiveSubsystem;           /* '<S7>/If' */
} DW_SOC_f_T;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

/* Zero-crossing (trigger) state for model 'SOC' */
#ifndef SOC_MDLREF_HIDE_CHILD_

typedef struct {
  ZCSigState Subsystem2_Trig_ZCE;      /* '<S51>/Subsystem2' */
  ZCSigState Subsystem2_Trig_ZCE_k;    /* '<S50>/Subsystem2' */
} ZCE_SOC_T;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

#ifndef SOC_MDLREF_HIDE_CHILD_

/* Real-time Model Data Structure */
struct tag_RTM_SOC_T {
  const char_T **errorStatus;
};

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

#ifndef SOC_MDLREF_HIDE_CHILD_

typedef struct {
  RT_MODEL_SOC_T rtm;
} MdlrefDW_SOC_T;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

extern void SOC_Init(void);
extern void SOC_Disable(void);
extern void SOC(void);

/* Model reference registration function */
extern void SOC_initialize(const char_T **rt_errorStatus);

#ifndef SOC_MDLREF_HIDE_CHILD_

extern void SOC_MATLABFunction(real_T rtu_x, real_T *rty_y);
extern void SOC_IfActionSubsystem(uint16_T rtu_SOC, uint16_T rtu_SOCfit,
  uint16_T *rty_Out1, uint16_T rtp_m);
extern void SOC_IfActionSubsystem1(uint16_T rtu_SOC, uint16_T rtu_SOCfit,
  uint16_T *rty_Out1);

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

#ifndef SOC_MDLREF_HIDE_CHILD_

extern MdlrefDW_SOC_T SOC_MdlrefDW;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

#ifndef SOC_MDLREF_HIDE_CHILD_

/* Block signals (default storage) */
extern B_SOC_c_T SOC_B;

/* Block states (default storage) */
extern DW_SOC_f_T SOC_DW;

/* Previous zero-crossings (trigger) states */
extern ZCE_SOC_T SOC_PrevZCX;

#endif                                 /*SOC_MDLREF_HIDE_CHILD_*/

/*-
 * These blocks were eliminated from the model due to optimizations:
 *
 * Block '<S12>/Scope' : Unused code path elimination
 * Block '<S12>/Signal Conversion' : Unused code path elimination
 * Block '<S29>/Display' : Unused code path elimination
 * Block '<S6>/Scope1' : Unused code path elimination
 * Block '<S33>/Scope2' : Unused code path elimination
 * Block '<S12>/Signal Conversion1' : Eliminate redundant signal conversion block
 * Block '<S37>/Signal Conversion' : Eliminate redundant signal conversion block
 * Block '<S49>/Saturation1' : Eliminated Saturate block
 */

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'SOC'
 * '<S1>'   : 'SOC/SOC'
 * '<S2>'   : 'SOC/SOC/EEcheck'
 * '<S3>'   : 'SOC/SOC/EKF'
 * '<S4>'   : 'SOC/SOC/EKF1'
 * '<S5>'   : 'SOC/SOC/Inti_correct'
 * '<S6>'   : 'SOC/SOC/bcuSoc'
 * '<S7>'   : 'SOC/SOC/estSOC'
 * '<S8>'   : 'SOC/SOC/EEcheck/If Action Subsystem'
 * '<S9>'   : 'SOC/SOC/EEcheck/If Action Subsystem1'
 * '<S10>'  : 'SOC/SOC/EEcheck/Subsystem'
 * '<S11>'  : 'SOC/SOC/EKF/EKF'
 * '<S12>'  : 'SOC/SOC/EKF/Subsystem'
 * '<S13>'  : 'SOC/SOC/EKF/Subsystem1'
 * '<S14>'  : 'SOC/SOC/EKF/Subsystem/初始'
 * '<S15>'  : 'SOC/SOC/EKF/Subsystem/协方差更新'
 * '<S16>'  : 'SOC/SOC/EKF/Subsystem/协方差计算'
 * '<S17>'  : 'SOC/SOC/EKF/Subsystem/卡尔曼增益'
 * '<S18>'  : 'SOC/SOC/EKF/Subsystem/状态修正'
 * '<S19>'  : 'SOC/SOC/EKF/Subsystem/状态更新'
 * '<S20>'  : 'SOC/SOC/EKF/Subsystem/电池参数'
 * '<S21>'  : 'SOC/SOC/EKF/Subsystem/矩阵计算'
 * '<S22>'  : 'SOC/SOC/EKF/Subsystem/矩阵计算/MATLAB Function'
 * '<S23>'  : 'SOC/SOC/EKF/Subsystem1/初始'
 * '<S24>'  : 'SOC/SOC/EKF/Subsystem1/协方差更新'
 * '<S25>'  : 'SOC/SOC/EKF/Subsystem1/协方差计算'
 * '<S26>'  : 'SOC/SOC/EKF/Subsystem1/卡尔曼增益'
 * '<S27>'  : 'SOC/SOC/EKF/Subsystem1/状态修正'
 * '<S28>'  : 'SOC/SOC/EKF/Subsystem1/状态更新'
 * '<S29>'  : 'SOC/SOC/EKF/Subsystem1/电池参数'
 * '<S30>'  : 'SOC/SOC/EKF/Subsystem1/矩阵计算'
 * '<S31>'  : 'SOC/SOC/EKF/Subsystem1/矩阵计算/MATLAB Function'
 * '<S32>'  : 'SOC/SOC/bcuSoc/Subsystem1'
 * '<S33>'  : 'SOC/SOC/bcuSoc/Subsystem2'
 * '<S34>'  : 'SOC/SOC/bcuSoc/Subsystem3'
 * '<S35>'  : 'SOC/SOC/bcuSoc/keep juged1'
 * '<S36>'  : 'SOC/SOC/bcuSoc/Subsystem2/LookUP1'
 * '<S37>'  : 'SOC/SOC/bcuSoc/Subsystem2/SOCfit'
 * '<S38>'  : 'SOC/SOC/bcuSoc/Subsystem2/SOCfit/If Action Subsystem'
 * '<S39>'  : 'SOC/SOC/bcuSoc/Subsystem2/SOCfit/If Action Subsystem1'
 * '<S40>'  : 'SOC/SOC/bcuSoc/Subsystem2/SOCfit/If Action Subsystem2'
 * '<S41>'  : 'SOC/SOC/bcuSoc/Subsystem3/LookUP1'
 * '<S42>'  : 'SOC/SOC/bcuSoc/Subsystem3/SOCfit1'
 * '<S43>'  : 'SOC/SOC/bcuSoc/Subsystem3/SOCfit1/If Action Subsystem'
 * '<S44>'  : 'SOC/SOC/bcuSoc/Subsystem3/SOCfit1/If Action Subsystem1'
 * '<S45>'  : 'SOC/SOC/bcuSoc/Subsystem3/SOCfit1/If Action Subsystem2'
 * '<S46>'  : 'SOC/SOC/estSOC/If Action Subsystem'
 * '<S47>'  : 'SOC/SOC/estSOC/If Action Subsystem1'
 * '<S48>'  : 'SOC/SOC/estSOC/If Action Subsystem2'
 * '<S49>'  : 'SOC/SOC/estSOC/Time++'
 * '<S50>'  : 'SOC/SOC/estSOC/chrgCCV'
 * '<S51>'  : 'SOC/SOC/estSOC/disChrgCCV'
 * '<S52>'  : 'SOC/SOC/estSOC/If Action Subsystem/Frist Keep'
 * '<S53>'  : 'SOC/SOC/estSOC/If Action Subsystem/Frist Keep1'
 * '<S54>'  : 'SOC/SOC/estSOC/If Action Subsystem/Frist Keep/Subsystem3'
 * '<S55>'  : 'SOC/SOC/estSOC/If Action Subsystem/Frist Keep1/Subsystem3'
 * '<S56>'  : 'SOC/SOC/estSOC/chrgCCV/Subsystem2'
 * '<S57>'  : 'SOC/SOC/estSOC/chrgCCV/inc'
 * '<S58>'  : 'SOC/SOC/estSOC/chrgCCV/keep juged'
 * '<S59>'  : 'SOC/SOC/estSOC/chrgCCV/keep juged1'
 * '<S60>'  : 'SOC/SOC/estSOC/disChrgCCV/Subsystem2'
 * '<S61>'  : 'SOC/SOC/estSOC/disChrgCCV/keep juged'
 */
#endif                                 /* RTW_HEADER_SOC_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */