NB_APP_Code/inc/SOH.h

/*
 * File: SOH.h
 *
 * Code generated for Simulink model 'SOH'.
 *
 * Model version                  : 1.31
 * Simulink Coder version         : 9.4 (R2020b) 29-Jul-2020
 * C/C++ source code generated on : Thu Sep  2 11:40:39 2021
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives: Unspecified
 * Validation result: Not run
 */

#ifndef RTW_HEADER_SOH_h_
#define RTW_HEADER_SOH_h_
#ifndef SOH_COMMON_INCLUDES_
#define SOH_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                                 /* SOH_COMMON_INCLUDES_ */

#include "SOH_types.h"

/* Includes for objects with custom storage classes. */
#include "BCUCal.h"
#include "BCUDisp.h"

/* Block signals for model 'SOH' */
#ifndef SOH_MDLREF_HIDE_CHILD_

typedef struct {
  uint16_T Divide;                     /* '<S9>/Divide' */
  uint16_T d[28];                      /* '<S13>/d' */
  uint16_T Add2;                       /* '<S13>/Add2' */
  uint16_T Qavrg;                      /* '<S3>/Chart' */
  uint16_T sohn_Q_packCapArrEo[10];    /* '<S3>/Chart' */
  uint16_T Divide1;                    /* '<S11>/Divide1' */
} B_SOH_c_T;

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

/* Block states (default storage) for model 'SOH' */
#ifndef SOH_MDLREF_HIDE_CHILD_

typedef struct {
  int32_T curr_icr_Delay_DSTATE;       /* '<S11>/curr_icr_Delay' */
  uint16_T Time_Delay_DSTATE;          /* '<S10>/Time_Delay' */
  uint16_T sohd_tm_chrgStartSta_Delay_DSTA;/* '<S6>/sohd_tm_chrgStartSta_Delay' */
  uint16_T UnitDelay1_DSTATE;          /* '<S7>/Unit Delay1' */
  uint16_T Time_Delay_DSTATE_k;        /* '<S9>/Time_Delay' */
  uint16_T sohv_V_chrgStartEo_Delay_DSTATE[28];/* '<S6>/sohv_V_chrgStartEo_Delay' */
  uint8_T UnitDelay_DSTATE;            /* '<S6>/Unit Delay' */
  uint8_T UnitDelay_DSTATE_g;          /* '<S7>/Unit Delay' */
  boolean_T First_Delay_DSTATE;        /* '<S4>/First_Delay' */
  boolean_T UnitDelay_DSTATE_e;        /* '<S3>/Unit Delay' */
  boolean_T UnitDelay1_DSTATE_j;       /* '<S6>/Unit Delay1' */
  boolean_T Fflg;                      /* '<S3>/Chart' */
  boolean_T ResettableSubsystem_MODE;  /* '<S8>/Resettable Subsystem' */
  boolean_T ResettableSubsystem_MODE_i;/* '<S6>/Resettable Subsystem' */
} DW_SOH_f_T;

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

#ifndef SOH_MDLREF_HIDE_CHILD_

/* Real-time Model Data Structure */
struct tag_RTM_SOH_T {
  const char_T **errorStatus;
};

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

#ifndef SOH_MDLREF_HIDE_CHILD_

typedef struct {
  RT_MODEL_SOH_T rtm;
} MdlrefDW_SOH_T;

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

extern void SOH_Init(void);
extern void SOH_Disable(void);
extern void SOH(void);

/* Model reference registration function */
extern void SOH_initialize(const char_T **rt_errorStatus);

#ifndef SOH_MDLREF_HIDE_CHILD_

extern void SOH_ArrMin_Init(uint16_T *rty_minCap);
extern void SOH_ArrMin(const uint16_T rtu_sohn_Q_cellCap[28], uint8_T rtu_N,
  uint16_T *rty_minCap);

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

#ifndef SOH_MDLREF_HIDE_CHILD_

extern MdlrefDW_SOH_T SOH_MdlrefDW;

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

#ifndef SOH_MDLREF_HIDE_CHILD_

/* Block signals (default storage) */
extern B_SOH_c_T SOH_B;

/* Block states (default storage) */
extern DW_SOH_f_T SOH_DW;

#endif                                 /*SOH_MDLREF_HIDE_CHILD_*/

/*-
 * These blocks were eliminated from the model due to optimizations:
 *
 * Block '<S7>/Scope' : Unused code path elimination
 * Block '<S7>/Scope1' : Unused code path elimination
 * Block '<S9>/Saturation' : Eliminated Saturate block
 */

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'SOH'
 * '<S1>'   : 'SOH/SOH'
 * '<S2>'   : 'SOH/SOH/Chrgmation'
 * '<S3>'   : 'SOH/SOH/Conut'
 * '<S4>'   : 'SOH/SOH/CountEn'
 * '<S5>'   : 'SOH/SOH/EEDeal'
 * '<S6>'   : 'SOH/SOH/Chrgmation/ChrgBe'
 * '<S7>'   : 'SOH/SOH/Chrgmation/ChrgEnd'
 * '<S8>'   : 'SOH/SOH/Chrgmation/Chrging'
 * '<S9>'   : 'SOH/SOH/Chrgmation/ChrgBe/Resettable Subsystem'
 * '<S10>'  : 'SOH/SOH/Chrgmation/ChrgBe/keep2'
 * '<S11>'  : 'SOH/SOH/Chrgmation/Chrging/Resettable Subsystem'
 * '<S12>'  : 'SOH/SOH/Conut/Chart'
 * '<S13>'  : 'SOH/SOH/Conut/Subsystem'
 * '<S14>'  : 'SOH/SOH/Conut/Subsystem/Subsystem'
 * '<S15>'  : 'SOH/SOH/Conut/Subsystem/Subsystem1'
 * '<S16>'  : 'SOH/SOH/Conut/Subsystem/Subsystem/ArrMin'
 * '<S17>'  : 'SOH/SOH/Conut/Subsystem/Subsystem1/ArrMin'
 * '<S18>'  : 'SOH/SOH/EEDeal/EECkeck'
 * '<S19>'  : 'SOH/SOH/EEDeal/FalseAction'
 * '<S20>'  : 'SOH/SOH/EEDeal/TureAction'
 */
#endif                                 /* RTW_HEADER_SOH_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */