portasm.asm 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172
  1. ;/*
  2. ; * FreeRTOS Kernel V10.4.6
  3. ; * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. ; *
  5. ; * SPDX-License-Identifier: MIT
  6. ; *
  7. ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. ; * this software and associated documentation files (the "Software"), to deal in
  9. ; * the Software without restriction, including without limitation the rights to
  10. ; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. ; * the Software, and to permit persons to whom the Software is furnished to do so,
  12. ; * subject to the following conditions:
  13. ; *
  14. ; * The above copyright notice and this permission notice shall be included in all
  15. ; * copies or substantial portions of the Software.
  16. ; *
  17. ; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. ; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. ; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. ; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. ; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. ; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. ; *
  24. ; * https://www.FreeRTOS.org
  25. ; * https://github.com/FreeRTOS
  26. ; *
  27. ; */
  28. .thumb
  29. .ref pxCurrentTCB
  30. .ref vTaskSwitchContext
  31. .ref ulMaxSyscallInterruptPriority
  32. .def xPortPendSVHandler
  33. .def ulPortGetIPSR
  34. .def vPortSVCHandler
  35. .def vPortStartFirstTask
  36. .def vPortEnableVFP
  37. NVICOffsetConst: .word 0xE000ED08
  38. CPACRConst: .word 0xE000ED88
  39. pxCurrentTCBConst: .word pxCurrentTCB
  40. ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
  41. ; -----------------------------------------------------------
  42. .align 4
  43. ulPortGetIPSR: .asmfunc
  44. mrs r0, ipsr
  45. bx r14
  46. .endasmfunc
  47. ; -----------------------------------------------------------
  48. .align 4
  49. vPortSetInterruptMask: .asmfunc
  50. push {r0}
  51. ldr r0, ulMaxSyscallInterruptPriorityConst
  52. msr basepri, r0
  53. pop {r0}
  54. bx r14
  55. .endasmfunc
  56. ; -----------------------------------------------------------
  57. .align 4
  58. xPortPendSVHandler: .asmfunc
  59. mrs r0, psp
  60. isb
  61. ;/* Get the location of the current TCB. */
  62. ldr r3, pxCurrentTCBConst
  63. ldr r2, [r3]
  64. ;/* Is the task using the FPU context? If so, push high vfp registers. */
  65. tst r14, #0x10
  66. it eq
  67. vstmdbeq r0!, {s16-s31}
  68. ;/* Save the core registers. */
  69. stmdb r0!, {r4-r11, r14}
  70. ;/* Save the new top of stack into the first member of the TCB. */
  71. str r0, [r2]
  72. stmdb sp!, {r0, r3}
  73. ldr r0, ulMaxSyscallInterruptPriorityConst
  74. ldr r1, [r0]
  75. msr basepri, r1
  76. dsb
  77. isb
  78. bl vTaskSwitchContext
  79. mov r0, #0
  80. msr basepri, r0
  81. ldmia sp!, {r0, r3}
  82. ;/* The first item in pxCurrentTCB is the task top of stack. */
  83. ldr r1, [r3]
  84. ldr r0, [r1]
  85. ;/* Pop the core registers. */
  86. ldmia r0!, {r4-r11, r14}
  87. ;/* Is the task using the FPU context? If so, pop the high vfp registers
  88. ;too. */
  89. tst r14, #0x10
  90. it eq
  91. vldmiaeq r0!, {s16-s31}
  92. msr psp, r0
  93. isb
  94. bx r14
  95. .endasmfunc
  96. ; -----------------------------------------------------------
  97. .align 4
  98. vPortSVCHandler: .asmfunc
  99. ;/* Get the location of the current TCB. */
  100. ldr r3, pxCurrentTCBConst
  101. ldr r1, [r3]
  102. ldr r0, [r1]
  103. ;/* Pop the core registers. */
  104. ldmia r0!, {r4-r11, r14}
  105. msr psp, r0
  106. isb
  107. mov r0, #0
  108. msr basepri, r0
  109. bx r14
  110. .endasmfunc
  111. ; -----------------------------------------------------------
  112. .align 4
  113. vPortStartFirstTask: .asmfunc
  114. ;/* Use the NVIC offset register to locate the stack. */
  115. ldr r0, NVICOffsetConst
  116. ldr r0, [r0]
  117. ldr r0, [r0]
  118. ;/* Set the msp back to the start of the stack. */
  119. msr msp, r0
  120. ;/* Clear the bit that indicates the FPU is in use in case the FPU was used
  121. ;before the scheduler was started - which would otherwise result in the
  122. ;unnecessary leaving of space in the SVC stack for lazy saving of FPU
  123. ;registers. */
  124. mov r0, #0
  125. msr control, r0
  126. ;/* Call SVC to start the first task. */
  127. cpsie i
  128. cpsie f
  129. dsb
  130. isb
  131. svc #0
  132. .endasmfunc
  133. ; -----------------------------------------------------------
  134. .align 4
  135. vPortEnableVFP: .asmfunc
  136. ;/* The FPU enable bits are in the CPACR. */
  137. ldr.w r0, CPACRConst
  138. ldr r1, [r0]
  139. ;/* Enable CP10 and CP11 coprocessors, then save back. */
  140. orr r1, r1, #( 0xf << 20 )
  141. str r1, [r0]
  142. bx r14
  143. .endasmfunc
  144. .end
  145. ; -----------------------------------------------------------