port.c 8.1 KB

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  1. /*
  2. * FreeRTOS Kernel V10.4.6
  3. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. *
  5. * SPDX-License-Identifier: MIT
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. * this software and associated documentation files (the "Software"), to deal in
  9. * the Software without restriction, including without limitation the rights to
  10. * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. * the Software, and to permit persons to whom the Software is furnished to do so,
  12. * subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in all
  15. * copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * https://www.FreeRTOS.org
  25. * https://github.com/FreeRTOS
  26. *
  27. */
  28. /*-----------------------------------------------------------
  29. * Implementation of functions defined in portable.h for the PPC405 port.
  30. *----------------------------------------------------------*/
  31. /* Scheduler includes. */
  32. #include "FreeRTOS.h"
  33. #include "task.h"
  34. /* Library includes. */
  35. #include "xtime_l.h"
  36. #include "xintc.h"
  37. #include "xintc_i.h"
  38. /*-----------------------------------------------------------*/
  39. /* Definitions to set the initial MSR of each task. */
  40. #define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
  41. #define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
  42. #define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
  43. #if configUSE_FPU == 1
  44. #define portAPU_PRESENT ( 1UL << 25UL )
  45. #define portFCM_FPU_PRESENT ( 1UL << 13UL )
  46. #else
  47. #define portAPU_PRESENT ( 0UL )
  48. #define portFCM_FPU_PRESENT ( 0UL )
  49. #endif
  50. #define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
  51. extern const unsigned _SDA_BASE_;
  52. extern const unsigned _SDA2_BASE_;
  53. /*-----------------------------------------------------------*/
  54. /*
  55. * Setup the system timer to generate the tick interrupt.
  56. */
  57. static void prvSetupTimerInterrupt( void );
  58. /*
  59. * The handler for the tick interrupt - defined in portasm.s.
  60. */
  61. extern void vPortTickISR( void );
  62. /*
  63. * The handler for the yield function - defined in portasm.s.
  64. */
  65. extern void vPortYield( void );
  66. /*
  67. * Function to start the scheduler running by starting the highest
  68. * priority task that has thus far been created.
  69. */
  70. extern void vPortStartFirstTask( void );
  71. /*-----------------------------------------------------------*/
  72. /* Structure used to hold the state of the interrupt controller. */
  73. static XIntc xInterruptController;
  74. /*-----------------------------------------------------------*/
  75. /*
  76. * Initialise the stack of a task to look exactly as if the task had been
  77. * interrupted.
  78. *
  79. * See the header file portable.h.
  80. */
  81. StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
  82. {
  83. /* Place a known value at the bottom of the stack for debugging. */
  84. *pxTopOfStack = 0xDEADBEEF;
  85. pxTopOfStack--;
  86. /* EABI stack frame. */
  87. pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
  88. /* Parameters in R13. */
  89. *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
  90. pxTopOfStack -= 10;
  91. /* Parameters in R3. */
  92. *pxTopOfStack = ( StackType_t ) pvParameters;
  93. pxTopOfStack--;
  94. /* Parameters in R2. */
  95. *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
  96. pxTopOfStack--;
  97. /* R1 is the stack pointer so is omitted. */
  98. *pxTopOfStack = 0x10000001UL;; /* R0. */
  99. pxTopOfStack--;
  100. *pxTopOfStack = 0x00000000UL; /* USPRG0. */
  101. pxTopOfStack--;
  102. *pxTopOfStack = 0x00000000UL; /* CR. */
  103. pxTopOfStack--;
  104. *pxTopOfStack = 0x00000000UL; /* XER. */
  105. pxTopOfStack--;
  106. *pxTopOfStack = 0x00000000UL; /* CTR. */
  107. pxTopOfStack--;
  108. *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
  109. pxTopOfStack--;
  110. *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
  111. pxTopOfStack--;
  112. *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
  113. pxTopOfStack--;
  114. *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
  115. pxTopOfStack--;
  116. *pxTopOfStack = 0x00000000UL;/* Backchain. */
  117. return pxTopOfStack;
  118. }
  119. /*-----------------------------------------------------------*/
  120. BaseType_t xPortStartScheduler( void )
  121. {
  122. prvSetupTimerInterrupt();
  123. XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
  124. vPortStartFirstTask();
  125. /* Should not get here as the tasks are now running! */
  126. return pdFALSE;
  127. }
  128. /*-----------------------------------------------------------*/
  129. void vPortEndScheduler( void )
  130. {
  131. /* Not implemented. */
  132. for( ;; );
  133. }
  134. /*-----------------------------------------------------------*/
  135. /*
  136. * Hardware initialisation to generate the RTOS tick.
  137. */
  138. static void prvSetupTimerInterrupt( void )
  139. {
  140. const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
  141. XTime_PITClearInterrupt();
  142. XTime_FITClearInterrupt();
  143. XTime_WDTClearInterrupt();
  144. XTime_WDTDisableInterrupt();
  145. XTime_FITDisableInterrupt();
  146. XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
  147. XTime_PITEnableAutoReload();
  148. XTime_PITSetInterval( ulInterval );
  149. XTime_PITEnableInterrupt();
  150. }
  151. /*-----------------------------------------------------------*/
  152. void vPortISRHandler( void *pvNullDoNotUse )
  153. {
  154. uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
  155. BaseType_t xInterruptNumber;
  156. XIntc_Config *pxInterruptController;
  157. XIntc_VectorTableEntry *pxTable;
  158. /* Just to remove compiler warning. */
  159. ( void ) pvNullDoNotUse;
  160. /* Get the configuration by using the device ID - in this case it is
  161. assumed that only one interrupt controller is being used. */
  162. pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
  163. /* Which interrupts are pending? */
  164. ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
  165. for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
  166. {
  167. if( ulInterruptStatus & 0x01UL )
  168. {
  169. /* Clear the pending interrupt. */
  170. XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
  171. /* Call the registered handler. */
  172. pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
  173. pxTable->Handler( pxTable->CallBackRef );
  174. }
  175. /* Check the next interrupt. */
  176. ulInterruptMask <<= 0x01UL;
  177. ulInterruptStatus >>= 0x01UL;
  178. /* Have we serviced all interrupts? */
  179. if( ulInterruptStatus == 0UL )
  180. {
  181. break;
  182. }
  183. }
  184. }
  185. /*-----------------------------------------------------------*/
  186. void vPortSetupInterruptController( void )
  187. {
  188. extern void vPortISRWrapper( void );
  189. /* Perform all library calls necessary to initialise the exception table
  190. and interrupt controller. This assumes only one interrupt controller is in
  191. use. */
  192. XExc_mDisableExceptions( XEXC_NON_CRITICAL );
  193. XExc_Init();
  194. /* The library functions save the context - we then jump to a wrapper to
  195. save the stack into the TCB. The wrapper then calls the handler defined
  196. above. */
  197. XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
  198. XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
  199. XIntc_Start( &xInterruptController, XIN_REAL_MODE );
  200. }
  201. /*-----------------------------------------------------------*/
  202. BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
  203. {
  204. BaseType_t xReturn = pdFAIL;
  205. /* This function is defined here so the scope of xInterruptController can
  206. remain within this file. */
  207. if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
  208. {
  209. XIntc_Enable( &xInterruptController, ucInterruptID );
  210. xReturn = pdPASS;
  211. }
  212. return xReturn;
  213. }