portasm.s 3.6 KB

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  1. /*
  2. * FreeRTOS Kernel V10.4.6
  3. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. *
  5. * SPDX-License-Identifier: MIT
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. * this software and associated documentation files (the "Software"), to deal in
  9. * the Software without restriction, including without limitation the rights to
  10. * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. * the Software, and to permit persons to whom the Software is furnished to do so,
  12. * subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in all
  15. * copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * https://www.FreeRTOS.org
  25. * https://github.com/FreeRTOS
  26. *
  27. */
  28. #include <FreeRTOSConfig.h>
  29. RSEG CODE:CODE(2)
  30. thumb
  31. EXTERN pxCurrentTCB
  32. EXTERN vTaskSwitchContext
  33. PUBLIC xPortPendSVHandler
  34. PUBLIC vPortSVCHandler
  35. PUBLIC vPortStartFirstTask
  36. PUBLIC vPortEnableVFP
  37. /*-----------------------------------------------------------*/
  38. xPortPendSVHandler:
  39. mrs r0, psp
  40. isb
  41. /* Get the location of the current TCB. */
  42. ldr r3, =pxCurrentTCB
  43. ldr r2, [r3]
  44. /* Is the task using the FPU context? If so, push high vfp registers. */
  45. tst r14, #0x10
  46. it eq
  47. vstmdbeq r0!, {s16-s31}
  48. /* Save the core registers. */
  49. stmdb r0!, {r4-r11, r14}
  50. /* Save the new top of stack into the first member of the TCB. */
  51. str r0, [r2]
  52. stmdb sp!, {r0, r3}
  53. mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
  54. msr basepri, r0
  55. dsb
  56. isb
  57. bl vTaskSwitchContext
  58. mov r0, #0
  59. msr basepri, r0
  60. ldmia sp!, {r0, r3}
  61. /* The first item in pxCurrentTCB is the task top of stack. */
  62. ldr r1, [r3]
  63. ldr r0, [r1]
  64. /* Pop the core registers. */
  65. ldmia r0!, {r4-r11, r14}
  66. /* Is the task using the FPU context? If so, pop the high vfp registers
  67. too. */
  68. tst r14, #0x10
  69. it eq
  70. vldmiaeq r0!, {s16-s31}
  71. msr psp, r0
  72. isb
  73. #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
  74. #if WORKAROUND_PMU_CM001 == 1
  75. push { r14 }
  76. pop { pc }
  77. #endif
  78. #endif
  79. bx r14
  80. /*-----------------------------------------------------------*/
  81. vPortSVCHandler:
  82. /* Get the location of the current TCB. */
  83. ldr r3, =pxCurrentTCB
  84. ldr r1, [r3]
  85. ldr r0, [r1]
  86. /* Pop the core registers. */
  87. ldmia r0!, {r4-r11, r14}
  88. msr psp, r0
  89. isb
  90. mov r0, #0
  91. msr basepri, r0
  92. bx r14
  93. /*-----------------------------------------------------------*/
  94. vPortStartFirstTask
  95. /* Use the NVIC offset register to locate the stack. */
  96. ldr r0, =0xE000ED08
  97. ldr r0, [r0]
  98. ldr r0, [r0]
  99. /* Set the msp back to the start of the stack. */
  100. msr msp, r0
  101. /* Clear the bit that indicates the FPU is in use in case the FPU was used
  102. before the scheduler was started - which would otherwise result in the
  103. unnecessary leaving of space in the SVC stack for lazy saving of FPU
  104. registers. */
  105. mov r0, #0
  106. msr control, r0
  107. /* Call SVC to start the first task. */
  108. cpsie i
  109. cpsie f
  110. dsb
  111. isb
  112. svc 0
  113. /*-----------------------------------------------------------*/
  114. vPortEnableVFP:
  115. /* The FPU enable bits are in the CPACR. */
  116. ldr.w r0, =0xE000ED88
  117. ldr r1, [r0]
  118. /* Enable CP10 and CP11 coprocessors, then save back. */
  119. orr r1, r1, #( 0xf << 20 )
  120. str r1, [r0]
  121. bx r14
  122. END