lib_AT91SAM7S64.h 123 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265
  1. //*----------------------------------------------------------------------------
  2. //* ATMEL Microcontroller Software Support - ROUSSET -
  3. //*----------------------------------------------------------------------------
  4. //* The software is delivered "AS IS" without warranty or condition of any
  5. //* kind, either express, implied or statutory. This includes without
  6. //* limitation any warranty or condition with respect to merchantability or
  7. //* fitness for any particular purpose, or against the infringements of
  8. //* intellectual property rights of others.
  9. //*----------------------------------------------------------------------------
  10. //* File Name : lib_AT91SAM7S64.h
  11. //* Object : AT91SAM7S64 inlined functions
  12. //* Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
  13. //*
  14. //* CVS Reference : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
  15. //* CVS Reference : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
  16. //* CVS Reference : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
  17. //* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
  18. //* CVS Reference : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
  19. //* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
  20. //* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
  21. //* CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
  22. //* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
  23. //* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
  24. //* CVS Reference : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
  25. //* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
  26. //* CVS Reference : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
  27. //* CVS Reference : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
  28. //*----------------------------------------------------------------------------
  29. #ifndef lib_AT91SAM7S64_H
  30. #define lib_AT91SAM7S64_H
  31. /* *****************************************************************************
  32. SOFTWARE API FOR MC
  33. ***************************************************************************** */
  34. #define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
  35. //*----------------------------------------------------------------------------
  36. //* \fn AT91F_MC_Remap
  37. //* \brief Make Remap
  38. //*----------------------------------------------------------------------------
  39. __inline void AT91F_MC_Remap (void) //
  40. {
  41. AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
  42. pMC->MC_RCR = AT91C_MC_RCB;
  43. }
  44. //*----------------------------------------------------------------------------
  45. //* \fn AT91F_MC_EFC_CfgModeReg
  46. //* \brief Configure the EFC Mode Register of the MC controller
  47. //*----------------------------------------------------------------------------
  48. __inline void AT91F_MC_EFC_CfgModeReg (
  49. AT91PS_MC pMC, // pointer to a MC controller
  50. unsigned int mode) // mode register
  51. {
  52. // Write to the FMR register
  53. pMC->MC_FMR = mode;
  54. }
  55. //*----------------------------------------------------------------------------
  56. //* \fn AT91F_MC_EFC_GetModeReg
  57. //* \brief Return MC EFC Mode Regsiter
  58. //*----------------------------------------------------------------------------
  59. __inline unsigned int AT91F_MC_EFC_GetModeReg(
  60. AT91PS_MC pMC) // pointer to a MC controller
  61. {
  62. return pMC->MC_FMR;
  63. }
  64. //*----------------------------------------------------------------------------
  65. //* \fn AT91F_MC_EFC_ComputeFMCN
  66. //* \brief Return MC EFC Mode Regsiter
  67. //*----------------------------------------------------------------------------
  68. __inline unsigned int AT91F_MC_EFC_ComputeFMCN(
  69. int master_clock) // master clock in Hz
  70. {
  71. return (master_clock/1000000 +2);
  72. }
  73. //*----------------------------------------------------------------------------
  74. //* \fn AT91F_MC_EFC_PerformCmd
  75. //* \brief Perform EFC Command
  76. //*----------------------------------------------------------------------------
  77. __inline void AT91F_MC_EFC_PerformCmd (
  78. AT91PS_MC pMC, // pointer to a MC controller
  79. unsigned int transfer_cmd)
  80. {
  81. pMC->MC_FCR = transfer_cmd;
  82. }
  83. //*----------------------------------------------------------------------------
  84. //* \fn AT91F_MC_EFC_GetStatus
  85. //* \brief Return MC EFC Status
  86. //*----------------------------------------------------------------------------
  87. __inline unsigned int AT91F_MC_EFC_GetStatus(
  88. AT91PS_MC pMC) // pointer to a MC controller
  89. {
  90. return pMC->MC_FSR;
  91. }
  92. //*----------------------------------------------------------------------------
  93. //* \fn AT91F_MC_EFC_IsInterruptMasked
  94. //* \brief Test if EFC MC Interrupt is Masked
  95. //*----------------------------------------------------------------------------
  96. __inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
  97. AT91PS_MC pMC, // \arg pointer to a MC controller
  98. unsigned int flag) // \arg flag to be tested
  99. {
  100. return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
  101. }
  102. //*----------------------------------------------------------------------------
  103. //* \fn AT91F_MC_EFC_IsInterruptSet
  104. //* \brief Test if EFC MC Interrupt is Set
  105. //*----------------------------------------------------------------------------
  106. __inline unsigned int AT91F_MC_EFC_IsInterruptSet(
  107. AT91PS_MC pMC, // \arg pointer to a MC controller
  108. unsigned int flag) // \arg flag to be tested
  109. {
  110. return (AT91F_MC_EFC_GetStatus(pMC) & flag);
  111. }
  112. /* *****************************************************************************
  113. SOFTWARE API FOR PDC
  114. ***************************************************************************** */
  115. //*----------------------------------------------------------------------------
  116. //* \fn AT91F_PDC_SetNextRx
  117. //* \brief Set the next receive transfer descriptor
  118. //*----------------------------------------------------------------------------
  119. __inline void AT91F_PDC_SetNextRx (
  120. AT91PS_PDC pPDC, // \arg pointer to a PDC controller
  121. char *address, // \arg address to the next bloc to be received
  122. unsigned int bytes) // \arg number of bytes to be received
  123. {
  124. pPDC->PDC_RNPR = (unsigned int) address;
  125. pPDC->PDC_RNCR = bytes;
  126. }
  127. //*----------------------------------------------------------------------------
  128. //* \fn AT91F_PDC_SetNextTx
  129. //* \brief Set the next transmit transfer descriptor
  130. //*----------------------------------------------------------------------------
  131. __inline void AT91F_PDC_SetNextTx (
  132. AT91PS_PDC pPDC, // \arg pointer to a PDC controller
  133. char *address, // \arg address to the next bloc to be transmitted
  134. unsigned int bytes) // \arg number of bytes to be transmitted
  135. {
  136. pPDC->PDC_TNPR = (unsigned int) address;
  137. pPDC->PDC_TNCR = bytes;
  138. }
  139. //*----------------------------------------------------------------------------
  140. //* \fn AT91F_PDC_SetRx
  141. //* \brief Set the receive transfer descriptor
  142. //*----------------------------------------------------------------------------
  143. __inline void AT91F_PDC_SetRx (
  144. AT91PS_PDC pPDC, // \arg pointer to a PDC controller
  145. char *address, // \arg address to the next bloc to be received
  146. unsigned int bytes) // \arg number of bytes to be received
  147. {
  148. pPDC->PDC_RPR = (unsigned int) address;
  149. pPDC->PDC_RCR = bytes;
  150. }
  151. //*----------------------------------------------------------------------------
  152. //* \fn AT91F_PDC_SetTx
  153. //* \brief Set the transmit transfer descriptor
  154. //*----------------------------------------------------------------------------
  155. __inline void AT91F_PDC_SetTx (
  156. AT91PS_PDC pPDC, // \arg pointer to a PDC controller
  157. char *address, // \arg address to the next bloc to be transmitted
  158. unsigned int bytes) // \arg number of bytes to be transmitted
  159. {
  160. pPDC->PDC_TPR = (unsigned int) address;
  161. pPDC->PDC_TCR = bytes;
  162. }
  163. //*----------------------------------------------------------------------------
  164. //* \fn AT91F_PDC_EnableTx
  165. //* \brief Enable transmit
  166. //*----------------------------------------------------------------------------
  167. __inline void AT91F_PDC_EnableTx (
  168. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  169. {
  170. pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
  171. }
  172. //*----------------------------------------------------------------------------
  173. //* \fn AT91F_PDC_EnableRx
  174. //* \brief Enable receive
  175. //*----------------------------------------------------------------------------
  176. __inline void AT91F_PDC_EnableRx (
  177. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  178. {
  179. pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
  180. }
  181. //*----------------------------------------------------------------------------
  182. //* \fn AT91F_PDC_DisableTx
  183. //* \brief Disable transmit
  184. //*----------------------------------------------------------------------------
  185. __inline void AT91F_PDC_DisableTx (
  186. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  187. {
  188. pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
  189. }
  190. //*----------------------------------------------------------------------------
  191. //* \fn AT91F_PDC_DisableRx
  192. //* \brief Disable receive
  193. //*----------------------------------------------------------------------------
  194. __inline void AT91F_PDC_DisableRx (
  195. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  196. {
  197. pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
  198. }
  199. //*----------------------------------------------------------------------------
  200. //* \fn AT91F_PDC_IsTxEmpty
  201. //* \brief Test if the current transfer descriptor has been sent
  202. //*----------------------------------------------------------------------------
  203. __inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
  204. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  205. {
  206. return !(pPDC->PDC_TCR);
  207. }
  208. //*----------------------------------------------------------------------------
  209. //* \fn AT91F_PDC_IsNextTxEmpty
  210. //* \brief Test if the next transfer descriptor has been moved to the current td
  211. //*----------------------------------------------------------------------------
  212. __inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
  213. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  214. {
  215. return !(pPDC->PDC_TNCR);
  216. }
  217. //*----------------------------------------------------------------------------
  218. //* \fn AT91F_PDC_IsRxEmpty
  219. //* \brief Test if the current transfer descriptor has been filled
  220. //*----------------------------------------------------------------------------
  221. __inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
  222. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  223. {
  224. return !(pPDC->PDC_RCR);
  225. }
  226. //*----------------------------------------------------------------------------
  227. //* \fn AT91F_PDC_IsNextRxEmpty
  228. //* \brief Test if the next transfer descriptor has been moved to the current td
  229. //*----------------------------------------------------------------------------
  230. __inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
  231. AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
  232. {
  233. return !(pPDC->PDC_RNCR);
  234. }
  235. //*----------------------------------------------------------------------------
  236. //* \fn AT91F_PDC_Open
  237. //* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
  238. //*----------------------------------------------------------------------------
  239. __inline void AT91F_PDC_Open (
  240. AT91PS_PDC pPDC) // \arg pointer to a PDC controller
  241. {
  242. //* Disable the RX and TX PDC transfer requests
  243. AT91F_PDC_DisableRx(pPDC);
  244. AT91F_PDC_DisableTx(pPDC);
  245. //* Reset all Counter register Next buffer first
  246. AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
  247. AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
  248. AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
  249. AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
  250. //* Enable the RX and TX PDC transfer requests
  251. AT91F_PDC_EnableRx(pPDC);
  252. AT91F_PDC_EnableTx(pPDC);
  253. }
  254. //*----------------------------------------------------------------------------
  255. //* \fn AT91F_PDC_Close
  256. //* \brief Close PDC: disable TX and RX reset transfer descriptors
  257. //*----------------------------------------------------------------------------
  258. __inline void AT91F_PDC_Close (
  259. AT91PS_PDC pPDC) // \arg pointer to a PDC controller
  260. {
  261. //* Disable the RX and TX PDC transfer requests
  262. AT91F_PDC_DisableRx(pPDC);
  263. AT91F_PDC_DisableTx(pPDC);
  264. //* Reset all Counter register Next buffer first
  265. AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
  266. AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
  267. AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
  268. AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
  269. }
  270. //*----------------------------------------------------------------------------
  271. //* \fn AT91F_PDC_SendFrame
  272. //* \brief Close PDC: disable TX and RX reset transfer descriptors
  273. //*----------------------------------------------------------------------------
  274. __inline unsigned int AT91F_PDC_SendFrame(
  275. AT91PS_PDC pPDC,
  276. char *pBuffer,
  277. unsigned int szBuffer,
  278. char *pNextBuffer,
  279. unsigned int szNextBuffer )
  280. {
  281. if (AT91F_PDC_IsTxEmpty(pPDC)) {
  282. //* Buffer and next buffer can be initialized
  283. AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
  284. AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
  285. return 2;
  286. }
  287. else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
  288. //* Only one buffer can be initialized
  289. AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
  290. return 1;
  291. }
  292. else {
  293. //* All buffer are in use...
  294. return 0;
  295. }
  296. }
  297. //*----------------------------------------------------------------------------
  298. //* \fn AT91F_PDC_ReceiveFrame
  299. //* \brief Close PDC: disable TX and RX reset transfer descriptors
  300. //*----------------------------------------------------------------------------
  301. __inline unsigned int AT91F_PDC_ReceiveFrame (
  302. AT91PS_PDC pPDC,
  303. char *pBuffer,
  304. unsigned int szBuffer,
  305. char *pNextBuffer,
  306. unsigned int szNextBuffer )
  307. {
  308. if (AT91F_PDC_IsRxEmpty(pPDC)) {
  309. //* Buffer and next buffer can be initialized
  310. AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
  311. AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
  312. return 2;
  313. }
  314. else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
  315. //* Only one buffer can be initialized
  316. AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
  317. return 1;
  318. }
  319. else {
  320. //* All buffer are in use...
  321. return 0;
  322. }
  323. }
  324. /* *****************************************************************************
  325. SOFTWARE API FOR DBGU
  326. ***************************************************************************** */
  327. //*----------------------------------------------------------------------------
  328. //* \fn AT91F_DBGU_InterruptEnable
  329. //* \brief Enable DBGU Interrupt
  330. //*----------------------------------------------------------------------------
  331. __inline void AT91F_DBGU_InterruptEnable(
  332. AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
  333. unsigned int flag) // \arg dbgu interrupt to be enabled
  334. {
  335. pDbgu->DBGU_IER = flag;
  336. }
  337. //*----------------------------------------------------------------------------
  338. //* \fn AT91F_DBGU_InterruptDisable
  339. //* \brief Disable DBGU Interrupt
  340. //*----------------------------------------------------------------------------
  341. __inline void AT91F_DBGU_InterruptDisable(
  342. AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
  343. unsigned int flag) // \arg dbgu interrupt to be disabled
  344. {
  345. pDbgu->DBGU_IDR = flag;
  346. }
  347. //*----------------------------------------------------------------------------
  348. //* \fn AT91F_DBGU_GetInterruptMaskStatus
  349. //* \brief Return DBGU Interrupt Mask Status
  350. //*----------------------------------------------------------------------------
  351. __inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
  352. AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller
  353. {
  354. return pDbgu->DBGU_IMR;
  355. }
  356. //*----------------------------------------------------------------------------
  357. //* \fn AT91F_DBGU_IsInterruptMasked
  358. //* \brief Test if DBGU Interrupt is Masked
  359. //*----------------------------------------------------------------------------
  360. __inline int AT91F_DBGU_IsInterruptMasked(
  361. AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller
  362. unsigned int flag) // \arg flag to be tested
  363. {
  364. return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
  365. }
  366. /* *****************************************************************************
  367. SOFTWARE API FOR SSC
  368. ***************************************************************************** */
  369. //* Define the standard I2S mode configuration
  370. //* Configuration to set in the SSC Transmit Clock Mode Register
  371. //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
  372. //* nb_slot_by_frame : number of channels
  373. #define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
  374. AT91C_SSC_CKS_DIV +\
  375. AT91C_SSC_CKO_CONTINOUS +\
  376. AT91C_SSC_CKG_NONE +\
  377. AT91C_SSC_START_FALL_RF +\
  378. AT91C_SSC_STTOUT +\
  379. ((1<<16) & AT91C_SSC_STTDLY) +\
  380. ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
  381. //* Configuration to set in the SSC Transmit Frame Mode Register
  382. //* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
  383. //* nb_slot_by_frame : number of channels
  384. #define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
  385. (nb_bit_by_slot-1) +\
  386. AT91C_SSC_MSBF +\
  387. (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
  388. (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
  389. AT91C_SSC_FSOS_NEGATIVE)
  390. //*----------------------------------------------------------------------------
  391. //* \fn AT91F_SSC_SetBaudrate
  392. //* \brief Set the baudrate according to the CPU clock
  393. //*----------------------------------------------------------------------------
  394. __inline void AT91F_SSC_SetBaudrate (
  395. AT91PS_SSC pSSC, // \arg pointer to a SSC controller
  396. unsigned int mainClock, // \arg peripheral clock
  397. unsigned int speed) // \arg SSC baudrate
  398. {
  399. unsigned int baud_value;
  400. //* Define the baud rate divisor register
  401. if (speed == 0)
  402. baud_value = 0;
  403. else
  404. {
  405. baud_value = (unsigned int) (mainClock * 10)/(2*speed);
  406. if ((baud_value % 10) >= 5)
  407. baud_value = (baud_value / 10) + 1;
  408. else
  409. baud_value /= 10;
  410. }
  411. pSSC->SSC_CMR = baud_value;
  412. }
  413. //*----------------------------------------------------------------------------
  414. //* \fn AT91F_SSC_Configure
  415. //* \brief Configure SSC
  416. //*----------------------------------------------------------------------------
  417. __inline void AT91F_SSC_Configure (
  418. AT91PS_SSC pSSC, // \arg pointer to a SSC controller
  419. unsigned int syst_clock, // \arg System Clock Frequency
  420. unsigned int baud_rate, // \arg Expected Baud Rate Frequency
  421. unsigned int clock_rx, // \arg Receiver Clock Parameters
  422. unsigned int mode_rx, // \arg mode Register to be programmed
  423. unsigned int clock_tx, // \arg Transmitter Clock Parameters
  424. unsigned int mode_tx) // \arg mode Register to be programmed
  425. {
  426. //* Disable interrupts
  427. pSSC->SSC_IDR = (unsigned int) -1;
  428. //* Reset receiver and transmitter
  429. pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
  430. //* Define the Clock Mode Register
  431. AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
  432. //* Write the Receive Clock Mode Register
  433. pSSC->SSC_RCMR = clock_rx;
  434. //* Write the Transmit Clock Mode Register
  435. pSSC->SSC_TCMR = clock_tx;
  436. //* Write the Receive Frame Mode Register
  437. pSSC->SSC_RFMR = mode_rx;
  438. //* Write the Transmit Frame Mode Register
  439. pSSC->SSC_TFMR = mode_tx;
  440. //* Clear Transmit and Receive Counters
  441. AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
  442. }
  443. //*----------------------------------------------------------------------------
  444. //* \fn AT91F_SSC_EnableRx
  445. //* \brief Enable receiving datas
  446. //*----------------------------------------------------------------------------
  447. __inline void AT91F_SSC_EnableRx (
  448. AT91PS_SSC pSSC) // \arg pointer to a SSC controller
  449. {
  450. //* Enable receiver
  451. pSSC->SSC_CR = AT91C_SSC_RXEN;
  452. }
  453. //*----------------------------------------------------------------------------
  454. //* \fn AT91F_SSC_DisableRx
  455. //* \brief Disable receiving datas
  456. //*----------------------------------------------------------------------------
  457. __inline void AT91F_SSC_DisableRx (
  458. AT91PS_SSC pSSC) // \arg pointer to a SSC controller
  459. {
  460. //* Disable receiver
  461. pSSC->SSC_CR = AT91C_SSC_RXDIS;
  462. }
  463. //*----------------------------------------------------------------------------
  464. //* \fn AT91F_SSC_EnableTx
  465. //* \brief Enable sending datas
  466. //*----------------------------------------------------------------------------
  467. __inline void AT91F_SSC_EnableTx (
  468. AT91PS_SSC pSSC) // \arg pointer to a SSC controller
  469. {
  470. //* Enable transmitter
  471. pSSC->SSC_CR = AT91C_SSC_TXEN;
  472. }
  473. //*----------------------------------------------------------------------------
  474. //* \fn AT91F_SSC_DisableTx
  475. //* \brief Disable sending datas
  476. //*----------------------------------------------------------------------------
  477. __inline void AT91F_SSC_DisableTx (
  478. AT91PS_SSC pSSC) // \arg pointer to a SSC controller
  479. {
  480. //* Disable transmitter
  481. pSSC->SSC_CR = AT91C_SSC_TXDIS;
  482. }
  483. //*----------------------------------------------------------------------------
  484. //* \fn AT91F_SSC_EnableIt
  485. //* \brief Enable SSC IT
  486. //*----------------------------------------------------------------------------
  487. __inline void AT91F_SSC_EnableIt (
  488. AT91PS_SSC pSSC, // \arg pointer to a SSC controller
  489. unsigned int flag) // \arg IT to be enabled
  490. {
  491. //* Write to the IER register
  492. pSSC->SSC_IER = flag;
  493. }
  494. //*----------------------------------------------------------------------------
  495. //* \fn AT91F_SSC_DisableIt
  496. //* \brief Disable SSC IT
  497. //*----------------------------------------------------------------------------
  498. __inline void AT91F_SSC_DisableIt (
  499. AT91PS_SSC pSSC, // \arg pointer to a SSC controller
  500. unsigned int flag) // \arg IT to be disabled
  501. {
  502. //* Write to the IDR register
  503. pSSC->SSC_IDR = flag;
  504. }
  505. //*----------------------------------------------------------------------------
  506. //* \fn AT91F_SSC_ReceiveFrame
  507. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
  508. //*----------------------------------------------------------------------------
  509. __inline unsigned int AT91F_SSC_ReceiveFrame (
  510. AT91PS_SSC pSSC,
  511. char *pBuffer,
  512. unsigned int szBuffer,
  513. char *pNextBuffer,
  514. unsigned int szNextBuffer )
  515. {
  516. return AT91F_PDC_ReceiveFrame(
  517. (AT91PS_PDC) &(pSSC->SSC_RPR),
  518. pBuffer,
  519. szBuffer,
  520. pNextBuffer,
  521. szNextBuffer);
  522. }
  523. //*----------------------------------------------------------------------------
  524. //* \fn AT91F_SSC_SendFrame
  525. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
  526. //*----------------------------------------------------------------------------
  527. __inline unsigned int AT91F_SSC_SendFrame(
  528. AT91PS_SSC pSSC,
  529. char *pBuffer,
  530. unsigned int szBuffer,
  531. char *pNextBuffer,
  532. unsigned int szNextBuffer )
  533. {
  534. return AT91F_PDC_SendFrame(
  535. (AT91PS_PDC) &(pSSC->SSC_RPR),
  536. pBuffer,
  537. szBuffer,
  538. pNextBuffer,
  539. szNextBuffer);
  540. }
  541. //*----------------------------------------------------------------------------
  542. //* \fn AT91F_SSC_GetInterruptMaskStatus
  543. //* \brief Return SSC Interrupt Mask Status
  544. //*----------------------------------------------------------------------------
  545. __inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
  546. AT91PS_SSC pSsc) // \arg pointer to a SSC controller
  547. {
  548. return pSsc->SSC_IMR;
  549. }
  550. //*----------------------------------------------------------------------------
  551. //* \fn AT91F_SSC_IsInterruptMasked
  552. //* \brief Test if SSC Interrupt is Masked
  553. //*----------------------------------------------------------------------------
  554. __inline int AT91F_SSC_IsInterruptMasked(
  555. AT91PS_SSC pSsc, // \arg pointer to a SSC controller
  556. unsigned int flag) // \arg flag to be tested
  557. {
  558. return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
  559. }
  560. /* *****************************************************************************
  561. SOFTWARE API FOR SPI
  562. ***************************************************************************** */
  563. //*----------------------------------------------------------------------------
  564. //* \fn AT91F_SPI_Open
  565. //* \brief Open a SPI Port
  566. //*----------------------------------------------------------------------------
  567. __inline unsigned int AT91F_SPI_Open (
  568. const unsigned int null) // \arg
  569. {
  570. /* NOT DEFINED AT THIS MOMENT */
  571. return ( 0 );
  572. }
  573. //*----------------------------------------------------------------------------
  574. //* \fn AT91F_SPI_CfgCs
  575. //* \brief Configure SPI chip select register
  576. //*----------------------------------------------------------------------------
  577. __inline void AT91F_SPI_CfgCs (
  578. AT91PS_SPI pSPI, // pointer to a SPI controller
  579. int cs, // SPI cs number (0 to 3)
  580. int val) // chip select register
  581. {
  582. //* Write to the CSR register
  583. *(pSPI->SPI_CSR + cs) = val;
  584. }
  585. //*----------------------------------------------------------------------------
  586. //* \fn AT91F_SPI_EnableIt
  587. //* \brief Enable SPI interrupt
  588. //*----------------------------------------------------------------------------
  589. __inline void AT91F_SPI_EnableIt (
  590. AT91PS_SPI pSPI, // pointer to a SPI controller
  591. unsigned int flag) // IT to be enabled
  592. {
  593. //* Write to the IER register
  594. pSPI->SPI_IER = flag;
  595. }
  596. //*----------------------------------------------------------------------------
  597. //* \fn AT91F_SPI_DisableIt
  598. //* \brief Disable SPI interrupt
  599. //*----------------------------------------------------------------------------
  600. __inline void AT91F_SPI_DisableIt (
  601. AT91PS_SPI pSPI, // pointer to a SPI controller
  602. unsigned int flag) // IT to be disabled
  603. {
  604. //* Write to the IDR register
  605. pSPI->SPI_IDR = flag;
  606. }
  607. //*----------------------------------------------------------------------------
  608. //* \fn AT91F_SPI_Reset
  609. //* \brief Reset the SPI controller
  610. //*----------------------------------------------------------------------------
  611. __inline void AT91F_SPI_Reset (
  612. AT91PS_SPI pSPI // pointer to a SPI controller
  613. )
  614. {
  615. //* Write to the CR register
  616. pSPI->SPI_CR = AT91C_SPI_SWRST;
  617. }
  618. //*----------------------------------------------------------------------------
  619. //* \fn AT91F_SPI_Enable
  620. //* \brief Enable the SPI controller
  621. //*----------------------------------------------------------------------------
  622. __inline void AT91F_SPI_Enable (
  623. AT91PS_SPI pSPI // pointer to a SPI controller
  624. )
  625. {
  626. //* Write to the CR register
  627. pSPI->SPI_CR = AT91C_SPI_SPIEN;
  628. }
  629. //*----------------------------------------------------------------------------
  630. //* \fn AT91F_SPI_Disable
  631. //* \brief Disable the SPI controller
  632. //*----------------------------------------------------------------------------
  633. __inline void AT91F_SPI_Disable (
  634. AT91PS_SPI pSPI // pointer to a SPI controller
  635. )
  636. {
  637. //* Write to the CR register
  638. pSPI->SPI_CR = AT91C_SPI_SPIDIS;
  639. }
  640. //*----------------------------------------------------------------------------
  641. //* \fn AT91F_SPI_CfgMode
  642. //* \brief Enable the SPI controller
  643. //*----------------------------------------------------------------------------
  644. __inline void AT91F_SPI_CfgMode (
  645. AT91PS_SPI pSPI, // pointer to a SPI controller
  646. int mode) // mode register
  647. {
  648. //* Write to the MR register
  649. pSPI->SPI_MR = mode;
  650. }
  651. //*----------------------------------------------------------------------------
  652. //* \fn AT91F_SPI_CfgPCS
  653. //* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
  654. //*----------------------------------------------------------------------------
  655. __inline void AT91F_SPI_CfgPCS (
  656. AT91PS_SPI pSPI, // pointer to a SPI controller
  657. char PCS_Device) // PCS of the Device
  658. {
  659. //* Write to the MR register
  660. pSPI->SPI_MR &= 0xFFF0FFFF;
  661. pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
  662. }
  663. //*----------------------------------------------------------------------------
  664. //* \fn AT91F_SPI_ReceiveFrame
  665. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
  666. //*----------------------------------------------------------------------------
  667. __inline unsigned int AT91F_SPI_ReceiveFrame (
  668. AT91PS_SPI pSPI,
  669. char *pBuffer,
  670. unsigned int szBuffer,
  671. char *pNextBuffer,
  672. unsigned int szNextBuffer )
  673. {
  674. return AT91F_PDC_ReceiveFrame(
  675. (AT91PS_PDC) &(pSPI->SPI_RPR),
  676. pBuffer,
  677. szBuffer,
  678. pNextBuffer,
  679. szNextBuffer);
  680. }
  681. //*----------------------------------------------------------------------------
  682. //* \fn AT91F_SPI_SendFrame
  683. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
  684. //*----------------------------------------------------------------------------
  685. __inline unsigned int AT91F_SPI_SendFrame(
  686. AT91PS_SPI pSPI,
  687. char *pBuffer,
  688. unsigned int szBuffer,
  689. char *pNextBuffer,
  690. unsigned int szNextBuffer )
  691. {
  692. return AT91F_PDC_SendFrame(
  693. (AT91PS_PDC) &(pSPI->SPI_RPR),
  694. pBuffer,
  695. szBuffer,
  696. pNextBuffer,
  697. szNextBuffer);
  698. }
  699. //*----------------------------------------------------------------------------
  700. //* \fn AT91F_SPI_Close
  701. //* \brief Close SPI: disable IT disable transfert, close PDC
  702. //*----------------------------------------------------------------------------
  703. __inline void AT91F_SPI_Close (
  704. AT91PS_SPI pSPI) // \arg pointer to a SPI controller
  705. {
  706. //* Reset all the Chip Select register
  707. pSPI->SPI_CSR[0] = 0 ;
  708. pSPI->SPI_CSR[1] = 0 ;
  709. pSPI->SPI_CSR[2] = 0 ;
  710. pSPI->SPI_CSR[3] = 0 ;
  711. //* Reset the SPI mode
  712. pSPI->SPI_MR = 0 ;
  713. //* Disable all interrupts
  714. pSPI->SPI_IDR = 0xFFFFFFFF ;
  715. //* Abort the Peripheral Data Transfers
  716. AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
  717. //* Disable receiver and transmitter and stop any activity immediately
  718. pSPI->SPI_CR = AT91C_SPI_SPIDIS;
  719. }
  720. //*----------------------------------------------------------------------------
  721. //* \fn AT91F_SPI_PutChar
  722. //* \brief Send a character,does not check if ready to send
  723. //*----------------------------------------------------------------------------
  724. __inline void AT91F_SPI_PutChar (
  725. AT91PS_SPI pSPI,
  726. unsigned int character,
  727. unsigned int cs_number )
  728. {
  729. unsigned int value_for_cs;
  730. value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number
  731. pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
  732. }
  733. //*----------------------------------------------------------------------------
  734. //* \fn AT91F_SPI_GetChar
  735. //* \brief Receive a character,does not check if a character is available
  736. //*----------------------------------------------------------------------------
  737. __inline int AT91F_SPI_GetChar (
  738. const AT91PS_SPI pSPI)
  739. {
  740. return((pSPI->SPI_RDR) & 0xFFFF);
  741. }
  742. //*----------------------------------------------------------------------------
  743. //* \fn AT91F_SPI_GetInterruptMaskStatus
  744. //* \brief Return SPI Interrupt Mask Status
  745. //*----------------------------------------------------------------------------
  746. __inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
  747. AT91PS_SPI pSpi) // \arg pointer to a SPI controller
  748. {
  749. return pSpi->SPI_IMR;
  750. }
  751. //*----------------------------------------------------------------------------
  752. //* \fn AT91F_SPI_IsInterruptMasked
  753. //* \brief Test if SPI Interrupt is Masked
  754. //*----------------------------------------------------------------------------
  755. __inline int AT91F_SPI_IsInterruptMasked(
  756. AT91PS_SPI pSpi, // \arg pointer to a SPI controller
  757. unsigned int flag) // \arg flag to be tested
  758. {
  759. return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
  760. }
  761. /* *****************************************************************************
  762. SOFTWARE API FOR PWMC
  763. ***************************************************************************** */
  764. //*----------------------------------------------------------------------------
  765. //* \fn AT91F_PWM_GetStatus
  766. //* \brief Return PWM Interrupt Status
  767. //*----------------------------------------------------------------------------
  768. __inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
  769. AT91PS_PWMC pPWM) // pointer to a PWM controller
  770. {
  771. return pPWM->PWMC_SR;
  772. }
  773. //*----------------------------------------------------------------------------
  774. //* \fn AT91F_PWM_InterruptEnable
  775. //* \brief Enable PWM Interrupt
  776. //*----------------------------------------------------------------------------
  777. __inline void AT91F_PWMC_InterruptEnable(
  778. AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
  779. unsigned int flag) // \arg PWM interrupt to be enabled
  780. {
  781. pPwm->PWMC_IER = flag;
  782. }
  783. //*----------------------------------------------------------------------------
  784. //* \fn AT91F_PWM_InterruptDisable
  785. //* \brief Disable PWM Interrupt
  786. //*----------------------------------------------------------------------------
  787. __inline void AT91F_PWMC_InterruptDisable(
  788. AT91PS_PWMC pPwm, // \arg pointer to a PWM controller
  789. unsigned int flag) // \arg PWM interrupt to be disabled
  790. {
  791. pPwm->PWMC_IDR = flag;
  792. }
  793. //*----------------------------------------------------------------------------
  794. //* \fn AT91F_PWM_GetInterruptMaskStatus
  795. //* \brief Return PWM Interrupt Mask Status
  796. //*----------------------------------------------------------------------------
  797. __inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
  798. AT91PS_PWMC pPwm) // \arg pointer to a PWM controller
  799. {
  800. return pPwm->PWMC_IMR;
  801. }
  802. //*----------------------------------------------------------------------------
  803. //* \fn AT91F_PWM_IsInterruptMasked
  804. //* \brief Test if PWM Interrupt is Masked
  805. //*----------------------------------------------------------------------------
  806. __inline unsigned int AT91F_PWMC_IsInterruptMasked(
  807. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  808. unsigned int flag) // \arg flag to be tested
  809. {
  810. return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
  811. }
  812. //*----------------------------------------------------------------------------
  813. //* \fn AT91F_PWM_IsStatusSet
  814. //* \brief Test if PWM Interrupt is Set
  815. //*----------------------------------------------------------------------------
  816. __inline unsigned int AT91F_PWMC_IsStatusSet(
  817. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  818. unsigned int flag) // \arg flag to be tested
  819. {
  820. return (AT91F_PWMC_GetStatus(pPWM) & flag);
  821. }
  822. //*----------------------------------------------------------------------------
  823. //* \fn AT91F_PWM_CfgChannel
  824. //* \brief Test if PWM Interrupt is Set
  825. //*----------------------------------------------------------------------------
  826. __inline void AT91F_PWMC_CfgChannel(
  827. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  828. unsigned int channelId, // \arg PWM channel ID
  829. unsigned int mode, // \arg PWM mode
  830. unsigned int period, // \arg PWM period
  831. unsigned int duty) // \arg PWM duty cycle
  832. {
  833. pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
  834. pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
  835. pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
  836. }
  837. //*----------------------------------------------------------------------------
  838. //* \fn AT91F_PWM_StartChannel
  839. //* \brief Enable channel
  840. //*----------------------------------------------------------------------------
  841. __inline void AT91F_PWMC_StartChannel(
  842. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  843. unsigned int flag) // \arg Channels IDs to be enabled
  844. {
  845. pPWM->PWMC_ENA = flag;
  846. }
  847. //*----------------------------------------------------------------------------
  848. //* \fn AT91F_PWM_StopChannel
  849. //* \brief Disable channel
  850. //*----------------------------------------------------------------------------
  851. __inline void AT91F_PWMC_StopChannel(
  852. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  853. unsigned int flag) // \arg Channels IDs to be enabled
  854. {
  855. pPWM->PWMC_DIS = flag;
  856. }
  857. //*----------------------------------------------------------------------------
  858. //* \fn AT91F_PWM_UpdateChannel
  859. //* \brief Update Period or Duty Cycle
  860. //*----------------------------------------------------------------------------
  861. __inline void AT91F_PWMC_UpdateChannel(
  862. AT91PS_PWMC pPWM, // \arg pointer to a PWM controller
  863. unsigned int channelId, // \arg PWM channel ID
  864. unsigned int update) // \arg Channels IDs to be enabled
  865. {
  866. pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
  867. }
  868. /* *****************************************************************************
  869. SOFTWARE API FOR TC
  870. ***************************************************************************** */
  871. //*----------------------------------------------------------------------------
  872. //* \fn AT91F_TC_InterruptEnable
  873. //* \brief Enable TC Interrupt
  874. //*----------------------------------------------------------------------------
  875. __inline void AT91F_TC_InterruptEnable(
  876. AT91PS_TC pTc, // \arg pointer to a TC controller
  877. unsigned int flag) // \arg TC interrupt to be enabled
  878. {
  879. pTc->TC_IER = flag;
  880. }
  881. //*----------------------------------------------------------------------------
  882. //* \fn AT91F_TC_InterruptDisable
  883. //* \brief Disable TC Interrupt
  884. //*----------------------------------------------------------------------------
  885. __inline void AT91F_TC_InterruptDisable(
  886. AT91PS_TC pTc, // \arg pointer to a TC controller
  887. unsigned int flag) // \arg TC interrupt to be disabled
  888. {
  889. pTc->TC_IDR = flag;
  890. }
  891. //*----------------------------------------------------------------------------
  892. //* \fn AT91F_TC_GetInterruptMaskStatus
  893. //* \brief Return TC Interrupt Mask Status
  894. //*----------------------------------------------------------------------------
  895. __inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
  896. AT91PS_TC pTc) // \arg pointer to a TC controller
  897. {
  898. return pTc->TC_IMR;
  899. }
  900. //*----------------------------------------------------------------------------
  901. //* \fn AT91F_TC_IsInterruptMasked
  902. //* \brief Test if TC Interrupt is Masked
  903. //*----------------------------------------------------------------------------
  904. __inline int AT91F_TC_IsInterruptMasked(
  905. AT91PS_TC pTc, // \arg pointer to a TC controller
  906. unsigned int flag) // \arg flag to be tested
  907. {
  908. return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
  909. }
  910. /* *****************************************************************************
  911. SOFTWARE API FOR PMC
  912. ***************************************************************************** */
  913. //*----------------------------------------------------------------------------
  914. //* \fn AT91F_PMC_CfgSysClkEnableReg
  915. //* \brief Configure the System Clock Enable Register of the PMC controller
  916. //*----------------------------------------------------------------------------
  917. __inline void AT91F_PMC_CfgSysClkEnableReg (
  918. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  919. unsigned int mode)
  920. {
  921. //* Write to the SCER register
  922. pPMC->PMC_SCER = mode;
  923. }
  924. //*----------------------------------------------------------------------------
  925. //* \fn AT91F_PMC_CfgSysClkDisableReg
  926. //* \brief Configure the System Clock Disable Register of the PMC controller
  927. //*----------------------------------------------------------------------------
  928. __inline void AT91F_PMC_CfgSysClkDisableReg (
  929. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  930. unsigned int mode)
  931. {
  932. //* Write to the SCDR register
  933. pPMC->PMC_SCDR = mode;
  934. }
  935. //*----------------------------------------------------------------------------
  936. //* \fn AT91F_PMC_GetSysClkStatusReg
  937. //* \brief Return the System Clock Status Register of the PMC controller
  938. //*----------------------------------------------------------------------------
  939. __inline unsigned int AT91F_PMC_GetSysClkStatusReg (
  940. AT91PS_PMC pPMC // pointer to a CAN controller
  941. )
  942. {
  943. return pPMC->PMC_SCSR;
  944. }
  945. //*----------------------------------------------------------------------------
  946. //* \fn AT91F_PMC_EnablePeriphClock
  947. //* \brief Enable peripheral clock
  948. //*----------------------------------------------------------------------------
  949. __inline void AT91F_PMC_EnablePeriphClock (
  950. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  951. unsigned int periphIds) // \arg IDs of peripherals to enable
  952. {
  953. pPMC->PMC_PCER = periphIds;
  954. }
  955. //*----------------------------------------------------------------------------
  956. //* \fn AT91F_PMC_DisablePeriphClock
  957. //* \brief Disable peripheral clock
  958. //*----------------------------------------------------------------------------
  959. __inline void AT91F_PMC_DisablePeriphClock (
  960. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  961. unsigned int periphIds) // \arg IDs of peripherals to enable
  962. {
  963. pPMC->PMC_PCDR = periphIds;
  964. }
  965. //*----------------------------------------------------------------------------
  966. //* \fn AT91F_PMC_GetPeriphClock
  967. //* \brief Get peripheral clock status
  968. //*----------------------------------------------------------------------------
  969. __inline unsigned int AT91F_PMC_GetPeriphClock (
  970. AT91PS_PMC pPMC) // \arg pointer to PMC controller
  971. {
  972. return pPMC->PMC_PCSR;
  973. }
  974. //*----------------------------------------------------------------------------
  975. //* \fn AT91F_CKGR_CfgMainOscillatorReg
  976. //* \brief Cfg the main oscillator
  977. //*----------------------------------------------------------------------------
  978. __inline void AT91F_CKGR_CfgMainOscillatorReg (
  979. AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
  980. unsigned int mode)
  981. {
  982. pCKGR->CKGR_MOR = mode;
  983. }
  984. //*----------------------------------------------------------------------------
  985. //* \fn AT91F_CKGR_GetMainOscillatorReg
  986. //* \brief Cfg the main oscillator
  987. //*----------------------------------------------------------------------------
  988. __inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
  989. AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
  990. {
  991. return pCKGR->CKGR_MOR;
  992. }
  993. //*----------------------------------------------------------------------------
  994. //* \fn AT91F_CKGR_EnableMainOscillator
  995. //* \brief Enable the main oscillator
  996. //*----------------------------------------------------------------------------
  997. __inline void AT91F_CKGR_EnableMainOscillator(
  998. AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
  999. {
  1000. pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
  1001. }
  1002. //*----------------------------------------------------------------------------
  1003. //* \fn AT91F_CKGR_DisableMainOscillator
  1004. //* \brief Disable the main oscillator
  1005. //*----------------------------------------------------------------------------
  1006. __inline void AT91F_CKGR_DisableMainOscillator (
  1007. AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
  1008. {
  1009. pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
  1010. }
  1011. //*----------------------------------------------------------------------------
  1012. //* \fn AT91F_CKGR_CfgMainOscStartUpTime
  1013. //* \brief Cfg MOR Register according to the main osc startup time
  1014. //*----------------------------------------------------------------------------
  1015. __inline void AT91F_CKGR_CfgMainOscStartUpTime (
  1016. AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
  1017. unsigned int startup_time, // \arg main osc startup time in microsecond (us)
  1018. unsigned int slowClock) // \arg slowClock in Hz
  1019. {
  1020. pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
  1021. pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
  1022. }
  1023. //*----------------------------------------------------------------------------
  1024. //* \fn AT91F_CKGR_GetMainClockFreqReg
  1025. //* \brief Cfg the main oscillator
  1026. //*----------------------------------------------------------------------------
  1027. __inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
  1028. AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
  1029. {
  1030. return pCKGR->CKGR_MCFR;
  1031. }
  1032. //*----------------------------------------------------------------------------
  1033. //* \fn AT91F_CKGR_GetMainClock
  1034. //* \brief Return Main clock in Hz
  1035. //*----------------------------------------------------------------------------
  1036. __inline unsigned int AT91F_CKGR_GetMainClock (
  1037. AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
  1038. unsigned int slowClock) // \arg slowClock in Hz
  1039. {
  1040. return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4;
  1041. }
  1042. //*----------------------------------------------------------------------------
  1043. //* \fn AT91F_PMC_CfgMCKReg
  1044. //* \brief Cfg Master Clock Register
  1045. //*----------------------------------------------------------------------------
  1046. __inline void AT91F_PMC_CfgMCKReg (
  1047. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  1048. unsigned int mode)
  1049. {
  1050. pPMC->PMC_MCKR = mode;
  1051. }
  1052. //*----------------------------------------------------------------------------
  1053. //* \fn AT91F_PMC_GetMCKReg
  1054. //* \brief Return Master Clock Register
  1055. //*----------------------------------------------------------------------------
  1056. __inline unsigned int AT91F_PMC_GetMCKReg(
  1057. AT91PS_PMC pPMC) // \arg pointer to PMC controller
  1058. {
  1059. return pPMC->PMC_MCKR;
  1060. }
  1061. //*------------------------------------------------------------------------------
  1062. //* \fn AT91F_PMC_GetMasterClock
  1063. //* \brief Return master clock in Hz which correponds to processor clock for ARM7
  1064. //*------------------------------------------------------------------------------
  1065. __inline unsigned int AT91F_PMC_GetMasterClock (
  1066. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  1067. AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
  1068. unsigned int slowClock) // \arg slowClock in Hz
  1069. {
  1070. unsigned int reg = pPMC->PMC_MCKR;
  1071. unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
  1072. unsigned int pllDivider, pllMultiplier;
  1073. switch (reg & AT91C_PMC_CSS) {
  1074. case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
  1075. return slowClock / prescaler;
  1076. case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
  1077. return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
  1078. case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
  1079. reg = pCKGR->CKGR_PLLR;
  1080. pllDivider = (reg & AT91C_CKGR_DIV);
  1081. pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1;
  1082. return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
  1083. }
  1084. return 0;
  1085. }
  1086. //*----------------------------------------------------------------------------
  1087. //* \fn AT91F_PMC_EnablePCK
  1088. //* \brief Enable peripheral clock
  1089. //*----------------------------------------------------------------------------
  1090. __inline void AT91F_PMC_EnablePCK (
  1091. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  1092. unsigned int pck, // \arg Peripheral clock identifier 0 .. 7
  1093. unsigned int mode)
  1094. {
  1095. pPMC->PMC_PCKR[pck] = mode;
  1096. pPMC->PMC_SCER = (1 << pck) << 8;
  1097. }
  1098. //*----------------------------------------------------------------------------
  1099. //* \fn AT91F_PMC_DisablePCK
  1100. //* \brief Enable peripheral clock
  1101. //*----------------------------------------------------------------------------
  1102. __inline void AT91F_PMC_DisablePCK (
  1103. AT91PS_PMC pPMC, // \arg pointer to PMC controller
  1104. unsigned int pck) // \arg Peripheral clock identifier 0 .. 7
  1105. {
  1106. pPMC->PMC_SCDR = (1 << pck) << 8;
  1107. }
  1108. //*----------------------------------------------------------------------------
  1109. //* \fn AT91F_PMC_EnableIt
  1110. //* \brief Enable PMC interrupt
  1111. //*----------------------------------------------------------------------------
  1112. __inline void AT91F_PMC_EnableIt (
  1113. AT91PS_PMC pPMC, // pointer to a PMC controller
  1114. unsigned int flag) // IT to be enabled
  1115. {
  1116. //* Write to the IER register
  1117. pPMC->PMC_IER = flag;
  1118. }
  1119. //*----------------------------------------------------------------------------
  1120. //* \fn AT91F_PMC_DisableIt
  1121. //* \brief Disable PMC interrupt
  1122. //*----------------------------------------------------------------------------
  1123. __inline void AT91F_PMC_DisableIt (
  1124. AT91PS_PMC pPMC, // pointer to a PMC controller
  1125. unsigned int flag) // IT to be disabled
  1126. {
  1127. //* Write to the IDR register
  1128. pPMC->PMC_IDR = flag;
  1129. }
  1130. //*----------------------------------------------------------------------------
  1131. //* \fn AT91F_PMC_GetStatus
  1132. //* \brief Return PMC Interrupt Status
  1133. //*----------------------------------------------------------------------------
  1134. __inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
  1135. AT91PS_PMC pPMC) // pointer to a PMC controller
  1136. {
  1137. return pPMC->PMC_SR;
  1138. }
  1139. //*----------------------------------------------------------------------------
  1140. //* \fn AT91F_PMC_GetInterruptMaskStatus
  1141. //* \brief Return PMC Interrupt Mask Status
  1142. //*----------------------------------------------------------------------------
  1143. __inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
  1144. AT91PS_PMC pPMC) // pointer to a PMC controller
  1145. {
  1146. return pPMC->PMC_IMR;
  1147. }
  1148. //*----------------------------------------------------------------------------
  1149. //* \fn AT91F_PMC_IsInterruptMasked
  1150. //* \brief Test if PMC Interrupt is Masked
  1151. //*----------------------------------------------------------------------------
  1152. __inline unsigned int AT91F_PMC_IsInterruptMasked(
  1153. AT91PS_PMC pPMC, // \arg pointer to a PMC controller
  1154. unsigned int flag) // \arg flag to be tested
  1155. {
  1156. return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
  1157. }
  1158. //*----------------------------------------------------------------------------
  1159. //* \fn AT91F_PMC_IsStatusSet
  1160. //* \brief Test if PMC Status is Set
  1161. //*----------------------------------------------------------------------------
  1162. __inline unsigned int AT91F_PMC_IsStatusSet(
  1163. AT91PS_PMC pPMC, // \arg pointer to a PMC controller
  1164. unsigned int flag) // \arg flag to be tested
  1165. {
  1166. return (AT91F_PMC_GetStatus(pPMC) & flag);
  1167. }/* *****************************************************************************
  1168. SOFTWARE API FOR ADC
  1169. ***************************************************************************** */
  1170. //*----------------------------------------------------------------------------
  1171. //* \fn AT91F_ADC_EnableIt
  1172. //* \brief Enable ADC interrupt
  1173. //*----------------------------------------------------------------------------
  1174. __inline void AT91F_ADC_EnableIt (
  1175. AT91PS_ADC pADC, // pointer to a ADC controller
  1176. unsigned int flag) // IT to be enabled
  1177. {
  1178. //* Write to the IER register
  1179. pADC->ADC_IER = flag;
  1180. }
  1181. //*----------------------------------------------------------------------------
  1182. //* \fn AT91F_ADC_DisableIt
  1183. //* \brief Disable ADC interrupt
  1184. //*----------------------------------------------------------------------------
  1185. __inline void AT91F_ADC_DisableIt (
  1186. AT91PS_ADC pADC, // pointer to a ADC controller
  1187. unsigned int flag) // IT to be disabled
  1188. {
  1189. //* Write to the IDR register
  1190. pADC->ADC_IDR = flag;
  1191. }
  1192. //*----------------------------------------------------------------------------
  1193. //* \fn AT91F_ADC_GetStatus
  1194. //* \brief Return ADC Interrupt Status
  1195. //*----------------------------------------------------------------------------
  1196. __inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
  1197. AT91PS_ADC pADC) // pointer to a ADC controller
  1198. {
  1199. return pADC->ADC_SR;
  1200. }
  1201. //*----------------------------------------------------------------------------
  1202. //* \fn AT91F_ADC_GetInterruptMaskStatus
  1203. //* \brief Return ADC Interrupt Mask Status
  1204. //*----------------------------------------------------------------------------
  1205. __inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
  1206. AT91PS_ADC pADC) // pointer to a ADC controller
  1207. {
  1208. return pADC->ADC_IMR;
  1209. }
  1210. //*----------------------------------------------------------------------------
  1211. //* \fn AT91F_ADC_IsInterruptMasked
  1212. //* \brief Test if ADC Interrupt is Masked
  1213. //*----------------------------------------------------------------------------
  1214. __inline unsigned int AT91F_ADC_IsInterruptMasked(
  1215. AT91PS_ADC pADC, // \arg pointer to a ADC controller
  1216. unsigned int flag) // \arg flag to be tested
  1217. {
  1218. return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
  1219. }
  1220. //*----------------------------------------------------------------------------
  1221. //* \fn AT91F_ADC_IsStatusSet
  1222. //* \brief Test if ADC Status is Set
  1223. //*----------------------------------------------------------------------------
  1224. __inline unsigned int AT91F_ADC_IsStatusSet(
  1225. AT91PS_ADC pADC, // \arg pointer to a ADC controller
  1226. unsigned int flag) // \arg flag to be tested
  1227. {
  1228. return (AT91F_ADC_GetStatus(pADC) & flag);
  1229. }
  1230. //*----------------------------------------------------------------------------
  1231. //* \fn AT91F_ADC_CfgModeReg
  1232. //* \brief Configure the Mode Register of the ADC controller
  1233. //*----------------------------------------------------------------------------
  1234. __inline void AT91F_ADC_CfgModeReg (
  1235. AT91PS_ADC pADC, // pointer to a ADC controller
  1236. unsigned int mode) // mode register
  1237. {
  1238. //* Write to the MR register
  1239. pADC->ADC_MR = mode;
  1240. }
  1241. //*----------------------------------------------------------------------------
  1242. //* \fn AT91F_ADC_GetModeReg
  1243. //* \brief Return the Mode Register of the ADC controller value
  1244. //*----------------------------------------------------------------------------
  1245. __inline unsigned int AT91F_ADC_GetModeReg (
  1246. AT91PS_ADC pADC // pointer to a ADC controller
  1247. )
  1248. {
  1249. return pADC->ADC_MR;
  1250. }
  1251. //*----------------------------------------------------------------------------
  1252. //* \fn AT91F_ADC_CfgTimings
  1253. //* \brief Configure the different necessary timings of the ADC controller
  1254. //*----------------------------------------------------------------------------
  1255. __inline void AT91F_ADC_CfgTimings (
  1256. AT91PS_ADC pADC, // pointer to a ADC controller
  1257. unsigned int mck_clock, // in MHz
  1258. unsigned int adc_clock, // in MHz
  1259. unsigned int startup_time, // in us
  1260. unsigned int sample_and_hold_time) // in ns
  1261. {
  1262. unsigned int prescal,startup,shtim;
  1263. prescal = mck_clock/(2*adc_clock) - 1;
  1264. startup = adc_clock*startup_time/8 - 1;
  1265. shtim = adc_clock*sample_and_hold_time/1000 - 1;
  1266. //* Write to the MR register
  1267. pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
  1268. }
  1269. //*----------------------------------------------------------------------------
  1270. //* \fn AT91F_ADC_EnableChannel
  1271. //* \brief Return ADC Timer Register Value
  1272. //*----------------------------------------------------------------------------
  1273. __inline void AT91F_ADC_EnableChannel (
  1274. AT91PS_ADC pADC, // pointer to a ADC controller
  1275. unsigned int channel) // mode register
  1276. {
  1277. //* Write to the CHER register
  1278. pADC->ADC_CHER = channel;
  1279. }
  1280. //*----------------------------------------------------------------------------
  1281. //* \fn AT91F_ADC_DisableChannel
  1282. //* \brief Return ADC Timer Register Value
  1283. //*----------------------------------------------------------------------------
  1284. __inline void AT91F_ADC_DisableChannel (
  1285. AT91PS_ADC pADC, // pointer to a ADC controller
  1286. unsigned int channel) // mode register
  1287. {
  1288. //* Write to the CHDR register
  1289. pADC->ADC_CHDR = channel;
  1290. }
  1291. //*----------------------------------------------------------------------------
  1292. //* \fn AT91F_ADC_GetChannelStatus
  1293. //* \brief Return ADC Timer Register Value
  1294. //*----------------------------------------------------------------------------
  1295. __inline unsigned int AT91F_ADC_GetChannelStatus (
  1296. AT91PS_ADC pADC // pointer to a ADC controller
  1297. )
  1298. {
  1299. return pADC->ADC_CHSR;
  1300. }
  1301. //*----------------------------------------------------------------------------
  1302. //* \fn AT91F_ADC_StartConversion
  1303. //* \brief Software request for a analog to digital conversion
  1304. //*----------------------------------------------------------------------------
  1305. __inline void AT91F_ADC_StartConversion (
  1306. AT91PS_ADC pADC // pointer to a ADC controller
  1307. )
  1308. {
  1309. pADC->ADC_CR = AT91C_ADC_START;
  1310. }
  1311. //*----------------------------------------------------------------------------
  1312. //* \fn AT91F_ADC_SoftReset
  1313. //* \brief Software reset
  1314. //*----------------------------------------------------------------------------
  1315. __inline void AT91F_ADC_SoftReset (
  1316. AT91PS_ADC pADC // pointer to a ADC controller
  1317. )
  1318. {
  1319. pADC->ADC_CR = AT91C_ADC_SWRST;
  1320. }
  1321. //*----------------------------------------------------------------------------
  1322. //* \fn AT91F_ADC_GetLastConvertedData
  1323. //* \brief Return the Last Converted Data
  1324. //*----------------------------------------------------------------------------
  1325. __inline unsigned int AT91F_ADC_GetLastConvertedData (
  1326. AT91PS_ADC pADC // pointer to a ADC controller
  1327. )
  1328. {
  1329. return pADC->ADC_LCDR;
  1330. }
  1331. //*----------------------------------------------------------------------------
  1332. //* \fn AT91F_ADC_GetConvertedDataCH0
  1333. //* \brief Return the Channel 0 Converted Data
  1334. //*----------------------------------------------------------------------------
  1335. __inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
  1336. AT91PS_ADC pADC // pointer to a ADC controller
  1337. )
  1338. {
  1339. return pADC->ADC_CDR0;
  1340. }
  1341. //*----------------------------------------------------------------------------
  1342. //* \fn AT91F_ADC_GetConvertedDataCH1
  1343. //* \brief Return the Channel 1 Converted Data
  1344. //*----------------------------------------------------------------------------
  1345. __inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
  1346. AT91PS_ADC pADC // pointer to a ADC controller
  1347. )
  1348. {
  1349. return pADC->ADC_CDR1;
  1350. }
  1351. //*----------------------------------------------------------------------------
  1352. //* \fn AT91F_ADC_GetConvertedDataCH2
  1353. //* \brief Return the Channel 2 Converted Data
  1354. //*----------------------------------------------------------------------------
  1355. __inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
  1356. AT91PS_ADC pADC // pointer to a ADC controller
  1357. )
  1358. {
  1359. return pADC->ADC_CDR2;
  1360. }
  1361. //*----------------------------------------------------------------------------
  1362. //* \fn AT91F_ADC_GetConvertedDataCH3
  1363. //* \brief Return the Channel 3 Converted Data
  1364. //*----------------------------------------------------------------------------
  1365. __inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
  1366. AT91PS_ADC pADC // pointer to a ADC controller
  1367. )
  1368. {
  1369. return pADC->ADC_CDR3;
  1370. }
  1371. //*----------------------------------------------------------------------------
  1372. //* \fn AT91F_ADC_GetConvertedDataCH4
  1373. //* \brief Return the Channel 4 Converted Data
  1374. //*----------------------------------------------------------------------------
  1375. __inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
  1376. AT91PS_ADC pADC // pointer to a ADC controller
  1377. )
  1378. {
  1379. return pADC->ADC_CDR4;
  1380. }
  1381. //*----------------------------------------------------------------------------
  1382. //* \fn AT91F_ADC_GetConvertedDataCH5
  1383. //* \brief Return the Channel 5 Converted Data
  1384. //*----------------------------------------------------------------------------
  1385. __inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
  1386. AT91PS_ADC pADC // pointer to a ADC controller
  1387. )
  1388. {
  1389. return pADC->ADC_CDR5;
  1390. }
  1391. //*----------------------------------------------------------------------------
  1392. //* \fn AT91F_ADC_GetConvertedDataCH6
  1393. //* \brief Return the Channel 6 Converted Data
  1394. //*----------------------------------------------------------------------------
  1395. __inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
  1396. AT91PS_ADC pADC // pointer to a ADC controller
  1397. )
  1398. {
  1399. return pADC->ADC_CDR6;
  1400. }
  1401. //*----------------------------------------------------------------------------
  1402. //* \fn AT91F_ADC_GetConvertedDataCH7
  1403. //* \brief Return the Channel 7 Converted Data
  1404. //*----------------------------------------------------------------------------
  1405. __inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
  1406. AT91PS_ADC pADC // pointer to a ADC controller
  1407. )
  1408. {
  1409. return pADC->ADC_CDR7;
  1410. }
  1411. /* *****************************************************************************
  1412. SOFTWARE API FOR PIO
  1413. ***************************************************************************** */
  1414. //*----------------------------------------------------------------------------
  1415. //* \fn AT91F_PIO_CfgPeriph
  1416. //* \brief Enable pins to be drived by peripheral
  1417. //*----------------------------------------------------------------------------
  1418. __inline void AT91F_PIO_CfgPeriph(
  1419. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1420. unsigned int periphAEnable, // \arg PERIPH A to enable
  1421. unsigned int periphBEnable) // \arg PERIPH B to enable
  1422. {
  1423. pPio->PIO_ASR = periphAEnable;
  1424. pPio->PIO_BSR = periphBEnable;
  1425. pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
  1426. }
  1427. //*----------------------------------------------------------------------------
  1428. //* \fn AT91F_PIO_CfgOutput
  1429. //* \brief Enable PIO in output mode
  1430. //*----------------------------------------------------------------------------
  1431. __inline void AT91F_PIO_CfgOutput(
  1432. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1433. unsigned int pioEnable) // \arg PIO to be enabled
  1434. {
  1435. pPio->PIO_PER = pioEnable; // Set in PIO mode
  1436. pPio->PIO_OER = pioEnable; // Configure in Output
  1437. }
  1438. //*----------------------------------------------------------------------------
  1439. //* \fn AT91F_PIO_CfgInput
  1440. //* \brief Enable PIO in input mode
  1441. //*----------------------------------------------------------------------------
  1442. __inline void AT91F_PIO_CfgInput(
  1443. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1444. unsigned int inputEnable) // \arg PIO to be enabled
  1445. {
  1446. // Disable output
  1447. pPio->PIO_ODR = inputEnable;
  1448. pPio->PIO_PER = inputEnable;
  1449. }
  1450. //*----------------------------------------------------------------------------
  1451. //* \fn AT91F_PIO_CfgOpendrain
  1452. //* \brief Configure PIO in open drain
  1453. //*----------------------------------------------------------------------------
  1454. __inline void AT91F_PIO_CfgOpendrain(
  1455. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1456. unsigned int multiDrvEnable) // \arg pio to be configured in open drain
  1457. {
  1458. // Configure the multi-drive option
  1459. pPio->PIO_MDDR = ~multiDrvEnable;
  1460. pPio->PIO_MDER = multiDrvEnable;
  1461. }
  1462. //*----------------------------------------------------------------------------
  1463. //* \fn AT91F_PIO_CfgPullup
  1464. //* \brief Enable pullup on PIO
  1465. //*----------------------------------------------------------------------------
  1466. __inline void AT91F_PIO_CfgPullup(
  1467. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1468. unsigned int pullupEnable) // \arg enable pullup on PIO
  1469. {
  1470. // Connect or not Pullup
  1471. pPio->PIO_PPUDR = ~pullupEnable;
  1472. pPio->PIO_PPUER = pullupEnable;
  1473. }
  1474. //*----------------------------------------------------------------------------
  1475. //* \fn AT91F_PIO_CfgDirectDrive
  1476. //* \brief Enable direct drive on PIO
  1477. //*----------------------------------------------------------------------------
  1478. __inline void AT91F_PIO_CfgDirectDrive(
  1479. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1480. unsigned int directDrive) // \arg PIO to be configured with direct drive
  1481. {
  1482. // Configure the Direct Drive
  1483. pPio->PIO_OWDR = ~directDrive;
  1484. pPio->PIO_OWER = directDrive;
  1485. }
  1486. //*----------------------------------------------------------------------------
  1487. //* \fn AT91F_PIO_CfgInputFilter
  1488. //* \brief Enable input filter on input PIO
  1489. //*----------------------------------------------------------------------------
  1490. __inline void AT91F_PIO_CfgInputFilter(
  1491. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1492. unsigned int inputFilter) // \arg PIO to be configured with input filter
  1493. {
  1494. // Configure the Direct Drive
  1495. pPio->PIO_IFDR = ~inputFilter;
  1496. pPio->PIO_IFER = inputFilter;
  1497. }
  1498. //*----------------------------------------------------------------------------
  1499. //* \fn AT91F_PIO_GetInput
  1500. //* \brief Return PIO input value
  1501. //*----------------------------------------------------------------------------
  1502. __inline unsigned int AT91F_PIO_GetInput( // \return PIO input
  1503. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1504. {
  1505. return pPio->PIO_PDSR;
  1506. }
  1507. //*----------------------------------------------------------------------------
  1508. //* \fn AT91F_PIO_IsInputSet
  1509. //* \brief Test if PIO is input flag is active
  1510. //*----------------------------------------------------------------------------
  1511. __inline int AT91F_PIO_IsInputSet(
  1512. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1513. unsigned int flag) // \arg flag to be tested
  1514. {
  1515. return (AT91F_PIO_GetInput(pPio) & flag);
  1516. }
  1517. //*----------------------------------------------------------------------------
  1518. //* \fn AT91F_PIO_SetOutput
  1519. //* \brief Set to 1 output PIO
  1520. //*----------------------------------------------------------------------------
  1521. __inline void AT91F_PIO_SetOutput(
  1522. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1523. unsigned int flag) // \arg output to be set
  1524. {
  1525. pPio->PIO_SODR = flag;
  1526. }
  1527. //*----------------------------------------------------------------------------
  1528. //* \fn AT91F_PIO_ClearOutput
  1529. //* \brief Set to 0 output PIO
  1530. //*----------------------------------------------------------------------------
  1531. __inline void AT91F_PIO_ClearOutput(
  1532. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1533. unsigned int flag) // \arg output to be cleared
  1534. {
  1535. pPio->PIO_CODR = flag;
  1536. }
  1537. //*----------------------------------------------------------------------------
  1538. //* \fn AT91F_PIO_ForceOutput
  1539. //* \brief Force output when Direct drive option is enabled
  1540. //*----------------------------------------------------------------------------
  1541. __inline void AT91F_PIO_ForceOutput(
  1542. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1543. unsigned int flag) // \arg output to be forced
  1544. {
  1545. pPio->PIO_ODSR = flag;
  1546. }
  1547. //*----------------------------------------------------------------------------
  1548. //* \fn AT91F_PIO_Enable
  1549. //* \brief Enable PIO
  1550. //*----------------------------------------------------------------------------
  1551. __inline void AT91F_PIO_Enable(
  1552. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1553. unsigned int flag) // \arg pio to be enabled
  1554. {
  1555. pPio->PIO_PER = flag;
  1556. }
  1557. //*----------------------------------------------------------------------------
  1558. //* \fn AT91F_PIO_Disable
  1559. //* \brief Disable PIO
  1560. //*----------------------------------------------------------------------------
  1561. __inline void AT91F_PIO_Disable(
  1562. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1563. unsigned int flag) // \arg pio to be disabled
  1564. {
  1565. pPio->PIO_PDR = flag;
  1566. }
  1567. //*----------------------------------------------------------------------------
  1568. //* \fn AT91F_PIO_GetStatus
  1569. //* \brief Return PIO Status
  1570. //*----------------------------------------------------------------------------
  1571. __inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
  1572. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1573. {
  1574. return pPio->PIO_PSR;
  1575. }
  1576. //*----------------------------------------------------------------------------
  1577. //* \fn AT91F_PIO_IsSet
  1578. //* \brief Test if PIO is Set
  1579. //*----------------------------------------------------------------------------
  1580. __inline int AT91F_PIO_IsSet(
  1581. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1582. unsigned int flag) // \arg flag to be tested
  1583. {
  1584. return (AT91F_PIO_GetStatus(pPio) & flag);
  1585. }
  1586. //*----------------------------------------------------------------------------
  1587. //* \fn AT91F_PIO_OutputEnable
  1588. //* \brief Output Enable PIO
  1589. //*----------------------------------------------------------------------------
  1590. __inline void AT91F_PIO_OutputEnable(
  1591. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1592. unsigned int flag) // \arg pio output to be enabled
  1593. {
  1594. pPio->PIO_OER = flag;
  1595. }
  1596. //*----------------------------------------------------------------------------
  1597. //* \fn AT91F_PIO_OutputDisable
  1598. //* \brief Output Enable PIO
  1599. //*----------------------------------------------------------------------------
  1600. __inline void AT91F_PIO_OutputDisable(
  1601. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1602. unsigned int flag) // \arg pio output to be disabled
  1603. {
  1604. pPio->PIO_ODR = flag;
  1605. }
  1606. //*----------------------------------------------------------------------------
  1607. //* \fn AT91F_PIO_GetOutputStatus
  1608. //* \brief Return PIO Output Status
  1609. //*----------------------------------------------------------------------------
  1610. __inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
  1611. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1612. {
  1613. return pPio->PIO_OSR;
  1614. }
  1615. //*----------------------------------------------------------------------------
  1616. //* \fn AT91F_PIO_IsOuputSet
  1617. //* \brief Test if PIO Output is Set
  1618. //*----------------------------------------------------------------------------
  1619. __inline int AT91F_PIO_IsOutputSet(
  1620. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1621. unsigned int flag) // \arg flag to be tested
  1622. {
  1623. return (AT91F_PIO_GetOutputStatus(pPio) & flag);
  1624. }
  1625. //*----------------------------------------------------------------------------
  1626. //* \fn AT91F_PIO_InputFilterEnable
  1627. //* \brief Input Filter Enable PIO
  1628. //*----------------------------------------------------------------------------
  1629. __inline void AT91F_PIO_InputFilterEnable(
  1630. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1631. unsigned int flag) // \arg pio input filter to be enabled
  1632. {
  1633. pPio->PIO_IFER = flag;
  1634. }
  1635. //*----------------------------------------------------------------------------
  1636. //* \fn AT91F_PIO_InputFilterDisable
  1637. //* \brief Input Filter Disable PIO
  1638. //*----------------------------------------------------------------------------
  1639. __inline void AT91F_PIO_InputFilterDisable(
  1640. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1641. unsigned int flag) // \arg pio input filter to be disabled
  1642. {
  1643. pPio->PIO_IFDR = flag;
  1644. }
  1645. //*----------------------------------------------------------------------------
  1646. //* \fn AT91F_PIO_GetInputFilterStatus
  1647. //* \brief Return PIO Input Filter Status
  1648. //*----------------------------------------------------------------------------
  1649. __inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
  1650. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1651. {
  1652. return pPio->PIO_IFSR;
  1653. }
  1654. //*----------------------------------------------------------------------------
  1655. //* \fn AT91F_PIO_IsInputFilterSet
  1656. //* \brief Test if PIO Input filter is Set
  1657. //*----------------------------------------------------------------------------
  1658. __inline int AT91F_PIO_IsInputFilterSet(
  1659. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1660. unsigned int flag) // \arg flag to be tested
  1661. {
  1662. return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
  1663. }
  1664. //*----------------------------------------------------------------------------
  1665. //* \fn AT91F_PIO_GetOutputDataStatus
  1666. //* \brief Return PIO Output Data Status
  1667. //*----------------------------------------------------------------------------
  1668. __inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
  1669. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1670. {
  1671. return pPio->PIO_ODSR;
  1672. }
  1673. //*----------------------------------------------------------------------------
  1674. //* \fn AT91F_PIO_InterruptEnable
  1675. //* \brief Enable PIO Interrupt
  1676. //*----------------------------------------------------------------------------
  1677. __inline void AT91F_PIO_InterruptEnable(
  1678. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1679. unsigned int flag) // \arg pio interrupt to be enabled
  1680. {
  1681. pPio->PIO_IER = flag;
  1682. }
  1683. //*----------------------------------------------------------------------------
  1684. //* \fn AT91F_PIO_InterruptDisable
  1685. //* \brief Disable PIO Interrupt
  1686. //*----------------------------------------------------------------------------
  1687. __inline void AT91F_PIO_InterruptDisable(
  1688. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1689. unsigned int flag) // \arg pio interrupt to be disabled
  1690. {
  1691. pPio->PIO_IDR = flag;
  1692. }
  1693. //*----------------------------------------------------------------------------
  1694. //* \fn AT91F_PIO_GetInterruptMaskStatus
  1695. //* \brief Return PIO Interrupt Mask Status
  1696. //*----------------------------------------------------------------------------
  1697. __inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
  1698. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1699. {
  1700. return pPio->PIO_IMR;
  1701. }
  1702. //*----------------------------------------------------------------------------
  1703. //* \fn AT91F_PIO_GetInterruptStatus
  1704. //* \brief Return PIO Interrupt Status
  1705. //*----------------------------------------------------------------------------
  1706. __inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
  1707. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1708. {
  1709. return pPio->PIO_ISR;
  1710. }
  1711. //*----------------------------------------------------------------------------
  1712. //* \fn AT91F_PIO_IsInterruptMasked
  1713. //* \brief Test if PIO Interrupt is Masked
  1714. //*----------------------------------------------------------------------------
  1715. __inline int AT91F_PIO_IsInterruptMasked(
  1716. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1717. unsigned int flag) // \arg flag to be tested
  1718. {
  1719. return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
  1720. }
  1721. //*----------------------------------------------------------------------------
  1722. //* \fn AT91F_PIO_IsInterruptSet
  1723. //* \brief Test if PIO Interrupt is Set
  1724. //*----------------------------------------------------------------------------
  1725. __inline int AT91F_PIO_IsInterruptSet(
  1726. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1727. unsigned int flag) // \arg flag to be tested
  1728. {
  1729. return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
  1730. }
  1731. //*----------------------------------------------------------------------------
  1732. //* \fn AT91F_PIO_MultiDriverEnable
  1733. //* \brief Multi Driver Enable PIO
  1734. //*----------------------------------------------------------------------------
  1735. __inline void AT91F_PIO_MultiDriverEnable(
  1736. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1737. unsigned int flag) // \arg pio to be enabled
  1738. {
  1739. pPio->PIO_MDER = flag;
  1740. }
  1741. //*----------------------------------------------------------------------------
  1742. //* \fn AT91F_PIO_MultiDriverDisable
  1743. //* \brief Multi Driver Disable PIO
  1744. //*----------------------------------------------------------------------------
  1745. __inline void AT91F_PIO_MultiDriverDisable(
  1746. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1747. unsigned int flag) // \arg pio to be disabled
  1748. {
  1749. pPio->PIO_MDDR = flag;
  1750. }
  1751. //*----------------------------------------------------------------------------
  1752. //* \fn AT91F_PIO_GetMultiDriverStatus
  1753. //* \brief Return PIO Multi Driver Status
  1754. //*----------------------------------------------------------------------------
  1755. __inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
  1756. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1757. {
  1758. return pPio->PIO_MDSR;
  1759. }
  1760. //*----------------------------------------------------------------------------
  1761. //* \fn AT91F_PIO_IsMultiDriverSet
  1762. //* \brief Test if PIO MultiDriver is Set
  1763. //*----------------------------------------------------------------------------
  1764. __inline int AT91F_PIO_IsMultiDriverSet(
  1765. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1766. unsigned int flag) // \arg flag to be tested
  1767. {
  1768. return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
  1769. }
  1770. //*----------------------------------------------------------------------------
  1771. //* \fn AT91F_PIO_A_RegisterSelection
  1772. //* \brief PIO A Register Selection
  1773. //*----------------------------------------------------------------------------
  1774. __inline void AT91F_PIO_A_RegisterSelection(
  1775. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1776. unsigned int flag) // \arg pio A register selection
  1777. {
  1778. pPio->PIO_ASR = flag;
  1779. }
  1780. //*----------------------------------------------------------------------------
  1781. //* \fn AT91F_PIO_B_RegisterSelection
  1782. //* \brief PIO B Register Selection
  1783. //*----------------------------------------------------------------------------
  1784. __inline void AT91F_PIO_B_RegisterSelection(
  1785. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1786. unsigned int flag) // \arg pio B register selection
  1787. {
  1788. pPio->PIO_BSR = flag;
  1789. }
  1790. //*----------------------------------------------------------------------------
  1791. //* \fn AT91F_PIO_Get_AB_RegisterStatus
  1792. //* \brief Return PIO Interrupt Status
  1793. //*----------------------------------------------------------------------------
  1794. __inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
  1795. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1796. {
  1797. return pPio->PIO_ABSR;
  1798. }
  1799. //*----------------------------------------------------------------------------
  1800. //* \fn AT91F_PIO_IsAB_RegisterSet
  1801. //* \brief Test if PIO AB Register is Set
  1802. //*----------------------------------------------------------------------------
  1803. __inline int AT91F_PIO_IsAB_RegisterSet(
  1804. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1805. unsigned int flag) // \arg flag to be tested
  1806. {
  1807. return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
  1808. }
  1809. //*----------------------------------------------------------------------------
  1810. //* \fn AT91F_PIO_OutputWriteEnable
  1811. //* \brief Output Write Enable PIO
  1812. //*----------------------------------------------------------------------------
  1813. __inline void AT91F_PIO_OutputWriteEnable(
  1814. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1815. unsigned int flag) // \arg pio output write to be enabled
  1816. {
  1817. pPio->PIO_OWER = flag;
  1818. }
  1819. //*----------------------------------------------------------------------------
  1820. //* \fn AT91F_PIO_OutputWriteDisable
  1821. //* \brief Output Write Disable PIO
  1822. //*----------------------------------------------------------------------------
  1823. __inline void AT91F_PIO_OutputWriteDisable(
  1824. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1825. unsigned int flag) // \arg pio output write to be disabled
  1826. {
  1827. pPio->PIO_OWDR = flag;
  1828. }
  1829. //*----------------------------------------------------------------------------
  1830. //* \fn AT91F_PIO_GetOutputWriteStatus
  1831. //* \brief Return PIO Output Write Status
  1832. //*----------------------------------------------------------------------------
  1833. __inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
  1834. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1835. {
  1836. return pPio->PIO_OWSR;
  1837. }
  1838. //*----------------------------------------------------------------------------
  1839. //* \fn AT91F_PIO_IsOutputWriteSet
  1840. //* \brief Test if PIO OutputWrite is Set
  1841. //*----------------------------------------------------------------------------
  1842. __inline int AT91F_PIO_IsOutputWriteSet(
  1843. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1844. unsigned int flag) // \arg flag to be tested
  1845. {
  1846. return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
  1847. }
  1848. //*----------------------------------------------------------------------------
  1849. //* \fn AT91F_PIO_GetCfgPullup
  1850. //* \brief Return PIO Configuration Pullup
  1851. //*----------------------------------------------------------------------------
  1852. __inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
  1853. AT91PS_PIO pPio) // \arg pointer to a PIO controller
  1854. {
  1855. return pPio->PIO_PPUSR;
  1856. }
  1857. //*----------------------------------------------------------------------------
  1858. //* \fn AT91F_PIO_IsOutputDataStatusSet
  1859. //* \brief Test if PIO Output Data Status is Set
  1860. //*----------------------------------------------------------------------------
  1861. __inline int AT91F_PIO_IsOutputDataStatusSet(
  1862. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1863. unsigned int flag) // \arg flag to be tested
  1864. {
  1865. return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
  1866. }
  1867. //*----------------------------------------------------------------------------
  1868. //* \fn AT91F_PIO_IsCfgPullupStatusSet
  1869. //* \brief Test if PIO Configuration Pullup Status is Set
  1870. //*----------------------------------------------------------------------------
  1871. __inline int AT91F_PIO_IsCfgPullupStatusSet(
  1872. AT91PS_PIO pPio, // \arg pointer to a PIO controller
  1873. unsigned int flag) // \arg flag to be tested
  1874. {
  1875. return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
  1876. }
  1877. /* *****************************************************************************
  1878. SOFTWARE API FOR TWI
  1879. ***************************************************************************** */
  1880. //*----------------------------------------------------------------------------
  1881. //* \fn AT91F_TWI_EnableIt
  1882. //* \brief Enable TWI IT
  1883. //*----------------------------------------------------------------------------
  1884. __inline void AT91F_TWI_EnableIt (
  1885. AT91PS_TWI pTWI, // \arg pointer to a TWI controller
  1886. unsigned int flag) // \arg IT to be enabled
  1887. {
  1888. //* Write to the IER register
  1889. pTWI->TWI_IER = flag;
  1890. }
  1891. //*----------------------------------------------------------------------------
  1892. //* \fn AT91F_TWI_DisableIt
  1893. //* \brief Disable TWI IT
  1894. //*----------------------------------------------------------------------------
  1895. __inline void AT91F_TWI_DisableIt (
  1896. AT91PS_TWI pTWI, // \arg pointer to a TWI controller
  1897. unsigned int flag) // \arg IT to be disabled
  1898. {
  1899. //* Write to the IDR register
  1900. pTWI->TWI_IDR = flag;
  1901. }
  1902. //*----------------------------------------------------------------------------
  1903. //* \fn AT91F_TWI_Configure
  1904. //* \brief Configure TWI in master mode
  1905. //*----------------------------------------------------------------------------
  1906. __inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller
  1907. {
  1908. //* Disable interrupts
  1909. pTWI->TWI_IDR = (unsigned int) -1;
  1910. //* Reset peripheral
  1911. pTWI->TWI_CR = AT91C_TWI_SWRST;
  1912. //* Set Master mode
  1913. pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
  1914. }
  1915. //*----------------------------------------------------------------------------
  1916. //* \fn AT91F_TWI_GetInterruptMaskStatus
  1917. //* \brief Return TWI Interrupt Mask Status
  1918. //*----------------------------------------------------------------------------
  1919. __inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
  1920. AT91PS_TWI pTwi) // \arg pointer to a TWI controller
  1921. {
  1922. return pTwi->TWI_IMR;
  1923. }
  1924. //*----------------------------------------------------------------------------
  1925. //* \fn AT91F_TWI_IsInterruptMasked
  1926. //* \brief Test if TWI Interrupt is Masked
  1927. //*----------------------------------------------------------------------------
  1928. __inline int AT91F_TWI_IsInterruptMasked(
  1929. AT91PS_TWI pTwi, // \arg pointer to a TWI controller
  1930. unsigned int flag) // \arg flag to be tested
  1931. {
  1932. return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
  1933. }
  1934. /* *****************************************************************************
  1935. SOFTWARE API FOR USART
  1936. ***************************************************************************** */
  1937. //*----------------------------------------------------------------------------
  1938. //* \fn AT91F_US_Baudrate
  1939. //* \brief Calculate the baudrate
  1940. //* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
  1941. #define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
  1942. AT91C_US_NBSTOP_1_BIT + \
  1943. AT91C_US_PAR_NONE + \
  1944. AT91C_US_CHRL_8_BITS + \
  1945. AT91C_US_CLKS_CLOCK )
  1946. //* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
  1947. #define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
  1948. AT91C_US_NBSTOP_1_BIT + \
  1949. AT91C_US_PAR_NONE + \
  1950. AT91C_US_CHRL_8_BITS + \
  1951. AT91C_US_CLKS_EXT )
  1952. //* Standard Synchronous Mode : 8 bits , 1 stop , no parity
  1953. #define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
  1954. AT91C_US_USMODE_NORMAL + \
  1955. AT91C_US_NBSTOP_1_BIT + \
  1956. AT91C_US_PAR_NONE + \
  1957. AT91C_US_CHRL_8_BITS + \
  1958. AT91C_US_CLKS_CLOCK )
  1959. //* SCK used Label
  1960. #define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
  1961. //* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
  1962. #define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
  1963. AT91C_US_CLKS_CLOCK +\
  1964. AT91C_US_NBSTOP_1_BIT + \
  1965. AT91C_US_PAR_EVEN + \
  1966. AT91C_US_CHRL_8_BITS + \
  1967. AT91C_US_CKLO +\
  1968. AT91C_US_OVER)
  1969. //* Standard IRDA mode
  1970. #define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \
  1971. AT91C_US_NBSTOP_1_BIT + \
  1972. AT91C_US_PAR_NONE + \
  1973. AT91C_US_CHRL_8_BITS + \
  1974. AT91C_US_CLKS_CLOCK )
  1975. //*----------------------------------------------------------------------------
  1976. //* \fn AT91F_US_Baudrate
  1977. //* \brief Caluculate baud_value according to the main clock and the baud rate
  1978. //*----------------------------------------------------------------------------
  1979. __inline unsigned int AT91F_US_Baudrate (
  1980. const unsigned int main_clock, // \arg peripheral clock
  1981. const unsigned int baud_rate) // \arg UART baudrate
  1982. {
  1983. unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
  1984. if ((baud_value % 10) >= 5)
  1985. baud_value = (baud_value / 10) + 1;
  1986. else
  1987. baud_value /= 10;
  1988. return baud_value;
  1989. }
  1990. //*----------------------------------------------------------------------------
  1991. //* \fn AT91F_US_SetBaudrate
  1992. //* \brief Set the baudrate according to the CPU clock
  1993. //*----------------------------------------------------------------------------
  1994. __inline void AT91F_US_SetBaudrate (
  1995. AT91PS_USART pUSART, // \arg pointer to a USART controller
  1996. unsigned int mainClock, // \arg peripheral clock
  1997. unsigned int speed) // \arg UART baudrate
  1998. {
  1999. //* Define the baud rate divisor register
  2000. pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
  2001. }
  2002. //*----------------------------------------------------------------------------
  2003. //* \fn AT91F_US_SetTimeguard
  2004. //* \brief Set USART timeguard
  2005. //*----------------------------------------------------------------------------
  2006. __inline void AT91F_US_SetTimeguard (
  2007. AT91PS_USART pUSART, // \arg pointer to a USART controller
  2008. unsigned int timeguard) // \arg timeguard value
  2009. {
  2010. //* Write the Timeguard Register
  2011. pUSART->US_TTGR = timeguard ;
  2012. }
  2013. //*----------------------------------------------------------------------------
  2014. //* \fn AT91F_US_EnableIt
  2015. //* \brief Enable USART IT
  2016. //*----------------------------------------------------------------------------
  2017. __inline void AT91F_US_EnableIt (
  2018. AT91PS_USART pUSART, // \arg pointer to a USART controller
  2019. unsigned int flag) // \arg IT to be enabled
  2020. {
  2021. //* Write to the IER register
  2022. pUSART->US_IER = flag;
  2023. }
  2024. //*----------------------------------------------------------------------------
  2025. //* \fn AT91F_US_DisableIt
  2026. //* \brief Disable USART IT
  2027. //*----------------------------------------------------------------------------
  2028. __inline void AT91F_US_DisableIt (
  2029. AT91PS_USART pUSART, // \arg pointer to a USART controller
  2030. unsigned int flag) // \arg IT to be disabled
  2031. {
  2032. //* Write to the IER register
  2033. pUSART->US_IDR = flag;
  2034. }
  2035. //*----------------------------------------------------------------------------
  2036. //* \fn AT91F_US_Configure
  2037. //* \brief Configure USART
  2038. //*----------------------------------------------------------------------------
  2039. __inline void AT91F_US_Configure (
  2040. AT91PS_USART pUSART, // \arg pointer to a USART controller
  2041. unsigned int mainClock, // \arg peripheral clock
  2042. unsigned int mode , // \arg mode Register to be programmed
  2043. unsigned int baudRate , // \arg baudrate to be programmed
  2044. unsigned int timeguard ) // \arg timeguard to be programmed
  2045. {
  2046. //* Disable interrupts
  2047. pUSART->US_IDR = (unsigned int) -1;
  2048. //* Reset receiver and transmitter
  2049. pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
  2050. //* Define the baud rate divisor register
  2051. AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
  2052. //* Write the Timeguard Register
  2053. AT91F_US_SetTimeguard(pUSART, timeguard);
  2054. //* Clear Transmit and Receive Counters
  2055. AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
  2056. //* Define the USART mode
  2057. pUSART->US_MR = mode ;
  2058. }
  2059. //*----------------------------------------------------------------------------
  2060. //* \fn AT91F_US_EnableRx
  2061. //* \brief Enable receiving characters
  2062. //*----------------------------------------------------------------------------
  2063. __inline void AT91F_US_EnableRx (
  2064. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2065. {
  2066. //* Enable receiver
  2067. pUSART->US_CR = AT91C_US_RXEN;
  2068. }
  2069. //*----------------------------------------------------------------------------
  2070. //* \fn AT91F_US_EnableTx
  2071. //* \brief Enable sending characters
  2072. //*----------------------------------------------------------------------------
  2073. __inline void AT91F_US_EnableTx (
  2074. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2075. {
  2076. //* Enable transmitter
  2077. pUSART->US_CR = AT91C_US_TXEN;
  2078. }
  2079. //*----------------------------------------------------------------------------
  2080. //* \fn AT91F_US_ResetRx
  2081. //* \brief Reset Receiver and re-enable it
  2082. //*----------------------------------------------------------------------------
  2083. __inline void AT91F_US_ResetRx (
  2084. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2085. {
  2086. //* Reset receiver
  2087. pUSART->US_CR = AT91C_US_RSTRX;
  2088. //* Re-Enable receiver
  2089. pUSART->US_CR = AT91C_US_RXEN;
  2090. }
  2091. //*----------------------------------------------------------------------------
  2092. //* \fn AT91F_US_ResetTx
  2093. //* \brief Reset Transmitter and re-enable it
  2094. //*----------------------------------------------------------------------------
  2095. __inline void AT91F_US_ResetTx (
  2096. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2097. {
  2098. //* Reset transmitter
  2099. pUSART->US_CR = AT91C_US_RSTTX;
  2100. //* Enable transmitter
  2101. pUSART->US_CR = AT91C_US_TXEN;
  2102. }
  2103. //*----------------------------------------------------------------------------
  2104. //* \fn AT91F_US_DisableRx
  2105. //* \brief Disable Receiver
  2106. //*----------------------------------------------------------------------------
  2107. __inline void AT91F_US_DisableRx (
  2108. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2109. {
  2110. //* Disable receiver
  2111. pUSART->US_CR = AT91C_US_RXDIS;
  2112. }
  2113. //*----------------------------------------------------------------------------
  2114. //* \fn AT91F_US_DisableTx
  2115. //* \brief Disable Transmitter
  2116. //*----------------------------------------------------------------------------
  2117. __inline void AT91F_US_DisableTx (
  2118. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2119. {
  2120. //* Disable transmitter
  2121. pUSART->US_CR = AT91C_US_TXDIS;
  2122. }
  2123. //*----------------------------------------------------------------------------
  2124. //* \fn AT91F_US_Close
  2125. //* \brief Close USART: disable IT disable receiver and transmitter, close PDC
  2126. //*----------------------------------------------------------------------------
  2127. __inline void AT91F_US_Close (
  2128. AT91PS_USART pUSART) // \arg pointer to a USART controller
  2129. {
  2130. //* Reset the baud rate divisor register
  2131. pUSART->US_BRGR = 0 ;
  2132. //* Reset the USART mode
  2133. pUSART->US_MR = 0 ;
  2134. //* Reset the Timeguard Register
  2135. pUSART->US_TTGR = 0;
  2136. //* Disable all interrupts
  2137. pUSART->US_IDR = 0xFFFFFFFF ;
  2138. //* Abort the Peripheral Data Transfers
  2139. AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
  2140. //* Disable receiver and transmitter and stop any activity immediately
  2141. pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
  2142. }
  2143. //*----------------------------------------------------------------------------
  2144. //* \fn AT91F_US_TxReady
  2145. //* \brief Return 1 if a character can be written in US_THR
  2146. //*----------------------------------------------------------------------------
  2147. __inline unsigned int AT91F_US_TxReady (
  2148. AT91PS_USART pUSART ) // \arg pointer to a USART controller
  2149. {
  2150. return (pUSART->US_CSR & AT91C_US_TXRDY);
  2151. }
  2152. //*----------------------------------------------------------------------------
  2153. //* \fn AT91F_US_RxReady
  2154. //* \brief Return 1 if a character can be read in US_RHR
  2155. //*----------------------------------------------------------------------------
  2156. __inline unsigned int AT91F_US_RxReady (
  2157. AT91PS_USART pUSART ) // \arg pointer to a USART controller
  2158. {
  2159. return (pUSART->US_CSR & AT91C_US_RXRDY);
  2160. }
  2161. //*----------------------------------------------------------------------------
  2162. //* \fn AT91F_US_Error
  2163. //* \brief Return the error flag
  2164. //*----------------------------------------------------------------------------
  2165. __inline unsigned int AT91F_US_Error (
  2166. AT91PS_USART pUSART ) // \arg pointer to a USART controller
  2167. {
  2168. return (pUSART->US_CSR &
  2169. (AT91C_US_OVRE | // Overrun error
  2170. AT91C_US_FRAME | // Framing error
  2171. AT91C_US_PARE)); // Parity error
  2172. }
  2173. //*----------------------------------------------------------------------------
  2174. //* \fn AT91F_US_PutChar
  2175. //* \brief Send a character,does not check if ready to send
  2176. //*----------------------------------------------------------------------------
  2177. __inline void AT91F_US_PutChar (
  2178. AT91PS_USART pUSART,
  2179. int character )
  2180. {
  2181. pUSART->US_THR = (character & 0x1FF);
  2182. }
  2183. //*----------------------------------------------------------------------------
  2184. //* \fn AT91F_US_GetChar
  2185. //* \brief Receive a character,does not check if a character is available
  2186. //*----------------------------------------------------------------------------
  2187. __inline int AT91F_US_GetChar (
  2188. const AT91PS_USART pUSART)
  2189. {
  2190. return((pUSART->US_RHR) & 0x1FF);
  2191. }
  2192. //*----------------------------------------------------------------------------
  2193. //* \fn AT91F_US_SendFrame
  2194. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
  2195. //*----------------------------------------------------------------------------
  2196. __inline unsigned int AT91F_US_SendFrame(
  2197. AT91PS_USART pUSART,
  2198. char *pBuffer,
  2199. unsigned int szBuffer,
  2200. char *pNextBuffer,
  2201. unsigned int szNextBuffer )
  2202. {
  2203. return AT91F_PDC_SendFrame(
  2204. (AT91PS_PDC) &(pUSART->US_RPR),
  2205. pBuffer,
  2206. szBuffer,
  2207. pNextBuffer,
  2208. szNextBuffer);
  2209. }
  2210. //*----------------------------------------------------------------------------
  2211. //* \fn AT91F_US_ReceiveFrame
  2212. //* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
  2213. //*----------------------------------------------------------------------------
  2214. __inline unsigned int AT91F_US_ReceiveFrame (
  2215. AT91PS_USART pUSART,
  2216. char *pBuffer,
  2217. unsigned int szBuffer,
  2218. char *pNextBuffer,
  2219. unsigned int szNextBuffer )
  2220. {
  2221. return AT91F_PDC_ReceiveFrame(
  2222. (AT91PS_PDC) &(pUSART->US_RPR),
  2223. pBuffer,
  2224. szBuffer,
  2225. pNextBuffer,
  2226. szNextBuffer);
  2227. }
  2228. //*----------------------------------------------------------------------------
  2229. //* \fn AT91F_US_SetIrdaFilter
  2230. //* \brief Set the value of IrDa filter tregister
  2231. //*----------------------------------------------------------------------------
  2232. __inline void AT91F_US_SetIrdaFilter (
  2233. AT91PS_USART pUSART,
  2234. unsigned char value
  2235. )
  2236. {
  2237. pUSART->US_IF = value;
  2238. }
  2239. /* *****************************************************************************
  2240. SOFTWARE API FOR UDP
  2241. ***************************************************************************** */
  2242. //*----------------------------------------------------------------------------
  2243. //* \fn AT91F_UDP_EnableIt
  2244. //* \brief Enable UDP IT
  2245. //*----------------------------------------------------------------------------
  2246. __inline void AT91F_UDP_EnableIt (
  2247. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2248. unsigned int flag) // \arg IT to be enabled
  2249. {
  2250. //* Write to the IER register
  2251. pUDP->UDP_IER = flag;
  2252. }
  2253. //*----------------------------------------------------------------------------
  2254. //* \fn AT91F_UDP_DisableIt
  2255. //* \brief Disable UDP IT
  2256. //*----------------------------------------------------------------------------
  2257. __inline void AT91F_UDP_DisableIt (
  2258. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2259. unsigned int flag) // \arg IT to be disabled
  2260. {
  2261. //* Write to the IDR register
  2262. pUDP->UDP_IDR = flag;
  2263. }
  2264. //*----------------------------------------------------------------------------
  2265. //* \fn AT91F_UDP_SetAddress
  2266. //* \brief Set UDP functional address
  2267. //*----------------------------------------------------------------------------
  2268. __inline void AT91F_UDP_SetAddress (
  2269. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2270. unsigned char address) // \arg new UDP address
  2271. {
  2272. pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
  2273. }
  2274. //*----------------------------------------------------------------------------
  2275. //* \fn AT91F_UDP_EnableEp
  2276. //* \brief Enable Endpoint
  2277. //*----------------------------------------------------------------------------
  2278. __inline void AT91F_UDP_EnableEp (
  2279. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2280. unsigned int flag) // \arg endpoints to be enabled
  2281. {
  2282. pUDP->UDP_GLBSTATE |= flag;
  2283. }
  2284. //*----------------------------------------------------------------------------
  2285. //* \fn AT91F_UDP_DisableEp
  2286. //* \brief Enable Endpoint
  2287. //*----------------------------------------------------------------------------
  2288. __inline void AT91F_UDP_DisableEp (
  2289. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2290. unsigned int flag) // \arg endpoints to be enabled
  2291. {
  2292. pUDP->UDP_GLBSTATE &= ~(flag);
  2293. }
  2294. //*----------------------------------------------------------------------------
  2295. //* \fn AT91F_UDP_SetState
  2296. //* \brief Set UDP Device state
  2297. //*----------------------------------------------------------------------------
  2298. __inline void AT91F_UDP_SetState (
  2299. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2300. unsigned int flag) // \arg new UDP address
  2301. {
  2302. pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
  2303. pUDP->UDP_GLBSTATE |= flag;
  2304. }
  2305. //*----------------------------------------------------------------------------
  2306. //* \fn AT91F_UDP_GetState
  2307. //* \brief return UDP Device state
  2308. //*----------------------------------------------------------------------------
  2309. __inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
  2310. AT91PS_UDP pUDP) // \arg pointer to a UDP controller
  2311. {
  2312. return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
  2313. }
  2314. //*----------------------------------------------------------------------------
  2315. //* \fn AT91F_UDP_ResetEp
  2316. //* \brief Reset UDP endpoint
  2317. //*----------------------------------------------------------------------------
  2318. __inline void AT91F_UDP_ResetEp ( // \return the UDP device state
  2319. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2320. unsigned int flag) // \arg Endpoints to be reset
  2321. {
  2322. pUDP->UDP_RSTEP = flag;
  2323. }
  2324. //*----------------------------------------------------------------------------
  2325. //* \fn AT91F_UDP_EpStall
  2326. //* \brief Endpoint will STALL requests
  2327. //*----------------------------------------------------------------------------
  2328. __inline void AT91F_UDP_EpStall(
  2329. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2330. unsigned char endpoint) // \arg endpoint number
  2331. {
  2332. pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
  2333. }
  2334. //*----------------------------------------------------------------------------
  2335. //* \fn AT91F_UDP_EpWrite
  2336. //* \brief Write value in the DPR
  2337. //*----------------------------------------------------------------------------
  2338. __inline void AT91F_UDP_EpWrite(
  2339. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2340. unsigned char endpoint, // \arg endpoint number
  2341. unsigned char value) // \arg value to be written in the DPR
  2342. {
  2343. pUDP->UDP_FDR[endpoint] = value;
  2344. }
  2345. //*----------------------------------------------------------------------------
  2346. //* \fn AT91F_UDP_EpRead
  2347. //* \brief Return value from the DPR
  2348. //*----------------------------------------------------------------------------
  2349. __inline unsigned int AT91F_UDP_EpRead(
  2350. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2351. unsigned char endpoint) // \arg endpoint number
  2352. {
  2353. return pUDP->UDP_FDR[endpoint];
  2354. }
  2355. //*----------------------------------------------------------------------------
  2356. //* \fn AT91F_UDP_EpEndOfWr
  2357. //* \brief Notify the UDP that values in DPR are ready to be sent
  2358. //*----------------------------------------------------------------------------
  2359. __inline void AT91F_UDP_EpEndOfWr(
  2360. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2361. unsigned char endpoint) // \arg endpoint number
  2362. {
  2363. pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
  2364. }
  2365. //*----------------------------------------------------------------------------
  2366. //* \fn AT91F_UDP_EpClear
  2367. //* \brief Clear flag in the endpoint CSR register
  2368. //*----------------------------------------------------------------------------
  2369. __inline void AT91F_UDP_EpClear(
  2370. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2371. unsigned char endpoint, // \arg endpoint number
  2372. unsigned int flag) // \arg flag to be cleared
  2373. {
  2374. pUDP->UDP_CSR[endpoint] &= ~(flag);
  2375. }
  2376. //*----------------------------------------------------------------------------
  2377. //* \fn AT91F_UDP_EpSet
  2378. //* \brief Set flag in the endpoint CSR register
  2379. //*----------------------------------------------------------------------------
  2380. __inline void AT91F_UDP_EpSet(
  2381. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2382. unsigned char endpoint, // \arg endpoint number
  2383. unsigned int flag) // \arg flag to be cleared
  2384. {
  2385. pUDP->UDP_CSR[endpoint] |= flag;
  2386. }
  2387. //*----------------------------------------------------------------------------
  2388. //* \fn AT91F_UDP_EpStatus
  2389. //* \brief Return the endpoint CSR register
  2390. //*----------------------------------------------------------------------------
  2391. __inline unsigned int AT91F_UDP_EpStatus(
  2392. AT91PS_UDP pUDP, // \arg pointer to a UDP controller
  2393. unsigned char endpoint) // \arg endpoint number
  2394. {
  2395. return pUDP->UDP_CSR[endpoint];
  2396. }
  2397. //*----------------------------------------------------------------------------
  2398. //* \fn AT91F_UDP_GetInterruptMaskStatus
  2399. //* \brief Return UDP Interrupt Mask Status
  2400. //*----------------------------------------------------------------------------
  2401. __inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
  2402. AT91PS_UDP pUdp) // \arg pointer to a UDP controller
  2403. {
  2404. return pUdp->UDP_IMR;
  2405. }
  2406. //*----------------------------------------------------------------------------
  2407. //* \fn AT91F_UDP_IsInterruptMasked
  2408. //* \brief Test if UDP Interrupt is Masked
  2409. //*----------------------------------------------------------------------------
  2410. __inline int AT91F_UDP_IsInterruptMasked(
  2411. AT91PS_UDP pUdp, // \arg pointer to a UDP controller
  2412. unsigned int flag) // \arg flag to be tested
  2413. {
  2414. return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
  2415. }
  2416. /* *****************************************************************************
  2417. SOFTWARE API FOR AIC
  2418. ***************************************************************************** */
  2419. #define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
  2420. //*----------------------------------------------------------------------------
  2421. //* \fn AT91F_AIC_ConfigureIt
  2422. //* \brief Interrupt Handler Initialization
  2423. //*----------------------------------------------------------------------------
  2424. __inline unsigned int AT91F_AIC_ConfigureIt (
  2425. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2426. unsigned int irq_id, // \arg interrupt number to initialize
  2427. unsigned int priority, // \arg priority to give to the interrupt
  2428. unsigned int src_type, // \arg activation and sense of activation
  2429. void (*newHandler) (void) ) // \arg address of the interrupt handler
  2430. {
  2431. unsigned int oldHandler;
  2432. unsigned int mask ;
  2433. oldHandler = pAic->AIC_SVR[irq_id];
  2434. mask = 0x1 << irq_id ;
  2435. //* Disable the interrupt on the interrupt controller
  2436. pAic->AIC_IDCR = mask ;
  2437. //* Save the interrupt handler routine pointer and the interrupt priority
  2438. pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
  2439. //* Store the Source Mode Register
  2440. pAic->AIC_SMR[irq_id] = src_type | priority ;
  2441. //* Clear the interrupt on the interrupt controller
  2442. pAic->AIC_ICCR = mask ;
  2443. return oldHandler;
  2444. }
  2445. //*----------------------------------------------------------------------------
  2446. //* \fn AT91F_AIC_EnableIt
  2447. //* \brief Enable corresponding IT number
  2448. //*----------------------------------------------------------------------------
  2449. __inline void AT91F_AIC_EnableIt (
  2450. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2451. unsigned int irq_id ) // \arg interrupt number to initialize
  2452. {
  2453. //* Enable the interrupt on the interrupt controller
  2454. pAic->AIC_IECR = 0x1 << irq_id ;
  2455. }
  2456. //*----------------------------------------------------------------------------
  2457. //* \fn AT91F_AIC_DisableIt
  2458. //* \brief Disable corresponding IT number
  2459. //*----------------------------------------------------------------------------
  2460. __inline void AT91F_AIC_DisableIt (
  2461. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2462. unsigned int irq_id ) // \arg interrupt number to initialize
  2463. {
  2464. unsigned int mask = 0x1 << irq_id;
  2465. //* Disable the interrupt on the interrupt controller
  2466. pAic->AIC_IDCR = mask ;
  2467. //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  2468. pAic->AIC_ICCR = mask ;
  2469. }
  2470. //*----------------------------------------------------------------------------
  2471. //* \fn AT91F_AIC_ClearIt
  2472. //* \brief Clear corresponding IT number
  2473. //*----------------------------------------------------------------------------
  2474. __inline void AT91F_AIC_ClearIt (
  2475. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2476. unsigned int irq_id) // \arg interrupt number to initialize
  2477. {
  2478. //* Clear the interrupt on the Interrupt Controller ( if one is pending )
  2479. pAic->AIC_ICCR = (0x1 << irq_id);
  2480. }
  2481. //*----------------------------------------------------------------------------
  2482. //* \fn AT91F_AIC_AcknowledgeIt
  2483. //* \brief Acknowledge corresponding IT number
  2484. //*----------------------------------------------------------------------------
  2485. __inline void AT91F_AIC_AcknowledgeIt (
  2486. AT91PS_AIC pAic) // \arg pointer to the AIC registers
  2487. {
  2488. pAic->AIC_EOICR = pAic->AIC_EOICR;
  2489. }
  2490. //*----------------------------------------------------------------------------
  2491. //* \fn AT91F_AIC_SetExceptionVector
  2492. //* \brief Configure vector handler
  2493. //*----------------------------------------------------------------------------
  2494. __inline unsigned int AT91F_AIC_SetExceptionVector (
  2495. unsigned int *pVector, // \arg pointer to the AIC registers
  2496. void (*Handler) () ) // \arg Interrupt Handler
  2497. {
  2498. unsigned int oldVector = *pVector;
  2499. if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
  2500. *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
  2501. else
  2502. *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
  2503. return oldVector;
  2504. }
  2505. //*----------------------------------------------------------------------------
  2506. //* \fn AT91F_AIC_Trig
  2507. //* \brief Trig an IT
  2508. //*----------------------------------------------------------------------------
  2509. __inline void AT91F_AIC_Trig (
  2510. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2511. unsigned int irq_id) // \arg interrupt number
  2512. {
  2513. pAic->AIC_ISCR = (0x1 << irq_id) ;
  2514. }
  2515. //*----------------------------------------------------------------------------
  2516. //* \fn AT91F_AIC_IsActive
  2517. //* \brief Test if an IT is active
  2518. //*----------------------------------------------------------------------------
  2519. __inline unsigned int AT91F_AIC_IsActive (
  2520. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2521. unsigned int irq_id) // \arg Interrupt Number
  2522. {
  2523. return (pAic->AIC_ISR & (0x1 << irq_id));
  2524. }
  2525. //*----------------------------------------------------------------------------
  2526. //* \fn AT91F_AIC_IsPending
  2527. //* \brief Test if an IT is pending
  2528. //*----------------------------------------------------------------------------
  2529. __inline unsigned int AT91F_AIC_IsPending (
  2530. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2531. unsigned int irq_id) // \arg Interrupt Number
  2532. {
  2533. return (pAic->AIC_IPR & (0x1 << irq_id));
  2534. }
  2535. //*----------------------------------------------------------------------------
  2536. //* \fn AT91F_AIC_Open
  2537. //* \brief Set exception vectors and AIC registers to default values
  2538. //*----------------------------------------------------------------------------
  2539. __inline void AT91F_AIC_Open(
  2540. AT91PS_AIC pAic, // \arg pointer to the AIC registers
  2541. void (*IrqHandler) (), // \arg Default IRQ vector exception
  2542. void (*FiqHandler) (), // \arg Default FIQ vector exception
  2543. void (*DefaultHandler) (), // \arg Default Handler set in ISR
  2544. void (*SpuriousHandler) (), // \arg Default Spurious Handler
  2545. unsigned int protectMode) // \arg Debug Control Register
  2546. {
  2547. int i;
  2548. // Disable all interrupts and set IVR to the default handler
  2549. for (i = 0; i < 32; ++i) {
  2550. AT91F_AIC_DisableIt(pAic, i);
  2551. AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
  2552. }
  2553. // Set the IRQ exception vector
  2554. AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
  2555. // Set the Fast Interrupt exception vector
  2556. AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
  2557. pAic->AIC_SPU = (unsigned int) SpuriousHandler;
  2558. pAic->AIC_DCR = protectMode;
  2559. }
  2560. //*----------------------------------------------------------------------------
  2561. //* \fn AT91F_MC_CfgPMC
  2562. //* \brief Enable Peripheral clock in PMC for MC
  2563. //*----------------------------------------------------------------------------
  2564. __inline void AT91F_MC_CfgPMC (void)
  2565. {
  2566. AT91F_PMC_EnablePeriphClock(
  2567. AT91C_BASE_PMC, // PIO controller base address
  2568. ((unsigned int) 1 << AT91C_ID_SYS));
  2569. }
  2570. //*----------------------------------------------------------------------------
  2571. //* \fn AT91F_DBGU_CfgPMC
  2572. //* \brief Enable Peripheral clock in PMC for DBGU
  2573. //*----------------------------------------------------------------------------
  2574. __inline void AT91F_DBGU_CfgPMC (void)
  2575. {
  2576. AT91F_PMC_EnablePeriphClock(
  2577. AT91C_BASE_PMC, // PIO controller base address
  2578. ((unsigned int) 1 << AT91C_ID_SYS));
  2579. }
  2580. //*----------------------------------------------------------------------------
  2581. //* \fn AT91F_DBGU_CfgPIO
  2582. //* \brief Configure PIO controllers to drive DBGU signals
  2583. //*----------------------------------------------------------------------------
  2584. __inline void AT91F_DBGU_CfgPIO (void)
  2585. {
  2586. // Configure PIO controllers to periph mode
  2587. AT91F_PIO_CfgPeriph(
  2588. AT91C_BASE_PIOA, // PIO controller base address
  2589. ((unsigned int) AT91C_PA10_DTXD ) |
  2590. ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A
  2591. 0); // Peripheral B
  2592. }
  2593. //*----------------------------------------------------------------------------
  2594. //* \fn AT91F_PWMC_CH3_CfgPIO
  2595. //* \brief Configure PIO controllers to drive PWMC_CH3 signals
  2596. //*----------------------------------------------------------------------------
  2597. __inline void AT91F_PWMC_CH3_CfgPIO (void)
  2598. {
  2599. // Configure PIO controllers to periph mode
  2600. AT91F_PIO_CfgPeriph(
  2601. AT91C_BASE_PIOA, // PIO controller base address
  2602. 0, // Peripheral A
  2603. ((unsigned int) AT91C_PA14_PWM3 ) |
  2604. ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B
  2605. }
  2606. //*----------------------------------------------------------------------------
  2607. //* \fn AT91F_PWMC_CH2_CfgPIO
  2608. //* \brief Configure PIO controllers to drive PWMC_CH2 signals
  2609. //*----------------------------------------------------------------------------
  2610. __inline void AT91F_PWMC_CH2_CfgPIO (void)
  2611. {
  2612. // Configure PIO controllers to periph mode
  2613. AT91F_PIO_CfgPeriph(
  2614. AT91C_BASE_PIOA, // PIO controller base address
  2615. ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A
  2616. ((unsigned int) AT91C_PA25_PWM2 ) |
  2617. ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B
  2618. }
  2619. //*----------------------------------------------------------------------------
  2620. //* \fn AT91F_PWMC_CH1_CfgPIO
  2621. //* \brief Configure PIO controllers to drive PWMC_CH1 signals
  2622. //*----------------------------------------------------------------------------
  2623. __inline void AT91F_PWMC_CH1_CfgPIO (void)
  2624. {
  2625. // Configure PIO controllers to periph mode
  2626. AT91F_PIO_CfgPeriph(
  2627. AT91C_BASE_PIOA, // PIO controller base address
  2628. ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A
  2629. ((unsigned int) AT91C_PA24_PWM1 ) |
  2630. ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B
  2631. }
  2632. //*----------------------------------------------------------------------------
  2633. //* \fn AT91F_PWMC_CH0_CfgPIO
  2634. //* \brief Configure PIO controllers to drive PWMC_CH0 signals
  2635. //*----------------------------------------------------------------------------
  2636. __inline void AT91F_PWMC_CH0_CfgPIO (void)
  2637. {
  2638. // Configure PIO controllers to periph mode
  2639. AT91F_PIO_CfgPeriph(
  2640. AT91C_BASE_PIOA, // PIO controller base address
  2641. ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A
  2642. ((unsigned int) AT91C_PA23_PWM0 ) |
  2643. ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B
  2644. }
  2645. //*----------------------------------------------------------------------------
  2646. //* \fn AT91F_SSC_CfgPMC
  2647. //* \brief Enable Peripheral clock in PMC for SSC
  2648. //*----------------------------------------------------------------------------
  2649. __inline void AT91F_SSC_CfgPMC (void)
  2650. {
  2651. AT91F_PMC_EnablePeriphClock(
  2652. AT91C_BASE_PMC, // PIO controller base address
  2653. ((unsigned int) 1 << AT91C_ID_SSC));
  2654. }
  2655. //*----------------------------------------------------------------------------
  2656. //* \fn AT91F_SSC_CfgPIO
  2657. //* \brief Configure PIO controllers to drive SSC signals
  2658. //*----------------------------------------------------------------------------
  2659. __inline void AT91F_SSC_CfgPIO (void)
  2660. {
  2661. // Configure PIO controllers to periph mode
  2662. AT91F_PIO_CfgPeriph(
  2663. AT91C_BASE_PIOA, // PIO controller base address
  2664. ((unsigned int) AT91C_PA17_TD ) |
  2665. ((unsigned int) AT91C_PA15_TF ) |
  2666. ((unsigned int) AT91C_PA19_RK ) |
  2667. ((unsigned int) AT91C_PA18_RD ) |
  2668. ((unsigned int) AT91C_PA20_RF ) |
  2669. ((unsigned int) AT91C_PA16_TK ), // Peripheral A
  2670. 0); // Peripheral B
  2671. }
  2672. //*----------------------------------------------------------------------------
  2673. //* \fn AT91F_SPI_CfgPMC
  2674. //* \brief Enable Peripheral clock in PMC for SPI
  2675. //*----------------------------------------------------------------------------
  2676. __inline void AT91F_SPI_CfgPMC (void)
  2677. {
  2678. AT91F_PMC_EnablePeriphClock(
  2679. AT91C_BASE_PMC, // PIO controller base address
  2680. ((unsigned int) 1 << AT91C_ID_SPI));
  2681. }
  2682. //*----------------------------------------------------------------------------
  2683. //* \fn AT91F_SPI_CfgPIO
  2684. //* \brief Configure PIO controllers to drive SPI signals
  2685. //*----------------------------------------------------------------------------
  2686. __inline void AT91F_SPI_CfgPIO (void)
  2687. {
  2688. // Configure PIO controllers to periph mode
  2689. AT91F_PIO_CfgPeriph(
  2690. AT91C_BASE_PIOA, // PIO controller base address
  2691. ((unsigned int) AT91C_PA11_NPCS0 ) |
  2692. ((unsigned int) AT91C_PA13_MOSI ) |
  2693. ((unsigned int) AT91C_PA31_NPCS1 ) |
  2694. ((unsigned int) AT91C_PA12_MISO ) |
  2695. ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A
  2696. ((unsigned int) AT91C_PA9_NPCS1 ) |
  2697. ((unsigned int) AT91C_PA30_NPCS2 ) |
  2698. ((unsigned int) AT91C_PA10_NPCS2 ) |
  2699. ((unsigned int) AT91C_PA22_NPCS3 ) |
  2700. ((unsigned int) AT91C_PA3_NPCS3 ) |
  2701. ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B
  2702. }
  2703. //*----------------------------------------------------------------------------
  2704. //* \fn AT91F_PWMC_CfgPMC
  2705. //* \brief Enable Peripheral clock in PMC for PWMC
  2706. //*----------------------------------------------------------------------------
  2707. __inline void AT91F_PWMC_CfgPMC (void)
  2708. {
  2709. AT91F_PMC_EnablePeriphClock(
  2710. AT91C_BASE_PMC, // PIO controller base address
  2711. ((unsigned int) 1 << AT91C_ID_PWMC));
  2712. }
  2713. //*----------------------------------------------------------------------------
  2714. //* \fn AT91F_TC2_CfgPMC
  2715. //* \brief Enable Peripheral clock in PMC for TC2
  2716. //*----------------------------------------------------------------------------
  2717. __inline void AT91F_TC2_CfgPMC (void)
  2718. {
  2719. AT91F_PMC_EnablePeriphClock(
  2720. AT91C_BASE_PMC, // PIO controller base address
  2721. ((unsigned int) 1 << AT91C_ID_TC2));
  2722. }
  2723. //*----------------------------------------------------------------------------
  2724. //* \fn AT91F_TC2_CfgPIO
  2725. //* \brief Configure PIO controllers to drive TC2 signals
  2726. //*----------------------------------------------------------------------------
  2727. __inline void AT91F_TC2_CfgPIO (void)
  2728. {
  2729. // Configure PIO controllers to periph mode
  2730. AT91F_PIO_CfgPeriph(
  2731. AT91C_BASE_PIOA, // PIO controller base address
  2732. 0, // Peripheral A
  2733. ((unsigned int) AT91C_PA26_TIOA2 ) |
  2734. ((unsigned int) AT91C_PA27_TIOB2 ) |
  2735. ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B
  2736. }
  2737. //*----------------------------------------------------------------------------
  2738. //* \fn AT91F_TC1_CfgPMC
  2739. //* \brief Enable Peripheral clock in PMC for TC1
  2740. //*----------------------------------------------------------------------------
  2741. __inline void AT91F_TC1_CfgPMC (void)
  2742. {
  2743. AT91F_PMC_EnablePeriphClock(
  2744. AT91C_BASE_PMC, // PIO controller base address
  2745. ((unsigned int) 1 << AT91C_ID_TC1));
  2746. }
  2747. //*----------------------------------------------------------------------------
  2748. //* \fn AT91F_TC1_CfgPIO
  2749. //* \brief Configure PIO controllers to drive TC1 signals
  2750. //*----------------------------------------------------------------------------
  2751. __inline void AT91F_TC1_CfgPIO (void)
  2752. {
  2753. // Configure PIO controllers to periph mode
  2754. AT91F_PIO_CfgPeriph(
  2755. AT91C_BASE_PIOA, // PIO controller base address
  2756. 0, // Peripheral A
  2757. ((unsigned int) AT91C_PA15_TIOA1 ) |
  2758. ((unsigned int) AT91C_PA16_TIOB1 ) |
  2759. ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B
  2760. }
  2761. //*----------------------------------------------------------------------------
  2762. //* \fn AT91F_TC0_CfgPMC
  2763. //* \brief Enable Peripheral clock in PMC for TC0
  2764. //*----------------------------------------------------------------------------
  2765. __inline void AT91F_TC0_CfgPMC (void)
  2766. {
  2767. AT91F_PMC_EnablePeriphClock(
  2768. AT91C_BASE_PMC, // PIO controller base address
  2769. ((unsigned int) 1 << AT91C_ID_TC0));
  2770. }
  2771. //*----------------------------------------------------------------------------
  2772. //* \fn AT91F_TC0_CfgPIO
  2773. //* \brief Configure PIO controllers to drive TC0 signals
  2774. //*----------------------------------------------------------------------------
  2775. __inline void AT91F_TC0_CfgPIO (void)
  2776. {
  2777. // Configure PIO controllers to periph mode
  2778. AT91F_PIO_CfgPeriph(
  2779. AT91C_BASE_PIOA, // PIO controller base address
  2780. 0, // Peripheral A
  2781. ((unsigned int) AT91C_PA0_TIOA0 ) |
  2782. ((unsigned int) AT91C_PA1_TIOB0 ) |
  2783. ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B
  2784. }
  2785. //*----------------------------------------------------------------------------
  2786. //* \fn AT91F_PMC_CfgPMC
  2787. //* \brief Enable Peripheral clock in PMC for PMC
  2788. //*----------------------------------------------------------------------------
  2789. __inline void AT91F_PMC_CfgPMC (void)
  2790. {
  2791. AT91F_PMC_EnablePeriphClock(
  2792. AT91C_BASE_PMC, // PIO controller base address
  2793. ((unsigned int) 1 << AT91C_ID_SYS));
  2794. }
  2795. //*----------------------------------------------------------------------------
  2796. //* \fn AT91F_PMC_CfgPIO
  2797. //* \brief Configure PIO controllers to drive PMC signals
  2798. //*----------------------------------------------------------------------------
  2799. __inline void AT91F_PMC_CfgPIO (void)
  2800. {
  2801. // Configure PIO controllers to periph mode
  2802. AT91F_PIO_CfgPeriph(
  2803. AT91C_BASE_PIOA, // PIO controller base address
  2804. 0, // Peripheral A
  2805. ((unsigned int) AT91C_PA17_PCK1 ) |
  2806. ((unsigned int) AT91C_PA21_PCK1 ) |
  2807. ((unsigned int) AT91C_PA31_PCK2 ) |
  2808. ((unsigned int) AT91C_PA18_PCK2 ) |
  2809. ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B
  2810. }
  2811. //*----------------------------------------------------------------------------
  2812. //* \fn AT91F_ADC_CfgPMC
  2813. //* \brief Enable Peripheral clock in PMC for ADC
  2814. //*----------------------------------------------------------------------------
  2815. __inline void AT91F_ADC_CfgPMC (void)
  2816. {
  2817. AT91F_PMC_EnablePeriphClock(
  2818. AT91C_BASE_PMC, // PIO controller base address
  2819. ((unsigned int) 1 << AT91C_ID_ADC));
  2820. }
  2821. //*----------------------------------------------------------------------------
  2822. //* \fn AT91F_ADC_CfgPIO
  2823. //* \brief Configure PIO controllers to drive ADC signals
  2824. //*----------------------------------------------------------------------------
  2825. __inline void AT91F_ADC_CfgPIO (void)
  2826. {
  2827. // Configure PIO controllers to periph mode
  2828. AT91F_PIO_CfgPeriph(
  2829. AT91C_BASE_PIOA, // PIO controller base address
  2830. 0, // Peripheral A
  2831. ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B
  2832. }
  2833. //*----------------------------------------------------------------------------
  2834. //* \fn AT91F_PIOA_CfgPMC
  2835. //* \brief Enable Peripheral clock in PMC for PIOA
  2836. //*----------------------------------------------------------------------------
  2837. __inline void AT91F_PIOA_CfgPMC (void)
  2838. {
  2839. AT91F_PMC_EnablePeriphClock(
  2840. AT91C_BASE_PMC, // PIO controller base address
  2841. ((unsigned int) 1 << AT91C_ID_PIOA));
  2842. }
  2843. //*----------------------------------------------------------------------------
  2844. //* \fn AT91F_TWI_CfgPMC
  2845. //* \brief Enable Peripheral clock in PMC for TWI
  2846. //*----------------------------------------------------------------------------
  2847. __inline void AT91F_TWI_CfgPMC (void)
  2848. {
  2849. AT91F_PMC_EnablePeriphClock(
  2850. AT91C_BASE_PMC, // PIO controller base address
  2851. ((unsigned int) 1 << AT91C_ID_TWI));
  2852. }
  2853. //*----------------------------------------------------------------------------
  2854. //* \fn AT91F_TWI_CfgPIO
  2855. //* \brief Configure PIO controllers to drive TWI signals
  2856. //*----------------------------------------------------------------------------
  2857. __inline void AT91F_TWI_CfgPIO (void)
  2858. {
  2859. // Configure PIO controllers to periph mode
  2860. AT91F_PIO_CfgPeriph(
  2861. AT91C_BASE_PIOA, // PIO controller base address
  2862. ((unsigned int) AT91C_PA3_TWD ) |
  2863. ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A
  2864. 0); // Peripheral B
  2865. }
  2866. //*----------------------------------------------------------------------------
  2867. //* \fn AT91F_US1_CfgPMC
  2868. //* \brief Enable Peripheral clock in PMC for US1
  2869. //*----------------------------------------------------------------------------
  2870. __inline void AT91F_US1_CfgPMC (void)
  2871. {
  2872. AT91F_PMC_EnablePeriphClock(
  2873. AT91C_BASE_PMC, // PIO controller base address
  2874. ((unsigned int) 1 << AT91C_ID_US1));
  2875. }
  2876. //*----------------------------------------------------------------------------
  2877. //* \fn AT91F_US1_CfgPIO
  2878. //* \brief Configure PIO controllers to drive US1 signals
  2879. //*----------------------------------------------------------------------------
  2880. __inline void AT91F_US1_CfgPIO (void)
  2881. {
  2882. // Configure PIO controllers to periph mode
  2883. AT91F_PIO_CfgPeriph(
  2884. AT91C_BASE_PIOA, // PIO controller base address
  2885. ((unsigned int) AT91C_PA21_RXD1 ) |
  2886. ((unsigned int) AT91C_PA27_DTR1 ) |
  2887. ((unsigned int) AT91C_PA26_DCD1 ) |
  2888. ((unsigned int) AT91C_PA22_TXD1 ) |
  2889. ((unsigned int) AT91C_PA24_RTS1 ) |
  2890. ((unsigned int) AT91C_PA23_SCK1 ) |
  2891. ((unsigned int) AT91C_PA28_DSR1 ) |
  2892. ((unsigned int) AT91C_PA29_RI1 ) |
  2893. ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A
  2894. 0); // Peripheral B
  2895. }
  2896. //*----------------------------------------------------------------------------
  2897. //* \fn AT91F_US0_CfgPMC
  2898. //* \brief Enable Peripheral clock in PMC for US0
  2899. //*----------------------------------------------------------------------------
  2900. __inline void AT91F_US0_CfgPMC (void)
  2901. {
  2902. AT91F_PMC_EnablePeriphClock(
  2903. AT91C_BASE_PMC, // PIO controller base address
  2904. ((unsigned int) 1 << AT91C_ID_US0));
  2905. }
  2906. //*----------------------------------------------------------------------------
  2907. //* \fn AT91F_US0_CfgPIO
  2908. //* \brief Configure PIO controllers to drive US0 signals
  2909. //*----------------------------------------------------------------------------
  2910. __inline void AT91F_US0_CfgPIO (void)
  2911. {
  2912. // Configure PIO controllers to periph mode
  2913. AT91F_PIO_CfgPeriph(
  2914. AT91C_BASE_PIOA, // PIO controller base address
  2915. ((unsigned int) AT91C_PA5_RXD0 ) |
  2916. ((unsigned int) AT91C_PA6_TXD0 ) |
  2917. ((unsigned int) AT91C_PA7_RTS0 ) |
  2918. ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A
  2919. ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B
  2920. }
  2921. //*----------------------------------------------------------------------------
  2922. //* \fn AT91F_UDP_CfgPMC
  2923. //* \brief Enable Peripheral clock in PMC for UDP
  2924. //*----------------------------------------------------------------------------
  2925. __inline void AT91F_UDP_CfgPMC (void)
  2926. {
  2927. AT91F_PMC_EnablePeriphClock(
  2928. AT91C_BASE_PMC, // PIO controller base address
  2929. ((unsigned int) 1 << AT91C_ID_UDP));
  2930. }
  2931. //*----------------------------------------------------------------------------
  2932. //* \fn AT91F_AIC_CfgPMC
  2933. //* \brief Enable Peripheral clock in PMC for AIC
  2934. //*----------------------------------------------------------------------------
  2935. __inline void AT91F_AIC_CfgPMC (void)
  2936. {
  2937. AT91F_PMC_EnablePeriphClock(
  2938. AT91C_BASE_PMC, // PIO controller base address
  2939. ((unsigned int) 1 << AT91C_ID_IRQ0) |
  2940. ((unsigned int) 1 << AT91C_ID_FIQ) |
  2941. ((unsigned int) 1 << AT91C_ID_IRQ1));
  2942. }
  2943. //*----------------------------------------------------------------------------
  2944. //* \fn AT91F_AIC_CfgPIO
  2945. //* \brief Configure PIO controllers to drive AIC signals
  2946. //*----------------------------------------------------------------------------
  2947. __inline void AT91F_AIC_CfgPIO (void)
  2948. {
  2949. // Configure PIO controllers to periph mode
  2950. AT91F_PIO_CfgPeriph(
  2951. AT91C_BASE_PIOA, // PIO controller base address
  2952. ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A
  2953. ((unsigned int) AT91C_PA20_IRQ0 ) |
  2954. ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B
  2955. }
  2956. #endif // lib_AT91SAM7S64_H