port.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616
  1. /*
  2. * FreeRTOS Kernel V10.4.6
  3. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. *
  5. * SPDX-License-Identifier: MIT
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. * this software and associated documentation files (the "Software"), to deal in
  9. * the Software without restriction, including without limitation the rights to
  10. * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. * the Software, and to permit persons to whom the Software is furnished to do so,
  12. * subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in all
  15. * copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * https://www.FreeRTOS.org
  25. * https://github.com/FreeRTOS
  26. *
  27. */
  28. /*
  29. Changes between V1.2.4 and V1.2.5
  30. + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
  31. interrupt flag setting. Using the two bits defined within
  32. portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
  33. before the test was performed.
  34. Changes from V1.2.5
  35. + Set the interrupt vector address to 0x08. Previously it was at the
  36. incorrect address for compatibility mode of 0x18.
  37. Changes from V2.1.1
  38. + PCLATU and PCLATH are now saved as part of the context. This allows
  39. function pointers to be used within tasks. Thanks to Javier Espeche
  40. for the enhancement.
  41. Changes from V2.3.1
  42. + TABLAT is now saved as part of the task context.
  43. Changes from V3.2.0
  44. + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
  45. value and does not write to the register.
  46. */
  47. /* Scheduler include files. */
  48. #include "FreeRTOS.h"
  49. #include "task.h"
  50. /* MPLAB library include file. */
  51. #include "timers.h"
  52. /*-----------------------------------------------------------
  53. * Implementation of functions defined in portable.h for the PIC port.
  54. *----------------------------------------------------------*/
  55. /* Hardware setup for tick. */
  56. #define portTIMER_FOSC_SCALE ( ( uint32_t ) 4 )
  57. /* Initial interrupt enable state for newly created tasks. This value is
  58. copied into INTCON when a task switches in for the first time. */
  59. #define portINITAL_INTERRUPT_STATE 0xc0
  60. /* Just the bit within INTCON for the global interrupt flag. */
  61. #define portGLOBAL_INTERRUPT_FLAG 0x80
  62. /* Constant used for context switch macro when we require the interrupt
  63. enable state to be unchanged when the interrupted task is switched back in. */
  64. #define portINTERRUPTS_UNCHANGED 0x00
  65. /* Some memory areas get saved as part of the task context. These memory
  66. area's get used by the compiler for temporary storage, especially when
  67. performing mathematical operations, or when using 32bit data types. This
  68. constant defines the size of memory area which must be saved. */
  69. #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( uint8_t ) 0x13 )
  70. /* We require the address of the pxCurrentTCB variable, but don't want to know
  71. any details of its type. */
  72. typedef void TCB_t;
  73. extern volatile TCB_t * volatile pxCurrentTCB;
  74. /* IO port constants. */
  75. #define portBIT_SET ( ( uint8_t ) 1 )
  76. #define portBIT_CLEAR ( ( uint8_t ) 0 )
  77. /*
  78. * The serial port ISR's are defined in serial.c, but are called from portable
  79. * as they use the same vector as the tick ISR.
  80. */
  81. void vSerialTxISR( void );
  82. void vSerialRxISR( void );
  83. /*
  84. * Perform hardware setup to enable ticks.
  85. */
  86. static void prvSetupTimerInterrupt( void );
  87. /*
  88. * ISR to maintain the tick, and perform tick context switches if the
  89. * preemptive scheduler is being used.
  90. */
  91. static void prvTickISR( void );
  92. /*
  93. * ISR placed on the low priority vector. This calls the appropriate ISR for
  94. * the actual interrupt.
  95. */
  96. static void prvLowInterrupt( void );
  97. /*
  98. * Macro that pushes all the registers that make up the context of a task onto
  99. * the stack, then saves the new top of stack into the TCB.
  100. *
  101. * If this is called from an ISR then the interrupt enable bits must have been
  102. * set for the ISR to ever get called. Therefore we want to save the INTCON
  103. * register with the enable bits forced to be set - and ucForcedInterruptFlags
  104. * must contain these bit settings. This means the interrupts will again be
  105. * enabled when the interrupted task is switched back in.
  106. *
  107. * If this is called from a manual context switch (i.e. from a call to yield),
  108. * then we want to save the INTCON so it is restored with its current state,
  109. * and ucForcedInterruptFlags must be 0. This allows a yield from within
  110. * a critical section.
  111. *
  112. * The compiler uses some locations at the bottom of the memory for temporary
  113. * storage during math and other computations. This is especially true if
  114. * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
  115. * and MATH_DATA sections have to be stored in there entirety as part of a task
  116. * context. This macro stores from data address 0x00 to
  117. * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
  118. * applications but you should check the map file for your project to ensure
  119. * this is sufficient for your needs. It is not clear whether this size is
  120. * fixed for all compilations or has the potential to be program specific.
  121. */
  122. #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
  123. { \
  124. _asm \
  125. /* Save the status and WREG registers first, as these will get modified \
  126. by the operations below. */ \
  127. MOVFF WREG, PREINC1 \
  128. MOVFF STATUS, PREINC1 \
  129. /* Save the INTCON register with the appropriate bits forced if \
  130. necessary - as described above. */ \
  131. MOVFF INTCON, WREG \
  132. IORLW ucForcedInterruptFlags \
  133. MOVFF WREG, PREINC1 \
  134. _endasm \
  135. \
  136. portDISABLE_INTERRUPTS(); \
  137. \
  138. _asm \
  139. /* Store the necessary registers to the stack. */ \
  140. MOVFF BSR, PREINC1 \
  141. MOVFF FSR2L, PREINC1 \
  142. MOVFF FSR2H, PREINC1 \
  143. MOVFF FSR0L, PREINC1 \
  144. MOVFF FSR0H, PREINC1 \
  145. MOVFF TABLAT, PREINC1 \
  146. MOVFF TBLPTRU, PREINC1 \
  147. MOVFF TBLPTRH, PREINC1 \
  148. MOVFF TBLPTRL, PREINC1 \
  149. MOVFF PRODH, PREINC1 \
  150. MOVFF PRODL, PREINC1 \
  151. MOVFF PCLATU, PREINC1 \
  152. MOVFF PCLATH, PREINC1 \
  153. /* Store the .tempdata and MATH_DATA areas as described above. */ \
  154. CLRF FSR0L, 0 \
  155. CLRF FSR0H, 0 \
  156. MOVFF POSTINC0, PREINC1 \
  157. MOVFF POSTINC0, PREINC1 \
  158. MOVFF POSTINC0, PREINC1 \
  159. MOVFF POSTINC0, PREINC1 \
  160. MOVFF POSTINC0, PREINC1 \
  161. MOVFF POSTINC0, PREINC1 \
  162. MOVFF POSTINC0, PREINC1 \
  163. MOVFF POSTINC0, PREINC1 \
  164. MOVFF POSTINC0, PREINC1 \
  165. MOVFF POSTINC0, PREINC1 \
  166. MOVFF POSTINC0, PREINC1 \
  167. MOVFF POSTINC0, PREINC1 \
  168. MOVFF POSTINC0, PREINC1 \
  169. MOVFF POSTINC0, PREINC1 \
  170. MOVFF POSTINC0, PREINC1 \
  171. MOVFF POSTINC0, PREINC1 \
  172. MOVFF POSTINC0, PREINC1 \
  173. MOVFF POSTINC0, PREINC1 \
  174. MOVFF POSTINC0, PREINC1 \
  175. MOVFF INDF0, PREINC1 \
  176. MOVFF FSR0L, PREINC1 \
  177. MOVFF FSR0H, PREINC1 \
  178. /* Store the hardware stack pointer in a temp register before we \
  179. modify it. */ \
  180. MOVFF STKPTR, FSR0L \
  181. _endasm \
  182. \
  183. /* Store each address from the hardware stack. */ \
  184. while( STKPTR > ( uint8_t ) 0 ) \
  185. { \
  186. _asm \
  187. MOVFF TOSL, PREINC1 \
  188. MOVFF TOSH, PREINC1 \
  189. MOVFF TOSU, PREINC1 \
  190. POP \
  191. _endasm \
  192. } \
  193. \
  194. _asm \
  195. /* Store the number of addresses on the hardware stack (from the \
  196. temporary register). */ \
  197. MOVFF FSR0L, PREINC1 \
  198. MOVF PREINC1, 1, 0 \
  199. _endasm \
  200. \
  201. /* Save the new top of the software stack in the TCB. */ \
  202. _asm \
  203. MOVFF pxCurrentTCB, FSR0L \
  204. MOVFF pxCurrentTCB + 1, FSR0H \
  205. MOVFF FSR1L, POSTINC0 \
  206. MOVFF FSR1H, POSTINC0 \
  207. _endasm \
  208. }
  209. /*-----------------------------------------------------------*/
  210. /*
  211. * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
  212. * details.
  213. */
  214. #define portRESTORE_CONTEXT() \
  215. { \
  216. _asm \
  217. /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
  218. MOVFF pxCurrentTCB, FSR0L \
  219. MOVFF pxCurrentTCB + 1, FSR0H \
  220. \
  221. /* De-reference FSR0 to set the address it holds into FSR1. \
  222. (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
  223. MOVFF POSTINC0, FSR1L \
  224. MOVFF POSTINC0, FSR1H \
  225. \
  226. /* How many return addresses are there on the hardware stack? Discard \
  227. the first byte as we are pointing to the next free space. */ \
  228. MOVFF POSTDEC1, FSR0L \
  229. MOVFF POSTDEC1, FSR0L \
  230. _endasm \
  231. \
  232. /* Fill the hardware stack from our software stack. */ \
  233. STKPTR = 0; \
  234. \
  235. while( STKPTR < FSR0L ) \
  236. { \
  237. _asm \
  238. PUSH \
  239. MOVF POSTDEC1, 0, 0 \
  240. MOVWF TOSU, 0 \
  241. MOVF POSTDEC1, 0, 0 \
  242. MOVWF TOSH, 0 \
  243. MOVF POSTDEC1, 0, 0 \
  244. MOVWF TOSL, 0 \
  245. _endasm \
  246. } \
  247. \
  248. _asm \
  249. /* Restore the .tmpdata and MATH_DATA memory. */ \
  250. MOVFF POSTDEC1, FSR0H \
  251. MOVFF POSTDEC1, FSR0L \
  252. MOVFF POSTDEC1, POSTDEC0 \
  253. MOVFF POSTDEC1, POSTDEC0 \
  254. MOVFF POSTDEC1, POSTDEC0 \
  255. MOVFF POSTDEC1, POSTDEC0 \
  256. MOVFF POSTDEC1, POSTDEC0 \
  257. MOVFF POSTDEC1, POSTDEC0 \
  258. MOVFF POSTDEC1, POSTDEC0 \
  259. MOVFF POSTDEC1, POSTDEC0 \
  260. MOVFF POSTDEC1, POSTDEC0 \
  261. MOVFF POSTDEC1, POSTDEC0 \
  262. MOVFF POSTDEC1, POSTDEC0 \
  263. MOVFF POSTDEC1, POSTDEC0 \
  264. MOVFF POSTDEC1, POSTDEC0 \
  265. MOVFF POSTDEC1, POSTDEC0 \
  266. MOVFF POSTDEC1, POSTDEC0 \
  267. MOVFF POSTDEC1, POSTDEC0 \
  268. MOVFF POSTDEC1, POSTDEC0 \
  269. MOVFF POSTDEC1, POSTDEC0 \
  270. MOVFF POSTDEC1, POSTDEC0 \
  271. MOVFF POSTDEC1, INDF0 \
  272. /* Restore the other registers forming the tasks context. */ \
  273. MOVFF POSTDEC1, PCLATH \
  274. MOVFF POSTDEC1, PCLATU \
  275. MOVFF POSTDEC1, PRODL \
  276. MOVFF POSTDEC1, PRODH \
  277. MOVFF POSTDEC1, TBLPTRL \
  278. MOVFF POSTDEC1, TBLPTRH \
  279. MOVFF POSTDEC1, TBLPTRU \
  280. MOVFF POSTDEC1, TABLAT \
  281. MOVFF POSTDEC1, FSR0H \
  282. MOVFF POSTDEC1, FSR0L \
  283. MOVFF POSTDEC1, FSR2H \
  284. MOVFF POSTDEC1, FSR2L \
  285. MOVFF POSTDEC1, BSR \
  286. /* The next byte is the INTCON register. Read this into WREG as some \
  287. manipulation is required. */ \
  288. MOVFF POSTDEC1, WREG \
  289. _endasm \
  290. \
  291. /* From the INTCON register, only the interrupt enable bits form part \
  292. of the tasks context. It is perfectly legitimate for another task to \
  293. have modified any other bits. We therefore only restore the top two bits. \
  294. */ \
  295. if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
  296. { \
  297. _asm \
  298. MOVFF POSTDEC1, STATUS \
  299. MOVFF POSTDEC1, WREG \
  300. /* Return enabling interrupts. */ \
  301. RETFIE 0 \
  302. _endasm \
  303. } \
  304. else \
  305. { \
  306. _asm \
  307. MOVFF POSTDEC1, STATUS \
  308. MOVFF POSTDEC1, WREG \
  309. /* Return without effecting interrupts. The context may have \
  310. been saved from a critical region. */ \
  311. RETURN 0 \
  312. _endasm \
  313. } \
  314. }
  315. /*-----------------------------------------------------------*/
  316. /*
  317. * See header file for description.
  318. */
  319. StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
  320. {
  321. uint32_t ulAddress;
  322. uint8_t ucBlock;
  323. /* Place a few bytes of known values on the bottom of the stack.
  324. This is just useful for debugging. */
  325. *pxTopOfStack = 0x11;
  326. pxTopOfStack++;
  327. *pxTopOfStack = 0x22;
  328. pxTopOfStack++;
  329. *pxTopOfStack = 0x33;
  330. pxTopOfStack++;
  331. /* Simulate how the stack would look after a call to vPortYield() generated
  332. by the compiler.
  333. First store the function parameters. This is where the task will expect to
  334. find them when it starts running. */
  335. ulAddress = ( uint32_t ) pvParameters;
  336. *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
  337. pxTopOfStack++;
  338. ulAddress >>= 8;
  339. *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
  340. pxTopOfStack++;
  341. /* Next we just leave a space. When a context is saved the stack pointer
  342. is incremented before it is used so as not to corrupt whatever the stack
  343. pointer is actually pointing to. This is especially necessary during
  344. function epilogue code generated by the compiler. */
  345. *pxTopOfStack = 0x44;
  346. pxTopOfStack++;
  347. /* Next are all the registers that form part of the task context. */
  348. *pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
  349. pxTopOfStack++;
  350. *pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
  351. pxTopOfStack++;
  352. /* INTCON is saved with interrupts enabled. */
  353. *pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
  354. pxTopOfStack++;
  355. *pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
  356. pxTopOfStack++;
  357. *pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
  358. pxTopOfStack++;
  359. *pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
  360. pxTopOfStack++;
  361. *pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
  362. pxTopOfStack++;
  363. *pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
  364. pxTopOfStack++;
  365. *pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
  366. pxTopOfStack++;
  367. *pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
  368. pxTopOfStack++;
  369. *pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
  370. pxTopOfStack++;
  371. *pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
  372. pxTopOfStack++;
  373. *pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
  374. pxTopOfStack++;
  375. *pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
  376. pxTopOfStack++;
  377. *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
  378. pxTopOfStack++;
  379. *pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
  380. pxTopOfStack++;
  381. /* Next the .tmpdata and MATH_DATA sections. */
  382. for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
  383. {
  384. *pxTopOfStack = ( StackType_t ) ucBlock;
  385. *pxTopOfStack++;
  386. }
  387. /* Store the top of the global data section. */
  388. *pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
  389. pxTopOfStack++;
  390. *pxTopOfStack = ( StackType_t ) 0x00; /* High. */
  391. pxTopOfStack++;
  392. /* The only function return address so far is the address of the
  393. task. */
  394. ulAddress = ( uint32_t ) pxCode;
  395. /* TOS low. */
  396. *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
  397. pxTopOfStack++;
  398. ulAddress >>= 8;
  399. /* TOS high. */
  400. *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
  401. pxTopOfStack++;
  402. ulAddress >>= 8;
  403. /* TOS even higher. */
  404. *pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
  405. pxTopOfStack++;
  406. /* Store the number of return addresses on the hardware stack - so far only
  407. the address of the task entry point. */
  408. *pxTopOfStack = ( StackType_t ) 1;
  409. pxTopOfStack++;
  410. return pxTopOfStack;
  411. }
  412. /*-----------------------------------------------------------*/
  413. BaseType_t xPortStartScheduler( void )
  414. {
  415. /* Setup a timer for the tick ISR is using the preemptive scheduler. */
  416. prvSetupTimerInterrupt();
  417. /* Restore the context of the first task to run. */
  418. portRESTORE_CONTEXT();
  419. /* Should not get here. Use the function name to stop compiler warnings. */
  420. ( void ) prvLowInterrupt;
  421. ( void ) prvTickISR;
  422. return pdTRUE;
  423. }
  424. /*-----------------------------------------------------------*/
  425. void vPortEndScheduler( void )
  426. {
  427. /* It is unlikely that the scheduler for the PIC port will get stopped
  428. once running. If required disable the tick interrupt here, then return
  429. to xPortStartScheduler(). */
  430. }
  431. /*-----------------------------------------------------------*/
  432. /*
  433. * Manual context switch. This is similar to the tick context switch,
  434. * but does not increment the tick count. It must be identical to the
  435. * tick context switch in how it stores the stack of a task.
  436. */
  437. void vPortYield( void )
  438. {
  439. /* This can get called with interrupts either enabled or disabled. We
  440. will save the INTCON register with the interrupt enable bits unmodified. */
  441. portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
  442. /* Switch to the highest priority task that is ready to run. */
  443. vTaskSwitchContext();
  444. /* Start executing the task we have just switched to. */
  445. portRESTORE_CONTEXT();
  446. }
  447. /*-----------------------------------------------------------*/
  448. /*
  449. * Vector for ISR. Nothing here must alter any registers!
  450. */
  451. #pragma code high_vector=0x08
  452. static void prvLowInterrupt( void )
  453. {
  454. /* Was the interrupt the tick? */
  455. if( PIR1bits.CCP1IF )
  456. {
  457. _asm
  458. goto prvTickISR
  459. _endasm
  460. }
  461. /* Was the interrupt a byte being received? */
  462. if( PIR1bits.RCIF )
  463. {
  464. _asm
  465. goto vSerialRxISR
  466. _endasm
  467. }
  468. /* Was the interrupt the Tx register becoming empty? */
  469. if( PIR1bits.TXIF )
  470. {
  471. if( PIE1bits.TXIE )
  472. {
  473. _asm
  474. goto vSerialTxISR
  475. _endasm
  476. }
  477. }
  478. }
  479. #pragma code
  480. /*-----------------------------------------------------------*/
  481. /*
  482. * ISR for the tick.
  483. * This increments the tick count and, if using the preemptive scheduler,
  484. * performs a context switch. This must be identical to the manual
  485. * context switch in how it stores the context of a task.
  486. */
  487. static void prvTickISR( void )
  488. {
  489. /* Interrupts must have been enabled for the ISR to fire, so we have to
  490. save the context with interrupts enabled. */
  491. portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
  492. PIR1bits.CCP1IF = 0;
  493. /* Maintain the tick count. */
  494. if( xTaskIncrementTick() != pdFALSE )
  495. {
  496. /* Switch to the highest priority task that is ready to run. */
  497. vTaskSwitchContext();
  498. }
  499. portRESTORE_CONTEXT();
  500. }
  501. /*-----------------------------------------------------------*/
  502. /*
  503. * Setup a timer for a regular tick.
  504. */
  505. static void prvSetupTimerInterrupt( void )
  506. {
  507. const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
  508. uint32_t ulCompareValue;
  509. uint8_t ucByte;
  510. /* Interrupts are disabled when this function is called.
  511. Setup CCP1 to provide the tick interrupt using a compare match on timer
  512. 1.
  513. Clear the time count then setup timer. */
  514. TMR1H = ( uint8_t ) 0x00;
  515. TMR1L = ( uint8_t ) 0x00;
  516. /* Set the compare match value. */
  517. ulCompareValue = ulConstCompareValue;
  518. CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
  519. ulCompareValue >>= ( uint32_t ) 8;
  520. CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
  521. CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
  522. CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
  523. CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
  524. CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
  525. PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
  526. /* We are only going to use the global interrupt bit, so set the peripheral
  527. bit to true. */
  528. INTCONbits.GIEL = portBIT_SET;
  529. /* Provided library function for setting up the timer that will produce the
  530. tick. */
  531. OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
  532. }