4G04_MCU/driver/hal_can.c

#include "hal_can.h"




#define MCAN_RX_INT_SEL                 (MCAN_INT_RX_FIFO0_NEW_MSG|MCAN_INT_RX_FIFO0_FULL |MCAN_INT_RX_FIFO1_NEW_MSG |MCAN_INT_RX_FIFO1_FULL |MCAN_INT_RX_BUF_NEW_MSG)                                                                                                                                                                
#define MCAN_TX_INT_SEL                 (MCAN_INT_TX_CPLT |MCAN_INT_TX_EVT_FIFO_NEW_DATA |MCAN_INT_BUS_OFF)
                                                                                 
#define MCAN_INT0_SEL                   MCAN_RX_INT_SEL
#define MCAN_INT1_SEL                   MCAN_TX_INT_SEL

/* Message RAM */
/* Each standard filter element size is 4 bytes */
#define MCAN_STD_FILTER_NUM             (1U)
/* Each extended filter element size is 8 bytes */
#define MCAN_EXT_FILTER_NUM             (1U)
/* Each Rx FIFO0 element size is 8+8 bytes */
#define MCAN_RX_FIFO0_NUM               (10U)
#define MCAN_RX_FIFO0_WATERMARK         (8U)
#define MCAN_RX_FIFO0_DATA_FIELD_SIZE   MCAN_DATA_SIZE_8BYTE
/* Each Rx FIFO1 element size is 8+8 bytes */
#define MCAN_RX_FIFO1_NUM               (10U)
#define MCAN_RX_FIFO1_WATERMARK         (7U)
#define MCAN_RX_FIFO1_DATA_FIELD_SIZE   MCAN_DATA_SIZE_8BYTE
/* Each Rx buffer element size is 8+8 bytes */
#define MCAN_RX_BUF_NUM                 (6U)
#define MCAN_RX_BUF_DATA_FIELD_SIZE     MCAN_DATA_SIZE_8BYTE
/* Each Tx buffer element size is 8+8 bytes */
#define MCAN_TX_BUF_NUM                 (12U)
#define MCAN_TX_FIFO_NUM                (6U)
#define MCAN_TX_BUF_DATA_FIELD_SIZE     MCAN_DATA_SIZE_8BYTE
#define MCAN_TX_NOTIFICATION_BUF        ((1UL << (MCAN_TX_BUF_NUM + MCAN_TX_FIFO_NUM)) - 1U)
/* Each extended filter element size is 8 bytes */
#define MCAN_TX_EVT_NUM                 (12U)

/* Filter */
#define MCAN_CFG_IGNOR                  (0U)
/* Accept standard frames with ID from 0x110 to 0x11F and store to Rx FIFO0 */
#define MCAN_STD_FILTER0                {.u32IdType = MCAN_STD_ID, .u32FilterIndex = 0U, .u32FilterType = MCAN_FILTER_RANGE, \
                                         .u32FilterConfig = MCAN_FILTER_TO_RX_FIFO0, .u32FilterId1 = 0x00UL, \
                                         .u32FilterId2 = 0x7FFUL,}
///* Accept standard frames with ID 0x130~0x132 and store to dedicated Rx buffer 0~2 */
//#define MCAN_STD_FILTER1                {.u32IdType = MCAN_STD_ID, .u32FilterIndex = 1U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x130UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF0}
//#define MCAN_STD_FILTER2                {.u32IdType = MCAN_STD_ID, .u32FilterIndex = 2U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x131UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF1}
//#define MCAN_STD_FILTER3                {.u32IdType = MCAN_STD_ID, .u32FilterIndex = 3U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x132UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF2}

/* Accept extended frames with ID from 0x12345110 to 0x1234511F and store to Rx FIFO1 */
#define MCAN_EXT_FILTER0                {.u32IdType = MCAN_EXT_ID, .u32FilterIndex = 0U, .u32FilterType = MCAN_FILTER_RANGE, \
                                         .u32FilterConfig = MCAN_FILTER_TO_RX_FIFO1, .u32FilterId1 = 0x0UL, \
                                         .u32FilterId2 = 0x1FFFFFFFUL,}
///* Accept extended frames with ID 0x12345130~0x12345132 and store to dedicated Rx buffer 3~5 */
//#define MCAN_EXT_FILTER1                {.u32IdType = MCAN_EXT_ID, .u32FilterIndex = 1U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x12345130UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF3}
//#define MCAN_EXT_FILTER2                {.u32IdType = MCAN_EXT_ID, .u32FilterIndex = 2U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x12345131UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF4}
//#define MCAN_EXT_FILTER3                {.u32IdType = MCAN_EXT_ID, .u32FilterIndex = 3U, .u32FilterType = MCAN_CFG_IGNOR, \
//                                         .u32FilterConfig = MCAN_FILTER_TO_RX_BUF, .u32FilterId1 = 0x12345132UL, \
//                                         .u32FilterId2 = MCAN_CFG_IGNOR, .u32RxBufferIndex = MCAN_RX_BUF5}

 



QueueHandle_t can1_recieve1_data_queue;
QueueHandle_t can1_recieve2_data_queue;																					 
QueueHandle_t can2_recieve1_data_queue;
 																	 
 																	 
/***************************************CAN1****************************************************/										 
void bsp_can1_init(void)
{
	  GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_01, GPIO_FUNC_56);//CAN1 TX  PB01
    GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_00, GPIO_FUNC_57);//CAN1 RX  PB00
  
	  /* SET STB pin high before output */   
	  stc_gpio_init_t stcGpioInit;
    GPIO_StructInit(&stcGpioInit);
    stcGpioInit.u16PinState = PIN_STAT_SET;
    stcGpioInit.u16PinDir = PIN_DIR_OUT;
    GPIO_Init(GPIO_PORT_B, GPIO_PIN_02, &stcGpioInit);
    GPIO_ResetPins(GPIO_PORT_B,GPIO_PIN_02);
  
		
    stc_mcan_init_t stcMcanInit;
    stc_mcan_filter_t stcStdFilterList[MCAN_STD_FILTER_NUM] = {
        MCAN_STD_FILTER0/*, MCAN_STD_FILTER1, MCAN_STD_FILTER2, MCAN_STD_FILTER3*/
    };
    stc_mcan_filter_t stcExtFilterList[MCAN_EXT_FILTER_NUM] = {
        MCAN_EXT_FILTER0/*, MCAN_EXT_FILTER1, MCAN_EXT_FILTER2, MCAN_EXT_FILTER3*/
    };

 
		CLK_SetCANClockSrc(CLK_MCAN1, CLK_MCANCLK_SYSCLK_DIV5);//5分频,200/5=40MHZ给到CAN,
    MCAN_StructInit(&stcMcanInit);
    stcMcanInit.u32Mode = MCAN_MD_NORMAL;
    stcMcanInit.u32FrameFormat = MCAN_FRAME_CLASSIC;
    /* Classic CAN. Baudrate 1Mbps, sample point 80% */ //40MHZ
    stcMcanInit.stcCanClassic.u32Prescaler     = 8U; //波特率改这里
    stcMcanInit.stcCanClassic.u32TimeSeg1      = 16U;
    stcMcanInit.stcCanClassic.u32TimeSeg2      = 4U;
    stcMcanInit.stcCanClassic.u32SyncJumpWidth = 4U;
    /* Message RAM */
    stcMcanInit.stcMsgRam.u32AddrOffset        = 0U;
    stcMcanInit.stcMsgRam.u32StdFilterNum      = MCAN_STD_FILTER_NUM;
    stcMcanInit.stcMsgRam.u32ExtFilterNum      = MCAN_EXT_FILTER_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo0Num        = MCAN_RX_FIFO0_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo0DataSize   = MCAN_RX_FIFO0_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32RxFifo1Num        = MCAN_RX_FIFO1_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo1DataSize   = MCAN_RX_FIFO1_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32RxBufferNum       = MCAN_RX_BUF_NUM;
    stcMcanInit.stcMsgRam.u32RxBufferDataSize  = MCAN_RX_BUF_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32TxBufferNum       = MCAN_TX_BUF_NUM;
    stcMcanInit.stcMsgRam.u32TxFifoQueueNum    = MCAN_TX_FIFO_NUM;
    stcMcanInit.stcMsgRam.u32TxFifoQueueMode   = MCAN_TX_FIFO_MD;
    stcMcanInit.stcMsgRam.u32TxDataSize        = MCAN_TX_BUF_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32TxEventNum        = MCAN_TX_EVT_NUM;
    /* Acceptance filter */
    stcMcanInit.stcFilter.pstcStdFilterList     = stcStdFilterList;
    stcMcanInit.stcFilter.pstcExtFilterList     = stcExtFilterList;
    stcMcanInit.stcFilter.u32StdFilterConfigNum = stcMcanInit.stcMsgRam.u32StdFilterNum;
    stcMcanInit.stcFilter.u32ExtFilterConfigNum = stcMcanInit.stcMsgRam.u32ExtFilterNum;

    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1, DISABLE);
    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN1, ENABLE);
    MCAN_Init(CM_MCAN1, &stcMcanInit);

    /* Watermark if needed */
    MCAN_SetFifoWatermark(CM_MCAN1, MCAN_WATERMARK_RX_FIFO0, MCAN_RX_FIFO0_WATERMARK);
    MCAN_SetFifoWatermark(CM_MCAN1, MCAN_WATERMARK_RX_FIFO1, MCAN_RX_FIFO1_WATERMARK);

    /* Configure Rx FIFO0 operation mode if needed.
       If new message received when Rx FIFO0 is full, the new message
       will not be stored and Message Lost Interrupt will be generated. */
    MCAN_RxFifoOperationModeConfig(CM_MCAN1, MCAN_RX_FIFO0, MCAN_RX_FIFO_BLOCKING);
    /* Configure Rx FIFO1 operation mode if needed.
       If new message received when Rx FIFO1 is full, the new received message
       will overwrite the oldest received message and RF1N Interrupt generated. */
    MCAN_RxFifoOperationModeConfig(CM_MCAN1, MCAN_RX_FIFO1, MCAN_RX_FIFO_BLOCKING);

    /* Configures timestamp if needed */
    MCAN_TimestampCounterConfig(CM_MCAN1, 1U);
    MCAN_TimestampCounterCmd(CM_MCAN1, ENABLE);

    /* The Tx buffer can cause transmission completed completed interrupt
       only when its own transmission completed interrupt is enabled. */
    MCAN_TxBufferNotificationCmd(CM_MCAN1, MCAN_TX_NOTIFICATION_BUF, MCAN_INT_TX_CPLT, ENABLE);

    MCAN_IntCmd(CM_MCAN1, MCAN_INT0_SEL, MCAN_INT_LINE0, ENABLE);
			 
		NVIC_ClearPendingIRQ(MCAN1_INT0_IRQn);
    NVIC_SetPriority(MCAN1_INT0_IRQn, DDL_IRQ_PRIO_06);
    NVIC_EnableIRQ(MCAN1_INT0_IRQn); 	
		
		MCAN_Start(CM_MCAN1);
}


void MCAN1_INT0_Handler(void)
{
    uint32_t u32RxBuffer;
    uint32_t u32TxBufferIndex;
    uint32_t u32TxBuffer = 0U;
    stc_mcan_rx_msg_t stcRxMsg;
    stc_mcan_tx_msg_t stcTxMsg;
    stc_mcan_rx_msg_t stcRxMsgRxFifo1[MCAN_RX_FIFO1_NUM];
	
		static uint32_t pxHigherPriorityTaskWoken = pdFALSE;

    /* Rx FIFO0 related interrupts */
    if (MCAN_GetStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO0_NEW_MSG) == SET) {
        MCAN_ClearStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO0_NEW_MSG);
        /* Messages stored in Rx FIFO0 can be read here */
        printf("Rx FIFO_0 new message->\r\n");
        if (MCAN_GetRxMsg(CM_MCAN1, MCAN_RX_FIFO0, &stcRxMsg) == LL_OK) {					
					//printf("stcRxMsg.IDE=%d,stcRxMsg.ID=%x\r\n",stcRxMsg.IDE,stcRxMsg.ID);
					for(int i =0;i <8;i++)
					{
					  printf("%x ",stcRxMsg.au8Data[i]);
					}
					
					hc32_can_rx_msg_t hc32_can_rx_msg;
					hc32_can_rx_msg.ide =stcRxMsg.IDE;
					hc32_can_rx_msg.id = stcRxMsg.ID;
					hc32_can_rx_msg.len = 8;//stcRxMsg.DLC;//直接赋值
					memcpy(hc32_can_rx_msg.data,stcRxMsg.au8Data,8);
					
					if(stcRxMsg.ID==MSG_RECEIVE_ID_STD)				
						xQueueSendFromISR(can1_recieve1_data_queue,&stcRxMsg,(BaseType_t*)&pxHigherPriorityTaskWoken);
          else
						xQueueOverwriteFromISR(can1_recieve2_data_queue,&hc32_can_rx_msg,(BaseType_t*)&pxHigherPriorityTaskWoken);	
					
					portEND_SWITCHING_ISR(pxHigherPriorityTaskWoken);
					
        }  
    }
    if (MCAN_GetStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO0_FULL) == SET) 
		{
        MCAN_ClearStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO0_FULL);
    }


    /* Rx FIFO1 related interrupts */
    if (MCAN_GetStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO1_NEW_MSG) == SET) 
		{
        MCAN_ClearStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO1_NEW_MSG);
			  printf("Rx FIFO_1 new message->\r\n");
        if (MCAN_GetRxMsg(CM_MCAN1, MCAN_RX_FIFO1, &stcRxMsg) == LL_OK) {
					//printf("stcRxMsg.IDE=%d,stcRxMsg.ID=%x\r\n",stcRxMsg.IDE,stcRxMsg.ID);
					for(int i =0;i <8;i++)
					{
					  printf("%x ",stcRxMsg.au8Data[i]);
					}
					hc32_can_rx_msg_t hc32_can_rx_msg;
					hc32_can_rx_msg.ide =stcRxMsg.IDE;
					hc32_can_rx_msg.id = stcRxMsg.ID;
					hc32_can_rx_msg.len = 8;//stcRxMsg.DLC;//直接赋值
					memcpy(hc32_can_rx_msg.data,stcRxMsg.au8Data,8);
					if(stcRxMsg.ID==MSG_RECEIVE_ID_STD)				
						xQueueOverwriteFromISR(can1_recieve1_data_queue,&stcRxMsg,(BaseType_t*)&pxHigherPriorityTaskWoken);
          else
						xQueueOverwriteFromISR(can1_recieve2_data_queue,&hc32_can_rx_msg,(BaseType_t*)&pxHigherPriorityTaskWoken);						
                               
					portEND_SWITCHING_ISR(pxHigherPriorityTaskWoken);
					
        } 
    }

    if (MCAN_GetStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO1_FULL) == SET) {
        MCAN_ClearStatus(CM_MCAN1, MCAN_FLAG_RX_FIFO1_FULL);
        /* All dedicated Tx buffer are filled. Add transmission requests. */
        MCAN_EnableTxBufferRequest(CM_MCAN1, u32TxBuffer);
    }
	
    /* Dedicated Rx buffer related interrupts */
    if (MCAN_GetStatus(CM_MCAN1, MCAN_FLAG_RX_BUF_NEW_MSG) == SET) {
        MCAN_ClearStatus(CM_MCAN1, MCAN_FLAG_RX_BUF_NEW_MSG);
    }
}




///***************************************CAN2****************************************************/								 
void bsp_can2_init(void)
{
//	  GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_00, GPIO_FUNC_56);//CAN1 TX  PB00
//    GPIO_SetFunc(GPIO_PORT_B, GPIO_PIN_01, GPIO_FUNC_57);//CAN1 RX  PB01
/*测试脚*/
	  GPIO_SetFunc(GPIO_PORT_C, GPIO_PIN_12, GPIO_FUNC_56);//CAN1 TX  PC12 
    GPIO_SetFunc(GPIO_PORT_D, GPIO_PIN_00, GPIO_FUNC_57);//CAN1 RX  PD00
 
	  /* SET STB pin high before output */   
	  stc_gpio_init_t stcGpioInit;
    GPIO_StructInit(&stcGpioInit);
    stcGpioInit.u16PinState = PIN_STAT_RST;
    stcGpioInit.u16PinDir = PIN_DIR_OUT;
    GPIO_Init(GPIO_PORT_B, GPIO_PIN_02, &stcGpioInit);
    GPIO_ResetPins(GPIO_PORT_B,GPIO_PIN_02);
  
		
    stc_mcan_init_t stcMcanInit;
    stc_mcan_filter_t stcStdFilterList[MCAN_STD_FILTER_NUM] = {
        MCAN_STD_FILTER0/*, MCAN_STD_FILTER1, MCAN_STD_FILTER2, MCAN_STD_FILTER3*/
    };
    stc_mcan_filter_t stcExtFilterList[MCAN_EXT_FILTER_NUM] = {
        MCAN_EXT_FILTER0/*, MCAN_EXT_FILTER1, MCAN_EXT_FILTER2, MCAN_EXT_FILTER3*/
    };

 
		CLK_SetCANClockSrc(CLK_MCAN2, CLK_MCANCLK_SYSCLK_DIV5);//5分频,200/5=40MHZ给到CAN,
    MCAN_StructInit(&stcMcanInit);
    stcMcanInit.u32Mode = MCAN_MD_NORMAL;
    stcMcanInit.u32FrameFormat = MCAN_FRAME_CLASSIC;
    /* Classic CAN. Baudrate 1Mbps, sample point 80% */ //40MHZ
    stcMcanInit.stcCanClassic.u32Prescaler     = 8U; //波特率改这里
    stcMcanInit.stcCanClassic.u32TimeSeg1      = 16U;
    stcMcanInit.stcCanClassic.u32TimeSeg2      = 4U;
    stcMcanInit.stcCanClassic.u32SyncJumpWidth = 4U;
    /* Message RAM */
    stcMcanInit.stcMsgRam.u32AddrOffset        = 0U;
    stcMcanInit.stcMsgRam.u32StdFilterNum      = MCAN_STD_FILTER_NUM;
    stcMcanInit.stcMsgRam.u32ExtFilterNum      = MCAN_EXT_FILTER_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo0Num        = MCAN_RX_FIFO0_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo0DataSize   = MCAN_RX_FIFO0_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32RxFifo1Num        = MCAN_RX_FIFO1_NUM;
    stcMcanInit.stcMsgRam.u32RxFifo1DataSize   = MCAN_RX_FIFO1_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32RxBufferNum       = MCAN_RX_BUF_NUM;
    stcMcanInit.stcMsgRam.u32RxBufferDataSize  = MCAN_RX_BUF_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32TxBufferNum       = MCAN_TX_BUF_NUM;
    stcMcanInit.stcMsgRam.u32TxFifoQueueNum    = MCAN_TX_FIFO_NUM;
    stcMcanInit.stcMsgRam.u32TxFifoQueueMode   = MCAN_TX_FIFO_MD;
    stcMcanInit.stcMsgRam.u32TxDataSize        = MCAN_TX_BUF_DATA_FIELD_SIZE;
    stcMcanInit.stcMsgRam.u32TxEventNum        = MCAN_TX_EVT_NUM;
    /* Acceptance filter */
    stcMcanInit.stcFilter.pstcStdFilterList     = stcStdFilterList;
    stcMcanInit.stcFilter.pstcExtFilterList     = stcExtFilterList;
    stcMcanInit.stcFilter.u32StdFilterConfigNum = stcMcanInit.stcMsgRam.u32StdFilterNum;
    stcMcanInit.stcFilter.u32ExtFilterConfigNum = stcMcanInit.stcMsgRam.u32ExtFilterNum;

    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN2, DISABLE);
    FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_MCAN2, ENABLE);
    MCAN_Init(CM_MCAN2, &stcMcanInit);

    /* Watermark if needed */
    MCAN_SetFifoWatermark(CM_MCAN2, MCAN_WATERMARK_RX_FIFO0, MCAN_RX_FIFO0_WATERMARK);
    MCAN_SetFifoWatermark(CM_MCAN2, MCAN_WATERMARK_RX_FIFO1, MCAN_RX_FIFO1_WATERMARK);

    /* Configure Rx FIFO0 operation mode if needed.
       If new message received when Rx FIFO0 is full, the new message
       will not be stored and Message Lost Interrupt will be generated. */
    MCAN_RxFifoOperationModeConfig(CM_MCAN2, MCAN_RX_FIFO0, MCAN_RX_FIFO_BLOCKING);
    /* Configure Rx FIFO1 operation mode if needed.
       If new message received when Rx FIFO1 is full, the new received message
       will overwrite the oldest received message and RF1N Interrupt generated. */
    MCAN_RxFifoOperationModeConfig(CM_MCAN2, MCAN_RX_FIFO1, MCAN_RX_FIFO_BLOCKING);

    /* Configures timestamp if needed */
    MCAN_TimestampCounterConfig(CM_MCAN2, 1U);
    MCAN_TimestampCounterCmd(CM_MCAN2, ENABLE);

    /* The Tx buffer can cause transmission completed completed interrupt
       only when its own transmission completed interrupt is enabled. */
    MCAN_TxBufferNotificationCmd(CM_MCAN2, MCAN_TX_NOTIFICATION_BUF, MCAN_INT_TX_CPLT, ENABLE);

    MCAN_IntCmd(CM_MCAN2, MCAN_INT0_SEL, MCAN_INT_LINE0, ENABLE);

			 
		NVIC_ClearPendingIRQ(MCAN2_INT0_IRQn);
    NVIC_SetPriority(MCAN2_INT0_IRQn, DDL_IRQ_PRIO_06);
    NVIC_EnableIRQ(MCAN2_INT0_IRQn); 
	
}


void MCAN2_INT0_Handler(void)
{
    uint32_t u32RxBuffer;
    uint32_t u32TxBufferIndex;
    uint32_t u32TxBuffer = 0U;
    stc_mcan_rx_msg_t stcRxMsg;
    stc_mcan_tx_msg_t stcTxMsg;
    stc_mcan_rx_msg_t stcRxMsgRxFifo1[MCAN_RX_FIFO1_NUM];
	
		static uint32_t pxHigherPriorityTaskWoken = pdFALSE;

    /* Rx FIFO0 related interrupts */
    if (MCAN_GetStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO0_NEW_MSG) == SET) {
        MCAN_ClearStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO0_NEW_MSG);
        /* Messages stored in Rx FIFO0 can be read here */
        printf("Rx FIFO_0 new message->\r\n");
        if (MCAN_GetRxMsg(CM_MCAN2, MCAN_RX_FIFO0, &stcRxMsg) == LL_OK) {					
					//printf("stcRxMsg.IDE=%d,stcRxMsg.ID=%x\r\n",stcRxMsg.IDE,stcRxMsg.ID);
					for(int i =0;i <8;i++)
					{
					  printf("%x ",stcRxMsg.au8Data[i]);
					}									
					
					hc32_can_rx_msg_t hc32_can_rx_msg;
					hc32_can_rx_msg.ide =stcRxMsg.IDE;
					hc32_can_rx_msg.id = stcRxMsg.ID;
					hc32_can_rx_msg.len = 8;//stcRxMsg.DLC;//直接赋值
					memcpy(hc32_can_rx_msg.data,stcRxMsg.au8Data,8);
					
					xQueueOverwriteFromISR(can2_recieve1_data_queue,&hc32_can_rx_msg,(BaseType_t*)&pxHigherPriorityTaskWoken);
                               
					portEND_SWITCHING_ISR(pxHigherPriorityTaskWoken);	
        }  
    }
    if (MCAN_GetStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO0_FULL) == SET) 
		{
        MCAN_ClearStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO0_FULL);
    }

 
    /* Rx FIFO1 related interrupts */
    if (MCAN_GetStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO1_NEW_MSG) == SET) 
		{
        MCAN_ClearStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO1_NEW_MSG);
			  printf("Rx FIFO_1 new message->\r\n");
        if (MCAN_GetRxMsg(CM_MCAN2, MCAN_RX_FIFO1, &stcRxMsg) == LL_OK) {
					//printf("stcRxMsg.IDE=%d,stcRxMsg.ID=%x\r\n",stcRxMsg.IDE,stcRxMsg.ID);
					for(int i =0;i <8;i++)
					{
					  printf("%x ",stcRxMsg.au8Data[i]);
					}
						
					hc32_can_rx_msg_t hc32_can_rx_msg;
					hc32_can_rx_msg.ide =stcRxMsg.IDE;
					hc32_can_rx_msg.id = stcRxMsg.ID;
					hc32_can_rx_msg.len = 8;//stcRxMsg.DLC;//直接赋值
					memcpy(hc32_can_rx_msg.data,stcRxMsg.au8Data,8);					
					xQueueOverwriteFromISR(can2_recieve1_data_queue,&hc32_can_rx_msg,(BaseType_t*)&pxHigherPriorityTaskWoken);
 
                               
					portEND_SWITCHING_ISR(pxHigherPriorityTaskWoken);
					
        } 
    }

    if (MCAN_GetStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO1_FULL) == SET) {
        MCAN_ClearStatus(CM_MCAN2, MCAN_FLAG_RX_FIFO1_FULL);
        /* All dedicated Tx buffer are filled. Add transmission requests. */
        MCAN_EnableTxBufferRequest(CM_MCAN2, u32TxBuffer);
    }
	
    /* Dedicated Rx buffer related interrupts */
    if (MCAN_GetStatus(CM_MCAN2, MCAN_FLAG_RX_BUF_NEW_MSG) == SET) {
        MCAN_ClearStatus(CM_MCAN2, MCAN_FLAG_RX_BUF_NEW_MSG);
    }
}


int32_t can_send_msg(CM_MCAN_TypeDef *MCANx,stc_mcan_tx_msg_t *pTxMsg)
{
	return MCAN_AddMsgToTxFifoQueue(MCANx,pTxMsg);
}