hal_clk_func.c 2.0 KB

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  1. #include "hal_clk_func.h"
  2. #include "hc32_ll_clk.h"
  3. #include <string.h>
  4. #include <stdio.h>
  5. #include "hal_uart.h"
  6. #include "hc32_ll_sram.h"
  7. #include "hc32_ll_efm.h"
  8. int fputc(int ch, FILE *f)
  9. {
  10. (void)f;
  11. USART_UART_Trans(CM_USART2,&ch,1,0xff);
  12. return ch;
  13. }
  14. void sys_clk_init(void)
  15. {
  16. stc_clock_xtal_init_t stcXtalInit;
  17. stc_clock_pll_init_t stcPLLHInit;
  18. /* PCLK0, HCLK Max 200MHz */
  19. /* PCLK1, PCLK4, EX BUS Max 100MHz */
  20. /* PCLK2 Max 75MHz */
  21. /* PCLK3 Max 50MHz */
  22. CLK_SetClockDiv(CLK_BUS_CLK_ALL,
  23. (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
  24. CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 |
  25. CLK_HCLK_DIV1));
  26. GPIO_AnalogCmd(GPIO_PORT_H, GPIO_PIN_00 | GPIO_PIN_01, ENABLE);//PH0,PH1
  27. (void)CLK_XtalStructInit(&stcXtalInit);
  28. /* Config Xtal and enable Xtal */
  29. stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
  30. stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
  31. stcXtalInit.u8State = CLK_XTAL_ON;
  32. stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
  33. (void)CLK_XtalInit(&stcXtalInit);
  34. (void)CLK_PLLStructInit(&stcPLLHInit);
  35. /* VCO = (8/1)*100 = 800MHz*/
  36. /* 8MHz/M*N = 8/1*100/4 = 200MHz *///????????
  37. /* 16MHz/M*N = 16/2*100/4 = 200MHz *///????????
  38. stcPLLHInit.u8PLLState = CLK_PLL_ON;
  39. stcPLLHInit.PLLCFGR = 0UL;
  40. stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;//
  41. stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
  42. stcPLLHInit.PLLCFGR_f.PLLP = 8UL - 1UL;
  43. stcPLLHInit.PLLCFGR_f.PLLQ = 8UL - 1UL;
  44. stcPLLHInit.PLLCFGR_f.PLLR = 8UL - 1UL;
  45. stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
  46. (void)CLK_PLLInit(&stcPLLHInit);
  47. SRAM_SetWaitCycle((SRAM_SRAMH | SRAM_SRAM0), SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
  48. /* SRAMB set to 1 Read/Write wait cycle */
  49. SRAM_SetWaitCycle(SRAM_SRAMB, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
  50. /* 3 cycles for 150 ~ 200MHz */
  51. (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3);
  52. /* 3 cycles for 150 ~ 200MHz */
  53. GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
  54. CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
  55. }