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- #include "hal_clk_func.h"
- #include "hc32_ll_clk.h"
- #include <string.h>
- #include <stdio.h>
- #include "hal_uart.h"
- #include "hc32_ll_sram.h"
- #include "hc32_ll_efm.h"
- int fputc(int ch, FILE *f)
- {
- (void)f;
- USART_UART_Trans(CM_USART2,&ch,1,0xff);
- return ch;
- }
- void sys_clk_init(void)
- {
- stc_clock_xtal_init_t stcXtalInit;
- stc_clock_pll_init_t stcPLLHInit;
- /* PCLK0, HCLK Max 200MHz */
- /* PCLK1, PCLK4, EX BUS Max 100MHz */
- /* PCLK2 Max 75MHz */
- /* PCLK3 Max 50MHz */
- CLK_SetClockDiv(CLK_BUS_CLK_ALL,
- (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
- CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 |
- CLK_HCLK_DIV1));
-
- GPIO_AnalogCmd(GPIO_PORT_H, GPIO_PIN_00 | GPIO_PIN_01, ENABLE);//PH0,PH1
- (void)CLK_XtalStructInit(&stcXtalInit);
- /* Config Xtal and enable Xtal */
- stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
- stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
- stcXtalInit.u8State = CLK_XTAL_ON;
- stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
- (void)CLK_XtalInit(&stcXtalInit);
- (void)CLK_PLLStructInit(&stcPLLHInit);
- /* VCO = (8/1)*100 = 800MHz*/
- /* 8MHz/M*N = 8/1*100/4 = 200MHz *///????????
-
- /* 16MHz/M*N = 16/2*100/4 = 200MHz *///????????
- stcPLLHInit.u8PLLState = CLK_PLL_ON;
- stcPLLHInit.PLLCFGR = 0UL;
- stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;//
- stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
- stcPLLHInit.PLLCFGR_f.PLLP = 8UL - 1UL;
- stcPLLHInit.PLLCFGR_f.PLLQ = 8UL - 1UL;
- stcPLLHInit.PLLCFGR_f.PLLR = 8UL - 1UL;
- stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
- (void)CLK_PLLInit(&stcPLLHInit);
- SRAM_SetWaitCycle((SRAM_SRAMH | SRAM_SRAM0), SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
- /* SRAMB set to 1 Read/Write wait cycle */
- SRAM_SetWaitCycle(SRAM_SRAMB, SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
- /* 3 cycles for 150 ~ 200MHz */
- (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3);
- /* 3 cycles for 150 ~ 200MHz */
- GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
- CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
- }
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