hc32_ll_mcan.h 71 KB

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  1. /**
  2. *******************************************************************************
  3. * @file hc32_ll_mcan.h
  4. * @brief This file contains all the functions prototypes of the MCAN driver
  5. * library.
  6. @verbatim
  7. Change Logs:
  8. Date Author Notes
  9. 2022-12-31 CDT First version
  10. @endverbatim
  11. *******************************************************************************
  12. * Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd. All rights reserved.
  13. *
  14. * This software component is licensed by XHSC under BSD 3-Clause license
  15. * (the "License"); You may not use this file except in compliance with the
  16. * License. You may obtain a copy of the License at:
  17. * opensource.org/licenses/BSD-3-Clause
  18. *
  19. *******************************************************************************
  20. */
  21. #ifndef __HC32_LL_MCAN_H__
  22. #define __HC32_LL_MCAN_H__
  23. /* C binding of definitions if building with C++ compiler */
  24. #ifdef __cplusplus
  25. extern "C"
  26. {
  27. #endif
  28. /*******************************************************************************
  29. * Include files
  30. ******************************************************************************/
  31. #include "hc32_ll_def.h"
  32. #include "hc32f4xx.h"
  33. #include "hc32f4xx_conf.h"
  34. /**
  35. * @addtogroup LL_Driver
  36. * @{
  37. */
  38. /**
  39. * @addtogroup LL_MCAN
  40. * @{
  41. */
  42. #if (LL_MCAN_ENABLE == DDL_ON)
  43. /*******************************************************************************
  44. * Global type definitions ('typedef')
  45. ******************************************************************************/
  46. /**
  47. * @defgroup MCAN_Global_Types MCAN Global Types
  48. * @{
  49. */
  50. /**
  51. * @brief MCAN classic CAN configuration structure definition
  52. */
  53. typedef struct {
  54. uint32_t u32Prescaler; /*!< Specifies the nominal bit rate prescaler.
  55. This parameter must be a number between 1 and 512 */
  56. uint32_t u32TimeSeg1; /*!< Specifies the nominal time segment before sample point(the sum of Sync_Seg,
  57. Prop_Seg and Phase_Seg1).
  58. This parameter must be a number between 3 and 257 */
  59. uint32_t u32TimeSeg2; /*!< Specifies the nominal time segment after sample point(Phase_Seg2).
  60. This parameter must be a number between 2 and 128 */
  61. uint32_t u32SyncJumpWidth; /*!< Specifies the nominal (re)synchronization jump width(SJW).
  62. This parameter must be a number between 1 and 128 */
  63. } stc_mcan_classic_config_t;
  64. /**
  65. * @brief MCAN FD CAN configuration structure definition
  66. */
  67. typedef struct {
  68. uint32_t u32FdIso; /*!< Specifies the CAN FD frame format, according to ISO 11898-1:2015
  69. or Bosch CAN FD Specification V1.0.
  70. This parameter can be a value of @ref MCAN_FD_ISO_Operation */
  71. uint32_t u32Prescaler; /*!< Specifies the data bit rate prescaler.
  72. This parameter must be a number between 1 and 32
  73. NOTE: when u32TDC is MCAN_FD_TDC_ENABLE, the range is limited to 1, 2 */
  74. uint32_t u32TimeSeg1; /*!< Specifies the data time segment before sample point(the sum of Sync_Seg,
  75. Prop_Seg and Phase_Seg1).
  76. This parameter must be a number between 2 and 33 */
  77. uint32_t u32TimeSeg2; /*!< Specifies the data time segment after sample point(Phase_Seg2).
  78. This parameter must be a number between 1 and 16 */
  79. uint32_t u32SyncJumpWidth; /*!< Specifies the data (re)synchronization jump width(SJW).
  80. This parameter must be a number between 1 and 16 */
  81. uint32_t u32TDC; /*!< Enable or disable TDC(Transmitter Delay Compensation).
  82. This parameter can be a value of @ref MCAN_TDC_Enable */
  83. uint32_t u32SspOffset; /*!< Specifies the transmitter delay compensation SSP offset.
  84. This parameter must be a number between 0 and 127(MCAN clock) */
  85. uint32_t u32TdcFilter; /*!< Specifies the transmitter delay compensation filter window length.
  86. This parameter defines the minimum value for the SSP position.
  87. The feature is enabled when this parameter is configured to a value
  88. greater than u32SspOffset.
  89. This parameter must be a number between 0 and 127(MCAN clock) */
  90. } stc_mcan_fd_config_t;
  91. /**
  92. * @brief MCAN message RAM address blocks
  93. */
  94. typedef struct {
  95. uint32_t u32StdFilterStartAddr; /*!< Output parameter. Indicates the standard filter list start address. */
  96. uint32_t u32ExtFilterStartAddr; /*!< Output parameter. Indicates the extended filter list start address. */
  97. uint32_t u32RxFifo0StartAddr; /*!< Output parameter. Indicates the Rx FIFO 0 start address. */
  98. uint32_t u32RxFifo1StartAddr; /*!< Output parameter. Indicates the Rx FIFO 1 start address. */
  99. uint32_t u32RxBufferStartAddr; /*!< Output parameter. Indicates the Rx buffer start address. */
  100. uint32_t u32TxEventStartAddr; /*!< Output parameter. Indicates the Tx event FIFO start address. */
  101. uint32_t u32TxBufferStartAddr; /*!< Output parameter. Indicates the Tx buffers start address. */
  102. uint32_t u32TxFifoQueueStartAddr; /*!< Output parameter. Indicates the Tx FIFO/Queue start address. */
  103. uint32_t u32EndAddr; /*!< Output parameter. Indicates the end address of the allocated RAM. */
  104. uint32_t *pu32StdFilterAddrList; /*!< Pointer to an address that used to store each standard ID filter element address.
  105. Set it to NULL if you do not need the element address information. */
  106. uint32_t *pu32ExtFilterAddrList; /*!< Pointer to an address that used to store each extended ID filter element address.
  107. Set it to NULL if you do not need the element address information. */
  108. uint32_t *pu32RxFifo0AddrList; /*!< Pointer to an address that used to store each Rx FIFO0 element address.
  109. Set it to NULL if you do not need the element address information. */
  110. uint32_t *pu32RxFifo1AddrList; /*!< Pointer to an address that used to store each Rx FIFO1 element address.
  111. Set it to NULL if you do not need the element address information. */
  112. uint32_t *pu32RxBufferAddrList; /*!< Pointer to an address that used to store each Rx buffer element address.
  113. Set it to NULL if you do not need the element address information. */
  114. uint32_t *pu32TxEventAddrList; /*!< Pointer to an address that used to store each Tx event FIFO element address.
  115. Set it to NULL if you do not need the element address information. */
  116. uint32_t *pu32TxBufferAddrList; /*!< Pointer to an address that used to store each dedicated Tx buffer element address.
  117. Set it to NULL if you do not need the element address information. */
  118. uint32_t *pu32TxFifoQueueAddrList; /*!< Pointer to an address that used to store each Tx FIFO/queue element address.
  119. Set it to NULL if you do not need the element address information. */
  120. } stc_mcan_msg_ram_addr_t;
  121. /**
  122. * @brief MCAN message RAM configuration structure definition
  123. */
  124. typedef struct {
  125. uint32_t u32AddrOffset; /*!< Specifies the message RAM start address.
  126. NOTE: The message RAM is 2K bytes and shared by MCAN1 and MCAN2. */
  127. uint32_t u32StdFilterNum; /*!< Specifies the number of standard message ID filters.
  128. This parameter is used to allocate RAM to standard ID filters.
  129. This parameter must be a number between 0 and 128 */
  130. uint32_t u32ExtFilterNum; /*!< Specifies the number of extended message ID filters.
  131. This parameter is used to allocate RAM to extended ID filters.
  132. This parameter must be a number between 0 and 64 */
  133. uint32_t u32RxFifo0Num; /*!< Specifies the number of Rx FIFO0 elements.
  134. u32RxFifo0Num and u32RxFifo0DataSize are used to allocate RAM to Rx FIFO0.
  135. This parameter must be a number between 0 and 64 */
  136. uint32_t u32RxFifo0DataSize; /*!< Specifies the data field size in an Rx FIFO 0 element.
  137. This parameter can be a value of @ref MCAN_Data_Field_Size */
  138. uint32_t u32RxFifo1Num; /*!< Specifies the number of Rx FIFO 1 elements.
  139. u32RxFifo1Num and u32RxFifo1DataSize are used to allocate RAM to Rx FIFO1.
  140. This parameter must be a number between 0 and 64 */
  141. uint32_t u32RxFifo1DataSize; /*!< Specifies the data field size in an Rx FIFO 1 element.
  142. This parameter can be a value of @ref MCAN_Data_Field_Size */
  143. uint32_t u32RxBufferNum; /*!< Specifies the number of dedicated Rx buffer elements.
  144. u32RxBufferNum and u32RxBufferDataSize are used to allocate RAM to Rx buffer.
  145. This parameter must be a number between 0 and 64 */
  146. uint32_t u32RxBufferDataSize; /*!< Specifies the data field size in an Rx buffer element.
  147. This parameter can be a value of @ref MCAN_Data_Field_Size */
  148. uint32_t u32TxEventNum; /*!< Specifies the number of Tx event FIFO elements.
  149. This parameter is used to allocate RAM to Tx event FIFO.
  150. This parameter must be a number between 0 and 32 */
  151. uint32_t u32TxBufferNum; /*!< Specifies the number of dedicated Tx buffers.
  152. u32TxBufferNum and u32TxFifoQueueNum and u32TxDataSize are used to allocate RAM for Tx messages.
  153. The sum of u32TxBufferNum and u32TxFifoQueueNum must be a number between 0 and 32 */
  154. uint32_t u32TxFifoQueueNum; /*!< Specifies the number of Tx buffers used for Tx FIFO/queue.
  155. The sum of u32TxFifoQueueNum and u32TxBufferNum must be a number between 0 and 32 */
  156. uint32_t u32TxFifoQueueMode; /*!< Specifies Tx FIFO/Queue operation mode.
  157. This parameter can be a value of @ref MCAN_Tx_FIFO_Queue_Mode */
  158. uint32_t u32TxDataSize; /*!< Specifies the data field size in a Tx element.
  159. This parameter can be a value of @ref MCAN_Data_Field_Size */
  160. uint32_t u32AllocatedSize; /*!< Output parameter. Indicates the message RAM size that allocated to the configured MCAN.
  161. It is also the address offset of the MCAN to be configured. */
  162. } stc_mcan_msg_ram_config_t;
  163. /**
  164. * @brief MCAN filter structure definition
  165. */
  166. typedef struct {
  167. uint32_t u32IdType; /*!< Specifies the ID type.
  168. This parameter can be a value of @ref MCAN_ID_Type */
  169. uint32_t u32FilterIndex; /*!< Specifies the filter which will be initialized.
  170. This parameter must be a number between:
  171. - 0 and 127, if u32IdType is MCAN_STD_ID
  172. - 0 and 63, if u32IdType is MCAN_EXT_ID */
  173. uint32_t u32FilterType; /*!< Specifies the filter type.
  174. This parameter can be a value of @ref MCAN_Filter_Type
  175. The value MCAN_FILTER_RANGE_NO_EIDM is permitted only when u32IdType is MCAN_EXT_ID.
  176. This parameter is ignored if u32FilterConfig is set to MCAN_FILTER_TO_RX_BUF */
  177. uint32_t u32FilterConfig; /*!< Specifies the filter configuration.
  178. This parameter can be a value of @ref MCAN_Filter_Config */
  179. uint32_t u32FilterId1; /*!< Specifies the filter ID1.
  180. This parameter must be a number between:
  181. - 0 and 0x7FF, if u32IdType is MCAN_STD_ID
  182. - 0 and 0x1FFFFFFF, if u32IdType is MCAN_EXT_ID */
  183. uint32_t u32FilterId2; /*!< Specifies the filter ID2.
  184. This parameter is ignored if u32FilterConfig is set to MCAN_FILTER_TO_RX_BUF.
  185. This parameter must be a number between:
  186. - 0 and 0x7FF, if u32IdType is MCAN_STD_ID
  187. - 0 and 0x1FFFFFFF, if u32IdType is MCAN_EXT_ID */
  188. uint32_t u32RxBufferIndex; /*!< Specifies the dedicated Rx buffer in which the matching message will be stored.
  189. This parameter must be a number between 0 and 63, and less than or equal to
  190. u32RxBufferNum of @ref stc_mcan_msg_ram_config_t
  191. This parameter is ignored if u32FilterConfig is different from MCAN_FILTER_TO_RX_BUF */
  192. } stc_mcan_filter_t;
  193. /**
  194. * @brief MCAN filter initialization structure definition
  195. */
  196. typedef struct {
  197. stc_mcan_filter_t *pstcStdFilterList; /*!< Pointer to the standard ID filter elements list.
  198. These filter elements can be configured only when:
  199. pstcStdFilterList != NULL and
  200. u32StdFilterConfigNum > 0 and
  201. u32StdFilterConfigNum <= u32StdFilterNum of @ref stc_mcan_msg_ram_config_t */
  202. stc_mcan_filter_t *pstcExtFilterList; /*!< Pointer to the extended ID filter elements list.
  203. These filter elements can be configured only when:
  204. pstcExtFilterList != NULL and
  205. u32ExtFilterConfigNum > 0 and
  206. u32ExtFilterConfigNum <= u32ExtFilterNum of @ref stc_mcan_msg_ram_config_t */
  207. uint32_t u32StdFilterConfigNum; /*!< Number of the standard ID filter elements which to be configured.
  208. This parameter must less than or equal to u32StdFilterNum
  209. of @ref stc_mcan_msg_ram_config_t */
  210. uint32_t u32ExtFilterConfigNum; /*!< Number of the extended ID filter elements which to be configured.
  211. This parameter must less than or equal to u32ExtFilterNum
  212. of @ref stc_mcan_msg_ram_config_t */
  213. } stc_mcan_filter_config_t;
  214. /**
  215. * @brief MCAN initialization structure
  216. */
  217. typedef struct {
  218. uint32_t u32Mode; /*!< Specifies MCAN operating mode.
  219. This parameter can be a value of @ref MCAN_Operating_Mode */
  220. uint32_t u32FrameFormat; /*!< Specifies the frame format supported by MCAN hardware.
  221. This parameter can be a value of @ref MCAN_Frame_Format */
  222. uint32_t u32AutoRetx; /*!< Enable or disable automatic retransmission.
  223. This parameter can be a value of @ref MCAN_Auto_Retx_Enable */
  224. uint32_t u32TxPause; /*!< Enable or disable transmit pause.
  225. If transmit pause is enabled, MCAN pauses for two CAN bit times before starting
  226. the next transmission after itself has successfully transmitted a frame.
  227. This parameter can be a value of @ref MCAN_Tx_Pause_Enable */
  228. uint32_t u32ProtocolException; /*!< Enable or disable protocol exception handling.
  229. When this function is disabled, MCAN will transmit an error frame
  230. when it detects a protocol exception condition.
  231. This parameter can be a value of @ref MCAN_Protocol_Exception_Enable */
  232. stc_mcan_classic_config_t stcCanClassic; /*!< Classic CAN configuration structure. */
  233. stc_mcan_fd_config_t stcCanFd; /*!< FD CAN configuration structure. */
  234. stc_mcan_msg_ram_config_t stcMsgRam; /*!< Message RAM configuration structure. */
  235. stc_mcan_filter_config_t stcFilter; /*!< Acceptance filter configuration structure. */
  236. } stc_mcan_init_t;
  237. /**
  238. * @brief MCAN Tx message structure definition
  239. */
  240. typedef struct {
  241. uint32_t ID; /*!< Specifies the ID.
  242. This parameter must be a number between:
  243. - 0 and 0x7FF, if IDE is 0
  244. - 0 and 0x1FFFFFFF, if IDE is 1 */
  245. uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the transmitted message.
  246. This parameter can be a value of:
  247. - 0: 11-bit standard ID
  248. - 1: 29-bit extended ID */
  249. uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the transmitted message.
  250. This parameter can be a value of:
  251. - 0: Data frame to be transmitted
  252. - 1: Remote frame to be transmitted */
  253. uint32_t DLC; /*!< Data Length Code. Specifies the length of the data field of the transmitted frame.
  254. This parameter can be a value of @ref MCAN_Data_Length_Code */
  255. uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator.
  256. This parameter can be a value of:
  257. - 0: Transmitting node is error active
  258. - 1: Transmitting node is error passive */
  259. uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is transmitted with or without bit rate switching.
  260. This parameter can be a value of:
  261. - 0: Frame transmitted without bit rate switching
  262. - 1: Frame transmitted with bit rate switching */
  263. uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is transmitted in classic or FD format.
  264. This parameter can be a value of:
  265. - 0: Classical CAN frame format
  266. - 1: CAN FD frame format (new DLC-coding and CRC) */
  267. uint32_t u32StoreTxEvent; /*!< Specifies the event FIFO control.
  268. This parameter can be a value of:
  269. - 0: DO NOT store tx event
  270. - 1: Store tx event into TX event FIFO */
  271. uint32_t u32MsgMarker; /*!< Specifies the message marker to be copied into Tx event FIFO
  272. element for identification of Tx message status.
  273. This parameter must be a number between:
  274. - 0 and 0xFF if 8-bit message marker used(CCCR.WMM == 0)
  275. - 0 and 0xFFFF if 16-bit-width message marker used(CCCR.WMM == 1) */
  276. uint32_t u32TxBuffer; /*!< Specifies the dedicated Tx buffer that used to transmit the message.
  277. This parameter can be a value of @ref MCAN_Tx_Location
  278. This parameter valid when Tx via dedicated Tx buffer. */
  279. uint8_t au8Data[64U]; /*!< Data payload of the message that to be transmitted. */
  280. uint32_t u32LastTxFifoQueueRequest; /*!< Ouput parameter of Tx buffer index of last Tx FIFO/queue request.
  281. This paramter valid when Tx via FIFO or queue. */
  282. } stc_mcan_tx_msg_t;
  283. /**
  284. * @brief MCAN Rx message structure definition
  285. */
  286. typedef struct {
  287. uint32_t ID; /*!< Specifies the ID.
  288. This parameter must be a number between:
  289. - 0 and 0x7FF, if IDE is 0
  290. - 0 and 0x1FFFFFFF, if IDE is 1 */
  291. uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the received message.
  292. This parameter can be a value of:
  293. - 0: 11-bit standard ID
  294. - 1: 29-bit extended ID */
  295. uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the received message.
  296. This parameter can be a value of:
  297. - 0: Data frame received
  298. - 1: Remote frame received */
  299. uint32_t DLC; /*!< Data Length Code. Specifies the length of data filed of the received frame.
  300. This parameter can be a value of @ref MCAN_Data_Length_Code */
  301. uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator.
  302. This parameter can be a value of:
  303. - 0: Transmitting node is error active
  304. - 1: Transmitting node is error passive */
  305. uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is received with or without bit rate switching.
  306. This parameter can be a value of:
  307. - 0: Frame received without bit rate switching
  308. - 1: Frame received with bit rate switching */
  309. uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is received in classic or FD format.
  310. This parameter can be a value of:
  311. - 0: Classical CAN frame format
  312. - 1: CAN FD frame format (new DLC-coding and CRC) */
  313. uint32_t u32RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
  314. This parameter must be a number between 0 and 0xFFFF */
  315. uint32_t u32FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
  316. This parameter must be a number between:
  317. - 0 and 127, if IDE is 0
  318. - 0 and 63, if IDE is 1 */
  319. uint32_t u32NmfFlag; /*!< Specifies whether the accepted frame did not match any Rx filter.
  320. Acceptance of non-matching frames may be configured via @ref MCAN_GlobalFilterConfig()
  321. This parameter can be:
  322. - 0: Received frame matching filter index u32FilterIndex
  323. - 1: Received frame did not match any Rx filter element */
  324. uint8_t au8Data[64U]; /*!< Data payload of the received message */
  325. uint32_t u32DataSize; /*!< Size of Rx data payload */
  326. } stc_mcan_rx_msg_t;
  327. /**
  328. * @brief MCAN Tx event structure definition
  329. */
  330. typedef struct {
  331. uint32_t ID; /*!< Specifies the ID.
  332. This parameter must be a number between:
  333. - 0 and 0x7FF, if IDE is 0
  334. - 0 and 0x1FFFFFFF, if IDE is 1 */
  335. uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the transmitted message.
  336. This parameter can be a value of:
  337. - 0: 11-bit standard ID
  338. - 1: 29-bit extended ID */
  339. uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the transmitted message.
  340. This parameter can be a value of:
  341. - 0: Data frame transmitted
  342. - 1: Remote frame transmitted */
  343. uint32_t DLC; /*!< Data Length Code. Specifies the length of the transmitted frame.
  344. This parameter can be a value of @ref MCAN_Data_Length_Code */
  345. uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator.
  346. This parameter can be a value of:
  347. - 0: Transmitting node is error active
  348. - 1: Transmitting node is error passive */
  349. uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is transmitted with or without bit rate switching.
  350. This parameter can be a value of:
  351. - 0: Frame transmitted without bit rate switching
  352. - 1: Frame transmitted with bit rate switching */
  353. uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is transmitted in classic or FD format.
  354. This parameter can be a value of:
  355. - 0: Classical CAN frame format
  356. - 1: CAN FD frame format (new DLC-coding and CRC) */
  357. uint32_t u32TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame transmission.
  358. This parameter is valid only when 8-bit message marker used.
  359. This parameter must be a number between 0 and 0xFFFF. */
  360. uint32_t u32MsgMarker; /*!< Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status.
  361. This parameter must be a number between:
  362. - 0 and 0xFF if 8-bit message marker used(CCCR.WMM == 0)
  363. - 0 and 0xFFFF if 16-bit-width message marker used(CCCR.WMM == 1) */
  364. uint32_t u32EventType; /*!< Specifies the event type.
  365. This parameter can be a value of @ref MCAN_Evt_Type */
  366. } stc_mcan_tx_event_t;
  367. /**
  368. * @brief MCAN high priority message status structure definition
  369. */
  370. typedef struct {
  371. uint8_t u8FilterListType; /*!< Specifies the filter list of the matching filter element.
  372. This parameter can be:
  373. - 0: Standard filter list
  374. - 1: Extended filter list */
  375. uint8_t u8FilterIndex; /*!< Specifies the index of matching filter element.
  376. This parameter can be a number between:
  377. - 0 and 127, if u8FilterListType is 0 (Standard)
  378. - 0 and 63, if u8FilterListType is 1 (Extended) */
  379. uint8_t u8MsgStorage; /*!< Specifies the high priority message storage.
  380. This parameter can be a value of @ref MCAN_HPM_Storage */
  381. uint8_t u8MsgStorageIndex; /*!< Specifies the index of Rx FIFO element to which the message was stored.
  382. This parameter is valid only when u32MsgStorage is:
  383. MCAN_HPM_STORED_IN_RX_FIFO0 or MCAN_HPM_STORED_IN_RX_FIFO1 */
  384. } stc_mcan_hpm_status_t;
  385. /**
  386. * @brief MCAN protocol status structure definition
  387. */
  388. typedef struct {
  389. uint8_t u8LastErrorCode; /*!< Specifies the type of the last error that occurred on the CAN bus.
  390. This parameter can be a value of @ref MCAN_Protocol_Error_Code */
  391. uint8_t u8DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
  392. frame with its BRS flag set.
  393. This parameter can be a value of @ref MCAN_Protocol_Error_Code */
  394. uint8_t u8Activity; /*!< Specifies the CAN module communication state.
  395. This parameter can be a value of @ref MCAN_Comm_State */
  396. uint8_t u8ErrorPassiveFlag; /*!< Specifies the CAN module error status.
  397. This parameter can be:
  398. - 0: The CAN is in the Error_Active state
  399. - 1: The CAN is in the Error_Passive state */
  400. uint8_t u8WarningFlag; /*!< Specifies the CAN module warning status.
  401. This parameter can be:
  402. - 0: Both error counters are below the Error_Warning limit of 96
  403. - 1: At least one of error counter has reached the Error_Warning limit of 96 */
  404. uint8_t u8BusOffFlag; /*!< Specifies the CAN module Bus_Off status.
  405. This parameter can be:
  406. - 0: The CAN is not in Bus_Off state
  407. - 1: The CAN is in Bus_Off state */
  408. uint8_t u8RxESIFlag; /*!< Specifies ESI flag of last received CAN FD message.
  409. This parameter can be:
  410. - 0: Last received CAN FD message did not have its ESI flag set
  411. - 1: Last received CAN FD message had its ESI flag set */
  412. uint8_t u8RxBRSFlag; /*!< Specifies BRS flag of last received CAN FD message.
  413. This parameter can be:
  414. - 0: Last received CAN FD message did not have its BRS flag set
  415. - 1: Last received CAN FD message had its BRS flag set */
  416. uint8_t u8RxFDFFlag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
  417. This parameter can be:
  418. - 0: Since this bit was reset by the CPU, no CAN FD message has been received
  419. - 1: Message in CAN FD format with FDF flag set has been received */
  420. uint8_t u8ProtocolExceptionFlag; /*!< Specifies the CAN module protocol exception status.
  421. This parameter can be:
  422. - 0: No protocol exception event occurred since last read access
  423. - 1: Protocol exception event occurred */
  424. uint8_t u8TdcValue; /*!< Specifies the Transmitter Delay Compensation Value.
  425. This parameter can be a number between 0 and 127 */
  426. } stc_mcan_protocol_status_t;
  427. /**
  428. * @brief MCAN error counters structure definition
  429. */
  430. typedef struct {
  431. uint8_t u8TxErrorCount; /*!< Specifies the Transmit Error Counter Value.
  432. This parameter can be a number between 0 and 255 */
  433. uint8_t u8RxErrorCount; /*!< Specifies the Receive Error Counter Value.
  434. This parameter can be a number between 0 and 127 */
  435. uint8_t u8RxErrorPassive; /*!< Specifies the Receive Error Passive status.
  436. This parameter can be:
  437. - 0: The Receive Error Counter (u8RxErrorCount) is below the error passive level of 128
  438. - 1: The Receive Error Counter (u8RxErrorCount) has reached the error passive level of 128 */
  439. uint8_t u8ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
  440. This parameter can be a number between 0 and 255.
  441. This counter is incremented each time when a CAN protocol error causes the u8TxErrorCount
  442. or the u8RxErrorCount to be incremented. The counter stops at 255; the next increment of
  443. u8TxErrorCount or u8RxErrorCount sets interrupt flag MCAN_FLAG_ERR_LOG_OVF */
  444. } stc_mcan_error_counter_t;
  445. /**
  446. * @}
  447. */
  448. /*******************************************************************************
  449. * Global pre-processor symbols/macros ('#define')
  450. ******************************************************************************/
  451. /**
  452. * @defgroup MCAN_Global_Macros MCAN Global Macros
  453. * @{
  454. */
  455. /**
  456. * @defgroup MCAN_Operating_Mode MCAN Operating Mode
  457. * @{
  458. */
  459. #define MCAN_MD_NORMAL (0U) /*!< Normal mode */
  460. #define MCAN_MD_RESTRICTED_OPERATION (1U) /*!< Restricted operation mode */
  461. #define MCAN_MD_BUS_MONITORING (2U) /*!< Bus monitoring mode */
  462. #define MCAN_MD_INTERNAL_LOOPBACK (3U) /*!< Internal loopBack mode */
  463. #define MCAN_MD_EXTERNAL_LOOPBACK (4U) /*!< External loopBack mode */
  464. /**
  465. * @}
  466. */
  467. /**
  468. * @defgroup MCAN_Msg_RAM_Info MCAN Message RAM Information
  469. * @{
  470. */
  471. #define MCAN_MSG_RAM_BASE (0x4002B000UL) /*!< MCAN message RAM start address */
  472. #define MCAN_MSG_RAM_SIZE (1024UL * 2UL) /*!< MCAN message RAM size */
  473. #define MCAN_MSG_RAM_END (MCAN_MSG_RAM_BASE + \
  474. MCAN_MSG_RAM_SIZE) /*!< MCAN message RAM end address */
  475. /**
  476. * @}
  477. */
  478. /**
  479. * @defgroup MCAN_ID_Type MCAN ID Type
  480. * @{
  481. */
  482. #define MCAN_STD_ID (0U) /*!< Standard ID */
  483. #define MCAN_EXT_ID (1U) /*!< Extended ID */
  484. /**
  485. * @}
  486. */
  487. /**
  488. * @defgroup MCAN_ID_Mask MCAN ID Mask
  489. * @{
  490. */
  491. #define MCAN_STD_ID_MASK (0x7FFUL) /*!< Standard ID mask */
  492. #define MCAN_EXT_ID_MASK (0x1FFFFFFFUL) /*!< Extended ID mask */
  493. /**
  494. * @}
  495. */
  496. /**
  497. * @defgroup MCAN_Frame_Format MCAN Frame Format
  498. * @{
  499. */
  500. #define MCAN_FRAME_CLASSIC (0x0U) /*!< Classic mode */
  501. #define MCAN_FRAME_FD_NO_BRS (MCAN_CCCR_FDOE) /*!< FD mode without bit rate switching */
  502. #define MCAN_FRAME_FD_BRS (MCAN_CCCR_FDOE | \
  503. MCAN_CCCR_BRSE) /*!< FD mode with bit rate switching */
  504. /**
  505. * @}
  506. */
  507. /**
  508. * @defgroup MCAN_FD_ISO_Operation MCAN FD ISO Operation
  509. * @{
  510. */
  511. #define MCAN_FD_ISO (0x0U) /*!< CAN FD frame format according to ISO 11898-1:2015 */
  512. #define MCAN_FD_NON_ISO (MCAN_CCCR_NISO) /*!< CAN FD frame format according to Bosch CAN FD Specification V1.0 */
  513. /**
  514. * @}
  515. */
  516. /**
  517. * @defgroup MCAN_Auto_Retx_Enable MCAN Automatic Retransmission Enable
  518. * @{
  519. */
  520. #define MCAN_AUTO_RETX_DISABLE (MCAN_CCCR_DAR) /*!< Disable automatic retransmission */
  521. #define MCAN_AUTO_RETX_ENABLE (0x0U) /*!< Automatic retransmission of messages not transmitted successfully */
  522. /**
  523. * @}
  524. */
  525. /**
  526. * @defgroup MCAN_Tx_Pause_Enable MCAN Tx Pause Enable
  527. * @{
  528. */
  529. #define MCAN_TX_PAUSE_DISABLE (0x0U) /*!< Disable transmit pause */
  530. #define MCAN_TX_PAUSE_ENABLE (MCAN_CCCR_TXP) /*!< Enable transmit pause */
  531. /**
  532. * @}
  533. */
  534. /**
  535. * @defgroup MCAN_Msg_Marker_Cfg MCAN Message Marker Configuration
  536. * @{
  537. */
  538. #define MCAN_MSG_MARKER_8BIT (0U) /*!< 8-bit message marker used */
  539. #define MCAN_MSG_MARKER_16BIT (MCAN_CCCR_WMM) /*!< 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO */
  540. /**
  541. * @}
  542. */
  543. /**
  544. * @defgroup MCAN_Protocol_Exception_Enable MCAN Protocol Exception Enable
  545. * @{
  546. */
  547. #define MCAN_PROTOCOL_EXCEPTION_DISABLE (MCAN_CCCR_PXHD) /*!< Disable protocol exception handling */
  548. #define MCAN_PROTOCOL_EXCEPTION_ENABLE (0x0U) /*!< Enable protocol exception handling */
  549. /**
  550. * @}
  551. */
  552. /**
  553. * @defgroup MCAN_TDC_Enable MCAN Transmitter Delay Compensation Enable
  554. * @{
  555. */
  556. #define MCAN_FD_TDC_DISABLE (0x0U) /*!< Disable transmitter delay compensation. */
  557. #define MCAN_FD_TDC_ENABLE (MCAN_DBTP_TDC) /*!< Enable transmitter delay compensation. */
  558. /**
  559. * @}
  560. */
  561. /**
  562. * @defgroup MCAN_Tx_Pin_Ctrl MCAN Tx Pin Control
  563. * @{
  564. */
  565. #define MCAN_TX_PIN_NORMAL (0U) /*!< Tx pin controlled by the CAN Core, updated at the end of the CAN bit time */
  566. #define MCAN_TX_PIN_MONITOR (MCAN_TEST_TX_0) /*!< Sample Point can be monitored at Tx pin */
  567. #define MCAN_TX_PIN_DOMINANT (MCAN_TEST_TX_1) /*!< Dominant (‘0’) level at Tx pin */
  568. #define MCAN_TX_PIN_RECESSIVE (MCAN_TEST_TX) /*!< Recessive (‘1’) level at Tx pin */
  569. /**
  570. * @}
  571. */
  572. /**
  573. * @defgroup MCAN_Data_Length_Code MCAN Data Length Code
  574. * @{
  575. */
  576. #define MCAN_DLC0 (0x0U) /*!< Classic-CAN and FD-CAN: data field size is 0 bytes. */
  577. #define MCAN_DLC1 (0x1U) /*!< Classic-CAN and FD-CAN: data field size is 1 bytes. */
  578. #define MCAN_DLC2 (0x2U) /*!< Classic-CAN and FD-CAN: data field size is 2 bytes. */
  579. #define MCAN_DLC3 (0x3U) /*!< Classic-CAN and FD-CAN: data field size is 3 bytes. */
  580. #define MCAN_DLC4 (0x4U) /*!< Classic-CAN and FD-CAN: data field size is 4 bytes. */
  581. #define MCAN_DLC5 (0x5U) /*!< Classic-CAN and FD-CAN: data field size is 5 bytes. */
  582. #define MCAN_DLC6 (0x6U) /*!< Classic-CAN and FD-CAN: data field size is 6 bytes. */
  583. #define MCAN_DLC7 (0x7U) /*!< Classic-CAN and FD-CAN: data field size is 7 bytes. */
  584. #define MCAN_DLC8 (0x8U) /*!< Classic-CAN and FD-CAN: data field size is 8 bytes. */
  585. #define MCAN_DLC12 (0x9U) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 12 bytes. */
  586. #define MCAN_DLC16 (0xAU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 16 bytes. */
  587. #define MCAN_DLC20 (0xBU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 20 bytes. */
  588. #define MCAN_DLC24 (0xCU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 24 bytes. */
  589. #define MCAN_DLC32 (0xDU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 32 bytes. */
  590. #define MCAN_DLC48 (0xEU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 48 bytes. */
  591. #define MCAN_DLC64 (0xFU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 64 bytes. */
  592. /**
  593. * @}
  594. */
  595. /**
  596. * @defgroup MCAN_Data_Field_Size MCAN Data Field Size
  597. * @{
  598. */
  599. #define MCAN_DATA_SIZE_8BYTE (0x0U) /*!< 8 bytes data field */
  600. #define MCAN_DATA_SIZE_12BYTE (0x1U) /*!< 12 bytes data field */
  601. #define MCAN_DATA_SIZE_16BYTE (0x2U) /*!< 16 bytes data field */
  602. #define MCAN_DATA_SIZE_20BYTE (0x3U) /*!< 20 bytes data field */
  603. #define MCAN_DATA_SIZE_24BYTE (0x4U) /*!< 24 bytes data field */
  604. #define MCAN_DATA_SIZE_32BYTE (0x5U) /*!< 32 bytes data field */
  605. #define MCAN_DATA_SIZE_48BYTE (0x6U) /*!< 48 bytes data field */
  606. #define MCAN_DATA_SIZE_64BYTE (0x7U) /*!< 64 bytes data field */
  607. /**
  608. * @}
  609. */
  610. /**
  611. * @defgroup MCAN_Tx_FIFO_Queue_Mode MCAN Tx FIFO/Queue Mode
  612. * @{
  613. */
  614. #define MCAN_TX_FIFO_MD (0x0U) /*!< Tx FIFO operation mode */
  615. #define MCAN_TX_QUEUE_MD (MCAN_TXBC_TFQM) /*!< Tx Queue operation mode */
  616. /**
  617. * @}
  618. */
  619. /**
  620. * @defgroup MCAN_Filter_Type MCAN Filter Type
  621. * @{
  622. */
  623. #define MCAN_FILTER_RANGE (0x0U) /*!< Range filter from filter ID1 to filter ID2 */
  624. #define MCAN_FILTER_DUAL (0x1U) /*!< Dual ID filter for filter ID1 or filter ID2 */
  625. #define MCAN_FILTER_MASK (0x2U) /*!< Classic filter: filter ID1 = filter, filter ID2 = mask */
  626. #define MCAN_FILTER_RANGE_NO_EIDM (0x3U) /*!< Range filter from filter ID1 to filter ID2, EIDM mask not applied */
  627. /**
  628. * @}
  629. */
  630. /**
  631. * @defgroup MCAN_Filter_Config MCAN Filter Configuration
  632. * @{
  633. */
  634. #define MCAN_FILTER_DISABLE (0x0U) /*!< Disable filter element */
  635. #define MCAN_FILTER_TO_RX_FIFO0 (0x1U) /*!< Store in Rx FIFO 0 if filter matches */
  636. #define MCAN_FILTER_TO_RX_FIFO1 (0x2U) /*!< Store in Rx FIFO 1 if filter matches */
  637. #define MCAN_FILTER_REJECT (0x3U) /*!< Reject ID if filter matches */
  638. #define MCAN_FILTER_HP_NO_STORAGE (0x4U) /*!< Set high priority if filter matches, no storage */
  639. #define MCAN_FILTER_HP_TO_RX_FIFO0 (0x5U) /*!< Set high priority and store in FIFO 0 if filter matches */
  640. #define MCAN_FILTER_HP_TO_RX_FIFO1 (0x6U) /*!< Set high priority and store in FIFO 1 if filter matches */
  641. #define MCAN_FILTER_TO_RX_BUF (0x7U) /*!< Store into Rx buffer, configuration of @ref MCAN_Filter_Type ignored */
  642. /**
  643. * @}
  644. */
  645. /**
  646. * @defgroup MCAN_Tx_Location MCAN Tx Location
  647. * @{
  648. */
  649. #define MCAN_TX_BUF0 (0x1UL << 0U) /*!< Add message to Tx buffer 0 */
  650. #define MCAN_TX_BUF1 (0x1UL << 1U) /*!< Add message to Tx buffer 1 */
  651. #define MCAN_TX_BUF2 (0x1UL << 2U) /*!< Add message to Tx buffer 2 */
  652. #define MCAN_TX_BUF3 (0x1UL << 3U) /*!< Add message to Tx buffer 3 */
  653. #define MCAN_TX_BUF4 (0x1UL << 4U) /*!< Add message to Tx buffer 4 */
  654. #define MCAN_TX_BUF5 (0x1UL << 5U) /*!< Add message to Tx buffer 5 */
  655. #define MCAN_TX_BUF6 (0x1UL << 6U) /*!< Add message to Tx buffer 6 */
  656. #define MCAN_TX_BUF7 (0x1UL << 7U) /*!< Add message to Tx buffer 7 */
  657. #define MCAN_TX_BUF8 (0x1UL << 8U) /*!< Add message to Tx buffer 8 */
  658. #define MCAN_TX_BUF9 (0x1UL << 9U) /*!< Add message to Tx buffer 9 */
  659. #define MCAN_TX_BUF10 (0x1UL << 10U) /*!< Add message to Tx buffer 10 */
  660. #define MCAN_TX_BUF11 (0x1UL << 11U) /*!< Add message to Tx buffer 11 */
  661. #define MCAN_TX_BUF12 (0x1UL << 12U) /*!< Add message to Tx buffer 12 */
  662. #define MCAN_TX_BUF13 (0x1UL << 13U) /*!< Add message to Tx buffer 13 */
  663. #define MCAN_TX_BUF14 (0x1UL << 14U) /*!< Add message to Tx buffer 14 */
  664. #define MCAN_TX_BUF15 (0x1UL << 15U) /*!< Add message to Tx buffer 15 */
  665. #define MCAN_TX_BUF16 (0x1UL << 16U) /*!< Add message to Tx buffer 16 */
  666. #define MCAN_TX_BUF17 (0x1UL << 17U) /*!< Add message to Tx buffer 17 */
  667. #define MCAN_TX_BUF18 (0x1UL << 18U) /*!< Add message to Tx buffer 18 */
  668. #define MCAN_TX_BUF19 (0x1UL << 19U) /*!< Add message to Tx buffer 19 */
  669. #define MCAN_TX_BUF20 (0x1UL << 20U) /*!< Add message to Tx buffer 20 */
  670. #define MCAN_TX_BUF21 (0x1UL << 21U) /*!< Add message to Tx buffer 21 */
  671. #define MCAN_TX_BUF22 (0x1UL << 22U) /*!< Add message to Tx buffer 22 */
  672. #define MCAN_TX_BUF23 (0x1UL << 23U) /*!< Add message to Tx buffer 23 */
  673. #define MCAN_TX_BUF24 (0x1UL << 24U) /*!< Add message to Tx buffer 24 */
  674. #define MCAN_TX_BUF25 (0x1UL << 25U) /*!< Add message to Tx buffer 25 */
  675. #define MCAN_TX_BUF26 (0x1UL << 26U) /*!< Add message to Tx buffer 26 */
  676. #define MCAN_TX_BUF27 (0x1UL << 27U) /*!< Add message to Tx buffer 27 */
  677. #define MCAN_TX_BUF28 (0x1UL << 28U) /*!< Add message to Tx buffer 28 */
  678. #define MCAN_TX_BUF29 (0x1UL << 29U) /*!< Add message to Tx buffer 29 */
  679. #define MCAN_TX_BUF30 (0x1UL << 30U) /*!< Add message to Tx buffer 30 */
  680. #define MCAN_TX_BUF31 (0x1UL << 31U) /*!< Add message to Tx buffer 31 */
  681. #define MCAN_TX_BUF_ALL (0xFFFFFFFFUL)
  682. /**
  683. * @}
  684. */
  685. /**
  686. * @defgroup MCAN_Rx_Location MCAN Rx Location
  687. * @{
  688. */
  689. #define MCAN_RX_FIFO0 (0x40U) /*!< Get received message from Rx FIFO 0 */
  690. #define MCAN_RX_FIFO1 (0x41U) /*!< Get received message from Rx FIFO 1 */
  691. #define MCAN_RX_BUF0 (0x00U) /*!< Get received message from Rx buffer 0 */
  692. #define MCAN_RX_BUF1 (0x01U) /*!< Get received message from Rx buffer 1 */
  693. #define MCAN_RX_BUF2 (0x02U) /*!< Get received message from Rx buffer 2 */
  694. #define MCAN_RX_BUF3 (0x03U) /*!< Get received message from Rx buffer 3 */
  695. #define MCAN_RX_BUF4 (0x04U) /*!< Get received message from Rx buffer 4 */
  696. #define MCAN_RX_BUF5 (0x05U) /*!< Get received message from Rx buffer 5 */
  697. #define MCAN_RX_BUF6 (0x06U) /*!< Get received message from Rx buffer 6 */
  698. #define MCAN_RX_BUF7 (0x07U) /*!< Get received message from Rx buffer 7 */
  699. #define MCAN_RX_BUF8 (0x08U) /*!< Get received message from Rx buffer 8 */
  700. #define MCAN_RX_BUF9 (0x09U) /*!< Get received message from Rx buffer 9 */
  701. #define MCAN_RX_BUF10 (0x0AU) /*!< Get received message from Rx buffer 10 */
  702. #define MCAN_RX_BUF11 (0x0BU) /*!< Get received message from Rx buffer 11 */
  703. #define MCAN_RX_BUF12 (0x0CU) /*!< Get received message from Rx buffer 12 */
  704. #define MCAN_RX_BUF13 (0x0DU) /*!< Get received message from Rx buffer 13 */
  705. #define MCAN_RX_BUF14 (0x0EU) /*!< Get received message from Rx buffer 14 */
  706. #define MCAN_RX_BUF15 (0x0FU) /*!< Get received message from Rx buffer 15 */
  707. #define MCAN_RX_BUF16 (0x10U) /*!< Get received message from Rx buffer 16 */
  708. #define MCAN_RX_BUF17 (0x11U) /*!< Get received message from Rx buffer 17 */
  709. #define MCAN_RX_BUF18 (0x12U) /*!< Get received message from Rx buffer 18 */
  710. #define MCAN_RX_BUF19 (0x13U) /*!< Get received message from Rx buffer 19 */
  711. #define MCAN_RX_BUF20 (0x14U) /*!< Get received message from Rx buffer 20 */
  712. #define MCAN_RX_BUF21 (0x15U) /*!< Get received message from Rx buffer 21 */
  713. #define MCAN_RX_BUF22 (0x16U) /*!< Get received message from Rx buffer 22 */
  714. #define MCAN_RX_BUF23 (0x17U) /*!< Get received message from Rx buffer 23 */
  715. #define MCAN_RX_BUF24 (0x18U) /*!< Get received message from Rx buffer 24 */
  716. #define MCAN_RX_BUF25 (0x19U) /*!< Get received message from Rx buffer 25 */
  717. #define MCAN_RX_BUF26 (0x1AU) /*!< Get received message from Rx buffer 26 */
  718. #define MCAN_RX_BUF27 (0x1BU) /*!< Get received message from Rx buffer 27 */
  719. #define MCAN_RX_BUF28 (0x1CU) /*!< Get received message from Rx buffer 28 */
  720. #define MCAN_RX_BUF29 (0x1DU) /*!< Get received message from Rx buffer 29 */
  721. #define MCAN_RX_BUF30 (0x1EU) /*!< Get received message from Rx buffer 30 */
  722. #define MCAN_RX_BUF31 (0x1FU) /*!< Get received message from Rx buffer 31 */
  723. #define MCAN_RX_BUF32 (0x20U) /*!< Get received message from Rx buffer 32 */
  724. #define MCAN_RX_BUF33 (0x21U) /*!< Get received message from Rx buffer 33 */
  725. #define MCAN_RX_BUF34 (0x22U) /*!< Get received message from Rx buffer 34 */
  726. #define MCAN_RX_BUF35 (0x23U) /*!< Get received message from Rx buffer 35 */
  727. #define MCAN_RX_BUF36 (0x24U) /*!< Get received message from Rx buffer 36 */
  728. #define MCAN_RX_BUF37 (0x25U) /*!< Get received message from Rx buffer 37 */
  729. #define MCAN_RX_BUF38 (0x26U) /*!< Get received message from Rx buffer 38 */
  730. #define MCAN_RX_BUF39 (0x27U) /*!< Get received message from Rx buffer 39 */
  731. #define MCAN_RX_BUF40 (0x28U) /*!< Get received message from Rx buffer 40 */
  732. #define MCAN_RX_BUF41 (0x29U) /*!< Get received message from Rx buffer 41 */
  733. #define MCAN_RX_BUF42 (0x2AU) /*!< Get received message from Rx buffer 42 */
  734. #define MCAN_RX_BUF43 (0x2BU) /*!< Get received message from Rx buffer 43 */
  735. #define MCAN_RX_BUF44 (0x2CU) /*!< Get received message from Rx buffer 44 */
  736. #define MCAN_RX_BUF45 (0x2DU) /*!< Get received message from Rx buffer 45 */
  737. #define MCAN_RX_BUF46 (0x2EU) /*!< Get received message from Rx buffer 46 */
  738. #define MCAN_RX_BUF47 (0x2FU) /*!< Get received message from Rx buffer 47 */
  739. #define MCAN_RX_BUF48 (0x30U) /*!< Get received message from Rx buffer 48 */
  740. #define MCAN_RX_BUF49 (0x31U) /*!< Get received message from Rx buffer 49 */
  741. #define MCAN_RX_BUF50 (0x32U) /*!< Get received message from Rx buffer 50 */
  742. #define MCAN_RX_BUF51 (0x33U) /*!< Get received message from Rx buffer 51 */
  743. #define MCAN_RX_BUF52 (0x34U) /*!< Get received message from Rx buffer 52 */
  744. #define MCAN_RX_BUF53 (0x35U) /*!< Get received message from Rx buffer 53 */
  745. #define MCAN_RX_BUF54 (0x36U) /*!< Get received message from Rx buffer 54 */
  746. #define MCAN_RX_BUF55 (0x37U) /*!< Get received message from Rx buffer 55 */
  747. #define MCAN_RX_BUF56 (0x38U) /*!< Get received message from Rx buffer 56 */
  748. #define MCAN_RX_BUF57 (0x39U) /*!< Get received message from Rx buffer 57 */
  749. #define MCAN_RX_BUF58 (0x3AU) /*!< Get received message from Rx buffer 58 */
  750. #define MCAN_RX_BUF59 (0x3BU) /*!< Get received message from Rx buffer 59 */
  751. #define MCAN_RX_BUF60 (0x3CU) /*!< Get received message from Rx buffer 60 */
  752. #define MCAN_RX_BUF61 (0x3DU) /*!< Get received message from Rx buffer 61 */
  753. #define MCAN_RX_BUF62 (0x3EU) /*!< Get received message from Rx buffer 62 */
  754. #define MCAN_RX_BUF63 (0x3FU) /*!< Get received message from Rx buffer 63 */
  755. #define MCAN_RX_BUF_MAX MCAN_RX_BUF63
  756. /**
  757. * @}
  758. */
  759. /**
  760. * @defgroup MCAN_HPM_Storage MCAN High Priority Message Storage
  761. * @{
  762. */
  763. #define MCAN_HPM_NO_STORAGE (0x00U) /*!< No FIFO selected */
  764. #define MCAN_HPM_LOST (0x40U) /*!< FIFO message lost */
  765. #define MCAN_HPM_STORED_IN_RX_FIFO0 (0x80U) /*!< Message stored in FIFO 0 */
  766. #define MCAN_HPM_STORED_IN_RX_FIFO1 (0xC0U) /*!< Message stored in FIFO 1 */
  767. /**
  768. * @}
  769. */
  770. /**
  771. * @defgroup MCAN_Protocol_Error_Code MCAN Protocol Error Code
  772. * @{
  773. */
  774. #define MCAN_PROTOCOL_NONE_ERR (0x0U) /*!< No error occurred */
  775. #define MCAN_PROTOCOL_STUFF_ERR (0x1U) /*!< Stuff error */
  776. #define MCAN_PROTOCOL_FORM_ERR (0x2U) /*!< Form error */
  777. #define MCAN_PROTOCOL_ACK_ERR (0x3U) /*!< Acknowledge error */
  778. #define MCAN_PROTOCOL_BIT1_ERR (0x4U) /*!< Bit 1 (recessive) error */
  779. #define MCAN_PROTOCOL_BIT0_ERR (0x5U) /*!< Bit 0 (dominant) error */
  780. #define MCAN_PROTOCOL_CRC_ERR (0x6U) /*!< CRC check sum error */
  781. #define MCAN_PROTOCOL_ERR_NO_CHANGE (0x7U) /*!< No change since last read */
  782. /**
  783. * @}
  784. */
  785. /**
  786. * @defgroup MCAN_Comm_State MCAN Communication State
  787. * @{
  788. */
  789. #define MCAN_COMM_STATE_SYNC (0x00U) /*!< Node is synchronizing on CAN communication */
  790. #define MCAN_COMM_STATE_IDLE (0x08U) /*!< Node is neither receiver nor transmitter */
  791. #define MCAN_COMM_STATE_RX (0x10U) /*!< Node is operating as receiver */
  792. #define MCAN_COMM_STATE_TX (0x18U) /*!< Node is operating as transmitter */
  793. /**
  794. * @}
  795. */
  796. /**
  797. * @defgroup MCAN_Watermark_Fifo MCAN Watermark FIFO
  798. * @{
  799. */
  800. #define MCAN_WATERMARK_RX_FIFO0 (0x0U) /*!< Rx FIFO0 */
  801. #define MCAN_WATERMARK_RX_FIFO1 (0x1U) /*!< Rx FIFO1 */
  802. #define MCAN_WATERMARK_TX_EVT_FIFO (0x2U) /*!< Tx event FIFO */
  803. /**
  804. * @}
  805. */
  806. /**
  807. * @defgroup MCAN_Rx_Fifo_Operation_Mode MCAN FIFO Operation Mode
  808. * @{
  809. */
  810. #define MCAN_RX_FIFO_BLOCKING (0x0U) /*!< Rx FIFO blocking mode.
  811. New received message will be discarded. */
  812. #define MCAN_RX_FIFO_OVERWRITE (MCAN_RXF0C_F0OM) /*!< Rx FIFO overwrite mode.
  813. New received message will overwrite the oldest received message. */
  814. /**
  815. * @}
  816. */
  817. /**
  818. * @defgroup MCAN_NMF_Operation MCAN Non-matching Frame Operation
  819. * @{
  820. */
  821. #define MCAN_NMF_ACCEPT_IN_RX_FIFO0 (0x0U) /*!< Accept in Rx FIFO 0 */
  822. #define MCAN_NMF_ACCEPT_IN_RX_FIFO1 (0x1U) /*!< Accept in Rx FIFO 1 */
  823. #define MCAN_NMF_REJECT (0x2U) /*!< Reject all non-matching frames */
  824. /**
  825. * @}
  826. */
  827. /**
  828. * @defgroup MCAN_Remote_Frame_Operation MCAN Remote Frame Operation
  829. * @{
  830. */
  831. #define MCAN_REMOTE_FRAME_FILTER (0x0U) /*!< Filter remote frames with ID */
  832. #define MCAN_REMOTE_FRAME_REJECT (0x1U) /*!< Reject all remote frames */
  833. /**
  834. * @}
  835. */
  836. /**
  837. * @defgroup MCAN_Interrupt_Line MCAN Interrupt Line
  838. * @{
  839. */
  840. #define MCAN_INT_LINE0 (0x1U) /*!< Interrupt line 0 */
  841. #define MCAN_INT_LINE1 (0x2U) /*!< Interrupt line 1 */
  842. /**
  843. * @}
  844. */
  845. /**
  846. * @defgroup MCAN_Timeout_Select MCAN Timeout Select
  847. * @{
  848. */
  849. #define MCAN_TIMEOUT_CONTINUOUS (0x0U) /*!< Timeout continuous operation */
  850. #define MCAN_TIMEOUT_TX_EVT_FIFO (MCAN_TOCC_TOS_0) /*!< Timeout controlled by Tx event FIFO */
  851. #define MCAN_TIMEOUT_RX_FIFO0 (MCAN_TOCC_TOS_1) /*!< Timeout controlled by Rx FIFO0 */
  852. #define MCAN_TIMEOUT_RX_FIFO1 (MCAN_TOCC_TOS) /*!< Timeout controlled by Rx FIFO1 */
  853. /**
  854. * @}
  855. */
  856. /**
  857. * @defgroup MCAN_Interrupt MCAN Interrupt
  858. * @{
  859. */
  860. #define MCAN_INT_RX_FIFO0_NEW_MSG (MCAN_IE_RF0NE) /*!< New message written to Rx FIFO 0 */
  861. #define MCAN_INT_RX_FIFO0_WATERMARK (MCAN_IE_RF0WE) /*!< Rx FIFO 0 fill level reached watermark */
  862. #define MCAN_INT_RX_FIFO0_FULL (MCAN_IE_RF0FE) /*!< Rx FIFO 0 full */
  863. #define MCAN_INT_RX_FIFO0_MSG_LOST (MCAN_IE_RF0LE) /*!< Rx FIFO 0 message lost */
  864. #define MCAN_INT_RX_FIFO1_NEW_MSG (MCAN_IE_RF1NE) /*!< New message written to Rx FIFO 1 */
  865. #define MCAN_INT_RX_FIFO1_WATERMARK (MCAN_IE_RF1WE) /*!< Rx FIFO 1 fill level reached watermark */
  866. #define MCAN_INT_RX_FIFO1_FULL (MCAN_IE_RF1FE) /*!< Rx FIFO 1 full */
  867. #define MCAN_INT_RX_FIFO1_MSG_LOST (MCAN_IE_RF1LE) /*!< Rx FIFO 1 message lost */
  868. #define MCAN_INT_RX_HPM (MCAN_IE_HPME) /*!< High priority message received */
  869. #define MCAN_INT_TX_CPLT (MCAN_IE_TCE) /*!< Transmission completed */
  870. #define MCAN_INT_TX_ABORT_CPLT (MCAN_IE_TCFE) /*!< Transmission cancellation finished */
  871. #define MCAN_INT_TX_FIFO_EMPTY (MCAN_IE_TFEE) /*!< Tx FIFO empty */
  872. #define MCAN_INT_TX_EVT_FIFO_NEW_DATA (MCAN_IE_TEFNE) /*!< Tx handler wrote Tx event FIFO element */
  873. #define MCAN_INT_TX_EVT_FIFO_WATERMARK (MCAN_IE_TEFWE) /*!< Tx event FIFO fill level reached watermark */
  874. #define MCAN_INT_TX_EVT_FIFO_FULL (MCAN_IE_TEFFE) /*!< Tx event FIFO full */
  875. #define MCAN_INT_TX_EVT_FIFO_LOST (MCAN_IE_TEFLE) /*!< Tx event FIFO element lost */
  876. #define MCAN_INT_TIMESTAMP_WRAPAROUND (MCAN_IE_TSWE) /*!< Timestamp counter wrapped around */
  877. #define MCAN_INT_RAM_ACCESS_FAILURE (MCAN_IE_MRAFE) /*!< Message RAM access failure occurred */
  878. #define MCAN_INT_TIMEOUT (MCAN_IE_TOOE) /*!< Timeout reached */
  879. #define MCAN_INT_RX_BUF_NEW_MSG (MCAN_IE_DRXE) /*!< At least one received message stored into a Rx buffer */
  880. #define MCAN_INT_BEC (MCAN_IE_BECE) /*!< Bit error detected and corrected (e.g. ECC) */
  881. #define MCAN_INT_BEU (MCAN_IE_BEUE) /*!< Bit error detected, uncorrected (e.g. parity logic) */
  882. #define MCAN_INT_ERR_LOG_OVF (MCAN_IE_ELOE) /*!< Overflow of CAN error logging counter occurred */
  883. #define MCAN_INT_ERR_PASSIVE (MCAN_IE_EPE) /*!< Error_Passive status changed */
  884. #define MCAN_INT_ERR_WARNING (MCAN_IE_EWE) /*!< Error_Warning status changed */
  885. #define MCAN_INT_BUS_OFF (MCAN_IE_BOE) /*!< Bus_Off status changed */
  886. #define MCAN_INT_RAM_WATCHDOG (MCAN_IE_WDIE) /*!< Message RAM Watchdog event due to missing READY */
  887. #define MCAN_INT_ARB_PHASE_ERROR (MCAN_IE_PEAE) /*!< Protocol error in arbitration phase detected */
  888. #define MCAN_INT_DATA_PHASE_ERROR (MCAN_IE_PEDE) /*!< Protocol error in data phase detected */
  889. #define MCAN_INT_RSVD_ADDR_ACCESS (MCAN_IE_ARAE) /*!< Access to reserved address occurred */
  890. #define MCAN_INT_ALL (0x3FFFFFFFUL)
  891. /**
  892. * @}
  893. */
  894. /**
  895. * @defgroup MCAN_Interrupt_Flag MCAN Interrupt Flag
  896. * @{
  897. */
  898. #define MCAN_FLAG_RX_FIFO0_NEW_MSG (MCAN_IR_RF0N) /*!< New message written to Rx FIFO 0 */
  899. #define MCAN_FLAG_RX_FIFO0_WATERMARK (MCAN_IR_RF0W) /*!< Rx FIFO 0 fill level reached watermark */
  900. #define MCAN_FLAG_RX_FIFO0_FULL (MCAN_IR_RF0F) /*!< Rx FIFO 0 full */
  901. #define MCAN_FLAG_RX_FIFO0_MSG_LOST (MCAN_IR_RF0L) /*!< Rx FIFO 0 message lost */
  902. #define MCAN_FLAG_RX_FIFO1_NEW_MSG (MCAN_IR_RF1N) /*!< New message written to Rx FIFO 1 */
  903. #define MCAN_FLAG_RX_FIFO1_WATERMARK (MCAN_IR_RF1W) /*!< Rx FIFO 1 fill level reached watermark */
  904. #define MCAN_FLAG_RX_FIFO1_FULL (MCAN_IR_RF1F) /*!< Rx FIFO 1 full */
  905. #define MCAN_FLAG_RX_FIFO1_MSG_LOST (MCAN_IR_RF1L) /*!< Rx FIFO 1 message lost */
  906. #define MCAN_FLAG_RX_HPM (MCAN_IR_HPM) /*!< High priority message received */
  907. #define MCAN_FLAG_TX_CPLT (MCAN_IR_TC) /*!< Transmission completed */
  908. #define MCAN_FLAG_TX_ABORT_CPLT (MCAN_IR_TCF) /*!< Transmission cancellation finished */
  909. #define MCAN_FLAG_TX_FIFO_EMPTY (MCAN_IR_TFE) /*!< Tx FIFO empty */
  910. #define MCAN_FLAG_TX_EVT_FIFO_NEW_DATA (MCAN_IR_TEFN) /*!< Tx handler wrote Tx event FIFO element */
  911. #define MCAN_FLAG_TX_EVT_FIFO_WATERMARK (MCAN_IR_TEFW) /*!< Tx event FIFO fill level reached watermark */
  912. #define MCAN_FLAG_TX_EVT_FIFO_FULL (MCAN_IR_TEFF) /*!< Tx event FIFO full */
  913. #define MCAN_FLAG_TX_EVT_FIFO_LOST (MCAN_IR_TEFL) /*!< Tx event FIFO element lost */
  914. #define MCAN_FLAG_TIMESTAMP_WRAPAROUND (MCAN_IR_TSW) /*!< Timestamp counter wrapped around */
  915. #define MCAN_FLAG_RAM_ACCESS_FAILURE (MCAN_IR_MRAF) /*!< Message RAM access failure occurred */
  916. #define MCAN_FLAG_TIMEOUT (MCAN_IR_TOO) /*!< Timeout reached */
  917. #define MCAN_FLAG_RX_BUF_NEW_MSG (MCAN_IR_DRX) /*!< At least one received message stored into a Rx buffer */
  918. #define MCAN_FLAG_BEC (MCAN_IR_BEC) /*!< Bit error detected and corrected (e.g. ECC) */
  919. #define MCAN_FLAG_BEU (MCAN_IR_BEU) /*!< Bit error detected, uncorrected (e.g. parity logic) */
  920. #define MCAN_FLAG_ERR_LOG_OVF (MCAN_IR_ELO) /*!< Overflow of CAN error logging counter occurred */
  921. #define MCAN_FLAG_ERR_PASSIVE (MCAN_IR_EP) /*!< Error_Passive status changed */
  922. #define MCAN_FLAG_ERR_WARNING (MCAN_IR_EW) /*!< Error_Warning status changed */
  923. #define MCAN_FLAG_BUS_OFF (MCAN_IR_BO) /*!< Bus_Off status changed */
  924. #define MCAN_FLAG_RAM_WATCHDOG (MCAN_IR_WDI) /*!< Message RAM Watchdog event due to missing READY */
  925. #define MCAN_FLAG_ARB_PHASE_ERROR (MCAN_IR_PEA) /*!< Protocol error in arbitration phase detected */
  926. #define MCAN_FLAG_DATA_PHASE_ERROR (MCAN_IR_PED) /*!< Protocol error in data phase detected */
  927. #define MCAN_FLAG_RSVD_ADDR_ACCESS (MCAN_IR_ARA) /*!< Access to reserved address occurred */
  928. #define MCAN_FLAG_ALL (0x3FFFFFFFUL)
  929. /**
  930. * @}
  931. */
  932. /**
  933. * @defgroup MCAN_Evt_Type MCAN Event Type
  934. * @{
  935. */
  936. #define MCAN_EVT_TX_EVT (0x01U) /*!< Tx event */
  937. #define MCAN_EVT_TX_WHEN_ABORTED (0x02U) /*!< Transmission in spite of cancellation (always set for transmissions in DAR mode) */
  938. /**
  939. * @}
  940. */
  941. /**
  942. * @}
  943. */
  944. /*******************************************************************************
  945. * Global variable definitions ('extern')
  946. ******************************************************************************/
  947. /*******************************************************************************
  948. Global function prototypes (definition in C source)
  949. ******************************************************************************/
  950. /**
  951. * @addtogroup MCAN_Global_Functions
  952. * @{
  953. */
  954. /* Initialization and de-initialization functions *****************************/
  955. int32_t MCAN_Init(CM_MCAN_TypeDef *MCANx, stc_mcan_init_t *pstcMcanInit);
  956. int32_t MCAN_StructInit(stc_mcan_init_t *pstcMcanInit);
  957. void MCAN_DeInit(CM_MCAN_TypeDef *MCANx);
  958. void MCAN_Start(CM_MCAN_TypeDef *MCANx);
  959. int32_t MCAN_Stop(CM_MCAN_TypeDef *MCANx);
  960. int32_t MCAN_EnterSleepMode(CM_MCAN_TypeDef *MCANx);
  961. int32_t MCAN_ExitSleepMode(CM_MCAN_TypeDef *MCANx);
  962. int32_t MCAN_GetMsgRamAddr(const CM_MCAN_TypeDef *MCANx, stc_mcan_msg_ram_addr_t *pstcAddr);
  963. /* Configuration functions ****************************************************/
  964. int32_t MCAN_FilterConfig(CM_MCAN_TypeDef *MCANx, stc_mcan_filter_t *pstcFilter);
  965. void MCAN_GlobalFilterConfig(CM_MCAN_TypeDef *MCANx, \
  966. uint32_t u32StdNmfOperation, uint32_t u32ExtNmfOperation, \
  967. uint32_t u32StdRemoteOperation, uint32_t u32ExtRemoteOperation);
  968. void MCAN_SetExtIDMask(CM_MCAN_TypeDef *MCANx, uint32_t u32Mask);
  969. void MCAN_RxFifoOperationModeConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo, uint32_t u32OperationMode);
  970. void MCAN_SetFifoWatermark(CM_MCAN_TypeDef *MCANx, uint32_t u32Fifo, uint32_t u32Watermark);
  971. void MCAN_RamWatchdogConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32StartValue);
  972. uint8_t MCAN_GetRamWatchdogCountValue(const CM_MCAN_TypeDef *MCANx);
  973. void MCAN_TimestampCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32TsPrescaler);
  974. void MCAN_TimestampCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState);
  975. uint16_t MCAN_GetTimestampCounter(const CM_MCAN_TypeDef *MCANx);
  976. void MCAN_ResetTimestampCounter(CM_MCAN_TypeDef *MCANx);
  977. void MCAN_TimeoutCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32ToSelect, uint32_t u32ToPeriod);
  978. void MCAN_TimeoutCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState);
  979. uint16_t MCAN_GetTimeoutCounter(const CM_MCAN_TypeDef *MCANx);
  980. void MCAN_ResetTimeoutCounter(CM_MCAN_TypeDef *MCANx);
  981. void MCAN_TxDelayCompensationConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32SspOffset, uint32_t u32TdcFilter);
  982. void MCAN_TxDelayCompensationCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState);
  983. void MCAN_SetFdIsoOperation(CM_MCAN_TypeDef *MCANx, uint32_t u32FdIsoOperation);
  984. void MCAN_EdgeFilteringCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState);
  985. void MCAN_TxEventMsgMarkerConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32MsgMarker);
  986. /* Control functions **********************************************************/
  987. int32_t MCAN_AddMsgToTxFifoQueue(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg);
  988. int32_t MCAN_AddMsgToTxBuffer(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg);
  989. void MCAN_EnableTxBufferRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer);
  990. void MCAN_AbortTxRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer);
  991. int32_t MCAN_GetRxMsg(CM_MCAN_TypeDef *MCANx, uint32_t u32RxLocation, stc_mcan_rx_msg_t *pRxMsg);
  992. int32_t MCAN_GetTxEvent(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_event_t *pTxEvent);
  993. int32_t MCAN_GetHighPriorityMsgStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_hpm_status_t *pHpmStatus);
  994. int32_t MCAN_GetProtocolStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_protocol_status_t *pProtocolStatus);
  995. int32_t MCAN_GetErrorCounter(const CM_MCAN_TypeDef *MCANx, stc_mcan_error_counter_t *pErrorCounter);
  996. en_flag_status_t MCAN_GetStatus(const CM_MCAN_TypeDef *MCANx, uint32_t u32Flag);
  997. void MCAN_ClearStatus(CM_MCAN_TypeDef *MCANx, uint32_t u32Flag);
  998. uint32_t MCAN_GetTxOccurredList(const CM_MCAN_TypeDef *MCANx);
  999. uint32_t MCAN_GetTxAbortedList(const CM_MCAN_TypeDef *MCANx);
  1000. int32_t MCAN_CheckTxOccurred(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer);
  1001. int32_t MCAN_CheckTxAborted(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer);
  1002. int32_t MCAN_CheckRxBufferMsgAvailable(CM_MCAN_TypeDef *MCANx, uint32_t u32RxBufferIndex);
  1003. int32_t MCAN_CheckTxBufferPending(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer);
  1004. uint32_t MCAN_GetRxFifoFillLevel(const CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo);
  1005. uint32_t MCAN_GetTxFifoFreeLevel(const CM_MCAN_TypeDef *MCANx);
  1006. int32_t MCAN_CheckRestrictedOperationMode(const CM_MCAN_TypeDef *MCANx);
  1007. void MCAN_ExitRestrictedOperationMode(CM_MCAN_TypeDef *MCANx);
  1008. uint8_t MCAN_GetStartedTxBufferNum(const CM_MCAN_TypeDef *MCANx);
  1009. uint8_t MCAN_GetPreparedTxBufferNum(const CM_MCAN_TypeDef *MCANx);
  1010. uint8_t MCAN_GetBusLogicalState(const CM_MCAN_TypeDef *MCANx);
  1011. void MCAN_TxPinControl(CM_MCAN_TypeDef *MCANx, uint32_t u32PinCtrl);
  1012. /* Interrupts management ******************************************************/
  1013. void MCAN_IntCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32IntType, uint32_t u32IntLine, \
  1014. en_functional_state_t enNewState);
  1015. void MCAN_TxBufferNotificationCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer, \
  1016. uint32_t u32Notification, en_functional_state_t enNewState);
  1017. /**
  1018. * @}
  1019. */
  1020. #endif /* LL_MCAN_ENABLE */
  1021. /**
  1022. * @}
  1023. */
  1024. /**
  1025. * @}
  1026. */
  1027. #ifdef __cplusplus
  1028. }
  1029. #endif
  1030. #endif /* __HC32_LL_MCAN_H__ */
  1031. /*******************************************************************************
  1032. * EOF (not truncated)
  1033. ******************************************************************************/