/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _PMIC_EIC_H_
#define _PMIC_EIC_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_PMIC_EIC_BASE (0x51108500)

typedef volatile struct
{
    uint32_t eic_dbnc_data;   // 0x00000000
    uint32_t eic_dbnc_dmsk;   // 0x00000004
    uint32_t __8[3];          // 0x00000008
    uint32_t eic_dbnc_iev;    // 0x00000014
    uint32_t eic_dbnc_ie;     // 0x00000018
    uint32_t eic_dbnc_ris;    // 0x0000001c
    uint32_t eic_dbnc_mis;    // 0x00000020
    uint32_t eic_dbnc_ic;     // 0x00000024
    uint32_t eic_dbnc_trig;   // 0x00000028
    uint32_t __44[5];         // 0x0000002c
    uint32_t eic0_dbnc_ctrl;  // 0x00000040
    uint32_t eic1_dbnc_ctrl;  // 0x00000044
    uint32_t eic2_dbnc_ctrl;  // 0x00000048
    uint32_t eic3_dbnc_ctrl;  // 0x0000004c
    uint32_t eic4_dbnc_ctrl;  // 0x00000050
    uint32_t eic5_dbnc_ctrl;  // 0x00000054
    uint32_t eic6_dbnc_ctrl;  // 0x00000058
    uint32_t eic7_dbnc_ctrl;  // 0x0000005c
    uint32_t eic8_dbnc_ctrl;  // 0x00000060
    uint32_t eic9_dbnc_ctrl;  // 0x00000064
    uint32_t eic10_dbnc_ctrl; // 0x00000068
    uint32_t eic11_dbnc_ctrl; // 0x0000006c
    uint32_t eic12_dbnc_ctrl; // 0x00000070
    uint32_t eic13_dbnc_ctrl; // 0x00000074
    uint32_t eic14_dbnc_ctrl; // 0x00000078
    uint32_t eic15_dbnc_ctrl; // 0x0000007c
} HWP_PMIC_EIC_T;

#define hwp_pmicEic ((HWP_PMIC_EIC_T *)REG_ACCESS_ADDRESS(REG_PMIC_EIC_BASE))

// eic_dbnc_data
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_data : 16; // [15:0], read only
        uint32_t __31_16 : 16;   // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_DATA_T;

// eic_dbnc_dmsk
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_dmsk : 16; // [15:0]
        uint32_t __31_16 : 16;   // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_DMSK_T;

// eic_dbnc_iev
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_iev : 16; // [15:0]
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_IEV_T;

// eic_dbnc_ie
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_ie : 16; // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_IE_T;

// eic_dbnc_ris
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_ris : 16; // [15:0], read only
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_RIS_T;

// eic_dbnc_mis
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_mis : 16; // [15:0], read only
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_MIS_T;

// eic_dbnc_ic
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_ic : 16; // [15:0], write clear
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_IC_T;

// eic_dbnc_trig
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_trig : 16; // [15:0]
        uint32_t __31_16 : 16;   // [31:16]
    } b;
} REG_PMIC_EIC_EIC_DBNC_TRIG_T;

// eic0_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt0 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en0 : 1;        // [14]
        uint32_t force_clk_dbnc0 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC0_DBNC_CTRL_T;

// eic1_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt1 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en1 : 1;        // [14]
        uint32_t force_clk_dbnc1 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC1_DBNC_CTRL_T;

// eic2_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt2 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en2 : 1;        // [14]
        uint32_t force_clk_dbnc2 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC2_DBNC_CTRL_T;

// eic3_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt3 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en3 : 1;        // [14]
        uint32_t force_clk_dbnc3 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC3_DBNC_CTRL_T;

// eic4_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt4 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en4 : 1;        // [14]
        uint32_t force_clk_dbnc4 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC4_DBNC_CTRL_T;

// eic5_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt5 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en5 : 1;        // [14]
        uint32_t force_clk_dbnc5 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC5_DBNC_CTRL_T;

// eic6_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt6 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en6 : 1;        // [14]
        uint32_t force_clk_dbnc6 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC6_DBNC_CTRL_T;

// eic7_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt7 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en7 : 1;        // [14]
        uint32_t force_clk_dbnc7 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC7_DBNC_CTRL_T;

// eic8_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt8 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en8 : 1;        // [14]
        uint32_t force_clk_dbnc8 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC8_DBNC_CTRL_T;

// eic9_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt9 : 12;      // [11:0]
        uint32_t __13_12 : 2;         // [13:12]
        uint32_t dbnc_en9 : 1;        // [14]
        uint32_t force_clk_dbnc9 : 1; // [15]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_PMIC_EIC_EIC9_DBNC_CTRL_T;

// eic10_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt10 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en10 : 1;        // [14]
        uint32_t force_clk_dbnc10 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC10_DBNC_CTRL_T;

// eic11_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt11 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en11 : 1;        // [14]
        uint32_t force_clk_dbnc11 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC11_DBNC_CTRL_T;

// eic12_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt12 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en12 : 1;        // [14]
        uint32_t force_clk_dbnc12 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC12_DBNC_CTRL_T;

// eic13_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt13 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en13 : 1;        // [14]
        uint32_t force_clk_dbnc13 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC13_DBNC_CTRL_T;

// eic14_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt14 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en14 : 1;        // [14]
        uint32_t force_clk_dbnc14 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC14_DBNC_CTRL_T;

// eic15_dbnc_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbnc_cnt15 : 12;      // [11:0]
        uint32_t __13_12 : 2;          // [13:12]
        uint32_t dbnc_en15 : 1;        // [14]
        uint32_t force_clk_dbnc15 : 1; // [15]
        uint32_t __31_16 : 16;         // [31:16]
    } b;
} REG_PMIC_EIC_EIC15_DBNC_CTRL_T;

// eic_dbnc_data
#define PMIC_EIC_DBNC_DATA(n) (((n)&0xffff) << 0)

// eic_dbnc_dmsk
#define PMIC_EIC_DBNC_DMSK(n) (((n)&0xffff) << 0)

// eic_dbnc_iev
#define PMIC_EIC_DBNC_IEV(n) (((n)&0xffff) << 0)

// eic_dbnc_ie
#define PMIC_EIC_DBNC_IE(n) (((n)&0xffff) << 0)

// eic_dbnc_ris
#define PMIC_EIC_DBNC_RIS(n) (((n)&0xffff) << 0)

// eic_dbnc_mis
#define PMIC_EIC_DBNC_MIS(n) (((n)&0xffff) << 0)

// eic_dbnc_ic
#define PMIC_EIC_DBNC_IC(n) (((n)&0xffff) << 0)

// eic_dbnc_trig
#define PMIC_EIC_DBNC_TRIG(n) (((n)&0xffff) << 0)

// eic0_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT0(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN0 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC0 (1 << 15)

// eic1_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT1(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN1 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC1 (1 << 15)

// eic2_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT2(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN2 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC2 (1 << 15)

// eic3_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT3(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN3 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC3 (1 << 15)

// eic4_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT4(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN4 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC4 (1 << 15)

// eic5_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT5(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN5 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC5 (1 << 15)

// eic6_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT6(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN6 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC6 (1 << 15)

// eic7_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT7(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN7 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC7 (1 << 15)

// eic8_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT8(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN8 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC8 (1 << 15)

// eic9_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT9(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN9 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC9 (1 << 15)

// eic10_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT10(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN10 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC10 (1 << 15)

// eic11_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT11(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN11 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC11 (1 << 15)

// eic12_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT12(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN12 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC12 (1 << 15)

// eic13_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT13(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN13 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC13 (1 << 15)

// eic14_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT14(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN14 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC14 (1 << 15)

// eic15_dbnc_ctrl
#define PMIC_EIC_DBNC_CNT15(n) (((n)&0xfff) << 0)
#define PMIC_EIC_DBNC_EN15 (1 << 14)
#define PMIC_EIC_FORCE_CLK_DBNC15 (1 << 15)

#endif // _PMIC_EIC_H_
