/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _REG_FW_IDLE_LPS_H_
#define _REG_FW_IDLE_LPS_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_REG_FW_IDLE_LPS_BASE (0x51314000)

typedef volatile struct
{
    uint32_t reg_rd_ctrl_0;            // 0x00000000
    uint32_t reg_rd_ctrl_1;            // 0x00000004
    uint32_t reg_rd_ctrl_2;            // 0x00000008
    uint32_t reg_wr_ctrl_0;            // 0x0000000c
    uint32_t reg_wr_ctrl_1;            // 0x00000010
    uint32_t reg_wr_ctrl_2;            // 0x00000014
    uint32_t bit_wr_ctrl_addr_array0;  // 0x00000018
    uint32_t bit_wr_ctrl_addr_array1;  // 0x0000001c
    uint32_t bit_wr_ctrl_addr_array2;  // 0x00000020
    uint32_t bit_wr_ctrl_addr_array3;  // 0x00000024
    uint32_t bit_wr_ctrl_addr_array4;  // 0x00000028
    uint32_t bit_wr_ctrl_addr_array5;  // 0x0000002c
    uint32_t bit_wr_ctrl_addr_array6;  // 0x00000030
    uint32_t bit_wr_ctrl_addr_array7;  // 0x00000034
    uint32_t bit_wr_ctrl_addr_array8;  // 0x00000038
    uint32_t bit_wr_ctrl_addr_array9;  // 0x0000003c
    uint32_t bit_wr_ctrl_addr_array10; // 0x00000040
    uint32_t bit_wr_ctrl_addr_array11; // 0x00000044
    uint32_t bit_wr_ctrl_addr_array12; // 0x00000048
    uint32_t bit_wr_ctrl_addr_array13; // 0x0000004c
    uint32_t bit_wr_ctrl_addr_array14; // 0x00000050
    uint32_t bit_wr_ctrl_addr_array15; // 0x00000054
    uint32_t bit_wr_ctrl_array0;       // 0x00000058
    uint32_t bit_wr_ctrl_array1;       // 0x0000005c
    uint32_t bit_wr_ctrl_array2;       // 0x00000060
    uint32_t bit_wr_ctrl_array3;       // 0x00000064
    uint32_t bit_wr_ctrl_array4;       // 0x00000068
    uint32_t bit_wr_ctrl_array5;       // 0x0000006c
    uint32_t bit_wr_ctrl_array6;       // 0x00000070
    uint32_t bit_wr_ctrl_array7;       // 0x00000074
    uint32_t bit_wr_ctrl_array8;       // 0x00000078
    uint32_t bit_wr_ctrl_array9;       // 0x0000007c
    uint32_t bit_wr_ctrl_array10;      // 0x00000080
    uint32_t bit_wr_ctrl_array11;      // 0x00000084
    uint32_t bit_wr_ctrl_array12;      // 0x00000088
    uint32_t bit_wr_ctrl_array13;      // 0x0000008c
    uint32_t bit_wr_ctrl_array14;      // 0x00000090
    uint32_t bit_wr_ctrl_array15;      // 0x00000094
} HWP_REG_FW_IDLE_LPS_T;

#define hwp_regFwIdleLps ((HWP_REG_FW_IDLE_LPS_T *)REG_ACCESS_ADDRESS(REG_REG_FW_IDLE_LPS_BASE))

// reg_rd_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_ctrl_ap_rd_sec : 1;      // [0]
        uint32_t ap_sig_en_rd_sec : 1;        // [1]
        uint32_t ap_lps_sig_time_rd_sec : 1;  // [2]
        uint32_t lps_ctrl_cp_rd_sec : 1;      // [3]
        uint32_t cp_pm2_sta_rd_sec : 1;       // [4]
        uint32_t cp_sig_en_rd_sec : 1;        // [5]
        uint32_t cp_lps_sig_time_rd_sec : 1;  // [6]
        uint32_t pm2_off_time_rd_sec : 1;     // [7]
        uint32_t pm2_on_time_rd_sec : 1;      // [8]
        uint32_t pm2_on_off_time_rd_sec : 1;  // [9]
        uint32_t ap_pm2_sta_rd_sec : 1;       // [10]
        uint32_t ap_pm2_mode_en_rd_sec : 1;   // [11]
        uint32_t aon_sig_en_rd_sec : 1;       // [12]
        uint32_t sleep_prot_time_rd_sec : 1;  // [13]
        uint32_t eliminate_jitter_rd_sec : 1; // [14]
        uint32_t ap_lps_sta_rd_sec : 1;       // [15]
        uint32_t cp_inten_rd_sec : 1;         // [16]
        uint32_t cp_int_sta_rd_sec : 1;       // [17]
        uint32_t ap_inten_rd_sec : 1;         // [18]
        uint32_t ap_int_sta_rd_sec : 1;       // [19]
        uint32_t ap_awk_en_rd_sec : 1;        // [20]
        uint32_t ap_awk_st_rd_sec : 1;        // [21]
        uint32_t cp_awk_en_rd_sec : 1;        // [22]
        uint32_t cp_awk_st_rd_sec : 1;        // [23]
        uint32_t cp_lps_sta_rd_sec : 1;       // [24]
        uint32_t cp_p1_time_rd_sec : 1;       // [25]
        uint32_t cp_p2_time_rd_sec : 1;       // [26]
        uint32_t lps_t_time1_rd_sec : 1;      // [27]
        uint32_t lps_t_time2_rd_sec : 1;      // [28]
        uint32_t lps_t_time3_rd_sec : 1;      // [29]
        uint32_t lps_t_time4_rd_sec : 1;      // [30]
        uint32_t lps_t_time5_rd_sec : 1;      // [31]
    } b;
} REG_REG_FW_IDLE_LPS_REG_RD_CTRL_0_T;

// reg_rd_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_t_time6_rd_sec : 1; // [0]
        uint32_t load_en_rd_sec : 1;     // [1]
        uint32_t lps_32k_ref_rd_sec : 1; // [2]
        uint32_t ref_32k_fnl_rd_sec : 1; // [3]
        uint32_t lps_tpctrl_rd_sec : 1;  // [4]
        uint32_t lps_tp_sta_rd_sec : 1;  // [5]
        uint32_t load_time_rd_sec : 1;   // [6]
        uint32_t mon_sel_rd_sec : 1;     // [7]
        uint32_t lps_res0_rd_sec : 1;    // [8]
        uint32_t lps_res1_rd_sec : 1;    // [9]
        uint32_t lps_res2_rd_sec : 1;    // [10]
        uint32_t lps_res3_rd_sec : 1;    // [11]
        uint32_t lps_res4_rd_sec : 1;    // [12]
        uint32_t lps_res5_rd_sec : 1;    // [13]
        uint32_t lps_res6_rd_sec : 1;    // [14]
        uint32_t lps_res7_rd_sec : 1;    // [15]
        uint32_t lps_res8_rd_sec : 1;    // [16]
        uint32_t lps_res9_rd_sec : 1;    // [17]
        uint32_t lps_res10_rd_sec : 1;   // [18]
        uint32_t lps_res11_rd_sec : 1;   // [19]
        uint32_t cp_p1_en_rd_sec : 1;    // [20]
        uint32_t cp_p2_en_rd_sec : 1;    // [21]
        uint32_t lps_t1_en_rd_sec : 1;   // [22]
        uint32_t lps_t2_en_rd_sec : 1;   // [23]
        uint32_t lps_t3_en_rd_sec : 1;   // [24]
        uint32_t lps_t4_en_rd_sec : 1;   // [25]
        uint32_t lps_t5_en_rd_sec : 1;   // [26]
        uint32_t lps_t6_en_rd_sec : 1;   // [27]
        uint32_t ap_awk_en1_rd_sec : 1;  // [28]
        uint32_t ap_awk_st1_rd_sec : 1;  // [29]
        uint32_t cp_awk_en1_rd_sec : 1;  // [30]
        uint32_t cp_awk_st1_rd_sec : 1;  // [31]
    } b;
} REG_REG_FW_IDLE_LPS_REG_RD_CTRL_1_T;

// reg_rd_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_t_time7_rd_sec : 1;    // [0]
        uint32_t lps_t_time8_rd_sec : 1;    // [1]
        uint32_t lps_t_time9_rd_sec : 1;    // [2]
        uint32_t lps_t7_en_rd_sec : 1;      // [3]
        uint32_t lps_t8_en_rd_sec : 1;      // [4]
        uint32_t lps_t9_en_rd_sec : 1;      // [5]
        uint32_t cp_pm2_mode_en_rd_sec : 1; // [6]
        uint32_t __31_7 : 25;               // [31:7]
    } b;
} REG_REG_FW_IDLE_LPS_REG_RD_CTRL_2_T;

// reg_wr_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_ctrl_ap_wr_sec : 1;      // [0]
        uint32_t ap_sig_en_wr_sec : 1;        // [1]
        uint32_t ap_lps_sig_time_wr_sec : 1;  // [2]
        uint32_t lps_ctrl_cp_wr_sec : 1;      // [3]
        uint32_t cp_pm2_sta_wr_sec : 1;       // [4]
        uint32_t cp_sig_en_wr_sec : 1;        // [5]
        uint32_t cp_lps_sig_time_wr_sec : 1;  // [6]
        uint32_t pm2_off_time_wr_sec : 1;     // [7]
        uint32_t pm2_on_time_wr_sec : 1;      // [8]
        uint32_t pm2_on_off_time_wr_sec : 1;  // [9]
        uint32_t ap_pm2_sta_wr_sec : 1;       // [10]
        uint32_t ap_pm2_mode_en_wr_sec : 1;   // [11]
        uint32_t aon_sig_en_wr_sec : 1;       // [12]
        uint32_t sleep_prot_time_wr_sec : 1;  // [13]
        uint32_t eliminate_jitter_wr_sec : 1; // [14]
        uint32_t ap_lps_sta_wr_sec : 1;       // [15]
        uint32_t cp_inten_wr_sec : 1;         // [16]
        uint32_t cp_int_sta_wr_sec : 1;       // [17]
        uint32_t ap_inten_wr_sec : 1;         // [18]
        uint32_t ap_int_sta_wr_sec : 1;       // [19]
        uint32_t ap_awk_en_wr_sec : 1;        // [20]
        uint32_t ap_awk_st_wr_sec : 1;        // [21]
        uint32_t cp_awk_en_wr_sec : 1;        // [22]
        uint32_t cp_awk_st_wr_sec : 1;        // [23]
        uint32_t cp_lps_sta_wr_sec : 1;       // [24]
        uint32_t cp_p1_time_wr_sec : 1;       // [25]
        uint32_t cp_p2_time_wr_sec : 1;       // [26]
        uint32_t lps_t_time1_wr_sec : 1;      // [27]
        uint32_t lps_t_time2_wr_sec : 1;      // [28]
        uint32_t lps_t_time3_wr_sec : 1;      // [29]
        uint32_t lps_t_time4_wr_sec : 1;      // [30]
        uint32_t lps_t_time5_wr_sec : 1;      // [31]
    } b;
} REG_REG_FW_IDLE_LPS_REG_WR_CTRL_0_T;

// reg_wr_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_t_time6_wr_sec : 1; // [0]
        uint32_t load_en_wr_sec : 1;     // [1]
        uint32_t lps_32k_ref_wr_sec : 1; // [2]
        uint32_t ref_32k_fnl_wr_sec : 1; // [3]
        uint32_t lps_tpctrl_wr_sec : 1;  // [4]
        uint32_t lps_tp_sta_wr_sec : 1;  // [5]
        uint32_t load_time_wr_sec : 1;   // [6]
        uint32_t mon_sel_wr_sec : 1;     // [7]
        uint32_t lps_res0_wr_sec : 1;    // [8]
        uint32_t lps_res1_wr_sec : 1;    // [9]
        uint32_t lps_res2_wr_sec : 1;    // [10]
        uint32_t lps_res3_wr_sec : 1;    // [11]
        uint32_t lps_res4_wr_sec : 1;    // [12]
        uint32_t lps_res5_wr_sec : 1;    // [13]
        uint32_t lps_res6_wr_sec : 1;    // [14]
        uint32_t lps_res7_wr_sec : 1;    // [15]
        uint32_t lps_res8_wr_sec : 1;    // [16]
        uint32_t lps_res9_wr_sec : 1;    // [17]
        uint32_t lps_res10_wr_sec : 1;   // [18]
        uint32_t lps_res11_wr_sec : 1;   // [19]
        uint32_t cp_p1_en_wr_sec : 1;    // [20]
        uint32_t cp_p2_en_wr_sec : 1;    // [21]
        uint32_t lps_t1_en_wr_sec : 1;   // [22]
        uint32_t lps_t2_en_wr_sec : 1;   // [23]
        uint32_t lps_t3_en_wr_sec : 1;   // [24]
        uint32_t lps_t4_en_wr_sec : 1;   // [25]
        uint32_t lps_t5_en_wr_sec : 1;   // [26]
        uint32_t lps_t6_en_wr_sec : 1;   // [27]
        uint32_t ap_awk_en1_wr_sec : 1;  // [28]
        uint32_t ap_awk_st1_wr_sec : 1;  // [29]
        uint32_t cp_awk_en1_wr_sec : 1;  // [30]
        uint32_t cp_awk_st1_wr_sec : 1;  // [31]
    } b;
} REG_REG_FW_IDLE_LPS_REG_WR_CTRL_1_T;

// reg_wr_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lps_t_time7_wr_sec : 1;    // [0]
        uint32_t lps_t_time8_wr_sec : 1;    // [1]
        uint32_t lps_t_time9_wr_sec : 1;    // [2]
        uint32_t lps_t7_en_wr_sec : 1;      // [3]
        uint32_t lps_t8_en_wr_sec : 1;      // [4]
        uint32_t lps_t9_en_wr_sec : 1;      // [5]
        uint32_t cp_pm2_mode_en_wr_sec : 1; // [6]
        uint32_t __31_7 : 25;               // [31:7]
    } b;
} REG_REG_FW_IDLE_LPS_REG_WR_CTRL_2_T;

// bit_wr_ctrl_addr_array0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array0 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY0_T;

// bit_wr_ctrl_addr_array1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array1 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY1_T;

// bit_wr_ctrl_addr_array2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array2 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY2_T;

// bit_wr_ctrl_addr_array3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array3 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY3_T;

// bit_wr_ctrl_addr_array4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array4 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY4_T;

// bit_wr_ctrl_addr_array5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array5 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY5_T;

// bit_wr_ctrl_addr_array6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array6 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY6_T;

// bit_wr_ctrl_addr_array7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array7 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY7_T;

// bit_wr_ctrl_addr_array8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array8 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY8_T;

// bit_wr_ctrl_addr_array9
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array9 : 12; // [11:0]
        uint32_t __31_12 : 20;                 // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY9_T;

// bit_wr_ctrl_addr_array10
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array10 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY10_T;

// bit_wr_ctrl_addr_array11
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array11 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY11_T;

// bit_wr_ctrl_addr_array12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array12 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY12_T;

// bit_wr_ctrl_addr_array13
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array13 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY13_T;

// bit_wr_ctrl_addr_array14
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array14 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY14_T;

// bit_wr_ctrl_addr_array15
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_wr_ctrl_addr_array15 : 12; // [11:0]
        uint32_t __31_12 : 20;                  // [31:12]
    } b;
} REG_REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY15_T;

// reg_rd_ctrl_0
#define REG_FW_IDLE_LPS_LPS_CTRL_AP_RD_SEC (1 << 0)
#define REG_FW_IDLE_LPS_AP_SIG_EN_RD_SEC (1 << 1)
#define REG_FW_IDLE_LPS_AP_LPS_SIG_TIME_RD_SEC (1 << 2)
#define REG_FW_IDLE_LPS_LPS_CTRL_CP_RD_SEC (1 << 3)
#define REG_FW_IDLE_LPS_CP_PM2_STA_RD_SEC (1 << 4)
#define REG_FW_IDLE_LPS_CP_SIG_EN_RD_SEC (1 << 5)
#define REG_FW_IDLE_LPS_CP_LPS_SIG_TIME_RD_SEC (1 << 6)
#define REG_FW_IDLE_LPS_PM2_OFF_TIME_RD_SEC (1 << 7)
#define REG_FW_IDLE_LPS_PM2_ON_TIME_RD_SEC (1 << 8)
#define REG_FW_IDLE_LPS_PM2_ON_OFF_TIME_RD_SEC (1 << 9)
#define REG_FW_IDLE_LPS_AP_PM2_STA_RD_SEC (1 << 10)
#define REG_FW_IDLE_LPS_AP_PM2_MODE_EN_RD_SEC (1 << 11)
#define REG_FW_IDLE_LPS_AON_SIG_EN_RD_SEC (1 << 12)
#define REG_FW_IDLE_LPS_SLEEP_PROT_TIME_RD_SEC (1 << 13)
#define REG_FW_IDLE_LPS_ELIMINATE_JITTER_RD_SEC (1 << 14)
#define REG_FW_IDLE_LPS_AP_LPS_STA_RD_SEC (1 << 15)
#define REG_FW_IDLE_LPS_CP_INTEN_RD_SEC (1 << 16)
#define REG_FW_IDLE_LPS_CP_INT_STA_RD_SEC (1 << 17)
#define REG_FW_IDLE_LPS_AP_INTEN_RD_SEC (1 << 18)
#define REG_FW_IDLE_LPS_AP_INT_STA_RD_SEC (1 << 19)
#define REG_FW_IDLE_LPS_AP_AWK_EN_RD_SEC (1 << 20)
#define REG_FW_IDLE_LPS_AP_AWK_ST_RD_SEC (1 << 21)
#define REG_FW_IDLE_LPS_CP_AWK_EN_RD_SEC (1 << 22)
#define REG_FW_IDLE_LPS_CP_AWK_ST_RD_SEC (1 << 23)
#define REG_FW_IDLE_LPS_CP_LPS_STA_RD_SEC (1 << 24)
#define REG_FW_IDLE_LPS_CP_P1_TIME_RD_SEC (1 << 25)
#define REG_FW_IDLE_LPS_CP_P2_TIME_RD_SEC (1 << 26)
#define REG_FW_IDLE_LPS_LPS_T_TIME1_RD_SEC (1 << 27)
#define REG_FW_IDLE_LPS_LPS_T_TIME2_RD_SEC (1 << 28)
#define REG_FW_IDLE_LPS_LPS_T_TIME3_RD_SEC (1 << 29)
#define REG_FW_IDLE_LPS_LPS_T_TIME4_RD_SEC (1 << 30)
#define REG_FW_IDLE_LPS_LPS_T_TIME5_RD_SEC (1 << 31)

// reg_rd_ctrl_1
#define REG_FW_IDLE_LPS_LPS_T_TIME6_RD_SEC (1 << 0)
#define REG_FW_IDLE_LPS_LOAD_EN_RD_SEC (1 << 1)
#define REG_FW_IDLE_LPS_LPS_32K_REF_RD_SEC (1 << 2)
#define REG_FW_IDLE_LPS_REF_32K_FNL_RD_SEC (1 << 3)
#define REG_FW_IDLE_LPS_LPS_TPCTRL_RD_SEC (1 << 4)
#define REG_FW_IDLE_LPS_LPS_TP_STA_RD_SEC (1 << 5)
#define REG_FW_IDLE_LPS_LOAD_TIME_RD_SEC (1 << 6)
#define REG_FW_IDLE_LPS_MON_SEL_RD_SEC (1 << 7)
#define REG_FW_IDLE_LPS_LPS_RES0_RD_SEC (1 << 8)
#define REG_FW_IDLE_LPS_LPS_RES1_RD_SEC (1 << 9)
#define REG_FW_IDLE_LPS_LPS_RES2_RD_SEC (1 << 10)
#define REG_FW_IDLE_LPS_LPS_RES3_RD_SEC (1 << 11)
#define REG_FW_IDLE_LPS_LPS_RES4_RD_SEC (1 << 12)
#define REG_FW_IDLE_LPS_LPS_RES5_RD_SEC (1 << 13)
#define REG_FW_IDLE_LPS_LPS_RES6_RD_SEC (1 << 14)
#define REG_FW_IDLE_LPS_LPS_RES7_RD_SEC (1 << 15)
#define REG_FW_IDLE_LPS_LPS_RES8_RD_SEC (1 << 16)
#define REG_FW_IDLE_LPS_LPS_RES9_RD_SEC (1 << 17)
#define REG_FW_IDLE_LPS_LPS_RES10_RD_SEC (1 << 18)
#define REG_FW_IDLE_LPS_LPS_RES11_RD_SEC (1 << 19)
#define REG_FW_IDLE_LPS_CP_P1_EN_RD_SEC (1 << 20)
#define REG_FW_IDLE_LPS_CP_P2_EN_RD_SEC (1 << 21)
#define REG_FW_IDLE_LPS_LPS_T1_EN_RD_SEC (1 << 22)
#define REG_FW_IDLE_LPS_LPS_T2_EN_RD_SEC (1 << 23)
#define REG_FW_IDLE_LPS_LPS_T3_EN_RD_SEC (1 << 24)
#define REG_FW_IDLE_LPS_LPS_T4_EN_RD_SEC (1 << 25)
#define REG_FW_IDLE_LPS_LPS_T5_EN_RD_SEC (1 << 26)
#define REG_FW_IDLE_LPS_LPS_T6_EN_RD_SEC (1 << 27)
#define REG_FW_IDLE_LPS_AP_AWK_EN1_RD_SEC (1 << 28)
#define REG_FW_IDLE_LPS_AP_AWK_ST1_RD_SEC (1 << 29)
#define REG_FW_IDLE_LPS_CP_AWK_EN1_RD_SEC (1 << 30)
#define REG_FW_IDLE_LPS_CP_AWK_ST1_RD_SEC (1 << 31)

// reg_rd_ctrl_2
#define REG_FW_IDLE_LPS_LPS_T_TIME7_RD_SEC (1 << 0)
#define REG_FW_IDLE_LPS_LPS_T_TIME8_RD_SEC (1 << 1)
#define REG_FW_IDLE_LPS_LPS_T_TIME9_RD_SEC (1 << 2)
#define REG_FW_IDLE_LPS_LPS_T7_EN_RD_SEC (1 << 3)
#define REG_FW_IDLE_LPS_LPS_T8_EN_RD_SEC (1 << 4)
#define REG_FW_IDLE_LPS_LPS_T9_EN_RD_SEC (1 << 5)
#define REG_FW_IDLE_LPS_CP_PM2_MODE_EN_RD_SEC (1 << 6)

// reg_wr_ctrl_0
#define REG_FW_IDLE_LPS_LPS_CTRL_AP_WR_SEC (1 << 0)
#define REG_FW_IDLE_LPS_AP_SIG_EN_WR_SEC (1 << 1)
#define REG_FW_IDLE_LPS_AP_LPS_SIG_TIME_WR_SEC (1 << 2)
#define REG_FW_IDLE_LPS_LPS_CTRL_CP_WR_SEC (1 << 3)
#define REG_FW_IDLE_LPS_CP_PM2_STA_WR_SEC (1 << 4)
#define REG_FW_IDLE_LPS_CP_SIG_EN_WR_SEC (1 << 5)
#define REG_FW_IDLE_LPS_CP_LPS_SIG_TIME_WR_SEC (1 << 6)
#define REG_FW_IDLE_LPS_PM2_OFF_TIME_WR_SEC (1 << 7)
#define REG_FW_IDLE_LPS_PM2_ON_TIME_WR_SEC (1 << 8)
#define REG_FW_IDLE_LPS_PM2_ON_OFF_TIME_WR_SEC (1 << 9)
#define REG_FW_IDLE_LPS_AP_PM2_STA_WR_SEC (1 << 10)
#define REG_FW_IDLE_LPS_AP_PM2_MODE_EN_WR_SEC (1 << 11)
#define REG_FW_IDLE_LPS_AON_SIG_EN_WR_SEC (1 << 12)
#define REG_FW_IDLE_LPS_SLEEP_PROT_TIME_WR_SEC (1 << 13)
#define REG_FW_IDLE_LPS_ELIMINATE_JITTER_WR_SEC (1 << 14)
#define REG_FW_IDLE_LPS_AP_LPS_STA_WR_SEC (1 << 15)
#define REG_FW_IDLE_LPS_CP_INTEN_WR_SEC (1 << 16)
#define REG_FW_IDLE_LPS_CP_INT_STA_WR_SEC (1 << 17)
#define REG_FW_IDLE_LPS_AP_INTEN_WR_SEC (1 << 18)
#define REG_FW_IDLE_LPS_AP_INT_STA_WR_SEC (1 << 19)
#define REG_FW_IDLE_LPS_AP_AWK_EN_WR_SEC (1 << 20)
#define REG_FW_IDLE_LPS_AP_AWK_ST_WR_SEC (1 << 21)
#define REG_FW_IDLE_LPS_CP_AWK_EN_WR_SEC (1 << 22)
#define REG_FW_IDLE_LPS_CP_AWK_ST_WR_SEC (1 << 23)
#define REG_FW_IDLE_LPS_CP_LPS_STA_WR_SEC (1 << 24)
#define REG_FW_IDLE_LPS_CP_P1_TIME_WR_SEC (1 << 25)
#define REG_FW_IDLE_LPS_CP_P2_TIME_WR_SEC (1 << 26)
#define REG_FW_IDLE_LPS_LPS_T_TIME1_WR_SEC (1 << 27)
#define REG_FW_IDLE_LPS_LPS_T_TIME2_WR_SEC (1 << 28)
#define REG_FW_IDLE_LPS_LPS_T_TIME3_WR_SEC (1 << 29)
#define REG_FW_IDLE_LPS_LPS_T_TIME4_WR_SEC (1 << 30)
#define REG_FW_IDLE_LPS_LPS_T_TIME5_WR_SEC (1 << 31)

// reg_wr_ctrl_1
#define REG_FW_IDLE_LPS_LPS_T_TIME6_WR_SEC (1 << 0)
#define REG_FW_IDLE_LPS_LOAD_EN_WR_SEC (1 << 1)
#define REG_FW_IDLE_LPS_LPS_32K_REF_WR_SEC (1 << 2)
#define REG_FW_IDLE_LPS_REF_32K_FNL_WR_SEC (1 << 3)
#define REG_FW_IDLE_LPS_LPS_TPCTRL_WR_SEC (1 << 4)
#define REG_FW_IDLE_LPS_LPS_TP_STA_WR_SEC (1 << 5)
#define REG_FW_IDLE_LPS_LOAD_TIME_WR_SEC (1 << 6)
#define REG_FW_IDLE_LPS_MON_SEL_WR_SEC (1 << 7)
#define REG_FW_IDLE_LPS_LPS_RES0_WR_SEC (1 << 8)
#define REG_FW_IDLE_LPS_LPS_RES1_WR_SEC (1 << 9)
#define REG_FW_IDLE_LPS_LPS_RES2_WR_SEC (1 << 10)
#define REG_FW_IDLE_LPS_LPS_RES3_WR_SEC (1 << 11)
#define REG_FW_IDLE_LPS_LPS_RES4_WR_SEC (1 << 12)
#define REG_FW_IDLE_LPS_LPS_RES5_WR_SEC (1 << 13)
#define REG_FW_IDLE_LPS_LPS_RES6_WR_SEC (1 << 14)
#define REG_FW_IDLE_LPS_LPS_RES7_WR_SEC (1 << 15)
#define REG_FW_IDLE_LPS_LPS_RES8_WR_SEC (1 << 16)
#define REG_FW_IDLE_LPS_LPS_RES9_WR_SEC (1 << 17)
#define REG_FW_IDLE_LPS_LPS_RES10_WR_SEC (1 << 18)
#define REG_FW_IDLE_LPS_LPS_RES11_WR_SEC (1 << 19)
#define REG_FW_IDLE_LPS_CP_P1_EN_WR_SEC (1 << 20)
#define REG_FW_IDLE_LPS_CP_P2_EN_WR_SEC (1 << 21)
#define REG_FW_IDLE_LPS_LPS_T1_EN_WR_SEC (1 << 22)
#define REG_FW_IDLE_LPS_LPS_T2_EN_WR_SEC (1 << 23)
#define REG_FW_IDLE_LPS_LPS_T3_EN_WR_SEC (1 << 24)
#define REG_FW_IDLE_LPS_LPS_T4_EN_WR_SEC (1 << 25)
#define REG_FW_IDLE_LPS_LPS_T5_EN_WR_SEC (1 << 26)
#define REG_FW_IDLE_LPS_LPS_T6_EN_WR_SEC (1 << 27)
#define REG_FW_IDLE_LPS_AP_AWK_EN1_WR_SEC (1 << 28)
#define REG_FW_IDLE_LPS_AP_AWK_ST1_WR_SEC (1 << 29)
#define REG_FW_IDLE_LPS_CP_AWK_EN1_WR_SEC (1 << 30)
#define REG_FW_IDLE_LPS_CP_AWK_ST1_WR_SEC (1 << 31)

// reg_wr_ctrl_2
#define REG_FW_IDLE_LPS_LPS_T_TIME7_WR_SEC (1 << 0)
#define REG_FW_IDLE_LPS_LPS_T_TIME8_WR_SEC (1 << 1)
#define REG_FW_IDLE_LPS_LPS_T_TIME9_WR_SEC (1 << 2)
#define REG_FW_IDLE_LPS_LPS_T7_EN_WR_SEC (1 << 3)
#define REG_FW_IDLE_LPS_LPS_T8_EN_WR_SEC (1 << 4)
#define REG_FW_IDLE_LPS_LPS_T9_EN_WR_SEC (1 << 5)
#define REG_FW_IDLE_LPS_CP_PM2_MODE_EN_WR_SEC (1 << 6)

// bit_wr_ctrl_addr_array0
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY0(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array1
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY1(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array2
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY2(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array3
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY3(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array4
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY4(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array5
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY5(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array6
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY6(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array7
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY7(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array8
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY8(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array9
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY9(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array10
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY10(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array11
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY11(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array12
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY12(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array13
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY13(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array14
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY14(n) (((n)&0xfff) << 0)

// bit_wr_ctrl_addr_array15
#define REG_FW_IDLE_LPS_BIT_WR_CTRL_ADDR_ARRAY15(n) (((n)&0xfff) << 0)

#endif // _REG_FW_IDLE_LPS_H_
