/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _RTC_TIMER_H_
#define _RTC_TIMER_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_RTC_TIMER_BASE (0x51708000)

typedef volatile struct
{
    uint32_t ctrl;        // 0x00000000
    uint32_t cur_val_l;   // 0x00000004
    uint32_t cur_val_m;   // 0x00000008
    uint32_t cur_val_h;   // 0x0000000c
    uint32_t alarm_val_l; // 0x00000010
    uint32_t alarm_val_m; // 0x00000014
    uint32_t alarm_val_h; // 0x00000018
    uint32_t load_val_l;  // 0x0000001c
    uint32_t load_val_m;  // 0x00000020
    uint32_t load_val_h;  // 0x00000024
    uint32_t int_mask;    // 0x00000028
    uint32_t int_clr;     // 0x0000002c
    uint32_t int_status;  // 0x00000030
    uint32_t int_cause;   // 0x00000034
} HWP_RTC_TIMER_T;

#define hwp_rtcTimer ((HWP_RTC_TIMER_T *)REG_ACCESS_ADDRESS(REG_RTC_TIMER_BASE))

// ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t timer_enable : 1;    // [0]
        uint32_t alarm_enable : 1;    // [1]
        uint32_t wrap_int_enable : 1; // [2]
        uint32_t read_lock : 1;       // [3], write clear
        uint32_t data_valid : 1;      // [4], read only
        uint32_t data_valid_clr : 1;  // [5], write clear
        uint32_t load_value : 1;      // [6], write clear
        uint32_t __31_7 : 25;         // [31:7]
    } b;
} REG_RTC_TIMER_CTRL_T;

// cur_val_l
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0], read only
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_CUR_VAL_L_T;

// cur_val_m
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0], read only
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_CUR_VAL_M_T;

// cur_val_h
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0], read only
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_CUR_VAL_H_T;

// alarm_val_l
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_ALARM_VAL_L_T;

// alarm_val_m
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_ALARM_VAL_M_T;

// alarm_val_h
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_ALARM_VAL_H_T;

// load_val_l
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_LOAD_VAL_L_T;

// load_val_m
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_LOAD_VAL_M_T;

// load_val_h
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data : 16;    // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_RTC_TIMER_LOAD_VAL_H_T;

// int_mask
typedef union {
    uint32_t v;
    struct
    {
        uint32_t wrap : 1;    // [0]
        uint32_t alarm : 1;   // [1]
        uint32_t __31_2 : 30; // [31:2]
    } b;
} REG_RTC_TIMER_INT_MASK_T;

// int_clr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t wrap : 1;    // [0], write clear
        uint32_t alarm : 1;   // [1], write clear
        uint32_t __31_2 : 30; // [31:2]
    } b;
} REG_RTC_TIMER_INT_CLR_T;

// int_status
typedef union {
    uint32_t v;
    struct
    {
        uint32_t wrap : 1;    // [0], read only
        uint32_t alarm : 1;   // [1], read only
        uint32_t __31_2 : 30; // [31:2]
    } b;
} REG_RTC_TIMER_INT_STATUS_T;

// int_cause
typedef union {
    uint32_t v;
    struct
    {
        uint32_t wrap : 1;    // [0], read only
        uint32_t alarm : 1;   // [1], read only
        uint32_t __31_2 : 30; // [31:2]
    } b;
} REG_RTC_TIMER_INT_CAUSE_T;

// ctrl
#define RTC_TIMER_TIMER_ENABLE (1 << 0)
#define RTC_TIMER_ALARM_ENABLE (1 << 1)
#define RTC_TIMER_WRAP_INT_ENABLE (1 << 2)
#define RTC_TIMER_READ_LOCK (1 << 3)
#define RTC_TIMER_DATA_VALID (1 << 4)
#define RTC_TIMER_DATA_VALID_CLR (1 << 5)
#define RTC_TIMER_LOAD_VALUE (1 << 6)

// cur_val_l
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// cur_val_m
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// cur_val_h
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// alarm_val_l
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// alarm_val_m
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// alarm_val_h
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// load_val_l
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// load_val_m
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// load_val_h
#define RTC_TIMER_DATA(n) (((n)&0xffff) << 0)

// int_mask
#define RTC_TIMER_WRAP (1 << 0)
#define RTC_TIMER_ALARM (1 << 1)

// int_clr
#define RTC_TIMER_WRAP (1 << 0)
#define RTC_TIMER_ALARM (1 << 1)

// int_status
#define RTC_TIMER_WRAP (1 << 0)
#define RTC_TIMER_ALARM (1 << 1)

// int_cause
#define RTC_TIMER_WRAP (1 << 0)
#define RTC_TIMER_ALARM (1 << 1)

#endif // _RTC_TIMER_H_
