/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _LDTC1_H_
#define _LDTC1_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_LDTC1_BASE (0x19000000)

typedef volatile struct
{
    uint32_t csys_para_nxt;      // 0x00000000
    uint32_t cnid_cell_nxt;      // 0x00000004
    uint32_t dsys_para_nxt;      // 0x00000008
    uint32_t dnid_cell_nxt;      // 0x0000000c
    uint32_t ra_t_rnti;          // 0x00000010
    uint32_t c_sps_rnti;         // 0x00000014
    uint32_t tpc_rnti;           // 0x00000018
    uint32_t g_rnti;             // 0x0000001c
    uint32_t csi_rsmap0_nxt;     // 0x00000020
    uint32_t csi_rsmap1_nxt;     // 0x00000024
    uint32_t pmi_cfg;            // 0x00000028
    uint32_t pcfi_cfg_nxt;       // 0x0000002c
    uint32_t phi_cfg_nxt;        // 0x00000030
    uint32_t pdcch_cfg_nxt;      // 0x00000034
    uint32_t pdsch0_cfg_nxt;     // 0x00000038
    uint32_t pdsch1_cfg_nxt;     // 0x0000003c
    uint32_t pdsch2_cfg_nxt;     // 0x00000040
    uint32_t frame_ccnt_nxt;     // 0x00000044
    uint32_t frame_dcnt_nxt;     // 0x00000048
    uint32_t ldtc1_cserv_nxt;    // 0x0000004c
    uint32_t ldtc1_dserv_nxt;    // 0x00000050
    uint32_t ldtc1_cctrl_nxt;    // 0x00000054
    uint32_t ldtc1_dctrl_nxt;    // 0x00000058
    uint32_t ldtc1_cstart;       // 0x0000005c
    uint32_t ldtc1_dstart;       // 0x00000060
    uint32_t ctrl_flag;          // 0x00000064
    uint32_t data_flag;          // 0x00000068
    uint32_t buf_flag;           // 0x0000006c
    uint32_t alg_comm_para;      // 0x00000070
    uint32_t che_fh_para;        // 0x00000074
    uint32_t che_th_para;        // 0x00000078
    uint32_t rbbm_pds00_nxt;     // 0x0000007c
    uint32_t rbbm_pds01_nxt;     // 0x00000080
    uint32_t rbbm_pds02_nxt;     // 0x00000084
    uint32_t rbbm_pds03_nxt;     // 0x00000088
    uint32_t rbbm_pds10_nxt;     // 0x0000008c
    uint32_t rbbm_pds11_nxt;     // 0x00000090
    uint32_t rbbm_pds12_nxt;     // 0x00000094
    uint32_t rbbm_pds13_nxt;     // 0x00000098
    uint32_t rbbm_si00_nxt;      // 0x0000009c
    uint32_t rbbm_si01_nxt;      // 0x000000a0
    uint32_t rbbm_si02_nxt;      // 0x000000a4
    uint32_t rbbm_si03_nxt;      // 0x000000a8
    uint32_t rbbm_si10_nxt;      // 0x000000ac
    uint32_t rbbm_si11_nxt;      // 0x000000b0
    uint32_t rbbm_si12_nxt;      // 0x000000b4
    uint32_t rbbm_si13_nxt;      // 0x000000b8
    uint32_t rbbm_pag00_nxt;     // 0x000000bc
    uint32_t rbbm_pag01_nxt;     // 0x000000c0
    uint32_t rbbm_pag02_nxt;     // 0x000000c4
    uint32_t rbbm_pag03_nxt;     // 0x000000c8
    uint32_t rbbm_pag10_nxt;     // 0x000000cc
    uint32_t rbbm_pag11_nxt;     // 0x000000d0
    uint32_t rbbm_pag12_nxt;     // 0x000000d4
    uint32_t rbbm_pag13_nxt;     // 0x000000d8
    uint32_t pmi_pds0_nxt;       // 0x000000dc
    uint32_t pmi_pds1_nxt;       // 0x000000e0
    uint32_t pmi_pds2_nxt;       // 0x000000e4
    uint32_t pmi_pds3_nxt;       // 0x000000e8
    uint32_t spwr_wb;            // 0x000000ec
    uint32_t npwr_wb;            // 0x000000f0
    uint32_t spwr_wb_agc;        // 0x000000f4
    uint32_t npwr_wb_agc;        // 0x000000f8
    uint32_t sd_scaling_factor0; // 0x000000fc
    uint32_t sd_scaling_factor1; // 0x00000100
    uint32_t sd_scaling_factor2; // 0x00000104
    uint32_t sd_scaling_factor3; // 0x00000108
    uint32_t sd_data_factor0;    // 0x0000010c
    uint32_t sd_data_factor1;    // 0x00000110
    uint32_t sd_data_factor2;    // 0x00000114
    uint32_t cnoise_nxt;         // 0x00000118
    uint32_t cnoise_agc_nxt;     // 0x0000011c
    uint32_t cnoise_th;          // 0x00000120
    uint32_t dnoise_nxt;         // 0x00000124
    uint32_t dnoise_agc_nxt;     // 0x00000128
    uint32_t dnoise_th;          // 0x0000012c
    uint32_t sd_scaling_bcout0;  // 0x00000130
    uint32_t sd_scaling_dout0;   // 0x00000134
    uint32_t sd_scaling_dout1;   // 0x00000138
    uint32_t sd_scaling_dout2;   // 0x0000013c
    uint32_t sd_scaling_dout3;   // 0x00000140
    uint32_t sd_scaling_dout4;   // 0x00000144
    uint32_t hq_hb_sta;          // 0x00000148
    uint32_t hq_hb_proc0;        // 0x0000014c
    uint32_t hq_hb_proc1;        // 0x00000150
    uint32_t turbo_para;         // 0x00000154
    uint32_t turbo_iter;         // 0x00000158
    uint32_t vit_par;            // 0x0000015c
    uint32_t vit_faconf;         // 0x00000160
    uint32_t vit_len;            // 0x00000164
    uint32_t vit_start;          // 0x00000168
    uint32_t vit_flag;           // 0x0000016c
    uint32_t vit_faout;          // 0x00000170
    uint32_t cfi_out;            // 0x00000174
    uint32_t hi_out;             // 0x00000178
    uint32_t sw_cin_nxt;         // 0x0000017c
    uint32_t sw_din_nxt;         // 0x00000180
    uint32_t sw_cout;            // 0x00000184
    uint32_t sw_dout;            // 0x00000188
    uint32_t pds_rep_num;        // 0x0000018c
    uint32_t si_rep_num;         // 0x00000190
    uint32_t pbch_rep_num;       // 0x00000194
    uint32_t rtctrl_cfg;         // 0x00000198
    uint32_t cabis_enbl_nxt;     // 0x0000019c
    uint32_t cabis_cfg_nxt;      // 0x000001a0
    uint32_t cabis_dly1_nxt;     // 0x000001a4
    uint32_t cabis_dly2_nxt;     // 0x000001a8
    uint32_t cabis_shft_nxt;     // 0x000001ac
    uint32_t dabis_enbl_nxt;     // 0x000001b0
    uint32_t dabis_cfg_nxt;      // 0x000001b4
    uint32_t dabis_dly1_nxt;     // 0x000001b8
    uint32_t dabis_dly2_nxt;     // 0x000001bc
    uint32_t dabis_shft_nxt;     // 0x000001c0
    uint32_t reis_conf;          // 0x000001c4
    uint32_t reis_pos0;          // 0x000001c8
    uint32_t reis_pos1;          // 0x000001cc
    uint32_t reis_pos2;          // 0x000001d0
    uint32_t reis_pos3;          // 0x000001d4
    uint32_t rbis_par;           // 0x000001d8
    uint32_t rbis_posout0;       // 0x000001dc
    uint32_t rbis_posout1;       // 0x000001e0
    uint32_t rbis_ave;           // 0x000001e4
    uint32_t rbis_max;           // 0x000001e8
    uint32_t pbml_cfg_nxt;       // 0x000001ec
    uint32_t ctrl_state;         // 0x000001f0
    uint32_t data_state;         // 0x000001f4
    uint32_t frame_ccnt_out;     // 0x000001f8
    uint32_t frame_dcnt_out;     // 0x000001fc
    uint32_t pds0_harqin0_info;  // 0x00000200
    uint32_t pds0_harqin1_info;  // 0x00000204
    uint32_t pds1_harqin0_info;  // 0x00000208
    uint32_t pds1_harqin1_info;  // 0x0000020c
    uint32_t si_harqin0_info;    // 0x00000210
    uint32_t si_harqin1_info;    // 0x00000214
    uint32_t pag_harqin0_info;   // 0x00000218
    uint32_t pag_harqin1_info;   // 0x0000021c
    uint32_t cabis_shft_out;     // 0x00000220
    uint32_t dabis_shft_out;     // 0x00000224
    uint32_t mc_dly1_nxt;        // 0x00000228
    uint32_t mc_dly2_nxt;        // 0x0000022c
    uint32_t mc_dlyth_nxt;       // 0x00000230
    uint32_t __564[262003];      // 0x00000234
    uint32_t cfhmem1;            // 0x00100000
    uint32_t __1048580[16383];   // 0x00100004
    uint32_t cfhmem2;            // 0x00110000
    uint32_t __1114116[16383];   // 0x00110004
    uint32_t crsmem1;            // 0x00120000
    uint32_t __1179652[1023];    // 0x00120004
    uint32_t crsmem2;            // 0x00121000
    uint32_t __1183748[1023];    // 0x00121004
    uint32_t clsmem;             // 0x00122000
    uint32_t __1187844[14335];   // 0x00122004
    uint32_t ursmem;             // 0x00130000
    uint32_t __1245188[8191];    // 0x00130004
    uint32_t ulsmem;             // 0x00138000
    uint32_t __1277956[8191];    // 0x00138004
    uint32_t pwr_mem1;           // 0x00140000
    uint32_t __1310724[111];     // 0x00140004
    uint32_t pwr_mem1_sb_sinr;   // 0x001401c0
    uint32_t __1311172[24];      // 0x001401c4
    uint32_t pwr_mem1_wb_sinr;   // 0x00140224
    uint32_t __1311272[1910];    // 0x00140228
    uint32_t cell_qfmem1;        // 0x00142000
    uint32_t __1318916[3071];    // 0x00142004
    uint32_t cell_qfmem2;        // 0x00145000
    uint32_t __1331204[5119];    // 0x00145004
    uint32_t ct_qtmem1;          // 0x0014a000
    uint32_t __1351684[13];      // 0x0014a004
    uint32_t ct_qtmem1_p01_tap2; // 0x0014a038
    uint32_t __1351740[13];      // 0x0014a03c
    uint32_t ct_qtmem1_p01_tap3; // 0x0014a070
    uint32_t __1351796[37];      // 0x0014a074
    uint32_t ct_qtmem1_p23_tap2; // 0x0014a108
    uint32_t __1351948[445];     // 0x0014a10c
    uint32_t ct_qtmem2;          // 0x0014a800
    uint32_t __1353732[13];      // 0x0014a804
    uint32_t ct_qtmem2_p01_tap2; // 0x0014a838
    uint32_t __1353788[13];      // 0x0014a83c
    uint32_t ct_qtmem2_p01_tap3; // 0x0014a870
    uint32_t __1353844[37];      // 0x0014a874
    uint32_t ct_qtmem2_p23_tap2; // 0x0014a908
    uint32_t __1353996[1469];    // 0x0014a90c
    uint32_t dt_qtmem1;          // 0x0014c000
    uint32_t __1359876[1023];    // 0x0014c004
    uint32_t dt_qtmem2;          // 0x0014d000
    uint32_t __1363972[3071];    // 0x0014d004
    uint32_t agc_cls_mem;        // 0x00150000
    uint32_t __1376260[63];      // 0x00150004
    uint32_t agc_uls_mem;        // 0x00150100
    uint32_t __1376516[63];      // 0x00150104
    uint32_t agc_cfh_mem1;       // 0x00150200
    uint32_t __1376772[63];      // 0x00150204
    uint32_t agc_cfh_mem2;       // 0x00150300
    uint32_t __1377028[63];      // 0x00150304
    uint32_t agc_ufh_mem1;       // 0x00150400
    uint32_t __1377284[63];      // 0x00150404
    uint32_t agc_ufh_mem2;       // 0x00150500
    uint32_t __1377540[63];      // 0x00150504
    uint32_t gold__mem1;         // 0x00150600
    uint32_t __1377796[63];      // 0x00150604
    uint32_t gold__mem2;         // 0x00150700
    uint32_t __1378052[575];     // 0x00150704
    uint32_t ufhmem;             // 0x00151000
    uint32_t __1380356[9215];    // 0x00151004
    uint32_t csi_in_mem;         // 0x0015a000
    uint32_t __1417220[1023];    // 0x0015a004
    uint32_t pmi_mem;            // 0x0015b000
    uint32_t __1421316[11];      // 0x0015b004
    uint32_t pmi_mem_sb;         // 0x0015b030
    uint32_t __1421364[7155];    // 0x0015b034
    uint32_t cell_qfmem3;        // 0x00162000
    uint32_t __1449988[8191];    // 0x00162004
    uint32_t ct_qtmem3;          // 0x0016a000
    uint32_t __1482756[13];      // 0x0016a004
    uint32_t ct_qtmem3_p01_tap2; // 0x0016a038
    uint32_t __1482812[13];      // 0x0016a03c
    uint32_t ct_qtmem3_p01_tap3; // 0x0016a070
    uint32_t __1482868[37];      // 0x0016a074
    uint32_t ct_qtmem3_p23_tap2; // 0x0016a108
    uint32_t __1483020[1981];    // 0x0016a10c
    uint32_t dt_qtmem3;          // 0x0016c000
    uint32_t __1490948[151551];  // 0x0016c004
    uint32_t sdmemch0;           // 0x00200000
    uint32_t __2097156[8191];    // 0x00200004
    uint32_t sdmemch1;           // 0x00208000
    uint32_t __2129924[8191];    // 0x00208004
    uint32_t sdmemcg0;           // 0x00210000
    uint32_t __2162692[8191];    // 0x00210004
    uint32_t sdmemcg1;           // 0x00218000
    uint32_t __2195460[8191];    // 0x00218004
    uint32_t sdmemdh0;           // 0x00220000
    uint32_t __2228228[8191];    // 0x00220004
    uint32_t sdmemdh1;           // 0x00228000
    uint32_t __2260996[8191];    // 0x00228004
    uint32_t sdmemdg0;           // 0x00230000
    uint32_t __2293764[1023];    // 0x00230004
    uint32_t sdmemdg1;           // 0x00231000
    uint32_t __2297860[1023];    // 0x00231004
    uint32_t sdmemdg2;           // 0x00232000
    uint32_t __2301956[1023];    // 0x00232004
    uint32_t sdmemdg3;           // 0x00233000
    uint32_t __2306052[209919];  // 0x00233004
    uint32_t pdcch_memin;        // 0x00300000
    uint32_t __3145732[4095];    // 0x00300004
    uint32_t pdcch_memgold;      // 0x00304000
    uint32_t __3162116[511];     // 0x00304004
    uint32_t pdcch_mempbch0;     // 0x00304800
    uint32_t __3164164[255];     // 0x00304804
    uint32_t pdcch_mempbch1;     // 0x00304c00
    uint32_t __3165188[255];     // 0x00304c04
    uint32_t pdcch_mempbch2;     // 0x00305000
    uint32_t __3166212[255];     // 0x00305004
    uint32_t dci0_out1;          // 0x00305400
    uint32_t dci0_out2;          // 0x00305404
    uint32_t dci0_pwr;           // 0x00305408
    uint32_t dci0_fa;            // 0x0030540c
    uint32_t dci0_info1;         // 0x00305410
    uint32_t dci0_info2;         // 0x00305414
    uint32_t dci0_info3;         // 0x00305418
    uint32_t dci0_info4;         // 0x0030541c
    uint32_t dci0_info5;         // 0x00305420
    uint32_t dci0_info6;         // 0x00305424
    uint32_t dci0_info7;         // 0x00305428
    uint32_t dci0_info8;         // 0x0030542c
    uint32_t dci0_info9;         // 0x00305430
    uint32_t dci0_info10;        // 0x00305434
    uint32_t dci0_info11;        // 0x00305438
    uint32_t dci0_info12;        // 0x0030543c
    uint32_t dci1_out1;          // 0x00305440
    uint32_t dci1_out2;          // 0x00305444
    uint32_t dci1_pwr;           // 0x00305448
    uint32_t dci1_fa;            // 0x0030544c
    uint32_t dci1_info1;         // 0x00305450
    uint32_t dci1_info2;         // 0x00305454
    uint32_t dci1_info3;         // 0x00305458
    uint32_t dci1_info4;         // 0x0030545c
    uint32_t dci1_info5;         // 0x00305460
    uint32_t dci1_info6;         // 0x00305464
    uint32_t dci1_info7;         // 0x00305468
    uint32_t dci1_info8;         // 0x0030546c
    uint32_t dci1_info9;         // 0x00305470
    uint32_t dci1_info10;        // 0x00305474
    uint32_t dci1_info11;        // 0x00305478
    uint32_t dci1_info12;        // 0x0030547c
    uint32_t dci2_out1;          // 0x00305480
    uint32_t dci2_out2;          // 0x00305484
    uint32_t dci2_pwr;           // 0x00305488
    uint32_t dci2_fa;            // 0x0030548c
    uint32_t dci2_info1;         // 0x00305490
    uint32_t dci2_info2;         // 0x00305494
    uint32_t dci2_info3;         // 0x00305498
    uint32_t dci2_info4;         // 0x0030549c
    uint32_t dci2_info5;         // 0x003054a0
    uint32_t dci2_info6;         // 0x003054a4
    uint32_t dci2_info7;         // 0x003054a8
    uint32_t dci2_info8;         // 0x003054ac
    uint32_t dci2_info9;         // 0x003054b0
    uint32_t dci2_info10;        // 0x003054b4
    uint32_t dci2_info11;        // 0x003054b8
    uint32_t dci2_info12;        // 0x003054bc
    uint32_t dci3_out1;          // 0x003054c0
    uint32_t dci3_out2;          // 0x003054c4
    uint32_t dci3_pwr;           // 0x003054c8
    uint32_t dci3_fa;            // 0x003054cc
    uint32_t dci3_info1;         // 0x003054d0
    uint32_t dci3_info2;         // 0x003054d4
    uint32_t dci3_info3;         // 0x003054d8
    uint32_t dci3_info4;         // 0x003054dc
    uint32_t dci3_info5;         // 0x003054e0
    uint32_t dci3_info6;         // 0x003054e4
    uint32_t dci3_info7;         // 0x003054e8
    uint32_t dci3_info8;         // 0x003054ec
    uint32_t dci3_info9;         // 0x003054f0
    uint32_t dci3_info10;        // 0x003054f4
    uint32_t dci3_info11;        // 0x003054f8
    uint32_t dci3_info12;        // 0x003054fc
    uint32_t dci4_out1;          // 0x00305500
    uint32_t dci4_out2;          // 0x00305504
    uint32_t dci4_pwr;           // 0x00305508
    uint32_t dci4_fa;            // 0x0030550c
    uint32_t dci4_info1;         // 0x00305510
    uint32_t dci4_info2;         // 0x00305514
    uint32_t dci4_info3;         // 0x00305518
    uint32_t dci4_info4;         // 0x0030551c
    uint32_t dci4_info5;         // 0x00305520
    uint32_t dci4_info6;         // 0x00305524
    uint32_t dci4_info7;         // 0x00305528
    uint32_t dci4_info8;         // 0x0030552c
    uint32_t dci4_info9;         // 0x00305530
    uint32_t dci4_info10;        // 0x00305534
    uint32_t dci4_info11;        // 0x00305538
    uint32_t dci4_info12;        // 0x0030553c
    uint32_t dci5_out1;          // 0x00305540
    uint32_t dci5_out2;          // 0x00305544
    uint32_t dci5_pwr;           // 0x00305548
    uint32_t dci5_fa;            // 0x0030554c
    uint32_t dci5_info1;         // 0x00305550
    uint32_t dci5_info2;         // 0x00305554
    uint32_t dci5_info3;         // 0x00305558
    uint32_t dci5_info4;         // 0x0030555c
    uint32_t dci5_info5;         // 0x00305560
    uint32_t dci5_info6;         // 0x00305564
    uint32_t dci5_info7;         // 0x00305568
    uint32_t dci5_info8;         // 0x0030556c
    uint32_t dci5_info9;         // 0x00305570
    uint32_t dci5_info10;        // 0x00305574
    uint32_t dci5_info11;        // 0x00305578
    uint32_t dci5_info12;        // 0x0030557c
    uint32_t dci6_out1;          // 0x00305580
    uint32_t dci6_out2;          // 0x00305584
    uint32_t dci6_pwr;           // 0x00305588
    uint32_t dci6_fa;            // 0x0030558c
    uint32_t dci6_info1;         // 0x00305590
    uint32_t dci6_info2;         // 0x00305594
    uint32_t dci6_info3;         // 0x00305598
    uint32_t dci6_info4;         // 0x0030559c
    uint32_t dci6_info5;         // 0x003055a0
    uint32_t dci6_info6;         // 0x003055a4
    uint32_t dci6_info7;         // 0x003055a8
    uint32_t dci6_info8;         // 0x003055ac
    uint32_t dci6_info9;         // 0x003055b0
    uint32_t dci6_info10;        // 0x003055b4
    uint32_t dci6_info11;        // 0x003055b8
    uint32_t dci6_info12;        // 0x003055bc
    uint32_t dci7_out1;          // 0x003055c0
    uint32_t dci7_out2;          // 0x003055c4
    uint32_t dci7_pwr;           // 0x003055c8
    uint32_t dci7_fa;            // 0x003055cc
    uint32_t dci7_info1;         // 0x003055d0
    uint32_t dci7_info2;         // 0x003055d4
    uint32_t dci7_info3;         // 0x003055d8
    uint32_t dci7_info4;         // 0x003055dc
    uint32_t dci7_info5;         // 0x003055e0
    uint32_t dci7_info6;         // 0x003055e4
    uint32_t dci7_info7;         // 0x003055e8
    uint32_t dci7_info8;         // 0x003055ec
    uint32_t dci7_info9;         // 0x003055f0
    uint32_t dci7_info10;        // 0x003055f4
    uint32_t dci7_info11;        // 0x003055f8
    uint32_t dci7_info12;        // 0x003055fc
    uint32_t __3167744[2688];    // 0x00305600
    uint32_t pdcch_memdem;       // 0x00308000
    uint32_t __3178500[4095];    // 0x00308004
    uint32_t pdcch_memreg;       // 0x0030c000
    uint32_t __3194884[2047];    // 0x0030c004
    uint32_t pdcch_mempbchin;    // 0x0030e000
    uint32_t __3203076[255];     // 0x0030e004
    uint32_t mib0_out;           // 0x0030e400
    uint32_t mib0_info;          // 0x0030e404
    uint32_t mib1_out;           // 0x0030e408
    uint32_t mib1_info;          // 0x0030e40c
    uint32_t mib2_out;           // 0x0030e410
    uint32_t mib2_info;          // 0x0030e414
    uint32_t mib3_out;           // 0x0030e418
    uint32_t mib3_info;          // 0x0030e41c
    uint32_t __3204128[247544];  // 0x0030e420
    uint32_t hqmem11;            // 0x00400000
    uint32_t __4194308[3071];    // 0x00400004
    uint32_t hqmem12;            // 0x00403000
    uint32_t __4206596[29695];   // 0x00403004
    uint32_t hqmem21;            // 0x00420000
    uint32_t __4325380[8191];    // 0x00420004
    uint32_t hqmem22;            // 0x00428000
    uint32_t __4358148[8191];    // 0x00428004
    uint32_t hqmem23;            // 0x00430000
    uint32_t __4390916[8191];    // 0x00430004
    uint32_t hqmem24;            // 0x00438000
    uint32_t __4423684[204799];  // 0x00438004
    uint32_t tbmemin0;           // 0x00500000
    uint32_t __5242884[7167];    // 0x00500004
    uint32_t tbmemout0;          // 0x00507000
    uint32_t __5271556[9215];    // 0x00507004
    uint32_t tbmemin1;           // 0x00510000
    uint32_t __5308420[7167];    // 0x00510004
    uint32_t tbmemout1;          // 0x00517000
    uint32_t __5337092[9215];    // 0x00517004
    uint32_t pdsmemout0;         // 0x00520000
    uint32_t __5373956[383];     // 0x00520004
    uint32_t pdsmemout0_si;      // 0x00520600
    uint32_t __5375492[69];      // 0x00520604
    uint32_t pdsmemout0_pch;     // 0x00520718
    uint32_t __5375772[569];     // 0x0052071c
    uint32_t pdsmemout1;         // 0x00521000
    uint32_t __5378052[383];     // 0x00521004
    uint32_t pdsmemout1_si;      // 0x00521600
    uint32_t __5379588[69];      // 0x00521604
    uint32_t pdsmemout1_pch;     // 0x00521718
    uint32_t __5379868[227897];  // 0x0052171c
    uint32_t fftbuf0;            // 0x00600000
    uint32_t __6291460[16383];   // 0x00600004
    uint32_t fftbuf1;            // 0x00610000
    uint32_t __6356996[245759];  // 0x00610004
    uint32_t hqbuf;              // 0x00700000
} HWP_LDTC1_T;

#define hwp_ldtc1 ((HWP_LDTC1_T *)REG_ACCESS_ADDRESS(REG_LDTC1_BASE))

// csys_para_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fdd_tdd : 1;   // [0]
        uint32_t cp_ind : 1;    // [1]
        uint32_t ant_tx : 2;    // [3:2]
        uint32_t bw_ind : 3;    // [6:4]
        uint32_t uldl_conf : 3; // [9:7]
        uint32_t ss_conf : 4;   // [13:10]
        uint32_t tm_mode : 4;   // [17:14]
        uint32_t ng_ind : 2;    // [19:18]
        uint32_t bw_ind_ul : 3; // [22:20]
        uint32_t phi_dur : 1;   // [23]
        uint32_t phi_res : 2;   // [25:24]
        uint32_t schd_sib1 : 5; // [30:26]
        uint32_t __31_31 : 1;   // [31]
    } b;
} REG_LDTC1_CSYS_PARA_NXT_T;

// cnid_cell_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t nid_cell : 9; // [8:0]
        uint32_t __31_9 : 23;  // [31:9]
    } b;
} REG_LDTC1_CNID_CELL_NXT_T;

// dsys_para_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fdd_tdd : 1;   // [0]
        uint32_t cp_ind : 1;    // [1]
        uint32_t ant_tx : 2;    // [3:2]
        uint32_t bw_ind : 3;    // [6:4]
        uint32_t uldl_conf : 3; // [9:7]
        uint32_t ss_conf : 4;   // [13:10]
        uint32_t tm_mode : 4;   // [17:14]
        uint32_t ng_ind : 2;    // [19:18]
        uint32_t bw_ind_ul : 3; // [22:20]
        uint32_t __31_23 : 9;   // [31:23]
    } b;
} REG_LDTC1_DSYS_PARA_NXT_T;

// dnid_cell_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t nid_cell : 9; // [8:0]
        uint32_t __31_9 : 23;  // [31:9]
    } b;
} REG_LDTC1_DNID_CELL_NXT_T;

// ra_t_rnti
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ra_rnti : 16; // [15:0]
        uint32_t t_rnti : 16;  // [31:16]
    } b;
} REG_LDTC1_RA_T_RNTI_T;

// c_sps_rnti
typedef union {
    uint32_t v;
    struct
    {
        uint32_t c_rnti : 16;   // [15:0]
        uint32_t sps_rnti : 16; // [31:16]
    } b;
} REG_LDTC1_C_SPS_RNTI_T;

// tpc_rnti
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpcc_rnti : 16; // [15:0]
        uint32_t tpcs_rnti : 16; // [31:16]
    } b;
} REG_LDTC1_TPC_RNTI_T;

// g_rnti
typedef union {
    uint32_t v;
    struct
    {
        uint32_t g_rnti : 16;  // [15:0]
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_LDTC1_G_RNTI_T;

// csi_rsmap0_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_group1 : 12; // [11:0]
        uint32_t csirs_group2 : 12; // [23:12]
        uint32_t __31_24 : 8;       // [31:24]
    } b;
} REG_LDTC1_CSI_RSMAP0_NXT_T;

// csi_rsmap1_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_group3 : 12; // [11:0]
        uint32_t csirs_group4 : 12; // [23:12]
        uint32_t csirs_jump : 7;    // [30:24]
        uint32_t __31_31 : 1;       // [31]
    } b;
} REG_LDTC1_CSI_RSMAP1_NXT_T;

// pmi_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_cbsr : 16; // [15:0]
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_LDTC1_PMI_CFG_T;

// pcfi_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfi_val : 4; // [3:0]
        uint32_t __31_4 : 28; // [31:4]
    } b;
} REG_LDTC1_PCFI_CFG_NXT_T;

// phi_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t phi0_grpnum : 7; // [6:0]
        uint32_t phi0_seqnum : 3; // [9:7]
        uint32_t phi0_en : 1;     // [10]
        uint32_t phi1_grpnum : 7; // [17:11]
        uint32_t phi1_seqnum : 3; // [20:18]
        uint32_t phi1_en : 1;     // [21]
        uint32_t hi_cond : 2;     // [23:22]
        uint32_t __31_24 : 8;     // [31:24]
    } b;
} REG_LDTC1_PHI_CFG_NXT_T;

// pdcch_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pdcch_det_num : 3; // [2:0]
        uint32_t srs_act : 1;       // [3]
        uint32_t antsel_en : 1;     // [4]
        uint32_t csi_sel : 1;       // [5]
        uint32_t pus_enh : 1;       // [6]
        uint32_t dcilen_sel : 1;    // [7]
        uint32_t dcilen_comm0 : 6;  // [13:8]
        uint32_t dcilen_comm1 : 6;  // [19:14]
        uint32_t dcilen_ue0 : 6;    // [25:20]
        uint32_t dcilen_ue1 : 6;    // [31:26]
    } b;
} REG_LDTC1_PDCCH_CFG_NXT_T;

// pdsch0_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tbsize : 14;      // [13:0]
        uint32_t modu : 2;         // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_PDSCH0_CFG_NXT_T;

// pdsch1_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tbsize : 14;  // [13:0]
        uint32_t rv_sel : 2;   // [15:14]
        uint32_t ra_type : 1;  // [16]
        uint32_t __31_17 : 15; // [31:17]
    } b;
} REG_LDTC1_PDSCH1_CFG_NXT_T;

// pdsch2_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tbsize : 14;  // [13:0]
        uint32_t rv_sel : 2;   // [15:14]
        uint32_t ra_type : 1;  // [16]
        uint32_t __31_17 : 15; // [31:17]
    } b;
} REG_LDTC1_PDSCH2_CFG_NXT_T;

// frame_ccnt_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sf_cnt : 4;    // [3:0]
        uint32_t rf_cnt : 10;   // [13:4]
        uint32_t __15_14 : 2;   // [15:14]
        uint32_t ssfn_cnt : 16; // [31:16]
    } b;
} REG_LDTC1_FRAME_CCNT_NXT_T;

// frame_dcnt_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sf_cnt : 4;    // [3:0]
        uint32_t rf_cnt : 10;   // [13:4]
        uint32_t __15_14 : 2;   // [15:14]
        uint32_t ssfn_cnt : 16; // [31:16]
    } b;
} REG_LDTC1_FRAME_DCNT_NXT_T;

// ldtc1_cserv_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t si_rnti_en : 1;   // [0]
        uint32_t p_rnti_en : 1;    // [1]
        uint32_t ra_rnti_en : 1;   // [2]
        uint32_t c_rnti_en : 1;    // [3]
        uint32_t sps_rnti_en : 1;  // [4]
        uint32_t t_rnti_en : 1;    // [5]
        uint32_t tpcs_rnti_en : 1; // [6]
        uint32_t tpcc_rnti_en : 1; // [7]
        uint32_t g_rnti_en : 1;    // [8]
        uint32_t sc_rnti_en : 1;   // [9]
        uint32_t sc_n_rnti_en : 1; // [10]
        uint32_t __31_11 : 21;     // [31:11]
    } b;
} REG_LDTC1_LDTC1_CSERV_NXT_T;

// ldtc1_dserv_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t si_rnti_en : 1;  // [0]
        uint32_t p_rnti_en : 1;   // [1]
        uint32_t ra_rnti_en : 1;  // [2]
        uint32_t c_rnti_en : 1;   // [3]
        uint32_t sps_rnti_en : 1; // [4]
        uint32_t t_rnti_en : 1;   // [5]
        uint32_t g_rnti_en : 1;   // [6]
        uint32_t sc_rnti_en : 1;  // [7]
        uint32_t __31_8 : 24;     // [31:8]
    } b;
} REG_LDTC1_LDTC1_DSERV_NXT_T;

// ldtc1_cctrl_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pbch_en : 1;     // [0]
        uint32_t pdcch_en : 1;    // [1]
        uint32_t hi_en : 1;       // [2]
        uint32_t pmi_en : 1;      // [3]
        uint32_t sinr_en : 1;     // [4]
        uint32_t pbch_first : 1;  // [5]
        uint32_t cqfqt_ppsel : 2; // [7:6]
        uint32_t mbms_sf : 1;     // [8]
        uint32_t int_b_en : 1;    // [9]
        uint32_t int_c_en : 1;    // [10]
        uint32_t int_m_en : 1;    // [11]
        uint32_t int_s_en : 1;    // [12]
        uint32_t dma_m_en : 1;    // [13]
        uint32_t dma_s_en : 1;    // [14]
        uint32_t __31_15 : 17;    // [31:15]
    } b;
} REG_LDTC1_LDTC1_CCTRL_NXT_T;

// ldtc1_dctrl_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pdsch_en : 1;    // [0]
        uint32_t pds_first : 1;   // [1]
        uint32_t si_first : 1;    // [2]
        uint32_t sihqbuf_sel : 1; // [3]
        uint32_t csirs_en : 1;    // [4]
        uint32_t dqfqt_ppsel : 2; // [6:5]
        uint32_t int_d_en : 1;    // [7]
        uint32_t dma_d_en : 1;    // [8]
        uint32_t __31_9 : 23;     // [31:9]
    } b;
} REG_LDTC1_LDTC1_DCTRL_NXT_T;

// ldtc1_cstart
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ldtc_cstart : 1; // [0]
        uint32_t __31_1 : 31;     // [31:1]
    } b;
} REG_LDTC1_LDTC1_CSTART_T;

// ldtc1_dstart
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ldtc_dstart : 1; // [0]
        uint32_t __31_1 : 31;     // [31:1]
    } b;
} REG_LDTC1_LDTC1_DSTART_T;

// ctrl_flag
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_bflag : 1; // [0], write clear
        uint32_t int_cflag : 1; // [1], write clear
        uint32_t int_mflag : 1; // [2], write clear
        uint32_t int_sflag : 1; // [3], write clear
        uint32_t mib_valid : 4; // [7:4], write clear
        uint32_t dci_valid : 8; // [15:8], write clear
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_LDTC1_CTRL_FLAG_T;

// data_flag
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_dflag : 1;        // [0], write clear
        uint32_t pdsch_crc_flag : 1;   // [1], write clear
        uint32_t pdsch_zero_flag : 1;  // [2], write clear
        uint32_t si_crc_flag : 1;      // [3], write clear
        uint32_t si_zero_flag : 1;     // [4], write clear
        uint32_t paging_crc_flag : 1;  // [5], write clear
        uint32_t paging_zero_flag : 1; // [6], write clear
        uint32_t __31_7 : 25;          // [31:7]
    } b;
} REG_LDTC1_DATA_FLAG_T;

// buf_flag
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fftbuf_ind : 1;  // [0], read only
        uint32_t dschout_ind : 1; // [1], read only
        uint32_t cfh_ind : 1;     // [2], read only
        uint32_t dfh_ind : 1;     // [3], read only
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_BUF_FLAG_T;

// alg_comm_para
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ue_bund : 1;    // [0]
        uint32_t crs_fh_len : 1; // [1]
        uint32_t crs_g_len : 1;  // [2]
        uint32_t ctcg_sel : 1;   // [3]
        uint32_t subbw_sel : 1;  // [4]
        uint32_t sdgn_sel : 1;   // [5]
        uint32_t hqbit_sel : 1;  // [6]
        uint32_t cc_ir : 1;      // [7]
        uint32_t g_scale : 3;    // [10:8]
        uint32_t pdc_th : 6;     // [16:11]
        uint32_t __31_17 : 15;   // [31:17]
    } b;
} REG_LDTC1_ALG_COMM_PARA_T;

// che_fh_para
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fh16_bitsel : 4;      // [3:0]
        uint32_t fh10_bitsel : 3;      // [6:4]
        uint32_t fh10_bitsel_type : 1; // [7]
        uint32_t __31_8 : 24;          // [31:8]
    } b;
} REG_LDTC1_CHE_FH_PARA_T;

// che_th_para
typedef union {
    uint32_t v;
    struct
    {
        uint32_t th16_bitsel : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_CHE_TH_PARA_T;

// rbbm_pds03_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_03 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_PDS03_NXT_T;

// rbbm_pds13_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_13 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_PDS13_NXT_T;

// rbbm_si03_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_03 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_SI03_NXT_T;

// rbbm_si13_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_13 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_SI13_NXT_T;

// rbbm_pag03_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_03 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_PAG03_NXT_T;

// rbbm_pag13_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbbm_nxt_13 : 4; // [3:0]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_RBBM_PAG13_NXT_T;

// pmi_pds0_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_1 : 4; // [3:0]
        uint32_t pmi_2 : 4; // [7:4]
        uint32_t pmi_3 : 4; // [11:8]
        uint32_t pmi_4 : 4; // [15:12]
        uint32_t pmi_5 : 4; // [19:16]
        uint32_t pmi_6 : 4; // [23:20]
        uint32_t pmi_7 : 4; // [27:24]
        uint32_t pmi_8 : 4; // [31:28]
    } b;
} REG_LDTC1_PMI_PDS0_NXT_T;

// pmi_pds1_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_9 : 4;  // [3:0]
        uint32_t pmi_10 : 4; // [7:4]
        uint32_t pmi_11 : 4; // [11:8]
        uint32_t pmi_12 : 4; // [15:12]
        uint32_t pmi_13 : 4; // [19:16]
        uint32_t pmi_14 : 4; // [23:20]
        uint32_t pmi_15 : 4; // [27:24]
        uint32_t pmi_16 : 4; // [31:28]
    } b;
} REG_LDTC1_PMI_PDS1_NXT_T;

// pmi_pds2_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_17 : 4; // [3:0]
        uint32_t pmi_18 : 4; // [7:4]
        uint32_t pmi_19 : 4; // [11:8]
        uint32_t pmi_20 : 4; // [15:12]
        uint32_t pmi_21 : 4; // [19:16]
        uint32_t pmi_22 : 4; // [23:20]
        uint32_t pmi_23 : 4; // [27:24]
        uint32_t pmi_24 : 4; // [31:28]
    } b;
} REG_LDTC1_PMI_PDS2_NXT_T;

// pmi_pds3_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_25 : 4;  // [3:0]
        uint32_t __31_4 : 28; // [31:4]
    } b;
} REG_LDTC1_PMI_PDS3_NXT_T;

// spwr_wb_agc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t spwr_wb_agc : 10; // [9:0], read only
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_LDTC1_SPWR_WB_AGC_T;

// npwr_wb_agc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t npwr_wb_agc : 10; // [9:0], read only
        uint32_t __31_10 : 22;     // [31:10]
    } b;
} REG_LDTC1_NPWR_WB_AGC_T;

// sd_scaling_factor0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pbch_scale0 : 9;     // [8:0]
        uint32_t pbch_scale1 : 9;     // [17:9]
        uint32_t pbch_scale_sel : 1;  // [18]
        uint32_t pdcch_scale_sel : 1; // [19]
        uint32_t __31_20 : 12;        // [31:20]
    } b;
} REG_LDTC1_SD_SCALING_FACTOR0_T;

// sd_scaling_factor1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pdsch_scale0 : 12;   // [11:0]
        uint32_t pdsch_scale_sel : 1; // [12]
        uint32_t __31_13 : 19;        // [31:13]
    } b;
} REG_LDTC1_SD_SCALING_FACTOR1_T;

// sd_scaling_factor2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pdsch_scale1 : 12; // [11:0]
        uint32_t pdsch_scale2 : 12; // [23:12]
        uint32_t __31_24 : 8;       // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_FACTOR2_T;

// sd_scaling_factor3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pdsch_scale3 : 12; // [11:0]
        uint32_t pdsch_scale4 : 12; // [23:12]
        uint32_t __31_24 : 8;       // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_FACTOR3_T;

// sd_data_factor0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ucr_data_factor : 16; // [15:0]
        uint32_t cr_data_factor : 16;  // [31:16]
    } b;
} REG_LDTC1_SD_DATA_FACTOR0_T;

// sd_data_factor1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ucr_data_factor : 16; // [15:0]
        uint32_t cr_data_factor : 16;  // [31:16]
    } b;
} REG_LDTC1_SD_DATA_FACTOR1_T;

// sd_data_factor2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ucr_data_factor : 16; // [15:0]
        uint32_t cr_data_factor : 16;  // [31:16]
    } b;
} REG_LDTC1_SD_DATA_FACTOR2_T;

// cnoise_agc_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_agc : 10; // [9:0]
        uint32_t __31_10 : 22;   // [31:10]
    } b;
} REG_LDTC1_CNOISE_AGC_NXT_T;

// cnoise_th
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_th : 16; // [15:0]
        uint32_t __31_16 : 16;  // [31:16]
    } b;
} REG_LDTC1_CNOISE_TH_T;

// dnoise_agc_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_agc : 10; // [9:0]
        uint32_t __31_10 : 22;   // [31:10]
    } b;
} REG_LDTC1_DNOISE_AGC_NXT_T;

// dnoise_th
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_th1 : 16; // [15:0]
        uint32_t noise_th2 : 16; // [31:16]
    } b;
} REG_LDTC1_DNOISE_TH_T;

// sd_scaling_bcout0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bscale_out0 : 2; // [1:0], read only
        uint32_t bscale_out1 : 2; // [3:2], read only
        uint32_t bscale_out2 : 2; // [5:4], read only
        uint32_t bscale_out3 : 2; // [7:6], read only
        uint32_t cscale_out : 4;  // [11:8], read only
        uint32_t __31_12 : 20;    // [31:12]
    } b;
} REG_LDTC1_SD_SCALING_BCOUT0_T;

// sd_scaling_dout0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dscale_out0 : 3; // [2:0], read only
        uint32_t dscale_out1 : 3; // [5:3], read only
        uint32_t dscale_out2 : 3; // [8:6], read only
        uint32_t dscale_out3 : 3; // [11:9], read only
        uint32_t dscale_out4 : 3; // [14:12], read only
        uint32_t dscale_out5 : 3; // [17:15], read only
        uint32_t dscale_out6 : 3; // [20:18], read only
        uint32_t dscale_out7 : 3; // [23:21], read only
        uint32_t __31_24 : 8;     // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_DOUT0_T;

// sd_scaling_dout1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dscale_out8 : 3;  // [2:0], read only
        uint32_t dscale_out9 : 3;  // [5:3], read only
        uint32_t dscale_out10 : 3; // [8:6], read only
        uint32_t dscale_out11 : 3; // [11:9], read only
        uint32_t dscale_out12 : 3; // [14:12], read only
        uint32_t dscale_out13 : 3; // [17:15], read only
        uint32_t dscale_out14 : 3; // [20:18], read only
        uint32_t dscale_out15 : 3; // [23:21], read only
        uint32_t __31_24 : 8;      // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_DOUT1_T;

// sd_scaling_dout2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dscale_out16 : 3; // [2:0], read only
        uint32_t dscale_out17 : 3; // [5:3], read only
        uint32_t dscale_out18 : 3; // [8:6], read only
        uint32_t dscale_out19 : 3; // [11:9], read only
        uint32_t dscale_out20 : 3; // [14:12], read only
        uint32_t dscale_out21 : 3; // [17:15], read only
        uint32_t dscale_out22 : 3; // [20:18], read only
        uint32_t dscale_out23 : 3; // [23:21], read only
        uint32_t __31_24 : 8;      // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_DOUT2_T;

// sd_scaling_dout3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dscale_out24 : 3; // [2:0], read only
        uint32_t dscale_out25 : 3; // [5:3], read only
        uint32_t dscale_out26 : 3; // [8:6], read only
        uint32_t dscale_out27 : 3; // [11:9], read only
        uint32_t dscale_out28 : 3; // [14:12], read only
        uint32_t dscale_out29 : 3; // [17:15], read only
        uint32_t dscale_out30 : 3; // [20:18], read only
        uint32_t dscale_out31 : 3; // [23:21], read only
        uint32_t __31_24 : 8;      // [31:24]
    } b;
} REG_LDTC1_SD_SCALING_DOUT3_T;

// sd_scaling_dout4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dscale_out32 : 3; // [2:0], read only
        uint32_t dscale_out33 : 3; // [5:3], read only
        uint32_t dscale_out34 : 3; // [8:6], read only
        uint32_t __31_9 : 23;      // [31:9]
    } b;
} REG_LDTC1_SD_SCALING_DOUT4_T;

// hq_hb_sta
typedef union {
    uint32_t v;
    struct
    {
        uint32_t hb0_sta : 1;  // [0], write clear
        uint32_t hb1_sta : 1;  // [1], write clear
        uint32_t hb2_sta : 1;  // [2], write clear
        uint32_t hb3_sta : 1;  // [3], write clear
        uint32_t hb4_sta : 1;  // [4], write clear
        uint32_t hb5_sta : 1;  // [5], write clear
        uint32_t hb6_sta : 1;  // [6], write clear
        uint32_t hb7_sta : 1;  // [7], write clear
        uint32_t hb8_sta : 1;  // [8], write clear
        uint32_t hb9_sta : 1;  // [9], write clear
        uint32_t hb10_sta : 1; // [10], write clear
        uint32_t hb11_sta : 1; // [11], write clear
        uint32_t hb12_sta : 1; // [12], write clear
        uint32_t hb13_sta : 1; // [13], write clear
        uint32_t hb14_sta : 1; // [14], write clear
        uint32_t hb15_sta : 1; // [15], write clear
        uint32_t __31_16 : 16; // [31:16]
    } b;
} REG_LDTC1_HQ_HB_STA_T;

// hq_hb_proc0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t hb0_proc : 4; // [3:0], read only
        uint32_t hb1_proc : 4; // [7:4], read only
        uint32_t hb2_proc : 4; // [11:8], read only
        uint32_t hb3_proc : 4; // [15:12], read only
        uint32_t hb4_proc : 4; // [19:16], read only
        uint32_t hb5_proc : 4; // [23:20], read only
        uint32_t hb6_proc : 4; // [27:24], read only
        uint32_t hb7_proc : 4; // [31:28], read only
    } b;
} REG_LDTC1_HQ_HB_PROC0_T;

// hq_hb_proc1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t hb8_proc : 4;  // [3:0], read only
        uint32_t hb9_proc : 4;  // [7:4], read only
        uint32_t hb10_proc : 4; // [11:8], read only
        uint32_t hb11_proc : 4; // [15:12], read only
        uint32_t hb12_proc : 4; // [19:16], read only
        uint32_t hb13_proc : 4; // [23:20], read only
        uint32_t hb14_proc : 4; // [27:24], read only
        uint32_t hb15_proc : 4; // [31:28], read only
    } b;
} REG_LDTC1_HQ_HB_PROC1_T;

// turbo_para
typedef union {
    uint32_t v;
    struct
    {
        uint32_t iter_num_max : 4;   // [3:0]
        uint32_t shift_iternum1 : 4; // [7:4]
        uint32_t shift_iternum2 : 4; // [11:8]
        uint32_t shift_en0 : 1;      // [12]
        uint32_t shift_en1 : 1;      // [13]
        uint32_t shift_en2 : 1;      // [14]
        uint32_t norm_en0 : 1;       // [15]
        uint32_t norm_en1 : 1;       // [16]
        uint32_t norm_en2 : 1;       // [17]
        uint32_t __31_18 : 14;       // [31:18]
    } b;
} REG_LDTC1_TURBO_PARA_T;

// turbo_iter
typedef union {
    uint32_t v;
    struct
    {
        uint32_t real_iter0 : 4; // [3:0], read only
        uint32_t real_iter1 : 4; // [7:4], read only
        uint32_t real_iter2 : 4; // [11:8], read only
        uint32_t real_iter3 : 4; // [15:12], read only
        uint32_t __31_16 : 16;   // [31:16]
    } b;
} REG_LDTC1_TURBO_ITER_T;

// vit_par
typedef union {
    uint32_t v;
    struct
    {
        uint32_t vit_itnum : 2; // [1:0]
        uint32_t intv_en : 1;   // [2]
        uint32_t dmav_en : 1;   // [3]
        uint32_t crc_type : 1;  // [4]
        uint32_t mask_en : 1;   // [5]
        uint32_t __31_6 : 26;   // [31:6]
    } b;
} REG_LDTC1_VIT_PAR_T;

// vit_faconf
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fa_th : 8;     // [7:0]
        uint32_t fa_en : 1;     // [8]
        uint32_t __15_9 : 7;    // [15:9]
        uint32_t crc_mask : 16; // [31:16]
    } b;
} REG_LDTC1_VIT_FACONF_T;

// vit_len
typedef union {
    uint32_t v;
    struct
    {
        uint32_t vit_len : 10; // [9:0]
        uint32_t __31_10 : 22; // [31:10]
    } b;
} REG_LDTC1_VIT_LEN_T;

// vit_start
typedef union {
    uint32_t v;
    struct
    {
        uint32_t vit_start : 1; // [0]
        uint32_t __31_1 : 31;   // [31:1]
    } b;
} REG_LDTC1_VIT_START_T;

// vit_flag
typedef union {
    uint32_t v;
    struct
    {
        uint32_t int_vflag : 1;       // [0], write clear
        uint32_t vit_crc_flag : 1;    // [1], write clear
        uint32_t pdsch_zero_flag : 1; // [2], write clear
        uint32_t __31_3 : 29;         // [31:3]
    } b;
} REG_LDTC1_VIT_FLAG_T;

// vit_faout
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0], read only
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_VIT_FAOUT_T;

// cfi_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfi_out : 3; // [2:0], read only
        uint32_t __31_3 : 29; // [31:3]
    } b;
} REG_LDTC1_CFI_OUT_T;

// hi_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t hi0_out : 1; // [0], read only
        uint32_t hi1_out : 1; // [1], read only
        uint32_t __31_2 : 30; // [31:2]
    } b;
} REG_LDTC1_HI_OUT_T;

// pds_rep_num
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pds0_rep_num : 2;  // [1:0], read only
        uint32_t pds1_rep_num : 2;  // [3:2], read only
        uint32_t pds2_rep_num : 2;  // [5:4], read only
        uint32_t pds3_rep_num : 2;  // [7:6], read only
        uint32_t pds4_rep_num : 2;  // [9:8], read only
        uint32_t pds5_rep_num : 2;  // [11:10], read only
        uint32_t pds6_rep_num : 2;  // [13:12], read only
        uint32_t pds7_rep_num : 2;  // [15:14], read only
        uint32_t pds8_rep_num : 2;  // [17:16], read only
        uint32_t pds9_rep_num : 2;  // [19:18], read only
        uint32_t pds10_rep_num : 2; // [21:20], read only
        uint32_t pds11_rep_num : 2; // [23:22], read only
        uint32_t pds12_rep_num : 2; // [25:24], read only
        uint32_t pds13_rep_num : 2; // [27:26], read only
        uint32_t pds14_rep_num : 2; // [29:28], read only
        uint32_t pds15_rep_num : 2; // [31:30], read only
    } b;
} REG_LDTC1_PDS_REP_NUM_T;

// si_rep_num
typedef union {
    uint32_t v;
    struct
    {
        uint32_t si0_rep_num : 2; // [1:0], read only
        uint32_t si1_rep_num : 2; // [3:2], read only
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_LDTC1_SI_REP_NUM_T;

// pbch_rep_num
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pbch_rep_num : 2; // [1:0], read only
        uint32_t __31_2 : 30;      // [31:2]
    } b;
} REG_LDTC1_PBCH_REP_NUM_T;

// rtctrl_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rtctrl_cfg : 18; // [17:0]
        uint32_t __31_18 : 14;    // [31:18]
    } b;
} REG_LDTC1_RTCTRL_CFG_T;

// cabis_enbl_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_sdben : 1;   // [0]
        uint32_t cabis_sdcen : 1;   // [1]
        uint32_t cabis_sdden : 1;   // [2]
        uint32_t cabis_en : 1;      // [3]
        uint32_t cabis_sel : 1;     // [4]
        uint32_t cmc_en : 1;        // [5]
        uint32_t abis_portsel0 : 2; // [7:6]
        uint32_t abis_portsel1 : 2; // [9:8]
        uint32_t abis_portsel2 : 2; // [11:10]
        uint32_t __31_12 : 20;      // [31:12]
    } b;
} REG_LDTC1_CABIS_ENBL_NXT_T;

// cabis_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_cellid_next1 : 9; // [8:0]
        uint32_t cabis_cellid_next2 : 9; // [17:9]
        uint32_t cabis_nrb_next1 : 3;    // [20:18]
        uint32_t cabis_nrb_next2 : 3;    // [23:21]
        uint32_t cabis_txnum_next1 : 2;  // [25:24]
        uint32_t cabis_txnum_next2 : 2;  // [27:26]
        uint32_t cabis_num : 2;          // [29:28]
        uint32_t __31_30 : 2;            // [31:30]
    } b;
} REG_LDTC1_CABIS_CFG_NXT_T;

// cabis_dly1_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_dly_next1 : 19; // [18:0]
        uint32_t __31_19 : 13;         // [31:19]
    } b;
} REG_LDTC1_CABIS_DLY1_NXT_T;

// cabis_dly2_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_dly_next2 : 19; // [18:0]
        uint32_t __31_19 : 13;         // [31:19]
    } b;
} REG_LDTC1_CABIS_DLY2_NXT_T;

// cabis_shft_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_shft_next1 : 4; // [3:0], read only
        uint32_t cabis_shft_next2 : 4; // [7:4], read only
        uint32_t cabis_shft_next3 : 4; // [11:8], read only
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_LDTC1_CABIS_SHFT_NXT_T;

// dabis_enbl_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_sdben : 1;   // [0]
        uint32_t dabis_sdcen : 1;   // [1]
        uint32_t dabis_sdden : 1;   // [2]
        uint32_t dabis_en : 1;      // [3]
        uint32_t dabis_sel : 1;     // [4]
        uint32_t abis_portsel0 : 2; // [6:5]
        uint32_t abis_portsel1 : 2; // [8:7]
        uint32_t abis_portsel2 : 2; // [10:9]
        uint32_t __31_11 : 21;      // [31:11]
    } b;
} REG_LDTC1_DABIS_ENBL_NXT_T;

// dabis_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_cellid_next1 : 9; // [8:0]
        uint32_t dabis_cellid_next2 : 9; // [17:9]
        uint32_t dabis_nrb_next1 : 3;    // [20:18]
        uint32_t dabis_nrb_next2 : 3;    // [23:21]
        uint32_t dabis_txnum_next1 : 2;  // [25:24]
        uint32_t dabis_txnum_next2 : 2;  // [27:26]
        uint32_t dabis_num : 2;          // [29:28]
        uint32_t __31_30 : 2;            // [31:30]
    } b;
} REG_LDTC1_DABIS_CFG_NXT_T;

// dabis_dly1_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_dly_next1 : 19; // [18:0]
        uint32_t __31_19 : 13;         // [31:19]
    } b;
} REG_LDTC1_DABIS_DLY1_NXT_T;

// dabis_dly2_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_dly_next2 : 19; // [18:0]
        uint32_t __31_19 : 13;         // [31:19]
    } b;
} REG_LDTC1_DABIS_DLY2_NXT_T;

// dabis_shft_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_shft_next1 : 4; // [3:0], read only
        uint32_t dabis_shft_next2 : 4; // [7:4], read only
        uint32_t dabis_shft_next3 : 4; // [11:8], read only
        uint32_t __31_12 : 20;         // [31:12]
    } b;
} REG_LDTC1_DABIS_SHFT_NXT_T;

// reis_conf
typedef union {
    uint32_t v;
    struct
    {
        uint32_t reis_num : 4; // [3:0]
        uint32_t reis_en : 1;  // [4]
        uint32_t __31_5 : 27;  // [31:5]
    } b;
} REG_LDTC1_REIS_CONF_T;

// reis_pos0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t reis_re0 : 11;   // [10:0]
        uint32_t __11_11 : 1;     // [11]
        uint32_t reis_shift0 : 4; // [15:12]
        uint32_t reis_re1 : 11;   // [26:16]
        uint32_t __27_27 : 1;     // [27]
        uint32_t reis_shift1 : 4; // [31:28]
    } b;
} REG_LDTC1_REIS_POS0_T;

// reis_pos1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t reis_re2 : 11;   // [10:0]
        uint32_t __11_11 : 1;     // [11]
        uint32_t reis_shift2 : 4; // [15:12]
        uint32_t reis_re3 : 11;   // [26:16]
        uint32_t __27_27 : 1;     // [27]
        uint32_t reis_shift3 : 4; // [31:28]
    } b;
} REG_LDTC1_REIS_POS1_T;

// reis_pos2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t reis_re4 : 11;   // [10:0]
        uint32_t __11_11 : 1;     // [11]
        uint32_t reis_shift4 : 4; // [15:12]
        uint32_t reis_re5 : 11;   // [26:16]
        uint32_t __27_27 : 1;     // [27]
        uint32_t reis_shift5 : 4; // [31:28]
    } b;
} REG_LDTC1_REIS_POS2_T;

// reis_pos3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t reis_re6 : 11;   // [10:0]
        uint32_t __11_11 : 1;     // [11]
        uint32_t reis_shift6 : 4; // [15:12]
        uint32_t reis_re7 : 11;   // [26:16]
        uint32_t __27_27 : 1;     // [27]
        uint32_t reis_shift7 : 4; // [31:28]
    } b;
} REG_LDTC1_REIS_POS3_T;

// rbis_par
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbis_factor : 16; // [15:0]
        uint32_t rbis_dipos : 7;   // [22:16]
        uint32_t rbis_num : 3;     // [25:23]
        uint32_t rbis_posen : 1;   // [26]
        uint32_t rbis_sdben : 1;   // [27]
        uint32_t rbis_sdcen : 1;   // [28]
        uint32_t rbis_sdden : 1;   // [29]
        uint32_t rbis_en : 1;      // [30]
        uint32_t rbis_portsel : 1; // [31]
    } b;
} REG_LDTC1_RBIS_PAR_T;

// rbis_posout0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbis_posout0 : 7; // [6:0], read only
        uint32_t rbis_posout1 : 7; // [13:7], read only
        uint32_t rbis_posout2 : 7; // [20:14], read only
        uint32_t rbis_posout3 : 7; // [27:21], read only
        uint32_t __31_28 : 4;      // [31:28]
    } b;
} REG_LDTC1_RBIS_POSOUT0_T;

// rbis_posout1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbis_posout4 : 7; // [6:0], read only
        uint32_t __31_7 : 25;      // [31:7]
    } b;
} REG_LDTC1_RBIS_POSOUT1_T;

// rbis_max
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rbis_max : 25; // [24:0], read only
        uint32_t __31_25 : 7;   // [31:25]
    } b;
} REG_LDTC1_RBIS_MAX_T;

// pbml_cfg_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t llr_alpha : 8;   // [7:0]
        uint32_t llr_pos_sta : 6; // [13:8]
        uint32_t llr_cal_len : 6; // [19:14]
        uint32_t pbml_en : 1;     // [20]
        uint32_t __31_21 : 11;    // [31:21]
    } b;
} REG_LDTC1_PBML_CFG_NXT_T;

// ctrl_state
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ctrl_state : 26; // [25:0], read only
        uint32_t __31_26 : 6;     // [31:26]
    } b;
} REG_LDTC1_CTRL_STATE_T;

// data_state
typedef union {
    uint32_t v;
    struct
    {
        uint32_t data_state : 26; // [25:0], read only
        uint32_t __31_26 : 6;     // [31:26]
    } b;
} REG_LDTC1_DATA_STATE_T;

// frame_ccnt_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sf_cnt : 4;    // [3:0], read only
        uint32_t rf_cnt : 10;   // [13:4], read only
        uint32_t __15_14 : 2;   // [15:14]
        uint32_t ssfn_cnt : 16; // [31:16], read only
    } b;
} REG_LDTC1_FRAME_CCNT_OUT_T;

// frame_dcnt_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sf_cnt : 4;    // [3:0], read only
        uint32_t rf_cnt : 10;   // [13:4], read only
        uint32_t __15_14 : 2;   // [15:14]
        uint32_t ssfn_cnt : 16; // [31:16], read only
    } b;
} REG_LDTC1_FRAME_DCNT_OUT_T;

// pds0_harqin0_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pds_ini0 : 10; // [9:0], read only
        uint32_t __15_10 : 6;   // [15:10]
        uint32_t pds_len0 : 10; // [25:16], read only
        uint32_t __31_26 : 6;   // [31:26]
    } b;
} REG_LDTC1_PDS0_HARQIN0_INFO_T;

// pds0_harqin1_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pds_ini1 : 13; // [12:0], read only
        uint32_t __15_13 : 3;   // [15:13]
        uint32_t pds_e0 : 16;   // [31:16], read only
    } b;
} REG_LDTC1_PDS0_HARQIN1_INFO_T;

// pds1_harqin0_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pds_ini0 : 10; // [9:0], read only
        uint32_t __15_10 : 6;   // [15:10]
        uint32_t pds_len0 : 10; // [25:16], read only
        uint32_t __31_26 : 6;   // [31:26]
    } b;
} REG_LDTC1_PDS1_HARQIN0_INFO_T;

// pds1_harqin1_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pds_ini1 : 13; // [12:0], read only
        uint32_t __15_13 : 3;   // [15:13]
        uint32_t pds_e0 : 16;   // [31:16], read only
    } b;
} REG_LDTC1_PDS1_HARQIN1_INFO_T;

// si_harqin0_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t si_ini0 : 10; // [9:0], read only
        uint32_t __15_10 : 6;  // [15:10]
        uint32_t si_len0 : 10; // [25:16], read only
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_SI_HARQIN0_INFO_T;

// si_harqin1_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t si_ini1 : 13; // [12:0], read only
        uint32_t __15_13 : 3;  // [15:13]
        uint32_t si_e0 : 16;   // [31:16], read only
    } b;
} REG_LDTC1_SI_HARQIN1_INFO_T;

// pag_harqin0_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pag_ini0 : 10; // [9:0], read only
        uint32_t __15_10 : 6;   // [15:10]
        uint32_t pag_len0 : 10; // [25:16], read only
        uint32_t __31_26 : 6;   // [31:26]
    } b;
} REG_LDTC1_PAG_HARQIN0_INFO_T;

// pag_harqin1_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pag_ini1 : 13; // [12:0], read only
        uint32_t __15_13 : 3;   // [15:13]
        uint32_t pag_e0 : 16;   // [31:16], read only
    } b;
} REG_LDTC1_PAG_HARQIN1_INFO_T;

// cabis_shft_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cabis_shft1 : 4; // [3:0], read only
        uint32_t cabis_shft2 : 4; // [7:4], read only
        uint32_t cabis_shft3 : 4; // [11:8], read only
        uint32_t __31_12 : 20;    // [31:12]
    } b;
} REG_LDTC1_CABIS_SHFT_OUT_T;

// dabis_shft_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dabis_shft1 : 4; // [3:0], read only
        uint32_t dabis_shft2 : 4; // [7:4], read only
        uint32_t dabis_shft3 : 4; // [11:8], read only
        uint32_t __31_12 : 20;    // [31:12]
    } b;
} REG_LDTC1_DABIS_SHFT_OUT_T;

// mc_dly1_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mc_dly1 : 19; // [18:0]
        uint32_t __31_19 : 13; // [31:19]
    } b;
} REG_LDTC1_MC_DLY1_NXT_T;

// mc_dly2_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mc_dly2 : 19; // [18:0]
        uint32_t __31_19 : 13; // [31:19]
    } b;
} REG_LDTC1_MC_DLY2_NXT_T;

// mc_dlyth_nxt
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mc_dlyth : 10; // [9:0]
        uint32_t __31_10 : 22;  // [31:10]
    } b;
} REG_LDTC1_MC_DLYTH_NXT_T;

// cfhmem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfhmem1 : 30; // [29:0]
        uint32_t __31_30 : 2;  // [31:30]
    } b;
} REG_LDTC1_CFHMEM1_T;

// cfhmem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfhmem2 : 30; // [29:0]
        uint32_t __31_30 : 2;  // [31:30]
    } b;
} REG_LDTC1_CFHMEM2_T;

// crsmem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;       // [3:0]
        uint32_t crsmem1_im : 12; // [15:4]
        uint32_t __19_16 : 4;     // [19:16]
        uint32_t crsmem1_re : 12; // [31:20]
    } b;
} REG_LDTC1_CRSMEM1_T;

// crsmem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;       // [3:0]
        uint32_t crsmem2_im : 12; // [15:4]
        uint32_t __19_16 : 4;     // [19:16]
        uint32_t crsmem2_re : 12; // [31:20]
    } b;
} REG_LDTC1_CRSMEM2_T;

// clsmem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;      // [3:0]
        uint32_t clsmem_im : 12; // [15:4]
        uint32_t __19_16 : 4;    // [19:16]
        uint32_t clsmem_re : 12; // [31:20]
    } b;
} REG_LDTC1_CLSMEM_T;

// ursmem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;      // [3:0]
        uint32_t ursmem_im : 12; // [15:4]
        uint32_t __19_16 : 4;    // [19:16]
        uint32_t ursmem_re : 12; // [31:20]
    } b;
} REG_LDTC1_URSMEM_T;

// ulsmem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;      // [3:0]
        uint32_t ulsmem_im : 12; // [15:4]
        uint32_t __19_16 : 4;    // [19:16]
        uint32_t ulsmem_re : 12; // [31:20]
    } b;
} REG_LDTC1_ULSMEM_T;

// cell_qfmem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;           // [2:0]
        uint32_t cell_qfmem1_im : 13; // [15:3]
        uint32_t __18_16 : 3;         // [18:16]
        uint32_t cell_qfmem1_re : 13; // [31:19]
    } b;
} REG_LDTC1_CELL_QFMEM1_T;

// cell_qfmem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;           // [2:0]
        uint32_t cell_qfmem2_im : 13; // [15:3]
        uint32_t __18_16 : 3;         // [18:16]
        uint32_t cell_qfmem2_re : 13; // [31:19]
    } b;
} REG_LDTC1_CELL_QFMEM2_T;

// ct_qtmem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem1_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem1_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM1_T;

// ct_qtmem1_p01_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem1_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem1_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM1_P01_TAP2_T;

// ct_qtmem1_p01_tap3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem1_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem1_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM1_P01_TAP3_T;

// ct_qtmem1_p23_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem1_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem1_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM1_P23_TAP2_T;

// ct_qtmem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem2_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem2_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM2_T;

// ct_qtmem2_p01_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem2_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem2_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM2_P01_TAP2_T;

// ct_qtmem2_p01_tap3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem2_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem2_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM2_P01_TAP3_T;

// ct_qtmem2_p23_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem2_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem2_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM2_P23_TAP2_T;

// dt_qtmem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t dt_qtmem1_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t dt_qtmem1_2 : 13; // [31:19]
    } b;
} REG_LDTC1_DT_QTMEM1_T;

// dt_qtmem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t dt_qtmem2_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t dt_qtmem2_2 : 13; // [31:19]
    } b;
} REG_LDTC1_DT_QTMEM2_T;

// agc_cls_mem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;          // [5:0]
        uint32_t agc_cls_mem_1 : 10; // [15:6]
        uint32_t __21_16 : 6;        // [21:16]
        uint32_t agc_cls_mem_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_CLS_MEM_T;

// agc_uls_mem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;          // [5:0]
        uint32_t agc_uls_mem_1 : 10; // [15:6]
        uint32_t __21_16 : 6;        // [21:16]
        uint32_t agc_uls_mem_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_ULS_MEM_T;

// agc_cfh_mem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;           // [5:0]
        uint32_t agc_cfh_mem1_1 : 10; // [15:6]
        uint32_t __21_16 : 6;         // [21:16]
        uint32_t agc_cfh_mem1_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_CFH_MEM1_T;

// agc_cfh_mem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;           // [5:0]
        uint32_t agc_cfh_mem2_1 : 10; // [15:6]
        uint32_t __21_16 : 6;         // [21:16]
        uint32_t agc_cfh_mem2_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_CFH_MEM2_T;

// agc_ufh_mem1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;           // [5:0]
        uint32_t agc_ufh_mem1_1 : 10; // [15:6]
        uint32_t __21_16 : 6;         // [21:16]
        uint32_t agc_ufh_mem1_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_UFH_MEM1_T;

// agc_ufh_mem2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;           // [5:0]
        uint32_t agc_ufh_mem2_1 : 10; // [15:6]
        uint32_t __21_16 : 6;         // [21:16]
        uint32_t agc_ufh_mem2_2 : 10; // [31:22]
    } b;
} REG_LDTC1_AGC_UFH_MEM2_T;

// ufhmem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ufhmem : 30; // [29:0]
        uint32_t __31_30 : 2; // [31:30]
    } b;
} REG_LDTC1_UFHMEM_T;

// csi_in_mem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __3_0 : 4;      // [3:0]
        uint32_t csimem_im : 12; // [15:4]
        uint32_t __19_16 : 4;    // [19:16]
        uint32_t csimem_re : 12; // [31:20]
    } b;
} REG_LDTC1_CSI_IN_MEM_T;

// pmi_mem_sb
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pmi_prb96 : 4; // [3:0]
        uint32_t pmi_prb97 : 4; // [7:4]
        uint32_t pmi_prb98 : 4; // [11:8]
        uint32_t pmi_prb99 : 4; // [15:12]
        uint32_t pmi_sb1 : 4;   // [19:16]
        uint32_t pmi_sb2 : 4;   // [23:20]
        uint32_t pmi_sb3 : 4;   // [27:24]
        uint32_t pmi_sb4 : 4;   // [31:28]
    } b;
} REG_LDTC1_PMI_MEM_SB_T;

// cell_qfmem3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;          // [2:0]
        uint32_t cell_qfmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;        // [18:16]
        uint32_t cell_qfmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CELL_QFMEM3_T;

// ct_qtmem3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM3_T;

// ct_qtmem3_p01_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM3_P01_TAP2_T;

// ct_qtmem3_p01_tap3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM3_P01_TAP3_T;

// ct_qtmem3_p23_tap2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t ct_qtmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t ct_qtmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_CT_QTMEM3_P23_TAP2_T;

// dt_qtmem3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;        // [2:0]
        uint32_t dt_qtmem3_1 : 13; // [15:3]
        uint32_t __18_16 : 3;      // [18:16]
        uint32_t dt_qtmem3_2 : 13; // [31:19]
    } b;
} REG_LDTC1_DT_QTMEM3_T;

// sdmemcg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemcg0 : 21; // [31:11]
    } b;
} REG_LDTC1_SDMEMCG0_T;

// sdmemcg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemcg1 : 21; // [31:11]
    } b;
} REG_LDTC1_SDMEMCG1_T;

// sdmemdg0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemdg0 : 21; // [31:11]
    } b;
} REG_LDTC1_SDMEMDG0_T;

// sdmemdg1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemdg1 : 21; // [31:11]
    } b;
} REG_LDTC1_SDMEMDG1_T;

// sdmemdg2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemdg2 : 21; // [31:11], read only
    } b;
} REG_LDTC1_SDMEMDG2_T;

// sdmemdg3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __10_0 : 11;   // [10:0]
        uint32_t sdmemdg3 : 21; // [31:11], read only
    } b;
} REG_LDTC1_SDMEMDG3_T;

// pdcch_memin
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __4_0 : 5;          // [4:0]
        uint32_t pdcch_memin_1 : 11; // [15:5]
        uint32_t __20_16 : 5;        // [20:16]
        uint32_t pdcch_memin_2 : 11; // [31:21]
    } b;
} REG_LDTC1_PDCCH_MEMIN_T;

// dci0_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI0_PWR_T;

// dci0_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI0_FA_T;

// dci0_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI0_INFO1_T;

// dci0_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI0_INFO2_T;

// dci0_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI0_INFO3_T;

// dci0_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI0_INFO4_T;

// dci0_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI0_INFO8_T;

// dci0_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI0_INFO12_T;

// dci1_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI1_PWR_T;

// dci1_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI1_FA_T;

// dci1_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI1_INFO1_T;

// dci1_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI1_INFO2_T;

// dci1_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI1_INFO3_T;

// dci1_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI1_INFO4_T;

// dci1_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI1_INFO8_T;

// dci1_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI1_INFO12_T;

// dci2_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI2_PWR_T;

// dci2_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI2_FA_T;

// dci2_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI2_INFO1_T;

// dci2_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI2_INFO2_T;

// dci2_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI2_INFO3_T;

// dci2_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI2_INFO4_T;

// dci2_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI2_INFO8_T;

// dci2_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI2_INFO12_T;

// dci3_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI3_PWR_T;

// dci3_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI3_FA_T;

// dci3_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI3_INFO1_T;

// dci3_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI3_INFO2_T;

// dci3_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI3_INFO3_T;

// dci3_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI3_INFO4_T;

// dci3_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI3_INFO8_T;

// dci3_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI3_INFO12_T;

// dci4_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI4_PWR_T;

// dci4_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI4_FA_T;

// dci4_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI4_INFO1_T;

// dci4_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI4_INFO2_T;

// dci4_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI4_INFO3_T;

// dci4_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI4_INFO4_T;

// dci4_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI4_INFO8_T;

// dci4_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI4_INFO12_T;

// dci5_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI5_PWR_T;

// dci5_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI5_FA_T;

// dci5_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI5_INFO1_T;

// dci5_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI5_INFO2_T;

// dci5_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI5_INFO3_T;

// dci5_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI5_INFO4_T;

// dci5_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI5_INFO8_T;

// dci5_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI5_INFO12_T;

// dci6_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI6_PWR_T;

// dci6_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI6_FA_T;

// dci6_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI6_INFO1_T;

// dci6_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI6_INFO2_T;

// dci6_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI6_INFO3_T;

// dci6_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI6_INFO4_T;

// dci6_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI6_INFO8_T;

// dci6_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI6_INFO12_T;

// dci7_pwr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_pwr : 26; // [25:0]
        uint32_t __31_26 : 6;  // [31:26]
    } b;
} REG_LDTC1_DCI7_PWR_T;

// dci7_fa
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_fa : 8;      // [7:0]
        uint32_t dci_fa_zero : 8; // [15:8]
        uint32_t __31_16 : 16;    // [31:16]
    } b;
} REG_LDTC1_DCI7_FA_T;

// dci7_info1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dci_len : 6;    // [5:0]
        uint32_t dci_llevel : 3; // [8:6]
        uint32_t dci_stapos : 7; // [15:9]
        uint32_t comm_ue : 1;    // [16]
        uint32_t rnti_ind : 4;   // [20:17]
        uint32_t dci_type : 4;   // [24:21]
        uint32_t sps_ind : 2;    // [26:25]
        uint32_t order_flag : 1; // [27]
        uint32_t ant_sel : 1;    // [28]
        uint32_t __31_29 : 3;    // [31:29]
    } b;
} REG_LDTC1_DCI7_INFO1_T;

// dci7_info2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tb_size : 14;     // [13:0]
        uint32_t modu_type : 2;    // [15:14]
        uint32_t rv_sel : 2;       // [17:16]
        uint32_t n_scid : 1;       // [18]
        uint32_t ra_type : 1;      // [19]
        uint32_t trans_scheme : 3; // [22:20]
        uint32_t pmi_indx : 4;     // [26:23]
        uint32_t hq_proc : 4;      // [30:27]
        uint32_t pmi_confm : 1;    // [31]
    } b;
} REG_LDTC1_DCI7_INFO2_T;

// dci7_info3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tpc_step : 2; // [1:0]
        uint32_t dai : 2;      // [3:2]
        uint32_t pwr_ofst : 1; // [4]
        uint32_t ndi_ind : 1;  // [5]
        uint32_t srs_req : 1;  // [6]
        uint32_t tb_cw : 1;    // [7]
        uint32_t cqi_indx : 2; // [9:8]
        uint32_t cs_dmrs : 3;  // [12:10]
        uint32_t cw2_flag : 1; // [13]
        uint32_t mcs : 5;      // [18:14]
        uint32_t rep : 3;      // [21:19]
        uint32_t __31_22 : 10; // [31:22]
    } b;
} REG_LDTC1_DCI7_INFO3_T;

// dci7_info4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rba : 13;        // [12:0]
        uint32_t rb_hop_flag : 1; // [13]
        uint32_t ra_type : 1;     // [14]
        uint32_t nul_fd : 17;     // [31:15]
    } b;
} REG_LDTC1_DCI7_INFO4_T;

// dci7_info8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_03 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI7_INFO8_T;

// dci7_info12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rb_bm_13 : 4; // [3:0]
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_LDTC1_DCI7_INFO12_T;

// pdcch_memdem
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __4_0 : 5;           // [4:0]
        uint32_t pdcch_memdem_1 : 11; // [15:5]
        uint32_t __20_16 : 5;         // [20:16]
        uint32_t pdcch_memdem_2 : 11; // [31:21]
    } b;
} REG_LDTC1_PDCCH_MEMDEM_T;

// pdcch_mempbchin
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __5_0 : 6;         // [5:0]
        uint32_t pbch_memin_1 : 10; // [15:6]
        uint32_t __21_16 : 6;       // [21:16]
        uint32_t pbch_memin_2 : 10; // [31:22]
    } b;
} REG_LDTC1_PDCCH_MEMPBCHIN_T;

// mib0_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib0_out : 24; // [23:0], read only
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_MIB0_OUT_T;

// mib0_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib0_info : 2; // [1:0], read only
        uint32_t __31_2 : 30;   // [31:2]
    } b;
} REG_LDTC1_MIB0_INFO_T;

// mib1_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib1_out : 24; // [23:0], read only
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_MIB1_OUT_T;

// mib1_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib1_info : 2; // [1:0], read only
        uint32_t __31_2 : 30;   // [31:2]
    } b;
} REG_LDTC1_MIB1_INFO_T;

// mib2_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib2_out : 24; // [23:0], read only
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_MIB2_OUT_T;

// mib2_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib2_info : 2; // [1:0], read only
        uint32_t __31_2 : 30;   // [31:2]
    } b;
} REG_LDTC1_MIB2_INFO_T;

// mib3_out
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib3_out : 24; // [23:0], read only
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_MIB3_OUT_T;

// mib3_info
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mib3_info : 2; // [1:0], read only
        uint32_t __31_2 : 30;   // [31:2]
    } b;
} REG_LDTC1_MIB3_INFO_T;

// hqmem11
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __2_0 : 3;      // [2:0]
        uint32_t hqmem11_1 : 13; // [15:3]
        uint32_t __18_16 : 3;    // [18:16]
        uint32_t hqmem11_2 : 13; // [31:19]
    } b;
} REG_LDTC1_HQMEM11_T;

// tbmemin0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tbmemin0 : 24; // [23:0]
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_TBMEMIN0_T;

// tbmemin1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t tbmemin1 : 24; // [23:0]
        uint32_t __31_24 : 8;   // [31:24]
    } b;
} REG_LDTC1_TBMEMIN1_T;

// csys_para_nxt
#define LDTC1_FDD_TDD (1 << 0)
#define LDTC1_CP_IND (1 << 1)
#define LDTC1_ANT_TX(n) (((n)&0x3) << 2)
#define LDTC1_BW_IND(n) (((n)&0x7) << 4)
#define LDTC1_ULDL_CONF(n) (((n)&0x7) << 7)
#define LDTC1_SS_CONF(n) (((n)&0xf) << 10)
#define LDTC1_TM_MODE(n) (((n)&0xf) << 14)
#define LDTC1_NG_IND(n) (((n)&0x3) << 18)
#define LDTC1_BW_IND_UL(n) (((n)&0x7) << 20)
#define LDTC1_PHI_DUR (1 << 23)
#define LDTC1_PHI_RES(n) (((n)&0x3) << 24)
#define LDTC1_SCHD_SIB1(n) (((n)&0x1f) << 26)

// cnid_cell_nxt
#define LDTC1_NID_CELL(n) (((n)&0x1ff) << 0)

// dsys_para_nxt
#define LDTC1_FDD_TDD (1 << 0)
#define LDTC1_CP_IND (1 << 1)
#define LDTC1_ANT_TX(n) (((n)&0x3) << 2)
#define LDTC1_BW_IND(n) (((n)&0x7) << 4)
#define LDTC1_ULDL_CONF(n) (((n)&0x7) << 7)
#define LDTC1_SS_CONF(n) (((n)&0xf) << 10)
#define LDTC1_TM_MODE(n) (((n)&0xf) << 14)
#define LDTC1_NG_IND(n) (((n)&0x3) << 18)
#define LDTC1_BW_IND_UL(n) (((n)&0x7) << 20)

// dnid_cell_nxt
#define LDTC1_NID_CELL(n) (((n)&0x1ff) << 0)

// ra_t_rnti
#define LDTC1_RA_RNTI(n) (((n)&0xffff) << 0)
#define LDTC1_T_RNTI(n) (((n)&0xffff) << 16)

// c_sps_rnti
#define LDTC1_C_RNTI(n) (((n)&0xffff) << 0)
#define LDTC1_SPS_RNTI(n) (((n)&0xffff) << 16)

// tpc_rnti
#define LDTC1_TPCC_RNTI(n) (((n)&0xffff) << 0)
#define LDTC1_TPCS_RNTI(n) (((n)&0xffff) << 16)

// g_rnti
#define LDTC1_G_RNTI(n) (((n)&0xffff) << 0)

// csi_rsmap0_nxt
#define LDTC1_CSIRS_GROUP1(n) (((n)&0xfff) << 0)
#define LDTC1_CSIRS_GROUP2(n) (((n)&0xfff) << 12)

// csi_rsmap1_nxt
#define LDTC1_CSIRS_GROUP3(n) (((n)&0xfff) << 0)
#define LDTC1_CSIRS_GROUP4(n) (((n)&0xfff) << 12)
#define LDTC1_CSIRS_JUMP(n) (((n)&0x7f) << 24)

// pmi_cfg
#define LDTC1_PMI_CBSR(n) (((n)&0xffff) << 0)

// pcfi_cfg_nxt
#define LDTC1_CFI_VAL(n) (((n)&0xf) << 0)

// phi_cfg_nxt
#define LDTC1_PHI0_GRPNUM(n) (((n)&0x7f) << 0)
#define LDTC1_PHI0_SEQNUM(n) (((n)&0x7) << 7)
#define LDTC1_PHI0_EN (1 << 10)
#define LDTC1_PHI1_GRPNUM(n) (((n)&0x7f) << 11)
#define LDTC1_PHI1_SEQNUM(n) (((n)&0x7) << 18)
#define LDTC1_PHI1_EN (1 << 21)
#define LDTC1_HI_COND(n) (((n)&0x3) << 22)

// pdcch_cfg_nxt
#define LDTC1_PDCCH_DET_NUM(n) (((n)&0x7) << 0)
#define LDTC1_SRS_ACT (1 << 3)
#define LDTC1_ANTSEL_EN (1 << 4)
#define LDTC1_CSI_SEL (1 << 5)
#define LDTC1_PUS_ENH (1 << 6)
#define LDTC1_DCILEN_SEL (1 << 7)
#define LDTC1_DCILEN_COMM0(n) (((n)&0x3f) << 8)
#define LDTC1_DCILEN_COMM1(n) (((n)&0x3f) << 14)
#define LDTC1_DCILEN_UE0(n) (((n)&0x3f) << 20)
#define LDTC1_DCILEN_UE1(n) (((n)&0x3f) << 26)

// pdsch0_cfg_nxt
#define LDTC1_TBSIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU(n) (((n)&0x3) << 14)
#define LDTC1_PDSCH0_CFG_NXT_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_PDSCH0_CFG_NXT_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// pdsch1_cfg_nxt
#define LDTC1_TBSIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_PDSCH1_CFG_NXT_RV_SEL(n) (((n)&0x3) << 14)
#define LDTC1_PDSCH1_CFG_NXT_RA_TYPE (1 << 16)

// pdsch2_cfg_nxt
#define LDTC1_TBSIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_PDSCH2_CFG_NXT_RV_SEL(n) (((n)&0x3) << 14)
#define LDTC1_PDSCH2_CFG_NXT_RA_TYPE (1 << 16)

// frame_ccnt_nxt
#define LDTC1_SF_CNT(n) (((n)&0xf) << 0)
#define LDTC1_RF_CNT(n) (((n)&0x3ff) << 4)
#define LDTC1_SSFN_CNT(n) (((n)&0xffff) << 16)

// frame_dcnt_nxt
#define LDTC1_SF_CNT(n) (((n)&0xf) << 0)
#define LDTC1_RF_CNT(n) (((n)&0x3ff) << 4)
#define LDTC1_SSFN_CNT(n) (((n)&0xffff) << 16)

// ldtc1_cserv_nxt
#define LDTC1_SI_RNTI_EN (1 << 0)
#define LDTC1_P_RNTI_EN (1 << 1)
#define LDTC1_RA_RNTI_EN (1 << 2)
#define LDTC1_C_RNTI_EN (1 << 3)
#define LDTC1_SPS_RNTI_EN (1 << 4)
#define LDTC1_T_RNTI_EN (1 << 5)
#define LDTC1_TPCS_RNTI_EN (1 << 6)
#define LDTC1_TPCC_RNTI_EN (1 << 7)
#define LDTC1_LDTC1_CSERV_NXT_G_RNTI_EN (1 << 8)
#define LDTC1_LDTC1_CSERV_NXT_SC_RNTI_EN (1 << 9)
#define LDTC1_SC_N_RNTI_EN (1 << 10)

// ldtc1_dserv_nxt
#define LDTC1_SI_RNTI_EN (1 << 0)
#define LDTC1_P_RNTI_EN (1 << 1)
#define LDTC1_RA_RNTI_EN (1 << 2)
#define LDTC1_C_RNTI_EN (1 << 3)
#define LDTC1_SPS_RNTI_EN (1 << 4)
#define LDTC1_T_RNTI_EN (1 << 5)
#define LDTC1_LDTC1_DSERV_NXT_G_RNTI_EN (1 << 6)
#define LDTC1_LDTC1_DSERV_NXT_SC_RNTI_EN (1 << 7)

// ldtc1_cctrl_nxt
#define LDTC1_PBCH_EN (1 << 0)
#define LDTC1_PDCCH_EN (1 << 1)
#define LDTC1_HI_EN (1 << 2)
#define LDTC1_PMI_EN (1 << 3)
#define LDTC1_SINR_EN (1 << 4)
#define LDTC1_PBCH_FIRST (1 << 5)
#define LDTC1_CQFQT_PPSEL(n) (((n)&0x3) << 6)
#define LDTC1_MBMS_SF (1 << 8)
#define LDTC1_INT_B_EN (1 << 9)
#define LDTC1_INT_C_EN (1 << 10)
#define LDTC1_INT_M_EN (1 << 11)
#define LDTC1_INT_S_EN (1 << 12)
#define LDTC1_DMA_M_EN (1 << 13)
#define LDTC1_DMA_S_EN (1 << 14)

// ldtc1_dctrl_nxt
#define LDTC1_PDSCH_EN (1 << 0)
#define LDTC1_PDS_FIRST (1 << 1)
#define LDTC1_SI_FIRST (1 << 2)
#define LDTC1_SIHQBUF_SEL (1 << 3)
#define LDTC1_CSIRS_EN (1 << 4)
#define LDTC1_DQFQT_PPSEL(n) (((n)&0x3) << 5)
#define LDTC1_INT_D_EN (1 << 7)
#define LDTC1_DMA_D_EN (1 << 8)

// ldtc1_cstart
#define LDTC1_LDTC_CSTART (1 << 0)

// ldtc1_dstart
#define LDTC1_LDTC_DSTART (1 << 0)

// ctrl_flag
#define LDTC1_INT_BFLAG (1 << 0)
#define LDTC1_INT_CFLAG (1 << 1)
#define LDTC1_INT_MFLAG (1 << 2)
#define LDTC1_INT_SFLAG (1 << 3)
#define LDTC1_MIB_VALID(n) (((n)&0xf) << 4)
#define LDTC1_DCI_VALID(n) (((n)&0xff) << 8)

// data_flag
#define LDTC1_INT_DFLAG (1 << 0)
#define LDTC1_PDSCH_CRC_FLAG (1 << 1)
#define LDTC1_PDSCH_ZERO_FLAG (1 << 2)
#define LDTC1_SI_CRC_FLAG (1 << 3)
#define LDTC1_SI_ZERO_FLAG (1 << 4)
#define LDTC1_PAGING_CRC_FLAG (1 << 5)
#define LDTC1_PAGING_ZERO_FLAG (1 << 6)

// buf_flag
#define LDTC1_FFTBUF_IND (1 << 0)
#define LDTC1_DSCHOUT_IND (1 << 1)
#define LDTC1_CFH_IND (1 << 2)
#define LDTC1_DFH_IND (1 << 3)

// alg_comm_para
#define LDTC1_UE_BUND (1 << 0)
#define LDTC1_CRS_FH_LEN (1 << 1)
#define LDTC1_CRS_G_LEN (1 << 2)
#define LDTC1_CTCG_SEL (1 << 3)
#define LDTC1_SUBBW_SEL (1 << 4)
#define LDTC1_SDGN_SEL (1 << 5)
#define LDTC1_HQBIT_SEL (1 << 6)
#define LDTC1_CC_IR (1 << 7)
#define LDTC1_G_SCALE(n) (((n)&0x7) << 8)
#define LDTC1_PDC_TH(n) (((n)&0x3f) << 11)

// che_fh_para
#define LDTC1_FH16_BITSEL(n) (((n)&0xf) << 0)
#define LDTC1_FH10_BITSEL(n) (((n)&0x7) << 4)
#define LDTC1_FH10_BITSEL_TYPE (1 << 7)

// che_th_para
#define LDTC1_TH16_BITSEL(n) (((n)&0xf) << 0)

// rbbm_pds03_nxt
#define LDTC1_RBBM_NXT_03(n) (((n)&0xf) << 0)

// rbbm_pds13_nxt
#define LDTC1_RBBM_NXT_13(n) (((n)&0xf) << 0)

// rbbm_si03_nxt
#define LDTC1_RBBM_NXT_03(n) (((n)&0xf) << 0)

// rbbm_si13_nxt
#define LDTC1_RBBM_NXT_13(n) (((n)&0xf) << 0)

// rbbm_pag03_nxt
#define LDTC1_RBBM_NXT_03(n) (((n)&0xf) << 0)

// rbbm_pag13_nxt
#define LDTC1_RBBM_NXT_13(n) (((n)&0xf) << 0)

// pmi_pds0_nxt
#define LDTC1_PMI_1(n) (((n)&0xf) << 0)
#define LDTC1_PMI_2(n) (((n)&0xf) << 4)
#define LDTC1_PMI_3(n) (((n)&0xf) << 8)
#define LDTC1_PMI_4(n) (((n)&0xf) << 12)
#define LDTC1_PMI_5(n) (((n)&0xf) << 16)
#define LDTC1_PMI_6(n) (((n)&0xf) << 20)
#define LDTC1_PMI_7(n) (((n)&0xf) << 24)
#define LDTC1_PMI_8(n) (((n)&0xf) << 28)

// pmi_pds1_nxt
#define LDTC1_PMI_9(n) (((n)&0xf) << 0)
#define LDTC1_PMI_10(n) (((n)&0xf) << 4)
#define LDTC1_PMI_11(n) (((n)&0xf) << 8)
#define LDTC1_PMI_12(n) (((n)&0xf) << 12)
#define LDTC1_PMI_13(n) (((n)&0xf) << 16)
#define LDTC1_PMI_14(n) (((n)&0xf) << 20)
#define LDTC1_PMI_15(n) (((n)&0xf) << 24)
#define LDTC1_PMI_16(n) (((n)&0xf) << 28)

// pmi_pds2_nxt
#define LDTC1_PMI_17(n) (((n)&0xf) << 0)
#define LDTC1_PMI_18(n) (((n)&0xf) << 4)
#define LDTC1_PMI_19(n) (((n)&0xf) << 8)
#define LDTC1_PMI_20(n) (((n)&0xf) << 12)
#define LDTC1_PMI_21(n) (((n)&0xf) << 16)
#define LDTC1_PMI_22(n) (((n)&0xf) << 20)
#define LDTC1_PMI_23(n) (((n)&0xf) << 24)
#define LDTC1_PMI_24(n) (((n)&0xf) << 28)

// pmi_pds3_nxt
#define LDTC1_PMI_25(n) (((n)&0xf) << 0)

// spwr_wb_agc
#define LDTC1_SPWR_WB_AGC(n) (((n)&0x3ff) << 0)

// npwr_wb_agc
#define LDTC1_NPWR_WB_AGC(n) (((n)&0x3ff) << 0)

// sd_scaling_factor0
#define LDTC1_PBCH_SCALE0(n) (((n)&0x1ff) << 0)
#define LDTC1_PBCH_SCALE1(n) (((n)&0x1ff) << 9)
#define LDTC1_PBCH_SCALE_SEL (1 << 18)
#define LDTC1_PDCCH_SCALE_SEL (1 << 19)

// sd_scaling_factor1
#define LDTC1_PDSCH_SCALE0(n) (((n)&0xfff) << 0)
#define LDTC1_PDSCH_SCALE_SEL (1 << 12)

// sd_scaling_factor2
#define LDTC1_PDSCH_SCALE1(n) (((n)&0xfff) << 0)
#define LDTC1_PDSCH_SCALE2(n) (((n)&0xfff) << 12)

// sd_scaling_factor3
#define LDTC1_PDSCH_SCALE3(n) (((n)&0xfff) << 0)
#define LDTC1_PDSCH_SCALE4(n) (((n)&0xfff) << 12)

// sd_data_factor0
#define LDTC1_UCR_DATA_FACTOR(n) (((n)&0xffff) << 0)
#define LDTC1_CR_DATA_FACTOR(n) (((n)&0xffff) << 16)

// sd_data_factor1
#define LDTC1_UCR_DATA_FACTOR(n) (((n)&0xffff) << 0)
#define LDTC1_CR_DATA_FACTOR(n) (((n)&0xffff) << 16)

// sd_data_factor2
#define LDTC1_UCR_DATA_FACTOR(n) (((n)&0xffff) << 0)
#define LDTC1_CR_DATA_FACTOR(n) (((n)&0xffff) << 16)

// cnoise_agc_nxt
#define LDTC1_NOISE_AGC(n) (((n)&0x3ff) << 0)

// cnoise_th
#define LDTC1_NOISE_TH(n) (((n)&0xffff) << 0)

// dnoise_agc_nxt
#define LDTC1_NOISE_AGC(n) (((n)&0x3ff) << 0)

// dnoise_th
#define LDTC1_NOISE_TH1(n) (((n)&0xffff) << 0)
#define LDTC1_NOISE_TH2(n) (((n)&0xffff) << 16)

// sd_scaling_bcout0
#define LDTC1_BSCALE_OUT0(n) (((n)&0x3) << 0)
#define LDTC1_BSCALE_OUT1(n) (((n)&0x3) << 2)
#define LDTC1_BSCALE_OUT2(n) (((n)&0x3) << 4)
#define LDTC1_BSCALE_OUT3(n) (((n)&0x3) << 6)
#define LDTC1_CSCALE_OUT(n) (((n)&0xf) << 8)

// sd_scaling_dout0
#define LDTC1_DSCALE_OUT0(n) (((n)&0x7) << 0)
#define LDTC1_DSCALE_OUT1(n) (((n)&0x7) << 3)
#define LDTC1_DSCALE_OUT2(n) (((n)&0x7) << 6)
#define LDTC1_DSCALE_OUT3(n) (((n)&0x7) << 9)
#define LDTC1_DSCALE_OUT4(n) (((n)&0x7) << 12)
#define LDTC1_DSCALE_OUT5(n) (((n)&0x7) << 15)
#define LDTC1_DSCALE_OUT6(n) (((n)&0x7) << 18)
#define LDTC1_DSCALE_OUT7(n) (((n)&0x7) << 21)

// sd_scaling_dout1
#define LDTC1_DSCALE_OUT8(n) (((n)&0x7) << 0)
#define LDTC1_DSCALE_OUT9(n) (((n)&0x7) << 3)
#define LDTC1_DSCALE_OUT10(n) (((n)&0x7) << 6)
#define LDTC1_DSCALE_OUT11(n) (((n)&0x7) << 9)
#define LDTC1_DSCALE_OUT12(n) (((n)&0x7) << 12)
#define LDTC1_DSCALE_OUT13(n) (((n)&0x7) << 15)
#define LDTC1_DSCALE_OUT14(n) (((n)&0x7) << 18)
#define LDTC1_DSCALE_OUT15(n) (((n)&0x7) << 21)

// sd_scaling_dout2
#define LDTC1_DSCALE_OUT16(n) (((n)&0x7) << 0)
#define LDTC1_DSCALE_OUT17(n) (((n)&0x7) << 3)
#define LDTC1_DSCALE_OUT18(n) (((n)&0x7) << 6)
#define LDTC1_DSCALE_OUT19(n) (((n)&0x7) << 9)
#define LDTC1_DSCALE_OUT20(n) (((n)&0x7) << 12)
#define LDTC1_DSCALE_OUT21(n) (((n)&0x7) << 15)
#define LDTC1_DSCALE_OUT22(n) (((n)&0x7) << 18)
#define LDTC1_DSCALE_OUT23(n) (((n)&0x7) << 21)

// sd_scaling_dout3
#define LDTC1_DSCALE_OUT24(n) (((n)&0x7) << 0)
#define LDTC1_DSCALE_OUT25(n) (((n)&0x7) << 3)
#define LDTC1_DSCALE_OUT26(n) (((n)&0x7) << 6)
#define LDTC1_DSCALE_OUT27(n) (((n)&0x7) << 9)
#define LDTC1_DSCALE_OUT28(n) (((n)&0x7) << 12)
#define LDTC1_DSCALE_OUT29(n) (((n)&0x7) << 15)
#define LDTC1_DSCALE_OUT30(n) (((n)&0x7) << 18)
#define LDTC1_DSCALE_OUT31(n) (((n)&0x7) << 21)

// sd_scaling_dout4
#define LDTC1_DSCALE_OUT32(n) (((n)&0x7) << 0)
#define LDTC1_DSCALE_OUT33(n) (((n)&0x7) << 3)
#define LDTC1_DSCALE_OUT34(n) (((n)&0x7) << 6)

// hq_hb_sta
#define LDTC1_HB0_STA (1 << 0)
#define LDTC1_HB1_STA (1 << 1)
#define LDTC1_HB2_STA (1 << 2)
#define LDTC1_HB3_STA (1 << 3)
#define LDTC1_HB4_STA (1 << 4)
#define LDTC1_HB5_STA (1 << 5)
#define LDTC1_HB6_STA (1 << 6)
#define LDTC1_HB7_STA (1 << 7)
#define LDTC1_HB8_STA (1 << 8)
#define LDTC1_HB9_STA (1 << 9)
#define LDTC1_HB10_STA (1 << 10)
#define LDTC1_HB11_STA (1 << 11)
#define LDTC1_HB12_STA (1 << 12)
#define LDTC1_HB13_STA (1 << 13)
#define LDTC1_HB14_STA (1 << 14)
#define LDTC1_HB15_STA (1 << 15)

// hq_hb_proc0
#define LDTC1_HB0_PROC(n) (((n)&0xf) << 0)
#define LDTC1_HB1_PROC(n) (((n)&0xf) << 4)
#define LDTC1_HB2_PROC(n) (((n)&0xf) << 8)
#define LDTC1_HB3_PROC(n) (((n)&0xf) << 12)
#define LDTC1_HB4_PROC(n) (((n)&0xf) << 16)
#define LDTC1_HB5_PROC(n) (((n)&0xf) << 20)
#define LDTC1_HB6_PROC(n) (((n)&0xf) << 24)
#define LDTC1_HB7_PROC(n) (((n)&0xf) << 28)

// hq_hb_proc1
#define LDTC1_HB8_PROC(n) (((n)&0xf) << 0)
#define LDTC1_HB9_PROC(n) (((n)&0xf) << 4)
#define LDTC1_HB10_PROC(n) (((n)&0xf) << 8)
#define LDTC1_HB11_PROC(n) (((n)&0xf) << 12)
#define LDTC1_HB12_PROC(n) (((n)&0xf) << 16)
#define LDTC1_HB13_PROC(n) (((n)&0xf) << 20)
#define LDTC1_HB14_PROC(n) (((n)&0xf) << 24)
#define LDTC1_HB15_PROC(n) (((n)&0xf) << 28)

// turbo_para
#define LDTC1_ITER_NUM_MAX(n) (((n)&0xf) << 0)
#define LDTC1_SHIFT_ITERNUM1(n) (((n)&0xf) << 4)
#define LDTC1_SHIFT_ITERNUM2(n) (((n)&0xf) << 8)
#define LDTC1_SHIFT_EN0 (1 << 12)
#define LDTC1_SHIFT_EN1 (1 << 13)
#define LDTC1_SHIFT_EN2 (1 << 14)
#define LDTC1_NORM_EN0 (1 << 15)
#define LDTC1_NORM_EN1 (1 << 16)
#define LDTC1_NORM_EN2 (1 << 17)

// turbo_iter
#define LDTC1_REAL_ITER0(n) (((n)&0xf) << 0)
#define LDTC1_REAL_ITER1(n) (((n)&0xf) << 4)
#define LDTC1_REAL_ITER2(n) (((n)&0xf) << 8)
#define LDTC1_REAL_ITER3(n) (((n)&0xf) << 12)

// vit_par
#define LDTC1_VIT_ITNUM(n) (((n)&0x3) << 0)
#define LDTC1_INTV_EN (1 << 2)
#define LDTC1_DMAV_EN (1 << 3)
#define LDTC1_CRC_TYPE (1 << 4)
#define LDTC1_MASK_EN (1 << 5)

// vit_faconf
#define LDTC1_FA_TH(n) (((n)&0xff) << 0)
#define LDTC1_FA_EN (1 << 8)
#define LDTC1_CRC_MASK(n) (((n)&0xffff) << 16)

// vit_len
#define LDTC1_VIT_LEN(n) (((n)&0x3ff) << 0)

// vit_start
#define LDTC1_VIT_START (1 << 0)

// vit_flag
#define LDTC1_INT_VFLAG (1 << 0)
#define LDTC1_VIT_CRC_FLAG (1 << 1)
#define LDTC1_PDSCH_ZERO_FLAG (1 << 2)

// vit_faout
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// cfi_out
#define LDTC1_CFI_OUT(n) (((n)&0x7) << 0)

// hi_out
#define LDTC1_HI0_OUT (1 << 0)
#define LDTC1_HI1_OUT (1 << 1)

// pds_rep_num
#define LDTC1_PDS0_REP_NUM(n) (((n)&0x3) << 0)
#define LDTC1_PDS1_REP_NUM(n) (((n)&0x3) << 2)
#define LDTC1_PDS2_REP_NUM(n) (((n)&0x3) << 4)
#define LDTC1_PDS3_REP_NUM(n) (((n)&0x3) << 6)
#define LDTC1_PDS4_REP_NUM(n) (((n)&0x3) << 8)
#define LDTC1_PDS5_REP_NUM(n) (((n)&0x3) << 10)
#define LDTC1_PDS6_REP_NUM(n) (((n)&0x3) << 12)
#define LDTC1_PDS7_REP_NUM(n) (((n)&0x3) << 14)
#define LDTC1_PDS8_REP_NUM(n) (((n)&0x3) << 16)
#define LDTC1_PDS9_REP_NUM(n) (((n)&0x3) << 18)
#define LDTC1_PDS10_REP_NUM(n) (((n)&0x3) << 20)
#define LDTC1_PDS11_REP_NUM(n) (((n)&0x3) << 22)
#define LDTC1_PDS12_REP_NUM(n) (((n)&0x3) << 24)
#define LDTC1_PDS13_REP_NUM(n) (((n)&0x3) << 26)
#define LDTC1_PDS14_REP_NUM(n) (((n)&0x3) << 28)
#define LDTC1_PDS15_REP_NUM(n) (((n)&0x3) << 30)

// si_rep_num
#define LDTC1_SI0_REP_NUM(n) (((n)&0x3) << 0)
#define LDTC1_SI1_REP_NUM(n) (((n)&0x3) << 2)

// pbch_rep_num
#define LDTC1_PBCH_REP_NUM(n) (((n)&0x3) << 0)

// rtctrl_cfg
#define LDTC1_RTCTRL_CFG(n) (((n)&0x3ffff) << 0)

// cabis_enbl_nxt
#define LDTC1_CABIS_SDBEN (1 << 0)
#define LDTC1_CABIS_SDCEN (1 << 1)
#define LDTC1_CABIS_SDDEN (1 << 2)
#define LDTC1_CABIS_EN (1 << 3)
#define LDTC1_CABIS_SEL (1 << 4)
#define LDTC1_CMC_EN (1 << 5)
#define LDTC1_CABIS_ENBL_NXT_ABIS_PORTSEL0(n) (((n)&0x3) << 6)
#define LDTC1_CABIS_ENBL_NXT_ABIS_PORTSEL1(n) (((n)&0x3) << 8)
#define LDTC1_CABIS_ENBL_NXT_ABIS_PORTSEL2(n) (((n)&0x3) << 10)

// cabis_cfg_nxt
#define LDTC1_CABIS_CELLID_NEXT1(n) (((n)&0x1ff) << 0)
#define LDTC1_CABIS_CELLID_NEXT2(n) (((n)&0x1ff) << 9)
#define LDTC1_CABIS_NRB_NEXT1(n) (((n)&0x7) << 18)
#define LDTC1_CABIS_NRB_NEXT2(n) (((n)&0x7) << 21)
#define LDTC1_CABIS_TXNUM_NEXT1(n) (((n)&0x3) << 24)
#define LDTC1_CABIS_TXNUM_NEXT2(n) (((n)&0x3) << 26)
#define LDTC1_CABIS_NUM(n) (((n)&0x3) << 28)

// cabis_dly1_nxt
#define LDTC1_CABIS_DLY_NEXT1(n) (((n)&0x7ffff) << 0)

// cabis_dly2_nxt
#define LDTC1_CABIS_DLY_NEXT2(n) (((n)&0x7ffff) << 0)

// cabis_shft_nxt
#define LDTC1_CABIS_SHFT_NEXT1(n) (((n)&0xf) << 0)
#define LDTC1_CABIS_SHFT_NEXT2(n) (((n)&0xf) << 4)
#define LDTC1_CABIS_SHFT_NEXT3(n) (((n)&0xf) << 8)

// dabis_enbl_nxt
#define LDTC1_DABIS_SDBEN (1 << 0)
#define LDTC1_DABIS_SDCEN (1 << 1)
#define LDTC1_DABIS_SDDEN (1 << 2)
#define LDTC1_DABIS_EN (1 << 3)
#define LDTC1_DABIS_SEL (1 << 4)
#define LDTC1_DABIS_ENBL_NXT_ABIS_PORTSEL0(n) (((n)&0x3) << 5)
#define LDTC1_DABIS_ENBL_NXT_ABIS_PORTSEL1(n) (((n)&0x3) << 7)
#define LDTC1_DABIS_ENBL_NXT_ABIS_PORTSEL2(n) (((n)&0x3) << 9)

// dabis_cfg_nxt
#define LDTC1_DABIS_CELLID_NEXT1(n) (((n)&0x1ff) << 0)
#define LDTC1_DABIS_CELLID_NEXT2(n) (((n)&0x1ff) << 9)
#define LDTC1_DABIS_NRB_NEXT1(n) (((n)&0x7) << 18)
#define LDTC1_DABIS_NRB_NEXT2(n) (((n)&0x7) << 21)
#define LDTC1_DABIS_TXNUM_NEXT1(n) (((n)&0x3) << 24)
#define LDTC1_DABIS_TXNUM_NEXT2(n) (((n)&0x3) << 26)
#define LDTC1_DABIS_NUM(n) (((n)&0x3) << 28)

// dabis_dly1_nxt
#define LDTC1_DABIS_DLY_NEXT1(n) (((n)&0x7ffff) << 0)

// dabis_dly2_nxt
#define LDTC1_DABIS_DLY_NEXT2(n) (((n)&0x7ffff) << 0)

// dabis_shft_nxt
#define LDTC1_DABIS_SHFT_NEXT1(n) (((n)&0xf) << 0)
#define LDTC1_DABIS_SHFT_NEXT2(n) (((n)&0xf) << 4)
#define LDTC1_DABIS_SHFT_NEXT3(n) (((n)&0xf) << 8)

// reis_conf
#define LDTC1_REIS_NUM(n) (((n)&0xf) << 0)
#define LDTC1_REIS_EN (1 << 4)

// reis_pos0
#define LDTC1_REIS_RE0(n) (((n)&0x7ff) << 0)
#define LDTC1_REIS_SHIFT0(n) (((n)&0xf) << 12)
#define LDTC1_REIS_RE1(n) (((n)&0x7ff) << 16)
#define LDTC1_REIS_SHIFT1(n) (((n)&0xf) << 28)

// reis_pos1
#define LDTC1_REIS_RE2(n) (((n)&0x7ff) << 0)
#define LDTC1_REIS_SHIFT2(n) (((n)&0xf) << 12)
#define LDTC1_REIS_RE3(n) (((n)&0x7ff) << 16)
#define LDTC1_REIS_SHIFT3(n) (((n)&0xf) << 28)

// reis_pos2
#define LDTC1_REIS_RE4(n) (((n)&0x7ff) << 0)
#define LDTC1_REIS_SHIFT4(n) (((n)&0xf) << 12)
#define LDTC1_REIS_RE5(n) (((n)&0x7ff) << 16)
#define LDTC1_REIS_SHIFT5(n) (((n)&0xf) << 28)

// reis_pos3
#define LDTC1_REIS_RE6(n) (((n)&0x7ff) << 0)
#define LDTC1_REIS_SHIFT6(n) (((n)&0xf) << 12)
#define LDTC1_REIS_RE7(n) (((n)&0x7ff) << 16)
#define LDTC1_REIS_SHIFT7(n) (((n)&0xf) << 28)

// rbis_par
#define LDTC1_RBIS_FACTOR(n) (((n)&0xffff) << 0)
#define LDTC1_RBIS_DIPOS(n) (((n)&0x7f) << 16)
#define LDTC1_RBIS_NUM(n) (((n)&0x7) << 23)
#define LDTC1_RBIS_POSEN (1 << 26)
#define LDTC1_RBIS_SDBEN (1 << 27)
#define LDTC1_RBIS_SDCEN (1 << 28)
#define LDTC1_RBIS_SDDEN (1 << 29)
#define LDTC1_RBIS_EN (1 << 30)
#define LDTC1_RBIS_PORTSEL (1 << 31)

// rbis_posout0
#define LDTC1_RBIS_POSOUT0(n) (((n)&0x7f) << 0)
#define LDTC1_RBIS_POSOUT1(n) (((n)&0x7f) << 7)
#define LDTC1_RBIS_POSOUT2(n) (((n)&0x7f) << 14)
#define LDTC1_RBIS_POSOUT3(n) (((n)&0x7f) << 21)

// rbis_posout1
#define LDTC1_RBIS_POSOUT4(n) (((n)&0x7f) << 0)

// rbis_max
#define LDTC1_RBIS_MAX(n) (((n)&0x1ffffff) << 0)

// pbml_cfg_nxt
#define LDTC1_LLR_ALPHA(n) (((n)&0xff) << 0)
#define LDTC1_LLR_POS_STA(n) (((n)&0x3f) << 8)
#define LDTC1_LLR_CAL_LEN(n) (((n)&0x3f) << 14)
#define LDTC1_PBML_EN (1 << 20)

// ctrl_state
#define LDTC1_CTRL_STATE(n) (((n)&0x3ffffff) << 0)

// data_state
#define LDTC1_DATA_STATE(n) (((n)&0x3ffffff) << 0)

// frame_ccnt_out
#define LDTC1_SF_CNT(n) (((n)&0xf) << 0)
#define LDTC1_RF_CNT(n) (((n)&0x3ff) << 4)
#define LDTC1_SSFN_CNT(n) (((n)&0xffff) << 16)

// frame_dcnt_out
#define LDTC1_SF_CNT(n) (((n)&0xf) << 0)
#define LDTC1_RF_CNT(n) (((n)&0x3ff) << 4)
#define LDTC1_SSFN_CNT(n) (((n)&0xffff) << 16)

// pds0_harqin0_info
#define LDTC1_PDS_INI0(n) (((n)&0x3ff) << 0)
#define LDTC1_PDS_LEN0(n) (((n)&0x3ff) << 16)

// pds0_harqin1_info
#define LDTC1_PDS_INI1(n) (((n)&0x1fff) << 0)
#define LDTC1_PDS_E0(n) (((n)&0xffff) << 16)

// pds1_harqin0_info
#define LDTC1_PDS_INI0(n) (((n)&0x3ff) << 0)
#define LDTC1_PDS_LEN0(n) (((n)&0x3ff) << 16)

// pds1_harqin1_info
#define LDTC1_PDS_INI1(n) (((n)&0x1fff) << 0)
#define LDTC1_PDS_E0(n) (((n)&0xffff) << 16)

// si_harqin0_info
#define LDTC1_SI_INI0(n) (((n)&0x3ff) << 0)
#define LDTC1_SI_LEN0(n) (((n)&0x3ff) << 16)

// si_harqin1_info
#define LDTC1_SI_INI1(n) (((n)&0x1fff) << 0)
#define LDTC1_SI_E0(n) (((n)&0xffff) << 16)

// pag_harqin0_info
#define LDTC1_PAG_INI0(n) (((n)&0x3ff) << 0)
#define LDTC1_PAG_LEN0(n) (((n)&0x3ff) << 16)

// pag_harqin1_info
#define LDTC1_PAG_INI1(n) (((n)&0x1fff) << 0)
#define LDTC1_PAG_E0(n) (((n)&0xffff) << 16)

// cabis_shft_out
#define LDTC1_CABIS_SHFT1(n) (((n)&0xf) << 0)
#define LDTC1_CABIS_SHFT2(n) (((n)&0xf) << 4)
#define LDTC1_CABIS_SHFT3(n) (((n)&0xf) << 8)

// dabis_shft_out
#define LDTC1_DABIS_SHFT1(n) (((n)&0xf) << 0)
#define LDTC1_DABIS_SHFT2(n) (((n)&0xf) << 4)
#define LDTC1_DABIS_SHFT3(n) (((n)&0xf) << 8)

// mc_dly1_nxt
#define LDTC1_MC_DLY1(n) (((n)&0x7ffff) << 0)

// mc_dly2_nxt
#define LDTC1_MC_DLY2(n) (((n)&0x7ffff) << 0)

// mc_dlyth_nxt
#define LDTC1_MC_DLYTH(n) (((n)&0x3ff) << 0)

// cfhmem1
#define LDTC1_CFHMEM1(n) (((n)&0x3fffffff) << 0)

// cfhmem2
#define LDTC1_CFHMEM2(n) (((n)&0x3fffffff) << 0)

// crsmem1
#define LDTC1_CRSMEM1_IM(n) (((n)&0xfff) << 4)
#define LDTC1_CRSMEM1_RE(n) (((n)&0xfff) << 20)

// crsmem2
#define LDTC1_CRSMEM2_IM(n) (((n)&0xfff) << 4)
#define LDTC1_CRSMEM2_RE(n) (((n)&0xfff) << 20)

// clsmem
#define LDTC1_CLSMEM_IM(n) (((n)&0xfff) << 4)
#define LDTC1_CLSMEM_RE(n) (((n)&0xfff) << 20)

// ursmem
#define LDTC1_URSMEM_IM(n) (((n)&0xfff) << 4)
#define LDTC1_URSMEM_RE(n) (((n)&0xfff) << 20)

// ulsmem
#define LDTC1_ULSMEM_IM(n) (((n)&0xfff) << 4)
#define LDTC1_ULSMEM_RE(n) (((n)&0xfff) << 20)

// cell_qfmem1
#define LDTC1_CELL_QFMEM1_IM(n) (((n)&0x1fff) << 3)
#define LDTC1_CELL_QFMEM1_RE(n) (((n)&0x1fff) << 19)

// cell_qfmem2
#define LDTC1_CELL_QFMEM2_IM(n) (((n)&0x1fff) << 3)
#define LDTC1_CELL_QFMEM2_RE(n) (((n)&0x1fff) << 19)

// ct_qtmem1
#define LDTC1_CT_QTMEM1_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM1_2(n) (((n)&0x1fff) << 19)

// ct_qtmem1_p01_tap2
#define LDTC1_CT_QTMEM1_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM1_2(n) (((n)&0x1fff) << 19)

// ct_qtmem1_p01_tap3
#define LDTC1_CT_QTMEM1_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM1_2(n) (((n)&0x1fff) << 19)

// ct_qtmem1_p23_tap2
#define LDTC1_CT_QTMEM1_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM1_2(n) (((n)&0x1fff) << 19)

// ct_qtmem2
#define LDTC1_CT_QTMEM2_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM2_2(n) (((n)&0x1fff) << 19)

// ct_qtmem2_p01_tap2
#define LDTC1_CT_QTMEM2_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM2_2(n) (((n)&0x1fff) << 19)

// ct_qtmem2_p01_tap3
#define LDTC1_CT_QTMEM2_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM2_2(n) (((n)&0x1fff) << 19)

// ct_qtmem2_p23_tap2
#define LDTC1_CT_QTMEM2_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM2_2(n) (((n)&0x1fff) << 19)

// dt_qtmem1
#define LDTC1_DT_QTMEM1_1(n) (((n)&0x1fff) << 3)
#define LDTC1_DT_QTMEM1_2(n) (((n)&0x1fff) << 19)

// dt_qtmem2
#define LDTC1_DT_QTMEM2_1(n) (((n)&0x1fff) << 3)
#define LDTC1_DT_QTMEM2_2(n) (((n)&0x1fff) << 19)

// agc_cls_mem
#define LDTC1_AGC_CLS_MEM_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_CLS_MEM_2(n) (((n)&0x3ff) << 22)

// agc_uls_mem
#define LDTC1_AGC_ULS_MEM_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_ULS_MEM_2(n) (((n)&0x3ff) << 22)

// agc_cfh_mem1
#define LDTC1_AGC_CFH_MEM1_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_CFH_MEM1_2(n) (((n)&0x3ff) << 22)

// agc_cfh_mem2
#define LDTC1_AGC_CFH_MEM2_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_CFH_MEM2_2(n) (((n)&0x3ff) << 22)

// agc_ufh_mem1
#define LDTC1_AGC_UFH_MEM1_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_UFH_MEM1_2(n) (((n)&0x3ff) << 22)

// agc_ufh_mem2
#define LDTC1_AGC_UFH_MEM2_1(n) (((n)&0x3ff) << 6)
#define LDTC1_AGC_UFH_MEM2_2(n) (((n)&0x3ff) << 22)

// ufhmem
#define LDTC1_UFHMEM(n) (((n)&0x3fffffff) << 0)

// csi_in_mem
#define LDTC1_CSIMEM_IM(n) (((n)&0xfff) << 4)
#define LDTC1_CSIMEM_RE(n) (((n)&0xfff) << 20)

// pmi_mem_sb
#define LDTC1_PMI_PRB96(n) (((n)&0xf) << 0)
#define LDTC1_PMI_PRB97(n) (((n)&0xf) << 4)
#define LDTC1_PMI_PRB98(n) (((n)&0xf) << 8)
#define LDTC1_PMI_PRB99(n) (((n)&0xf) << 12)
#define LDTC1_PMI_SB1(n) (((n)&0xf) << 16)
#define LDTC1_PMI_SB2(n) (((n)&0xf) << 20)
#define LDTC1_PMI_SB3(n) (((n)&0xf) << 24)
#define LDTC1_PMI_SB4(n) (((n)&0xf) << 28)

// cell_qfmem3
#define LDTC1_CELL_QFMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CELL_QFMEM3_2(n) (((n)&0x1fff) << 19)

// ct_qtmem3
#define LDTC1_CT_QTMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM3_2(n) (((n)&0x1fff) << 19)

// ct_qtmem3_p01_tap2
#define LDTC1_CT_QTMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM3_2(n) (((n)&0x1fff) << 19)

// ct_qtmem3_p01_tap3
#define LDTC1_CT_QTMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM3_2(n) (((n)&0x1fff) << 19)

// ct_qtmem3_p23_tap2
#define LDTC1_CT_QTMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_CT_QTMEM3_2(n) (((n)&0x1fff) << 19)

// dt_qtmem3
#define LDTC1_DT_QTMEM3_1(n) (((n)&0x1fff) << 3)
#define LDTC1_DT_QTMEM3_2(n) (((n)&0x1fff) << 19)

// sdmemcg0
#define LDTC1_SDMEMCG0(n) (((n)&0x1fffff) << 11)

// sdmemcg1
#define LDTC1_SDMEMCG1(n) (((n)&0x1fffff) << 11)

// sdmemdg0
#define LDTC1_SDMEMDG0(n) (((n)&0x1fffff) << 11)

// sdmemdg1
#define LDTC1_SDMEMDG1(n) (((n)&0x1fffff) << 11)

// sdmemdg2
#define LDTC1_SDMEMDG2(n) (((n)&0x1fffff) << 11)

// sdmemdg3
#define LDTC1_SDMEMDG3(n) (((n)&0x1fffff) << 11)

// pdcch_memin
#define LDTC1_PDCCH_MEMIN_1(n) (((n)&0x7ff) << 5)
#define LDTC1_PDCCH_MEMIN_2(n) (((n)&0x7ff) << 21)

// dci0_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci0_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci0_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci0_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI0_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI0_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci0_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci0_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI0_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci0_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci0_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci1_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci1_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci1_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci1_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI1_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI1_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci1_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci1_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI1_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci1_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci1_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci2_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci2_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci2_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci2_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI2_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI2_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci2_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci2_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI2_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci2_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci2_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci3_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci3_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci3_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci3_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI3_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI3_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci3_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci3_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI3_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci3_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci3_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci4_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci4_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci4_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci4_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI4_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI4_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci4_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci4_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI4_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci4_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci4_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci5_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci5_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci5_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci5_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI5_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI5_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci5_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci5_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI5_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci5_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci5_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci6_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci6_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci6_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci6_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI6_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI6_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci6_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci6_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI6_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci6_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci6_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// dci7_pwr
#define LDTC1_DCI_PWR(n) (((n)&0x3ffffff) << 0)

// dci7_fa
#define LDTC1_DCI_FA(n) (((n)&0xff) << 0)
#define LDTC1_DCI_FA_ZERO(n) (((n)&0xff) << 8)

// dci7_info1
#define LDTC1_DCI_LEN(n) (((n)&0x3f) << 0)
#define LDTC1_DCI_LLEVEL(n) (((n)&0x7) << 6)
#define LDTC1_DCI_STAPOS(n) (((n)&0x7f) << 9)
#define LDTC1_COMM_UE (1 << 16)
#define LDTC1_RNTI_IND(n) (((n)&0xf) << 17)
#define LDTC1_DCI_TYPE(n) (((n)&0xf) << 21)
#define LDTC1_SPS_IND(n) (((n)&0x3) << 25)
#define LDTC1_ORDER_FLAG (1 << 27)
#define LDTC1_ANT_SEL (1 << 28)

// dci7_info2
#define LDTC1_TB_SIZE(n) (((n)&0x3fff) << 0)
#define LDTC1_MODU_TYPE(n) (((n)&0x3) << 14)
#define LDTC1_DCI7_INFO2_RV_SEL(n) (((n)&0x3) << 16)
#define LDTC1_N_SCID (1 << 18)
#define LDTC1_DCI7_INFO2_RA_TYPE (1 << 19)
#define LDTC1_TRANS_SCHEME(n) (((n)&0x7) << 20)
#define LDTC1_PMI_INDX(n) (((n)&0xf) << 23)
#define LDTC1_HQ_PROC(n) (((n)&0xf) << 27)
#define LDTC1_PMI_CONFM (1 << 31)

// dci7_info3
#define LDTC1_TPC_STEP(n) (((n)&0x3) << 0)
#define LDTC1_DAI(n) (((n)&0x3) << 2)
#define LDTC1_PWR_OFST (1 << 4)
#define LDTC1_NDI_IND (1 << 5)
#define LDTC1_SRS_REQ (1 << 6)
#define LDTC1_TB_CW (1 << 7)
#define LDTC1_CQI_INDX(n) (((n)&0x3) << 8)
#define LDTC1_CS_DMRS(n) (((n)&0x7) << 10)
#define LDTC1_CW2_FLAG (1 << 13)
#define LDTC1_MCS(n) (((n)&0x1f) << 14)
#define LDTC1_REP(n) (((n)&0x7) << 19)

// dci7_info4
#define LDTC1_RBA(n) (((n)&0x1fff) << 0)
#define LDTC1_RB_HOP_FLAG (1 << 13)
#define LDTC1_DCI7_INFO4_RA_TYPE (1 << 14)
#define LDTC1_NUL_FD(n) (((n)&0x1ffff) << 15)

// dci7_info8
#define LDTC1_RB_BM_03(n) (((n)&0xf) << 0)

// dci7_info12
#define LDTC1_RB_BM_13(n) (((n)&0xf) << 0)

// pdcch_memdem
#define LDTC1_PDCCH_MEMDEM_1(n) (((n)&0x7ff) << 5)
#define LDTC1_PDCCH_MEMDEM_2(n) (((n)&0x7ff) << 21)

// pdcch_mempbchin
#define LDTC1_PBCH_MEMIN_1(n) (((n)&0x3ff) << 6)
#define LDTC1_PBCH_MEMIN_2(n) (((n)&0x3ff) << 22)

// mib0_out
#define LDTC1_MIB0_OUT(n) (((n)&0xffffff) << 0)

// mib0_info
#define LDTC1_MIB0_INFO(n) (((n)&0x3) << 0)

// mib1_out
#define LDTC1_MIB1_OUT(n) (((n)&0xffffff) << 0)

// mib1_info
#define LDTC1_MIB1_INFO(n) (((n)&0x3) << 0)

// mib2_out
#define LDTC1_MIB2_OUT(n) (((n)&0xffffff) << 0)

// mib2_info
#define LDTC1_MIB2_INFO(n) (((n)&0x3) << 0)

// mib3_out
#define LDTC1_MIB3_OUT(n) (((n)&0xffffff) << 0)

// mib3_info
#define LDTC1_MIB3_INFO(n) (((n)&0x3) << 0)

// hqmem11
#define LDTC1_HQMEM11_1(n) (((n)&0x1fff) << 3)
#define LDTC1_HQMEM11_2(n) (((n)&0x1fff) << 19)

// tbmemin0
#define LDTC1_TBMEMIN0(n) (((n)&0xffffff) << 0)

// tbmemin1
#define LDTC1_TBMEMIN1(n) (((n)&0xffffff) << 0)

#endif // _LDTC1_H_
