/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _AON_CLK_GEN_H_
#define _AON_CLK_GEN_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_AON_CLK_GEN_BASE (0x51508000)

typedef volatile struct
{
    uint32_t __0[8];                            // 0x00000000
    uint32_t soft_cnt_done0_cfg;                // 0x00000020
    uint32_t pll_wait_sel0_cfg;                 // 0x00000024
    uint32_t pll_wait_sw_ctl0_cfg;              // 0x00000028
    uint32_t div_en_sel0_cfg;                   // 0x0000002c
    uint32_t div_en_sw_ctl0_cfg;                // 0x00000030
    uint32_t gate_en_sel0_cfg;                  // 0x00000034
    uint32_t gate_en_sel1_cfg;                  // 0x00000038
    uint32_t gate_en_sw_ctl0_cfg;               // 0x0000003c
    uint32_t gate_en_sw_ctl1_cfg;               // 0x00000040
    uint32_t monitor_wait_en_status0_cfg;       // 0x00000044
    uint32_t monitor_div_auto_en_status0_cfg;   // 0x00000048
    uint32_t monitor_gate_auto_en_status00_cfg; // 0x0000004c
    uint32_t monitor_gate_auto_en_status10_cfg; // 0x00000050
} HWP_AON_CLK_GEN_T;

#define hwp_aonClkGen ((HWP_AON_CLK_GEN_T *)REG_ACCESS_ADDRESS(REG_AON_CLK_GEN_BASE))

// soft_cnt_done0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_78m_soft_cnt_done : 1;      // [0]
        uint32_t xtal_lp_26m_soft_cnt_done : 1;    // [1]
        uint32_t xtal_26m_soft_cnt_done : 1;       // [2]
        uint32_t audio_pll_122m_soft_cnt_done : 1; // [3]
        uint32_t mempll_1000m_soft_cnt_done : 1;   // [4]
        uint32_t apll_1000m_soft_cnt_done : 1;     // [5]
        uint32_t __31_6 : 26;                      // [31:6]
    } b;
} REG_AON_CLK_GEN_SOFT_CNT_DONE0_CFG_T;

// pll_wait_sel0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_78m_wait_auto_gate_sel : 1;      // [0]
        uint32_t xtal_lp_26m_wait_auto_gate_sel : 1;    // [1]
        uint32_t xtal_26m_wait_auto_gate_sel : 1;       // [2]
        uint32_t audio_pll_122m_wait_auto_gate_sel : 1; // [3]
        uint32_t mempll_1000m_wait_auto_gate_sel : 1;   // [4]
        uint32_t apll_1000m_wait_auto_gate_sel : 1;     // [5]
        uint32_t __31_6 : 26;                           // [31:6]
    } b;
} REG_AON_CLK_GEN_PLL_WAIT_SEL0_CFG_T;

// pll_wait_sw_ctl0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rc26m_78m_wait_force_en : 1;      // [0]
        uint32_t xtal_lp_26m_wait_force_en : 1;    // [1]
        uint32_t xtal_26m_wait_force_en : 1;       // [2]
        uint32_t audio_pll_122m_wait_force_en : 1; // [3]
        uint32_t mempll_1000m_wait_force_en : 1;   // [4]
        uint32_t apll_1000m_wait_force_en : 1;     // [5]
        uint32_t __31_6 : 26;                      // [31:6]
    } b;
} REG_AON_CLK_GEN_PLL_WAIT_SW_CTL0_CFG_T;

// div_en_sel0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mempll_div_1000m_500m_auto_gate_sel : 1;   // [0]
        uint32_t audio_div_pll_122m_30m7_auto_gate_sel : 1; // [1]
        uint32_t apll_div_1000m_100m_auto_gate_sel : 1;     // [2]
        uint32_t apll_div_1000m_200m_auto_gate_sel : 1;     // [3]
        uint32_t apll_div_1000m_166m7_auto_gate_sel : 1;    // [4]
        uint32_t apll_div_1000m_333m3_auto_gate_sel : 1;    // [5]
        uint32_t apll_div_1000m_31m2_auto_gate_sel : 1;     // [6]
        uint32_t apll_div_1000m_62m5_auto_gate_sel : 1;     // [7]
        uint32_t apll_div_1000m_125m_auto_gate_sel : 1;     // [8]
        uint32_t apll_div_1000m_250m_auto_gate_sel : 1;     // [9]
        uint32_t apll_div_1000m_500m_auto_gate_sel : 1;     // [10]
        uint32_t apll_div_1000m_90m9_auto_gate_sel : 1;     // [11]
        uint32_t __31_12 : 20;                              // [31:12]
    } b;
} REG_AON_CLK_GEN_DIV_EN_SEL0_CFG_T;

// div_en_sw_ctl0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t mempll_div_1000m_500m_force_en : 1;   // [0]
        uint32_t audio_div_pll_122m_30m7_force_en : 1; // [1]
        uint32_t apll_div_1000m_100m_force_en : 1;     // [2]
        uint32_t apll_div_1000m_200m_force_en : 1;     // [3]
        uint32_t apll_div_1000m_166m7_force_en : 1;    // [4]
        uint32_t apll_div_1000m_333m3_force_en : 1;    // [5]
        uint32_t apll_div_1000m_31m2_force_en : 1;     // [6]
        uint32_t apll_div_1000m_62m5_force_en : 1;     // [7]
        uint32_t apll_div_1000m_125m_force_en : 1;     // [8]
        uint32_t apll_div_1000m_250m_force_en : 1;     // [9]
        uint32_t apll_div_1000m_500m_force_en : 1;     // [10]
        uint32_t apll_div_1000m_90m9_force_en : 1;     // [11]
        uint32_t __31_12 : 20;                         // [31:12]
    } b;
} REG_AON_CLK_GEN_DIV_EN_SW_CTL0_CFG_T;

// gate_en_sel0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_mempll_500m_pub_auto_gate_sel : 1;      // [0]
        uint32_t cgm_xtal_26m_pub_auto_gate_sel : 1;         // [1]
        uint32_t cgm_rc_26m_pub_auto_gate_sel : 1;           // [2]
        uint32_t cgm_audiopll_30_72m_aon_auto_gate_sel : 1;  // [3]
        uint32_t cgm_audiopll_122_88m_aon_auto_gate_sel : 1; // [4]
        uint32_t cgm_apll_31_25m_aon_auto_gate_sel : 1;      // [5]
        uint32_t cgm_apll_62_5m_aon_auto_gate_sel : 1;       // [6]
        uint32_t cgm_apll_100m_aon_auto_gate_sel : 1;        // [7]
        uint32_t cgm_apll_125m_aon_auto_gate_sel : 1;        // [8]
        uint32_t cgm_apll_167m_aon_auto_gate_sel : 1;        // [9]
        uint32_t cgm_apll_200m_aon_auto_gate_sel : 1;        // [10]
        uint32_t cgm_apll_250m_aon_auto_gate_sel : 1;        // [11]
        uint32_t cgm_apll_333m_aon_auto_gate_sel : 1;        // [12]
        uint32_t cgm_apll_400m_aon_auto_gate_sel : 1;        // [13]
        uint32_t cgm_xtal_lp_26m_aon_auto_gate_sel : 1;      // [14]
        uint32_t cgm_xtal_26m_aon_auto_gate_sel : 1;         // [15]
        uint32_t cgm_rc_26m_aon_auto_gate_sel : 1;           // [16]
        uint32_t cgm_apll_200m_cp_auto_gate_sel : 1;         // [17]
        uint32_t cgm_apll_400m_cp_auto_gate_sel : 1;         // [18]
        uint32_t cgm_xtal_26m_cp_auto_gate_sel : 1;          // [19]
        uint32_t cgm_rtc_32k_cp_auto_gate_sel : 1;           // [20]
        uint32_t cgm_apll_31_25m_ap_auto_gate_sel : 1;       // [21]
        uint32_t cgm_apll_62_5m_ap_auto_gate_sel : 1;        // [22]
        uint32_t cgm_apll_100m_ap_auto_gate_sel : 1;         // [23]
        uint32_t cgm_apll_125m_ap_auto_gate_sel : 1;         // [24]
        uint32_t cgm_apll_167m_ap_auto_gate_sel : 1;         // [25]
        uint32_t cgm_apll_250m_ap_auto_gate_sel : 1;         // [26]
        uint32_t cgm_apll_400m_ap_auto_gate_sel : 1;         // [27]
        uint32_t cgm_apll_500m_ap_auto_gate_sel : 1;         // [28]
        uint32_t cgm_xtal_26m_ap_auto_gate_sel : 1;          // [29]
        uint32_t cgm_rc_26m_ap_auto_gate_sel : 1;            // [30]
        uint32_t cgm_rtc_32k_ap_auto_gate_sel : 1;           // [31]
    } b;
} REG_AON_CLK_GEN_GATE_EN_SEL0_CFG_T;

// gate_en_sel1_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_xtal_26m_rf_auto_gate_sel : 1;     // [0]
        uint32_t cgm_apll_62_5m_gnss_auto_gate_sel : 1; // [1]
        uint32_t cgm_apll_125m_gnss_auto_gate_sel : 1;  // [2]
        uint32_t cgm_apll_167m_gnss_auto_gate_sel : 1;  // [3]
        uint32_t cgm_xtal_26m_gnss_auto_gate_sel : 1;   // [4]
        uint32_t cgm_apll_250m_pub_auto_gate_sel : 1;   // [5]
        uint32_t cgm_apll_400m_pub_auto_gate_sel : 1;   // [6]
        uint32_t cgm_apll_500m_pub_auto_gate_sel : 1;   // [7]
        uint32_t __31_8 : 24;                           // [31:8]
    } b;
} REG_AON_CLK_GEN_GATE_EN_SEL1_CFG_T;

// gate_en_sw_ctl0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_mempll_500m_pub_force_en : 1;      // [0]
        uint32_t cgm_xtal_26m_pub_force_en : 1;         // [1]
        uint32_t cgm_rc_26m_pub_force_en : 1;           // [2]
        uint32_t cgm_audiopll_30_72m_aon_force_en : 1;  // [3]
        uint32_t cgm_audiopll_122_88m_aon_force_en : 1; // [4]
        uint32_t cgm_apll_31_25m_aon_force_en : 1;      // [5]
        uint32_t cgm_apll_62_5m_aon_force_en : 1;       // [6]
        uint32_t cgm_apll_100m_aon_force_en : 1;        // [7]
        uint32_t cgm_apll_125m_aon_force_en : 1;        // [8]
        uint32_t cgm_apll_167m_aon_force_en : 1;        // [9]
        uint32_t cgm_apll_200m_aon_force_en : 1;        // [10]
        uint32_t cgm_apll_250m_aon_force_en : 1;        // [11]
        uint32_t cgm_apll_333m_aon_force_en : 1;        // [12]
        uint32_t cgm_apll_400m_aon_force_en : 1;        // [13]
        uint32_t cgm_xtal_lp_26m_aon_force_en : 1;      // [14]
        uint32_t cgm_xtal_26m_aon_force_en : 1;         // [15]
        uint32_t cgm_rc_26m_aon_force_en : 1;           // [16]
        uint32_t cgm_apll_200m_cp_force_en : 1;         // [17]
        uint32_t cgm_apll_400m_cp_force_en : 1;         // [18]
        uint32_t cgm_xtal_26m_cp_force_en : 1;          // [19]
        uint32_t cgm_rtc_32k_cp_force_en : 1;           // [20]
        uint32_t cgm_apll_31_25m_ap_force_en : 1;       // [21]
        uint32_t cgm_apll_62_5m_ap_force_en : 1;        // [22]
        uint32_t cgm_apll_100m_ap_force_en : 1;         // [23]
        uint32_t cgm_apll_125m_ap_force_en : 1;         // [24]
        uint32_t cgm_apll_167m_ap_force_en : 1;         // [25]
        uint32_t cgm_apll_250m_ap_force_en : 1;         // [26]
        uint32_t cgm_apll_400m_ap_force_en : 1;         // [27]
        uint32_t cgm_apll_500m_ap_force_en : 1;         // [28]
        uint32_t cgm_xtal_26m_ap_force_en : 1;          // [29]
        uint32_t cgm_rc_26m_ap_force_en : 1;            // [30]
        uint32_t cgm_rtc_32k_ap_force_en : 1;           // [31]
    } b;
} REG_AON_CLK_GEN_GATE_EN_SW_CTL0_CFG_T;

// gate_en_sw_ctl1_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cgm_xtal_26m_rf_force_en : 1;     // [0]
        uint32_t cgm_apll_62_5m_gnss_force_en : 1; // [1]
        uint32_t cgm_apll_125m_gnss_force_en : 1;  // [2]
        uint32_t cgm_apll_167m_gnss_force_en : 1;  // [3]
        uint32_t cgm_xtal_26m_gnss_force_en : 1;   // [4]
        uint32_t cgm_apll_250m_pub_force_en : 1;   // [5]
        uint32_t cgm_apll_400m_pub_force_en : 1;   // [6]
        uint32_t cgm_apll_500m_pub_force_en : 1;   // [7]
        uint32_t __31_8 : 24;                      // [31:8]
    } b;
} REG_AON_CLK_GEN_GATE_EN_SW_CTL1_CFG_T;

// monitor_wait_en_status0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t monitor_wait_en_status : 6; // [5:0], read only
        uint32_t __31_6 : 26;                // [31:6]
    } b;
} REG_AON_CLK_GEN_MONITOR_WAIT_EN_STATUS0_CFG_T;

// monitor_div_auto_en_status0_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t monitor_div_auto_en_status : 12; // [11:0], read only
        uint32_t __31_12 : 20;                    // [31:12]
    } b;
} REG_AON_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS0_CFG_T;

// monitor_gate_auto_en_status10_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t monitor_gate_auto_en_status1 : 8; // [7:0], read only
        uint32_t __31_8 : 24;                      // [31:8]
    } b;
} REG_AON_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS10_CFG_T;

// soft_cnt_done0_cfg
#define AON_CLK_GEN_RC26M_78M_SOFT_CNT_DONE (1 << 0)
#define AON_CLK_GEN_XTAL_LP_26M_SOFT_CNT_DONE (1 << 1)
#define AON_CLK_GEN_XTAL_26M_SOFT_CNT_DONE (1 << 2)
#define AON_CLK_GEN_AUDIO_PLL_122M_SOFT_CNT_DONE (1 << 3)
#define AON_CLK_GEN_MEMPLL_1000M_SOFT_CNT_DONE (1 << 4)
#define AON_CLK_GEN_APLL_1000M_SOFT_CNT_DONE (1 << 5)

// pll_wait_sel0_cfg
#define AON_CLK_GEN_RC26M_78M_WAIT_AUTO_GATE_SEL (1 << 0)
#define AON_CLK_GEN_XTAL_LP_26M_WAIT_AUTO_GATE_SEL (1 << 1)
#define AON_CLK_GEN_XTAL_26M_WAIT_AUTO_GATE_SEL (1 << 2)
#define AON_CLK_GEN_AUDIO_PLL_122M_WAIT_AUTO_GATE_SEL (1 << 3)
#define AON_CLK_GEN_MEMPLL_1000M_WAIT_AUTO_GATE_SEL (1 << 4)
#define AON_CLK_GEN_APLL_1000M_WAIT_AUTO_GATE_SEL (1 << 5)

// pll_wait_sw_ctl0_cfg
#define AON_CLK_GEN_RC26M_78M_WAIT_FORCE_EN (1 << 0)
#define AON_CLK_GEN_XTAL_LP_26M_WAIT_FORCE_EN (1 << 1)
#define AON_CLK_GEN_XTAL_26M_WAIT_FORCE_EN (1 << 2)
#define AON_CLK_GEN_AUDIO_PLL_122M_WAIT_FORCE_EN (1 << 3)
#define AON_CLK_GEN_MEMPLL_1000M_WAIT_FORCE_EN (1 << 4)
#define AON_CLK_GEN_APLL_1000M_WAIT_FORCE_EN (1 << 5)

// div_en_sel0_cfg
#define AON_CLK_GEN_MEMPLL_DIV_1000M_500M_AUTO_GATE_SEL (1 << 0)
#define AON_CLK_GEN_AUDIO_DIV_PLL_122M_30M7_AUTO_GATE_SEL (1 << 1)
#define AON_CLK_GEN_APLL_DIV_1000M_100M_AUTO_GATE_SEL (1 << 2)
#define AON_CLK_GEN_APLL_DIV_1000M_200M_AUTO_GATE_SEL (1 << 3)
#define AON_CLK_GEN_APLL_DIV_1000M_166M7_AUTO_GATE_SEL (1 << 4)
#define AON_CLK_GEN_APLL_DIV_1000M_333M3_AUTO_GATE_SEL (1 << 5)
#define AON_CLK_GEN_APLL_DIV_1000M_31M2_AUTO_GATE_SEL (1 << 6)
#define AON_CLK_GEN_APLL_DIV_1000M_62M5_AUTO_GATE_SEL (1 << 7)
#define AON_CLK_GEN_APLL_DIV_1000M_125M_AUTO_GATE_SEL (1 << 8)
#define AON_CLK_GEN_APLL_DIV_1000M_250M_AUTO_GATE_SEL (1 << 9)
#define AON_CLK_GEN_APLL_DIV_1000M_500M_AUTO_GATE_SEL (1 << 10)
#define AON_CLK_GEN_APLL_DIV_1000M_90M9_AUTO_GATE_SEL (1 << 11)

// div_en_sw_ctl0_cfg
#define AON_CLK_GEN_MEMPLL_DIV_1000M_500M_FORCE_EN (1 << 0)
#define AON_CLK_GEN_AUDIO_DIV_PLL_122M_30M7_FORCE_EN (1 << 1)
#define AON_CLK_GEN_APLL_DIV_1000M_100M_FORCE_EN (1 << 2)
#define AON_CLK_GEN_APLL_DIV_1000M_200M_FORCE_EN (1 << 3)
#define AON_CLK_GEN_APLL_DIV_1000M_166M7_FORCE_EN (1 << 4)
#define AON_CLK_GEN_APLL_DIV_1000M_333M3_FORCE_EN (1 << 5)
#define AON_CLK_GEN_APLL_DIV_1000M_31M2_FORCE_EN (1 << 6)
#define AON_CLK_GEN_APLL_DIV_1000M_62M5_FORCE_EN (1 << 7)
#define AON_CLK_GEN_APLL_DIV_1000M_125M_FORCE_EN (1 << 8)
#define AON_CLK_GEN_APLL_DIV_1000M_250M_FORCE_EN (1 << 9)
#define AON_CLK_GEN_APLL_DIV_1000M_500M_FORCE_EN (1 << 10)
#define AON_CLK_GEN_APLL_DIV_1000M_90M9_FORCE_EN (1 << 11)

// gate_en_sel0_cfg
#define AON_CLK_GEN_CGM_MEMPLL_500M_PUB_AUTO_GATE_SEL (1 << 0)
#define AON_CLK_GEN_CGM_XTAL_26M_PUB_AUTO_GATE_SEL (1 << 1)
#define AON_CLK_GEN_CGM_RC_26M_PUB_AUTO_GATE_SEL (1 << 2)
#define AON_CLK_GEN_CGM_AUDIOPLL_30_72M_AON_AUTO_GATE_SEL (1 << 3)
#define AON_CLK_GEN_CGM_AUDIOPLL_122_88M_AON_AUTO_GATE_SEL (1 << 4)
#define AON_CLK_GEN_CGM_APLL_31_25M_AON_AUTO_GATE_SEL (1 << 5)
#define AON_CLK_GEN_CGM_APLL_62_5M_AON_AUTO_GATE_SEL (1 << 6)
#define AON_CLK_GEN_CGM_APLL_100M_AON_AUTO_GATE_SEL (1 << 7)
#define AON_CLK_GEN_CGM_APLL_125M_AON_AUTO_GATE_SEL (1 << 8)
#define AON_CLK_GEN_CGM_APLL_167M_AON_AUTO_GATE_SEL (1 << 9)
#define AON_CLK_GEN_CGM_APLL_200M_AON_AUTO_GATE_SEL (1 << 10)
#define AON_CLK_GEN_CGM_APLL_250M_AON_AUTO_GATE_SEL (1 << 11)
#define AON_CLK_GEN_CGM_APLL_333M_AON_AUTO_GATE_SEL (1 << 12)
#define AON_CLK_GEN_CGM_APLL_400M_AON_AUTO_GATE_SEL (1 << 13)
#define AON_CLK_GEN_CGM_XTAL_LP_26M_AON_AUTO_GATE_SEL (1 << 14)
#define AON_CLK_GEN_CGM_XTAL_26M_AON_AUTO_GATE_SEL (1 << 15)
#define AON_CLK_GEN_CGM_RC_26M_AON_AUTO_GATE_SEL (1 << 16)
#define AON_CLK_GEN_CGM_APLL_200M_CP_AUTO_GATE_SEL (1 << 17)
#define AON_CLK_GEN_CGM_APLL_400M_CP_AUTO_GATE_SEL (1 << 18)
#define AON_CLK_GEN_CGM_XTAL_26M_CP_AUTO_GATE_SEL (1 << 19)
#define AON_CLK_GEN_CGM_RTC_32K_CP_AUTO_GATE_SEL (1 << 20)
#define AON_CLK_GEN_CGM_APLL_31_25M_AP_AUTO_GATE_SEL (1 << 21)
#define AON_CLK_GEN_CGM_APLL_62_5M_AP_AUTO_GATE_SEL (1 << 22)
#define AON_CLK_GEN_CGM_APLL_100M_AP_AUTO_GATE_SEL (1 << 23)
#define AON_CLK_GEN_CGM_APLL_125M_AP_AUTO_GATE_SEL (1 << 24)
#define AON_CLK_GEN_CGM_APLL_167M_AP_AUTO_GATE_SEL (1 << 25)
#define AON_CLK_GEN_CGM_APLL_250M_AP_AUTO_GATE_SEL (1 << 26)
#define AON_CLK_GEN_CGM_APLL_400M_AP_AUTO_GATE_SEL (1 << 27)
#define AON_CLK_GEN_CGM_APLL_500M_AP_AUTO_GATE_SEL (1 << 28)
#define AON_CLK_GEN_CGM_XTAL_26M_AP_AUTO_GATE_SEL (1 << 29)
#define AON_CLK_GEN_CGM_RC_26M_AP_AUTO_GATE_SEL (1 << 30)
#define AON_CLK_GEN_CGM_RTC_32K_AP_AUTO_GATE_SEL (1 << 31)

// gate_en_sel1_cfg
#define AON_CLK_GEN_CGM_XTAL_26M_RF_AUTO_GATE_SEL (1 << 0)
#define AON_CLK_GEN_CGM_APLL_62_5M_GNSS_AUTO_GATE_SEL (1 << 1)
#define AON_CLK_GEN_CGM_APLL_125M_GNSS_AUTO_GATE_SEL (1 << 2)
#define AON_CLK_GEN_CGM_APLL_167M_GNSS_AUTO_GATE_SEL (1 << 3)
#define AON_CLK_GEN_CGM_XTAL_26M_GNSS_AUTO_GATE_SEL (1 << 4)
#define AON_CLK_GEN_CGM_APLL_250M_PUB_AUTO_GATE_SEL (1 << 5)
#define AON_CLK_GEN_CGM_APLL_400M_PUB_AUTO_GATE_SEL (1 << 6)
#define AON_CLK_GEN_CGM_APLL_500M_PUB_AUTO_GATE_SEL (1 << 7)

// gate_en_sw_ctl0_cfg
#define AON_CLK_GEN_CGM_MEMPLL_500M_PUB_FORCE_EN (1 << 0)
#define AON_CLK_GEN_CGM_XTAL_26M_PUB_FORCE_EN (1 << 1)
#define AON_CLK_GEN_CGM_RC_26M_PUB_FORCE_EN (1 << 2)
#define AON_CLK_GEN_CGM_AUDIOPLL_30_72M_AON_FORCE_EN (1 << 3)
#define AON_CLK_GEN_CGM_AUDIOPLL_122_88M_AON_FORCE_EN (1 << 4)
#define AON_CLK_GEN_CGM_APLL_31_25M_AON_FORCE_EN (1 << 5)
#define AON_CLK_GEN_CGM_APLL_62_5M_AON_FORCE_EN (1 << 6)
#define AON_CLK_GEN_CGM_APLL_100M_AON_FORCE_EN (1 << 7)
#define AON_CLK_GEN_CGM_APLL_125M_AON_FORCE_EN (1 << 8)
#define AON_CLK_GEN_CGM_APLL_167M_AON_FORCE_EN (1 << 9)
#define AON_CLK_GEN_CGM_APLL_200M_AON_FORCE_EN (1 << 10)
#define AON_CLK_GEN_CGM_APLL_250M_AON_FORCE_EN (1 << 11)
#define AON_CLK_GEN_CGM_APLL_333M_AON_FORCE_EN (1 << 12)
#define AON_CLK_GEN_CGM_APLL_400M_AON_FORCE_EN (1 << 13)
#define AON_CLK_GEN_CGM_XTAL_LP_26M_AON_FORCE_EN (1 << 14)
#define AON_CLK_GEN_CGM_XTAL_26M_AON_FORCE_EN (1 << 15)
#define AON_CLK_GEN_CGM_RC_26M_AON_FORCE_EN (1 << 16)
#define AON_CLK_GEN_CGM_APLL_200M_CP_FORCE_EN (1 << 17)
#define AON_CLK_GEN_CGM_APLL_400M_CP_FORCE_EN (1 << 18)
#define AON_CLK_GEN_CGM_XTAL_26M_CP_FORCE_EN (1 << 19)
#define AON_CLK_GEN_CGM_RTC_32K_CP_FORCE_EN (1 << 20)
#define AON_CLK_GEN_CGM_APLL_31_25M_AP_FORCE_EN (1 << 21)
#define AON_CLK_GEN_CGM_APLL_62_5M_AP_FORCE_EN (1 << 22)
#define AON_CLK_GEN_CGM_APLL_100M_AP_FORCE_EN (1 << 23)
#define AON_CLK_GEN_CGM_APLL_125M_AP_FORCE_EN (1 << 24)
#define AON_CLK_GEN_CGM_APLL_167M_AP_FORCE_EN (1 << 25)
#define AON_CLK_GEN_CGM_APLL_250M_AP_FORCE_EN (1 << 26)
#define AON_CLK_GEN_CGM_APLL_400M_AP_FORCE_EN (1 << 27)
#define AON_CLK_GEN_CGM_APLL_500M_AP_FORCE_EN (1 << 28)
#define AON_CLK_GEN_CGM_XTAL_26M_AP_FORCE_EN (1 << 29)
#define AON_CLK_GEN_CGM_RC_26M_AP_FORCE_EN (1 << 30)
#define AON_CLK_GEN_CGM_RTC_32K_AP_FORCE_EN (1 << 31)

// gate_en_sw_ctl1_cfg
#define AON_CLK_GEN_CGM_XTAL_26M_RF_FORCE_EN (1 << 0)
#define AON_CLK_GEN_CGM_APLL_62_5M_GNSS_FORCE_EN (1 << 1)
#define AON_CLK_GEN_CGM_APLL_125M_GNSS_FORCE_EN (1 << 2)
#define AON_CLK_GEN_CGM_APLL_167M_GNSS_FORCE_EN (1 << 3)
#define AON_CLK_GEN_CGM_XTAL_26M_GNSS_FORCE_EN (1 << 4)
#define AON_CLK_GEN_CGM_APLL_250M_PUB_FORCE_EN (1 << 5)
#define AON_CLK_GEN_CGM_APLL_400M_PUB_FORCE_EN (1 << 6)
#define AON_CLK_GEN_CGM_APLL_500M_PUB_FORCE_EN (1 << 7)

// monitor_wait_en_status0_cfg
#define AON_CLK_GEN_MONITOR_WAIT_EN_STATUS(n) (((n)&0x3f) << 0)

// monitor_div_auto_en_status0_cfg
#define AON_CLK_GEN_MONITOR_DIV_AUTO_EN_STATUS(n) (((n)&0xfff) << 0)

// monitor_gate_auto_en_status10_cfg
#define AON_CLK_GEN_MONITOR_GATE_AUTO_EN_STATUS1(n) (((n)&0xff) << 0)

#endif // _AON_CLK_GEN_H_
