/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _AP_APB_H_
#define _AP_APB_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_AP_APB_SET_OFFSET (1024)
#define REG_AP_APB_CLR_OFFSET (2048)

#define REG_AP_APB_BASE (0x04803000)

typedef volatile struct
{
    uint32_t clk_ap_mode0;            // 0x00000000
    uint32_t clk_ap_en0;              // 0x00000004
    uint32_t clk_ap_mode1;            // 0x00000008
    uint32_t clk_ap_en1;              // 0x0000000c
    uint32_t clk_ap_mode2;            // 0x00000010
    uint32_t clk_ap_en2;              // 0x00000014
    uint32_t ap_rst0;                 // 0x00000018
    uint32_t ap_rst1;                 // 0x0000001c
    uint32_t ap_rst2;                 // 0x00000020
    uint32_t m0_lpc;                  // 0x00000024
    uint32_t m1_lpc;                  // 0x00000028
    uint32_t m2_lpc;                  // 0x0000002c
    uint32_t m3_lpc;                  // 0x00000030
    uint32_t m4_lpc;                  // 0x00000034
    uint32_t m5_lpc;                  // 0x00000038
    uint32_t m6_lpc;                  // 0x0000003c
    uint32_t m7_lpc;                  // 0x00000040
    uint32_t m8_lpc;                  // 0x00000044
    uint32_t m9_lpc;                  // 0x00000048
    uint32_t s0_lpc;                  // 0x0000004c
    uint32_t s1_lpc;                  // 0x00000050
    uint32_t s2_lpc;                  // 0x00000054
    uint32_t s3_lpc;                  // 0x00000058
    uint32_t s4_lpc;                  // 0x0000005c
    uint32_t s5_lpc;                  // 0x00000060
    uint32_t s6_lpc;                  // 0x00000064
    uint32_t main_lpc;                // 0x00000068
    uint32_t cache_emmc_sdio;         // 0x0000006c
    uint32_t misc_cfg;                // 0x00000070
    uint32_t chip_prod_id;            // 0x00000074
    uint32_t cfg_qos0;                // 0x00000078
    uint32_t cfg_qos1;                // 0x0000007c
    uint32_t cfg_qos2;                // 0x00000080
    uint32_t debug_monitor;           // 0x00000084
    uint32_t xhb_awsparse;            // 0x00000088
    uint32_t clk_mnt26m_th0;          // 0x0000008c
    uint32_t clk_mnt26m_th1;          // 0x00000090
    uint32_t clk_mnt26m_th2;          // 0x00000094
    uint32_t clk_mnt26m_th3;          // 0x00000098
    uint32_t clk_mnt32k_th0;          // 0x0000009c
    uint32_t clk_mnt32k_th1;          // 0x000000a0
    uint32_t clk_mnt_ctrl;            // 0x000000a4
    uint32_t cfg_bridge;              // 0x000000a8
    uint32_t __172[1];                // 0x000000ac
    uint32_t cgm_gate_auto_sel0;      // 0x000000b0
    uint32_t cgm_gate_auto_sel1;      // 0x000000b4
    uint32_t cgm_gate_auto_sel2;      // 0x000000b8
    uint32_t cgm_gate_auto_sel3;      // 0x000000bc
    uint32_t cgm_gate_force_en0;      // 0x000000c0
    uint32_t cgm_gate_force_en1;      // 0x000000c4
    uint32_t cgm_gate_force_en2;      // 0x000000c8
    uint32_t cgm_gate_force_en3;      // 0x000000cc
    uint32_t mnt_gate_en_status0;     // 0x000000d0
    uint32_t mnt_gate_en_status1;     // 0x000000d4
    uint32_t mnt_gate_en_status2;     // 0x000000d8
    uint32_t mnt_gate_en_status3;     // 0x000000dc
    uint32_t mnt_cgm_busy_status0;    // 0x000000e0
    uint32_t mnt_cgm_busy_status1;    // 0x000000e4
    uint32_t mnt_cgm_busy_status2;    // 0x000000e8
    uint32_t mnt_cgm_busy_status3;    // 0x000000ec
    uint32_t mnt_cgm_busy_status4;    // 0x000000f0
    uint32_t __244[3];                // 0x000000f4
    uint32_t cfg_clk_uart4;           // 0x00000100
    uint32_t cfg_clk_uart5;           // 0x00000104
    uint32_t cfg_clk_uart6;           // 0x00000108
    uint32_t cfg_clk_spiflash1;       // 0x0000010c
    uint32_t cfg_clk_spiflash2;       // 0x00000110
    uint32_t cfg_clk_apcpu_dbgen;     // 0x00000114
    uint32_t lp_force;                // 0x00000118
    uint32_t sleep_ctrl;              // 0x0000011c
    uint32_t light_sleep_bypass0;     // 0x00000120
    uint32_t light_sleep_bypass1;     // 0x00000124
    uint32_t anti_hang;               // 0x00000128
    uint32_t __300[1];                // 0x0000012c
    uint32_t ap_apb_rsd0;             // 0x00000130
    uint32_t ap_apb_rsd1;             // 0x00000134
    uint32_t ap_apb_rsd2;             // 0x00000138
    uint32_t ap_apb_rsd3;             // 0x0000013c
    uint32_t ap2pub_bridge_status;    // 0x00000140
    uint32_t ap2pub_bridge_debug;     // 0x00000144
    uint32_t __328[174];              // 0x00000148
    uint32_t clk_ap_mode0_set;        // 0x00000400
    uint32_t clk_ap_en0_set;          // 0x00000404
    uint32_t clk_ap_mode1_set;        // 0x00000408
    uint32_t clk_ap_en1_set;          // 0x0000040c
    uint32_t clk_ap_mode2_set;        // 0x00000410
    uint32_t clk_ap_en2_set;          // 0x00000414
    uint32_t ap_rst0_set;             // 0x00000418
    uint32_t ap_rst1_set;             // 0x0000041c
    uint32_t ap_rst2_set;             // 0x00000420
    uint32_t __1060[61];              // 0x00000424
    uint32_t lp_force_set;            // 0x00000518
    uint32_t sleep_ctrl_set;          // 0x0000051c
    uint32_t light_sleep_bypass0_set; // 0x00000520
    uint32_t light_sleep_bypass1_set; // 0x00000524
    uint32_t anti_hang_set;           // 0x00000528
    uint32_t __1324[181];             // 0x0000052c
    uint32_t clk_ap_mode0_clr;        // 0x00000800
    uint32_t clk_ap_en0_clr;          // 0x00000804
    uint32_t clk_ap_mode1_clr;        // 0x00000808
    uint32_t clk_ap_en1_clr;          // 0x0000080c
    uint32_t clk_ap_mode2_clr;        // 0x00000810
    uint32_t clk_ap_en2_clr;          // 0x00000814
    uint32_t ap_rst0_clr;             // 0x00000818
    uint32_t ap_rst1_clr;             // 0x0000081c
    uint32_t ap_rst2_clr;             // 0x00000820
    uint32_t __2084[61];              // 0x00000824
    uint32_t lp_force_clr;            // 0x00000918
    uint32_t sleep_ctrl_clr;          // 0x0000091c
    uint32_t light_sleep_bypass0_clr; // 0x00000920
    uint32_t light_sleep_bypass1_clr; // 0x00000924
    uint32_t anti_hang_clr;           // 0x00000928
} HWP_AP_APB_T;

#define hwp_apApb ((HWP_AP_APB_T *)REG_ACCESS_ADDRESS(REG_AP_APB_BASE))

// clk_ap_mode0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mode_ap_a5_fr : 1;        // [0]
        uint32_t clk_mode_ap_bus_fr : 1;       // [1]
        uint32_t clk_mode_uart4_bf_div_fr : 1; // [2]
        uint32_t clk_mode_uart5_bf_div_fr : 1; // [3]
        uint32_t clk_mode_uart6_bf_div_fr : 1; // [4]
        uint32_t clk_mode_spiflash1_fr : 1;    // [5]
        uint32_t clk_mode_spiflash2_fr : 1;    // [6]
        uint32_t clk_mode_camera_pix_fr : 1;   // [7]
        uint32_t clk_mode_camera_ref_fr : 1;   // [8]
        uint32_t clk_mode_camera_csi_fr : 1;   // [9]
        uint32_t clk_mode_spi1_fr : 1;         // [10]
        uint32_t clk_mode_i2c1_fr : 1;         // [11]
        uint32_t clk_mode_i2c2_fr : 1;         // [12]
        uint32_t clk_mode_gpt3_fr : 1;         // [13]
        uint32_t clk_mode_32k_fr : 1;          // [14]
        uint32_t clk_mode_26m_fr : 1;          // [15]
        uint32_t clk_mode_rc26m_fr : 1;        // [16]
        uint32_t __31_17 : 15;                 // [31:17]
    } b;
} REG_AP_APB_CLK_AP_MODE0_T;

// clk_ap_en0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_en_ap_a5_fr : 1;        // [0]
        uint32_t clk_en_ap_bus_fr : 1;       // [1]
        uint32_t clk_en_uart4_bf_div_fr : 1; // [2]
        uint32_t clk_en_uart5_bf_div_fr : 1; // [3]
        uint32_t clk_en_uart6_bf_div_fr : 1; // [4]
        uint32_t clk_en_spiflash1_fr : 1;    // [5]
        uint32_t clk_en_spiflash2_fr : 1;    // [6]
        uint32_t clk_en_camera_pix_fr : 1;   // [7]
        uint32_t clk_en_camera_ref_fr : 1;   // [8]
        uint32_t clk_en_camera_csi_fr : 1;   // [9]
        uint32_t clk_en_spi1_fr : 1;         // [10]
        uint32_t clk_en_i2c1_fr : 1;         // [11]
        uint32_t clk_en_i2c2_fr : 1;         // [12]
        uint32_t clk_en_gpt3_fr : 1;         // [13]
        uint32_t clk_en_32k_fr : 1;          // [14]
        uint32_t clk_en_26m_fr : 1;          // [15]
        uint32_t clk_en_rc26m_fr : 1;        // [16]
        uint32_t __31_17 : 15;               // [31:17]
    } b;
} REG_AP_APB_CLK_AP_EN0_T;

// clk_ap_mode1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mode_ap_imem : 1;   // [0]
        uint32_t clk_mode_gic400 : 1;    // [1]
        uint32_t clk_mode_spiflash1 : 1; // [2]
        uint32_t clk_mode_spiflash2 : 1; // [3]
        uint32_t clk_mode_gouda : 1;     // [4]
        uint32_t clk_mode_ap_axidma : 1; // [5]
        uint32_t clk_mode_med : 1;       // [6]
        uint32_t clk_mode_ce : 1;        // [7]
        uint32_t clk_mode_uart4 : 1;     // [8]
        uint32_t clk_mode_uart5 : 1;     // [9]
        uint32_t clk_mode_uart6 : 1;     // [10]
        uint32_t clk_mode_spi1 : 1;      // [11]
        uint32_t clk_mode_sdmmc : 1;     // [12]
        uint32_t clk_mode_camera : 1;    // [13]
        uint32_t clk_mode_ap_ifc : 1;    // [14]
        uint32_t clk_mode_lzma : 1;      // [15]
        uint32_t clk_mode_ap_busmon : 1; // [16]
        uint32_t clk_mode_emmc : 1;      // [17]
        uint32_t clk_mode_timer1 : 1;    // [18]
        uint32_t clk_mode_timer2 : 1;    // [19]
        uint32_t clk_mode_i2c1 : 1;      // [20]
        uint32_t clk_mode_i2c2 : 1;      // [21]
        uint32_t clk_mode_gpt3 : 1;      // [22]
        uint32_t clk_mode_apb_reg : 1;   // [23]
        uint32_t clk_mode_ap_clk : 1;    // [24]
        uint32_t clk_mode_ap_a5 : 1;     // [25]
        uint32_t clk_mode_ap_a5_dbg : 1; // [26]
        uint32_t clk_mode_mnt32k : 1;    // [27]
        uint32_t clk_mode_mnt26m : 1;    // [28]
        uint32_t __29_29 : 1;            // [29]
        uint32_t clk_mode_ap_ahb : 1;    // [30]
        uint32_t __31_31 : 1;            // [31]
    } b;
} REG_AP_APB_CLK_AP_MODE1_T;

// clk_ap_en1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_en_ap_imem : 1;   // [0]
        uint32_t clk_en_gic400 : 1;    // [1]
        uint32_t clk_en_spiflash1 : 1; // [2]
        uint32_t clk_en_spiflash2 : 1; // [3]
        uint32_t clk_en_gouda : 1;     // [4]
        uint32_t clk_en_ap_axidma : 1; // [5]
        uint32_t clk_en_med : 1;       // [6]
        uint32_t clk_en_ce : 1;        // [7]
        uint32_t clk_en_uart4 : 1;     // [8]
        uint32_t clk_en_uart5 : 1;     // [9]
        uint32_t clk_en_uart6 : 1;     // [10]
        uint32_t clk_en_spi1 : 1;      // [11]
        uint32_t clk_en_sdmmc : 1;     // [12]
        uint32_t clk_en_camera : 1;    // [13]
        uint32_t clk_en_ap_ifc : 1;    // [14]
        uint32_t clk_en_lzma : 1;      // [15]
        uint32_t clk_en_ap_busmon : 1; // [16]
        uint32_t clk_en_emmc : 1;      // [17]
        uint32_t clk_en_timer1 : 1;    // [18]
        uint32_t clk_en_timer2 : 1;    // [19]
        uint32_t clk_en_i2c1 : 1;      // [20]
        uint32_t clk_en_i2c2 : 1;      // [21]
        uint32_t clk_en_gpt3 : 1;      // [22]
        uint32_t clk_en_apb_reg : 1;   // [23]
        uint32_t clk_en_ap_clk : 1;    // [24]
        uint32_t clk_en_ap_a5 : 1;     // [25]
        uint32_t clk_en_ap_a5_dbg : 1; // [26]
        uint32_t clk_en_mnt32k : 1;    // [27]
        uint32_t clk_en_mnt26m : 1;    // [28]
        uint32_t __29_29 : 1;          // [29]
        uint32_t clk_en_ap_ahb : 1;    // [30]
        uint32_t __31_31 : 1;          // [31]
    } b;
} REG_AP_APB_CLK_AP_EN1_T;

// clk_ap_mode2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mode_aon2ap_h2x_async : 1;   // [0]
        uint32_t clk_mode_usb_h2h_async : 1;      // [1]
        uint32_t clk_mode_ap2pub_x2x_async : 1;   // [2]
        uint32_t clk_mode_gouda_h2x_sync : 1;     // [3]
        uint32_t clk_mode_ap_ifc_h2x_sync : 1;    // [4]
        uint32_t clk_mode_med_h2x_sync : 1;       // [5]
        uint32_t clk_mode_ap_ahb_x2h_sync : 1;    // [6]
        uint32_t clk_mode_spiflash1_x2h_sync : 1; // [7]
        uint32_t clk_mode_spiflash2_x2h_sync : 1; // [8]
        uint32_t clk_mode_ap2aon_x2h_sync : 1;    // [9]
        uint32_t clk_mode_ce2efs_p2p_async : 1;   // [10]
        uint32_t clk_mode_i2c1_p2p_async : 1;     // [11]
        uint32_t clk_mode_i2c2_p2p_async : 1;     // [12]
        uint32_t clk_mode_gpt3_p2p_async : 1;     // [13]
        uint32_t __31_14 : 18;                    // [31:14]
    } b;
} REG_AP_APB_CLK_AP_MODE2_T;

// clk_ap_en2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_en_aon2ap_h2x_async : 1;   // [0]
        uint32_t clk_en_usb_h2h_async : 1;      // [1]
        uint32_t clk_en_ap2pub_x2x_async : 1;   // [2]
        uint32_t clk_en_gouda_h2x_sync : 1;     // [3]
        uint32_t clk_en_ap_ifc_h2x_sync : 1;    // [4]
        uint32_t clk_en_med_h2x_sync : 1;       // [5]
        uint32_t clk_en_ap_ahb_x2h_sync : 1;    // [6]
        uint32_t clk_en_spiflash1_x2h_sync : 1; // [7]
        uint32_t clk_en_spiflash2_x2h_sync : 1; // [8]
        uint32_t clk_en_ap2aon_x2h_sync : 1;    // [9]
        uint32_t clk_en_ce2efs_p2p_async : 1;   // [10]
        uint32_t clk_en_i2c1_p2p_async : 1;     // [11]
        uint32_t clk_en_i2c2_p2p_async : 1;     // [12]
        uint32_t clk_en_gpt3_p2p_async : 1;     // [13]
        uint32_t __31_14 : 18;                  // [31:14]
    } b;
} REG_AP_APB_CLK_AP_EN2_T;

// ap_rst0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rst_ap_imem : 1;   // [0]
        uint32_t rst_gic400 : 1;    // [1]
        uint32_t rst_spiflash1 : 1; // [2]
        uint32_t rst_spiflash2 : 1; // [3]
        uint32_t rst_gouda : 1;     // [4]
        uint32_t rst_ap_axidma : 1; // [5]
        uint32_t rst_med : 1;       // [6]
        uint32_t rst_ce_sec : 1;    // [7]
        uint32_t rst_uart4 : 1;     // [8]
        uint32_t rst_uart5 : 1;     // [9]
        uint32_t rst_uart6 : 1;     // [10]
        uint32_t rst_spi1 : 1;      // [11]
        uint32_t rst_sdmmc : 1;     // [12]
        uint32_t rst_camera : 1;    // [13]
        uint32_t rst_ap_ifc : 1;    // [14]
        uint32_t rst_lzma : 1;      // [15]
        uint32_t rst_ap_busmon : 1; // [16]
        uint32_t rst_emmc : 1;      // [17]
        uint32_t rst_timer1 : 1;    // [18]
        uint32_t rst_timer2 : 1;    // [19]
        uint32_t rst_i2c1 : 1;      // [20]
        uint32_t rst_i2c2 : 1;      // [21]
        uint32_t rst_gpt3 : 1;      // [22]
        uint32_t __23_23 : 1;       // [23]
        uint32_t rst_ap_clk : 1;    // [24]
        uint32_t rst_ap_a5 : 1;     // [25]
        uint32_t rst_mnt32k : 1;    // [26]
        uint32_t rst_mnt26m : 1;    // [27]
        uint32_t __28_28 : 1;       // [28]
        uint32_t rst_ce_pub : 1;    // [29]
        uint32_t __31_30 : 2;       // [31:30]
    } b;
} REG_AP_APB_AP_RST0_T;

// ap_rst1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;                  // [0]
        uint32_t rst_ap_a5_dbg : 1;          // [1]
        uint32_t rst_ap_a5_cs : 1;           // [2]
        uint32_t rst_aon2ap_h2x_async : 1;   // [3]
        uint32_t rst_usb_h2h_async : 1;      // [4]
        uint32_t rst_ap2pub_x2x_async : 1;   // [5]
        uint32_t rst_gouda_h2x_sync : 1;     // [6]
        uint32_t rst_ap_ifc_h2x_sync : 1;    // [7]
        uint32_t rst_med_h2x_sync : 1;       // [8]
        uint32_t __9_9 : 1;                  // [9]
        uint32_t rst_spiflash1_x2h_sync : 1; // [10]
        uint32_t rst_spiflash2_x2h_sync : 1; // [11]
        uint32_t rst_ap2aon_x2h_sync : 1;    // [12]
        uint32_t rst_ce2efs_p2p_async : 1;   // [13]
        uint32_t rst_i2c1_p2p_async : 1;     // [14]
        uint32_t rst_i2c2_p2p_async : 1;     // [15]
        uint32_t rst_gpt3_p2p_async : 1;     // [16]
        uint32_t __31_17 : 15;               // [31:17]
    } b;
} REG_AP_APB_AP_RST1_T;

// ap_rst2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t rst_apb_reg : 1; // [0]
        uint32_t __31_1 : 31;     // [31:1]
    } b;
} REG_AP_APB_AP_RST2_T;

// m0_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m0_lp_num : 16; // [15:0]
        uint32_t main_m0_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m0_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M0_LPC_T;

// m1_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m1_lp_num : 16; // [15:0]
        uint32_t main_m1_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m1_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M1_LPC_T;

// m2_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m2_lp_num : 16; // [15:0]
        uint32_t main_m2_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m2_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M2_LPC_T;

// m3_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m3_lp_num : 16; // [15:0]
        uint32_t main_m3_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m3_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M3_LPC_T;

// m4_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m4_lp_num : 16; // [15:0]
        uint32_t main_m4_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m4_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M4_LPC_T;

// m5_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m5_lp_num : 16; // [15:0]
        uint32_t main_m5_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m5_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M5_LPC_T;

// m6_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m6_lp_num : 16; // [15:0]
        uint32_t main_m6_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m6_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M6_LPC_T;

// m7_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m7_lp_num : 16; // [15:0]
        uint32_t main_m7_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m7_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M7_LPC_T;

// m8_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m8_lp_num : 16; // [15:0]
        uint32_t main_m8_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m8_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M8_LPC_T;

// m9_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_m9_lp_num : 16; // [15:0]
        uint32_t main_m9_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_m9_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_M9_LPC_T;

// s0_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s0_lp_num : 16; // [15:0]
        uint32_t main_s0_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s0_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S0_LPC_T;

// s1_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s1_lp_num : 16; // [15:0]
        uint32_t main_s1_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s1_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S1_LPC_T;

// s2_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s2_lp_num : 16; // [15:0]
        uint32_t main_s2_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s2_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S2_LPC_T;

// s3_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s3_lp_num : 16; // [15:0]
        uint32_t main_s3_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s3_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S3_LPC_T;

// s4_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s4_lp_num : 16; // [15:0]
        uint32_t main_s4_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s4_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S4_LPC_T;

// s5_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s5_lp_num : 16; // [15:0]
        uint32_t main_s5_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s5_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S5_LPC_T;

// s6_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_s6_lp_num : 16; // [15:0]
        uint32_t main_s6_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;         // [23:17]
        uint32_t main_s6_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_S6_LPC_T;

// main_lpc
typedef union {
    uint32_t v;
    struct
    {
        uint32_t main_lp_num : 16; // [15:0]
        uint32_t main_lp_eb : 1;   // [16]
        uint32_t __23_17 : 7;      // [23:17]
        uint32_t main_pu_num : 8;  // [31:24]
    } b;
} REG_AP_APB_MAIN_LPC_T;

// cache_emmc_sdio
typedef union {
    uint32_t v;
    struct
    {
        uint32_t awcache_emmc : 4; // [3:0]
        uint32_t arcache_emmc : 4; // [7:4]
        uint32_t __31_8 : 24;      // [31:8]
    } b;
} REG_AP_APB_CACHE_EMMC_SDIO_T;

// misc_cfg
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfgsdisable_gic400 : 1;     // [0]
        uint32_t __5_1 : 5;                  // [5:1]
        uint32_t med_read_bus_sel : 1;       // [6]
        uint32_t ap_ifc_hresp_err_mask : 1;  // [7]
        uint32_t camera_spiclk_pol : 1;      // [8]
        uint32_t camera_refclk_out_en : 1;   // [9]
        uint32_t camera_refclk_out_mode : 1; // [10]
        uint32_t __31_11 : 21;               // [31:11]
    } b;
} REG_AP_APB_MISC_CFG_T;

// chip_prod_id
typedef union {
    uint32_t v;
    struct
    {
        uint32_t metal_id : 12; // [11:0], read only
        uint32_t bond_id : 4;   // [15:12], read only
        uint32_t prod_id : 16;  // [31:16], read only
    } b;
} REG_AP_APB_CHIP_PROD_ID_T;

// cfg_qos0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ap_a5_arqos : 4; // [3:0]
        uint32_t ap_a5_awqos : 4; // [7:4]
        uint32_t ce_arqos : 4;    // [11:8]
        uint32_t ce_awqos : 4;    // [15:12]
        uint32_t emmc_arqos : 4;  // [19:16]
        uint32_t emmc_awqos : 4;  // [23:20]
        uint32_t lzma_arqos : 4;  // [27:24]
        uint32_t lzma_awqos : 4;  // [31:28]
    } b;
} REG_AP_APB_CFG_QOS0_T;

// cfg_qos1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t gouda_arqos : 4;  // [3:0]
        uint32_t gouda_awqos : 4;  // [7:4]
        uint32_t usb_arqos : 4;    // [11:8]
        uint32_t usb_awqos : 4;    // [15:12]
        uint32_t ap_ifc_arqos : 4; // [19:16]
        uint32_t ap_ifc_awqos : 4; // [23:20]
        uint32_t aon_arqos : 4;    // [27:24]
        uint32_t aon_awqos : 4;    // [31:28]
    } b;
} REG_AP_APB_CFG_QOS1_T;

// cfg_qos2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t med_arqos : 4;       // [3:0]
        uint32_t med_awqos : 4;       // [7:4]
        uint32_t ap_axidma_arqos : 4; // [11:8]
        uint32_t ap_axidma_awqos : 4; // [15:12]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_AP_APB_CFG_QOS2_T;

// debug_monitor
typedef union {
    uint32_t v;
    struct
    {
        uint32_t med_dbg_bus_sel : 5; // [4:0]
        uint32_t __31_5 : 27;         // [31:5]
    } b;
} REG_AP_APB_DEBUG_MONITOR_T;

// xhb_awsparse
typedef union {
    uint32_t v;
    struct
    {
        uint32_t xhb_ap_ahb_awsparse : 1;    // [0]
        uint32_t xhb_spiflash1_awsparse : 1; // [1]
        uint32_t xhb_spiflash2_awsparse : 1; // [2]
        uint32_t xhb_ap2aon_awsparse : 1;    // [3]
        uint32_t __31_4 : 28;                // [31:4]
    } b;
} REG_AP_APB_XHB_AWSPARSE_T;

// clk_mnt26m_th0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt26m_th0 : 8; // [7:0]
        uint32_t __31_8 : 24;        // [31:8]
    } b;
} REG_AP_APB_CLK_MNT26M_TH0_T;

// clk_mnt26m_th1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt26m_th1 : 16; // [15:0]
        uint32_t __31_16 : 16;        // [31:16]
    } b;
} REG_AP_APB_CLK_MNT26M_TH1_T;

// clk_mnt26m_th2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt26m_th2 : 7; // [6:0]
        uint32_t __31_7 : 25;        // [31:7]
    } b;
} REG_AP_APB_CLK_MNT26M_TH2_T;

// clk_mnt26m_th3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt26m_th3 : 9; // [8:0]
        uint32_t __31_9 : 23;        // [31:9]
    } b;
} REG_AP_APB_CLK_MNT26M_TH3_T;

// clk_mnt32k_th0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt32k_th0 : 12; // [11:0]
        uint32_t __31_12 : 20;        // [31:12]
    } b;
} REG_AP_APB_CLK_MNT32K_TH0_T;

// clk_mnt32k_th1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt32k_th1 : 12; // [11:0]
        uint32_t __31_12 : 20;        // [31:12]
    } b;
} REG_AP_APB_CLK_MNT32K_TH1_T;

// clk_mnt_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_mnt32k_en : 1;     // [0]
        uint32_t clk_mnt26m_en : 1;     // [1]
        uint32_t en_int_clk_mnt32k : 1; // [2]
        uint32_t en_int_clk_mnt26m : 1; // [3]
        uint32_t st_clk_mnt32k : 1;     // [4]
        uint32_t st_clk_mnt26m : 1;     // [5]
        uint32_t __31_6 : 26;           // [31:6]
    } b;
} REG_AP_APB_CLK_MNT_CTRL_T;

// cfg_bridge
typedef union {
    uint32_t v;
    struct
    {
        uint32_t aon2ap_h2x_async_mclk_auto_gate_en : 1;    // [0]
        uint32_t aon2ap_h2x_async_sclk_auto_gate_en : 1;    // [1]
        uint32_t aon2ap_h2x_async_nonbuf_early_resp_en : 1; // [2]
        uint32_t aon2ap_h2x_async_fifo_clr : 1;             // [3]
        uint32_t aon2ap_h2x_async_fifo_clr_end : 1;         // [4], read only
        uint32_t usb_h2h_async_mclk_auto_gate_en : 1;       // [5]
        uint32_t usb_h2h_async_sclk_auto_gate_en : 1;       // [6]
        uint32_t usb_h2h_async_nonbuf_early_resp_en : 1;    // [7]
        uint32_t usb_h2h_async_fifo_clr : 1;                // [8]
        uint32_t usb_h2h_async_fifo_clr_end : 1;            // [9], read only
        uint32_t gouda_h2x_sync_clk_auto_gate_en : 1;       // [10]
        uint32_t gouda_h2x_sync_nonbuf_early_resp_en : 1;   // [11]
        uint32_t ap_ifc_h2x_sync_clk_auto_gate_en : 1;      // [12]
        uint32_t ap_ifc_h2x_sync_nonbuf_early_resp_en : 1;  // [13]
        uint32_t med_h2x_sync_clk_auto_gate_en : 1;         // [14]
        uint32_t med_h2x_sync_nonbuf_early_resp_en : 1;     // [15]
        uint32_t ce2efs_p2p_async_mclk_auto_gate_en : 1;    // [16]
        uint32_t ce2efs_p2p_async_sclk_auto_gate_en : 1;    // [17]
        uint32_t ce2efs_p2p_async_fifo_clr : 1;             // [18]
        uint32_t ce2efs_p2p_async_fifo_clr_end : 1;         // [19], read only
        uint32_t i2c1_p2p_async_mclk_auto_gate_en : 1;      // [20]
        uint32_t i2c1_p2p_async_sclk_auto_gate_en : 1;      // [21]
        uint32_t i2c1_p2p_async_fifo_clr : 1;               // [22]
        uint32_t i2c1_p2p_async_fifo_clr_end : 1;           // [23], read only
        uint32_t i2c2_p2p_async_mclk_auto_gate_en : 1;      // [24]
        uint32_t i2c2_p2p_async_sclk_auto_gate_en : 1;      // [25]
        uint32_t i2c2_p2p_async_fifo_clr : 1;               // [26]
        uint32_t i2c2_p2p_async_fifo_clr_end : 1;           // [27], read only
        uint32_t gpt3_p2p_async_mclk_auto_gate_en : 1;      // [28]
        uint32_t gpt3_p2p_async_sclk_auto_gate_en : 1;      // [29]
        uint32_t gpt3_p2p_async_fifo_clr : 1;               // [30]
        uint32_t gpt3_p2p_async_fifo_clr_end : 1;           // [31], read only
    } b;
} REG_AP_APB_CFG_BRIDGE_T;

// cfg_clk_uart4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t uart4_div_denom : 17; // [16:0]
        uint32_t uart4_div_num : 13;   // [29:17]
        uint32_t __31_30 : 2;          // [31:30]
    } b;
} REG_AP_APB_CFG_CLK_UART4_T;

// cfg_clk_uart5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t uart5_div_denom : 17; // [16:0]
        uint32_t uart5_div_num : 13;   // [29:17]
        uint32_t __31_30 : 2;          // [31:30]
    } b;
} REG_AP_APB_CFG_CLK_UART5_T;

// cfg_clk_uart6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t uart6_div_denom : 17; // [16:0]
        uint32_t uart6_div_num : 13;   // [29:17]
        uint32_t __31_30 : 2;          // [31:30]
    } b;
} REG_AP_APB_CFG_CLK_UART6_T;

// cfg_clk_spiflash1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t spiflash1_freq : 4; // [3:0]
        uint32_t __31_4 : 28;        // [31:4]
    } b;
} REG_AP_APB_CFG_CLK_SPIFLASH1_T;

// cfg_clk_spiflash2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t spiflash2_freq : 4; // [3:0]
        uint32_t __31_4 : 28;        // [31:4]
    } b;
} REG_AP_APB_CFG_CLK_SPIFLASH2_T;

// cfg_clk_apcpu_dbgen
typedef union {
    uint32_t v;
    struct
    {
        uint32_t div_num : 3;     // [2:0]
        uint32_t div_disable : 1; // [3]
        uint32_t __31_4 : 28;     // [31:4]
    } b;
} REG_AP_APB_CFG_CLK_APCPU_DBGEN_T;

// lp_force
typedef union {
    uint32_t v;
    struct
    {
        uint32_t lp_force_m0 : 1;   // [0]
        uint32_t lp_force_m1 : 1;   // [1]
        uint32_t lp_force_m2 : 1;   // [2]
        uint32_t lp_force_m3 : 1;   // [3]
        uint32_t lp_force_m4 : 1;   // [4]
        uint32_t lp_force_m5 : 1;   // [5]
        uint32_t lp_force_m6 : 1;   // [6]
        uint32_t lp_force_m7 : 1;   // [7]
        uint32_t lp_force_m8 : 1;   // [8]
        uint32_t lp_force_m9 : 1;   // [9]
        uint32_t lp_force_s0 : 1;   // [10]
        uint32_t lp_force_s1 : 1;   // [11]
        uint32_t lp_force_s2 : 1;   // [12]
        uint32_t lp_force_s3 : 1;   // [13]
        uint32_t lp_force_s4 : 1;   // [14]
        uint32_t lp_force_s5 : 1;   // [15]
        uint32_t lp_force_s6 : 1;   // [16]
        uint32_t lp_force_main : 1; // [17]
        uint32_t __31_18 : 14;      // [31:18]
    } b;
} REG_AP_APB_LP_FORCE_T;

// sleep_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t deep_sleep_core_int_disable : 1; // [0]
        uint32_t light_sleep_enable : 1;          // [1]
        uint32_t ap_a5_clk_auto_gate : 1;         // [2]
        uint32_t light_sleep_rc26m_sel : 1;       // [3]
        uint32_t deep_sleep_core_bypass : 1;      // [4]
        uint32_t lp_force_ack_m0 : 1;             // [5], read only
        uint32_t lp_force_ack_m1 : 1;             // [6], read only
        uint32_t lp_force_ack_m2 : 1;             // [7], read only
        uint32_t lp_force_ack_m3 : 1;             // [8], read only
        uint32_t lp_force_ack_m4 : 1;             // [9], read only
        uint32_t lp_force_ack_m5 : 1;             // [10], read only
        uint32_t lp_force_ack_m6 : 1;             // [11], read only
        uint32_t lp_force_ack_m7 : 1;             // [12], read only
        uint32_t lp_force_ack_m8 : 1;             // [13], read only
        uint32_t lp_force_ack_m9 : 1;             // [14], read only
        uint32_t lp_force_ack_s0 : 1;             // [15], read only
        uint32_t lp_force_ack_s1 : 1;             // [16], read only
        uint32_t lp_force_ack_s2 : 1;             // [17], read only
        uint32_t lp_force_ack_s3 : 1;             // [18], read only
        uint32_t lp_force_ack_s4 : 1;             // [19], read only
        uint32_t lp_force_ack_s5 : 1;             // [20], read only
        uint32_t lp_force_ack_s6 : 1;             // [21], read only
        uint32_t lp_force_ack_main : 1;           // [22], read only
        uint32_t __31_23 : 9;                     // [31:23]
    } b;
} REG_AP_APB_SLEEP_CTRL_T;

// light_sleep_bypass0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t light_bypass_m0_lpc : 1;   // [0]
        uint32_t light_bypass_m1_lpc : 1;   // [1]
        uint32_t light_bypass_m2_lpc : 1;   // [2]
        uint32_t light_bypass_m3_lpc : 1;   // [3]
        uint32_t light_bypass_m4_lpc : 1;   // [4]
        uint32_t light_bypass_m5_lpc : 1;   // [5]
        uint32_t light_bypass_m6_lpc : 1;   // [6]
        uint32_t light_bypass_m7_lpc : 1;   // [7]
        uint32_t light_bypass_m8_lpc : 1;   // [8]
        uint32_t light_bypass_m9_lpc : 1;   // [9]
        uint32_t light_bypass_s0_lpc : 1;   // [10]
        uint32_t light_bypass_s1_lpc : 1;   // [11]
        uint32_t light_bypass_s2_lpc : 1;   // [12]
        uint32_t light_bypass_s3_lpc : 1;   // [13]
        uint32_t light_bypass_s4_lpc : 1;   // [14]
        uint32_t light_bypass_s5_lpc : 1;   // [15]
        uint32_t light_bypass_s6_lpc : 1;   // [16]
        uint32_t light_bypass_main_lpc : 1; // [17]
        uint32_t light_bypass_m0 : 1;       // [18]
        uint32_t light_bypass_m1 : 1;       // [19]
        uint32_t light_bypass_m2 : 1;       // [20]
        uint32_t light_bypass_m3 : 1;       // [21]
        uint32_t light_bypass_m4 : 1;       // [22]
        uint32_t light_bypass_m5 : 1;       // [23]
        uint32_t light_bypass_m6 : 1;       // [24]
        uint32_t light_bypass_m7 : 1;       // [25]
        uint32_t light_bypass_m8 : 1;       // [26]
        uint32_t light_bypass_m9 : 1;       // [27]
        uint32_t __31_28 : 4;               // [31:28]
    } b;
} REG_AP_APB_LIGHT_SLEEP_BYPASS0_T;

// light_sleep_bypass1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t light_bypass_uart4 : 1;      // [0]
        uint32_t light_bypass_uart5 : 1;      // [1]
        uint32_t light_bypass_uart6 : 1;      // [2]
        uint32_t light_bypass_sdmmc : 1;      // [3]
        uint32_t light_bypass_camera : 1;     // [4]
        uint32_t light_bypass_i2c1 : 1;       // [5]
        uint32_t light_bypass_i2c2 : 1;       // [6]
        uint32_t light_bypass_gpt3 : 1;       // [7]
        uint32_t light_bypass_spi1 : 1;       // [8]
        uint32_t light_bypass_med : 1;        // [9]
        uint32_t light_bypass_timer1 : 1;     // [10]
        uint32_t light_bypass_timer2 : 1;     // [11]
        uint32_t light_bypass_ap_ifc_ch0 : 1; // [12]
        uint32_t light_bypass_ap_ifc_ch1 : 1; // [13]
        uint32_t light_bypass_ap_ifc_ch2 : 1; // [14]
        uint32_t light_bypass_ap_ifc_ch3 : 1; // [15]
        uint32_t light_bypass_ap_ifc_ch4 : 1; // [16]
        uint32_t light_bypass_ap_ifc_ch5 : 1; // [17]
        uint32_t light_bypass_ap_ifc_ch6 : 1; // [18]
        uint32_t light_bypass_ap_ifc_ch7 : 1; // [19]
        uint32_t light_bypass_ap_ifc_ch8 : 1; // [20]
        uint32_t light_bypass_ap_ifc_ch9 : 1; // [21]
        uint32_t light_bypass_usb_dma : 1;    // [22]
        uint32_t __31_23 : 9;                 // [31:23]
    } b;
} REG_AP_APB_LIGHT_SLEEP_BYPASS1_T;

// anti_hang
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ap2pub_downstream_disable_sel : 1;   // [0]
        uint32_t ap2pub_downstream_disable_force : 1; // [1]
        uint32_t ahb_slave_err_resp_en : 1;           // [2]
        uint32_t apb1_slave_err_resp_en : 1;          // [3]
        uint32_t apb2_slave_err_resp_en : 1;          // [4]
        uint32_t apb3_slave_err_resp_en : 1;          // [5]
        uint32_t ap_a5_err_resp_en : 1;               // [6]
        uint32_t __31_7 : 25;                         // [31:7]
    } b;
} REG_AP_APB_ANTI_HANG_T;

// ap2pub_bridge_status
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ap2pub_axi_detector_overflow : 1; // [0], read only
        uint32_t ap2pub_pwr_handshk_clk_req : 1;   // [1], read only
        uint32_t ap2pub_bridge_trans_idle : 1;     // [2], read only
        uint32_t __31_3 : 29;                      // [31:3]
    } b;
} REG_AP_APB_AP2PUB_BRIDGE_STATUS_T;

// clk_ap_mode0
#define AP_APB_CLK_MODE_AP_A5_FR (1 << 0)
#define AP_APB_CLK_MODE_AP_BUS_FR (1 << 1)
#define AP_APB_CLK_MODE_UART4_BF_DIV_FR (1 << 2)
#define AP_APB_CLK_MODE_UART5_BF_DIV_FR (1 << 3)
#define AP_APB_CLK_MODE_UART6_BF_DIV_FR (1 << 4)
#define AP_APB_CLK_MODE_SPIFLASH1_FR (1 << 5)
#define AP_APB_CLK_MODE_SPIFLASH2_FR (1 << 6)
#define AP_APB_CLK_MODE_CAMERA_PIX_FR (1 << 7)
#define AP_APB_CLK_MODE_CAMERA_REF_FR (1 << 8)
#define AP_APB_CLK_MODE_CAMERA_CSI_FR (1 << 9)
#define AP_APB_CLK_MODE_SPI1_FR (1 << 10)
#define AP_APB_CLK_MODE_I2C1_FR (1 << 11)
#define AP_APB_CLK_MODE_I2C2_FR (1 << 12)
#define AP_APB_CLK_MODE_GPT3_FR (1 << 13)
#define AP_APB_CLK_MODE_32K_FR (1 << 14)
#define AP_APB_CLK_MODE_26M_FR (1 << 15)
#define AP_APB_CLK_MODE_RC26M_FR (1 << 16)

// clk_ap_en0
#define AP_APB_CLK_EN_AP_A5_FR (1 << 0)
#define AP_APB_CLK_EN_AP_BUS_FR (1 << 1)
#define AP_APB_CLK_EN_UART4_BF_DIV_FR (1 << 2)
#define AP_APB_CLK_EN_UART5_BF_DIV_FR (1 << 3)
#define AP_APB_CLK_EN_UART6_BF_DIV_FR (1 << 4)
#define AP_APB_CLK_EN_SPIFLASH1_FR (1 << 5)
#define AP_APB_CLK_EN_SPIFLASH2_FR (1 << 6)
#define AP_APB_CLK_EN_CAMERA_PIX_FR (1 << 7)
#define AP_APB_CLK_EN_CAMERA_REF_FR (1 << 8)
#define AP_APB_CLK_EN_CAMERA_CSI_FR (1 << 9)
#define AP_APB_CLK_EN_SPI1_FR (1 << 10)
#define AP_APB_CLK_EN_I2C1_FR (1 << 11)
#define AP_APB_CLK_EN_I2C2_FR (1 << 12)
#define AP_APB_CLK_EN_GPT3_FR (1 << 13)
#define AP_APB_CLK_EN_32K_FR (1 << 14)
#define AP_APB_CLK_EN_26M_FR (1 << 15)
#define AP_APB_CLK_EN_RC26M_FR (1 << 16)

// clk_ap_mode1
#define AP_APB_CLK_MODE_AP_IMEM (1 << 0)
#define AP_APB_CLK_MODE_GIC400 (1 << 1)
#define AP_APB_CLK_MODE_SPIFLASH1 (1 << 2)
#define AP_APB_CLK_MODE_SPIFLASH2 (1 << 3)
#define AP_APB_CLK_MODE_GOUDA (1 << 4)
#define AP_APB_CLK_MODE_AP_AXIDMA (1 << 5)
#define AP_APB_CLK_MODE_MED (1 << 6)
#define AP_APB_CLK_MODE_CE (1 << 7)
#define AP_APB_CLK_MODE_UART4 (1 << 8)
#define AP_APB_CLK_MODE_UART5 (1 << 9)
#define AP_APB_CLK_MODE_UART6 (1 << 10)
#define AP_APB_CLK_MODE_SPI1 (1 << 11)
#define AP_APB_CLK_MODE_SDMMC (1 << 12)
#define AP_APB_CLK_MODE_CAMERA (1 << 13)
#define AP_APB_CLK_MODE_AP_IFC (1 << 14)
#define AP_APB_CLK_MODE_LZMA (1 << 15)
#define AP_APB_CLK_MODE_AP_BUSMON (1 << 16)
#define AP_APB_CLK_MODE_EMMC (1 << 17)
#define AP_APB_CLK_MODE_TIMER1 (1 << 18)
#define AP_APB_CLK_MODE_TIMER2 (1 << 19)
#define AP_APB_CLK_MODE_I2C1 (1 << 20)
#define AP_APB_CLK_MODE_I2C2 (1 << 21)
#define AP_APB_CLK_MODE_GPT3 (1 << 22)
#define AP_APB_CLK_MODE_APB_REG (1 << 23)
#define AP_APB_CLK_MODE_AP_CLK (1 << 24)
#define AP_APB_CLK_MODE_AP_A5 (1 << 25)
#define AP_APB_CLK_MODE_AP_A5_DBG (1 << 26)
#define AP_APB_CLK_MODE_MNT32K (1 << 27)
#define AP_APB_CLK_MODE_MNT26M (1 << 28)
#define AP_APB_CLK_MODE_AP_AHB (1 << 30)

// clk_ap_en1
#define AP_APB_CLK_EN_AP_IMEM (1 << 0)
#define AP_APB_CLK_EN_GIC400 (1 << 1)
#define AP_APB_CLK_EN_SPIFLASH1 (1 << 2)
#define AP_APB_CLK_EN_SPIFLASH2 (1 << 3)
#define AP_APB_CLK_EN_GOUDA (1 << 4)
#define AP_APB_CLK_EN_AP_AXIDMA (1 << 5)
#define AP_APB_CLK_EN_MED (1 << 6)
#define AP_APB_CLK_EN_CE (1 << 7)
#define AP_APB_CLK_EN_UART4 (1 << 8)
#define AP_APB_CLK_EN_UART5 (1 << 9)
#define AP_APB_CLK_EN_UART6 (1 << 10)
#define AP_APB_CLK_EN_SPI1 (1 << 11)
#define AP_APB_CLK_EN_SDMMC (1 << 12)
#define AP_APB_CLK_EN_CAMERA (1 << 13)
#define AP_APB_CLK_EN_AP_IFC (1 << 14)
#define AP_APB_CLK_EN_LZMA (1 << 15)
#define AP_APB_CLK_EN_AP_BUSMON (1 << 16)
#define AP_APB_CLK_EN_EMMC (1 << 17)
#define AP_APB_CLK_EN_TIMER1 (1 << 18)
#define AP_APB_CLK_EN_TIMER2 (1 << 19)
#define AP_APB_CLK_EN_I2C1 (1 << 20)
#define AP_APB_CLK_EN_I2C2 (1 << 21)
#define AP_APB_CLK_EN_GPT3 (1 << 22)
#define AP_APB_CLK_EN_APB_REG (1 << 23)
#define AP_APB_CLK_EN_AP_CLK (1 << 24)
#define AP_APB_CLK_EN_AP_A5 (1 << 25)
#define AP_APB_CLK_EN_AP_A5_DBG (1 << 26)
#define AP_APB_CLK_EN_MNT32K (1 << 27)
#define AP_APB_CLK_EN_MNT26M (1 << 28)
#define AP_APB_CLK_EN_AP_AHB (1 << 30)

// clk_ap_mode2
#define AP_APB_CLK_MODE_AON2AP_H2X_ASYNC (1 << 0)
#define AP_APB_CLK_MODE_USB_H2H_ASYNC (1 << 1)
#define AP_APB_CLK_MODE_AP2PUB_X2X_ASYNC (1 << 2)
#define AP_APB_CLK_MODE_GOUDA_H2X_SYNC (1 << 3)
#define AP_APB_CLK_MODE_AP_IFC_H2X_SYNC (1 << 4)
#define AP_APB_CLK_MODE_MED_H2X_SYNC (1 << 5)
#define AP_APB_CLK_MODE_AP_AHB_X2H_SYNC (1 << 6)
#define AP_APB_CLK_MODE_SPIFLASH1_X2H_SYNC (1 << 7)
#define AP_APB_CLK_MODE_SPIFLASH2_X2H_SYNC (1 << 8)
#define AP_APB_CLK_MODE_AP2AON_X2H_SYNC (1 << 9)
#define AP_APB_CLK_MODE_CE2EFS_P2P_ASYNC (1 << 10)
#define AP_APB_CLK_MODE_I2C1_P2P_ASYNC (1 << 11)
#define AP_APB_CLK_MODE_I2C2_P2P_ASYNC (1 << 12)
#define AP_APB_CLK_MODE_GPT3_P2P_ASYNC (1 << 13)

// clk_ap_en2
#define AP_APB_CLK_EN_AON2AP_H2X_ASYNC (1 << 0)
#define AP_APB_CLK_EN_USB_H2H_ASYNC (1 << 1)
#define AP_APB_CLK_EN_AP2PUB_X2X_ASYNC (1 << 2)
#define AP_APB_CLK_EN_GOUDA_H2X_SYNC (1 << 3)
#define AP_APB_CLK_EN_AP_IFC_H2X_SYNC (1 << 4)
#define AP_APB_CLK_EN_MED_H2X_SYNC (1 << 5)
#define AP_APB_CLK_EN_AP_AHB_X2H_SYNC (1 << 6)
#define AP_APB_CLK_EN_SPIFLASH1_X2H_SYNC (1 << 7)
#define AP_APB_CLK_EN_SPIFLASH2_X2H_SYNC (1 << 8)
#define AP_APB_CLK_EN_AP2AON_X2H_SYNC (1 << 9)
#define AP_APB_CLK_EN_CE2EFS_P2P_ASYNC (1 << 10)
#define AP_APB_CLK_EN_I2C1_P2P_ASYNC (1 << 11)
#define AP_APB_CLK_EN_I2C2_P2P_ASYNC (1 << 12)
#define AP_APB_CLK_EN_GPT3_P2P_ASYNC (1 << 13)

// ap_rst0
#define AP_APB_RST_AP_IMEM (1 << 0)
#define AP_APB_RST_GIC400 (1 << 1)
#define AP_APB_RST_SPIFLASH1 (1 << 2)
#define AP_APB_RST_SPIFLASH2 (1 << 3)
#define AP_APB_RST_GOUDA (1 << 4)
#define AP_APB_RST_AP_AXIDMA (1 << 5)
#define AP_APB_RST_MED (1 << 6)
#define AP_APB_RST_CE_SEC (1 << 7)
#define AP_APB_RST_UART4 (1 << 8)
#define AP_APB_RST_UART5 (1 << 9)
#define AP_APB_RST_UART6 (1 << 10)
#define AP_APB_RST_SPI1 (1 << 11)
#define AP_APB_RST_SDMMC (1 << 12)
#define AP_APB_RST_CAMERA (1 << 13)
#define AP_APB_RST_AP_IFC (1 << 14)
#define AP_APB_RST_LZMA (1 << 15)
#define AP_APB_RST_AP_BUSMON (1 << 16)
#define AP_APB_RST_EMMC (1 << 17)
#define AP_APB_RST_TIMER1 (1 << 18)
#define AP_APB_RST_TIMER2 (1 << 19)
#define AP_APB_RST_I2C1 (1 << 20)
#define AP_APB_RST_I2C2 (1 << 21)
#define AP_APB_RST_GPT3 (1 << 22)
#define AP_APB_RST_AP_CLK (1 << 24)
#define AP_APB_RST_AP_A5 (1 << 25)
#define AP_APB_RST_MNT32K (1 << 26)
#define AP_APB_RST_MNT26M (1 << 27)
#define AP_APB_RST_CE_PUB (1 << 29)

// ap_rst1
#define AP_APB_RST_AP_A5_DBG (1 << 1)
#define AP_APB_RST_AP_A5_CS (1 << 2)
#define AP_APB_RST_AON2AP_H2X_ASYNC (1 << 3)
#define AP_APB_RST_USB_H2H_ASYNC (1 << 4)
#define AP_APB_RST_AP2PUB_X2X_ASYNC (1 << 5)
#define AP_APB_RST_GOUDA_H2X_SYNC (1 << 6)
#define AP_APB_RST_AP_IFC_H2X_SYNC (1 << 7)
#define AP_APB_RST_MED_H2X_SYNC (1 << 8)
#define AP_APB_RST_SPIFLASH1_X2H_SYNC (1 << 10)
#define AP_APB_RST_SPIFLASH2_X2H_SYNC (1 << 11)
#define AP_APB_RST_AP2AON_X2H_SYNC (1 << 12)
#define AP_APB_RST_CE2EFS_P2P_ASYNC (1 << 13)
#define AP_APB_RST_I2C1_P2P_ASYNC (1 << 14)
#define AP_APB_RST_I2C2_P2P_ASYNC (1 << 15)
#define AP_APB_RST_GPT3_P2P_ASYNC (1 << 16)

// ap_rst2
#define AP_APB_RST_APB_REG (1 << 0)

// m0_lpc
#define AP_APB_MAIN_M0_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M0_LP_EB (1 << 16)
#define AP_APB_MAIN_M0_PU_NUM(n) (((n)&0xff) << 24)

// m1_lpc
#define AP_APB_MAIN_M1_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M1_LP_EB (1 << 16)
#define AP_APB_MAIN_M1_PU_NUM(n) (((n)&0xff) << 24)

// m2_lpc
#define AP_APB_MAIN_M2_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M2_LP_EB (1 << 16)
#define AP_APB_MAIN_M2_PU_NUM(n) (((n)&0xff) << 24)

// m3_lpc
#define AP_APB_MAIN_M3_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M3_LP_EB (1 << 16)
#define AP_APB_MAIN_M3_PU_NUM(n) (((n)&0xff) << 24)

// m4_lpc
#define AP_APB_MAIN_M4_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M4_LP_EB (1 << 16)
#define AP_APB_MAIN_M4_PU_NUM(n) (((n)&0xff) << 24)

// m5_lpc
#define AP_APB_MAIN_M5_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M5_LP_EB (1 << 16)
#define AP_APB_MAIN_M5_PU_NUM(n) (((n)&0xff) << 24)

// m6_lpc
#define AP_APB_MAIN_M6_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M6_LP_EB (1 << 16)
#define AP_APB_MAIN_M6_PU_NUM(n) (((n)&0xff) << 24)

// m7_lpc
#define AP_APB_MAIN_M7_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M7_LP_EB (1 << 16)
#define AP_APB_MAIN_M7_PU_NUM(n) (((n)&0xff) << 24)

// m8_lpc
#define AP_APB_MAIN_M8_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M8_LP_EB (1 << 16)
#define AP_APB_MAIN_M8_PU_NUM(n) (((n)&0xff) << 24)

// m9_lpc
#define AP_APB_MAIN_M9_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_M9_LP_EB (1 << 16)
#define AP_APB_MAIN_M9_PU_NUM(n) (((n)&0xff) << 24)

// s0_lpc
#define AP_APB_MAIN_S0_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S0_LP_EB (1 << 16)
#define AP_APB_MAIN_S0_PU_NUM(n) (((n)&0xff) << 24)

// s1_lpc
#define AP_APB_MAIN_S1_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S1_LP_EB (1 << 16)
#define AP_APB_MAIN_S1_PU_NUM(n) (((n)&0xff) << 24)

// s2_lpc
#define AP_APB_MAIN_S2_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S2_LP_EB (1 << 16)
#define AP_APB_MAIN_S2_PU_NUM(n) (((n)&0xff) << 24)

// s3_lpc
#define AP_APB_MAIN_S3_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S3_LP_EB (1 << 16)
#define AP_APB_MAIN_S3_PU_NUM(n) (((n)&0xff) << 24)

// s4_lpc
#define AP_APB_MAIN_S4_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S4_LP_EB (1 << 16)
#define AP_APB_MAIN_S4_PU_NUM(n) (((n)&0xff) << 24)

// s5_lpc
#define AP_APB_MAIN_S5_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S5_LP_EB (1 << 16)
#define AP_APB_MAIN_S5_PU_NUM(n) (((n)&0xff) << 24)

// s6_lpc
#define AP_APB_MAIN_S6_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_S6_LP_EB (1 << 16)
#define AP_APB_MAIN_S6_PU_NUM(n) (((n)&0xff) << 24)

// main_lpc
#define AP_APB_MAIN_LP_NUM(n) (((n)&0xffff) << 0)
#define AP_APB_MAIN_LP_EB (1 << 16)
#define AP_APB_MAIN_PU_NUM(n) (((n)&0xff) << 24)

// cache_emmc_sdio
#define AP_APB_AWCACHE_EMMC(n) (((n)&0xf) << 0)
#define AP_APB_ARCACHE_EMMC(n) (((n)&0xf) << 4)

// misc_cfg
#define AP_APB_CFGSDISABLE_GIC400 (1 << 0)
#define AP_APB_MED_READ_BUS_SEL (1 << 6)
#define AP_APB_AP_IFC_HRESP_ERR_MASK (1 << 7)
#define AP_APB_CAMERA_SPICLK_POL (1 << 8)
#define AP_APB_CAMERA_REFCLK_OUT_EN (1 << 9)
#define AP_APB_CAMERA_REFCLK_OUT_MODE (1 << 10)

// chip_prod_id
#define AP_APB_METAL_ID(n) (((n)&0xfff) << 0)
#define AP_APB_BOND_ID(n) (((n)&0xf) << 12)
#define AP_APB_PROD_ID(n) (((n)&0xffff) << 16)

// cfg_qos0
#define AP_APB_AP_A5_ARQOS(n) (((n)&0xf) << 0)
#define AP_APB_AP_A5_AWQOS(n) (((n)&0xf) << 4)
#define AP_APB_CE_ARQOS(n) (((n)&0xf) << 8)
#define AP_APB_CE_AWQOS(n) (((n)&0xf) << 12)
#define AP_APB_EMMC_ARQOS(n) (((n)&0xf) << 16)
#define AP_APB_EMMC_AWQOS(n) (((n)&0xf) << 20)
#define AP_APB_LZMA_ARQOS(n) (((n)&0xf) << 24)
#define AP_APB_LZMA_AWQOS(n) (((n)&0xf) << 28)

// cfg_qos1
#define AP_APB_GOUDA_ARQOS(n) (((n)&0xf) << 0)
#define AP_APB_GOUDA_AWQOS(n) (((n)&0xf) << 4)
#define AP_APB_USB_ARQOS(n) (((n)&0xf) << 8)
#define AP_APB_USB_AWQOS(n) (((n)&0xf) << 12)
#define AP_APB_AP_IFC_ARQOS(n) (((n)&0xf) << 16)
#define AP_APB_AP_IFC_AWQOS(n) (((n)&0xf) << 20)
#define AP_APB_AON_ARQOS(n) (((n)&0xf) << 24)
#define AP_APB_AON_AWQOS(n) (((n)&0xf) << 28)

// cfg_qos2
#define AP_APB_MED_ARQOS(n) (((n)&0xf) << 0)
#define AP_APB_MED_AWQOS(n) (((n)&0xf) << 4)
#define AP_APB_AP_AXIDMA_ARQOS(n) (((n)&0xf) << 8)
#define AP_APB_AP_AXIDMA_AWQOS(n) (((n)&0xf) << 12)

// debug_monitor
#define AP_APB_MED_DBG_BUS_SEL(n) (((n)&0x1f) << 0)

// xhb_awsparse
#define AP_APB_XHB_AP_AHB_AWSPARSE (1 << 0)
#define AP_APB_XHB_SPIFLASH1_AWSPARSE (1 << 1)
#define AP_APB_XHB_SPIFLASH2_AWSPARSE (1 << 2)
#define AP_APB_XHB_AP2AON_AWSPARSE (1 << 3)

// clk_mnt26m_th0
#define AP_APB_CLK_MNT26M_TH0(n) (((n)&0xff) << 0)

// clk_mnt26m_th1
#define AP_APB_CLK_MNT26M_TH1(n) (((n)&0xffff) << 0)

// clk_mnt26m_th2
#define AP_APB_CLK_MNT26M_TH2(n) (((n)&0x7f) << 0)

// clk_mnt26m_th3
#define AP_APB_CLK_MNT26M_TH3(n) (((n)&0x1ff) << 0)

// clk_mnt32k_th0
#define AP_APB_CLK_MNT32K_TH0(n) (((n)&0xfff) << 0)

// clk_mnt32k_th1
#define AP_APB_CLK_MNT32K_TH1(n) (((n)&0xfff) << 0)

// clk_mnt_ctrl
#define AP_APB_CLK_MNT32K_EN (1 << 0)
#define AP_APB_CLK_MNT26M_EN (1 << 1)
#define AP_APB_EN_INT_CLK_MNT32K (1 << 2)
#define AP_APB_EN_INT_CLK_MNT26M (1 << 3)
#define AP_APB_ST_CLK_MNT32K (1 << 4)
#define AP_APB_ST_CLK_MNT26M (1 << 5)

// cfg_bridge
#define AP_APB_AON2AP_H2X_ASYNC_MCLK_AUTO_GATE_EN (1 << 0)
#define AP_APB_AON2AP_H2X_ASYNC_SCLK_AUTO_GATE_EN (1 << 1)
#define AP_APB_AON2AP_H2X_ASYNC_NONBUF_EARLY_RESP_EN (1 << 2)
#define AP_APB_AON2AP_H2X_ASYNC_FIFO_CLR (1 << 3)
#define AP_APB_AON2AP_H2X_ASYNC_FIFO_CLR_END (1 << 4)
#define AP_APB_USB_H2H_ASYNC_MCLK_AUTO_GATE_EN (1 << 5)
#define AP_APB_USB_H2H_ASYNC_SCLK_AUTO_GATE_EN (1 << 6)
#define AP_APB_USB_H2H_ASYNC_NONBUF_EARLY_RESP_EN (1 << 7)
#define AP_APB_USB_H2H_ASYNC_FIFO_CLR (1 << 8)
#define AP_APB_USB_H2H_ASYNC_FIFO_CLR_END (1 << 9)
#define AP_APB_GOUDA_H2X_SYNC_CLK_AUTO_GATE_EN (1 << 10)
#define AP_APB_GOUDA_H2X_SYNC_NONBUF_EARLY_RESP_EN (1 << 11)
#define AP_APB_AP_IFC_H2X_SYNC_CLK_AUTO_GATE_EN (1 << 12)
#define AP_APB_AP_IFC_H2X_SYNC_NONBUF_EARLY_RESP_EN (1 << 13)
#define AP_APB_MED_H2X_SYNC_CLK_AUTO_GATE_EN (1 << 14)
#define AP_APB_MED_H2X_SYNC_NONBUF_EARLY_RESP_EN (1 << 15)
#define AP_APB_CE2EFS_P2P_ASYNC_MCLK_AUTO_GATE_EN (1 << 16)
#define AP_APB_CE2EFS_P2P_ASYNC_SCLK_AUTO_GATE_EN (1 << 17)
#define AP_APB_CE2EFS_P2P_ASYNC_FIFO_CLR (1 << 18)
#define AP_APB_CE2EFS_P2P_ASYNC_FIFO_CLR_END (1 << 19)
#define AP_APB_I2C1_P2P_ASYNC_MCLK_AUTO_GATE_EN (1 << 20)
#define AP_APB_I2C1_P2P_ASYNC_SCLK_AUTO_GATE_EN (1 << 21)
#define AP_APB_I2C1_P2P_ASYNC_FIFO_CLR (1 << 22)
#define AP_APB_I2C1_P2P_ASYNC_FIFO_CLR_END (1 << 23)
#define AP_APB_I2C2_P2P_ASYNC_MCLK_AUTO_GATE_EN (1 << 24)
#define AP_APB_I2C2_P2P_ASYNC_SCLK_AUTO_GATE_EN (1 << 25)
#define AP_APB_I2C2_P2P_ASYNC_FIFO_CLR (1 << 26)
#define AP_APB_I2C2_P2P_ASYNC_FIFO_CLR_END (1 << 27)
#define AP_APB_GPT3_P2P_ASYNC_MCLK_AUTO_GATE_EN (1 << 28)
#define AP_APB_GPT3_P2P_ASYNC_SCLK_AUTO_GATE_EN (1 << 29)
#define AP_APB_GPT3_P2P_ASYNC_FIFO_CLR (1 << 30)
#define AP_APB_GPT3_P2P_ASYNC_FIFO_CLR_END (1 << 31)

// cfg_clk_uart4
#define AP_APB_UART4_DIV_DENOM(n) (((n)&0x1ffff) << 0)
#define AP_APB_UART4_DIV_NUM(n) (((n)&0x1fff) << 17)

// cfg_clk_uart5
#define AP_APB_UART5_DIV_DENOM(n) (((n)&0x1ffff) << 0)
#define AP_APB_UART5_DIV_NUM(n) (((n)&0x1fff) << 17)

// cfg_clk_uart6
#define AP_APB_UART6_DIV_DENOM(n) (((n)&0x1ffff) << 0)
#define AP_APB_UART6_DIV_NUM(n) (((n)&0x1fff) << 17)

// cfg_clk_spiflash1
#define AP_APB_SPIFLASH1_FREQ(n) (((n)&0xf) << 0)

// cfg_clk_spiflash2
#define AP_APB_SPIFLASH2_FREQ(n) (((n)&0xf) << 0)

// cfg_clk_apcpu_dbgen
#define AP_APB_DIV_NUM(n) (((n)&0x7) << 0)
#define AP_APB_DIV_DISABLE (1 << 3)

// lp_force
#define AP_APB_LP_FORCE_M0 (1 << 0)
#define AP_APB_LP_FORCE_M1 (1 << 1)
#define AP_APB_LP_FORCE_M2 (1 << 2)
#define AP_APB_LP_FORCE_M3 (1 << 3)
#define AP_APB_LP_FORCE_M4 (1 << 4)
#define AP_APB_LP_FORCE_M5 (1 << 5)
#define AP_APB_LP_FORCE_M6 (1 << 6)
#define AP_APB_LP_FORCE_M7 (1 << 7)
#define AP_APB_LP_FORCE_M8 (1 << 8)
#define AP_APB_LP_FORCE_M9 (1 << 9)
#define AP_APB_LP_FORCE_S0 (1 << 10)
#define AP_APB_LP_FORCE_S1 (1 << 11)
#define AP_APB_LP_FORCE_S2 (1 << 12)
#define AP_APB_LP_FORCE_S3 (1 << 13)
#define AP_APB_LP_FORCE_S4 (1 << 14)
#define AP_APB_LP_FORCE_S5 (1 << 15)
#define AP_APB_LP_FORCE_S6 (1 << 16)
#define AP_APB_LP_FORCE_MAIN (1 << 17)

// sleep_ctrl
#define AP_APB_DEEP_SLEEP_CORE_INT_DISABLE (1 << 0)
#define AP_APB_LIGHT_SLEEP_ENABLE (1 << 1)
#define AP_APB_AP_A5_CLK_AUTO_GATE (1 << 2)
#define AP_APB_LIGHT_SLEEP_RC26M_SEL (1 << 3)
#define AP_APB_DEEP_SLEEP_CORE_BYPASS (1 << 4)
#define AP_APB_LP_FORCE_ACK_M0 (1 << 5)
#define AP_APB_LP_FORCE_ACK_M1 (1 << 6)
#define AP_APB_LP_FORCE_ACK_M2 (1 << 7)
#define AP_APB_LP_FORCE_ACK_M3 (1 << 8)
#define AP_APB_LP_FORCE_ACK_M4 (1 << 9)
#define AP_APB_LP_FORCE_ACK_M5 (1 << 10)
#define AP_APB_LP_FORCE_ACK_M6 (1 << 11)
#define AP_APB_LP_FORCE_ACK_M7 (1 << 12)
#define AP_APB_LP_FORCE_ACK_M8 (1 << 13)
#define AP_APB_LP_FORCE_ACK_M9 (1 << 14)
#define AP_APB_LP_FORCE_ACK_S0 (1 << 15)
#define AP_APB_LP_FORCE_ACK_S1 (1 << 16)
#define AP_APB_LP_FORCE_ACK_S2 (1 << 17)
#define AP_APB_LP_FORCE_ACK_S3 (1 << 18)
#define AP_APB_LP_FORCE_ACK_S4 (1 << 19)
#define AP_APB_LP_FORCE_ACK_S5 (1 << 20)
#define AP_APB_LP_FORCE_ACK_S6 (1 << 21)
#define AP_APB_LP_FORCE_ACK_MAIN (1 << 22)

// light_sleep_bypass0
#define AP_APB_LIGHT_BYPASS_M0_LPC (1 << 0)
#define AP_APB_LIGHT_BYPASS_M1_LPC (1 << 1)
#define AP_APB_LIGHT_BYPASS_M2_LPC (1 << 2)
#define AP_APB_LIGHT_BYPASS_M3_LPC (1 << 3)
#define AP_APB_LIGHT_BYPASS_M4_LPC (1 << 4)
#define AP_APB_LIGHT_BYPASS_M5_LPC (1 << 5)
#define AP_APB_LIGHT_BYPASS_M6_LPC (1 << 6)
#define AP_APB_LIGHT_BYPASS_M7_LPC (1 << 7)
#define AP_APB_LIGHT_BYPASS_M8_LPC (1 << 8)
#define AP_APB_LIGHT_BYPASS_M9_LPC (1 << 9)
#define AP_APB_LIGHT_BYPASS_S0_LPC (1 << 10)
#define AP_APB_LIGHT_BYPASS_S1_LPC (1 << 11)
#define AP_APB_LIGHT_BYPASS_S2_LPC (1 << 12)
#define AP_APB_LIGHT_BYPASS_S3_LPC (1 << 13)
#define AP_APB_LIGHT_BYPASS_S4_LPC (1 << 14)
#define AP_APB_LIGHT_BYPASS_S5_LPC (1 << 15)
#define AP_APB_LIGHT_BYPASS_S6_LPC (1 << 16)
#define AP_APB_LIGHT_BYPASS_MAIN_LPC (1 << 17)
#define AP_APB_LIGHT_BYPASS_M0 (1 << 18)
#define AP_APB_LIGHT_BYPASS_M1 (1 << 19)
#define AP_APB_LIGHT_BYPASS_M2 (1 << 20)
#define AP_APB_LIGHT_BYPASS_M3 (1 << 21)
#define AP_APB_LIGHT_BYPASS_M4 (1 << 22)
#define AP_APB_LIGHT_BYPASS_M5 (1 << 23)
#define AP_APB_LIGHT_BYPASS_M6 (1 << 24)
#define AP_APB_LIGHT_BYPASS_M7 (1 << 25)
#define AP_APB_LIGHT_BYPASS_M8 (1 << 26)
#define AP_APB_LIGHT_BYPASS_M9 (1 << 27)

// light_sleep_bypass1
#define AP_APB_LIGHT_BYPASS_UART4 (1 << 0)
#define AP_APB_LIGHT_BYPASS_UART5 (1 << 1)
#define AP_APB_LIGHT_BYPASS_UART6 (1 << 2)
#define AP_APB_LIGHT_BYPASS_SDMMC (1 << 3)
#define AP_APB_LIGHT_BYPASS_CAMERA (1 << 4)
#define AP_APB_LIGHT_BYPASS_I2C1 (1 << 5)
#define AP_APB_LIGHT_BYPASS_I2C2 (1 << 6)
#define AP_APB_LIGHT_BYPASS_GPT3 (1 << 7)
#define AP_APB_LIGHT_BYPASS_SPI1 (1 << 8)
#define AP_APB_LIGHT_BYPASS_MED (1 << 9)
#define AP_APB_LIGHT_BYPASS_TIMER1 (1 << 10)
#define AP_APB_LIGHT_BYPASS_TIMER2 (1 << 11)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH0 (1 << 12)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH1 (1 << 13)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH2 (1 << 14)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH3 (1 << 15)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH4 (1 << 16)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH5 (1 << 17)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH6 (1 << 18)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH7 (1 << 19)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH8 (1 << 20)
#define AP_APB_LIGHT_BYPASS_AP_IFC_CH9 (1 << 21)
#define AP_APB_LIGHT_BYPASS_USB_DMA (1 << 22)

// anti_hang
#define AP_APB_AP2PUB_DOWNSTREAM_DISABLE_SEL (1 << 0)
#define AP_APB_AP2PUB_DOWNSTREAM_DISABLE_FORCE (1 << 1)
#define AP_APB_AHB_SLAVE_ERR_RESP_EN (1 << 2)
#define AP_APB_APB1_SLAVE_ERR_RESP_EN (1 << 3)
#define AP_APB_APB2_SLAVE_ERR_RESP_EN (1 << 4)
#define AP_APB_APB3_SLAVE_ERR_RESP_EN (1 << 5)
#define AP_APB_AP_A5_ERR_RESP_EN (1 << 6)

// ap2pub_bridge_status
#define AP_APB_AP2PUB_AXI_DETECTOR_OVERFLOW (1 << 0)
#define AP_APB_AP2PUB_PWR_HANDSHK_CLK_REQ (1 << 1)
#define AP_APB_AP2PUB_BRIDGE_TRANS_IDLE (1 << 2)

#endif // _AP_APB_H_
