/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _REG_FW_AP_APB_H_
#define _REG_FW_AP_APB_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_REG_FW_AP_APB_BASE (0x5132a000)

typedef volatile struct
{
    uint32_t reg_rd_ctrl_0;         // 0x00000000
    uint32_t reg_rd_ctrl_1;         // 0x00000004
    uint32_t reg_rd_ctrl_2;         // 0x00000008
    uint32_t reg_wr_ctrl_0;         // 0x0000000c
    uint32_t reg_wr_ctrl_1;         // 0x00000010
    uint32_t reg_wr_ctrl_2;         // 0x00000014
    uint32_t bit_ctrl_addr_array0;  // 0x00000018
    uint32_t bit_ctrl_addr_array1;  // 0x0000001c
    uint32_t bit_ctrl_addr_array2;  // 0x00000020
    uint32_t bit_ctrl_addr_array3;  // 0x00000024
    uint32_t bit_ctrl_addr_array4;  // 0x00000028
    uint32_t bit_ctrl_addr_array5;  // 0x0000002c
    uint32_t bit_ctrl_addr_array6;  // 0x00000030
    uint32_t bit_ctrl_addr_array7;  // 0x00000034
    uint32_t bit_ctrl_addr_array8;  // 0x00000038
    uint32_t bit_ctrl_addr_array9;  // 0x0000003c
    uint32_t bit_ctrl_addr_array10; // 0x00000040
    uint32_t bit_ctrl_addr_array11; // 0x00000044
    uint32_t bit_ctrl_addr_array12; // 0x00000048
    uint32_t bit_ctrl_addr_array13; // 0x0000004c
    uint32_t bit_ctrl_addr_array14; // 0x00000050
    uint32_t bit_ctrl_addr_array15; // 0x00000054
    uint32_t bit_ctrl_array0;       // 0x00000058
    uint32_t bit_ctrl_array1;       // 0x0000005c
    uint32_t bit_ctrl_array2;       // 0x00000060
    uint32_t bit_ctrl_array3;       // 0x00000064
    uint32_t bit_ctrl_array4;       // 0x00000068
    uint32_t bit_ctrl_array5;       // 0x0000006c
    uint32_t bit_ctrl_array6;       // 0x00000070
    uint32_t bit_ctrl_array7;       // 0x00000074
    uint32_t bit_ctrl_array8;       // 0x00000078
    uint32_t bit_ctrl_array9;       // 0x0000007c
    uint32_t bit_ctrl_array10;      // 0x00000080
    uint32_t bit_ctrl_array11;      // 0x00000084
    uint32_t bit_ctrl_array12;      // 0x00000088
    uint32_t bit_ctrl_array13;      // 0x0000008c
    uint32_t bit_ctrl_array14;      // 0x00000090
    uint32_t bit_ctrl_array15;      // 0x00000094
} HWP_REG_FW_AP_APB_T;

#define hwp_regFwApApb ((HWP_REG_FW_AP_APB_T *)REG_ACCESS_ADDRESS(REG_REG_FW_AP_APB_BASE))

// reg_rd_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_ap_mode0_rd_sec : 1;    // [0]
        uint32_t clk_ap_en0_rd_sec : 1;      // [1]
        uint32_t clk_ap_mode1_rd_sec : 1;    // [2]
        uint32_t clk_ap_en1_rd_sec : 1;      // [3]
        uint32_t clk_ap_mode2_rd_sec : 1;    // [4]
        uint32_t clk_ap_en2_rd_sec : 1;      // [5]
        uint32_t ap_rst0_rd_sec : 1;         // [6]
        uint32_t ap_rst1_rd_sec : 1;         // [7]
        uint32_t ap_rst2_rd_sec : 1;         // [8]
        uint32_t m0_lpc_rd_sec : 1;          // [9]
        uint32_t m1_lpc_rd_sec : 1;          // [10]
        uint32_t m2_lpc_rd_sec : 1;          // [11]
        uint32_t m3_lpc_rd_sec : 1;          // [12]
        uint32_t m4_lpc_rd_sec : 1;          // [13]
        uint32_t m5_lpc_rd_sec : 1;          // [14]
        uint32_t m6_lpc_rd_sec : 1;          // [15]
        uint32_t m7_lpc_rd_sec : 1;          // [16]
        uint32_t m8_lpc_rd_sec : 1;          // [17]
        uint32_t m9_lpc_rd_sec : 1;          // [18]
        uint32_t s0_lpc_rd_sec : 1;          // [19]
        uint32_t s1_lpc_rd_sec : 1;          // [20]
        uint32_t s2_lpc_rd_sec : 1;          // [21]
        uint32_t s3_lpc_rd_sec : 1;          // [22]
        uint32_t s4_lpc_rd_sec : 1;          // [23]
        uint32_t s5_lpc_rd_sec : 1;          // [24]
        uint32_t s6_lpc_rd_sec : 1;          // [25]
        uint32_t main_lpc_rd_sec : 1;        // [26]
        uint32_t cache_emmc_sdio_rd_sec : 1; // [27]
        uint32_t misc_cfg_rd_sec : 1;        // [28]
        uint32_t chip_prod_id_rd_sec : 1;    // [29]
        uint32_t cfg_qos0_rd_sec : 1;        // [30]
        uint32_t cfg_qos1_rd_sec : 1;        // [31]
    } b;
} REG_REG_FW_AP_APB_REG_RD_CTRL_0_T;

// reg_rd_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfg_qos2_rd_sec : 1;             // [0]
        uint32_t debug_monitor_rd_sec : 1;        // [1]
        uint32_t xhb_awsparse_rd_sec : 1;         // [2]
        uint32_t clk_mnt26m_th0_rd_sec : 1;       // [3]
        uint32_t clk_mnt26m_th1_rd_sec : 1;       // [4]
        uint32_t clk_mnt26m_th2_rd_sec : 1;       // [5]
        uint32_t clk_mnt26m_th3_rd_sec : 1;       // [6]
        uint32_t clk_mnt32k_th0_rd_sec : 1;       // [7]
        uint32_t clk_mnt32k_th1_rd_sec : 1;       // [8]
        uint32_t clk_mnt_ctrl_rd_sec : 1;         // [9]
        uint32_t cfg_bridge_rd_sec : 1;           // [10]
        uint32_t cgm_gate_auto_sel0_rd_sec : 1;   // [11]
        uint32_t cgm_gate_auto_sel1_rd_sec : 1;   // [12]
        uint32_t cgm_gate_auto_sel2_rd_sec : 1;   // [13]
        uint32_t cgm_gate_auto_sel3_rd_sec : 1;   // [14]
        uint32_t cgm_gate_force_en0_rd_sec : 1;   // [15]
        uint32_t cgm_gate_force_en1_rd_sec : 1;   // [16]
        uint32_t cgm_gate_force_en2_rd_sec : 1;   // [17]
        uint32_t cgm_gate_force_en3_rd_sec : 1;   // [18]
        uint32_t mnt_gate_en_status0_rd_sec : 1;  // [19]
        uint32_t mnt_gate_en_status1_rd_sec : 1;  // [20]
        uint32_t mnt_gate_en_status2_rd_sec : 1;  // [21]
        uint32_t mnt_gate_en_status3_rd_sec : 1;  // [22]
        uint32_t mnt_cgm_busy_status0_rd_sec : 1; // [23]
        uint32_t mnt_cgm_busy_status1_rd_sec : 1; // [24]
        uint32_t mnt_cgm_busy_status2_rd_sec : 1; // [25]
        uint32_t mnt_cgm_busy_status3_rd_sec : 1; // [26]
        uint32_t mnt_cgm_busy_status4_rd_sec : 1; // [27]
        uint32_t cfg_clk_uart4_rd_sec : 1;        // [28]
        uint32_t cfg_clk_uart5_rd_sec : 1;        // [29]
        uint32_t cfg_clk_uart6_rd_sec : 1;        // [30]
        uint32_t cfg_clk_spiflash1_rd_sec : 1;    // [31]
    } b;
} REG_REG_FW_AP_APB_REG_RD_CTRL_1_T;

// reg_rd_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfg_clk_spiflash2_rd_sec : 1;    // [0]
        uint32_t cfg_clk_apcpu_dbgen_rd_sec : 1;  // [1]
        uint32_t lp_force_rd_sec : 1;             // [2]
        uint32_t sleep_ctrl_rd_sec : 1;           // [3]
        uint32_t light_sleep_bypass0_rd_sec : 1;  // [4]
        uint32_t light_sleep_bypass1_rd_sec : 1;  // [5]
        uint32_t anti_hang_rd_sec : 1;            // [6]
        uint32_t ap_apb_rsd0_rd_sec : 1;          // [7]
        uint32_t ap_apb_rsd1_rd_sec : 1;          // [8]
        uint32_t ap_apb_rsd2_rd_sec : 1;          // [9]
        uint32_t ap_apb_rsd3_rd_sec : 1;          // [10]
        uint32_t ap2pub_bridge_status_rd_sec : 1; // [11]
        uint32_t ap2pub_bridge_debug_rd_sec : 1;  // [12]
        uint32_t __31_13 : 19;                    // [31:13]
    } b;
} REG_REG_FW_AP_APB_REG_RD_CTRL_2_T;

// reg_wr_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_ap_mode0_wr_sec : 1;    // [0]
        uint32_t clk_ap_en0_wr_sec : 1;      // [1]
        uint32_t clk_ap_mode1_wr_sec : 1;    // [2]
        uint32_t clk_ap_en1_wr_sec : 1;      // [3]
        uint32_t clk_ap_mode2_wr_sec : 1;    // [4]
        uint32_t clk_ap_en2_wr_sec : 1;      // [5]
        uint32_t ap_rst0_wr_sec : 1;         // [6]
        uint32_t ap_rst1_wr_sec : 1;         // [7]
        uint32_t ap_rst2_wr_sec : 1;         // [8]
        uint32_t m0_lpc_wr_sec : 1;          // [9]
        uint32_t m1_lpc_wr_sec : 1;          // [10]
        uint32_t m2_lpc_wr_sec : 1;          // [11]
        uint32_t m3_lpc_wr_sec : 1;          // [12]
        uint32_t m4_lpc_wr_sec : 1;          // [13]
        uint32_t m5_lpc_wr_sec : 1;          // [14]
        uint32_t m6_lpc_wr_sec : 1;          // [15]
        uint32_t m7_lpc_wr_sec : 1;          // [16]
        uint32_t m8_lpc_wr_sec : 1;          // [17]
        uint32_t m9_lpc_wr_sec : 1;          // [18]
        uint32_t s0_lpc_wr_sec : 1;          // [19]
        uint32_t s1_lpc_wr_sec : 1;          // [20]
        uint32_t s2_lpc_wr_sec : 1;          // [21]
        uint32_t s3_lpc_wr_sec : 1;          // [22]
        uint32_t s4_lpc_wr_sec : 1;          // [23]
        uint32_t s5_lpc_wr_sec : 1;          // [24]
        uint32_t s6_lpc_wr_sec : 1;          // [25]
        uint32_t main_lpc_wr_sec : 1;        // [26]
        uint32_t cache_emmc_sdio_wr_sec : 1; // [27]
        uint32_t misc_cfg_wr_sec : 1;        // [28]
        uint32_t chip_prod_id_wr_sec : 1;    // [29]
        uint32_t cfg_qos0_wr_sec : 1;        // [30]
        uint32_t cfg_qos1_wr_sec : 1;        // [31]
    } b;
} REG_REG_FW_AP_APB_REG_WR_CTRL_0_T;

// reg_wr_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfg_qos2_wr_sec : 1;             // [0]
        uint32_t debug_monitor_wr_sec : 1;        // [1]
        uint32_t xhb_awsparse_wr_sec : 1;         // [2]
        uint32_t clk_mnt26m_th0_wr_sec : 1;       // [3]
        uint32_t clk_mnt26m_th1_wr_sec : 1;       // [4]
        uint32_t clk_mnt26m_th2_wr_sec : 1;       // [5]
        uint32_t clk_mnt26m_th3_wr_sec : 1;       // [6]
        uint32_t clk_mnt32k_th0_wr_sec : 1;       // [7]
        uint32_t clk_mnt32k_th1_wr_sec : 1;       // [8]
        uint32_t clk_mnt_ctrl_wr_sec : 1;         // [9]
        uint32_t cfg_bridge_wr_sec : 1;           // [10]
        uint32_t cgm_gate_auto_sel0_wr_sec : 1;   // [11]
        uint32_t cgm_gate_auto_sel1_wr_sec : 1;   // [12]
        uint32_t cgm_gate_auto_sel2_wr_sec : 1;   // [13]
        uint32_t cgm_gate_auto_sel3_wr_sec : 1;   // [14]
        uint32_t cgm_gate_force_en0_wr_sec : 1;   // [15]
        uint32_t cgm_gate_force_en1_wr_sec : 1;   // [16]
        uint32_t cgm_gate_force_en2_wr_sec : 1;   // [17]
        uint32_t cgm_gate_force_en3_wr_sec : 1;   // [18]
        uint32_t mnt_gate_en_status0_wr_sec : 1;  // [19]
        uint32_t mnt_gate_en_status1_wr_sec : 1;  // [20]
        uint32_t mnt_gate_en_status2_wr_sec : 1;  // [21]
        uint32_t mnt_gate_en_status3_wr_sec : 1;  // [22]
        uint32_t mnt_cgm_busy_status0_wr_sec : 1; // [23]
        uint32_t mnt_cgm_busy_status1_wr_sec : 1; // [24]
        uint32_t mnt_cgm_busy_status2_wr_sec : 1; // [25]
        uint32_t mnt_cgm_busy_status3_wr_sec : 1; // [26]
        uint32_t mnt_cgm_busy_status4_wr_sec : 1; // [27]
        uint32_t cfg_clk_uart4_wr_sec : 1;        // [28]
        uint32_t cfg_clk_uart5_wr_sec : 1;        // [29]
        uint32_t cfg_clk_uart6_wr_sec : 1;        // [30]
        uint32_t cfg_clk_spiflash1_wr_sec : 1;    // [31]
    } b;
} REG_REG_FW_AP_APB_REG_WR_CTRL_1_T;

// reg_wr_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cfg_clk_spiflash2_wr_sec : 1;    // [0]
        uint32_t cfg_clk_apcpu_dbgen_wr_sec : 1;  // [1]
        uint32_t lp_force_wr_sec : 1;             // [2]
        uint32_t sleep_ctrl_wr_sec : 1;           // [3]
        uint32_t light_sleep_bypass0_wr_sec : 1;  // [4]
        uint32_t light_sleep_bypass1_wr_sec : 1;  // [5]
        uint32_t anti_hang_wr_sec : 1;            // [6]
        uint32_t ap_apb_rsd0_wr_sec : 1;          // [7]
        uint32_t ap_apb_rsd1_wr_sec : 1;          // [8]
        uint32_t ap_apb_rsd2_wr_sec : 1;          // [9]
        uint32_t ap_apb_rsd3_wr_sec : 1;          // [10]
        uint32_t ap2pub_bridge_status_wr_sec : 1; // [11]
        uint32_t ap2pub_bridge_debug_wr_sec : 1;  // [12]
        uint32_t __31_13 : 19;                    // [31:13]
    } b;
} REG_REG_FW_AP_APB_REG_WR_CTRL_2_T;

// bit_ctrl_addr_array0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array0 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY0_T;

// bit_ctrl_addr_array1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array1 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY1_T;

// bit_ctrl_addr_array2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array2 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY2_T;

// bit_ctrl_addr_array3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array3 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY3_T;

// bit_ctrl_addr_array4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array4 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY4_T;

// bit_ctrl_addr_array5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array5 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY5_T;

// bit_ctrl_addr_array6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array6 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY6_T;

// bit_ctrl_addr_array7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array7 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY7_T;

// bit_ctrl_addr_array8
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array8 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY8_T;

// bit_ctrl_addr_array9
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array9 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY9_T;

// bit_ctrl_addr_array10
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array10 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY10_T;

// bit_ctrl_addr_array11
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array11 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY11_T;

// bit_ctrl_addr_array12
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array12 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY12_T;

// bit_ctrl_addr_array13
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array13 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY13_T;

// bit_ctrl_addr_array14
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array14 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY14_T;

// bit_ctrl_addr_array15
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array15 : 12; // [11:0]
        uint32_t __31_12 : 20;               // [31:12]
    } b;
} REG_REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY15_T;

// reg_rd_ctrl_0
#define REG_FW_AP_APB_CLK_AP_MODE0_RD_SEC (1 << 0)
#define REG_FW_AP_APB_CLK_AP_EN0_RD_SEC (1 << 1)
#define REG_FW_AP_APB_CLK_AP_MODE1_RD_SEC (1 << 2)
#define REG_FW_AP_APB_CLK_AP_EN1_RD_SEC (1 << 3)
#define REG_FW_AP_APB_CLK_AP_MODE2_RD_SEC (1 << 4)
#define REG_FW_AP_APB_CLK_AP_EN2_RD_SEC (1 << 5)
#define REG_FW_AP_APB_AP_RST0_RD_SEC (1 << 6)
#define REG_FW_AP_APB_AP_RST1_RD_SEC (1 << 7)
#define REG_FW_AP_APB_AP_RST2_RD_SEC (1 << 8)
#define REG_FW_AP_APB_M0_LPC_RD_SEC (1 << 9)
#define REG_FW_AP_APB_M1_LPC_RD_SEC (1 << 10)
#define REG_FW_AP_APB_M2_LPC_RD_SEC (1 << 11)
#define REG_FW_AP_APB_M3_LPC_RD_SEC (1 << 12)
#define REG_FW_AP_APB_M4_LPC_RD_SEC (1 << 13)
#define REG_FW_AP_APB_M5_LPC_RD_SEC (1 << 14)
#define REG_FW_AP_APB_M6_LPC_RD_SEC (1 << 15)
#define REG_FW_AP_APB_M7_LPC_RD_SEC (1 << 16)
#define REG_FW_AP_APB_M8_LPC_RD_SEC (1 << 17)
#define REG_FW_AP_APB_M9_LPC_RD_SEC (1 << 18)
#define REG_FW_AP_APB_S0_LPC_RD_SEC (1 << 19)
#define REG_FW_AP_APB_S1_LPC_RD_SEC (1 << 20)
#define REG_FW_AP_APB_S2_LPC_RD_SEC (1 << 21)
#define REG_FW_AP_APB_S3_LPC_RD_SEC (1 << 22)
#define REG_FW_AP_APB_S4_LPC_RD_SEC (1 << 23)
#define REG_FW_AP_APB_S5_LPC_RD_SEC (1 << 24)
#define REG_FW_AP_APB_S6_LPC_RD_SEC (1 << 25)
#define REG_FW_AP_APB_MAIN_LPC_RD_SEC (1 << 26)
#define REG_FW_AP_APB_CACHE_EMMC_SDIO_RD_SEC (1 << 27)
#define REG_FW_AP_APB_MISC_CFG_RD_SEC (1 << 28)
#define REG_FW_AP_APB_CHIP_PROD_ID_RD_SEC (1 << 29)
#define REG_FW_AP_APB_CFG_QOS0_RD_SEC (1 << 30)
#define REG_FW_AP_APB_CFG_QOS1_RD_SEC (1 << 31)

// reg_rd_ctrl_1
#define REG_FW_AP_APB_CFG_QOS2_RD_SEC (1 << 0)
#define REG_FW_AP_APB_DEBUG_MONITOR_RD_SEC (1 << 1)
#define REG_FW_AP_APB_XHB_AWSPARSE_RD_SEC (1 << 2)
#define REG_FW_AP_APB_CLK_MNT26M_TH0_RD_SEC (1 << 3)
#define REG_FW_AP_APB_CLK_MNT26M_TH1_RD_SEC (1 << 4)
#define REG_FW_AP_APB_CLK_MNT26M_TH2_RD_SEC (1 << 5)
#define REG_FW_AP_APB_CLK_MNT26M_TH3_RD_SEC (1 << 6)
#define REG_FW_AP_APB_CLK_MNT32K_TH0_RD_SEC (1 << 7)
#define REG_FW_AP_APB_CLK_MNT32K_TH1_RD_SEC (1 << 8)
#define REG_FW_AP_APB_CLK_MNT_CTRL_RD_SEC (1 << 9)
#define REG_FW_AP_APB_CFG_BRIDGE_RD_SEC (1 << 10)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL0_RD_SEC (1 << 11)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL1_RD_SEC (1 << 12)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL2_RD_SEC (1 << 13)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL3_RD_SEC (1 << 14)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN0_RD_SEC (1 << 15)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN1_RD_SEC (1 << 16)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN2_RD_SEC (1 << 17)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN3_RD_SEC (1 << 18)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS0_RD_SEC (1 << 19)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS1_RD_SEC (1 << 20)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS2_RD_SEC (1 << 21)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS3_RD_SEC (1 << 22)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS0_RD_SEC (1 << 23)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS1_RD_SEC (1 << 24)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS2_RD_SEC (1 << 25)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS3_RD_SEC (1 << 26)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS4_RD_SEC (1 << 27)
#define REG_FW_AP_APB_CFG_CLK_UART4_RD_SEC (1 << 28)
#define REG_FW_AP_APB_CFG_CLK_UART5_RD_SEC (1 << 29)
#define REG_FW_AP_APB_CFG_CLK_UART6_RD_SEC (1 << 30)
#define REG_FW_AP_APB_CFG_CLK_SPIFLASH1_RD_SEC (1 << 31)

// reg_rd_ctrl_2
#define REG_FW_AP_APB_CFG_CLK_SPIFLASH2_RD_SEC (1 << 0)
#define REG_FW_AP_APB_CFG_CLK_APCPU_DBGEN_RD_SEC (1 << 1)
#define REG_FW_AP_APB_LP_FORCE_RD_SEC (1 << 2)
#define REG_FW_AP_APB_SLEEP_CTRL_RD_SEC (1 << 3)
#define REG_FW_AP_APB_LIGHT_SLEEP_BYPASS0_RD_SEC (1 << 4)
#define REG_FW_AP_APB_LIGHT_SLEEP_BYPASS1_RD_SEC (1 << 5)
#define REG_FW_AP_APB_ANTI_HANG_RD_SEC (1 << 6)
#define REG_FW_AP_APB_AP_APB_RSD0_RD_SEC (1 << 7)
#define REG_FW_AP_APB_AP_APB_RSD1_RD_SEC (1 << 8)
#define REG_FW_AP_APB_AP_APB_RSD2_RD_SEC (1 << 9)
#define REG_FW_AP_APB_AP_APB_RSD3_RD_SEC (1 << 10)
#define REG_FW_AP_APB_AP2PUB_BRIDGE_STATUS_RD_SEC (1 << 11)
#define REG_FW_AP_APB_AP2PUB_BRIDGE_DEBUG_RD_SEC (1 << 12)

// reg_wr_ctrl_0
#define REG_FW_AP_APB_CLK_AP_MODE0_WR_SEC (1 << 0)
#define REG_FW_AP_APB_CLK_AP_EN0_WR_SEC (1 << 1)
#define REG_FW_AP_APB_CLK_AP_MODE1_WR_SEC (1 << 2)
#define REG_FW_AP_APB_CLK_AP_EN1_WR_SEC (1 << 3)
#define REG_FW_AP_APB_CLK_AP_MODE2_WR_SEC (1 << 4)
#define REG_FW_AP_APB_CLK_AP_EN2_WR_SEC (1 << 5)
#define REG_FW_AP_APB_AP_RST0_WR_SEC (1 << 6)
#define REG_FW_AP_APB_AP_RST1_WR_SEC (1 << 7)
#define REG_FW_AP_APB_AP_RST2_WR_SEC (1 << 8)
#define REG_FW_AP_APB_M0_LPC_WR_SEC (1 << 9)
#define REG_FW_AP_APB_M1_LPC_WR_SEC (1 << 10)
#define REG_FW_AP_APB_M2_LPC_WR_SEC (1 << 11)
#define REG_FW_AP_APB_M3_LPC_WR_SEC (1 << 12)
#define REG_FW_AP_APB_M4_LPC_WR_SEC (1 << 13)
#define REG_FW_AP_APB_M5_LPC_WR_SEC (1 << 14)
#define REG_FW_AP_APB_M6_LPC_WR_SEC (1 << 15)
#define REG_FW_AP_APB_M7_LPC_WR_SEC (1 << 16)
#define REG_FW_AP_APB_M8_LPC_WR_SEC (1 << 17)
#define REG_FW_AP_APB_M9_LPC_WR_SEC (1 << 18)
#define REG_FW_AP_APB_S0_LPC_WR_SEC (1 << 19)
#define REG_FW_AP_APB_S1_LPC_WR_SEC (1 << 20)
#define REG_FW_AP_APB_S2_LPC_WR_SEC (1 << 21)
#define REG_FW_AP_APB_S3_LPC_WR_SEC (1 << 22)
#define REG_FW_AP_APB_S4_LPC_WR_SEC (1 << 23)
#define REG_FW_AP_APB_S5_LPC_WR_SEC (1 << 24)
#define REG_FW_AP_APB_S6_LPC_WR_SEC (1 << 25)
#define REG_FW_AP_APB_MAIN_LPC_WR_SEC (1 << 26)
#define REG_FW_AP_APB_CACHE_EMMC_SDIO_WR_SEC (1 << 27)
#define REG_FW_AP_APB_MISC_CFG_WR_SEC (1 << 28)
#define REG_FW_AP_APB_CHIP_PROD_ID_WR_SEC (1 << 29)
#define REG_FW_AP_APB_CFG_QOS0_WR_SEC (1 << 30)
#define REG_FW_AP_APB_CFG_QOS1_WR_SEC (1 << 31)

// reg_wr_ctrl_1
#define REG_FW_AP_APB_CFG_QOS2_WR_SEC (1 << 0)
#define REG_FW_AP_APB_DEBUG_MONITOR_WR_SEC (1 << 1)
#define REG_FW_AP_APB_XHB_AWSPARSE_WR_SEC (1 << 2)
#define REG_FW_AP_APB_CLK_MNT26M_TH0_WR_SEC (1 << 3)
#define REG_FW_AP_APB_CLK_MNT26M_TH1_WR_SEC (1 << 4)
#define REG_FW_AP_APB_CLK_MNT26M_TH2_WR_SEC (1 << 5)
#define REG_FW_AP_APB_CLK_MNT26M_TH3_WR_SEC (1 << 6)
#define REG_FW_AP_APB_CLK_MNT32K_TH0_WR_SEC (1 << 7)
#define REG_FW_AP_APB_CLK_MNT32K_TH1_WR_SEC (1 << 8)
#define REG_FW_AP_APB_CLK_MNT_CTRL_WR_SEC (1 << 9)
#define REG_FW_AP_APB_CFG_BRIDGE_WR_SEC (1 << 10)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL0_WR_SEC (1 << 11)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL1_WR_SEC (1 << 12)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL2_WR_SEC (1 << 13)
#define REG_FW_AP_APB_CGM_GATE_AUTO_SEL3_WR_SEC (1 << 14)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN0_WR_SEC (1 << 15)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN1_WR_SEC (1 << 16)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN2_WR_SEC (1 << 17)
#define REG_FW_AP_APB_CGM_GATE_FORCE_EN3_WR_SEC (1 << 18)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS0_WR_SEC (1 << 19)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS1_WR_SEC (1 << 20)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS2_WR_SEC (1 << 21)
#define REG_FW_AP_APB_MNT_GATE_EN_STATUS3_WR_SEC (1 << 22)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS0_WR_SEC (1 << 23)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS1_WR_SEC (1 << 24)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS2_WR_SEC (1 << 25)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS3_WR_SEC (1 << 26)
#define REG_FW_AP_APB_MNT_CGM_BUSY_STATUS4_WR_SEC (1 << 27)
#define REG_FW_AP_APB_CFG_CLK_UART4_WR_SEC (1 << 28)
#define REG_FW_AP_APB_CFG_CLK_UART5_WR_SEC (1 << 29)
#define REG_FW_AP_APB_CFG_CLK_UART6_WR_SEC (1 << 30)
#define REG_FW_AP_APB_CFG_CLK_SPIFLASH1_WR_SEC (1 << 31)

// reg_wr_ctrl_2
#define REG_FW_AP_APB_CFG_CLK_SPIFLASH2_WR_SEC (1 << 0)
#define REG_FW_AP_APB_CFG_CLK_APCPU_DBGEN_WR_SEC (1 << 1)
#define REG_FW_AP_APB_LP_FORCE_WR_SEC (1 << 2)
#define REG_FW_AP_APB_SLEEP_CTRL_WR_SEC (1 << 3)
#define REG_FW_AP_APB_LIGHT_SLEEP_BYPASS0_WR_SEC (1 << 4)
#define REG_FW_AP_APB_LIGHT_SLEEP_BYPASS1_WR_SEC (1 << 5)
#define REG_FW_AP_APB_ANTI_HANG_WR_SEC (1 << 6)
#define REG_FW_AP_APB_AP_APB_RSD0_WR_SEC (1 << 7)
#define REG_FW_AP_APB_AP_APB_RSD1_WR_SEC (1 << 8)
#define REG_FW_AP_APB_AP_APB_RSD2_WR_SEC (1 << 9)
#define REG_FW_AP_APB_AP_APB_RSD3_WR_SEC (1 << 10)
#define REG_FW_AP_APB_AP2PUB_BRIDGE_STATUS_WR_SEC (1 << 11)
#define REG_FW_AP_APB_AP2PUB_BRIDGE_DEBUG_WR_SEC (1 << 12)

// bit_ctrl_addr_array0
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY0(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array1
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY1(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array2
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY2(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array3
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY3(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array4
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY4(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array5
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY5(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array6
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY6(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array7
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY7(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array8
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY8(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array9
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY9(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array10
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY10(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array11
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY11(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array12
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY12(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array13
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY13(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array14
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY14(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array15
#define REG_FW_AP_APB_BIT_CTRL_ADDR_ARRAY15(n) (((n)&0xfff) << 0)

#endif // _REG_FW_AP_APB_H_
