/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _REG_FW_PWRCTRL_H_
#define _REG_FW_PWRCTRL_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_REG_FW_PWRCTRL_BASE (0x51315000)

typedef volatile struct
{
    uint32_t reg_rd_ctrl_0;        // 0x00000000
    uint32_t reg_wr_ctrl_0;        // 0x00000004
    uint32_t bit_ctrl_addr_array0; // 0x00000008
    uint32_t bit_ctrl_addr_array1; // 0x0000000c
    uint32_t bit_ctrl_addr_array2; // 0x00000010
    uint32_t bit_ctrl_addr_array3; // 0x00000014
    uint32_t bit_ctrl_addr_array4; // 0x00000018
    uint32_t bit_ctrl_addr_array5; // 0x0000001c
    uint32_t bit_ctrl_addr_array6; // 0x00000020
    uint32_t bit_ctrl_addr_array7; // 0x00000024
    uint32_t bit_ctrl_array0;      // 0x00000028
    uint32_t bit_ctrl_array1;      // 0x0000002c
    uint32_t bit_ctrl_array2;      // 0x00000030
    uint32_t bit_ctrl_array3;      // 0x00000034
    uint32_t bit_ctrl_array4;      // 0x00000038
    uint32_t bit_ctrl_array5;      // 0x0000003c
    uint32_t bit_ctrl_array6;      // 0x00000040
    uint32_t bit_ctrl_array7;      // 0x00000044
} HWP_REG_FW_PWRCTRL_T;

#define hwp_regFwPwrctrl ((HWP_REG_FW_PWRCTRL_T *)REG_ACCESS_ADDRESS(REG_REG_FW_PWRCTRL_BASE))

// reg_rd_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwrctrl_hwen_rd_sec : 1;      // [0]
        uint32_t ap_pwr_ctrl_rd_sec : 1;       // [1]
        uint32_t cp_pwr_ctrl_rd_sec : 1;       // [2]
        uint32_t pub_pwr_ctrl_rd_sec : 1;      // [3]
        uint32_t rf_pwr_ctrl_rd_sec : 1;       // [4]
        uint32_t usb_pwr_ctrl_rd_sec : 1;      // [5]
        uint32_t lte_pwr_ctrl_rd_sec : 1;      // [6]
        uint32_t gnss_pwr_ctrl_rd_sec : 1;     // [7]
        uint32_t ap_pwr_stat_rd_sec : 1;       // [8]
        uint32_t cp_pwr_stat_rd_sec : 1;       // [9]
        uint32_t pub_pwr_stat_rd_sec : 1;      // [10]
        uint32_t rf_pwr_stat_rd_sec : 1;       // [11]
        uint32_t usb_pwr_stat_rd_sec : 1;      // [12]
        uint32_t lte_pwr_stat_rd_sec : 1;      // [13]
        uint32_t gnss_pwr_stat_rd_sec : 1;     // [14]
        uint32_t state_delay_rd_sec : 1;       // [15]
        uint32_t pd_m_delay_rd_sec : 1;        // [16]
        uint32_t pd_d_delay_rd_sec : 1;        // [17]
        uint32_t psram_hold_ctrl_rd_sec : 1;   // [18]
        uint32_t slp_bypass_rd_sec : 1;        // [19]
        uint32_t slp_timeout_flag_rd_sec : 1;  // [20]
        uint32_t pwrctrl_int_en_ap_rd_sec : 1; // [21]
        uint32_t pwrctrl_int_en_cp_rd_sec : 1; // [22]
        uint32_t pwrctrl_sm_state_rd_sec : 1;  // [23]
        uint32_t __31_24 : 8;                  // [31:24]
    } b;
} REG_REG_FW_PWRCTRL_REG_RD_CTRL_0_T;

// reg_wr_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pwrctrl_hwen_wr_sec : 1;      // [0]
        uint32_t ap_pwr_ctrl_wr_sec : 1;       // [1]
        uint32_t cp_pwr_ctrl_wr_sec : 1;       // [2]
        uint32_t pub_pwr_ctrl_wr_sec : 1;      // [3]
        uint32_t rf_pwr_ctrl_wr_sec : 1;       // [4]
        uint32_t usb_pwr_ctrl_wr_sec : 1;      // [5]
        uint32_t lte_pwr_ctrl_wr_sec : 1;      // [6]
        uint32_t gnss_pwr_ctrl_wr_sec : 1;     // [7]
        uint32_t ap_pwr_stat_wr_sec : 1;       // [8]
        uint32_t cp_pwr_stat_wr_sec : 1;       // [9]
        uint32_t pub_pwr_stat_wr_sec : 1;      // [10]
        uint32_t rf_pwr_stat_wr_sec : 1;       // [11]
        uint32_t usb_pwr_stat_wr_sec : 1;      // [12]
        uint32_t lte_pwr_stat_wr_sec : 1;      // [13]
        uint32_t gnss_pwr_stat_wr_sec : 1;     // [14]
        uint32_t state_delay_wr_sec : 1;       // [15]
        uint32_t pd_m_delay_wr_sec : 1;        // [16]
        uint32_t pd_d_delay_wr_sec : 1;        // [17]
        uint32_t psram_hold_ctrl_wr_sec : 1;   // [18]
        uint32_t slp_bypass_wr_sec : 1;        // [19]
        uint32_t slp_timeout_flag_wr_sec : 1;  // [20]
        uint32_t pwrctrl_int_en_ap_wr_sec : 1; // [21]
        uint32_t pwrctrl_int_en_cp_wr_sec : 1; // [22]
        uint32_t pwrctrl_sm_state_wr_sec : 1;  // [23]
        uint32_t __31_24 : 8;                  // [31:24]
    } b;
} REG_REG_FW_PWRCTRL_REG_WR_CTRL_0_T;

// bit_ctrl_addr_array0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array0 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY0_T;

// bit_ctrl_addr_array1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array1 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY1_T;

// bit_ctrl_addr_array2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array2 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY2_T;

// bit_ctrl_addr_array3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array3 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY3_T;

// bit_ctrl_addr_array4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array4 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY4_T;

// bit_ctrl_addr_array5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array5 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY5_T;

// bit_ctrl_addr_array6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array6 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY6_T;

// bit_ctrl_addr_array7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array7 : 12; // [11:0]
        uint32_t __31_12 : 20;              // [31:12]
    } b;
} REG_REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY7_T;

// reg_rd_ctrl_0
#define REG_FW_PWRCTRL_PWRCTRL_HWEN_RD_SEC (1 << 0)
#define REG_FW_PWRCTRL_AP_PWR_CTRL_RD_SEC (1 << 1)
#define REG_FW_PWRCTRL_CP_PWR_CTRL_RD_SEC (1 << 2)
#define REG_FW_PWRCTRL_PUB_PWR_CTRL_RD_SEC (1 << 3)
#define REG_FW_PWRCTRL_RF_PWR_CTRL_RD_SEC (1 << 4)
#define REG_FW_PWRCTRL_USB_PWR_CTRL_RD_SEC (1 << 5)
#define REG_FW_PWRCTRL_LTE_PWR_CTRL_RD_SEC (1 << 6)
#define REG_FW_PWRCTRL_GNSS_PWR_CTRL_RD_SEC (1 << 7)
#define REG_FW_PWRCTRL_AP_PWR_STAT_RD_SEC (1 << 8)
#define REG_FW_PWRCTRL_CP_PWR_STAT_RD_SEC (1 << 9)
#define REG_FW_PWRCTRL_PUB_PWR_STAT_RD_SEC (1 << 10)
#define REG_FW_PWRCTRL_RF_PWR_STAT_RD_SEC (1 << 11)
#define REG_FW_PWRCTRL_USB_PWR_STAT_RD_SEC (1 << 12)
#define REG_FW_PWRCTRL_LTE_PWR_STAT_RD_SEC (1 << 13)
#define REG_FW_PWRCTRL_GNSS_PWR_STAT_RD_SEC (1 << 14)
#define REG_FW_PWRCTRL_STATE_DELAY_RD_SEC (1 << 15)
#define REG_FW_PWRCTRL_PD_M_DELAY_RD_SEC (1 << 16)
#define REG_FW_PWRCTRL_PD_D_DELAY_RD_SEC (1 << 17)
#define REG_FW_PWRCTRL_PSRAM_HOLD_CTRL_RD_SEC (1 << 18)
#define REG_FW_PWRCTRL_SLP_BYPASS_RD_SEC (1 << 19)
#define REG_FW_PWRCTRL_SLP_TIMEOUT_FLAG_RD_SEC (1 << 20)
#define REG_FW_PWRCTRL_PWRCTRL_INT_EN_AP_RD_SEC (1 << 21)
#define REG_FW_PWRCTRL_PWRCTRL_INT_EN_CP_RD_SEC (1 << 22)
#define REG_FW_PWRCTRL_PWRCTRL_SM_STATE_RD_SEC (1 << 23)

// reg_wr_ctrl_0
#define REG_FW_PWRCTRL_PWRCTRL_HWEN_WR_SEC (1 << 0)
#define REG_FW_PWRCTRL_AP_PWR_CTRL_WR_SEC (1 << 1)
#define REG_FW_PWRCTRL_CP_PWR_CTRL_WR_SEC (1 << 2)
#define REG_FW_PWRCTRL_PUB_PWR_CTRL_WR_SEC (1 << 3)
#define REG_FW_PWRCTRL_RF_PWR_CTRL_WR_SEC (1 << 4)
#define REG_FW_PWRCTRL_USB_PWR_CTRL_WR_SEC (1 << 5)
#define REG_FW_PWRCTRL_LTE_PWR_CTRL_WR_SEC (1 << 6)
#define REG_FW_PWRCTRL_GNSS_PWR_CTRL_WR_SEC (1 << 7)
#define REG_FW_PWRCTRL_AP_PWR_STAT_WR_SEC (1 << 8)
#define REG_FW_PWRCTRL_CP_PWR_STAT_WR_SEC (1 << 9)
#define REG_FW_PWRCTRL_PUB_PWR_STAT_WR_SEC (1 << 10)
#define REG_FW_PWRCTRL_RF_PWR_STAT_WR_SEC (1 << 11)
#define REG_FW_PWRCTRL_USB_PWR_STAT_WR_SEC (1 << 12)
#define REG_FW_PWRCTRL_LTE_PWR_STAT_WR_SEC (1 << 13)
#define REG_FW_PWRCTRL_GNSS_PWR_STAT_WR_SEC (1 << 14)
#define REG_FW_PWRCTRL_STATE_DELAY_WR_SEC (1 << 15)
#define REG_FW_PWRCTRL_PD_M_DELAY_WR_SEC (1 << 16)
#define REG_FW_PWRCTRL_PD_D_DELAY_WR_SEC (1 << 17)
#define REG_FW_PWRCTRL_PSRAM_HOLD_CTRL_WR_SEC (1 << 18)
#define REG_FW_PWRCTRL_SLP_BYPASS_WR_SEC (1 << 19)
#define REG_FW_PWRCTRL_SLP_TIMEOUT_FLAG_WR_SEC (1 << 20)
#define REG_FW_PWRCTRL_PWRCTRL_INT_EN_AP_WR_SEC (1 << 21)
#define REG_FW_PWRCTRL_PWRCTRL_INT_EN_CP_WR_SEC (1 << 22)
#define REG_FW_PWRCTRL_PWRCTRL_SM_STATE_WR_SEC (1 << 23)

// bit_ctrl_addr_array0
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY0(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array1
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY1(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array2
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY2(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array3
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY3(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array4
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY4(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array5
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY5(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array6
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY6(n) (((n)&0xfff) << 0)

// bit_ctrl_addr_array7
#define REG_FW_PWRCTRL_BIT_CTRL_ADDR_ARRAY7(n) (((n)&0xfff) << 0)

#endif // _REG_FW_PWRCTRL_H_
