/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _ANALOG_G3_H_
#define _ANALOG_G3_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_ANALOG_G3_SET_OFFSET (1024)
#define REG_ANALOG_G3_CLR_OFFSET (2048)

#define REG_ANALOG_G3_BASE (0x51709000)

typedef volatile struct
{
    uint32_t analog_osc_26m_apll_ctrl;         // 0x00000000
    uint32_t analog_osc_26m_reg_sel_cfg_0;     // 0x00000004
    uint32_t __8[254];                         // 0x00000008
    uint32_t analog_osc_26m_apll_ctrl_set;     // 0x00000400
    uint32_t analog_osc_26m_reg_sel_cfg_0_set; // 0x00000404
    uint32_t __1032[254];                      // 0x00000408
    uint32_t analog_osc_26m_apll_ctrl_clr;     // 0x00000800
    uint32_t analog_osc_26m_reg_sel_cfg_0_clr; // 0x00000804
} HWP_ANALOG_G3_T;

#define hwp_analogG3 ((HWP_ANALOG_G3_T *)REG_ACCESS_ADDRESS(REG_ANALOG_G3_BASE))

// analog_osc_26m_apll_ctrl
typedef union {
    uint32_t v;
    struct
    {
        uint32_t analog_osc_26m_osc26m_ibas_ctrl : 1; // [0]
        uint32_t analog_osc_26m_osc26m_c_tune : 3;    // [3:1]
        uint32_t analog_osc_26m_osc26m_r_tune : 4;    // [7:4]
        uint32_t analog_osc_26m_osc26m_pu : 1;        // [8]
        uint32_t __31_9 : 23;                         // [31:9]
    } b;
} REG_ANALOG_G3_ANALOG_OSC_26M_APLL_CTRL_T;

// analog_osc_26m_reg_sel_cfg_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dbg_sel_analog_osc_26m_osc26m_pu : 1; // [0]
        uint32_t __31_1 : 31;                          // [31:1]
    } b;
} REG_ANALOG_G3_ANALOG_OSC_26M_REG_SEL_CFG_0_T;

// analog_osc_26m_apll_ctrl
#define ANALOG_G3_ANALOG_OSC_26M_OSC26M_IBAS_CTRL (1 << 0)
#define ANALOG_G3_ANALOG_OSC_26M_OSC26M_C_TUNE(n) (((n)&0x7) << 1)
#define ANALOG_G3_ANALOG_OSC_26M_OSC26M_R_TUNE(n) (((n)&0xf) << 4)
#define ANALOG_G3_ANALOG_OSC_26M_OSC26M_PU (1 << 8)

// analog_osc_26m_reg_sel_cfg_0
#define ANALOG_G3_DBG_SEL_ANALOG_OSC_26M_OSC26M_PU (1 << 0)

#endif // _ANALOG_G3_H_
