/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _PMIC_PIN_REG_H_
#define _PMIC_PIN_REG_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_PMIC_PIN_REG_BASE (0x511087c0)

typedef volatile struct
{
    uint32_t pin_adi_sclk;   // 0x00000000
    uint32_t pin_adi_d;      // 0x00000004
    uint32_t pin_ext_rst_b;  // 0x00000008
    uint32_t pin_ana_int;    // 0x0000000c
    uint32_t pin_chip_sellp; // 0x00000010
    uint32_t pin_clk_32k;    // 0x00000014
    uint32_t pin_ptesto;     // 0x00000018
    uint32_t pin_clk26m;     // 0x0000001c
    uint32_t ext_xtl_en0;    // 0x00000020
    uint32_t ext_xtl_en1;    // 0x00000024
    uint32_t ext_xtl_en2;    // 0x00000028
    uint32_t ext_xtl_en3;    // 0x0000002c
    uint32_t ext_xtl_en4;    // 0x00000030
    uint32_t ext_xtl_en5;    // 0x00000034
    uint32_t ext_xtl_en6;    // 0x00000038
    uint32_t ext_xtl_en7;    // 0x0000003c
} HWP_PMIC_PIN_REG_T;

#define hwp_pmicPinReg ((HWP_PMIC_PIN_REG_T *)REG_ACCESS_ADDRESS(REG_PMIC_PIN_REG_BASE))

// pin_adi_sclk
typedef union {
    uint32_t v;
    struct
    {
        uint32_t adi_sclk_slp_oe : 1;   // [0]
        uint32_t adi_sclk_slp_ie : 1;   // [1]
        uint32_t adi_sclk_slp_wpdo : 1; // [2]
        uint32_t adi_sclk_slp_wpu : 1;  // [3]
        uint32_t adi_sclk_fun_sel : 2;  // [5:4]
        uint32_t adi_sclk_fun_wpdo : 1; // [6]
        uint32_t adi_sclk_fun_wpu : 1;  // [7]
        uint32_t adi_sclk_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_ADI_SCLK_T;

// pin_adi_d
typedef union {
    uint32_t v;
    struct
    {
        uint32_t adi_d_slp_oe : 1;   // [0]
        uint32_t adi_d_slp_ie : 1;   // [1]
        uint32_t adi_d_slp_wpdo : 1; // [2]
        uint32_t adi_d_slp_wpu : 1;  // [3]
        uint32_t adi_d_fun_sel : 2;  // [5:4]
        uint32_t adi_d_fun_wpdo : 1; // [6]
        uint32_t adi_d_fun_wpu : 1;  // [7]
        uint32_t adi_d_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;       // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_ADI_D_T;

// pin_ext_rst_b
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_rst_b_slp_oe : 1;   // [0]
        uint32_t ext_rst_b_slp_ie : 1;   // [1]
        uint32_t ext_rst_b_slp_wpdo : 1; // [2]
        uint32_t ext_rst_b_slp_wpu : 1;  // [3]
        uint32_t ext_rst_b_fun_sel : 2;  // [5:4]
        uint32_t ext_rst_b_fun_wpdo : 1; // [6]
        uint32_t ext_rst_b_fun_wpu : 1;  // [7]
        uint32_t ext_rst_b_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;           // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_EXT_RST_B_T;

// pin_ana_int
typedef union {
    uint32_t v;
    struct
    {
        uint32_t adi_sclk_slp_oe : 1;   // [0]
        uint32_t adi_sclk_slp_ie : 1;   // [1]
        uint32_t adi_sclk_slp_wpdo : 1; // [2]
        uint32_t adi_sclk_slp_wpu : 1;  // [3]
        uint32_t adi_sclk_fun_sel : 2;  // [5:4]
        uint32_t adi_sclk_fun_wpdo : 1; // [6]
        uint32_t adi_sclk_fun_wpu : 1;  // [7]
        uint32_t adi_sclk_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_ANA_INT_T;

// pin_chip_sellp
typedef union {
    uint32_t v;
    struct
    {
        uint32_t chip_sleep_slp_oe : 1;   // [0]
        uint32_t chip_sleep_slp_ie : 1;   // [1]
        uint32_t chip_sleep_slp_wpdo : 1; // [2]
        uint32_t chip_sleep_slp_wpu : 1;  // [3]
        uint32_t chip_sleep_fun_sel : 2;  // [5:4]
        uint32_t chip_sleep_fun_wpdo : 1; // [6]
        uint32_t chip_sleep_fun_wpu : 1;  // [7]
        uint32_t chip_sleep_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;            // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_CHIP_SELLP_T;

// pin_clk_32k
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk_32k_slp_oe : 1;   // [0]
        uint32_t clk_32k_slp_ie : 1;   // [1]
        uint32_t clk_32k_slp_wpdo : 1; // [2]
        uint32_t clk_32k_slp_wpu : 1;  // [3]
        uint32_t clk_32k_fun_sel : 2;  // [5:4]
        uint32_t clk_32k_fun_wpdo : 1; // [6]
        uint32_t clk_32k_fun_wpu : 1;  // [7]
        uint32_t clk_32k_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;         // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_CLK_32K_T;

// pin_ptesto
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ptesto_slp_oe : 1;   // [0]
        uint32_t ptesto_slp_ie : 1;   // [1]
        uint32_t ptesto_slp_wpdo : 1; // [2]
        uint32_t ptesto_slp_wpu : 1;  // [3]
        uint32_t ptesto_fun_sel : 2;  // [5:4]
        uint32_t ptesto_fun_wpdo : 1; // [6]
        uint32_t ptesto_fun_wpu : 1;  // [7]
        uint32_t ptesto_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;        // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_PTESTO_T;

// pin_clk26m
typedef union {
    uint32_t v;
    struct
    {
        uint32_t clk26m_slp_oe : 1;   // [0]
        uint32_t clk26m_slp_ie : 1;   // [1]
        uint32_t clk26m_slp_wpdo : 1; // [2]
        uint32_t clk26m_slp_wpu : 1;  // [3]
        uint32_t clk26m_fun_sel : 2;  // [5:4]
        uint32_t clk26m_fun_wpdo : 1; // [6]
        uint32_t clk26m_fun_wpu : 1;  // [7]
        uint32_t clk26m_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;        // [31:10]
    } b;
} REG_PMIC_PIN_REG_PIN_CLK26M_T;

// ext_xtl_en0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en0_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en0_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en0_wpdo : 1;     // [2]
        uint32_t ext_xtl_en0_wpu : 1;      // [3]
        uint32_t ext_xtl_en0_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en0_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en0_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en0_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN0_T;

// ext_xtl_en1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en1_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en1_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en1_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en1_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en1_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en1_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en1_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en1_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN1_T;

// ext_xtl_en2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en2_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en2_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en2_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en2_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en2_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en2_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en2_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en2_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN2_T;

// ext_xtl_en3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en3_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en3_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en3_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en3_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en3_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en3_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en3_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en3_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN3_T;

// ext_xtl_en4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en4_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en4_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en4_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en4_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en4_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en4_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en4_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en4_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN4_T;

// ext_xtl_en5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en5_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en5_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en5_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en5_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en5_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en5_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en5_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en5_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN5_T;

// ext_xtl_en6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en6_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en6_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en6_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en6_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en6_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en6_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en6_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en6_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN6_T;

// ext_xtl_en7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ext_xtl_en7_slp_oe : 1;   // [0]
        uint32_t ext_xtl_en7_slp_ie : 1;   // [1]
        uint32_t ext_xtl_en7_slp_wpdo : 1; // [2]
        uint32_t ext_xtl_en7_slp_wpu : 1;  // [3]
        uint32_t ext_xtl_en7_fun_sel : 2;  // [5:4]
        uint32_t ext_xtl_en7_fun_wpdo : 1; // [6]
        uint32_t ext_xtl_en7_fun_wpu : 1;  // [7]
        uint32_t ext_xtl_en7_bsr_drv : 2;  // [9:8]
        uint32_t __31_10 : 22;             // [31:10]
    } b;
} REG_PMIC_PIN_REG_EXT_XTL_EN7_T;

// pin_adi_sclk
#define PMIC_PIN_REG_ADI_SCLK_SLP_OE (1 << 0)
#define PMIC_PIN_REG_ADI_SCLK_SLP_IE (1 << 1)
#define PMIC_PIN_REG_ADI_SCLK_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_ADI_SCLK_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_ADI_SCLK_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_ADI_SCLK_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_ADI_SCLK_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_ADI_SCLK_BSR_DRV(n) (((n)&0x3) << 8)

// pin_adi_d
#define PMIC_PIN_REG_ADI_D_SLP_OE (1 << 0)
#define PMIC_PIN_REG_ADI_D_SLP_IE (1 << 1)
#define PMIC_PIN_REG_ADI_D_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_ADI_D_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_ADI_D_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_ADI_D_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_ADI_D_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_ADI_D_BSR_DRV(n) (((n)&0x3) << 8)

// pin_ext_rst_b
#define PMIC_PIN_REG_EXT_RST_B_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_RST_B_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_RST_B_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_RST_B_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_RST_B_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_RST_B_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_RST_B_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_RST_B_BSR_DRV(n) (((n)&0x3) << 8)

// pin_ana_int
#define PMIC_PIN_REG_ADI_SCLK_SLP_OE (1 << 0)
#define PMIC_PIN_REG_ADI_SCLK_SLP_IE (1 << 1)
#define PMIC_PIN_REG_ADI_SCLK_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_ADI_SCLK_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_ADI_SCLK_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_ADI_SCLK_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_ADI_SCLK_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_ADI_SCLK_BSR_DRV(n) (((n)&0x3) << 8)

// pin_chip_sellp
#define PMIC_PIN_REG_CHIP_SLEEP_SLP_OE (1 << 0)
#define PMIC_PIN_REG_CHIP_SLEEP_SLP_IE (1 << 1)
#define PMIC_PIN_REG_CHIP_SLEEP_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_CHIP_SLEEP_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_CHIP_SLEEP_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_CHIP_SLEEP_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_CHIP_SLEEP_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_CHIP_SLEEP_BSR_DRV(n) (((n)&0x3) << 8)

// pin_clk_32k
#define PMIC_PIN_REG_CLK_32K_SLP_OE (1 << 0)
#define PMIC_PIN_REG_CLK_32K_SLP_IE (1 << 1)
#define PMIC_PIN_REG_CLK_32K_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_CLK_32K_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_CLK_32K_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_CLK_32K_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_CLK_32K_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_CLK_32K_BSR_DRV(n) (((n)&0x3) << 8)

// pin_ptesto
#define PMIC_PIN_REG_PTESTO_SLP_OE (1 << 0)
#define PMIC_PIN_REG_PTESTO_SLP_IE (1 << 1)
#define PMIC_PIN_REG_PTESTO_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_PTESTO_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_PTESTO_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_PTESTO_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_PTESTO_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_PTESTO_BSR_DRV(n) (((n)&0x3) << 8)

// pin_clk26m
#define PMIC_PIN_REG_CLK26M_SLP_OE (1 << 0)
#define PMIC_PIN_REG_CLK26M_SLP_IE (1 << 1)
#define PMIC_PIN_REG_CLK26M_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_CLK26M_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_CLK26M_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_CLK26M_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_CLK26M_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_CLK26M_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en0
#define PMIC_PIN_REG_EXT_XTL_EN0_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN0_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN0_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN0_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN0_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN0_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN0_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN0_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en1
#define PMIC_PIN_REG_EXT_XTL_EN1_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN1_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN1_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN1_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN1_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN1_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN1_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN1_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en2
#define PMIC_PIN_REG_EXT_XTL_EN2_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN2_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN2_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN2_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN2_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN2_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN2_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN2_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en3
#define PMIC_PIN_REG_EXT_XTL_EN3_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN3_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN3_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN3_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN3_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN3_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN3_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN3_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en4
#define PMIC_PIN_REG_EXT_XTL_EN4_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN4_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN4_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN4_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN4_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN4_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN4_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN4_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en5
#define PMIC_PIN_REG_EXT_XTL_EN5_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN5_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN5_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN5_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN5_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN5_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN5_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN5_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en6
#define PMIC_PIN_REG_EXT_XTL_EN6_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN6_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN6_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN6_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN6_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN6_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN6_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN6_BSR_DRV(n) (((n)&0x3) << 8)

// ext_xtl_en7
#define PMIC_PIN_REG_EXT_XTL_EN7_SLP_OE (1 << 0)
#define PMIC_PIN_REG_EXT_XTL_EN7_SLP_IE (1 << 1)
#define PMIC_PIN_REG_EXT_XTL_EN7_SLP_WPDO (1 << 2)
#define PMIC_PIN_REG_EXT_XTL_EN7_SLP_WPU (1 << 3)
#define PMIC_PIN_REG_EXT_XTL_EN7_FUN_SEL(n) (((n)&0x3) << 4)
#define PMIC_PIN_REG_EXT_XTL_EN7_FUN_WPDO (1 << 6)
#define PMIC_PIN_REG_EXT_XTL_EN7_FUN_WPU (1 << 7)
#define PMIC_PIN_REG_EXT_XTL_EN7_BSR_DRV(n) (((n)&0x3) << 8)

#endif // _PMIC_PIN_REG_H_
