/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _REG_FW_IOMUX_H_
#define _REG_FW_IOMUX_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_REG_FW_IOMUX_BASE (0x51306000)

typedef volatile struct
{
    uint32_t reg_rd_ctrl_0;        // 0x00000000
    uint32_t reg_rd_ctrl_1;        // 0x00000004
    uint32_t reg_rd_ctrl_2;        // 0x00000008
    uint32_t reg_rd_ctrl_3;        // 0x0000000c
    uint32_t reg_wr_ctrl_0;        // 0x00000010
    uint32_t reg_wr_ctrl_1;        // 0x00000014
    uint32_t reg_wr_ctrl_2;        // 0x00000018
    uint32_t reg_wr_ctrl_3;        // 0x0000001c
    uint32_t bit_ctrl_addr_array0; // 0x00000020
    uint32_t bit_ctrl_addr_array1; // 0x00000024
    uint32_t bit_ctrl_addr_array2; // 0x00000028
    uint32_t bit_ctrl_addr_array3; // 0x0000002c
    uint32_t bit_ctrl_addr_array4; // 0x00000030
    uint32_t bit_ctrl_addr_array5; // 0x00000034
    uint32_t bit_ctrl_addr_array6; // 0x00000038
    uint32_t bit_ctrl_addr_array7; // 0x0000003c
    uint32_t bit_ctrl_array0;      // 0x00000040
    uint32_t bit_ctrl_array1;      // 0x00000044
    uint32_t bit_ctrl_array2;      // 0x00000048
    uint32_t bit_ctrl_array3;      // 0x0000004c
    uint32_t bit_ctrl_array4;      // 0x00000050
    uint32_t bit_ctrl_array5;      // 0x00000054
    uint32_t bit_ctrl_array6;      // 0x00000058
    uint32_t bit_ctrl_array7;      // 0x0000005c
} HWP_REG_FW_IOMUX_T;

#define hwp_regFwIomux ((HWP_REG_FW_IOMUX_T *)REG_ACCESS_ADDRESS(REG_REG_FW_IOMUX_BASE))

// reg_rd_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;                // [0]
        uint32_t pin_ctrl_reg0_rd_sec : 1; // [1]
        uint32_t pin_ctrl_reg1_rd_sec : 1; // [2]
        uint32_t pin_ctrl_reg2_rd_sec : 1; // [3]
        uint32_t pin_ctrl_reg3_rd_sec : 1; // [4]
        uint32_t pin_ctrl_reg4_rd_sec : 1; // [5]
        uint32_t pin_ctrl_reg5_rd_sec : 1; // [6]
        uint32_t rfdig_gpio_7_rd_sec : 1;  // [7]
        uint32_t rfdig_gpio_6_rd_sec : 1;  // [8]
        uint32_t rfdig_gpio_5_rd_sec : 1;  // [9]
        uint32_t rfdig_gpio_4_rd_sec : 1;  // [10]
        uint32_t rfdig_gpio_3_rd_sec : 1;  // [11]
        uint32_t rfdig_gpio_2_rd_sec : 1;  // [12]
        uint32_t rfdig_gpio_1_rd_sec : 1;  // [13]
        uint32_t rfdig_gpio_0_rd_sec : 1;  // [14]
        uint32_t keyin_4_rd_sec : 1;       // [15]
        uint32_t keyout_5_rd_sec : 1;      // [16]
        uint32_t keyin_5_rd_sec : 1;       // [17]
        uint32_t keyout_4_rd_sec : 1;      // [18]
        uint32_t uart_1_rts_rd_sec : 1;    // [19]
        uint32_t uart_1_txd_rd_sec : 1;    // [20]
        uint32_t uart_1_rxd_rd_sec : 1;    // [21]
        uint32_t uart_1_cts_rd_sec : 1;    // [22]
        uint32_t gpio_0_rd_sec : 1;        // [23]
        uint32_t gpio_3_rd_sec : 1;        // [24]
        uint32_t gpio_2_rd_sec : 1;        // [25]
        uint32_t gpio_1_rd_sec : 1;        // [26]
        uint32_t gpio_7_rd_sec : 1;        // [27]
        uint32_t gpio_6_rd_sec : 1;        // [28]
        uint32_t gpio_5_rd_sec : 1;        // [29]
        uint32_t gpio_4_rd_sec : 1;        // [30]
        uint32_t adi_sda_rd_sec : 1;       // [31]
    } b;
} REG_REG_FW_IOMUX_REG_RD_CTRL_0_T;

// reg_rd_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t adi_scl_rd_sec : 1;         // [0]
        uint32_t resetb_rd_sec : 1;          // [1]
        uint32_t osc_32k_rd_sec : 1;         // [2]
        uint32_t pmic_ext_int_rd_sec : 1;    // [3]
        uint32_t chip_pd_rd_sec : 1;         // [4]
        uint32_t ptest_rd_sec : 1;           // [5]
        uint32_t clk26m_pmic_rd_sec : 1;     // [6]
        uint32_t sim_1_rst_rd_sec : 1;       // [7]
        uint32_t sim_1_dio_rd_sec : 1;       // [8]
        uint32_t sim_1_clk_rd_sec : 1;       // [9]
        uint32_t sim_0_rst_rd_sec : 1;       // [10]
        uint32_t sim_0_dio_rd_sec : 1;       // [11]
        uint32_t sim_0_clk_rd_sec : 1;       // [12]
        uint32_t sw_clk_rd_sec : 1;          // [13]
        uint32_t sw_dio_rd_sec : 1;          // [14]
        uint32_t debug_host_tx_rd_sec : 1;   // [15]
        uint32_t debug_host_rx_rd_sec : 1;   // [16]
        uint32_t debug_host_clk_rd_sec : 1;  // [17]
        uint32_t camera_rst_l_rd_sec : 1;    // [18]
        uint32_t spi_camera_sck_rd_sec : 1;  // [19]
        uint32_t spi_camera_si_1_rd_sec : 1; // [20]
        uint32_t spi_camera_si_0_rd_sec : 1; // [21]
        uint32_t camera_ref_clk_rd_sec : 1;  // [22]
        uint32_t camera_pwdn_rd_sec : 1;     // [23]
        uint32_t i2s_sdat_i_rd_sec : 1;      // [24]
        uint32_t i2s1_sdat_o_rd_sec : 1;     // [25]
        uint32_t i2s1_lrck_rd_sec : 1;       // [26]
        uint32_t i2s1_bck_rd_sec : 1;        // [27]
        uint32_t i2s1_mclk_rd_sec : 1;       // [28]
        uint32_t i2c_m2_scl_rd_sec : 1;      // [29]
        uint32_t i2c_m2_sda_rd_sec : 1;      // [30]
        uint32_t nand_sel_rd_sec : 1;        // [31]
    } b;
} REG_REG_FW_IOMUX_REG_RD_CTRL_1_T;

// reg_rd_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t keyout_3_rd_sec : 1;       // [0]
        uint32_t keyout_2_rd_sec : 1;       // [1]
        uint32_t keyout_1_rd_sec : 1;       // [2]
        uint32_t keyout_0_rd_sec : 1;       // [3]
        uint32_t keyin_3_rd_sec : 1;        // [4]
        uint32_t keyin_2_rd_sec : 1;        // [5]
        uint32_t keyin_1_rd_sec : 1;        // [6]
        uint32_t keyin_0_rd_sec : 1;        // [7]
        uint32_t lcd_rstb_rd_sec : 1;       // [8]
        uint32_t lcd_fmark_rd_sec : 1;      // [9]
        uint32_t spi_lcd_select_rd_sec : 1; // [10]
        uint32_t spi_lcd_cs_rd_sec : 1;     // [11]
        uint32_t spi_lcd_clk_rd_sec : 1;    // [12]
        uint32_t spi_lcd_sdc_rd_sec : 1;    // [13]
        uint32_t spi_lcd_sio_rd_sec : 1;    // [14]
        uint32_t sdmmc1_rst_rd_sec : 1;     // [15]
        uint32_t sdmmc1_data_7_rd_sec : 1;  // [16]
        uint32_t sdmmc1_data_6_rd_sec : 1;  // [17]
        uint32_t sdmmc1_data_5_rd_sec : 1;  // [18]
        uint32_t sdmmc1_data_4_rd_sec : 1;  // [19]
        uint32_t sdmmc1_data_3_rd_sec : 1;  // [20]
        uint32_t sdmmc1_data_2_rd_sec : 1;  // [21]
        uint32_t sdmmc1_data_1_rd_sec : 1;  // [22]
        uint32_t sdmmc1_data_0_rd_sec : 1;  // [23]
        uint32_t sdmmc1_cmd_rd_sec : 1;     // [24]
        uint32_t sdmmc1_clk_rd_sec : 1;     // [25]
        uint32_t uart_2_rts_rd_sec : 1;     // [26]
        uint32_t uart_2_cts_rd_sec : 1;     // [27]
        uint32_t uart_2_txd_rd_sec : 1;     // [28]
        uint32_t uart_2_rxd_rd_sec : 1;     // [29]
        uint32_t i2c_m1_sda_rd_sec : 1;     // [30]
        uint32_t i2c_m1_scl_rd_sec : 1;     // [31]
    } b;
} REG_REG_FW_IOMUX_REG_RD_CTRL_2_T;

// reg_rd_ctrl_3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t gpio_23_rd_sec : 1;   // [0]
        uint32_t gpio_22_rd_sec : 1;   // [1]
        uint32_t gpio_21_rd_sec : 1;   // [2]
        uint32_t gpio_20_rd_sec : 1;   // [3]
        uint32_t gpio_19_rd_sec : 1;   // [4]
        uint32_t gpio_18_rd_sec : 1;   // [5]
        uint32_t gpio_17_rd_sec : 1;   // [6]
        uint32_t gpio_16_rd_sec : 1;   // [7]
        uint32_t m_spi_d_3_rd_sec : 1; // [8]
        uint32_t m_spi_d_2_rd_sec : 1; // [9]
        uint32_t m_spi_d_1_rd_sec : 1; // [10]
        uint32_t m_spi_d_0_rd_sec : 1; // [11]
        uint32_t m_spi_cs_rd_sec : 1;  // [12]
        uint32_t m_spi_clk_rd_sec : 1; // [13]
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_REG_FW_IOMUX_REG_RD_CTRL_3_T;

// reg_wr_ctrl_0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;                // [0]
        uint32_t pin_ctrl_reg0_wr_sec : 1; // [1]
        uint32_t pin_ctrl_reg1_wr_sec : 1; // [2]
        uint32_t pin_ctrl_reg2_wr_sec : 1; // [3]
        uint32_t pin_ctrl_reg3_wr_sec : 1; // [4]
        uint32_t pin_ctrl_reg4_wr_sec : 1; // [5]
        uint32_t pin_ctrl_reg5_wr_sec : 1; // [6]
        uint32_t rfdig_gpio_7_wr_sec : 1;  // [7]
        uint32_t rfdig_gpio_6_wr_sec : 1;  // [8]
        uint32_t rfdig_gpio_5_wr_sec : 1;  // [9]
        uint32_t rfdig_gpio_4_wr_sec : 1;  // [10]
        uint32_t rfdig_gpio_3_wr_sec : 1;  // [11]
        uint32_t rfdig_gpio_2_wr_sec : 1;  // [12]
        uint32_t rfdig_gpio_1_wr_sec : 1;  // [13]
        uint32_t rfdig_gpio_0_wr_sec : 1;  // [14]
        uint32_t keyin_4_wr_sec : 1;       // [15]
        uint32_t keyout_5_wr_sec : 1;      // [16]
        uint32_t keyin_5_wr_sec : 1;       // [17]
        uint32_t keyout_4_wr_sec : 1;      // [18]
        uint32_t uart_1_rts_wr_sec : 1;    // [19]
        uint32_t uart_1_txd_wr_sec : 1;    // [20]
        uint32_t uart_1_rxd_wr_sec : 1;    // [21]
        uint32_t uart_1_cts_wr_sec : 1;    // [22]
        uint32_t gpio_0_wr_sec : 1;        // [23]
        uint32_t gpio_3_wr_sec : 1;        // [24]
        uint32_t gpio_2_wr_sec : 1;        // [25]
        uint32_t gpio_1_wr_sec : 1;        // [26]
        uint32_t gpio_7_wr_sec : 1;        // [27]
        uint32_t gpio_6_wr_sec : 1;        // [28]
        uint32_t gpio_5_wr_sec : 1;        // [29]
        uint32_t gpio_4_wr_sec : 1;        // [30]
        uint32_t adi_sda_wr_sec : 1;       // [31]
    } b;
} REG_REG_FW_IOMUX_REG_WR_CTRL_0_T;

// reg_wr_ctrl_1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t adi_scl_wr_sec : 1;         // [0]
        uint32_t resetb_wr_sec : 1;          // [1]
        uint32_t osc_32k_wr_sec : 1;         // [2]
        uint32_t pmic_ext_int_wr_sec : 1;    // [3]
        uint32_t chip_pd_wr_sec : 1;         // [4]
        uint32_t ptest_wr_sec : 1;           // [5]
        uint32_t clk26m_pmic_wr_sec : 1;     // [6]
        uint32_t sim_1_rst_wr_sec : 1;       // [7]
        uint32_t sim_1_dio_wr_sec : 1;       // [8]
        uint32_t sim_1_clk_wr_sec : 1;       // [9]
        uint32_t sim_0_rst_wr_sec : 1;       // [10]
        uint32_t sim_0_dio_wr_sec : 1;       // [11]
        uint32_t sim_0_clk_wr_sec : 1;       // [12]
        uint32_t sw_clk_wr_sec : 1;          // [13]
        uint32_t sw_dio_wr_sec : 1;          // [14]
        uint32_t debug_host_tx_wr_sec : 1;   // [15]
        uint32_t debug_host_rx_wr_sec : 1;   // [16]
        uint32_t debug_host_clk_wr_sec : 1;  // [17]
        uint32_t camera_rst_l_wr_sec : 1;    // [18]
        uint32_t spi_camera_sck_wr_sec : 1;  // [19]
        uint32_t spi_camera_si_1_wr_sec : 1; // [20]
        uint32_t spi_camera_si_0_wr_sec : 1; // [21]
        uint32_t camera_ref_clk_wr_sec : 1;  // [22]
        uint32_t camera_pwdn_wr_sec : 1;     // [23]
        uint32_t i2s_sdat_i_wr_sec : 1;      // [24]
        uint32_t i2s1_sdat_o_wr_sec : 1;     // [25]
        uint32_t i2s1_lrck_wr_sec : 1;       // [26]
        uint32_t i2s1_bck_wr_sec : 1;        // [27]
        uint32_t i2s1_mclk_wr_sec : 1;       // [28]
        uint32_t i2c_m2_scl_wr_sec : 1;      // [29]
        uint32_t i2c_m2_sda_wr_sec : 1;      // [30]
        uint32_t nand_sel_wr_sec : 1;        // [31]
    } b;
} REG_REG_FW_IOMUX_REG_WR_CTRL_1_T;

// reg_wr_ctrl_2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t keyout_3_wr_sec : 1;       // [0]
        uint32_t keyout_2_wr_sec : 1;       // [1]
        uint32_t keyout_1_wr_sec : 1;       // [2]
        uint32_t keyout_0_wr_sec : 1;       // [3]
        uint32_t keyin_3_wr_sec : 1;        // [4]
        uint32_t keyin_2_wr_sec : 1;        // [5]
        uint32_t keyin_1_wr_sec : 1;        // [6]
        uint32_t keyin_0_wr_sec : 1;        // [7]
        uint32_t lcd_rstb_wr_sec : 1;       // [8]
        uint32_t lcd_fmark_wr_sec : 1;      // [9]
        uint32_t spi_lcd_select_wr_sec : 1; // [10]
        uint32_t spi_lcd_cs_wr_sec : 1;     // [11]
        uint32_t spi_lcd_clk_wr_sec : 1;    // [12]
        uint32_t spi_lcd_sdc_wr_sec : 1;    // [13]
        uint32_t spi_lcd_sio_wr_sec : 1;    // [14]
        uint32_t sdmmc1_rst_wr_sec : 1;     // [15]
        uint32_t sdmmc1_data_7_wr_sec : 1;  // [16]
        uint32_t sdmmc1_data_6_wr_sec : 1;  // [17]
        uint32_t sdmmc1_data_5_wr_sec : 1;  // [18]
        uint32_t sdmmc1_data_4_wr_sec : 1;  // [19]
        uint32_t sdmmc1_data_3_wr_sec : 1;  // [20]
        uint32_t sdmmc1_data_2_wr_sec : 1;  // [21]
        uint32_t sdmmc1_data_1_wr_sec : 1;  // [22]
        uint32_t sdmmc1_data_0_wr_sec : 1;  // [23]
        uint32_t sdmmc1_cmd_wr_sec : 1;     // [24]
        uint32_t sdmmc1_clk_wr_sec : 1;     // [25]
        uint32_t uart_2_rts_wr_sec : 1;     // [26]
        uint32_t uart_2_cts_wr_sec : 1;     // [27]
        uint32_t uart_2_txd_wr_sec : 1;     // [28]
        uint32_t uart_2_rxd_wr_sec : 1;     // [29]
        uint32_t i2c_m1_sda_wr_sec : 1;     // [30]
        uint32_t i2c_m1_scl_wr_sec : 1;     // [31]
    } b;
} REG_REG_FW_IOMUX_REG_WR_CTRL_2_T;

// reg_wr_ctrl_3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t gpio_23_wr_sec : 1;   // [0]
        uint32_t gpio_22_wr_sec : 1;   // [1]
        uint32_t gpio_21_wr_sec : 1;   // [2]
        uint32_t gpio_20_wr_sec : 1;   // [3]
        uint32_t gpio_19_wr_sec : 1;   // [4]
        uint32_t gpio_18_wr_sec : 1;   // [5]
        uint32_t gpio_17_wr_sec : 1;   // [6]
        uint32_t gpio_16_wr_sec : 1;   // [7]
        uint32_t m_spi_d_3_wr_sec : 1; // [8]
        uint32_t m_spi_d_2_wr_sec : 1; // [9]
        uint32_t m_spi_d_1_wr_sec : 1; // [10]
        uint32_t m_spi_d_0_wr_sec : 1; // [11]
        uint32_t m_spi_cs_wr_sec : 1;  // [12]
        uint32_t m_spi_clk_wr_sec : 1; // [13]
        uint32_t __31_14 : 18;         // [31:14]
    } b;
} REG_REG_FW_IOMUX_REG_WR_CTRL_3_T;

// bit_ctrl_addr_array0
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array0 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY0_T;

// bit_ctrl_addr_array1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array1 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY1_T;

// bit_ctrl_addr_array2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array2 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY2_T;

// bit_ctrl_addr_array3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array3 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY3_T;

// bit_ctrl_addr_array4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array4 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY4_T;

// bit_ctrl_addr_array5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array5 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY5_T;

// bit_ctrl_addr_array6
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array6 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY6_T;

// bit_ctrl_addr_array7
typedef union {
    uint32_t v;
    struct
    {
        uint32_t bit_ctrl_addr_array7 : 14; // [13:0]
        uint32_t __31_14 : 18;              // [31:14]
    } b;
} REG_REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY7_T;

// reg_rd_ctrl_0
#define REG_FW_IOMUX_PIN_CTRL_REG0_RD_SEC (1 << 1)
#define REG_FW_IOMUX_PIN_CTRL_REG1_RD_SEC (1 << 2)
#define REG_FW_IOMUX_PIN_CTRL_REG2_RD_SEC (1 << 3)
#define REG_FW_IOMUX_PIN_CTRL_REG3_RD_SEC (1 << 4)
#define REG_FW_IOMUX_PIN_CTRL_REG4_RD_SEC (1 << 5)
#define REG_FW_IOMUX_PIN_CTRL_REG5_RD_SEC (1 << 6)
#define REG_FW_IOMUX_RFDIG_GPIO_7_RD_SEC (1 << 7)
#define REG_FW_IOMUX_RFDIG_GPIO_6_RD_SEC (1 << 8)
#define REG_FW_IOMUX_RFDIG_GPIO_5_RD_SEC (1 << 9)
#define REG_FW_IOMUX_RFDIG_GPIO_4_RD_SEC (1 << 10)
#define REG_FW_IOMUX_RFDIG_GPIO_3_RD_SEC (1 << 11)
#define REG_FW_IOMUX_RFDIG_GPIO_2_RD_SEC (1 << 12)
#define REG_FW_IOMUX_RFDIG_GPIO_1_RD_SEC (1 << 13)
#define REG_FW_IOMUX_RFDIG_GPIO_0_RD_SEC (1 << 14)
#define REG_FW_IOMUX_KEYIN_4_RD_SEC (1 << 15)
#define REG_FW_IOMUX_KEYOUT_5_RD_SEC (1 << 16)
#define REG_FW_IOMUX_KEYIN_5_RD_SEC (1 << 17)
#define REG_FW_IOMUX_KEYOUT_4_RD_SEC (1 << 18)
#define REG_FW_IOMUX_UART_1_RTS_RD_SEC (1 << 19)
#define REG_FW_IOMUX_UART_1_TXD_RD_SEC (1 << 20)
#define REG_FW_IOMUX_UART_1_RXD_RD_SEC (1 << 21)
#define REG_FW_IOMUX_UART_1_CTS_RD_SEC (1 << 22)
#define REG_FW_IOMUX_GPIO_0_RD_SEC (1 << 23)
#define REG_FW_IOMUX_GPIO_3_RD_SEC (1 << 24)
#define REG_FW_IOMUX_GPIO_2_RD_SEC (1 << 25)
#define REG_FW_IOMUX_GPIO_1_RD_SEC (1 << 26)
#define REG_FW_IOMUX_GPIO_7_RD_SEC (1 << 27)
#define REG_FW_IOMUX_GPIO_6_RD_SEC (1 << 28)
#define REG_FW_IOMUX_GPIO_5_RD_SEC (1 << 29)
#define REG_FW_IOMUX_GPIO_4_RD_SEC (1 << 30)
#define REG_FW_IOMUX_ADI_SDA_RD_SEC (1 << 31)

// reg_rd_ctrl_1
#define REG_FW_IOMUX_ADI_SCL_RD_SEC (1 << 0)
#define REG_FW_IOMUX_RESETB_RD_SEC (1 << 1)
#define REG_FW_IOMUX_OSC_32K_RD_SEC (1 << 2)
#define REG_FW_IOMUX_PMIC_EXT_INT_RD_SEC (1 << 3)
#define REG_FW_IOMUX_CHIP_PD_RD_SEC (1 << 4)
#define REG_FW_IOMUX_PTEST_RD_SEC (1 << 5)
#define REG_FW_IOMUX_CLK26M_PMIC_RD_SEC (1 << 6)
#define REG_FW_IOMUX_SIM_1_RST_RD_SEC (1 << 7)
#define REG_FW_IOMUX_SIM_1_DIO_RD_SEC (1 << 8)
#define REG_FW_IOMUX_SIM_1_CLK_RD_SEC (1 << 9)
#define REG_FW_IOMUX_SIM_0_RST_RD_SEC (1 << 10)
#define REG_FW_IOMUX_SIM_0_DIO_RD_SEC (1 << 11)
#define REG_FW_IOMUX_SIM_0_CLK_RD_SEC (1 << 12)
#define REG_FW_IOMUX_SW_CLK_RD_SEC (1 << 13)
#define REG_FW_IOMUX_SW_DIO_RD_SEC (1 << 14)
#define REG_FW_IOMUX_DEBUG_HOST_TX_RD_SEC (1 << 15)
#define REG_FW_IOMUX_DEBUG_HOST_RX_RD_SEC (1 << 16)
#define REG_FW_IOMUX_DEBUG_HOST_CLK_RD_SEC (1 << 17)
#define REG_FW_IOMUX_CAMERA_RST_L_RD_SEC (1 << 18)
#define REG_FW_IOMUX_SPI_CAMERA_SCK_RD_SEC (1 << 19)
#define REG_FW_IOMUX_SPI_CAMERA_SI_1_RD_SEC (1 << 20)
#define REG_FW_IOMUX_SPI_CAMERA_SI_0_RD_SEC (1 << 21)
#define REG_FW_IOMUX_CAMERA_REF_CLK_RD_SEC (1 << 22)
#define REG_FW_IOMUX_CAMERA_PWDN_RD_SEC (1 << 23)
#define REG_FW_IOMUX_I2S_SDAT_I_RD_SEC (1 << 24)
#define REG_FW_IOMUX_I2S1_SDAT_O_RD_SEC (1 << 25)
#define REG_FW_IOMUX_I2S1_LRCK_RD_SEC (1 << 26)
#define REG_FW_IOMUX_I2S1_BCK_RD_SEC (1 << 27)
#define REG_FW_IOMUX_I2S1_MCLK_RD_SEC (1 << 28)
#define REG_FW_IOMUX_I2C_M2_SCL_RD_SEC (1 << 29)
#define REG_FW_IOMUX_I2C_M2_SDA_RD_SEC (1 << 30)
#define REG_FW_IOMUX_NAND_SEL_RD_SEC (1 << 31)

// reg_rd_ctrl_2
#define REG_FW_IOMUX_KEYOUT_3_RD_SEC (1 << 0)
#define REG_FW_IOMUX_KEYOUT_2_RD_SEC (1 << 1)
#define REG_FW_IOMUX_KEYOUT_1_RD_SEC (1 << 2)
#define REG_FW_IOMUX_KEYOUT_0_RD_SEC (1 << 3)
#define REG_FW_IOMUX_KEYIN_3_RD_SEC (1 << 4)
#define REG_FW_IOMUX_KEYIN_2_RD_SEC (1 << 5)
#define REG_FW_IOMUX_KEYIN_1_RD_SEC (1 << 6)
#define REG_FW_IOMUX_KEYIN_0_RD_SEC (1 << 7)
#define REG_FW_IOMUX_LCD_RSTB_RD_SEC (1 << 8)
#define REG_FW_IOMUX_LCD_FMARK_RD_SEC (1 << 9)
#define REG_FW_IOMUX_SPI_LCD_SELECT_RD_SEC (1 << 10)
#define REG_FW_IOMUX_SPI_LCD_CS_RD_SEC (1 << 11)
#define REG_FW_IOMUX_SPI_LCD_CLK_RD_SEC (1 << 12)
#define REG_FW_IOMUX_SPI_LCD_SDC_RD_SEC (1 << 13)
#define REG_FW_IOMUX_SPI_LCD_SIO_RD_SEC (1 << 14)
#define REG_FW_IOMUX_SDMMC1_RST_RD_SEC (1 << 15)
#define REG_FW_IOMUX_SDMMC1_DATA_7_RD_SEC (1 << 16)
#define REG_FW_IOMUX_SDMMC1_DATA_6_RD_SEC (1 << 17)
#define REG_FW_IOMUX_SDMMC1_DATA_5_RD_SEC (1 << 18)
#define REG_FW_IOMUX_SDMMC1_DATA_4_RD_SEC (1 << 19)
#define REG_FW_IOMUX_SDMMC1_DATA_3_RD_SEC (1 << 20)
#define REG_FW_IOMUX_SDMMC1_DATA_2_RD_SEC (1 << 21)
#define REG_FW_IOMUX_SDMMC1_DATA_1_RD_SEC (1 << 22)
#define REG_FW_IOMUX_SDMMC1_DATA_0_RD_SEC (1 << 23)
#define REG_FW_IOMUX_SDMMC1_CMD_RD_SEC (1 << 24)
#define REG_FW_IOMUX_SDMMC1_CLK_RD_SEC (1 << 25)
#define REG_FW_IOMUX_UART_2_RTS_RD_SEC (1 << 26)
#define REG_FW_IOMUX_UART_2_CTS_RD_SEC (1 << 27)
#define REG_FW_IOMUX_UART_2_TXD_RD_SEC (1 << 28)
#define REG_FW_IOMUX_UART_2_RXD_RD_SEC (1 << 29)
#define REG_FW_IOMUX_I2C_M1_SDA_RD_SEC (1 << 30)
#define REG_FW_IOMUX_I2C_M1_SCL_RD_SEC (1 << 31)

// reg_rd_ctrl_3
#define REG_FW_IOMUX_GPIO_23_RD_SEC (1 << 0)
#define REG_FW_IOMUX_GPIO_22_RD_SEC (1 << 1)
#define REG_FW_IOMUX_GPIO_21_RD_SEC (1 << 2)
#define REG_FW_IOMUX_GPIO_20_RD_SEC (1 << 3)
#define REG_FW_IOMUX_GPIO_19_RD_SEC (1 << 4)
#define REG_FW_IOMUX_GPIO_18_RD_SEC (1 << 5)
#define REG_FW_IOMUX_GPIO_17_RD_SEC (1 << 6)
#define REG_FW_IOMUX_GPIO_16_RD_SEC (1 << 7)
#define REG_FW_IOMUX_M_SPI_D_3_RD_SEC (1 << 8)
#define REG_FW_IOMUX_M_SPI_D_2_RD_SEC (1 << 9)
#define REG_FW_IOMUX_M_SPI_D_1_RD_SEC (1 << 10)
#define REG_FW_IOMUX_M_SPI_D_0_RD_SEC (1 << 11)
#define REG_FW_IOMUX_M_SPI_CS_RD_SEC (1 << 12)
#define REG_FW_IOMUX_M_SPI_CLK_RD_SEC (1 << 13)

// reg_wr_ctrl_0
#define REG_FW_IOMUX_PIN_CTRL_REG0_WR_SEC (1 << 1)
#define REG_FW_IOMUX_PIN_CTRL_REG1_WR_SEC (1 << 2)
#define REG_FW_IOMUX_PIN_CTRL_REG2_WR_SEC (1 << 3)
#define REG_FW_IOMUX_PIN_CTRL_REG3_WR_SEC (1 << 4)
#define REG_FW_IOMUX_PIN_CTRL_REG4_WR_SEC (1 << 5)
#define REG_FW_IOMUX_PIN_CTRL_REG5_WR_SEC (1 << 6)
#define REG_FW_IOMUX_RFDIG_GPIO_7_WR_SEC (1 << 7)
#define REG_FW_IOMUX_RFDIG_GPIO_6_WR_SEC (1 << 8)
#define REG_FW_IOMUX_RFDIG_GPIO_5_WR_SEC (1 << 9)
#define REG_FW_IOMUX_RFDIG_GPIO_4_WR_SEC (1 << 10)
#define REG_FW_IOMUX_RFDIG_GPIO_3_WR_SEC (1 << 11)
#define REG_FW_IOMUX_RFDIG_GPIO_2_WR_SEC (1 << 12)
#define REG_FW_IOMUX_RFDIG_GPIO_1_WR_SEC (1 << 13)
#define REG_FW_IOMUX_RFDIG_GPIO_0_WR_SEC (1 << 14)
#define REG_FW_IOMUX_KEYIN_4_WR_SEC (1 << 15)
#define REG_FW_IOMUX_KEYOUT_5_WR_SEC (1 << 16)
#define REG_FW_IOMUX_KEYIN_5_WR_SEC (1 << 17)
#define REG_FW_IOMUX_KEYOUT_4_WR_SEC (1 << 18)
#define REG_FW_IOMUX_UART_1_RTS_WR_SEC (1 << 19)
#define REG_FW_IOMUX_UART_1_TXD_WR_SEC (1 << 20)
#define REG_FW_IOMUX_UART_1_RXD_WR_SEC (1 << 21)
#define REG_FW_IOMUX_UART_1_CTS_WR_SEC (1 << 22)
#define REG_FW_IOMUX_GPIO_0_WR_SEC (1 << 23)
#define REG_FW_IOMUX_GPIO_3_WR_SEC (1 << 24)
#define REG_FW_IOMUX_GPIO_2_WR_SEC (1 << 25)
#define REG_FW_IOMUX_GPIO_1_WR_SEC (1 << 26)
#define REG_FW_IOMUX_GPIO_7_WR_SEC (1 << 27)
#define REG_FW_IOMUX_GPIO_6_WR_SEC (1 << 28)
#define REG_FW_IOMUX_GPIO_5_WR_SEC (1 << 29)
#define REG_FW_IOMUX_GPIO_4_WR_SEC (1 << 30)
#define REG_FW_IOMUX_ADI_SDA_WR_SEC (1 << 31)

// reg_wr_ctrl_1
#define REG_FW_IOMUX_ADI_SCL_WR_SEC (1 << 0)
#define REG_FW_IOMUX_RESETB_WR_SEC (1 << 1)
#define REG_FW_IOMUX_OSC_32K_WR_SEC (1 << 2)
#define REG_FW_IOMUX_PMIC_EXT_INT_WR_SEC (1 << 3)
#define REG_FW_IOMUX_CHIP_PD_WR_SEC (1 << 4)
#define REG_FW_IOMUX_PTEST_WR_SEC (1 << 5)
#define REG_FW_IOMUX_CLK26M_PMIC_WR_SEC (1 << 6)
#define REG_FW_IOMUX_SIM_1_RST_WR_SEC (1 << 7)
#define REG_FW_IOMUX_SIM_1_DIO_WR_SEC (1 << 8)
#define REG_FW_IOMUX_SIM_1_CLK_WR_SEC (1 << 9)
#define REG_FW_IOMUX_SIM_0_RST_WR_SEC (1 << 10)
#define REG_FW_IOMUX_SIM_0_DIO_WR_SEC (1 << 11)
#define REG_FW_IOMUX_SIM_0_CLK_WR_SEC (1 << 12)
#define REG_FW_IOMUX_SW_CLK_WR_SEC (1 << 13)
#define REG_FW_IOMUX_SW_DIO_WR_SEC (1 << 14)
#define REG_FW_IOMUX_DEBUG_HOST_TX_WR_SEC (1 << 15)
#define REG_FW_IOMUX_DEBUG_HOST_RX_WR_SEC (1 << 16)
#define REG_FW_IOMUX_DEBUG_HOST_CLK_WR_SEC (1 << 17)
#define REG_FW_IOMUX_CAMERA_RST_L_WR_SEC (1 << 18)
#define REG_FW_IOMUX_SPI_CAMERA_SCK_WR_SEC (1 << 19)
#define REG_FW_IOMUX_SPI_CAMERA_SI_1_WR_SEC (1 << 20)
#define REG_FW_IOMUX_SPI_CAMERA_SI_0_WR_SEC (1 << 21)
#define REG_FW_IOMUX_CAMERA_REF_CLK_WR_SEC (1 << 22)
#define REG_FW_IOMUX_CAMERA_PWDN_WR_SEC (1 << 23)
#define REG_FW_IOMUX_I2S_SDAT_I_WR_SEC (1 << 24)
#define REG_FW_IOMUX_I2S1_SDAT_O_WR_SEC (1 << 25)
#define REG_FW_IOMUX_I2S1_LRCK_WR_SEC (1 << 26)
#define REG_FW_IOMUX_I2S1_BCK_WR_SEC (1 << 27)
#define REG_FW_IOMUX_I2S1_MCLK_WR_SEC (1 << 28)
#define REG_FW_IOMUX_I2C_M2_SCL_WR_SEC (1 << 29)
#define REG_FW_IOMUX_I2C_M2_SDA_WR_SEC (1 << 30)
#define REG_FW_IOMUX_NAND_SEL_WR_SEC (1 << 31)

// reg_wr_ctrl_2
#define REG_FW_IOMUX_KEYOUT_3_WR_SEC (1 << 0)
#define REG_FW_IOMUX_KEYOUT_2_WR_SEC (1 << 1)
#define REG_FW_IOMUX_KEYOUT_1_WR_SEC (1 << 2)
#define REG_FW_IOMUX_KEYOUT_0_WR_SEC (1 << 3)
#define REG_FW_IOMUX_KEYIN_3_WR_SEC (1 << 4)
#define REG_FW_IOMUX_KEYIN_2_WR_SEC (1 << 5)
#define REG_FW_IOMUX_KEYIN_1_WR_SEC (1 << 6)
#define REG_FW_IOMUX_KEYIN_0_WR_SEC (1 << 7)
#define REG_FW_IOMUX_LCD_RSTB_WR_SEC (1 << 8)
#define REG_FW_IOMUX_LCD_FMARK_WR_SEC (1 << 9)
#define REG_FW_IOMUX_SPI_LCD_SELECT_WR_SEC (1 << 10)
#define REG_FW_IOMUX_SPI_LCD_CS_WR_SEC (1 << 11)
#define REG_FW_IOMUX_SPI_LCD_CLK_WR_SEC (1 << 12)
#define REG_FW_IOMUX_SPI_LCD_SDC_WR_SEC (1 << 13)
#define REG_FW_IOMUX_SPI_LCD_SIO_WR_SEC (1 << 14)
#define REG_FW_IOMUX_SDMMC1_RST_WR_SEC (1 << 15)
#define REG_FW_IOMUX_SDMMC1_DATA_7_WR_SEC (1 << 16)
#define REG_FW_IOMUX_SDMMC1_DATA_6_WR_SEC (1 << 17)
#define REG_FW_IOMUX_SDMMC1_DATA_5_WR_SEC (1 << 18)
#define REG_FW_IOMUX_SDMMC1_DATA_4_WR_SEC (1 << 19)
#define REG_FW_IOMUX_SDMMC1_DATA_3_WR_SEC (1 << 20)
#define REG_FW_IOMUX_SDMMC1_DATA_2_WR_SEC (1 << 21)
#define REG_FW_IOMUX_SDMMC1_DATA_1_WR_SEC (1 << 22)
#define REG_FW_IOMUX_SDMMC1_DATA_0_WR_SEC (1 << 23)
#define REG_FW_IOMUX_SDMMC1_CMD_WR_SEC (1 << 24)
#define REG_FW_IOMUX_SDMMC1_CLK_WR_SEC (1 << 25)
#define REG_FW_IOMUX_UART_2_RTS_WR_SEC (1 << 26)
#define REG_FW_IOMUX_UART_2_CTS_WR_SEC (1 << 27)
#define REG_FW_IOMUX_UART_2_TXD_WR_SEC (1 << 28)
#define REG_FW_IOMUX_UART_2_RXD_WR_SEC (1 << 29)
#define REG_FW_IOMUX_I2C_M1_SDA_WR_SEC (1 << 30)
#define REG_FW_IOMUX_I2C_M1_SCL_WR_SEC (1 << 31)

// reg_wr_ctrl_3
#define REG_FW_IOMUX_GPIO_23_WR_SEC (1 << 0)
#define REG_FW_IOMUX_GPIO_22_WR_SEC (1 << 1)
#define REG_FW_IOMUX_GPIO_21_WR_SEC (1 << 2)
#define REG_FW_IOMUX_GPIO_20_WR_SEC (1 << 3)
#define REG_FW_IOMUX_GPIO_19_WR_SEC (1 << 4)
#define REG_FW_IOMUX_GPIO_18_WR_SEC (1 << 5)
#define REG_FW_IOMUX_GPIO_17_WR_SEC (1 << 6)
#define REG_FW_IOMUX_GPIO_16_WR_SEC (1 << 7)
#define REG_FW_IOMUX_M_SPI_D_3_WR_SEC (1 << 8)
#define REG_FW_IOMUX_M_SPI_D_2_WR_SEC (1 << 9)
#define REG_FW_IOMUX_M_SPI_D_1_WR_SEC (1 << 10)
#define REG_FW_IOMUX_M_SPI_D_0_WR_SEC (1 << 11)
#define REG_FW_IOMUX_M_SPI_CS_WR_SEC (1 << 12)
#define REG_FW_IOMUX_M_SPI_CLK_WR_SEC (1 << 13)

// bit_ctrl_addr_array0
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY0(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array1
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY1(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array2
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY2(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array3
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY3(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array4
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY4(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array5
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY5(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array6
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY6(n) (((n)&0x3fff) << 0)

// bit_ctrl_addr_array7
#define REG_FW_IOMUX_BIT_CTRL_ADDR_ARRAY7(n) (((n)&0x3fff) << 0)

#endif // _REG_FW_IOMUX_H_
