/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA").
 * All rights reserved.
 *
 * This software is supplied "AS IS" without any warranties.
 * RDA assumes no responsibility or liability for the use of the software,
 * conveys no license or title under any patent, copyright, or mask work
 * right to the product. RDA reserves the right to make changes in the
 * software without notification.  RDA also make no representation or
 * warranty that such application will be suitable for the specified use
 * without further testing or modification.
 */

#ifndef _DLFFT_H_
#define _DLFFT_H_

// Auto generated by dtools(see dtools.txt for its version).
// Don't edit it manually!

#define REG_DLFFT_BASE (0x18a00000)

typedef volatile struct
{
    uint32_t dlfft_frame_config_next; // 0x00000000
    uint32_t cat1_rs_ctrl_next;       // 0x00000004
    uint32_t cat1_csi_para_next;      // 0x00000008
    uint32_t cat1_agc_next;           // 0x0000000c
    uint32_t cat1_dlfft_ctrl_next;    // 0x00000010
    uint32_t cat1_sys_config_next;    // 0x00000014
    uint32_t cat1_fft_gate_next;      // 0x00000018
    uint32_t catm_nb_sys_config_next; // 0x0000001c
    uint32_t catm_nb_rs_config_next;  // 0x00000020
    uint32_t catm_nb_nbw_next;        // 0x00000024
    uint32_t catm_agc_next;           // 0x00000028
    uint32_t abis_config_next;        // 0x0000002c
    uint32_t delay_next1;             // 0x00000030
    uint32_t delay_next2;             // 0x00000034
    uint32_t pb_next;                 // 0x00000038
    uint32_t noise_delta_next;        // 0x0000003c
    uint32_t noise_agc_next;          // 0x00000040
    uint32_t dlfft_mode_next;         // 0x00000044
    uint32_t fft_lnum_next;           // 0x00000048
    uint32_t dlfft_frame_config_curr; // 0x0000004c
    uint32_t cat1_rs_ctrl_curr;       // 0x00000050
    uint32_t cat1_csi_para_curr;      // 0x00000054
    uint32_t cat1_agc_curr;           // 0x00000058
    uint32_t cat1_dlfft_ctrl_curr;    // 0x0000005c
    uint32_t cat1_sys_config_curr;    // 0x00000060
    uint32_t cat1_fft_gate_curr;      // 0x00000064
    uint32_t catm_nb_sys_config_curr; // 0x00000068
    uint32_t catm_nb_rs_config_curr;  // 0x0000006c
    uint32_t catm_nb_nbw_curr;        // 0x00000070
    uint32_t catm_agc_curr;           // 0x00000074
    uint32_t abis_config_curr;        // 0x00000078
    uint32_t delay_curr1;             // 0x0000007c
    uint32_t delay_curr2;             // 0x00000080
    uint32_t pb_curr;                 // 0x00000084
    uint32_t noise_delta_curr;        // 0x00000088
    uint32_t noise_agc_curr;          // 0x0000008c
    uint32_t dlfft_mode_curr;         // 0x00000090
    uint32_t fft_lnum_curr;           // 0x00000094
    uint32_t dlfft_inten;             // 0x00000098
    uint32_t catm_nb_fft_gate;        // 0x0000009c
    uint32_t dlfft_start;             // 0x000000a0
    uint32_t dlfft_intf;              // 0x000000a4
    uint32_t ofdm_count;              // 0x000000a8
    uint32_t master_card;             // 0x000000ac
    uint32_t llr_out1;                // 0x000000b0
    uint32_t llr_out2;                // 0x000000b4
    uint32_t llr_out3;                // 0x000000b8
    uint32_t crs_pow_max1;            // 0x000000bc
    uint32_t crs_pow_agc1;            // 0x000000c0
    uint32_t crs_pow_max2;            // 0x000000c4
    uint32_t crs_pow_agc2;            // 0x000000c8
    uint32_t crs_pow_max3;            // 0x000000cc
    uint32_t crs_pow_agc3;            // 0x000000d0
    uint32_t crs_pow_max4;            // 0x000000d4
    uint32_t crs_pow_agc4;            // 0x000000d8
    uint32_t crs_pow_max5;            // 0x000000dc
    uint32_t crs_pow_agc5;            // 0x000000e0
    uint32_t fsm_state;               // 0x000000e4
    uint32_t txrx_norm_gene1;         // 0x000000e8
    uint32_t txrx_norm_gene2;         // 0x000000ec
    uint32_t txrx_soft_offset;        // 0x000000f0
    uint32_t ofdm_assert;             // 0x000000f4
    uint32_t fsm_state_assert;        // 0x000000f8
    uint32_t abis_real_time_flag;     // 0x000000fc
} HWP_DLFFT_T;

#define hwp_dlfft ((HWP_DLFFT_T *)REG_ACCESS_ADDRESS(REG_DLFFT_BASE))

// dlfft_frame_config_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sub_frame_num_next : 4;  // [3:0]
        uint32_t sys_frame_num_next : 10; // [13:4]
        uint32_t master_card_next : 1;    // [14]
        uint32_t fft_dma_inten_next : 1;  // [15]
        uint32_t dlfft_only_en_next : 1;  // [16]
        uint32_t fft_norm_en_next : 1;    // [17]
        uint32_t fft_norm_sel_next : 1;   // [18]
        uint32_t crs_pow_ofdm0_next : 1;  // [19]
        uint32_t __31_20 : 12;            // [31:20]
    } b;
} REG_DLFFT_DLFFT_FRAME_CONFIG_NEXT_T;

// cat1_rs_ctrl_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t uers_en_next : 1;            // [0]
        uint32_t cellrs_en_next : 1;          // [1]
        uint32_t ueport_sel_next : 1;         // [2]
        uint32_t cellport_sel_next : 2;       // [4:3]
        uint32_t cp_sel_next : 1;             // [5]
        uint32_t cellid_next : 9;             // [14:6]
        uint32_t mbms_en_next : 1;            // [15]
        uint32_t mbms_mode_sel_next : 2;      // [17:16]
        uint32_t cat1_crs_pow_ofdm0_next : 1; // [18]
        uint32_t crs_pow_index_next : 3;      // [21:19]
        uint32_t __31_22 : 10;                // [31:22]
    } b;
} REG_DLFFT_CAT1_RS_CTRL_NEXT_T;

// cat1_csi_para_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_ofdm0_next : 4;   // [3:0]
        uint32_t csirs_ofdm1_next : 4;   // [7:4]
        uint32_t csirs_bitmap_next : 12; // [19:8]
        uint32_t __31_20 : 12;           // [31:20]
    } b;
} REG_DLFFT_CAT1_CSI_PARA_NEXT_T;

// cat1_agc_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t agc0_next : 10; // [9:0]
        uint32_t agc1_next : 10; // [19:10]
        uint32_t __31_20 : 12;   // [31:20]
    } b;
} REG_DLFFT_CAT1_AGC_NEXT_T;

// cat1_dlfft_ctrl_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_en_next : 1; // [0]
        uint32_t pbch_en_next : 1;  // [1]
        uint32_t __31_2 : 30;       // [31:2]
    } b;
} REG_DLFFT_CAT1_DLFFT_CTRL_NEXT_T;

// cat1_sys_config_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t s_frame_config : 4; // [3:0]
        uint32_t mode_sel_next : 1;  // [4]
        uint32_t up_down_config : 3; // [7:5]
        uint32_t prb_index_next : 3; // [10:8]
        uint32_t __31_11 : 21;       // [31:11]
    } b;
} REG_DLFFT_CAT1_SYS_CONFIG_NEXT_T;

// cat1_fft_gate_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_gate_next : 13; // [12:0]
        uint32_t __31_13 : 19;       // [31:13]
    } b;
} REG_DLFFT_CAT1_FFT_GATE_NEXT_T;

// catm_nb_sys_config_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t s_frame_config_next : 4; // [3:0]
        uint32_t mode_sel_next : 1;       // [4]
        uint32_t up_down_config_next : 3; // [7:5]
        uint32_t cp_sel_next : 1;         // [8]
        uint32_t prb_index_next : 3;      // [11:9]
        uint32_t __31_12 : 20;            // [31:12]
    } b;
} REG_DLFFT_CATM_NB_SYS_CONFIG_NEXT_T;

// catm_nb_rs_config_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;              // [0]
        uint32_t rsport_sel_next : 2;    // [2:1]
        uint32_t id_value_next : 9;      // [11:3]
        uint32_t crs_nrs_sel_next : 1;   // [12]
        uint32_t crs_pow_index_next : 3; // [15:13]
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_DLFFT_CATM_NB_RS_CONFIG_NEXT_T;

// catm_nb_nbw_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t nbw_cover_zero_sel_next : 1; // [0]
        uint32_t __31_1 : 31;                 // [31:1]
    } b;
} REG_DLFFT_CATM_NB_NBW_NEXT_T;

// catm_agc_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t catm_agc_next : 10; // [9:0]
        uint32_t __31_10 : 22;       // [31:10]
    } b;
} REG_DLFFT_CATM_AGC_NEXT_T;

// abis_config_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cellid_neibour_next1 : 9; // [8:0]
        uint32_t cellid_neibour_next2 : 9; // [17:9]
        uint32_t nrb_neibour_next1 : 3;    // [20:18]
        uint32_t nrb_neibour_next2 : 3;    // [23:21]
        uint32_t txnum_neibour_next1 : 2;  // [25:24]
        uint32_t txnum_neibour_next2 : 2;  // [27:26]
        uint32_t num_neibour_next : 2;     // [29:28]
        uint32_t ctcg_sel_next : 1;        // [30]
        uint32_t frame_intra_sel_next : 1; // [31]
    } b;
} REG_DLFFT_ABIS_CONFIG_NEXT_T;

// delay_next1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t delay_next1 : 19; // [18:0]
        uint32_t __31_19 : 13;     // [31:19]
    } b;
} REG_DLFFT_DELAY_NEXT1_T;

// delay_next2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t delay_next2 : 19; // [18:0]
        uint32_t __31_19 : 13;     // [31:19]
    } b;
} REG_DLFFT_DELAY_NEXT2_T;

// pb_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pb_next : 2;                    // [1:0]
        uint32_t __3_2 : 2;                      // [3:2]
        uint32_t abis_start_ofdm_next : 4;       // [7:4]
        uint32_t abis_llr_shift_modify_next : 5; // [12:8]
        uint32_t __31_13 : 19;                   // [31:13]
    } b;
} REG_DLFFT_PB_NEXT_T;

// noise_agc_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_agc_next : 10; // [9:0]
        uint32_t __31_10 : 22;        // [31:10]
    } b;
} REG_DLFFT_NOISE_AGC_NEXT_T;

// dlfft_mode_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlfft_mode_sel_next : 2; // [1:0]
        uint32_t soft_irt_en_next : 1;    // [2]
        uint32_t crs_pow_clr_next : 1;    // [3]
        uint32_t dlfft_info_next : 10;    // [13:4]
        uint32_t dlfft_info_sel_next : 1; // [14]
        uint32_t __31_15 : 17;            // [31:15]
    } b;
} REG_DLFFT_DLFFT_MODE_NEXT_T;

// fft_lnum_next
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_lnum1_next : 2;  // [1:0]
        uint32_t fft_lnum2_next : 2;  // [3:2]
        uint32_t fft_lnum3_next : 2;  // [5:4]
        uint32_t fft_lnum4_next : 2;  // [7:6]
        uint32_t fft_lnum5_next : 2;  // [9:8]
        uint32_t fft_lnum6_next : 2;  // [11:10]
        uint32_t fft_lnum7_next : 2;  // [13:12]
        uint32_t fft_lnum8_next : 2;  // [15:14]
        uint32_t fft_lnum9_next : 2;  // [17:16]
        uint32_t fft_lnum10_next : 2; // [19:18]
        uint32_t fft_lnum11_next : 2; // [21:20]
        uint32_t __31_22 : 10;        // [31:22]
    } b;
} REG_DLFFT_FFT_LNUM_NEXT_T;

// dlfft_frame_config_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t sub_frame_num_curr : 4;  // [3:0], read only
        uint32_t sys_frame_num_curr : 10; // [13:4], read only
        uint32_t master_card_curr : 1;    // [14], read only
        uint32_t fft_dma_inten_curr : 1;  // [15], read only
        uint32_t dlfft_only_en_curr : 1;  // [16], read only
        uint32_t fft_norm_en_curr : 1;    // [17], read only
        uint32_t fft_norm_sel_curr : 1;   // [18], read only
        uint32_t crs_pow_ofdm0_curr : 1;  // [19], read only
        uint32_t __31_20 : 12;            // [31:20]
    } b;
} REG_DLFFT_DLFFT_FRAME_CONFIG_CURR_T;

// cat1_rs_ctrl_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t uers_en_curr : 1;       // [0], read only
        uint32_t cellrs_en_curr : 1;     // [1], read only
        uint32_t ueport_sel_curr : 1;    // [2], read only
        uint32_t cellport_sel_curr : 2;  // [4:3], read only
        uint32_t cp_sel_curr : 1;        // [5], read only
        uint32_t cellid_curr : 9;        // [14:6], read only
        uint32_t mbms_en_curr : 1;       // [15], read only
        uint32_t mbms_mode_sel_curr : 2; // [17:16], read only
        uint32_t crs_pow_ofdm0_curr : 1; // [18], read only
        uint32_t crs_pow_index_curr : 3; // [21:19], read only
        uint32_t __31_22 : 10;           // [31:22]
    } b;
} REG_DLFFT_CAT1_RS_CTRL_CURR_T;

// cat1_csi_para_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_ofdm0_curr : 4;   // [3:0], read only
        uint32_t csirs_ofdm1_curr : 4;   // [7:4], read only
        uint32_t csirs_bitmap_curr : 12; // [19:8], read only
        uint32_t __31_20 : 12;           // [31:20]
    } b;
} REG_DLFFT_CAT1_CSI_PARA_CURR_T;

// cat1_agc_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t agc0_curr : 10; // [9:0], read only
        uint32_t agc1_curr : 10; // [19:10], read only
        uint32_t __31_20 : 12;   // [31:20]
    } b;
} REG_DLFFT_CAT1_AGC_CURR_T;

// cat1_dlfft_ctrl_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t csirs_en_curr : 1; // [0], read only
        uint32_t pbch_en_curr : 1;  // [1], read only
        uint32_t __31_2 : 30;       // [31:2]
    } b;
} REG_DLFFT_CAT1_DLFFT_CTRL_CURR_T;

// cat1_sys_config_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t s_frame_config : 4; // [3:0], read only
        uint32_t mode_sel_curr : 1;  // [4], read only
        uint32_t up_down_config : 3; // [7:5], read only
        uint32_t prb_index_curr : 3; // [10:8], read only
        uint32_t __31_11 : 21;       // [31:11]
    } b;
} REG_DLFFT_CAT1_SYS_CONFIG_CURR_T;

// cat1_fft_gate_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_gate_curr : 13; // [12:0], read only
        uint32_t __31_13 : 19;       // [31:13]
    } b;
} REG_DLFFT_CAT1_FFT_GATE_CURR_T;

// catm_nb_sys_config_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t s_frame_config_curr : 4; // [3:0], read only
        uint32_t mode_sel_curr : 1;       // [4], read only
        uint32_t up_down_config_curr : 3; // [7:5], read only
        uint32_t cp_sel_curr : 1;         // [8], read only
        uint32_t prb_index_curr : 3;      // [11:9], read only
        uint32_t __31_12 : 20;            // [31:12]
    } b;
} REG_DLFFT_CATM_NB_SYS_CONFIG_CURR_T;

// catm_nb_rs_config_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t __0_0 : 1;              // [0]
        uint32_t rsport_sel_curr : 2;    // [2:1], read only
        uint32_t id_value_curr : 9;      // [11:3], read only
        uint32_t crs_nrs_sel_curr : 1;   // [12], read only
        uint32_t crs_pow_index_curr : 3; // [15:13], read only
        uint32_t __31_16 : 16;           // [31:16]
    } b;
} REG_DLFFT_CATM_NB_RS_CONFIG_CURR_T;

// catm_nb_nbw_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t nbw_cover_zero_sel_curr : 1; // [0], read only
        uint32_t __31_1 : 31;                 // [31:1]
    } b;
} REG_DLFFT_CATM_NB_NBW_CURR_T;

// catm_agc_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t catm_agc_curr : 10; // [9:0], read only
        uint32_t __31_10 : 22;       // [31:10]
    } b;
} REG_DLFFT_CATM_AGC_CURR_T;

// abis_config_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cellid_neibour_curr1 : 9; // [8:0], read only
        uint32_t cellid_neibour_curr2 : 9; // [17:9], read only
        uint32_t nrb_neibour_curr1 : 3;    // [20:18], read only
        uint32_t nrb_neibour_curr2 : 3;    // [23:21], read only
        uint32_t txnum_neibour_curr1 : 2;  // [25:24], read only
        uint32_t txnum_neibour_curr2 : 2;  // [27:26], read only
        uint32_t num_neibour_curr : 2;     // [29:28], read only
        uint32_t ctcg_sel_curr : 1;        // [30], read only
        uint32_t frame_intra_sel_curr : 1; // [31], read only
    } b;
} REG_DLFFT_ABIS_CONFIG_CURR_T;

// delay_curr1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t delay_curr1 : 19; // [18:0], read only
        uint32_t __31_19 : 13;     // [31:19]
    } b;
} REG_DLFFT_DELAY_CURR1_T;

// delay_curr2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t delay_curr2 : 19; // [18:0], read only
        uint32_t __31_19 : 13;     // [31:19]
    } b;
} REG_DLFFT_DELAY_CURR2_T;

// pb_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t pb_curr : 2;                    // [1:0], read only
        uint32_t __3_2 : 2;                      // [3:2]
        uint32_t abis_start_ofdm_curr : 4;       // [7:4], read only
        uint32_t abis_llr_shift_modify_curr : 5; // [12:8], read only
        uint32_t __31_13 : 19;                   // [31:13]
    } b;
} REG_DLFFT_PB_CURR_T;

// noise_agc_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t noise_agc_curr : 10; // [9:0], read only
        uint32_t __31_10 : 22;        // [31:10]
    } b;
} REG_DLFFT_NOISE_AGC_CURR_T;

// dlfft_mode_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t dlfft_mode_sel_curr : 2; // [1:0], read only
        uint32_t soft_irt_en_curr : 1;    // [2], read only
        uint32_t crs_pow_clr_curr : 1;    // [3], read only
        uint32_t dlfft_info_curr : 10;    // [13:4], read only
        uint32_t dlfft_info_sel_curr : 1; // [14], read only
        uint32_t __31_15 : 17;            // [31:15]
    } b;
} REG_DLFFT_DLFFT_MODE_CURR_T;

// fft_lnum_curr
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_lnum1_curr : 2;  // [1:0], read only
        uint32_t fft_lnum2_curr : 2;  // [3:2], read only
        uint32_t fft_lnum3_curr : 2;  // [5:4], read only
        uint32_t fft_lnum4_curr : 2;  // [7:6], read only
        uint32_t fft_lnum5_curr : 2;  // [9:8], read only
        uint32_t fft_lnum6_curr : 2;  // [11:10], read only
        uint32_t fft_lnum7_curr : 2;  // [13:12], read only
        uint32_t fft_lnum8_curr : 2;  // [15:14], read only
        uint32_t fft_lnum9_curr : 2;  // [17:16], read only
        uint32_t fft_lnum10_curr : 2; // [19:18], read only
        uint32_t fft_lnum11_curr : 2; // [21:20], read only
        uint32_t __31_22 : 10;        // [31:22]
    } b;
} REG_DLFFT_FFT_LNUM_CURR_T;

// dlfft_inten
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_dma_inten : 1;          // [0]
        uint32_t fft_core_inten : 1;         // [1]
        uint32_t fft_err_inten : 1;          // [2]
        uint32_t axi_dma_inten : 1;          // [3]
        uint32_t rf_over_inten : 1;          // [4]
        uint32_t rf_short_inten : 1;         // [5]
        uint32_t rf_abnormal_down_inten : 1; // [6]
        uint32_t rf_abnormal_up_inten : 1;   // [7]
        uint32_t rf_nodata_inten : 1;        // [8]
        uint32_t rxcapt_err_inten : 1;       // [9]
        uint32_t iddet_err_inten : 1;        // [10]
        uint32_t spare2_err_inten : 1;       // [11]
        uint32_t spare3_err_inten : 1;       // [12]
        uint32_t __31_13 : 19;               // [31:13]
    } b;
} REG_DLFFT_DLFFT_INTEN_T;

// catm_nb_fft_gate
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_gate : 13; // [12:0]
        uint32_t __31_13 : 19;  // [31:13]
    } b;
} REG_DLFFT_CATM_NB_FFT_GATE_T;

// dlfft_start
typedef union {
    uint32_t v;
    struct
    {
        uint32_t cat1_dlfft_start : 1;    // [0]
        uint32_t catm_nb_dlfft_start : 1; // [1]
        uint32_t __31_2 : 30;             // [31:2]
    } b;
} REG_DLFFT_DLFFT_START_T;

// dlfft_intf
typedef union {
    uint32_t v;
    struct
    {
        uint32_t fft_dma_intf : 1;          // [0], write clear
        uint32_t fft_core_intf : 1;         // [1], write clear
        uint32_t txrx_rd_errf : 1;          // [2], write clear
        uint32_t ldtc_wr_errf : 1;          // [3], write clear
        uint32_t mmse_wr_errf : 1;          // [4], write clear
        uint32_t csi_wr_errf : 1;           // [5], write clear
        uint32_t axi_dma_intf : 1;          // [6], write clear
        uint32_t rf_over_errf : 1;          // [7], write clear
        uint32_t rf_short_errf : 1;         // [8], write clear
        uint32_t rf_abnormal_down_errf : 1; // [9], write clear
        uint32_t rf_abnormal_up_errf : 1;   // [10], write clear
        uint32_t coeff2ldtc1_errf : 1;      // [11], write clear
        uint32_t coeff2ldtc_errf : 1;       // [12], write clear
        uint32_t sd_rd_errf : 1;            // [13], write clear
        uint32_t rf_nodata_errf : 1;        // [14], write clear
        uint32_t measpwr_debug_errf : 1;    // [15], write clear
        uint32_t rxcapt_errf : 1;           // [16], write clear
        uint32_t iddet_errf : 1;            // [17], write clear
        uint32_t spare2_errf : 1;           // [18], write clear
        uint32_t spare3_errf : 1;           // [19], write clear
        uint32_t __31_20 : 12;              // [31:20]
    } b;
} REG_DLFFT_DLFFT_INTF_T;

// ofdm_count
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ofdm_count : 4; // [3:0], read only
        uint32_t __31_4 : 28;    // [31:4]
    } b;
} REG_DLFFT_OFDM_COUNT_T;

// master_card
typedef union {
    uint32_t v;
    struct
    {
        uint32_t master_card_out : 1;  // [0], read only
        uint32_t dlfft_info_out1 : 10; // [10:1], read only
        uint32_t dlfft_info_out2 : 10; // [20:11], read only
        uint32_t __31_21 : 11;         // [31:21]
    } b;
} REG_DLFFT_MASTER_CARD_T;

// llr_out1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t llr_out1 : 4; // [3:0], read only
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_DLFFT_LLR_OUT1_T;

// llr_out2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t llr_out2 : 4; // [3:0], read only
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_DLFFT_LLR_OUT2_T;

// llr_out3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t llr_out3 : 4; // [3:0], read only
        uint32_t __31_4 : 28;  // [31:4]
    } b;
} REG_DLFFT_LLR_OUT3_T;

// crs_pow_agc1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t crs_pow_agc1 : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_DLFFT_CRS_POW_AGC1_T;

// crs_pow_agc2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t crs_pow_agc2 : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_DLFFT_CRS_POW_AGC2_T;

// crs_pow_agc3
typedef union {
    uint32_t v;
    struct
    {
        uint32_t crs_pow_agc3 : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_DLFFT_CRS_POW_AGC3_T;

// crs_pow_agc4
typedef union {
    uint32_t v;
    struct
    {
        uint32_t crs_pow_agc4 : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_DLFFT_CRS_POW_AGC4_T;

// crs_pow_agc5
typedef union {
    uint32_t v;
    struct
    {
        uint32_t crs_pow_agc5 : 10; // [9:0], read only
        uint32_t __31_10 : 22;      // [31:10]
    } b;
} REG_DLFFT_CRS_POW_AGC5_T;

// txrx_norm_gene1
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ofdm0_norm_gene : 4; // [3:0], read only
        uint32_t ofdm1_norm_gene : 4; // [7:4], read only
        uint32_t ofdm2_norm_gene : 4; // [11:8], read only
        uint32_t ofdm3_norm_gene : 4; // [15:12], read only
        uint32_t ofdm4_norm_gene : 4; // [19:16], read only
        uint32_t ofdm5_norm_gene : 4; // [23:20], read only
        uint32_t ofdm6_norm_gene : 4; // [27:24], read only
        uint32_t ofdm7_norm_gene : 4; // [31:28], read only
    } b;
} REG_DLFFT_TXRX_NORM_GENE1_T;

// txrx_norm_gene2
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ofdm8_norm_gene : 4;  // [3:0], read only
        uint32_t ofdm9_norm_gene : 4;  // [7:4], read only
        uint32_t ofdm10_norm_gene : 4; // [11:8], read only
        uint32_t ofdm11_norm_gene : 4; // [15:12], read only
        uint32_t ofdm12_norm_gene : 4; // [19:16], read only
        uint32_t ofdm13_norm_gene : 4; // [23:20], read only
        uint32_t __31_24 : 8;          // [31:24]
    } b;
} REG_DLFFT_TXRX_NORM_GENE2_T;

// txrx_soft_offset
typedef union {
    uint32_t v;
    struct
    {
        uint32_t txrx_soft_offset0 : 5; // [4:0], read only
        uint32_t txrx_soft_offset1 : 5; // [9:5], read only
        uint32_t __31_10 : 22;          // [31:10]
    } b;
} REG_DLFFT_TXRX_SOFT_OFFSET_T;

// ofdm_assert
typedef union {
    uint32_t v;
    struct
    {
        uint32_t ofdm_assert : 4;        // [3:0], read only
        uint32_t txrx_enable_assert : 1; // [4], read only
        uint32_t __31_5 : 27;            // [31:5]
    } b;
} REG_DLFFT_OFDM_ASSERT_T;

// abis_real_time_flag
typedef union {
    uint32_t v;
    struct
    {
        uint32_t abis_real_time_flag1 : 1; // [0], read only
        uint32_t abis_real_time_flag2 : 1; // [1], read only
        uint32_t abis_real_time_flag3 : 1; // [2], read only
        uint32_t __31_3 : 29;              // [31:3]
    } b;
} REG_DLFFT_ABIS_REAL_TIME_FLAG_T;

// dlfft_frame_config_next
#define DLFFT_SUB_FRAME_NUM_NEXT(n) (((n)&0xf) << 0)
#define DLFFT_SYS_FRAME_NUM_NEXT(n) (((n)&0x3ff) << 4)
#define DLFFT_MASTER_CARD_NEXT (1 << 14)
#define DLFFT_FFT_DMA_INTEN_NEXT (1 << 15)
#define DLFFT_DLFFT_ONLY_EN_NEXT (1 << 16)
#define DLFFT_FFT_NORM_EN_NEXT (1 << 17)
#define DLFFT_FFT_NORM_SEL_NEXT (1 << 18)
#define DLFFT_CRS_POW_OFDM0_NEXT (1 << 19)

// cat1_rs_ctrl_next
#define DLFFT_UERS_EN_NEXT (1 << 0)
#define DLFFT_CELLRS_EN_NEXT (1 << 1)
#define DLFFT_UEPORT_SEL_NEXT (1 << 2)
#define DLFFT_CELLPORT_SEL_NEXT(n) (((n)&0x3) << 3)
#define DLFFT_CAT1_RS_CTRL_NEXT_CP_SEL_NEXT (1 << 5)
#define DLFFT_CELLID_NEXT(n) (((n)&0x1ff) << 6)
#define DLFFT_MBMS_EN_NEXT (1 << 15)
#define DLFFT_MBMS_MODE_SEL_NEXT(n) (((n)&0x3) << 16)
#define DLFFT_CAT1_CRS_POW_OFDM0_NEXT (1 << 18)
#define DLFFT_CAT1_RS_CTRL_NEXT_CRS_POW_INDEX_NEXT(n) (((n)&0x7) << 19)

// cat1_csi_para_next
#define DLFFT_CSIRS_OFDM0_NEXT(n) (((n)&0xf) << 0)
#define DLFFT_CSIRS_OFDM1_NEXT(n) (((n)&0xf) << 4)
#define DLFFT_CSIRS_BITMAP_NEXT(n) (((n)&0xfff) << 8)

// cat1_agc_next
#define DLFFT_AGC0_NEXT(n) (((n)&0x3ff) << 0)
#define DLFFT_AGC1_NEXT(n) (((n)&0x3ff) << 10)

// cat1_dlfft_ctrl_next
#define DLFFT_CSIRS_EN_NEXT (1 << 0)
#define DLFFT_PBCH_EN_NEXT (1 << 1)

// cat1_sys_config_next
#define DLFFT_S_FRAME_CONFIG(n) (((n)&0xf) << 0)
#define DLFFT_MODE_SEL_NEXT (1 << 4)
#define DLFFT_UP_DOWN_CONFIG(n) (((n)&0x7) << 5)
#define DLFFT_CAT1_SYS_CONFIG_NEXT_PRB_INDEX_NEXT(n) (((n)&0x7) << 8)

// cat1_fft_gate_next
#define DLFFT_FFT_GATE_NEXT(n) (((n)&0x1fff) << 0)

// catm_nb_sys_config_next
#define DLFFT_S_FRAME_CONFIG_NEXT(n) (((n)&0xf) << 0)
#define DLFFT_MODE_SEL_NEXT (1 << 4)
#define DLFFT_UP_DOWN_CONFIG_NEXT(n) (((n)&0x7) << 5)
#define DLFFT_CATM_NB_SYS_CONFIG_NEXT_CP_SEL_NEXT (1 << 8)
#define DLFFT_CATM_NB_SYS_CONFIG_NEXT_PRB_INDEX_NEXT(n) (((n)&0x7) << 9)

// catm_nb_rs_config_next
#define DLFFT_RSPORT_SEL_NEXT(n) (((n)&0x3) << 1)
#define DLFFT_ID_VALUE_NEXT(n) (((n)&0x1ff) << 3)
#define DLFFT_CRS_NRS_SEL_NEXT (1 << 12)
#define DLFFT_CATM_NB_RS_CONFIG_NEXT_CRS_POW_INDEX_NEXT(n) (((n)&0x7) << 13)

// catm_nb_nbw_next
#define DLFFT_NBW_COVER_ZERO_SEL_NEXT (1 << 0)

// catm_agc_next
#define DLFFT_CATM_AGC_NEXT(n) (((n)&0x3ff) << 0)

// abis_config_next
#define DLFFT_CELLID_NEIBOUR_NEXT1(n) (((n)&0x1ff) << 0)
#define DLFFT_CELLID_NEIBOUR_NEXT2(n) (((n)&0x1ff) << 9)
#define DLFFT_NRB_NEIBOUR_NEXT1(n) (((n)&0x7) << 18)
#define DLFFT_NRB_NEIBOUR_NEXT2(n) (((n)&0x7) << 21)
#define DLFFT_TXNUM_NEIBOUR_NEXT1(n) (((n)&0x3) << 24)
#define DLFFT_TXNUM_NEIBOUR_NEXT2(n) (((n)&0x3) << 26)
#define DLFFT_NUM_NEIBOUR_NEXT(n) (((n)&0x3) << 28)
#define DLFFT_CTCG_SEL_NEXT (1 << 30)
#define DLFFT_FRAME_INTRA_SEL_NEXT (1 << 31)

// delay_next1
#define DLFFT_DELAY_NEXT1(n) (((n)&0x7ffff) << 0)

// delay_next2
#define DLFFT_DELAY_NEXT2(n) (((n)&0x7ffff) << 0)

// pb_next
#define DLFFT_PB_NEXT(n) (((n)&0x3) << 0)
#define DLFFT_ABIS_START_OFDM_NEXT(n) (((n)&0xf) << 4)
#define DLFFT_ABIS_LLR_SHIFT_MODIFY_NEXT(n) (((n)&0x1f) << 8)

// noise_agc_next
#define DLFFT_NOISE_AGC_NEXT(n) (((n)&0x3ff) << 0)

// dlfft_mode_next
#define DLFFT_DLFFT_MODE_SEL_NEXT(n) (((n)&0x3) << 0)
#define DLFFT_SOFT_IRT_EN_NEXT (1 << 2)
#define DLFFT_CRS_POW_CLR_NEXT (1 << 3)
#define DLFFT_DLFFT_INFO_NEXT(n) (((n)&0x3ff) << 4)
#define DLFFT_DLFFT_INFO_SEL_NEXT (1 << 14)

// fft_lnum_next
#define DLFFT_FFT_LNUM1_NEXT(n) (((n)&0x3) << 0)
#define DLFFT_FFT_LNUM2_NEXT(n) (((n)&0x3) << 2)
#define DLFFT_FFT_LNUM3_NEXT(n) (((n)&0x3) << 4)
#define DLFFT_FFT_LNUM4_NEXT(n) (((n)&0x3) << 6)
#define DLFFT_FFT_LNUM5_NEXT(n) (((n)&0x3) << 8)
#define DLFFT_FFT_LNUM6_NEXT(n) (((n)&0x3) << 10)
#define DLFFT_FFT_LNUM7_NEXT(n) (((n)&0x3) << 12)
#define DLFFT_FFT_LNUM8_NEXT(n) (((n)&0x3) << 14)
#define DLFFT_FFT_LNUM9_NEXT(n) (((n)&0x3) << 16)
#define DLFFT_FFT_LNUM10_NEXT(n) (((n)&0x3) << 18)
#define DLFFT_FFT_LNUM11_NEXT(n) (((n)&0x3) << 20)

// dlfft_frame_config_curr
#define DLFFT_SUB_FRAME_NUM_CURR(n) (((n)&0xf) << 0)
#define DLFFT_SYS_FRAME_NUM_CURR(n) (((n)&0x3ff) << 4)
#define DLFFT_MASTER_CARD_CURR (1 << 14)
#define DLFFT_FFT_DMA_INTEN_CURR (1 << 15)
#define DLFFT_DLFFT_ONLY_EN_CURR (1 << 16)
#define DLFFT_FFT_NORM_EN_CURR (1 << 17)
#define DLFFT_FFT_NORM_SEL_CURR (1 << 18)
#define DLFFT_DLFFT_FRAME_CONFIG_CURR_CRS_POW_OFDM0_CURR (1 << 19)

// cat1_rs_ctrl_curr
#define DLFFT_UERS_EN_CURR (1 << 0)
#define DLFFT_CELLRS_EN_CURR (1 << 1)
#define DLFFT_UEPORT_SEL_CURR (1 << 2)
#define DLFFT_CELLPORT_SEL_CURR(n) (((n)&0x3) << 3)
#define DLFFT_CAT1_RS_CTRL_CURR_CP_SEL_CURR (1 << 5)
#define DLFFT_CELLID_CURR(n) (((n)&0x1ff) << 6)
#define DLFFT_MBMS_EN_CURR (1 << 15)
#define DLFFT_MBMS_MODE_SEL_CURR(n) (((n)&0x3) << 16)
#define DLFFT_CAT1_RS_CTRL_CURR_CRS_POW_OFDM0_CURR (1 << 18)
#define DLFFT_CAT1_RS_CTRL_CURR_CRS_POW_INDEX_CURR(n) (((n)&0x7) << 19)

// cat1_csi_para_curr
#define DLFFT_CSIRS_OFDM0_CURR(n) (((n)&0xf) << 0)
#define DLFFT_CSIRS_OFDM1_CURR(n) (((n)&0xf) << 4)
#define DLFFT_CSIRS_BITMAP_CURR(n) (((n)&0xfff) << 8)

// cat1_agc_curr
#define DLFFT_AGC0_CURR(n) (((n)&0x3ff) << 0)
#define DLFFT_AGC1_CURR(n) (((n)&0x3ff) << 10)

// cat1_dlfft_ctrl_curr
#define DLFFT_CSIRS_EN_CURR (1 << 0)
#define DLFFT_PBCH_EN_CURR (1 << 1)

// cat1_sys_config_curr
#define DLFFT_S_FRAME_CONFIG(n) (((n)&0xf) << 0)
#define DLFFT_MODE_SEL_CURR (1 << 4)
#define DLFFT_UP_DOWN_CONFIG(n) (((n)&0x7) << 5)
#define DLFFT_CAT1_SYS_CONFIG_CURR_PRB_INDEX_CURR(n) (((n)&0x7) << 8)

// cat1_fft_gate_curr
#define DLFFT_FFT_GATE_CURR(n) (((n)&0x1fff) << 0)

// catm_nb_sys_config_curr
#define DLFFT_S_FRAME_CONFIG_CURR(n) (((n)&0xf) << 0)
#define DLFFT_MODE_SEL_CURR (1 << 4)
#define DLFFT_UP_DOWN_CONFIG_CURR(n) (((n)&0x7) << 5)
#define DLFFT_CATM_NB_SYS_CONFIG_CURR_CP_SEL_CURR (1 << 8)
#define DLFFT_CATM_NB_SYS_CONFIG_CURR_PRB_INDEX_CURR(n) (((n)&0x7) << 9)

// catm_nb_rs_config_curr
#define DLFFT_RSPORT_SEL_CURR(n) (((n)&0x3) << 1)
#define DLFFT_ID_VALUE_CURR(n) (((n)&0x1ff) << 3)
#define DLFFT_CRS_NRS_SEL_CURR (1 << 12)
#define DLFFT_CATM_NB_RS_CONFIG_CURR_CRS_POW_INDEX_CURR(n) (((n)&0x7) << 13)

// catm_nb_nbw_curr
#define DLFFT_NBW_COVER_ZERO_SEL_CURR (1 << 0)

// catm_agc_curr
#define DLFFT_CATM_AGC_CURR(n) (((n)&0x3ff) << 0)

// abis_config_curr
#define DLFFT_CELLID_NEIBOUR_CURR1(n) (((n)&0x1ff) << 0)
#define DLFFT_CELLID_NEIBOUR_CURR2(n) (((n)&0x1ff) << 9)
#define DLFFT_NRB_NEIBOUR_CURR1(n) (((n)&0x7) << 18)
#define DLFFT_NRB_NEIBOUR_CURR2(n) (((n)&0x7) << 21)
#define DLFFT_TXNUM_NEIBOUR_CURR1(n) (((n)&0x3) << 24)
#define DLFFT_TXNUM_NEIBOUR_CURR2(n) (((n)&0x3) << 26)
#define DLFFT_NUM_NEIBOUR_CURR(n) (((n)&0x3) << 28)
#define DLFFT_CTCG_SEL_CURR (1 << 30)
#define DLFFT_FRAME_INTRA_SEL_CURR (1 << 31)

// delay_curr1
#define DLFFT_DELAY_CURR1(n) (((n)&0x7ffff) << 0)

// delay_curr2
#define DLFFT_DELAY_CURR2(n) (((n)&0x7ffff) << 0)

// pb_curr
#define DLFFT_PB_CURR(n) (((n)&0x3) << 0)
#define DLFFT_ABIS_START_OFDM_CURR(n) (((n)&0xf) << 4)
#define DLFFT_ABIS_LLR_SHIFT_MODIFY_CURR(n) (((n)&0x1f) << 8)

// noise_agc_curr
#define DLFFT_NOISE_AGC_CURR(n) (((n)&0x3ff) << 0)

// dlfft_mode_curr
#define DLFFT_DLFFT_MODE_SEL_CURR(n) (((n)&0x3) << 0)
#define DLFFT_SOFT_IRT_EN_CURR (1 << 2)
#define DLFFT_CRS_POW_CLR_CURR (1 << 3)
#define DLFFT_DLFFT_INFO_CURR(n) (((n)&0x3ff) << 4)
#define DLFFT_DLFFT_INFO_SEL_CURR (1 << 14)

// fft_lnum_curr
#define DLFFT_FFT_LNUM1_CURR(n) (((n)&0x3) << 0)
#define DLFFT_FFT_LNUM2_CURR(n) (((n)&0x3) << 2)
#define DLFFT_FFT_LNUM3_CURR(n) (((n)&0x3) << 4)
#define DLFFT_FFT_LNUM4_CURR(n) (((n)&0x3) << 6)
#define DLFFT_FFT_LNUM5_CURR(n) (((n)&0x3) << 8)
#define DLFFT_FFT_LNUM6_CURR(n) (((n)&0x3) << 10)
#define DLFFT_FFT_LNUM7_CURR(n) (((n)&0x3) << 12)
#define DLFFT_FFT_LNUM8_CURR(n) (((n)&0x3) << 14)
#define DLFFT_FFT_LNUM9_CURR(n) (((n)&0x3) << 16)
#define DLFFT_FFT_LNUM10_CURR(n) (((n)&0x3) << 18)
#define DLFFT_FFT_LNUM11_CURR(n) (((n)&0x3) << 20)

// dlfft_inten
#define DLFFT_FFT_DMA_INTEN (1 << 0)
#define DLFFT_FFT_CORE_INTEN (1 << 1)
#define DLFFT_FFT_ERR_INTEN (1 << 2)
#define DLFFT_AXI_DMA_INTEN (1 << 3)
#define DLFFT_RF_OVER_INTEN (1 << 4)
#define DLFFT_RF_SHORT_INTEN (1 << 5)
#define DLFFT_RF_ABNORMAL_DOWN_INTEN (1 << 6)
#define DLFFT_RF_ABNORMAL_UP_INTEN (1 << 7)
#define DLFFT_RF_NODATA_INTEN (1 << 8)
#define DLFFT_RXCAPT_ERR_INTEN (1 << 9)
#define DLFFT_IDDET_ERR_INTEN (1 << 10)
#define DLFFT_SPARE2_ERR_INTEN (1 << 11)
#define DLFFT_SPARE3_ERR_INTEN (1 << 12)

// catm_nb_fft_gate
#define DLFFT_FFT_GATE(n) (((n)&0x1fff) << 0)

// dlfft_start
#define DLFFT_CAT1_DLFFT_START (1 << 0)
#define DLFFT_CATM_NB_DLFFT_START (1 << 1)

// dlfft_intf
#define DLFFT_FFT_DMA_INTF (1 << 0)
#define DLFFT_FFT_CORE_INTF (1 << 1)
#define DLFFT_TXRX_RD_ERRF (1 << 2)
#define DLFFT_LDTC_WR_ERRF (1 << 3)
#define DLFFT_MMSE_WR_ERRF (1 << 4)
#define DLFFT_CSI_WR_ERRF (1 << 5)
#define DLFFT_AXI_DMA_INTF (1 << 6)
#define DLFFT_RF_OVER_ERRF (1 << 7)
#define DLFFT_RF_SHORT_ERRF (1 << 8)
#define DLFFT_RF_ABNORMAL_DOWN_ERRF (1 << 9)
#define DLFFT_RF_ABNORMAL_UP_ERRF (1 << 10)
#define DLFFT_COEFF2LDTC1_ERRF (1 << 11)
#define DLFFT_COEFF2LDTC_ERRF (1 << 12)
#define DLFFT_SD_RD_ERRF (1 << 13)
#define DLFFT_RF_NODATA_ERRF (1 << 14)
#define DLFFT_MEASPWR_DEBUG_ERRF (1 << 15)
#define DLFFT_RXCAPT_ERRF (1 << 16)
#define DLFFT_IDDET_ERRF (1 << 17)
#define DLFFT_SPARE2_ERRF (1 << 18)
#define DLFFT_SPARE3_ERRF (1 << 19)

// ofdm_count
#define DLFFT_OFDM_COUNT(n) (((n)&0xf) << 0)

// master_card
#define DLFFT_MASTER_CARD_OUT (1 << 0)
#define DLFFT_DLFFT_INFO_OUT1(n) (((n)&0x3ff) << 1)
#define DLFFT_DLFFT_INFO_OUT2(n) (((n)&0x3ff) << 11)

// llr_out1
#define DLFFT_LLR_OUT1(n) (((n)&0xf) << 0)

// llr_out2
#define DLFFT_LLR_OUT2(n) (((n)&0xf) << 0)

// llr_out3
#define DLFFT_LLR_OUT3(n) (((n)&0xf) << 0)

// crs_pow_agc1
#define DLFFT_CRS_POW_AGC1(n) (((n)&0x3ff) << 0)

// crs_pow_agc2
#define DLFFT_CRS_POW_AGC2(n) (((n)&0x3ff) << 0)

// crs_pow_agc3
#define DLFFT_CRS_POW_AGC3(n) (((n)&0x3ff) << 0)

// crs_pow_agc4
#define DLFFT_CRS_POW_AGC4(n) (((n)&0x3ff) << 0)

// crs_pow_agc5
#define DLFFT_CRS_POW_AGC5(n) (((n)&0x3ff) << 0)

// txrx_norm_gene1
#define DLFFT_OFDM0_NORM_GENE(n) (((n)&0xf) << 0)
#define DLFFT_OFDM1_NORM_GENE(n) (((n)&0xf) << 4)
#define DLFFT_OFDM2_NORM_GENE(n) (((n)&0xf) << 8)
#define DLFFT_OFDM3_NORM_GENE(n) (((n)&0xf) << 12)
#define DLFFT_OFDM4_NORM_GENE(n) (((n)&0xf) << 16)
#define DLFFT_OFDM5_NORM_GENE(n) (((n)&0xf) << 20)
#define DLFFT_OFDM6_NORM_GENE(n) (((n)&0xf) << 24)
#define DLFFT_OFDM7_NORM_GENE(n) (((n)&0xf) << 28)

// txrx_norm_gene2
#define DLFFT_OFDM8_NORM_GENE(n) (((n)&0xf) << 0)
#define DLFFT_OFDM9_NORM_GENE(n) (((n)&0xf) << 4)
#define DLFFT_OFDM10_NORM_GENE(n) (((n)&0xf) << 8)
#define DLFFT_OFDM11_NORM_GENE(n) (((n)&0xf) << 12)
#define DLFFT_OFDM12_NORM_GENE(n) (((n)&0xf) << 16)
#define DLFFT_OFDM13_NORM_GENE(n) (((n)&0xf) << 20)

// txrx_soft_offset
#define DLFFT_TXRX_SOFT_OFFSET0(n) (((n)&0x1f) << 0)
#define DLFFT_TXRX_SOFT_OFFSET1(n) (((n)&0x1f) << 5)

// ofdm_assert
#define DLFFT_OFDM_ASSERT(n) (((n)&0xf) << 0)
#define DLFFT_TXRX_ENABLE_ASSERT (1 << 4)

// abis_real_time_flag
#define DLFFT_ABIS_REAL_TIME_FLAG1 (1 << 0)
#define DLFFT_ABIS_REAL_TIME_FLAG2 (1 << 1)
#define DLFFT_ABIS_REAL_TIME_FLAG3 (1 << 2)

#endif // _DLFFT_H_
