/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _TXRX_H_ #define _TXRX_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_TXRX_BASE (0x18000000) typedef volatile struct { uint32_t int_flag; // 0x00000000 uint32_t int_mask; // 0x00000004 uint32_t int_flag_ofdm_rx; // 0x00000008 uint32_t int_mask_ofdm_rx; // 0x0000000c uint32_t sys_cfg; // 0x00000010 uint32_t stop_cfg; // 0x00000014 uint32_t __24[2]; // 0x00000018 uint32_t rx_cfg; // 0x00000020 uint32_t rx_1st_ofdm_len_offset; // 0x00000024 uint32_t rx_afc_factor; // 0x00000028 uint32_t rx_rssi_max_cfg; // 0x0000002c uint32_t rx_norm_cfg; // 0x00000030 uint32_t rx_sat_val; // 0x00000034 uint32_t rx_pre_cfg; // 0x00000038 uint32_t rx_aux_cfg; // 0x0000003c uint32_t rx_phy_factor; // 0x00000040 uint32_t rx_dc_cfg; // 0x00000044 uint32_t rx_gain1_cfg; // 0x00000048 uint32_t rx_gain2_cfg; // 0x0000004c uint32_t rx_out_cfg; // 0x00000050 uint32_t __84[3]; // 0x00000054 uint32_t tx_cfg; // 0x00000060 uint32_t tx_1st_ofdm_len_offset; // 0x00000064 uint32_t tx_ofdm0_len; // 0x00000068 uint32_t tx_ofdm1_len; // 0x0000006c uint32_t tx_post_cfg; // 0x00000070 uint32_t tx_fill0_num; // 0x00000074 uint32_t __120[2]; // 0x00000078 uint32_t rx_phy_factor_cur; // 0x00000080 uint32_t rx_sat_cnt; // 0x00000084 uint32_t rx_norm_data; // 0x00000088 uint32_t rssi_max1; // 0x0000008c uint32_t rssi_max2; // 0x00000090 uint32_t rssi_max3; // 0x00000094 uint32_t rssi_max4; // 0x00000098 uint32_t rssi_max5; // 0x0000009c uint32_t rx_dc_cal_value; // 0x000000a0 uint32_t __164[7]; // 0x000000a4 uint32_t rx_ofdm_stat; // 0x000000c0 uint32_t tx_fifo_stat; // 0x000000c4 uint32_t rx_err_stat; // 0x000000c8 uint32_t tx_err_stat; // 0x000000cc uint32_t st_cnt_framc; // 0x000000d0 uint32_t st_cnt__add; // 0x000000d4 uint32_t ad_on_time; // 0x000000d8 uint32_t da_on_time; // 0x000000dc uint32_t fftbuf1_time; // 0x000000e0 uint32_t fftbuf2_time; // 0x000000e4 uint32_t fft2ldtc_time; // 0x000000e8 uint32_t tx_fir3_coe1_cfg; // 0x000000ec uint32_t tx_fir3_coe2_cfg; // 0x000000f0 uint32_t tx_fir3_coe3_cfg; // 0x000000f4 uint32_t tx_fir3_cfg; // 0x000000f8 uint32_t tx_vld_cnt_cfg; // 0x000000fc uint32_t __256[23488]; // 0x00000100 uint32_t mem5; // 0x00017000 uint32_t __94212[1024]; // 0x00017004 uint32_t mem3; // 0x00018004 uint32_t __98312[4095]; // 0x00018008 uint32_t mem4; // 0x0001c004 } HWP_TXRX_T; #define hwp_txrx ((HWP_TXRX_T *)REG_ACCESS_ADDRESS(REG_TXRX_BASE)) // int_flag typedef union { uint32_t v; struct { uint32_t rx_ofdm : 1; // [0], write clear uint32_t rx_fin : 1; // [1], write clear uint32_t tx_ofdm : 1; // [2], write clear uint32_t tx_fin : 1; // [3], write clear uint32_t rx_trace_fin : 1; // [4], write clear uint32_t tx_trace_fin : 1; // [5], write clear uint32_t __31_6 : 26; // [31:6] } b; } REG_TXRX_INT_FLAG_T; // int_mask typedef union { uint32_t v; struct { uint32_t rx_ofdm_mask : 1; // [0] uint32_t rx_finish_mask : 1; // [1] uint32_t tx_ofdm_mask : 1; // [2] uint32_t tx_finish_mask : 1; // [3] uint32_t rx_trace_fin : 1; // [4] uint32_t tx_trace_fin : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_TXRX_INT_MASK_T; // int_flag_ofdm_rx typedef union { uint32_t v; struct { uint32_t rx_ofdm_int_0 : 1; // [0], write clear uint32_t rx_ofdm_int_1 : 1; // [1], write clear uint32_t rx_ofdm_int_2 : 1; // [2], write clear uint32_t rx_ofdm_int_3 : 1; // [3], write clear uint32_t rx_ofdm_int_4 : 1; // [4], write clear uint32_t rx_ofdm_int_5 : 1; // [5], write clear uint32_t rx_ofdm_int_6 : 1; // [6], write clear uint32_t rx_ofdm_int_7 : 1; // [7], write clear uint32_t rx_ofdm_int_8 : 1; // [8], write clear uint32_t rx_ofdm_int_9 : 1; // [9], write clear uint32_t rx_ofdm_int_10 : 1; // [10], write clear uint32_t rx_ofdm_int_11 : 1; // [11], write clear uint32_t rx_ofdm_int_12 : 1; // [12], write clear uint32_t rx_ofdm_int_13 : 1; // [13], write clear uint32_t rx_ofdm_int_14 : 1; // [14], write clear uint32_t __31_15 : 17; // [31:15] } b; } REG_TXRX_INT_FLAG_OFDM_RX_T; // int_mask_ofdm_rx typedef union { uint32_t v; struct { uint32_t rx_int_en0 : 1; // [0] uint32_t rx_int_en1 : 1; // [1] uint32_t rx_int_en2 : 1; // [2] uint32_t rx_int_en3 : 1; // [3] uint32_t rx_int_en4 : 1; // [4] uint32_t rx_int_en5 : 1; // [5] uint32_t rx_int_en6 : 1; // [6] uint32_t rx_int_en7 : 1; // [7] uint32_t rx_int_en8 : 1; // [8] uint32_t rx_int_en9 : 1; // [9] uint32_t rx_int_en10 : 1; // [10] uint32_t rx_int_en11 : 1; // [11] uint32_t rx_int_en12 : 1; // [12] uint32_t rx_int_en13 : 1; // [13] uint32_t rx_int_en14 : 1; // [14] uint32_t rx_last_int_en : 1; // [15] uint32_t rx_inten : 1; // [16] uint32_t __31_17 : 15; // [31:17] } b; } REG_TXRX_INT_MASK_OFDM_RX_T; // sys_cfg typedef union { uint32_t v; struct { uint32_t cat1_en : 1; // [0] uint32_t tx_nb_en : 1; // [1] uint32_t tx_dfe_en : 1; // [2] uint32_t tx_ovt : 1; // [3] uint32_t rx_ovt : 1; // [4] uint32_t rx_dcoc_sel : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_TXRX_SYS_CFG_T; // stop_cfg typedef union { uint32_t v; struct { uint32_t rx_stop_en : 1; // [0] uint32_t tx_stop_en : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_TXRX_STOP_CFG_T; // rx_cfg typedef union { uint32_t v; struct { uint32_t glb_rxen : 1; // [0] uint32_t rx_rssi_en : 1; // [1] uint32_t rx_sat_en : 1; // [2] uint32_t rx_ave_en : 1; // [3] uint32_t rx_norm_en : 1; // [4] uint32_t rx_meas_en : 1; // [5] uint32_t offset_zero_flag : 1; // [6] uint32_t rx_trace_en : 1; // [7] uint32_t hf_fir_bitsel : 4; // [11:8] uint32_t __15_12 : 4; // [15:12] uint32_t rx_cp_type : 2; // [17:16] uint32_t rx_dlfft_en : 1; // [18] uint32_t rx_iddet_en : 1; // [19] uint32_t __20_20 : 1; // [20] uint32_t offset_ctrl_flag : 1; // [21] uint32_t rx_otdoa_en : 1; // [22] uint32_t rx_hf_fir_en : 1; // [23] uint32_t __24_24 : 1; // [24] uint32_t rssi_save_sel : 3; // [27:25] uint32_t __29_28 : 2; // [29:28] uint32_t rx_rssi_cfg : 1; // [30] uint32_t rx_soft_afc_en : 1; // [31] } b; } REG_TXRX_RX_CFG_T; // rx_1st_ofdm_len_offset typedef union { uint32_t v; struct { uint32_t rx_ist_ofdm_len_offset : 10; // [9:0] uint32_t __31_10 : 22; // [31:10] } b; } REG_TXRX_RX_1ST_OFDM_LEN_OFFSET_T; // rx_afc_factor typedef union { uint32_t v; struct { uint32_t rx_afc_factor : 16; // [15:0] uint32_t rx_afc_update : 1; // [16] uint32_t __31_17 : 15; // [31:17] } b; } REG_TXRX_RX_AFC_FACTOR_T; // rx_rssi_max_cfg typedef union { uint32_t v; struct { uint32_t rssi_max_start : 4; // [3:0] uint32_t rssi_max_clear : 1; // [4] uint32_t next_en : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_TXRX_RX_RSSI_MAX_CFG_T; // rx_norm_cfg typedef union { uint32_t v; struct { uint32_t rx_norm_cfg : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_TXRX_RX_NORM_CFG_T; // rx_sat_val typedef union { uint32_t v; struct { uint32_t sat_val_min : 12; // [11:0] uint32_t __15_12 : 4; // [15:12] uint32_t sat_val_max : 12; // [27:16] uint32_t __31_28 : 4; // [31:28] } b; } REG_TXRX_RX_SAT_VAL_T; // rx_pre_cfg typedef union { uint32_t v; struct { uint32_t rx_bitsel : 5; // [4:0] uint32_t __5_5 : 1; // [5] uint32_t fir_en : 1; // [6] uint32_t freq_en : 1; // [7] uint32_t rx_bw_sel : 3; // [10:8] uint32_t __11_11 : 1; // [11] uint32_t rx_freq_factor : 11; // [22:12] uint32_t __31_23 : 9; // [31:23] } b; } REG_TXRX_RX_PRE_CFG_T; // rx_dc_cfg typedef union { uint32_t v; struct { uint32_t rx_dc_q : 12; // [11:0] uint32_t __15_12 : 4; // [15:12] uint32_t rx_dc_i : 12; // [27:16] uint32_t __30_28 : 3; // [30:28] uint32_t rx_dc_update : 1; // [31] } b; } REG_TXRX_RX_DC_CFG_T; // rx_gain1_cfg typedef union { uint32_t v; struct { uint32_t rx_gain1 : 10; // [9:0] uint32_t __15_10 : 6; // [15:10] uint32_t rx_gain1_en : 1; // [16] uint32_t __31_17 : 15; // [31:17] } b; } REG_TXRX_RX_GAIN1_CFG_T; // rx_gain2_cfg typedef union { uint32_t v; struct { uint32_t rx_gain2 : 10; // [9:0] uint32_t __15_10 : 6; // [15:10] uint32_t rx_gain2_en : 1; // [16] uint32_t __31_17 : 15; // [31:17] } b; } REG_TXRX_RX_GAIN2_CFG_T; // rx_out_cfg typedef union { uint32_t v; struct { uint32_t meas_dat_fin : 3; // [2:0] uint32_t __3_3 : 1; // [3] uint32_t meas_dat_start : 2; // [5:4] uint32_t __7_6 : 2; // [7:6] uint32_t otdoa_dat_fin : 3; // [10:8] uint32_t __11_11 : 1; // [11] uint32_t otdoa_dat_start : 2; // [13:12] uint32_t __15_14 : 2; // [15:14] uint32_t iddet_dat_fin : 3; // [18:16] uint32_t __19_19 : 1; // [19] uint32_t iddet_dat_start : 2; // [21:20] uint32_t __31_22 : 10; // [31:22] } b; } REG_TXRX_RX_OUT_CFG_T; // tx_cfg typedef union { uint32_t v; struct { uint32_t glb_txen : 1; // [0] uint32_t __1_1 : 1; // [1] uint32_t tx_cp_type : 1; // [2] uint32_t tx_data_drive : 1; // [3] uint32_t tx_loop : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_TXRX_TX_CFG_T; // tx_1st_ofdm_len_offset typedef union { uint32_t v; struct { uint32_t tx_1st_ofdm_len_offset : 7; // [6:0] uint32_t __31_7 : 25; // [31:7] } b; } REG_TXRX_TX_1ST_OFDM_LEN_OFFSET_T; // tx_ofdm0_len typedef union { uint32_t v; struct { uint32_t tx_ofdm0_len : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_TXRX_TX_OFDM0_LEN_T; // tx_ofdm1_len typedef union { uint32_t v; struct { uint32_t tx_ofdm1_len : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_TXRX_TX_OFDM1_LEN_T; // tx_post_cfg typedef union { uint32_t v; struct { uint32_t tx_bitsel : 5; // [4:0] uint32_t __6_5 : 2; // [6:5] uint32_t tx_freq_en : 1; // [7] uint32_t tx_bw_sel : 3; // [10:8] uint32_t tx_fir_en : 1; // [11], read only uint32_t tx_nb_start : 7; // [18:12], read only uint32_t __19_19 : 1; // [19] uint32_t prach_format : 3; // [22:20], read only uint32_t prach_en : 1; // [23], read only uint32_t __31_24 : 8; // [31:24] } b; } REG_TXRX_TX_POST_CFG_T; // tx_fill0_num typedef union { uint32_t v; struct { uint32_t tx_fill0_num : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_TXRX_TX_FILL0_NUM_T; // rx_norm_data typedef union { uint32_t v; struct { uint32_t rx_norm_data : 4; // [3:0], read only uint32_t __31_4 : 28; // [31:4] } b; } REG_TXRX_RX_NORM_DATA_T; // rx_dc_cal_value typedef union { uint32_t v; struct { uint32_t rx_dc_cal_value_q : 16; // [15:0], read only uint32_t rx_dc_cal_value_i : 16; // [31:16], read only } b; } REG_TXRX_RX_DC_CAL_VALUE_T; // rx_ofdm_stat typedef union { uint32_t v; struct { uint32_t rx_ofdm_stat : 4; // [3:0], read only uint32_t ping_pang_stat : 1; // [4], read only uint32_t __5_5 : 1; // [5] uint32_t rx_no_data_err : 1; // [6], read only uint32_t cp_err : 1; // [7], read only uint32_t rx_meas_en : 1; // [8], read only uint32_t rx_iddet_en : 1; // [9], read only uint32_t rx_otdoa_en : 1; // [10], read only uint32_t rx_dlfft_en : 1; // [11], read only uint32_t rx_running : 1; // [12], read only uint32_t ad_on : 1; // [13], read only uint32_t __15_14 : 2; // [15:14] uint32_t rx_mem_addr : 12; // [27:16], read only uint32_t __31_28 : 4; // [31:28] } b; } REG_TXRX_RX_OFDM_STAT_T; // tx_fifo_stat typedef union { uint32_t v; struct { uint32_t tx_ofdm_stat : 4; // [3:0], read only uint32_t tx_fifo_stat : 1; // [4], read only uint32_t __11_5 : 7; // [11:5] uint32_t tx_running : 1; // [12], read only uint32_t da_on : 1; // [13], read only uint32_t __15_14 : 2; // [15:14] uint32_t tx_mem_addr : 12; // [27:16], read only uint32_t __31_28 : 4; // [31:28] } b; } REG_TXRX_TX_FIFO_STAT_T; // rx_err_stat typedef union { uint32_t v; struct { uint32_t cp_type_rx : 2; // [1:0], read only uint32_t pingpang_flag : 1; // [2], read only uint32_t dlfft_mem_sel : 1; // [3], read only uint32_t rx_running : 1; // [4], read only uint32_t ad_on : 1; // [5], read only uint32_t __7_6 : 2; // [7:6] uint32_t ofdm_num_rx : 4; // [11:8], read only uint32_t ts_cnt : 16; // [27:12], read only uint32_t frame_num : 4; // [31:28], read only } b; } REG_TXRX_RX_ERR_STAT_T; // tx_err_stat typedef union { uint32_t v; struct { uint32_t pa_empty_err : 1; // [0], read only uint32_t pi_empty_err : 1; // [1], read only uint32_t dft_wr_pa_err : 1; // [2], read only uint32_t dft_wr_pi_err : 1; // [3], read only uint32_t ram_pi_sel : 1; // [4], read only uint32_t tx_running : 1; // [5], read only uint32_t da_on : 1; // [6], read only uint32_t __7_7 : 1; // [7] uint32_t ofdm_num_tx : 4; // [11:8], read only uint32_t ts_cnt : 16; // [27:12], read only uint32_t frame_num : 4; // [31:28], read only } b; } REG_TXRX_TX_ERR_STAT_T; // st_cnt_framc typedef union { uint32_t v; struct { uint32_t rf_1st_int_framc : 16; // [15:0], read only uint32_t adon_pos_framc : 16; // [31:16], read only } b; } REG_TXRX_ST_CNT_FRAMC_T; // st_cnt__add typedef union { uint32_t v; struct { uint32_t rf_int_sub_add : 16; // [15:0], read only uint32_t rf_int_num : 16; // [31:16], read only } b; } REG_TXRX_ST_CNT__ADD_T; // ad_on_time typedef union { uint32_t v; struct { uint32_t ad_on_pos_time0 : 8; // [7:0], read only uint32_t ad_on_neg_time0 : 8; // [15:8], read only uint32_t ad_on_pos_time1 : 8; // [23:16], read only uint32_t ad_on_neg_time1 : 8; // [31:24], read only } b; } REG_TXRX_AD_ON_TIME_T; // da_on_time typedef union { uint32_t v; struct { uint32_t da_on_pos_time0 : 8; // [7:0], read only uint32_t da_on_neg_time0 : 8; // [15:8], read only uint32_t da_on_pos_time1 : 8; // [23:16], read only uint32_t da_on_neg_time1 : 8; // [31:24], read only } b; } REG_TXRX_DA_ON_TIME_T; // fftbuf1_time typedef union { uint32_t v; struct { uint32_t fftbuf1_time1 : 8; // [7:0], read only uint32_t fftbuf1_time2 : 8; // [15:8], read only uint32_t fftbuf1_time3 : 8; // [23:16], read only uint32_t fftbuf1_time4 : 8; // [31:24], read only } b; } REG_TXRX_FFTBUF1_TIME_T; // fftbuf2_time typedef union { uint32_t v; struct { uint32_t fftbuf2_time1 : 8; // [7:0], read only uint32_t fftbuf2_time2 : 8; // [15:8], read only uint32_t fftbuf2_time3 : 8; // [23:16], read only uint32_t fftbuf2_time4 : 8; // [31:24], read only } b; } REG_TXRX_FFTBUF2_TIME_T; // fft2ldtc_time typedef union { uint32_t v; struct { uint32_t fft2ldtc_time1 : 8; // [7:0], read only uint32_t fft2ldtc_time2 : 8; // [15:8], read only uint32_t fft2ldtc_time3 : 8; // [23:16], read only uint32_t fft2ldtc_time4 : 8; // [31:24], read only } b; } REG_TXRX_FFT2LDTC_TIME_T; // tx_fir3_coe1_cfg typedef union { uint32_t v; struct { uint32_t tx_fir_coe_a0 : 12; // [11:0] uint32_t tx_fir_coe_a1 : 12; // [23:12] uint32_t tx_fir_coe_a21 : 8; // [31:24] } b; } REG_TXRX_TX_FIR3_COE1_CFG_T; // tx_fir3_coe2_cfg typedef union { uint32_t v; struct { uint32_t tx_fir_coe_a22 : 4; // [3:0] uint32_t tx_fir_coe_a3 : 12; // [15:4] uint32_t tx_fir_coe_a4 : 12; // [27:16] uint32_t tx_fir_coe_a51 : 4; // [31:28] } b; } REG_TXRX_TX_FIR3_COE2_CFG_T; // tx_fir3_coe3_cfg typedef union { uint32_t v; struct { uint32_t tx_fir_coe_a52 : 8; // [7:0] uint32_t tx_fir_coe_a6 : 12; // [19:8] uint32_t tx_fir_coe_a7 : 12; // [31:20] } b; } REG_TXRX_TX_FIR3_COE3_CFG_T; // tx_fir3_cfg typedef union { uint32_t v; struct { uint32_t fir3_en : 1; // [0] uint32_t autock_en : 1; // [1] uint32_t reg_grp_delay : 5; // [6:2] uint32_t reg_samp_rate : 6; // [12:7] uint32_t __31_13 : 19; // [31:13] } b; } REG_TXRX_TX_FIR3_CFG_T; // tx_vld_cnt_cfg typedef union { uint32_t v; struct { uint32_t tx_vld_cnt : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_TXRX_TX_VLD_CNT_CFG_T; // mem3 typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t mem3_2 : 12; // [15:4] uint32_t __19_16 : 4; // [19:16] uint32_t mem3_1 : 12; // [31:20] } b; } REG_TXRX_MEM3_T; // mem4 typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t mem4_2 : 12; // [15:4] uint32_t __19_16 : 4; // [19:16] uint32_t mem4_1 : 12; // [31:20] } b; } REG_TXRX_MEM4_T; // int_flag #define TXRX_RX_OFDM (1 << 0) #define TXRX_RX_FIN (1 << 1) #define TXRX_TX_OFDM (1 << 2) #define TXRX_TX_FIN (1 << 3) #define TXRX_RX_TRACE_FIN (1 << 4) #define TXRX_TX_TRACE_FIN (1 << 5) // int_mask #define TXRX_RX_OFDM_MASK (1 << 0) #define TXRX_RX_FINISH_MASK (1 << 1) #define TXRX_TX_OFDM_MASK (1 << 2) #define TXRX_TX_FINISH_MASK (1 << 3) #define TXRX_RX_TRACE_FIN (1 << 4) #define TXRX_TX_TRACE_FIN (1 << 5) // int_flag_ofdm_rx #define TXRX_RX_OFDM_INT_0 (1 << 0) #define TXRX_RX_OFDM_INT_1 (1 << 1) #define TXRX_RX_OFDM_INT_2 (1 << 2) #define TXRX_RX_OFDM_INT_3 (1 << 3) #define TXRX_RX_OFDM_INT_4 (1 << 4) #define TXRX_RX_OFDM_INT_5 (1 << 5) #define TXRX_RX_OFDM_INT_6 (1 << 6) #define TXRX_RX_OFDM_INT_7 (1 << 7) #define TXRX_RX_OFDM_INT_8 (1 << 8) #define TXRX_RX_OFDM_INT_9 (1 << 9) #define TXRX_RX_OFDM_INT_10 (1 << 10) #define TXRX_RX_OFDM_INT_11 (1 << 11) #define TXRX_RX_OFDM_INT_12 (1 << 12) #define TXRX_RX_OFDM_INT_13 (1 << 13) #define TXRX_RX_OFDM_INT_14 (1 << 14) // int_mask_ofdm_rx #define TXRX_RX_INT_EN0 (1 << 0) #define TXRX_RX_INT_EN1 (1 << 1) #define TXRX_RX_INT_EN2 (1 << 2) #define TXRX_RX_INT_EN3 (1 << 3) #define TXRX_RX_INT_EN4 (1 << 4) #define TXRX_RX_INT_EN5 (1 << 5) #define TXRX_RX_INT_EN6 (1 << 6) #define TXRX_RX_INT_EN7 (1 << 7) #define TXRX_RX_INT_EN8 (1 << 8) #define TXRX_RX_INT_EN9 (1 << 9) #define TXRX_RX_INT_EN10 (1 << 10) #define TXRX_RX_INT_EN11 (1 << 11) #define TXRX_RX_INT_EN12 (1 << 12) #define TXRX_RX_INT_EN13 (1 << 13) #define TXRX_RX_INT_EN14 (1 << 14) #define TXRX_RX_LAST_INT_EN (1 << 15) #define TXRX_RX_INTEN (1 << 16) // sys_cfg #define TXRX_CAT1_EN (1 << 0) #define TXRX_TX_NB_EN (1 << 1) #define TXRX_TX_DFE_EN (1 << 2) #define TXRX_TX_OVT (1 << 3) #define TXRX_RX_OVT (1 << 4) #define TXRX_RX_DCOC_SEL (1 << 5) // stop_cfg #define TXRX_RX_STOP_EN (1 << 0) #define TXRX_TX_STOP_EN (1 << 1) // rx_cfg #define TXRX_GLB_RXEN (1 << 0) #define TXRX_RX_RSSI_EN (1 << 1) #define TXRX_RX_SAT_EN (1 << 2) #define TXRX_RX_AVE_EN (1 << 3) #define TXRX_RX_NORM_EN (1 << 4) #define TXRX_RX_CFG_RX_MEAS_EN (1 << 5) #define TXRX_OFFSET_ZERO_FLAG (1 << 6) #define TXRX_RX_TRACE_EN (1 << 7) #define TXRX_HF_FIR_BITSEL(n) (((n)&0xf) << 8) #define TXRX_RX_CP_TYPE(n) (((n)&0x3) << 16) #define TXRX_RX_CFG_RX_DLFFT_EN (1 << 18) #define TXRX_RX_CFG_RX_IDDET_EN (1 << 19) #define TXRX_OFFSET_CTRL_FLAG (1 << 21) #define TXRX_RX_CFG_RX_OTDOA_EN (1 << 22) #define TXRX_RX_HF_FIR_EN (1 << 23) #define TXRX_RSSI_SAVE_SEL(n) (((n)&0x7) << 25) #define TXRX_RX_RSSI_CFG (1 << 30) #define TXRX_RX_SOFT_AFC_EN (1 << 31) // rx_1st_ofdm_len_offset #define TXRX_RX_IST_OFDM_LEN_OFFSET(n) (((n)&0x3ff) << 0) // rx_afc_factor #define TXRX_RX_AFC_FACTOR(n) (((n)&0xffff) << 0) #define TXRX_RX_AFC_UPDATE (1 << 16) // rx_rssi_max_cfg #define TXRX_RSSI_MAX_START(n) (((n)&0xf) << 0) #define TXRX_RSSI_MAX_CLEAR (1 << 4) #define TXRX_NEXT_EN (1 << 5) // rx_norm_cfg #define TXRX_RX_NORM_CFG(n) (((n)&0x7) << 0) // rx_sat_val #define TXRX_SAT_VAL_MIN(n) (((n)&0xfff) << 0) #define TXRX_SAT_VAL_MAX(n) (((n)&0xfff) << 16) // rx_pre_cfg #define TXRX_RX_BITSEL(n) (((n)&0x1f) << 0) #define TXRX_FIR_EN (1 << 6) #define TXRX_FREQ_EN (1 << 7) #define TXRX_RX_BW_SEL(n) (((n)&0x7) << 8) #define TXRX_RX_FREQ_FACTOR(n) (((n)&0x7ff) << 12) // rx_dc_cfg #define TXRX_RX_DC_Q(n) (((n)&0xfff) << 0) #define TXRX_RX_DC_I(n) (((n)&0xfff) << 16) #define TXRX_RX_DC_UPDATE (1 << 31) // rx_gain1_cfg #define TXRX_RX_GAIN1(n) (((n)&0x3ff) << 0) #define TXRX_RX_GAIN1_EN (1 << 16) // rx_gain2_cfg #define TXRX_RX_GAIN2(n) (((n)&0x3ff) << 0) #define TXRX_RX_GAIN2_EN (1 << 16) // rx_out_cfg #define TXRX_MEAS_DAT_FIN(n) (((n)&0x7) << 0) #define TXRX_MEAS_DAT_START(n) (((n)&0x3) << 4) #define TXRX_OTDOA_DAT_FIN(n) (((n)&0x7) << 8) #define TXRX_OTDOA_DAT_START(n) (((n)&0x3) << 12) #define TXRX_IDDET_DAT_FIN(n) (((n)&0x7) << 16) #define TXRX_IDDET_DAT_START(n) (((n)&0x3) << 20) // tx_cfg #define TXRX_GLB_TXEN (1 << 0) #define TXRX_TX_CP_TYPE (1 << 2) #define TXRX_TX_DATA_DRIVE (1 << 3) #define TXRX_TX_LOOP (1 << 4) // tx_1st_ofdm_len_offset #define TXRX_TX_1ST_OFDM_LEN_OFFSET(n) (((n)&0x7f) << 0) // tx_ofdm0_len #define TXRX_TX_OFDM0_LEN(n) (((n)&0xfff) << 0) // tx_ofdm1_len #define TXRX_TX_OFDM1_LEN(n) (((n)&0xfff) << 0) // tx_post_cfg #define TXRX_TX_BITSEL(n) (((n)&0x1f) << 0) #define TXRX_TX_FREQ_EN (1 << 7) #define TXRX_TX_BW_SEL(n) (((n)&0x7) << 8) #define TXRX_TX_FIR_EN (1 << 11) #define TXRX_TX_NB_START(n) (((n)&0x7f) << 12) #define TXRX_PRACH_FORMAT(n) (((n)&0x7) << 20) #define TXRX_PRACH_EN (1 << 23) // tx_fill0_num #define TXRX_TX_FILL0_NUM(n) (((n)&0xff) << 0) // rx_norm_data #define TXRX_RX_NORM_DATA(n) (((n)&0xf) << 0) // rx_dc_cal_value #define TXRX_RX_DC_CAL_VALUE_Q(n) (((n)&0xffff) << 0) #define TXRX_RX_DC_CAL_VALUE_I(n) (((n)&0xffff) << 16) // rx_ofdm_stat #define TXRX_RX_OFDM_STAT(n) (((n)&0xf) << 0) #define TXRX_PING_PANG_STAT (1 << 4) #define TXRX_RX_NO_DATA_ERR (1 << 6) #define TXRX_CP_ERR (1 << 7) #define TXRX_RX_OFDM_STAT_RX_MEAS_EN (1 << 8) #define TXRX_RX_OFDM_STAT_RX_IDDET_EN (1 << 9) #define TXRX_RX_OFDM_STAT_RX_OTDOA_EN (1 << 10) #define TXRX_RX_OFDM_STAT_RX_DLFFT_EN (1 << 11) #define TXRX_RX_OFDM_STAT_RX_RUNNING (1 << 12) #define TXRX_RX_OFDM_STAT_AD_ON (1 << 13) #define TXRX_RX_MEM_ADDR(n) (((n)&0xfff) << 16) // tx_fifo_stat #define TXRX_TX_OFDM_STAT(n) (((n)&0xf) << 0) #define TXRX_TX_FIFO_STAT (1 << 4) #define TXRX_TX_FIFO_STAT_TX_RUNNING (1 << 12) #define TXRX_TX_FIFO_STAT_DA_ON (1 << 13) #define TXRX_TX_MEM_ADDR(n) (((n)&0xfff) << 16) // rx_err_stat #define TXRX_CP_TYPE_RX(n) (((n)&0x3) << 0) #define TXRX_PINGPANG_FLAG (1 << 2) #define TXRX_DLFFT_MEM_SEL (1 << 3) #define TXRX_RX_ERR_STAT_RX_RUNNING (1 << 4) #define TXRX_RX_ERR_STAT_AD_ON (1 << 5) #define TXRX_OFDM_NUM_RX(n) (((n)&0xf) << 8) #define TXRX_TS_CNT(n) (((n)&0xffff) << 12) #define TXRX_FRAME_NUM(n) (((n)&0xf) << 28) // tx_err_stat #define TXRX_PA_EMPTY_ERR (1 << 0) #define TXRX_PI_EMPTY_ERR (1 << 1) #define TXRX_DFT_WR_PA_ERR (1 << 2) #define TXRX_DFT_WR_PI_ERR (1 << 3) #define TXRX_RAM_PI_SEL (1 << 4) #define TXRX_TX_ERR_STAT_TX_RUNNING (1 << 5) #define TXRX_TX_ERR_STAT_DA_ON (1 << 6) #define TXRX_OFDM_NUM_TX(n) (((n)&0xf) << 8) #define TXRX_TS_CNT(n) (((n)&0xffff) << 12) #define TXRX_FRAME_NUM(n) (((n)&0xf) << 28) // st_cnt_framc #define TXRX_RF_1ST_INT_FRAMC(n) (((n)&0xffff) << 0) #define TXRX_ADON_POS_FRAMC(n) (((n)&0xffff) << 16) // st_cnt__add #define TXRX_RF_INT_SUB_ADD(n) (((n)&0xffff) << 0) #define TXRX_RF_INT_NUM(n) (((n)&0xffff) << 16) // ad_on_time #define TXRX_AD_ON_POS_TIME0(n) (((n)&0xff) << 0) #define TXRX_AD_ON_NEG_TIME0(n) (((n)&0xff) << 8) #define TXRX_AD_ON_POS_TIME1(n) (((n)&0xff) << 16) #define TXRX_AD_ON_NEG_TIME1(n) (((n)&0xff) << 24) // da_on_time #define TXRX_DA_ON_POS_TIME0(n) (((n)&0xff) << 0) #define TXRX_DA_ON_NEG_TIME0(n) (((n)&0xff) << 8) #define TXRX_DA_ON_POS_TIME1(n) (((n)&0xff) << 16) #define TXRX_DA_ON_NEG_TIME1(n) (((n)&0xff) << 24) // fftbuf1_time #define TXRX_FFTBUF1_TIME1(n) (((n)&0xff) << 0) #define TXRX_FFTBUF1_TIME2(n) (((n)&0xff) << 8) #define TXRX_FFTBUF1_TIME3(n) (((n)&0xff) << 16) #define TXRX_FFTBUF1_TIME4(n) (((n)&0xff) << 24) // fftbuf2_time #define TXRX_FFTBUF2_TIME1(n) (((n)&0xff) << 0) #define TXRX_FFTBUF2_TIME2(n) (((n)&0xff) << 8) #define TXRX_FFTBUF2_TIME3(n) (((n)&0xff) << 16) #define TXRX_FFTBUF2_TIME4(n) (((n)&0xff) << 24) // fft2ldtc_time #define TXRX_FFT2LDTC_TIME1(n) (((n)&0xff) << 0) #define TXRX_FFT2LDTC_TIME2(n) (((n)&0xff) << 8) #define TXRX_FFT2LDTC_TIME3(n) (((n)&0xff) << 16) #define TXRX_FFT2LDTC_TIME4(n) (((n)&0xff) << 24) // tx_fir3_coe1_cfg #define TXRX_TX_FIR_COE_A0(n) (((n)&0xfff) << 0) #define TXRX_TX_FIR_COE_A1(n) (((n)&0xfff) << 12) #define TXRX_TX_FIR_COE_A21(n) (((n)&0xff) << 24) // tx_fir3_coe2_cfg #define TXRX_TX_FIR_COE_A22(n) (((n)&0xf) << 0) #define TXRX_TX_FIR_COE_A3(n) (((n)&0xfff) << 4) #define TXRX_TX_FIR_COE_A4(n) (((n)&0xfff) << 16) #define TXRX_TX_FIR_COE_A51(n) (((n)&0xf) << 28) // tx_fir3_coe3_cfg #define TXRX_TX_FIR_COE_A52(n) (((n)&0xff) << 0) #define TXRX_TX_FIR_COE_A6(n) (((n)&0xfff) << 8) #define TXRX_TX_FIR_COE_A7(n) (((n)&0xfff) << 20) // tx_fir3_cfg #define TXRX_FIR3_EN (1 << 0) #define TXRX_AUTOCK_EN (1 << 1) #define TXRX_REG_GRP_DELAY(n) (((n)&0x1f) << 2) #define TXRX_REG_SAMP_RATE(n) (((n)&0x3f) << 7) // tx_vld_cnt_cfg #define TXRX_TX_VLD_CNT(n) (((n)&0x7) << 0) // mem3 #define TXRX_MEM3_2(n) (((n)&0xfff) << 4) #define TXRX_MEM3_1(n) (((n)&0xfff) << 20) // mem4 #define TXRX_MEM4_2(n) (((n)&0xfff) << 4) #define TXRX_MEM4_1(n) (((n)&0xfff) << 20) #endif // _TXRX_H_