IP version r7p0 Reserved Auxadc offset function enable 0: disable offset function 1: enable offset function Reserved auxadc convert data out average control: 000: disable adc average, output 12bit data and valid after once conversion; 001: adc convert twice and output the average data; 010: adc convert 4 times and output the average data; 011: adc convert 8 times and output the average data; 100: adc convert 16 times and output the average data; 101: adc convert 32 times and output the average data; 110: adc convert 64 times and output the average data; 111: adc convert 128 times and output the average data; the number of SW channel accessing, N+1. AUXADC output code selection: 0: adc_dout = (data-Doff) 1: if adc_offset_cal_en is 0 adc_dout = data if adc_offset_cal_en is 1 adc_dout = data-(Doff-2047) more detail see Function Description ADC 12bits mode 0: ADC in 10bits mode; 1: ADC in 12bits mode. SW channel run, Write '1' to run a SW channel accessing, it is cleared by HW. ADC global enable, 0: ADC module disable; 1: ADC module enable. Reserved ADC scale setting for current ADC channel Reserved Reserved ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC software config channel ID. Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC scale setting for current ADC channel Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved output the analog Reserved current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. Reserved ADC channel ID Reserved ADC HW channel accessing delay, its unit is ADC clock. It can be use for signal without enough setup time. ADC conversion result. Reserved ADC interrupt enable, 0: disable; 1: enable. ADC interrupt clear. Write "1" to clear. ADC masked interrupt. ADC raw interrupt. 0~7: fast HW channels; 8: SW channels; 9~16: slow HW channel; 31: no request. ADC accessing state: 0: idle; 1: fast HW request; 2: SW request; 3: slow HW request; 4: wait for fast HW request; 5: wait for slow HW request. ADC internal counter status, 0: idle; 1~n: work or wait counter. ADC fast HW channel7 timer enable, 0:disable; 1: enable. ADC fast HW channel6 timer enable, 0:disable; 1: enable. ADC fast HW channel5 timer enable, 0:disable; 1: enable. ADC fast HW channel4 timer enable, 0:disable; 1: enable. ADC fast HW channel3 timer enable, 0:disable; 1: enable. ADC fast HW channel2 timer enable, 0:disable; 1: enable. ADC fast HW channel1 timer enable, 0:disable; 1: enable. ADC fast HW channel0 timer enable, 0:disable; 1: enable. ADC fast HW channel timer working clock divider. ADC fast HW ch0 timer threshold. ADC fast HW ch1 timer threshold. ADC fast HW ch2 timer threshold. ADC fast HW ch3 timer threshold. ADC fast HW ch4 timer threshold. ADC fast HW ch5 timer threshold. ADC fast HW ch6 timer threshold. ADC fast HW ch7 timer threshold. Reserved ADC fast HW ch0 data, read twice, and capture the second value. Reserved ADC fast HW ch1 data, read twice, and capture the second value. Reserved ADC fast HW ch2 data, read twice, and capture the second value. Reserved ADC fast HW ch3 data, read twice, and capture the second value. Reserved ADC fast HW ch4 data, read twice, and capture the second value. Reserved ADC fast HW ch5 data, read twice, and capture the second value. Reserved ADC fast HW ch6 data, read twice, and capture the second value. Reserved ADC fast HW ch7 data, read twice, and capture the second value. Reserved output to analog output to analog THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration Reserved output to analog Aux ADC current sense enable signal, active high, default 0. Reserved ADC fast HW channel7 data valid. ADC fast HW channel6 data valid. ADC fast HW channel5 data valid. ADC fast HW channel4 data valid. ADC fast HW channel3 data valid. ADC fast HW channel2 data valid. ADC fast HW channel1 data valid. ADC fast HW channel0 data valid. 0:8k 1:4k 2:1k 3:16k 0:8k 1:4k 2:2k 3:1k 0: rc32k 1:xtal32k bit type is changed from w1c to rc. bit type is changed from w1c to rc. Write 1 to clear all wakeup status bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. wait time after vbat_det on, default is 2ms 0:32,1:64,��,7:4096,8:8192,9:16384,10:32768, default is 512 0: pd, 1: lp 0: pd, 1: lp 00: pd 01: pu 11: lp 0: pd 1: pu bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. reserved bit type is changed from w1c to rc. default is 500ms default is 1s default is 500ms default is 100ms default is 100ms default is 200ms default is 10ms bit type is changed from w1c to rc. Write 1 to clear all abnormal status Efuse type select, 00:TSMC default Efuse SW programme enable Efuse read data, If SW use efuse controller to send a read command to efuse memory, the return value will store here. Efuse data to be write. If SW want to program the efuse memory, the data to be programmed will write to this register before SW issue a PGM command. The efuse memory block index to be read or write. bit type is changed from w1c to rc. Write 1 to this bit will clear normal read flag.This bit is self-clear, read this bit will always get 0 bit type is changed from w1c to rc. Write 1 to this bit start READ mode(read mode).This bit is self-clear, read this bit will always get 0 bit type is changed from w1c to rc. Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0 ��1�� indicate EFUSE normal read has been done If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1. ��1�� indicate efuse memory in standby mode ��1�� indicate efuse memory in read mode ��1�� indicate efuse memory in programming mode Magic number, only when this field is 0x1811, the Efuse programming command can be handle. So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : a) PGM_EN =1; b) EFUSE_MAGIC_NUMBER = 0x1811 Magic number, only when this field is 0x6688, the margin read is usable. Config this register to control the timing of writing operation related signals Config this register to control the timing of writing operation related signals Efuse control version register bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. AUXADC current mode enable 1'b0: default, off 1'b1: current mode on AUXADC current step select AUXADC current calibration OTP threshold 3'b011: 135C, default OTP function enable control bit LDO_LP18 current limit threshold adjust default 1'b011 111~000 380mA~240mA 20mA/step LDO_LP18 short protect EN: ��0�� is disable ��1�� is enable(default) LDO_LP18 short protect current threshold adjust default 1'b1 LDO_LP18 compensation capacitor and resistor adjust LDO_LP18 discharge en clock selection for each channel RG_CLKOUT_SEL[0]: VCORE clk selection RG_CLKOUT_SEL[1]: VRF clk selection RG_CLKOUT_SEL[2]: VPA clk selection 0: internal mode, default 1: external mode phase shift option 1'b0: default, w/i 1/5 phase shift at internal mode 1'b1: uni-phase mode, all ouputs = channel 0 test mode control. 0: default, clock output off 0: default, clock output on anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset DCDC power down 1'b0: DCDC on 1'b1: DCDC power down low power mode 1'b0: active mode 1'b1: low-power mode anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on APC mode enable 1'b0: default, RG control mode 1'b1: APC mode APC ramp selection 1'b0: default, 2.0x ramp 1'b1: 2.5x ramp bypass mode disable 1'b0: default, auto bypass 1'b1: bypass off bypass force on 1'b0: default, auto bypass 1'b1: force bypass mode on bypass mode threshold 2'b00: default, ~200mV compensation C3 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current limit threshold tuning 2'b00: default 2'b01: -0.5pF 2'b10: +1pF 2'b11: +0.5pF current sense multiplier tuning 2'b00: default, x1 2'b01: x0.5 2'b10: x2 2'b11: x1.5 DVS control 1'b0: default, off 1'b0: on, for DCM down discharge force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode 100% duty selection 1'b0: default, max duty=100% 1'b1: max duty ~95% current sense average ratio current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% PFM mode threshold for upper limit 2'b00: default 2'b01: -50mV 2'b10: +50mV 2'b11: +100mV compensation R2 select 2'b00: default, 960k 2'b01: 880k 2'b10: 1040k 2'b11: 1120k compensation R3 select 2'b00: default, 5k 2'b01: 2.5k 2'b10: 10k 2'b11: 7.5k sawtooth tuning manully 2'b00: default 2'b01: +15% 2'b10: -30% 2'b11: -15% sawtooth calibration 1'b0: default, auto calibration before power-on 1'b1: calibration manully high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x current sense average ratio current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% output voltage selection, 25mV/step. 7'h00=0.4V, 7'h7C=3.5V default 7'h78=3.4V force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset DCDC to AUXADC trim channel selection 3'b001: select VCORE 3'b010: select VRF (VRF*18/37) 3'b011: select VPA (VPA*18/68) RG_DCDC_AUXTRIM_SEL[2], internal test mode select: 0: default, internal test mode disable 1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path 3'b100: enpwm_vrf 3'b101: zx_vrf 3'b110: enpwm_vcore 3'b111: zx_vcore AUX ADC channel ATE test scan mode control. 1 for ATE test channel scan, 0 for normal work. For ATE test channel scan, set this reg to 1, and using AUXAD_CS[4:0] to scan channel. AUXADC LDO output voltage selection, 00: AVDD_LDO=1.8V 01: AVDD_LDO=1.88V 10: AVDD_LDO=1.72V 11: AVDD_LDO=1.65V Default 00. AUXADC LDO enable signal, default 0 Set the direction of the GPIO n. 0 = output 1 = input When write, update the output value. When read, get the output value. When read, get the input value. '1', for rising edge and level high. '1', for falling edge and level low. '1', for level mode. 'Write '1' will clear GPIO interrupt. Each bit represents if there is a GPIO interrupt pending. '1', open negedge logic. Input triger number count enable slave_mode trigger select auto preload value Center-aligned mode select 00: disable , other:enable counter dir , 0: cnt ++ , 1: cnt -- one pulse mode, 0:disable 1:enable update disable, 0:disable, 1:enable clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass counter enable, 0: disbale, 1:enable slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable bit type is changed from w1c to rc. user trigger gen no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti2 prescale, 01:0 div2, 10: div4, others: bypass ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti1 prescale, 01:0 div2, 10: div4, others: bypass ti2 polarity ti2 enable ti1 polarity ti1 enable cnt value cnt prescale value cnt max value ic1 capture value ic2 capture value ic1 compare value ic2 compare value cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 bit type is changed from w1c to rc. trig gens, when counter works in slave mode bit type is changed from w1c to rc. bit type is changed from w1c to rc. GPIO_0 force enable for pu/pd GPIO_0 PUll up GPIO_0 PUll down GPIO_0 force enable for outoen. GPIO_0 force outoen value. GPIO_0 force output value for output. GPIO_0 pin output value. GPIO_0 select GPIO_1 force enable for pu/pd GPIO_1 PUll up GPIO_1 PUll down GPIO_1 force enable for outoen. GPIO_1 force outoen value. GPIO_1 force output value for output. GPIO_1 pin output value. GPIO_1 select GPIO_2 force enable for pu/pd GPIO_2 PUll up GPIO_2 PUll down GPIO_2 force enable for outoen. GPIO_2 force outoen value. GPIO_2 force output value for output. GPIO_2 pin output value. GPIO_2 select GPIO_3 force enable for pu/pd GPIO_3 PUll up GPIO_3 PUll down GPIO_3 force enable for outoen. GPIO_3 force outoen value. GPIO_3 force output value for output. GPIO_3 pin output value. GPIO_3 select GPIO_4 force enable for pu/pd GPIO_4 PUll up GPIO_4 PUll down GPIO_4 force enable for outoen. GPIO_4 force outoen value. GPIO_4 force output value for output. GPIO_4 pin output value. GPIO_4 select GPIO_5 force enable for pu/pd GPIO_5 PUll up GPIO_5 PUll down GPIO_5 force enable for outoen. GPIO_5 force outoen value. GPIO_5 force output value for output. GPIO_5 pin output value. GPIO_5 select GPIO_6 force enable for pu/pd GPIO_6 PUll up GPIO_6 PUll down GPIO_6 force enable for outoen. GPIO_6 force outoen value. GPIO_6 force output value for output. GPIO_6 pin output value. GPIO_6 select GPIO_7 force enable for pu/pd GPIO_7 PUll up GPIO_7 PUll down GPIO_7 force enable for outoen. GPIO_7 force outoen value. GPIO_7 force output value for output. GPIO_7 pin output value. GPIO_7 select bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. lower 16 bit of Count Value for 1st Timeout upper 16 bit of Count Value for 1st Timeout lower 16 bit of Count Value for 2nd Timeout upper 16 bit of Count Value for 2nd Timeout 0: reset only, 1: interrupt and reset reset pulse length in number of wdt clock cycles bit type is changed from w1c to rc. write 8'h76 to restart, write 8'h34 to stop, else do nothing bit type is changed from w1c to rc. A pulse to clear interrupt 1 when watchdog running, else 0 interrupt assert when 1 pmic base address AHB Address bus size System Ifc1 Number of generic channel System Ifc2 Number of generic channel BB Ifc Number of generic channel The following modules are linked to ifc dma req with 2 requests per module Number of IRQ /// XHALT macro will send the event 0x4a17 to the debug host and /// will stall the XCPU. The XCPU can be released from Coolwatcher /// by issuing a xrbp command. #define XHALT { \ asm("nop "); \ asm("nop "); \ asm("nop "); \ asm("nop "); \ while (hwp_debugHost->event != DEBUG_HOST_EVENT0_SEMA); \ hwp_debugHost->event = 0x4a17; \ hwp_sysCtrl->XCpu_Dbg_BKP |= SYS_CTRL_STALLED; \ asm("nop "); \ asm("nop "); \ asm("nop "); \ asm("nop "); \ } #define KSEG0(addr) (addr) #define KSEG1(addr) (addr) #define KSEG01_PHY_ADDR(addr) ((UINT32)(addr) & 0x0fffffff) #define barrier() __asm__ __volatile__("": : :"memory") #define REG_ACCESS_ADDRESS(addr) KSEG1(addr) /* Define access cached or uncached */ #define MEM_ACCESS_CACHED(addr) ((UINT32*)((UINT32)(addr)&0xdfffffff)) #define MEM_ACCESS_UNCACHED(addr) ((UINT32*)((UINT32)(addr)|0x20000000)) /* Register access for assembly */ #define BASE_HI(val) (((0x40000000 | val) & 0xfffff000) + (val & 0x1000)) #define BASE_LO(val) (((val) & 0xfff) - (val & 0x1000)) /* to extract bitfield from register value */ #define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) #define EXP2(n) (1<<(n)) /// XHALT macro will send the event 0x4a17 to the debug host and /// will stall the XCPU. The XCPU can be released from Coolwatcher /// by issuing a xrbp command. #define XHALT { \ asm("nop "); \ asm("nop "); \ asm("nop "); \ asm("nop "); \ while (hwp_debugHost->event != DEBUG_HOST_EVENT0_SEMA); \ hwp_debugHost->event = 0x4a17; \ hwp_sysCtrl->XCpu_Dbg_BKP |= SYS_CTRL_STALLED; \ asm("nop "); \ asm("nop "); \ asm("nop "); \ asm("nop "); \ } adi low bits version. adi high bits version,read only. addr mode for access. "00" word mode,means addr[x:2],"01" half word,means addr[x:1], "1x" byte mode, means addr[x:0]. configure write bit flag. addr bit number configure, "00" address is 12 bits, "01" address is 10 bits, "10" address is 15 bits. "1" write uses command mode, in this mode, must first configure channel addr, then data. write channel 0 priority. 0 has lowest priority, 4 has highest priority. read channel 1 priority. 0 has lowest priority, 4 has highest priority. read channel 2 priority. 0 has lowest priority, 4 has highest priority. read channel 3 priority. 0 has lowest priority, 4 has highest priority. read channel 4 priority. 0 has lowest priority, 4 has highest priority. read channel 5 priority. 0 has lowest priority, 4 has highest priority. "1" write command fifo enable. fifo overfolow interrupt mask. fifo overfolow interrupt without mask status. fifo overfolow interrupt with mask status. fifo overfolow interrupt clear. total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len. total adi cmd length = rf_gssi_addr_len + read/write flag. total adi data length . write bit position in frame stream . "1" write means 1, "0" write means 0. "1" hardware auto generate sync, "0" software generates sync. "1" sync is pulse, "0" sync is level. "1" software generates sync. "1" invert output sck. output oen : "1" oen add dummy cycle, "0" oen not add dummy cycle. reserved. "1" output dummy_clock, "0" gate dummy clock. "1" rx sample delay 1 adi clk cycle, "0" delay 0 adi clk cycle. "1" sck always on, "0" audo gate clock. "1" write bit disable, "0" write bit enable. "1" tx data at negedge of sck."0" tx data at posedge of sck. "1" rx data at negedge of sck."0" rx data at posedge of sck. F_sck = F_clk/(2*(rf_gssi_clk_div+1)) sync before data transfer sync end data transfer extral dummy sck extral dummy sck start sequence condition, only used in RFFE master turn around to salve length , only used in RFFE slave turn around to master length , only used in RFFE "1" 2 wires enable configure read address and start a read operation. read data from analog die. read address map to arm_red_cmd[16:2]. 1 means has not been read back. "1" write channel is busy "1" read channel is busy "1" adi operation is busy wfifo full status wfifo empty status wfifo fill data number adi fsm status event 0 wr status event 1 wr status event 2 wr status event 3 wr status the address map to the PMIC chip space, just for write operation the dat to the PMIC chip space, just for write operation This field indicates which standard channel to use. Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel. Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. When non-secure cpu read this register, the return value will automatic exlude the secure channel. 00000 = use Channel0 00001 = use Channel1 00010 = use Channel2 ... 01111 = use Channel15 11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example: 0000_0000 = All channels disabled 0000_0001 = Ch0 enabled 0000_0010 = Ch1 enabled 0000_0100 = Ch2 enabled 0000_0101 = Ch0 and Ch2 enabled 0000_0111 = Ch0, Ch1 and Ch2 enabled all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status . 0= The debug channel is running (not idle) 1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example: 0000_0000 = All channels registers can be accessed by secure master or non-secure master. 0000_0001 = Ch0 registers can only be accessed by secure master. 0000_0010 = Ch1 registers can only be accessed by secure master. 0000_0100 = Ch2 registers can only be accessed by secure master. 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. ...... all 1 = all channels registers can only be accessed by secure master. This register indicates rfspi channel register can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example: 0000_0000 = All channels dma are non-secure master. 0000_0001 = Ch0 dma is secure master. 0000_0010 = Ch1 dma is secure master. 0000_0100 = Ch2 dma is secure master. 0000_0101 = Ch0 and Ch2 dma are secure master. 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. ...... all 1 = all channels dma are secure master. This register indicates rfspi channel dma is secure master. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB Exchange the write data to fifo halfword MSB or LSB Set Auto-disable mode 0 = when TC reach zero the channel is not automatically released. 1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size 0= 8-bit peripheral 1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel. This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved. The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. . Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer. For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. Channel Enable, write one in this bit enable the channel. This channel works only in fifo mode. Channel Disable, write one in this bit to disable the channel. Enable bit, when '1' the channel is running The internal channel fifo is empty Internal fifo level AHB Start Address. This field represent the start address of the fifo. The start address must 32-bit aligned. AHB End Address. This field represent the last address of the fifo (it is the first address not used in the fifo). The end address must 32-bit aligned. Transfer Count, transfer size in bytes. This bit indicated the transfer size in bytes to perform. Up to 16kbytes per transfer. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. axi write data channel ready axi write address channel ready axi read address channel ready dma is working,and CPU can't access ce registers except ce_clear register. Reserved dma write port state: 4'd0: idle 4'd1: write burst calculate 4'd2: write burst calculate data number 4'd3: write burst wait enough data 4'd4: write burst start 4'd5: write burst execute 4'd6: write burst wait burst end 4'd7: write burst end dma read port state: 4'd0: idle 4'd1: read burst wait enough buffer space 4'd2: read burst wait one cycle 4'd3: read burst start 4'd4: read burst execute 4'd5: read burst wait burst end 4'd6: read burst done fde cmd fifo is non-empty cmd fifo is non-empty interrupt raw status is valid ce in error status dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 3'd0: idle 3'd1: pka read instruction start 3'd2: pka load start 3'd3: pka wait done 3'd4: pka send done 3'd5: pka jump judgement dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done Reserved rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done Reserved rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish sm4 state: 3'd0: idle 3'd1: generate key 3'd2: round start 3'd3: rounding 3'd4: xts generate key 3'd5: xts round start 3'd6: xts rounding 3'd7: done wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish Reserved [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait Reserved tdes module status: [3:0]: des run cycle counter [4]: des key check error generate wvalid state: 4'd0: idle 4'd1: wait enough data 4'd2: generate wvalid 4'd3: wait enough data when bursting 4'd4: wait wready for next burst data efuse access status: 4'd0: idle 4'd1: trng write start 4'd2: hmac read start 4'd3: hmac session key read start 4'd4: trng write 4'd5: hmac read 4'd6: hmac session key read 4'd7: cpu access start 4'd8: cpu read 4'd9: cpu write 4'd10: symmetric key1 read start 4'd11: symmetric key2 read start 4'd12: symmetric key1 read 4'd13: symmetric key2 read 4'd14: done 3'd0: idle 3'd1: pka store start 3'd2: pka wait done 3'd3: pka send done 3'd4: pka jump judgement dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 5'd20: pka store start 5'd21: pka wait done 5'd22: pka send done 5'd23: pka jump judgement [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait hash module status: [31:0]: hash register a value Reserved hash module status: [2:0]: hash state 3'd0: idle 3'd1: data request 3'd2: no-hmac 3'd3: hmac key 3'd4: first hmac message 3'd5: second hmac message 3'd6: digest out [8:3]: hash run cycle Reserved force fde aes clock enable Reserved force chacha engine clock enable force poly engine clock enable force rng autogate clock enable force aes key expan autogate clock enable Reserved force dma axi autogate clock enable force dma ctrl autogate clock enable force apb regbank autogate clock enable Reserved simon speck clock enable pka clock enable chacha poly clock enable sm4 clock enable trng clock enable des clock enable hash clock enable fde aes clock enable aes clock enable dma_main clock enable Reserved enable src/dst length error int enable one command done int Reserved enable src/dst length error int enable one command done int Reserved enable tdes key check error int Reserved Reserved src/dst length error int status one command done int status, Reserved src/dst length error int status one command done int status, Reserved ce tdes key check error int status Reserved Reserved src/dst length error int status one command done int status, Reserved bit type is changed from wc to rc. clear error int status bit type is changed from wc to rc. clear one command done int status, Reserved bit type is changed from wc to rc. clear tdes key check error int status Reserved Reserved bit type is changed from wc to rc. start ce reserved bit type is changed from wc to rc. reset ce status Reserved 1: don��t update key, 0: update key 0: rtl rotation, 1: no-rotation 00: key 128bits,01:192bits,10,11:256bits 0000:ECB,0001:CBC,0010:CTR,0011:XTS,0100:CMAC,0101:GCM,0110:GMAC,0111:CCM,1000:CBCMAC,1001:CFB,1010:OFB Reserved aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid 0:encode,1:decode Reserved aes module enable Reserved 0: disable, 1: enable even/odd check 0:odd check,1:even check Reserved 00:ECB,01:CBC Reserved 0:encode,1:decode Reserved tdes module enable Reserved sha3 shake out length Reserved 00: normal hash; 01: ipad ;10: opad; 11: reserved Reserved hash work module, 5��d0: Doesn��t work 5��d1: MD5 5��d2: SHA-1 mode 5��d3: SHA-224 mode 5��d4: SHA-256 mode 5��d5: SHA-384 mode 5��d6: SHA-512 mode 5��d7: SHA-512/224 mode 5��d8: SHA-512/256 mode 5��d9: SM3 mode 5��d10: SHA3-224 5��d11: SHA3-256 5��d12: SHA3-384 5��d13: SHA3-512 5��d14: SHA3-SHAKE128 5��d15: SHA3-SHAKE256 Reserved hash module enable Reserved 00:chacha20 ; 01:poly1305; 10:AEAD_CHACHA20_POLY1305 Reserved 0:encrypt,1:decrypt Reserved chacha poly module enable Reserved 1: don��t update key, 0: update key 00: key 128bits,01:192bits,10:256bits Reserved 000:ECB,001:CBC,010:CTR,100:CFB,101:OFB 0:speck; 1:simon Reserved 0:encrypt,1:decrypt Reserved chacha poly module enable Reserved switch source high 32bits and low 32bits switch destination high 32bits and low 32bits source data switch of one word destination data switch of one word Reserved list update iv/sec/cnt flag data end in link list mode list end flag 0: isn't aad list 1: is aad list 0: aad no-end list 1: aad end list wait axi B channel bready 0:normal mode, 1: iram key or secure ddr key 0: normal mode, 1: aes/sm4 key from session key Reserved 1: all crypto key in ddr/iram; 0: from registers 0:normal mode, 1: bypass ce 0: std flag 1: std aad flag 0: std aad no-end flag 1: std aad end flag std end flag 0: enable cmd int output: 1: don't output int 0: dump from ddr; 1: don't dump 0: rcv from ddr; 1: don't rcv 0:std mode, 1: link mode Reserved source address high 4bits; or aes mac aad address high 4bits source fragment length of each node; or aes mac aad length Reserved destination address high 4bits destination fragment length of each node source address; or aes mac aad address destination address; Reserved ce_list_ptr high 4bits Reserved first list length,support max 256 nodes first list start address Reserved aes hmac key address high 4bits aes hmac key length aes rsa hamc key address; Reserved aes tag address high 4bits aes tag length aes tag address low 32bits iv/sec/cnt shared register for aes;iv[127:0],iv[127:96] in low address,and little-edian iv/sec/cnt shared register for aes;iv[95:64] iv/sec/cnt shared register for aes;iv[63:32] iv/sec/cnt shared register for aes;iv[31:0] secure read;aes key1/sm4 key1;key[127:0],key[127:96] in low address,and little-edian aes key1/sm4 key1;key[95:64] aes key1/sm4 key1;key[63:32] aes key1/sm4 key1;key[31:0] aes key1 aes key1 aes key1 aes key1 aes key2/sm4 key2 aes key2/sm4 key2 aes key2/sm4 key2 aes key2/sm4 key2 aes key2 aes key2 aes key2 aes key2 Reserved 1: don��t update key, 0: update key 0: rtl rotation, 1: no-rotation 000:ECB,001:CBC,010:CTR,011:XTS,100:CFB,101:OFB Reserved 0:encode,1:decode Reserved sm4 module enable r4 px ce performace counter Reserved when the siganl is high ,then flag the pub aes/sm4/hash is catch the cmd from the pub cmd buf or the pub is working Reserved when the siganl is high ,then flag the sec aes/sm4/hash is catch the cmd from the sec cmd buf or the sec is working Reserved ce sec or pub use the ce aes/sm4/hash cicpher module Reserved axi read port outstanding number axi write port outstanding number axi bus wcache axi bus rcache Reserved bit type is changed from wc to rc. fde to restart 1: fde stop command is valid 0:fde to execute next cmd; 1: fde finish current cmd,then stop Reserved bit type is changed from wc to rc. to restart 1: stop command is valid 0: to execute next cmd; 1: finish current cmd,then stop Reserved Reserved reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable fde side sel; 1: enable fde side axi sel reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable pub side sel; 1: enable pub side axi sel ce performace counter high 32 bit secure os; can't support wrote by commandfifo mode,hash key can't be from session key secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os; can't support wrote by commandfifo mode,hash key can't be from iram key secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; ce command fifo entry ce command fifo status ce rcv address lo ce dump address lo Reserved ce dump address hi ce rcv address hi cmd finish counter,cpu read then clear ce fde aes cipher command fifo entry ce fde aes cipher command fifo status ce fde_aes cipher rcv address lo ce fde_aes cipher dump address lo;or aes tag address low 32bits Reserved ce fde_aes cipher dump address hi,or aes tag address high 4bits ce fde_aes cipher rcv address hi fde_aes cipher cmd finish counter,cpu read then clear Reserved bit type is changed from wc to rc. start fde_aes cipher ce(TDES/AES/SM4/SM1/SM7/GHASH) reserved bit type is changed from wc to rc. reset ce fde_aes cipher status Reserved aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid Reserved 00: key 128bits,01:192bits,10,11:256bits Reserved 0: rtl rotation, 1: no-rotation(sm4/aes) 0000:ECB,0001:CBC,0010:CTR,0011:XTS Reserved 0:encode,1:decode Reserved fde_aes cipher module enable Reserved ce fde iv auto add 1��b1 each 512Byte msg fde_aes switch source high 32bits and low 32bits fde_aes switch destination high 32bits and low 32bits fde_aes cipher source data switch of one byte fde_aes cipher destination data switch of one byte Reserved list update iv/sec/cnt flag fde_aes cipher data end in link list mode fde_aes cipher list end flag Reserved 0:normal mode, 1: iram key or secure ddr key 0: normal mode, 1: aes key from session key Reserved 1: fde_aes cipher all crypto key in ddr/iram,and the iv also come from drr except the link list mode; 0:fde_aes cipher from registers Reserved fde_aes cipher std end flag 0: fde_aes cipher enable cmd int output: 1: don't output int 0:fde_aes cipher dump from ddr; 1:fde_aes cipher don't dump 0:fde_aes cipher rcv from ddr; 1:fde_aes cipher don't rcv 0:fde_aes cipher std mode, 1:fde_aes cipher link mode Reserved ce_fde_aes_list_ptr high 4bits Reserved fde_aes cipher first list length,support max 40 nodes fde_aes cipher first list start address fde_aes cipher destination address high 4bits fde_aes cipher source address high 4bits; or aes mac aad address high 4bits fde_aes cipher source fragment length of each node; or aes mac aad length fde_aes cipher source address;or aes mac aad address fde_aes cipher destination address; Reserved fde aes key address high 4bits fde aes key length fde aes key address; Reserved axi awprot under key in iram mode 0: non_sec 1: sec Reserved ce fde aes dummy register iv/sec/cnt shared register for aes;iv[127:0],iv[127:96] in low address,and little-edian,when the key from ddr, the iv also come from ddr,except link list mode iv/sec/cnt shared register for aes ;iv[95:64] iv/sec/cnt shared register for aes ;iv[63:32] iv/sec/cnt shared register for aes;iv[31:0] secure read;fde aes key1key1;key[127:0],key[127:96] in low address,and little-edian fde aes key1;key[95:64] fde aes key1;key[63:32] fde aes key1;key[31:0] fde aes key1 fde aes key1 fde aes key1 fde aes key1 fde aes key2 fde aes key2 fde aes key2 fde aes key2 fde aes key2 fde aes key2 fde aes key2 fde aes key2 secure os; can't support wrote by commandfifo mode,hash/rc4 key can't be from session key secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os; can't support wrote by commandfifo mode,hash/rc4 key can't be from iram key secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; secure os permited; bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. General control signals set. Debug host generated reset. Signal to system control. Active high.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. Force wakeup. Active high.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). When write '1, generate a level IRQ to XCPU. Write '0 is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). When write '1', generate a level IRQ to BCPU. Write '0' is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Lock Debug port set.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. General control signals clear. Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
Write '1' to this bit will clear it to '0'.
Reseted by signal rst_host_reg. Force wakeup. Active high.
Write '1' to this bit will clear it to '0'.
Reseted by signal rst_host_reg. Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Lock Debug port clear.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Configure Debug UART Clock divider. Debug host clock divider. The serial clock is generated by dividing 14,7456MHz Host Clock by (CFG_CLK+2). So By default, the serial clock is 14,7456MHz / (2+2) = 3,6864 MHz which corresponds to the 921,6K Baud-rate.
Reseted by signal rst_host_reg. Configure Debug UART. When '1', Disable Normal Uart functional group.
This bit is set to '1' when break.
Reseted by signal rst_host_reg. When '1', Ignore IFC write and read access so only debug host internal is accessible.
This bit is set to '1' when break.
Reseted by signal rst_host_reg. The usage of this bit is deternimed by the specific chip.
Can be used as Debug_Port_Lock register to protect some register change by the regular software while debug hosr is used to set thoses registers to specific values.
Reseted by signal rst_host_reg. When '1', force the Debug Uart to have priority on TX.
Reseted by signal rst_host_reg. Status of CRC. This bit represents that an CRC error has occured in commands received by Debug Host. Once set to '1', it will keep the value until this register is clearred by write '1'.
'0' = no CRC error.
'1' = CRC error.
Reseted by signal sys_rst_others (host). This bit represents if the 16-byte Flow Control FIFO has an overflow error. This status will be kept until a RX break is received.
'0' = no Flow Control Overflow Error.
'1' = Flow Control Overflow Error.
Reseted by signal sys_rst_others (host). Host write, APB readable register. These bits can be read by APB and write by host. Corresponds to APB register STATUS. They can also be reseted to zeros by APB command. (see details in debug host APB register mapping)
Reseted by signal sys_rst_others (host). APB write, Host readable register. These bits can be written by APB and read by host. Corresponds to APB register STATUS.
Write to Bit 0 can reset the P2H status.
Reseted by signal sys_rst_others (host). Address of data to be read or written. These two bits indicates element data size.
when "00" = "byte".
when "01" = "half word".
when "10" = "word". This bit indicates command is read or write.
when "0" = "Read".
when "1" = "Write". Those bits are data to be read or written by IFC. When read, this bit is used for event semaphore.
'0' = no new event should be programed.
'1' = no pending event, new event is authorised.
If host is not enabled, this bit is always '1'. However in this case, any event written will be ignored.
When Write, this bit is the least significant bit for a 32-bit event. These bits combined with bit0 consists a 32-bit event number. If a new event is written before the previous event has been sent, it will be ignored. When '1', force the debug host on, use clock UART if clock host is not detected. This bit indicates if clock host is detected to be on or not.
'0' = no clock host.
'1' = clock host detected. Status which can be written through debug uart interface into a debug host internal register and read by APB. write in this bit will reset h2p status register. Status which can be written by APB and read through debug uart interface as a debug host internal register. when write '1', clear the xcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the xcpu irq status. when write '1', clear the bcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the bcpu irq status. Allows to turn off the UART: 0 = Disable 1 = Enable Number of data bits per character (least significant bit first): 0 = 7 bits 1 = 8 bits This bit will be masked to '1' if debug host is enabled. Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0). 0 = one stop bit is transmitted in the serial data. 1 = two stop bits are generated and transmitted in the serial data out. This bit will be masked to '0' if debug host is enabled. Parity is enabled when this bit is set. This bit will be masked to '0' if debug host is enabled. Controls the parity format when parity is enabled: 00 = an odd number of received 1 bits is checked, or transmitted (the parity bit is included). 01 = an even number of received 1 bits is checked or transmitted (the parity bit is included). 10 = a space is generated and received as parity bit. 11 = a mark is generated and received as parity bit. These bit will be ignored if debug host is enabled. Sends a break signal by holding the Uart_Tx line low until this bit is cleared. This bit will be masked to '0' if debug host is enabled. reset rx fifo. reset tx fifo. Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used: 00 = no transmit flow control. 01 = transmit XON1/XOFF1 as flow control bytes 10 = transmit XON2/XOFF2 as flow control bytes 11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used: 00 = no receive flow control 01 = receive XON1/XOFF1 as flow control bytes 10 = receive XON2/XOFF2 as flow control bytes 11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes Note: If single XON/XOFF character is used for flow contol, the received XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is received when XOFF is expected. If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. Otherwise they will be considered as data. This is also the case if XOFF1 is followed by character other than XOFF2. When soft flow control characters or backslash are encountered in the data file, they will be inverted and a backslash will be added before them. for example, if tx data is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON). When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16. 0 = (BCLK = SCLK / 4) 1 = (BCLK = SCLK / 16) This bit will be masked to '0' if debug host is enabled. When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details). This bit will be masked to '0' if debug host is enabled. Controls the Uart_RTS output (not directly in auto flow control mode). 0 = the Uart_RTS will be inactive high 1 = the Uart_RTS will be active low This bit will be masked to '1' if debug host is enabled. Enables the auto flow control. In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0), If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register). Tx data flow is stopped If Uart_CTS become inactive high. If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS bit in CMD_Set register. Uart_CTS will not take effect. In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0), If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register). If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit in CMD_Set register. Tx data flow will be stoped when XOFF is received either this bit is enable or disabled. This bit will be masked to '1' if debug host is enabled. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept. This bit will be masked to '0' if debug host is enabled. HST TXD output enable. '0' enable. Length of a break, in number of bits. This bit will be masked to "1011" if debug host is enabled. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. This bit indicates that the UART is receiving a byte. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), This bit is set when the Uart_CTS line changed since the last time this register has been written. In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), This bit is set when received XON/XOFF status changed since the last time this register has been writtern. This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), current value of the Uart_CTS line. '1' = Tx not allowed. '0' = Tx allowed. In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), current state of software flow control. '1' = when XOFF received. '0' = when XON received. This bit is set when Tx Fifo Reset command is received by CTRL register and is cleared when Tx fifo reset process has finished. This bit is set when Rx Fifo Reset command is received by CTRL register and is cleared when Rx fifo reset process has finished. This bit is set when bit enable is changed from '0' to '1' or from '1' to '0', it is cleared when the enable process has finished. This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling Rx RTS too early. The UART_RECEIVE_BUFFER register is a read-only register that contains the data byte received on the serial input port. This register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Clear to send signal change or XON/XOFF detected. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Pulse detected on Uart_Dma_Tx_Done_H signal. Pulse detected on Uart_Dma_Rx_Done_H signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Defines the threshold level at which the Data Available Interrupt will be generated. The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Defines the threshold level at which the Data Needed Interrupt will be generated. The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC). The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. XON1 character value. Reset Value is CTRL-Q 0x11. XOFF1 character value. Reset Value is CTRL-S 0x13 XON2 character value. XOFF2 character value. These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. reserved Dump source selection. 0: dump RX data from DFE 1: dump TX data from BB 2: dump DFE internal RX path data. It works with rxdp_test_dac_sel_rg register 3: dump DFE internal TX path data. It works with txdp_test_dac_sel_rg register RX/TX work mode in DFE: 0: RX 1: TX Software reset for CGU, active low. 0: reset 1: no reset Software reset for TXDP, active low. 0: reset 1: no reset Software reset for RXDP when reset_mode is 1, active low. 0: reset 1: no reset SW controlled reset for RXDP when reset_mode is 0, active low. 0: reset 1: no reset Reset source for RXDP. 0: reset from BB TCU event signal with precise timing control 1: reset from register resetn_rxdp PolarIQ mode enable for NB/WT TX 0: PolarIQ disabled 1: PolarIQ enabled reserved reserved 0: RX CIC1 doesn't work in loft mode; 1: RX CIC1 works in loft mode clock select for BB NB or dump. 0: 61.44MHz 1: 26MHz 0: registers module clk gating enabled; 1: registers module clk always on Invert DAC clock or not. 0: clk_dac is not inverted 1: clk_dac is inverted Invert ADC clock or not. 0: clk_adc is not inverted 1: clk_adc is inverted DFE clock shift control. 0: clock shift disabled 1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency reserved clock enable for BB NB/WT 61.44MHz clock enable for DFE NB/WT TX reserved clock enable for DFE RX clock enable for DFE DAC clock enable for DFE ADC. 0: clock disabled 1: clock enabled reserved Start to load DC value, active high. Before next load, set it low firstly IQ swap in DC module 0: no swap 1. swap Hold DC accumulator calculation in DC calibration mode This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. Load DC value in calibration mode to debug port, only used for debug purpose DC module work mode. 0: DC calibration mode 1: DC cancel mode DC real part value used in cancel mode DC image part value used in cancel mode Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register reserved Slow convergence control, work with conv_mode_ct_rg register Fast convergence control, work with conv_mode_ct_rg register Duration time of DC calibration, which is based on sample unit DC convergence loop mode selection. 0: fast 1: slow 2: fast->slow 3: fast->hold load rxdp_gain_ct to DFE. Write it to 1b'0 before assert it bypass rxdp_gain_ct_load Gain BB control. [-24db, 57.875db], step=0.125db Bit [15:0] of RX group delay coefficient 0 reserved Bit [19:16] of RX group delay coefficient 0 Bit [15:0] of RX group delay coefficient 1 reserved Bit [19:16] of RX group delay coefficient 1 Bit [15:0] of RX group delay coefficient 2 reserved Bit [19:16] of RX group delay coefficient 2 Bit [15:0] of RX group delay coefficient 2 reserved Bit [19:16] of RX group delay coefficient 2 reserved RF data type. 0: IF 1: ZF RF filter type. 0: BP 1: LP reserved Read rate of DFE ADC FIFO, which depends on RX mode. 5'h01: NB/WT Write enable of DFE ADC FIFO, active high reserved Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high Real part of DC value, it is stable when rxdp_dcc_val_reg is high Image part of DC value, it is stable when rxdp_dcc_val_reg is high reserved Data enable of Notch DC 0: disable 1: enable reserved Coefficient a for real part of Notch DC reserved Coefficient a for image part of Notch DC reserved Coefficient k of Notch DC reserved Data enable of Notch H 1st core 0: disable 1: enable Data enable of Notch H 2nd core 0: disable 1: enable reserved Coefficient a for real part of Notch H 1st core reserved Coefficient a for image part of Notch H 1st core reserved Coefficient a for real part of Notch H 2nd core reserved Coefficient a for image part of Notch H 2nd core reserved Coefficient k of Notch H 1st core Coefficient k of Notch H 2nd core Coefficient COEF0 of ACI filter Coefficient COEF1 of ACI filter Coefficient COEF2 of ACI filter Coefficient COEF3 of ACI filter Coefficient COEF4 of ACI filter Coefficient COEF5 of ACI filter Coefficient COEF6 of ACI filter Coefficient COEF7 of ACI filter Coefficient COEF8 of ACI filter Coefficient COEF9 of ACI filter Coefficient COEF10 of ACI filter Coefficient COEF11 of ACI filter Coefficient COEF12 of ACI filter Coefficient COEF13 of ACI filter Coefficient COEF14 of ACI filter Coefficient COEF15 of ACI filter Coefficient COEF16 of ACI filter Coefficient COEF17 of ACI filter Coefficient COEF18 of ACI filter Coefficient COEF19 of ACI filter Coefficient COEF20 of ACI filter Coefficient COEF21 of ACI filter Coefficient COEF22 of ACI filter Coefficient COEF23 of ACI filter Bit [15:0] of frequency offset for Mixer Bit [23:16] of frequency offset for Mixer reserved Outband RSSI enable Inband RSSI enable Outband RSSI ushift value Inband RSSI ushift value load rxdp_gain_ct_rf to DFE. Write it to 1b'0 before assert it bypass rxdp_gain_ct_rf_load Gain RF control. [-24db, 57.875db], step=0.125db reserved start inband RSSI max and min measurement timer count [15:0] for max and min measurement report after start timer count [31:16] for max and min measurement report after start reserved start to load max and min measurement report. Before next load, set it low firstly reserved valid indication of max and min measurement report after assert load_max_min_ib_rssi to avoid metastability. rssi_min_reg_ib_rssi and rssi_max_reg_ib_rssi are stable when this register is high reserved inband RSSI min value, it is stable when rssi_max_min_val_reg_ib_rssi is high reserved inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high reserved interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear reserved start to load instant measurement report. Before next load, set it low firstly reserved valid indication of instant measurement report after assert load_ib_rssi to avoid metastability. rssi_reg_ib_rssi is stable when this register is high reserved inband RSSI instant value, it is stable when rssi_val_reg_ib_rssi is high reserved start outband RSSI max and min measurement timer count [15:0] for max and min measurement report after start timer count [31:16] for max and min measurement report after start reserved start to load max and min measurement report. Before next load, set it low firstly reserved valid indication of max and min measurement report after assert load_max_min_ob_rssi to avoid metastability. rssi_min_reg_ob_rssi and rssi_max_reg_ob_rssi are stable when this register is high reserved outband RSSI min value, it is stable when rssi_max_min_val_reg_ob_rssi is high reserved outband RSSI max value, it is stable when rssi_max_min_val_reg_ob_rssi is high reserved interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear reserved start to load instant measurement report. Before next load, set it low firstly reserved valid indication of instant measurement report after assert load_ob_rssi to avoid metastability reserved outband RSSI instant value for WB, it is stable when rssi_val_reg_ob_rssi is high reserved outband RSSI instant value for UP, it is stable when rssi_val_reg_ob_rssi is high reserved outband RSSI instant value for DN, it is stable when rssi_val_reg_ob_rssi is high reserved Interp. HBF1 0: SW bypass disable 1: SW bypass enable Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter Gain_RF Group Delay Equ Notch(DC) Mixer RC IMBC DC Calib.&Cancel Deci.CIC1 reserved Interp. HBF1 0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement 1: bypass controlled by SW. When it is set, rxdp_bypass_uphb1 will be used Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter Gain_RF Group Delay Equ Notch(DC) Mixer RC IMBC DC Calib.&Cancel Deci.CIC1 reserved Coefficient a1 for PLL Equ. reserved Coefficient a2 for PLL Equ. reserved Coefficient b1 for PLL Equ. reserved Coefficient b2 for PLL Equ. Bit [27:12] of gain for PLL Equ. It is valid when AFC adjustment is being enabled Bypass load_g: 0: disable bypass 1: enable bypass Bypass PLL Equ. 0: disable bypass 1: enable bypass reserved 4 LSB control Former output shift control reseved reseved reseved Bit [34:32] for GSM TX frequency use former output or not 0: RX don't use 1: TX use Bit [15:0] for GSM TX frequency Bit [31:16] for GSM TX frequency Offset add to GSM TX frequency reseved GSM TX frequency control. 0: modulation signal act on GSM TX freqency 1: GSM TX freqency is fixed reseved GSM TX frequency load is at the same time of AFC adjustment or not 0: at the same time 1: not at the same time reserved reseved Bit [11:0] of gain for PLL Equ. It works with register txdp_gsm_g_rg reseved Delay1 index Delay2 index Bit [15:0] of gsm_grp_dly_coff1 reseved Bit [19:16] of gsm_grp_dly_coff1 Bit [15:0] of gsm_grp_dly_coff2 reseved Bit [19:16] of gsm_grp_dly_coff2 Bit [15:0] of gsm_grp_dly_coff3 reseved Bit [19:16] of gsm_grp_dly_coff3 Bit [15:0] of gsm_grp_dly_coff4 reseved Bit [19:16] of gsm_grp_dly_coff4 load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it bypass txdp_wedge_gain_ct_load Gain control of NB/WT TX. [-24db, 57.875db], step=0.125db reserved reserved reserved reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved divide resource of clk_dac when test mode. 000: divide by 1 001: divide by 2 010: divide by 4 011: divide by 8 100: divide by 16 101: divide by 32 110: divide by 64 default: divide by 1 resource of clk_dac when test mode. 01: clk_61.44m 10: clk_26m_fbc 11: clk_adc_gge_nb enable clk_dac when test mode 0: clk_dac is from function mode 1: clk_dac is from test mode reserved Delay3 index Delay4 index Delay5 index Delay6 index Delay7 index reserved Coefficient 0 of ACLR filter reserved Coefficient 1 of ACLR filter reserved Coefficient 2 of ACLR filter reserved Coefficient 3 of ACLR filter Bit [15:0] of coefficient 0 of group delay equ. for NB/WT TX reserved Bit [19:16] of coefficient 0 of group delay equ. for NB/WT TX Bit [15:0] of coefficient 1 of group delay equ. for NB/WT TX reserved Bit [19:16] of coefficient 1 of group delay equ. for NB/WT TX Bit [15:0] of coefficient 2 of group delay equ. for NB/WT TX reserved Bit [19:16] of coefficient 2 of group delay equ. for NB/WT TX Bit [15:0] of coefficient 3 of group delay equ. for NB/WT TX reserved Bit [19:16] of coefficient 3 of group delay equ. for NB/WT TX reserved Coefficient 0 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 1 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 2 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 3 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 4 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 5 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 6 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 7 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 8 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 9 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 10 of PolarIQ LPF in DPD for NB/WT TX reserved Coefficient 11 of PolarIQ LPF in DPD for NB/WT TX reserved BB TX data loopback to BB RX BB RX IQ swap. 0: normal 1: swap BB TX IQ swap. 0: normal 1: swap ADC IQ swap. 0: normal 1: swap DAC IQ swap. 0: normal 1: swap BB RX. 0: two's complement 1: offset binary BB TX. 0: two's complement 1: offset binary RF ADC. 0: two's complement 1: offset binary RF DAC. 0: two's complement 1: offset binary reserved reserved Globle clock gating disable register 0: no use 1: enable clock on all clock gating cells reserved enable dfe monitor swap of dfe_monitor[15:8] and dfe_monitor[7:0] 0: no swap 1: swap Monitor output selection reserved The offset on DAC real part reserved The offset on DAC image part reserved The DAC real part on test mode reserved The DAC image part on test mode reserved selection of function DAC data or test DAC data 00/01: select function DAC data including sine waveform 10: select test DAC data in RXDP path 11: select test DAC data in TXDP path enable sine waveform generation module enable test DAC data in RXDP path select test DAC data in RXDP path enable test DAC data in TXDP path select test DAC data in TXDP path reserved sine waveform amplitude bit [15:0] of sine waveform frequence reserved bit [22:16] of sine waveform frequence Interp. CIC1 0: SW bypass disable 1: SW bypass enable Group Delay Equ. when PolarIQ Interp.HBF5 Interp. HBF4 Group Delay Equ. LPF of DPD only when PolarIQ AMPM of DPD Split of DPD Whole DPD RC Gain Interp.HBF3 when PolarIQ Interp.HBF2 when PolarIQ Interp.HBF1 ACLR LPF reserved Interp. CIC1 0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement 1: bypass controlled by SW. When it is set, txdp_bypass_cic1 will be used Group Delay Equ. when PolarIQ Interp.HBF5 Interp.HBF4 Group Delay Equ. LPF of DPD only when PolarIQ AMPM of DPD Split of DPD Whole DPD RC Gain Interp.HBF3 when PolarIQ Interp.HBF2 when PolarIQ Interp.HBF1 ACLR LPF reserved all one bits, reserved for ECO 0:[11:0], 1:[12:1], 2:[13:2], 3:[14:3], 4: [15:4] FIFO txdp_rc full FIFO txdp_rc empty FIFO rxdp_rc full FIFO rxdp_rc empty FIFO ADC full FIFO ADC empty, this FIFO used between ADC and DFE reserved SW controlled reset for TXDP when reset_mode is 0, active low. 0: reset 1: no reset Reset source for TXDP. 0: reset from BB TCU event signal with precise timing control 1: reset from register resetn_txdp 0:0.5 1:0.609375 2:0.625 0:0.5 1:0.609375 2:0.625 0:0.5 1:0.609375 2:0.625 reserved Coefficient 4 of ACLR filter reserved Coefficient 5 of ACLR filter reserved Coefficient 6 of ACLR filter reserved Coefficient 7 of ACLR filter reserved Coefficient 8 of ACLR filter reserved Coefficient 9 of ACLR filter reserved Coefficient 10 of ACLR filter reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Amplitude compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved Phase compensation curve of DPD reserved power detect ushift reserved adc clk mode for pd 00:30.72M 01:15.36M 10:7.68M 11:3.84M source power detect 1:real part of data 0:imag part of data clear rssi value to 0 when txdp transmit finish 0: hold the last value 1: reset enable pd detect , active high. 0: disable 1: enable 0: pd module clk gating enabled; 1: pd module clk always on Software reset for pd, active low. 0: reset 1: no reset pd det value, it is stable when pd_rssi_reg_val is high reserved valid indication of pd measurement report after assert pd_load to avoid metastability. start to load instant pd detect measurement report. Before next load, set it low firstly number of invalid data when calculate rssi reserved interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear Returns 1 and locks the DMA channel for a transaction if it is available. Else returns 0.
Clear the transfer done interrupt status. Status of the DMA: 1 if enabled, 0 if disabled. Cause of the interrupt. This bit is set when the transfer is done and the interrupt mask bit is set.
Write one in the Int Clear or write 0 in Enable control bits to clear Int Done Cause bit. Status of the interrupt. Status of the transfer: 1 if the transfer is finished, 0 if it is not finished.
Write one in the Int Clear or write 0 in Enable control bits to clear Int Done Status bit. Actual status of channel lock. Channel is unlocked at the end of transaction or when the DMA is disabled. Controls the DMA. Write 1 to enable the DMA, write 0 to disable it. When 0 is written in this register, the Int Done Status and Cause bits are reset. End of transfer interrupt generation. When 1, the DMA will send an interrupt at transaction completion. Clear the transfer done interruption (this will clear Int Done Status and Int Done Cause).
This bit is auto-clear. You will always read 0 here. If this bit is set, the source address will be ignored and the memory will be fill with the value of the pattern register. Set the MAX burst length.
The 2'b10 mean burst max 16, 2'b01 mean burst max 8, 00 mean burst max 4. The DMA stop the current transfer and flush his FIFO (write only bit). When the FIFO is empty and last write performed, the DMA is disabled and available for a next transfer. The number of bytes copied is readable on DMA_XFER_SIZE register. Enable Gea process when 1. This field sets the type of GEA algorithm to process. This field selects the Direction in the GEA algorithm. Enable FCS process when 1. Destination address management.
00 : Normal DMA operation, DMA_DST_ADDR register define the destination address.
01 : DMA write address is constant (no incremented) and defined by the DMA_DST_ADDR register. All data write are in 16-bit.
10 : DMA write address is alternatively defined by DMA_DST_ADDR and DMA_SD_DST_ADDR registers. All data write are in 16-bit.
In this configuration, DMA write operation is alternatively:
DMA_DST_ADDR <= DMA_PATTERN register
DMA_SD_DST_ADDR <= Data[DMA_SRC_ADDR]
11 : reserved Source start read byte address. When a transfer is stalled by the Stop_Transfer bit, this register give the next current source address, which is directly the value to re-program to complete the transfer stopped. Destination start read byte address. When a transfer is stalled by the Stop_Transfer bit, this register give the next current destination address, which is directly the value to re-program to complete the transfer stopped. Second destination address. This register is only used when Dst_Address_Mgt=10. Transfer size in bytes. Maximum: 262144 bytes. When a transfer is stopped by the Stop_Transfer bit, this register give the number of remainder bytes to transfer. Value taken to fill the memory when the configuration bit Use Pattern is set. When the pattern mode is used the destination address must be 32-bit aligned and the transfer size multiple of 4. when Dst_Address_Mgt=10 Pattern is the data written at the address given by the Dst_Address register. GEA key Kc, LSB bit [31:0]. GEA key Kc, MSB bit [31:0]. MessKey (Input) register. Frame Check Sequence. The FCS is correct in reception when the final remainder is equal to C(x)= x^22 + x^21 + x^19 + x^18 + x^16 + x^15 + x^11 + x^8 + x^5 + x^4 f8 start bit, 0: not start or finished , 1: start when all groups done , 0: no gen int 1: gen int function sel 00: only move data , no encrypt 01: move data , AES encrypt 10: move data , snow3G encrypt 11: move data , zuc encrypt group start address total group cnt 0: not started or no finished 1: finished 0: not started or no finished 1: finished f9 start bit, 0: not start or finished , 1: start when all groups done , 0: no gen int 1: gen int function sel 00: AES encrypt 01: AES encrypt 10: snow3G encrypt 11: zuc encrypt group start address f9 result Set the direction of the GPIO n. 0 = output 1 = input 'Write '1' sets the corresponding GPIO pin as output. 'Write '1' sets the corresponding GPIO pin as input. When write, update the output value. When read, get the input value. Write '1' will set GPIO output value. When read, get the GPIO output value. 'Write '1' clears corresponding GPIO output value. When read, get the GPIO output value. '1', for rising edge and level high. '1', for falling edge and level low. '1', for level mode. 'Write '1' will clear GPIO interrupt. Each bit represents if there is a GPIO interrupt pending. '1', open negedge logic. Set the direction of the GPIO n. 0 = output 1 = input 'Write '1' sets the corresponding GPIO pin as output. 'Write '1' sets the corresponding GPIO pin as input. When write, update the output value. When read, get the input value. Write '1' will set GPIO output value. When read, get the GPIO output value. 'Write '1' clears corresponding GPIO output value. When read, get the GPIO output value. Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt. Each bit represents if there is a GPIO interrupt pending. time for which GPIO0 is set to output mode, after a start read DCON command is issued. The output time = (OUT_TIME+1)*30.5us. time for which GPIO0 should wait before reading DC_ON, after a start read DCON command is issued. The wait time = (WAIT_TIME+1)*30.5us. NOTE: wait_time must be strictly greater than out_time; interruption mode of GPIO0 in mode DC_ON detection. Write '1' to set GPIO0 to charger DCON detect mode. Write '1' to set GPO0 to charger watchdog mode. Write '1' to clear charger DCON detect mode of GPIO0. Write '1' to clear the charger watchdog mode of GPO0. Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles. 'Write '1' will set GPO output value. When read, get the GPO output value. 'Write '1' will clear GPO output value. When read, get the GPO output value. Set the direction of the GPIO n. 0 = output 1 = input 'Write '1' sets the corresponding GPIO pin as output. 'Write '1' sets the corresponding GPIO pin as input. When write, update the output value. When read, get the input value. Write '1' will set GPIO output value. When read, get the GPIO output value. 'Write '1' clears corresponding GPIO output value. When read, get the GPIO output value. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. Write '1' will set GPIO interrupt mask for falling edge and level low. When read, get the GPIO interrupt mask for falling edge and level low. Write '1' will clear GPIO interrupt mask for falling edge and level low. Write '1' will clear GPIO interrupt mask for falling edge and level low. Write '1' will enable debounce mechanism. Write '1' will enable debounce mechanism. Write '1' will disable debounce mechanism. Write '1' will disable debounce mechanism. Write '1' will set interruption mode to level. Write '1' will set interruption mode to level. Write '1' will set interruption mode to edge triggered. Write '1' will set interruption mode to edge triggered. Each bit represents if there is a GPIO interrupt pending. 'Write '1' will clear GPIO interrupt. count input triger number enable slave_mode trigger select auto preload value Center-aligned mode select 00: disable , other:enable counter dir , 0: cnt ++ , 1: cnt -- one pulse mode, 0:disable 1:enable update disable, 0:disable, 1:enable clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass counter enable, 0: disbale, 1:enable slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable bit type is changed from w1c to rc. user trigger gen no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti2 prescale, 01:0 div2, 10: div4, others: bypass ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti1 prescale, 01:0 div2, 10: div4, others: bypass ti2 polarity ti2 enable ti1 polarity ti1 enable cnt value cnt prescale value cnt max value ic1 capture value ic2 capture value ic1 compare value ic2 compare value cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 bit type is changed from w1c to rc. trig gens, when counter works in slave mode bit type is changed from w1c to rc. bit type is changed from w1c to rc. Input triger number count enable slave_mode trigger select auto preload value Center-aligned mode select 00: disable , other:enable counter dir , 0: cnt ++ , 1: cnt -- one pulse mode, 0:disable 1:enable update disable, 0:disable, 1:enable clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass counter enable, 0: disbale, 1:enable slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable bit type is changed from w1c to rc. user trigger gen no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[24] 0: output enable, 1 output disable bit[25] 0: use ti4, 1: use ti3 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[17] 0: output enable, 1 output disable bit[16] 0: use ti3, 1: use ti4 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 ti4 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti4 prescale, 01:0 div2, 10: div4, others: bypass ti3 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti3 prescale, 01:0 div2, 10: div4, others: bypass ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti2 prescale, 01:0 div2, 10: div4, others: bypass ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti1 prescale, 01:0 div2, 10: div4, others: bypass ti4 polarity ti4 enable ti3 polarity ti3 enable ti2 polarity ti2 enable ti1 polarity ti1 enable cnt value cnt prescale value cnt max value ic1 capture value ic2 capture value ic3 capture value ic4 capture value ic1 compare value ic2 compare value ic3 compare value ic4 compare value cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 bit type is changed from w1c to rc. trig gens, when counter works in slave mode bit type is changed from w1c to rc. bit type is changed from w1c to rc. I2C master enable, high active. I2C master interrupt enable, high active. This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared.

Example:
PCLK_MOD is 52 MHz, desired SCL is 100 KHz.
Prescale = 52MHz / (5 * 100KHz) -1 = 103. IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK. IRQ status bit. TIP, Transfer in progress. '1' when transferring data. '0' when transfer complete. AL,Arbitration lost. This bit is set when the I2C master lost arbitration. Busy,I2C bus busy. '1' after START signal detected. '0' after STOP signal detected. RxACK, Received acknowledge from slave. '1'= "No ACK" received. '0'= ACK received. Register writing is in process. '1'= Register writing is in process. '0'= Register writing is done. Byte to transmit via I2C.
for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit.
'1' = reading from slave.
'0' = writing to slave. Last byte received via I2C. ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1'). RD,read from slave, this bit is auto cleared. STO,generate stop condition, this bit is auto cleared. WR,write to slave, this bit is auto cleared. STA,generate (repeated) start condition, this bit is auto cleared. When write '1', clears a pending I2C interrupt. bit type is changed from w1c to rc. bit type is changed from w1c to rc. GPIO_0 shimit enable. GPIO_0 input enable. GPIO_0 driving strength. GPIO_0 force enable for pu/pd GPIO_0 PUll down GPIO_0 PUll up GPIO_0 force enable for outoen. GPIO_0 force outoen value. GPIO_0 force output value for output. GPIO_0 pin output value. GPIO_0 select GPIO_1 shimit enable. GPIO_1 input enable. GPIO_1 driving strength. GPIO_1 force enable for pu/pd GPIO_1 PUll down GPIO_1 PUll up GPIO_1 force enable for outoen. GPIO_1 force outoen value. GPIO_1 force output value for output. GPIO_1 pin output value. GPIO_1 select GPIO_2 shimit enable. GPIO_2 input enable. GPIO_2 driving strength. GPIO_2 force enable for pu/pd GPIO_2 PUll down GPIO_2 PUll up GPIO_2 force enable for outoen. GPIO_2 force outoen value. GPIO_2 force output value for output. GPIO_2 pin output value. GPIO_2 select GPIO_3 shimit enable. GPIO_3 input enable. GPIO_3 driving strength. GPIO_3 force enable for pu/pd GPIO_3 PUll down GPIO_3 PUll up GPIO_3 force enable for outoen. GPIO_3 force outoen value. GPIO_3 force output value for output. GPIO_3 pin output value. GPIO_3 select GPIO_4 shimit enable. GPIO_4 input enable. GPIO_4 driving strength. GPIO_4 force enable for pu/pd GPIO_4 PUll down GPIO_4 PUll up GPIO_4 force enable for outoen. GPIO_4 force outoen value. GPIO_4 force output value for output. GPIO_4 pin output value. GPIO_4 select GPIO_5 shimit enable. GPIO_5 input enable. GPIO_5 driving strength. GPIO_5 force enable for pu/pd GPIO_5 PUll down GPIO_5 PUll up GPIO_5 force enable for outoen. GPIO_5 force outoen value. GPIO_5 force output value for output. GPIO_5 pin output value. GPIO_5 select GPIO_6 shimit enable. GPIO_6 input enable. GPIO_6 driving strength. GPIO_6 force enable for pu/pd GPIO_6 PUll down GPIO_6 PUll up GPIO_6 force enable for outoen. GPIO_6 force outoen value. GPIO_6 force output value for output. GPIO_6 pin output value. GPIO_6 select GPIO_7 shimit enable. GPIO_7 input enable. GPIO_7 driving strength. GPIO_7 force enable for pu/pd GPIO_7 PUll down GPIO_7 PUll up GPIO_7 force enable for outoen. GPIO_7 force outoen value. GPIO_7 force output value for output. GPIO_7 pin output value. GPIO_7 select M_DQ_0 shimit enable. M_DQ_0 input enable. M_DQ_0 driving strength. M_DQ_0 force enable for pu/pd M_DQ_0 PUll down M_DQ_0 PUll up M_DQ_0 force enable for outoen. M_DQ_0 force outoen value. M_DQ_0 force output value for output. M_DQ_0 pin output value. M_DQ_0 select M_DQ_1 shimit enable. M_DQ_1 input enable. M_DQ_1 driving strength. M_DQ_1 force enable for pu/pd M_DQ_1 PUll down M_DQ_1 PUll up M_DQ_1 force enable for outoen. M_DQ_1 force outoen value. M_DQ_1 force output value for output. M_DQ_1 pin output value. M_DQ_1 select M_DQ_2 shimit enable. M_DQ_2 input enable. M_DQ_2 driving strength. M_DQ_2 force enable for pu/pd M_DQ_2 PUll down M_DQ_2 PUll up M_DQ_2 force enable for outoen. M_DQ_2 force outoen value. M_DQ_2 force output value for output. M_DQ_2 pin output value. M_DQ_2 select M_DQ_3 shimit enable. M_DQ_3 input enable. M_DQ_3 driving strength. M_DQ_3 force enable for pu/pd M_DQ_3 PUll down M_DQ_3 PUll up M_DQ_3 force enable for outoen. M_DQ_3 force outoen value. M_DQ_3 force output value for output. M_DQ_3 pin output value. M_DQ_3 select M_DQ_4 shimit enable. M_DQ_4 input enable. M_DQ_4 driving strength. M_DQ_4 force enable for pu/pd M_DQ_4 PUll down M_DQ_4 PUll up M_DQ_4 force enable for outoen. M_DQ_4 force outoen value. M_DQ_4 force output value for output. M_DQ_4 pin output value. M_DQ_4 select M_DQ_5 shimit enable. M_DQ_5 input enable. M_DQ_5 driving strength. M_DQ_5 force enable for pu/pd M_DQ_5 PUll down M_DQ_5 PUll up M_DQ_5 force enable for outoen. M_DQ_5 force outoen value. M_DQ_5 force output value for output. M_DQ_5 pin output value. M_DQ_5 select M_DQ_6 shimit enable. M_DQ_6 input enable. M_DQ_6 driving strength. M_DQ_6 force enable for pu/pd M_DQ_6 PUll down M_DQ_6 PUll up M_DQ_6 force enable for outoen. M_DQ_6 force outoen value. M_DQ_6 force output value for output. M_DQ_6 pin output value. M_DQ_6 select M_DQ_7 shimit enable. M_DQ_7 input enable. M_DQ_7 driving strength. M_DQ_7 force enable for pu/pd M_DQ_7 PUll down M_DQ_7 PUll up M_DQ_7 force enable for outoen. M_DQ_7 force outoen value. M_DQ_7 force output value for output. M_DQ_7 pin output value. M_DQ_7 select M_CS shimit enable. M_CS input enable. M_CS driving strength. M_CS force enable for pu/pd M_CS PUll down M_CS PUll up M_CS force enable for outoen. M_CS force outoen value. M_CS force output value for output. M_CS pin output value. M_CS select M_DM shimit enable. M_DM input enable. M_DM driving strength. M_DM force enable for pu/pd M_DM PUll down M_DM PUll up M_DM force enable for outoen. M_DM force outoen value. M_DM force output value for output. M_DM pin output value. M_DM select M_CLK shimit enable. M_CLK input enable. M_CLK driving strength. M_CLK force enable for pu/pd M_CLK PUll down M_CLK PUll up M_CLK force enable for outoen. M_CLK force outoen value. M_CLK force output value for output. M_CLK pin output value. M_CLK select M_CLKB shimit enable. M_CLKB input enable. M_CLKB driving strength. M_CLKB force enable for pu/pd M_CLKB PUll down M_CLKB PUll up M_CLKB force enable for outoen. M_CLKB force outoen value. M_CLKB force output value for output. M_CLKB pin output value. M_CLKB select M_DQS shimit enable. M_DQS input enable. M_DQS driving strength. M_DQS force enable for pu/pd M_DQS PUll down M_DQS PUll up M_DQS force enable for outoen. M_DQS force outoen value. M_DQS force output value for output. M_DQS pin output value. M_DQS select M_SPI_CLK shimit enable. M_SPI_CLK input enable. M_SPI_CLK driving strength. M_SPI_CLK force enable for pu/pd M_SPI_CLK PUll down M_SPI_CLK PUll up M_SPI_CLK force enable for outoen. M_SPI_CLK force outoen value. M_SPI_CLK force output value for output. M_SPI_CLK pin output value. M_SPI_CLK select M_SPI_CS shimit enable. M_SPI_CS input enable. M_SPI_CS driving strength. M_SPI_CS force enable for pu/pd M_SPI_CS PUll down M_SPI_CS PUll up M_SPI_CS force enable for outoen. M_SPI_CS force outoen value. M_SPI_CS force output value for output. M_SPI_CS pin output value. M_SPI_CS select M_SPI_D_0 shimit enable. M_SPI_D_0 input enable. M_SPI_D_0 driving strength. M_SPI_D_0 force enable for pu/pd M_SPI_D_0 PUll down M_SPI_D_0 PUll up M_SPI_D_0 force enable for outoen. M_SPI_D_0 force outoen value. M_SPI_D_0 force output value for output. M_SPI_D_0 pin output value. M_SPI_D_0 select M_SPI_D_1 shimit enable. M_SPI_D_1 input enable. M_SPI_D_1 driving strength. M_SPI_D_1 force enable for pu/pd M_SPI_D_1 PUll down M_SPI_D_1 PUll up M_SPI_D_1 force enable for outoen. M_SPI_D_1 force outoen value. M_SPI_D_1 force output value for output. M_SPI_D_1 pin output value. M_SPI_D_1 select M_SPI_D_2 shimit enable. M_SPI_D_2 input enable. M_SPI_D_2 driving strength. M_SPI_D_2 force enable for pu/pd M_SPI_D_2 PUll down M_SPI_D_2 PUll up M_SPI_D_2 force enable for outoen. M_SPI_D_2 force outoen value. M_SPI_D_2 force output value for output. M_SPI_D_2 pin output value. M_SPI_D_2 select M_SPI_D_3 shimit enable. M_SPI_D_3 input enable. M_SPI_D_3 driving strength. M_SPI_D_3 force enable for pu/pd M_SPI_D_3 PUll down M_SPI_D_3 PUll up M_SPI_D_3 force enable for outoen. M_SPI_D_3 force outoen value. M_SPI_D_3 force output value for output. M_SPI_D_3 pin output value. M_SPI_D_3 select GPIO_8 shimit enable. GPIO_8 input enable. GPIO_8 driving strength. GPIO_8 force enable for pu/pd GPIO_8 PUll down GPIO_8 PUll up GPIO_8 force enable for outoen. GPIO_8 force outoen value. GPIO_8 force output value for output. GPIO_8 pin output value. GPIO_8 select GPIO_9 shimit enable. GPIO_9 input enable. GPIO_9 driving strength. GPIO_9 force enable for pu/pd GPIO_9 PUll down GPIO_9 PUll up GPIO_9 force enable for outoen. GPIO_9 force outoen value. GPIO_9 force output value for output. GPIO_9 pin output value. GPIO_9 select GPIO_10 shimit enable. GPIO_10 input enable. GPIO_10 driving strength. GPIO_10 force enable for pu/pd GPIO_10 PUll down GPIO_10 PUll up GPIO_10 force enable for outoen. GPIO_10 force outoen value. GPIO_10 force output value for output. GPIO_10 pin output value. GPIO_10 select GPIO_11 shimit enable. GPIO_11 input enable. GPIO_11 driving strength. GPIO_11 force enable for pu/pd GPIO_11 PUll down GPIO_11 PUll up GPIO_11 force enable for outoen. GPIO_11 force outoen value. GPIO_11 force output value for output. GPIO_11 pin output value. GPIO_11 select GPIO_12 shimit enable. GPIO_12 input enable. GPIO_12 driving strength. GPIO_12 force enable for pu/pd GPIO_12 PUll down GPIO_12 PUll up GPIO_12 force enable for outoen. GPIO_12 force outoen value. GPIO_12 force output value for output. GPIO_12 pin output value. GPIO_12 select GPIO_13 shimit enable. GPIO_13 input enable. GPIO_13 driving strength. GPIO_13 force enable for pu/pd GPIO_13 PUll down GPIO_13 PUll up GPIO_13 force enable for outoen. GPIO_13 force outoen value. GPIO_13 force output value for output. GPIO_13 pin output value. GPIO_13 select GPIO_14 shimit enable. GPIO_14 input enable. GPIO_14 driving strength. GPIO_14 force enable for pu/pd GPIO_14 PUll down GPIO_14 PUll up GPIO_14 force enable for outoen. GPIO_14 force outoen value. GPIO_14 force output value for output. GPIO_14 pin output value. GPIO_14 select GPIO_15 shimit enable. GPIO_15 input enable. GPIO_15 driving strength. GPIO_15 force enable for pu/pd GPIO_15 PUll down GPIO_15 PUll up GPIO_15 force enable for outoen. GPIO_15 force outoen value. GPIO_15 force output value for output. GPIO_15 pin output value. GPIO_15 select GPIO_16 shimit enable. GPIO_16 input enable. GPIO_16 driving strength. GPIO_16 force enable for pu/pd GPIO_16 PUll down GPIO_16 PUll up GPIO_16 force enable for outoen. GPIO_16 force outoen value. GPIO_16 force output value for output. GPIO_16 pin output value. GPIO_16 select GPIO_17 shimit enable. GPIO_17 input enable. GPIO_17 driving strength. GPIO_17 force enable for pu/pd GPIO_17 PUll down GPIO_17 PUll up GPIO_17 force enable for outoen. GPIO_17 force outoen value. GPIO_17 force output value for output. GPIO_17 pin output value. GPIO_17 select GPIO_18 shimit enable. GPIO_18 input enable. GPIO_18 driving strength. GPIO_18 force enable for pu/pd GPIO_18 PUll down GPIO_18 PUll up GPIO_18 force enable for outoen. GPIO_18 force outoen value. GPIO_18 force output value for output. GPIO_18 pin output value. GPIO_18 select GPIO_19 shimit enable. GPIO_19 input enable. GPIO_19 driving strength. GPIO_19 force enable for pu/pd GPIO_19 PUll down GPIO_19 PUll up GPIO_19 force enable for outoen. GPIO_19 force outoen value. GPIO_19 force output value for output. GPIO_19 pin output value. GPIO_19 select GPIO_20 shimit enable. GPIO_20 input enable. GPIO_20 driving strength. GPIO_20 force enable for pu/pd GPIO_20 PUll down GPIO_20 PUll up GPIO_20 force enable for outoen. GPIO_20 force outoen value. GPIO_20 force output value for output. GPIO_20 pin output value. GPIO_20 select GPIO_21 shimit enable. GPIO_21 input enable. GPIO_21 driving strength. GPIO_21 force enable for pu/pd GPIO_21 PUll down GPIO_21 PUll up GPIO_21 force enable for outoen. GPIO_21 force outoen value. GPIO_21 force output value for output. GPIO_21 pin output value. GPIO_21 select GPIO_22 shimit enable. GPIO_22 input enable. GPIO_22 driving strength. GPIO_22 force enable for pu/pd GPIO_22 PUll down GPIO_22 PUll up GPIO_22 force enable for outoen. GPIO_22 force outoen value. GPIO_22 force output value for output. GPIO_22 pin output value. GPIO_22 select GPIO_23 shimit enable. GPIO_23 input enable. GPIO_23 driving strength. GPIO_23 force enable for pu/pd GPIO_23 PUll down GPIO_23 PUll up GPIO_23 force enable for outoen. GPIO_23 force outoen value. GPIO_23 force output value for output. GPIO_23 pin output value. GPIO_23 select GPIO_24 shimit enable. GPIO_24 input enable. GPIO_24 driving strength. GPIO_24 force enable for pu/pd GPIO_24 PUll down GPIO_24 PUll up GPIO_24 force enable for outoen. GPIO_24 force outoen value. GPIO_24 force output value for output. GPIO_24 pin output value. GPIO_24 select GPIO_25 shimit enable. GPIO_25 input enable. GPIO_25 driving strength. GPIO_25 force enable for pu/pd GPIO_25 PUll down GPIO_25 PUll up GPIO_25 force enable for outoen. GPIO_25 force outoen value. GPIO_25 force output value for output. GPIO_25 pin output value. GPIO_25 select GPIO_26 shimit enable. GPIO_26 input enable. GPIO_26 driving strength. GPIO_26 force enable for pu/pd GPIO_26 PUll down GPIO_26 PUll up GPIO_26 force enable for outoen. GPIO_26 force outoen value. GPIO_26 force output value for output. GPIO_26 pin output value. GPIO_26 select GPIO_27 shimit enable. GPIO_27 input enable. GPIO_27 driving strength. GPIO_27 force enable for pu/pd GPIO_27 PUll down GPIO_27 PUll up GPIO_27 force enable for outoen. GPIO_27 force outoen value. GPIO_27 force output value for output. GPIO_27 pin output value. GPIO_27 select GPIO_28 shimit enable. GPIO_28 input enable. GPIO_28 driving strength. GPIO_28 force enable for pu/pd GPIO_28 PUll down GPIO_28 PUll up GPIO_28 force enable for outoen. GPIO_28 force outoen value. GPIO_28 force output value for output. GPIO_28 pin output value. GPIO_28 select GPIO_29 shimit enable. GPIO_29 input enable. GPIO_29 driving strength. GPIO_29 force enable for pu/pd GPIO_29 PUll down GPIO_29 PUll up GPIO_29 force enable for outoen. GPIO_29 force outoen value. GPIO_29 force output value for output. GPIO_29 pin output value. GPIO_29 select GPIO_30 shimit enable. GPIO_30 input enable. GPIO_30 driving strength. GPIO_30 force enable for pu/pd GPIO_30 PUll down GPIO_30 PUll up GPIO_30 force enable for outoen. GPIO_30 force outoen value. GPIO_30 force output value for output. GPIO_30 pin output value. GPIO_30 select GPIO_31 shimit enable. GPIO_31 input enable. GPIO_31 driving strength. GPIO_31 force enable for pu/pd GPIO_31 PUll down GPIO_31 PUll up GPIO_31 force enable for outoen. GPIO_31 force outoen value. GPIO_31 force output value for output. GPIO_31 pin output value. GPIO_31 select GPIO_32 shimit enable. GPIO_32 input enable. GPIO_32 driving strength. GPIO_32 force enable for pu/pd GPIO_32 PUll down GPIO_32 PUll up GPIO_32 force enable for outoen. GPIO_32 force outoen value. GPIO_32 force output value for output. GPIO_32 pin output value. GPIO_32 select GPIO_33 shimit enable. GPIO_33 input enable. GPIO_33 driving strength. GPIO_33 force enable for pu/pd GPIO_33 PUll down GPIO_33 PUll up GPIO_33 force enable for outoen. GPIO_33 force outoen value. GPIO_33 force output value for output. GPIO_33 pin output value. GPIO_33 select SWCLK shimit enable. SWCLK input enable. SWCLK driving strength. SWCLK force enable for pu/pd SWCLK PUll down SWCLK PUll up SWCLK force enable for outoen. SWCLK force outoen value. SWCLK force output value for output. SWCLK pin output value. SWCLK select SWDIO shimit enable. SWDIO input enable. SWDIO driving strength. SWDIO force enable for pu/pd SWDIO PUll down SWDIO PUll up SWDIO force enable for outoen. SWDIO force outoen value. SWDIO force output value for output. SWDIO pin output value. SWDIO select SIM_CLK_0 shimit enable. SIM_CLK_0 input enable. SIM_CLK_0 driving strength. SIM_CLK_0 force enable for pu/pd SIM_CLK_0 PUll down SIM_CLK_0 PUll up SIM_CLK_0 force enable for outoen. SIM_CLK_0 force outoen value. SIM_CLK_0 force output value for output. SIM_CLK_0 pin output value. SIM_CLK_0 select SIM_RST_0 shimit enable. SIM_RST_0 input enable. SIM_RST_0 driving strength. SIM_RST_0 force enable for pu/pd SIM_RST_0 PUll down SIM_RST_0 PUll up SIM_RST_0 force enable for outoen. SIM_RST_0 force outoen value. SIM_RST_0 force output value for output. SIM_RST_0 pin output value. SIM_RST_0 select SIM_DIO_0 shimit enable. SIM_DIO_0 input enable. SIM_DIO_0 driving strength. SIM_DIO_0 force enable for pu/pd SIM_DIO_0 PUll down SIM_DIO_0 PUll up SIM_DIO_0 force enable for outoen. SIM_DIO_0 force outoen value. SIM_DIO_0 force output value for output. SIM_DIO_0 pin output value. SIM_DIO_0 select SIM_CLK_1 shimit enable. SIM_CLK_1 input enable. SIM_CLK_1 driving strength. SIM_CLK_1 force enable for pu/pd SIM_CLK_1 PUll down SIM_CLK_1 PUll up SIM_CLK_1 force enable for outoen. SIM_CLK_1 force outoen value. SIM_CLK_1 force output value for output. SIM_CLK_1 pin output value. SIM_CLK_1 select SIM_RST_1 shimit enable. SIM_RST_1 input enable. SIM_RST_1 driving strength. SIM_RST_1 force enable for pu/pd SIM_RST_1 PUll down SIM_RST_1 PUll up SIM_RST_1 force enable for outoen. SIM_RST_1 force outoen value. SIM_RST_1 force output value for output. SIM_RST_1 pin output value. SIM_RST_1 select SIM_DIO_1 shimit enable. SIM_DIO_1 input enable. SIM_DIO_1 driving strength. SIM_DIO_1 force enable for pu/pd SIM_DIO_1 PUll down SIM_DIO_1 PUll up SIM_DIO_1 force enable for outoen. SIM_DIO_1 force outoen value. SIM_DIO_1 force output value for output. SIM_DIO_1 pin output value. SIM_DIO_1 select Number of key in the keypad Number of key in the low data register Number of key in the high data register For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) :
0 = Released
1 = Pressed For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn):
0 = Released
1 = Pressed For keys in lines status
0 = Released
1 = Pressed Indicate Key ON pressing status :
0 = Release
1 = Pressed This bit enables key detection. If this bit is '0', the key detection function is disabled. Key ON is an exception, it can be still detected and generate key interrupt even if KP_En = '0', however in this case, the debouncing time configuration in key control register is ignored and the key ON state is considerred to be stable if it keeps same in consecutive 2 cycles of 16KHz clock.

0 = keypad disable
1 = keypad enable De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms. Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. each bit masks one input lines.
'1' = enabled
'0' = disabled
The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset.
Key_In 0: BOOT_MODE_NO_AUTO_PU.
Key_In 1: BOOT_MODE_FORCE_MONITOR.
Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE.
Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE.
Key_In 4: reserved each bit masks one output lines.
'1' = enabled
'0' = disabled This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by event1 (all keys release event).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time.
0 = keypad interval irq disable
1 = keypad interval irq enable keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. keypad event1(all keys release event) IRQ cause. keypad interval irq cause. keypad event0(key press or key release event, not including all keys release which is event1) irq status. keypad event1(all keys release event) irq status. keypad interval irq status. Write '1' to this bit clears key IRQ. Lps Skip Frame Enable. When enabled the frame interrupt are masked until the programmed number of frames are elapsed. This is done by masking the frame interrupt line from the regular TCU counter, and counting the frames. Also when activating the LowPower SkipFrame the frame counter is tranfered to the low power counter that will update it based on the 32kHz Clock. Controls the Lps Low Power Counters (counters at 32kHz) usage. Enable fake Fint used with wakeupNumber=0. Enable fake Fint when sys_sf_frame_count>=cfg_sf_frame. Default sys_sf_frame_count>cfg_sf_frame. Lps Skip Frame Ready, status of the state machines to keep valid state between system clock and 32Khz clock. Must read as '1' before entering Low Power Skip Frame or Calibration mode. '1' when Lps Skip Frame Low Power Counters are Running. When entering Low Power Skip Frame, the counters are not immediately started, they wait for the nextFrame interrupt. Reading this status allow to know if the counters are running, and the System Clock can be safely disabled. '1' when the Lps Skip Frame Calibration is Done. '1' when the Lps Skip Frame Power-up sequence frame is reached. '1' when tcu counter is restarted. Number of frames to Skip. If the power up sequence is enabled, frames are skipped until both this number is reached and the powerup sequence has finished. Note: The power up sequence must be Done before the the frame LPS_SF_Frame ends. Number of frames before activating the Power-up sequence. For LowPower SkipFrame mode: Value to restart TCU (and frame interrupt generation) on the system clock counter after a low power phase. For Calibration mode: number of 32k cycles for the calibration. Value of the frame period in system clock count. The rate is the number of System Clocks per 32kHz Clocks. Integer part of the rate. Fractional part of the rate. Current number of elapsed frames. Valid when Skip Frame is Enabled. Value of the system clock counter at the end of calibration (when CalibrationDone is '1' in LPS_SF_Status register). The hardware behind it is reused during other operation, reading that register at any other time will return an undefined value. 1 when the IRQ was triggered because the calibration is done. Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the Slow Counter started. Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the Power-Up frame was reached. Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the tcu counter was restarted. Write 1 in cause or status bit to clear. 1 when the calibration is done. Write 1 in cause or status bit to clear. 1 when the Slow Counter started. Write 1 in cause or status bit to clear. 1 when the Power-Up frame was reached. Write 1 in cause or status bit to clear. 1 when the tcu counter was restarted. Write 1 in cause or status bit to clear. when 1 the LPS_IRQ_Calibration_Done is enabled. when 1 the LPS_IRQ_Slow_Running is enabled. when 1 the LPS_IRQ_PU_Reached is enabled. when 1 the LPS_IRQ_TCU_Restart is enabled. 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch0; 0:disable ch0; the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch1; 0:disable ch1; the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch2; 0:disable ch2; the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch3; 0:disable ch3; the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu write address is 0x1000_0024,then after med , then address is is 0x2000_0024 the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF bit type is changed from wc to rc. 1:active,clear the 0x118 address bit31~bit12; bit type is changed from wc to rc. 1:active,clear the simon core bit type is changed from wc to rc. 1:active,clear the med inner write ram bit type is changed from wc to rc. 1:active,clear the med inner read ram can force the med clk gate always on, then the clk freerun when the med send cmd to write flash data, and the slave happen bus error, then the med will back the slave bus error to master. when the med send cmd to read flash data, and the slave happen bus error, then the med will back the slave bus error to master. enable the med module ahb bus error,when the master access to med, and the access address is error, the med will generate the buss error to master. 1:sel the key from efuse, 0: key from soft ware reserved enable med ahb addr out of range all channel enable med error response int enable med channel3 addr error int enable med channel2 addr error int enable med channel1 addr error int enable med channel0 addr error int enable med write done int reserved med ahb addr out of range all channel status med error response int status med channel3 addr error int status med channel2 addr error int status med channel1 addr error int status med channel0 addr error int status med write done int status reserved bit type is changed from wc to rc. clear med ahb addr out of range all channel status bit type is changed from wc to rc. clear med error response int bit type is changed from wc to rc. clear med channel3 addr error int bit type is changed from wc to rc. clear med channel2 addr error int bit type is changed from wc to rc. clear med channel1 addr error int bit type is changed from wc to rc. clear med channel0 addr error int bit type is changed from wc to rc. clear med write done int when master send error address, the addr store in this reg reserved software only config 32bit key, hardware copy four time,{med_soft_cfg_key,med_soft_cfg_key,med_soft_cfg_key,med_soft_cfg_key}=128bit,then send to simon bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wc to rc. bit type is changed from wr to rw. bit type is changed from wc to rc. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is 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changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to 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changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. bit type is changed from wr to rw. default r address 0 register(4K-Byte address, bit 24 ~ bit 12). bit type is changed from wr to rw. default w address 0 register(4K-Byte address, bit 24 ~ bit 12). bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. clock gate bypass bit type is changed from wr to rw. Port 0 write address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 write address miss int write-clear Port 0 write address miss original int 1: Address Miss 0: Normal Port 0 write address miss final int 1: Address Miss 0: Normal bit type is changed from wr to rw. Port 0 read address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read address miss int write-clear Port 0 read address miss original int 1: Address Miss 0: Normal Port 0 read address miss final int 1: Address Miss 0: Normal Port 0 write channel address, 4K-Byte Port 0 write channel id, MSB is prot[1] Port 0 read channel address, 4K-Byte Port 0 read channel id, MSB is prot[1] bit type is changed from wr to rw. Segment default first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment default last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 3 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from wr to rw. default r address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. default w address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. clock gate bypass bit type is changed from wr to rw. Port 0 write address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 write address miss int write-clear Port 0 write address miss original int 1: Address Miss 0: Normal Port 0 write address miss final int 1: Address Miss 0: Normal bit type is changed from wr to rw. Port 0 read address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read address miss int write-clear Port 0 read address miss original int 1: Address Miss 0: Normal Port 0 read address miss final int 1: Address Miss 0: Normal Port 0 write channel address, 4K-Byte Port 0 write channel id, MSB is prot[1] Port 0 read channel address, 4K-Byte Port 0 read channel id, MSB is prot[1] bit type is changed from wr to rw. Segment default first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment default last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. default r address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. default w address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. clock gate bypass bit type is changed from wr to rw. Port 0 write address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 write address miss int write-clear Port 0 write address miss original int 1: Address Miss 0: Normal Port 0 write address miss final int 1: Address Miss 0: Normal bit type is changed from wr to rw. Port 0 read address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read address miss int write-clear Port 0 read address miss original int 1: Address Miss 0: Normal Port 0 read address miss final int 1: Address Miss 0: Normal Port 0 write channel address, 4K-Byte Port 0 write channel id, MSB is prot[1] Port 0 read channel address, 4K-Byte Port 0 read channel id, MSB is prot[1] bit type is changed from wr to rw. Segment default first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment default last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. default r address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. default w address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. clock gate bypass bit type is changed from wr to rw. Port 0 write address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 write address miss int write-clear Port 0 write address miss original int 1: Address Miss 0: Normal Port 0 write address miss final int 1: Address Miss 0: Normal bit type is changed from wr to rw. Port 0 read address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read address miss int write-clear Port 0 read address miss original int 1: Address Miss 0: Normal Port 0 read address miss final int 1: Address Miss 0: Normal Port 0 write channel address, 4K-Byte Port 0 write channel id, MSB is prot[1] Port 0 read channel address, 4K-Byte Port 0 read channel id, MSB is prot[1] bit type is changed from wr to rw. Segment default first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment default last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. default r address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. default w address 0 register(4K-Byte address, bit 17 ~ bit 12). bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. clock gate bypass bit type is changed from wr to rw. Port 0 write address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 write address miss int write-clear Port 0 write address miss original int 1: Address Miss 0: Normal Port 0 write address miss final int 1: Address Miss 0: Normal bit type is changed from wr to rw. Port 0 read address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read address miss int write-clear Port 0 read address miss original int 1: Address Miss 0: Normal Port 0 read address miss final int 1: Address Miss 0: Normal Port 0 write channel address, 4K-Byte Port 0 write channel id, MSB is prot[1] Port 0 read channel address, 4K-Byte Port 0 read channel id, MSB is prot[1] bit type is changed from wr to rw. Segment default first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment default last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Default Segment write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 0 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 1 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Read Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can read 0: Master can't read bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 0~31. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 32~63. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 64~95. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 96~127. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 128~159. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 160~191. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 192~223. 1: Master can write 0: Master can't write bit type is changed from wr to rw. Segment 2 Write Master ID select, one bit indicates a master ID, master ID from 224~255. 1: Master can write 0: Master can't write NB accelerator Enable when enable is low, it would wait to the last DMA transfer to go back to idle status. Command Length (unit DW) Number of Command Command start address(unit: byte in DW aligned) Maximum time out value in AHB clock unit Default:(0) Disable Unit in AHB clock Start address limit0: Valid DMA Output address must be not less than Start address limit End address limit0: Valid DMA Output address must be less than End start address limit Maximum time out value in AHB clock unit: Default:(0) Disable Unit in AHB clock Start address limit1: Valid DMA Output address must be not less than Start address limit End address limit1: Valid DMA Output address must be less than End start address limit Output address Status 0: Normal 1: Error Header Status 0: Normal 1: Error Timeout Error 0: DMA Normal 1: DMA Error Bit 0: Read DMA Error Bit 1: Write DMA Error Bit 2: Top Error Current Command Count 0: Idle 1: On-going This bit is read write 1 clear 0: No Done 1: Done Write DMA control status report Read DMA control status report MODE0~3: NA MODE 4: report Max value of small window MODE 5: bit[0]: timeout status for wait HW done 1: timeout 0: normal MODE 7: Maximum value of all square sums in data window MODE 9: Maximum value MODE0~3: NA MODE 4: report Max value index of small window MODE 5: NA MODE 7: Maximum value's index of all square sums in data window MODE 9: Maximum value index MODE0~3: NA MODE 4: report Max value of large window MODE 5: NA MODE0~3: NA MODE 4: report Max value index of large window MODE 5: NA MODE0~3: NA MODE 4: report Max value value of small window MODE 5: bit[0]: timeout status for wait HW done 1: timeout 0: normal MODE 7: Maximum value of all square sums in data window MODE 9: Maximum value MODE0~3: NA MODE 4: report Max value index of small window MODE 5: NA MODE 7: Maximum value's index of all square sums in data window MODE 9: Maximum value index MODE0~3: NA MODE 4: report Max value of large window MODE 5: NA MODE0~3: NA MODE 4: report Max value index of large window MODE 5: NA RX dump enable (Auto clear when the RX dump done asserted) Start offset of subframe. Range is 0 to 9. Start offset of sample. Range is from 0 to 1919. Number of CA = 1-16 Downsample index 0: No Downsample 1: Downsample x 2 2: Downsample x 4 3: Downsample x 8 Number of CA = 1-16 DMA timeout value Default : 0xFFFF_FFFF 0: Disable CA RX dump Memory base Address in byte (with DW alignment) Each CA RX memory depth (with 16 IQ data alignment only) in DW Each CA RX memory length (with 16 IQ data alignment only) in DW If Length = 0, length = infinite until disable Each CA RX memory offset (with 16 IQ data alignment only) in byte RX memory dump transfer current memory address RX memory dump transfer current count Indicate how many data are transferred in a AHB burst cycle Indicate the cause of DMA done 0: DMA transfer success done 1: DMA done caused by i_dma_stop 2: DMA done caused by timeout For DMA debug: [4:0] dma controller state machine [5] dma_rfifo0_rdy [6] dma_rfifo1_rdy [7] dma_wfifo_rdy Capture FIFO Overflow 0: Normal 1: Error DMA Timeout Error 0: Normal 1: Error 0: Idle 1: Process (This bit is read write 1 clear) 0: No Done 1: Done Timer status control 0. It can control frame structure for MCA IFFT process. Maximum Sample number 0 Timer status control 0. It can control frame structure for MCA IFFT process. Maximum Sample number 1 Timer status control 1. It can control frame structure for MCA IFFT process. Maximum symbol Index Valid:0 to 31 for 0 is maximum symbol = 1 Symbol bitmap for maximum sample number For Bit i: 0: Maximum Sample number 0 (rMAX_SAMPLE_NUM0) 1: Maximum Sample number 1 (rMAX_SAMPLE_NUM1) DMA Transferred TX sample counter DMA Transferred TX symbol counter DMA Transferred TX subframe counter TX dump enable (Auto clear when the TX dump done asserted) 0: Disable 1: Enable Prefetch Start offset of subframe. Range is 0 to 9. Prefetch Start offset of sample. Range is from 0 to 1919. Start offset of subframe. Range is 0 to 9. Start offset of sample. Range is from 0 to 1919. Subsample Offset Delay for TX transmission Range: 0 - 511 (NB clock unit) Upsample index with zero insertion 0: No Upsample 1: Upsample x 2 2: Upsample x 4 3: Not support Number of CA = 1-16 Control the number of zero inserted at the end of the TX transmission. Remark: stop or disable command would not insert zero at the end. Valid: 0-511 DMA timeout value Default : 0xFFFF_FFFF 0: Disable CA TX dump Memory base Address in byte (with DW alignment) Each CA TX memory depth (with 16 IQ data alignment only) in DW Each CA TX memory length (with 16 IQ data alignment only) in DW If Length = 0, length = infinite until disable Each CA TX memory offset address (with 8 IQ data DW alignment only) in byte Stop offset of sample. Range is from 0 to 1919. Stop offset of subframe. Range is 0 to 9. CA TX dump stop position enable. Auto clear when the ca_tx_dump_done is asserted 0: Disable 1: Enable TX output data checksum enable 1: enable 0: disable RX memory dump transfer current count TX output data checksum counter TX memory dump transfer current memory address TX memory dump transfer current count - Indicate how many data are transferred in a AHB burst cycle - - - Indicate the cause of DMA done 0: DMA transfer success done 1: DMA done caused by i_dma_stop 2: DMA done caused by timeout - For DMA debug: -[4:0] dma controller state machine -[5] dma_rfifo0_rdy -[6] dma_rfifo1_rdy -[7] dma_wfifo_rdy - - - - IFFT ready signal is not high before TX dump prefetch timing - - - Read FIFO Underflow -0: Normal -1: Error - - - - DMA Timeout Error 0: Idle 1: Process (This bit is read write 1 clear) 0: No Done 1: Done PSS Enable 1'b0: Stop PSS calculation 1'b1: Start PSS calculation PSS hypothesis number PSS output ping-pong buffer selection 1'b1:Select the pong buffer as the first output buffer 1'b0: Select the ping buffer as the first output buffer PSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. PSS start offset of subframe. Range is from 0 to 9. PSS internal sub frame counter(from 0 to 9) Indicate the buffer selection on current interrupt 1'b0: buffer0 is selection 1'b1: buffer1 is selection PSS output buffer 0 status. Clear by DSP or MCU 1'b1: buffer 0 is ready. 1'b0:buffer0 is idle PSS output buffer 0 status. 1'b1: buffer 0 is over written. 1'b0: buffer 0 is normal PSS output buffer 1 status. Clear by DSP or MCU 1'b1: buffer 1 is ready. 1'b0:buffer 1 is idle PSS output buffer 1 status. 1'b1: buffer 1 is over written. 1'b0: buffer 1 is normal PSS calculation done status. Update very 1ms and clear by DSP or MCU. 1'b1: PSS calculation done 1'b0: PSS is idle or under calculating PSS write memory arbitration error status. 1'b1: the memory has conflict 1'b0: the memory is normal bit8: pss final output data non-zero status bit7: pss 148x40 memory out data non-zero status bit6: pss 148x40 memory in data non-zero status bit5: pss power non-zero status bit4: pss 1312x24 memory out data non-zero status bit3: pss 1312x24 memory in data non-zero status bit2: pss in local sequence non-zero status bit1: pss_corr_calc in data non-zero status bit0: pss_deci in data non-zero status PSS sample position for Pu of hypothesis 0 PSS sample position for Pu of hypothesis 1 PSS sample position for Pu of hypothesis 2 PSS sample position for Pu of hypothesis 3 PSS sample position for Pu of hypothesis 0 PSS sample position for Pu of hypothesis 1 PSS sample position for Pu of hypothesis 2 PSS sample position for Pl of hypothesis 0 PSS sample position for Pl of hypothesis 1 PSS sample position for Pl of hypothesis 2 PSS sample position for Pl of hypothesis 3 PSS sample position for Pl of hypothesis 4 PSS sample position for Pl of hypothesis 5 PSS sample position for Pl of hypothesis 6 PSS set 0 coefficient for hypothesis 0 PSS set 0 coefficient for hypothesis 1 PSS set 0 coefficient for hypothesis 2 PSS set 0 coefficient for hypothesis 3 PSS set 0 coefficient for hypothesis 4 PSS set 0 coefficient for hypothesis 5 PSS set 0 coefficient for hypothesis 7 PSS set 1 coefficient for hypothesis 0 PSS set 1 coefficient for hypothesis 1 PSS set 0 coefficient for hypothesis 2 PSS set 0 coefficient for hypothesis 3 PSS set 1 coefficient for hypothesis 4 PSS set 1 coefficient for hypothesis 5 PSS set 0 coefficient for hypothesis 6 Real part of the local sequence 0 Imag part of the local sequence 0 Real part of the local sequence 1 Imag part of the local sequence 1 Real part of the local sequence 2 Imag part of the local sequence 2 Real part of the local sequence 3 Imag part of the local sequence 3 Real part of the local sequence 4 Imag part of the local sequence 4 Real part of the local sequence 5 Imag part of the local sequence 5 Real part of the local sequence 6 Imag part of the local sequence 6 Start trigger of one CFO calculation process by writing "1" to this register CFO data capture start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. CFO data capture start offset of sub-frame. Range is from 0 to 13. CFO calculation start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. CFO calculation start offset of sub-frame. Range is from 0 to 13. Rotated frequency bin number when 'rCFO_MODE=0'. 1: Normal mode. CFO module only deal with 1 frequency bin(f0) and 9 sampling positions(Tau). 147 correlation results are reported to corresponding ram at most. 0: Searching mode. CFO module deal with 1~7 frequency bins(f0~6) and 21 sampling positions(Tau). 9 correlation results are reported to corresponding registers. Start write address of CFO correlation results' reporting ram Correlation results truncation (32bits to 16bits). 0:>>8 1:>>7 2:>>6 3:>>5 4:>>4 5:>>3 6:>>2 7:>>1 Tau number of CFO correlation when rCFO_MODE=0. Sampling position start offset for bin f0 Sampling position start offset for bin f1 Sampling position start offset for bin f2 Sampling position start offset for bin f3 Sampling position start offset for bin f4 Sampling position start offset for bin f5 Sampling position start offset for bin f6 The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). 'Tsa' means decimation with 8. [31:16]:Imag part [15:0]: Real part CFO calculation done status. Clear by DSP or MCU. 1'b1: CFO calculation done 1'b0: CFO is idle or under calculating Memory request error for writing of CFO reporting ram when 'rCFO_MOED=0' 0: Normal 1: Error Bit 2: DSP control bus error Bit 1: accelerator memory access collusion SSS Enable 1'b0:Stop SSS calculation 1'b1: Start SSS calculation SSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. SSS start offset of subframe. Range is from 0 to 9. SSS start calculation offset of sample within a subframe. Based on 1.92MHz. Range is from 0 to 1920. SSS start calculation offset of subframe. Range is from 0 to 9. Real part of SSS phase shift Imag part of SSS phase shift Real part of SSS phase shift 1 Imag part of SSS phase shift 1 Real part of SSS phase shift 2 Imag part of SSS phase shift 2 Real part of SSS phase shift 3 Imag part of SSS phase shift 3 Real part of SSS phase shift 4 Imag part of SSS phase shift 4 Real part of SSS phase shift 5 Imag part of SSS phase shift 5 Real part of SSS phase shift 6 Imag part of SSS phase shift 6 Real part of SSS phase shift 7 Imag part of SSS phase shift 7 Real part of SSS phase shift 8 Imag part of SSS phase shift 8 Real part of SSS phase shift 9 Imag part of SSS phase shift 9 Real part of SSS phase shift 10 Imag part of SSS phase shift 10 SSS internal sub frame counter(from 0 to 9) global sample count value at SSS subframe start global subframe count value at SSS subframe start Global radio frame count value at SSS subframe start Indicate the buffer selection on current interrupt 1'b0: MEM0 is selection 1'b1: MEM1 is selection RESERVED SSS output buffer 0 status. Clear by DSP or MCU bit 2: 1'b1: MEM2 or MEM0 is ready.1'b0:buffer0 is idle SSS output buffer 0 status. bit 3: 1'b1: MEM2 or MEM0 is over written. 1'b0: buffer 0 is normal SSS output buffer 1 status. Clear by DSP or MCU bit 4: 1'b1: MEM3 or MEM1 is ready.1'b0:buffer1 is idle SSS output buffer 1 status. bit 5: 1'b1: MEM3 or MEM1 is over written. 1'b0: buffer 1 is normal SSS calculation done status. Update very 1ms and clear by DSP or MCU. 1'b1: SSS calculation done 1'b0: SSS is idle or under calculating SSS write memory arbitration error status. 0: Normal 1: Error Bit 7: DSP control bus error Bit 8: accelerator memory access collusion OFDM symbol CP offset which use to locate the FFT windows start position for serving cell. Value:[0:9] FFT result scaling 3'd0: 2^-3 3'd1: 2^-2 3'd2: 2^-1 3'd3: 2^0 3'd4: 2^1 3'd5: 2^2 Correlation result sScaling for both power and correlation 3'd0: 20 3'd1: 2-1 3'd2: 2-2 3'd3: 2-3 3'd4: 2-4 3'd5: 2-5(Default) 3'd6: 2-6 3'd7: 2-7 Cyclic shift value It is used when rSSS_CYCLIC_SHIFT_FIX_EN = 1'b1.Rang is from 0 to 2. Fix cyclic shift enable PCI ID It is used when rSSS_PCI_ID_FIX_RN = 1'b1 or rSSS_SIC_EN = 1'b1. Range is from 0 to 503. Fix PCI ID Enable. Reserved SIC Enable Used for succesive interference cancellation. SSS output ping-pong buffer selection 1'b1:Select the pong buffer as the first output buffer 1'b0: Select the ping buffer as the first output buffer Scaling for correlation only 3'd0: 2-4 3'd1: 2-3 3'd2: 2-2 3'd3: 2-1 3'd4: 20(Default) 3'd5: 21 3'd6: 22 3'd7: 23 SSS total power "Search 16peak" accelerator enable When enable is low, it would wait to the last DMA transfer to go back to idle status 1: enable 0: disable 2'b00: continue mode(keep last table then do peaks searching) 2'b01: reset mode(reset table then do peaks searching) 2'b10: load mode(load a table from memory then do peaks searching) 2'b11: NA Start AHB address for loading a peak value table. It is used only when "rS16PEAK_TAB_CTRL=2'b10" Searching window start index Searching window size Start AHB address for reading searching window data Start AHB address for writing 16 max values and their indexes Up limit value for DMA timeout counter When this register is set to 0, function of timeout is disabled Up limit value for "search 16peak" module's timeout counter When this register is set to 0, function of timeout is disabled Status reporting register for FIFO part in "search 16peak" Status reporting register for AHB controlling part in "search 16peak" Reserved Indicating whether accelerator is on or not 1: ongoing 0: idle Indicating whether accelerator is timeout or not 1: timeout 0: normal Indicating whether output table buffer is updated 1: updated 0: not updated Reprot "serch 16peak" done status, write '1' to clear this status. 1: done 0: not done RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. RX interrupt output OS 0 - 127 Global timer sample rate per input clock source 0: 32 NB clock for 1 sample in global counter (Legacy Mode) 1: 64 NB clock for 1 sample in global counter (L230 Mode) 2: 128 clock for 1 sample in global counter 3: 256 clock for 1 sample in global counter 4: 512 clock for 1 sample in global counter Rx data input sample rate in global sample unit 0: 1 Global Counter Sample (1.92MHz - Legacy Mode) 1: 2 Global Counter Sample (960 Khz) 2: 4 Global Counter Sample (480 Khz) 3: 8 Global Counter Sample (240 Khz - L230 Mode) 4: 16 Global Counter Sample (120 Khz) 5: 32 Global Counter Sample (60 Khz) Tx data output sample rate in global sample unit 0: 1 Global Counter Sample (1.92MHz - Legacy Mode) 1: 2 Global Counter Sample (960 Khz) 2: 4 Global Counter Sample (480 Khz) 3: 8 Global Counter Sample (240 Khz - L230 Mode) 4: 16 Global Counter Sample (120 Khz) 5: 32 Global Counter Sample (60 Khz) RX interrupt DSP bitmap subframe mask from 0 to 9. LSB is subframe 0. RX interrupt MCU bitmap subframe mask from 0 to 9. LSB is subframe 0. RX adjustment subframe count from 0 - 9 (auto clear in next subframe) RX adjustment symbol count from 0 - 13 (auto clear in next subframe) RX adjustment symbol direction (auto clear in next subframe) 0: advance 1: postpone RX coarse adjustment sample count from 0 - 138 in (chip unit) - (auto clear in next subframe) RX coarse adjustment sample direction (auto clear in next subframe) 0: advance 1: postpone NB mode: RX fine adjustment sample count from 0 - 9 in (chip unit) 230 mode: RX fine adjustment sample count from 0 - 128 in (chip unit) RX fine adjustment sample direction (auto clear in next subframe) 0: advance 1: postpone RX interrupt symbol number 0-13 RX interrupt symbol number 0-13 RX interrupt buffer index Mirror rRX_INT_BUF_IDX_MCU register RX interrupt symbol number 0-13 RX interrupt symbol number 0-13 RX interrupt buffer index RX SFN number 0-1023 global sample count value at RX subframe start global subframe count value at RX subframe start global sample count value at RX subframe start global sample count value at RX radio frame start global subframe count value at RX radio frame start global sample count value at RX radio frame start global sample count value at TCU subframe start global subframe count value at TCU subframe start global sample count value at TCU subframe start global sample count value at TCU radio frame start global subframe count value at TCU radio frame start global sample count value at TCU radio frame start TX coarse adjustment sample count from 0 - 1919 in (chip unit) - (auto clear in next subframe) TX coarse adjustment sample direction - (auto clear in next subframe) 0: advance 1: postpone 15KHz: TX fine adjustment sample count from 0 - 9 in (chip unit) 3.75Hz: TX fine adjustment sample count from (0 - 9) x 4 in (chip unit) Remark: SW should configure the sample boundary which is aligned to 3.75Hz sample if the timing adjustment between TX transmission. (auto clear in next subframe) TX fine adjustment sample direction - (auto clear in next subframe) 0: advance 1: postpone TX fine adjustment mode control: 0: adjust the boundary at the end of the current subframe 1: adjust the CP at the first symbol of the next TX global sample count value at TX subframe start global subframe count value at TX subframe start global radio frame count value at TX subframe start TX subsample control 0: sync with global subsample counter 1: only sync with RX subsample counter when TX is not on transmission Control RX coarse adjustment status Control RX fine adjustment status Control TX coarse adjustment status Control TX fine adjustment status Control adjustment enable 1: enable 0: disable Trigger to sample global counter position for DSP debegging global counter sample position when CAPTURE1_GLB_CNT is accessed global counter subframe position when CAPTURE1_GLB_CNT is accessed global counter radio frame position when CAPTURE1_GLB_CNT is accessed Trigger to sample global counter position for MCU debegging global counter sample position when CAPTURE2_GLB_CNT is accessed global counter subframe position when CAPTURE2_GLB_CNT is accessed global counter radio frame position when CAPTURE2_GLB_CNT is accessed For sleep operation When SLEEP_W is accessed, the start values needed for wake-up are loaded. Then values have to be written before the SLEEP_W is accessed Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for alignment of the DFE input valid. 0-31 global counter sample position in sleep mode (in chip unit) global counter subframe position global counter radio frame position Global counter subsample MSB bit [8:5]. Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for align the DFE input valid. 0-31 RX sample count value RX OFDM symbol count value RX subframe count value Sleep Elapsed Subsample counter Range: 0-511 Sleep Elapsed Subsample counter Range: 0-1919 Sleep Elapsed SF counter Range: 0-2^32-1 Read global counter sample position Read global counter subframe position Read global counter radio frame position global subsample count value at TX transmission start 0-31 LSB[4:0] global sample count value at TX transmission start global subframe count value at TX transmission start global radio frame count value at TX transmission start global subsample count value at TX transmission start MSB bit[8:5](Not abailable in NB mode) TCU event subsample time TCU event subframe time RX synchronization method mode 0: normal mode 1: sync counter will synchronize with input i_rx_sync_start pulse in DUMP mode only (For testing only) 2: sync counter will synchronize first ca_rx data valid signal in DUMP mode only (For testing only) 3: sync counter will synchronize first rx data valid signal in DUMP mode only (For testing only) RX subframe count sync initialization value - 1 Global subframe count sync initialization value - 1 Global radio frame count sync initialization value - 1 RX Capture event sample time RX Capture event subframe time DSP memory 0 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 0 CLK disable 0: enable 1: disable DSP memory 1 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 1 CLK disable 0: enable 1: disable DSP memory 2 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 2 CLK disable 0: enable 1: disable DSP memory 3 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 3 CLK disable 0: enable 1: disable DSP memory 4 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 4 CLK disable 0: enable 1: disable DSP memory 5 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 5 CLK disable 0: enable 1: disable DSP memory 7 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 7 CLK disable 0: enable 1: disable DSP memory 8 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 8 CLK disable 0: enable 1: disable RX FFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Cell Search PSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Cell Search SSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX CFO sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Viterbi sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX AGC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX DS_BSEL sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. TX frontend sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. PUSCH encoder sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. TX CHSC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. FFT 512 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. NPRS acc1 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. FINE_IFFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. rNBIOT general part reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX RSRP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. CA RX dump sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. CA TX dump sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. NB ACC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. S16Peak sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. SP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. S16Peak sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. S16Peak sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 1'b0: default value; 1'b1: Reset whole sub-module. Enable/disable the clock for RX FFT/RSRP module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Cell Search module PSS 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Cell Search module SSS 0: clock disabled 1: clock enabled. Enable/disable the clock for RX CFO module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Viterbi module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX AGC module 0: clock disabled 1: clock enabled. Enable/disable the clock for DS_BSEL module 0: clock disabled 1: clock enabled. Enable/disable the clock for TX Frontend module. 0: clock disabled 1: clock enabled. Enable/disable the clock for PUSCH encoder module. 0: clock disabled 1: clock enabled. Enable/disable the clock for TX TX channel-interleaver and scrambling module. 0: clock disabled 1: clock enabled. Enable/disable the clock for FFT 512 module. 0: clock disabled 1: clock enabled. Enable/disable the clock for NPRS ACC1 module. 0: clock disabled 1: clock enabled. Enable/disable the clock for FINE ifft module 0: clock disabled 1: clock enabled. Enable/disable the clock for NBIOT module 0: clock disabled 1: clock enabled. Enable/disable the clock for CA Rx Dump module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for CA Tx Dump module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for NBIOT module 0: clock disabled 1: clock enabled. Enable/disable the clock for Search_16peak module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for SP module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for Tx MDD module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for LOCSEQ module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for TX_REG module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for RX_REG module 1'b0: clock disabled 1'b1: clock enabled. Enable/disable the clock for CS_REG module 1'b0: clock disabled 1'b1: clock enabled. Debug signal selection Debug signal output enable Reserved for debug only RFIN reset by DSP, it is used to re-timing the global timer to balance the timing of IQ data input from DFE in sample boundary. Write 1 and auto-clear by HW. 0: default value 1: reset to re-timing the sample boundary in global timer. Sample the glb_subsample_cnt with input rx_data_vld to check the phase change of the input Keep track the RFIN data strobe in valid window. 0: Normal 1: Error PSS Correlator coarse clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. SSS Correlator coarse clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. FFT_RSRP fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP. PSS Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. SSS Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. CFO Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module CFO Correlator. Viterbi fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module Viterbi. AGC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module AGC. DS_BSEL fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module DS_BSEL. TX_FRONTEND fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module TX_FRONTEND. PUSCH_ENC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PUSCH_ENC. TX_CHSC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module TX_CHSC. FFT 512 fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FFT 512. NPRS ACC1 fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module NPRS ACC1. FIne IFFT fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FINE_IFFT. RSRP fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP CA RX dump fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module CA RX dump CA TX dump fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module CA TX dump MCA FFT128 dump fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module Multi CA FFT 128 MCA IFFT128 dump fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module Multi CA IFFT 128 NB ACC fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module NB ACC Search16peak fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module Search16peak SP fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module SP NB matrix fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module NB matrix TX MDD fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module TX MDD LOCSEQ fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module LOCSEQ SS fine clock gating, 1'b0: free running 1'b1: clock gated by the clock enabled signal which generated from sub-module SS NBIOT CORE APB domain reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. Debug General Purpose Output Remark: need to set rNBIOT_MONITOR to 0x1a3 RX data input control: Please refer to diagram below in detail CA RX input data right shift control bit 9-7: 0: No left shift 1: Right shift 1 bit 2: Right shift 2 bit 3: Right shift 3 bit 4: Right shift 4 bit 5~7: Reserved bit 6-3: Reserved bit 2: Select the source to CA RX dump CA data 0 0: CA RX source input stage 0 1: DFE RX input bit 1: Select the CA RX source input stage 0 data path 0: LVDS CA RX input 1: NB CA TX output bit 0: Select the source to RX input data stream path 0: DFE RX input 1: LVDS CA RX input TX data output control: Please refer to diagram below in detail: bit 1: Select the source to LVDSTX data path 0: CA TX dump CA Tx data 0 output 1: TX frontend output bit 0: Select the source to DFE TX data path 0: TX frontend output 1: CA TX dump CA Tx data 0 output CA data valid status (Write 1 clear status) 0: no CA data valid occur 1: CA data valid occur Minor Revision MAJOR Revision DS_BSEL accelerator start Maximum time out value for TX bit level processing in 61.44Mhz unit Number of Candidate 0: 1 candidate 1: 2 candidate 2: 3 candidate 3: 4 candidate Bit de-selection and combining 0: Disable 1: enable Remark: When this bit is disabled, the output data number is equal to rDESCR_SIZE0 and it only support 1 candidate. Descramble enable 0: Disable 1: enable NCB minus: NCB - 3ND Start control 0:Trigger by SW start 1:Trigger by HW start by SP done signal Descramble X1 value for candidate 0 Descramble X1 value for candidate 1 Descramble X1 value for candidate 2 Descramble X1 value for candidate 3 Descramble X2 value for candidate 0 Descramble X2 value for candidate 1 Descramble X2 value for candidate 2 Descramble X2 value for candidate 3 Descramble size 0 Descramble size 1 Descramble size 3 Descramble size 2 Descramble input buffer start address 0 Descramble input buffer start address 1 Descramble input buffer start address 3 Descramble input buffer start address 4 DS_BSEL output memory start address for last X1/X2 state value DS_BSEL output memory start address The last candidate Descramble X2 state value The last candidate Descramble X2 state value (This bit is write 1 clear) 0: No Done 1: Done If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion 0: Normal 1: Error 0: Idle 1: On-going FFT calculation enable the period of FFT done interrupt, 0: one time per-subframe; 1: twice per-subframe. FFT/RSRP enable FFT result scaling 0: FFT disabled, 5 RSRP CELLs calculation mode; 1: FFT + 2 RSRP Cell calculation mode. FFT OFDM symbol CP offset RSRP Cell0 Enabled. RSRP Cell1 Enabled. RSRP Cell2 Enabled. RSRP Cell3 Enabled. RSRP Cell4 Enabled. Frame start position of RSRP Cell0 based on global timer. Frame start position of RSRP Cell1 based on global timer. Frame start position of RSRP Cell2 based on global timer. Frame start position of RSRP Cell3 based on global timer. Frame start position of RSRP Cell4 based on global timer. OFDM symbol CP offset for NCELL0. OFDM symbol CP offset for NCELL1. OFDM symbol CP offset for NCELL2. OFDM symbol CP offset for NCELL3. OFDM symbol CP offset for NCELL4. vshift of NCELL0. vshift of NCELL1. vshift of NCELL2. vshift of NCELL3. vshift of NCELL4. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. Offset address for RSRP write memory buffer. Reserved Indicated whether the data in ping-pong buffer is updated. FFT buffer ping-pong flag Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. subframe index of serving cell subframe idx of NCELL0 subframe idx of NCELL1 subframe idx of NCELL2 subframe idx of NCELL3 subframe idx of NCELL4 FFT pingpong buffer overwritten status RSRP Cell0 triple buffer over-written status. RSRP Cell1 triple buffer over-written status. RSRP Cell2 triple buffer over-written status. RSRP Cell3 triple buffer over-written status. RSRP Cell4 triple buffer over-written status. FFT write buffer bus error RSRP CELL0 write buffer bus error RSRP CELL1 write buffer bus error RSRP CELL2 write buffer bus error RSRP CELL3 write buffer bus error RSRP CELL4 write buffer bus error FFT pingpong buf idx RSRP0 Triple buffer idx RSRP1 Triple buffer idx RSRP2 Triple buffer idx RSRP3 Triple buffer idx RSRP4 Triple buffer idx FFT subframe idx RSRP Cell0 subframe idx RSRP Cell1 subframe idx RSRP Cell2 subframe idx RSRP Cell3 subframe idx RSRP Cell4 subframe idx The configurable value for FFT output saturation. 1'b0:FFT output is S16:10;make sure the output value range from[0x8001,0x7fff] 1'b1:FFT output is S16:9;one bit shift and make sure the output value range from[0xc001,0x3fff] Enable/Disable to limit the value of FFT result according to rFFT_OUT_MASK_VALUE 1'b0:Disable 1'b1:Enable(Defalut) Interrupt Masking bit for RX_INT_DSP Interrupt Masking bit for RX_INT_MCU Interrupt Masking bit for TX_INT_DSP Interrupt masking bit from the interrupt of fft_done_int Interrupt masking bit of NCELL0 decode done intterupt Interrupt masking bit of NCELL1 decode done interrupt Interrupt masking bit of NCELL2 decode done interrpt Interrupt masking bit of NCELL3 decode done interrupt Interrupt masking bit of NCELL4 decode done interrupt Interrupt masking bit of PSS SF done interrupt Interrupt masking bit of SSS SF done interrupt Interrupt masking bit of CFO SF done interrupt Interrupt masking bit of Viterbi decode done interrupt Interrupt masking bit of AGC interrupt masking Interrupt masking bit of DS_BSEL interrupt Interrupt masking bit of PUSCH encoder interrupt Interrupt masking bit of TX_CHSC interrupt Interrupt masking bit of FFT_512 done interrupt Interrupt masking bit of NPRS_ACC1 done interrupt Interrupt masking bit of FINE_IFFT done interrupt Interrupt masking bit of CA RX Dump done interrupt Interrupt masking bit of CA TX dump done interrupt Interrupt masking bit of NB ACC done interrupt interrupt status of RX_INT_DSP, write 1 clear. Interrupt status of RX_INT_MCU, write 1 clear. Interrupt status of TX_INT_DSP, write 1 clear. Interrupt status of fft_sf_done_int Interrupt status of RSRP Cell0 decode done interrupt Interrupt status of RSRP Cell1 decode done interrupt Interrupt status of RSRP Cell20 decode done interrupt Interrupt status of RSRP Cell3 decode done interrupt Interrupt status of RSRP Cell4 decode done interrupt Interrupt status of PSS SF done interrupt Interrupt status of SSS SF done interrupt Interrupt status of CFO SF done interrupt Interrupt status of Viterbi decode done Interrupt status of AGC interrupt Interrupt status of DS_BSEL interrupt Interrupt status of PUSCH Encoder interrupt Interrupt status of TX_CHSC interrupt Interrupt status of FFT_512 done interrupt Interrupt status of NPRS_ACC1 done interrupt Interrupt status of FINE IFFT done interrupt Interrupt status of CA RX dump done interrupt Interrupt status of CA TX dump done interrupt Interrupt status of NB ACC done interrupt Masking nb acc done for TXEV Masking S16PEAK done for TXEV Masking FFT_512 done for TXEV Masking NPRS_ACC1 done for TXEV Masking FINE_IFFT done for TXEV Masking LOCSEQ_GEN done for TXEV Masking SmartScheduler done for TXEV The start of LOCSEQ_GEN accelerator. Locseq type, 2'b00: No sequence; 2'b01: PBCH; 2'b10: NSSS; 2'b11: NWUS. Index of Binary sequence selection when NSSS. Reserved bits. Ifft output bit fixed point selection. u index of Zadoff-Chu sequence, whihch equal to Ncell_IDmod126+3. Vshift for NRS. NBIoT Tx antenna number. 2'd0: no NRS; 2'd1: 1 antenna port; 2'd2: 2 antenna port; 2'd3: Reserved; Vshift for CRS. LTE antenna number, 2'd0: no CRS; 2'd1: 1 antenna port; 2'd2: 2 antenna port; 2'd3: 3 antenna port; The cyclic shift in the frame number nf which is given by (nf/2)mod4. Reserved bit. Locseq gen backdoor enabled. 1'b0: Normal mode, locseq sequence backdoor is disabled. 1'b1: locseq sequence backdoor enabled. The NWUS Scramble enabled. 1'b0: Scramble disabled. 1'b1: Scramble enabled. Enabled Raw zad-off CHU sequence output. 1'b0: Disabled. 1'b1: Enabled. Symbol bitmap for NWUS and PBCH. bit0=1'b0: symbol0 disabled. bit0=1'b1: symbol0 enabled. bit1=1'b0: symbol1 disabled. bit1=1'b1: symbol1 enabled. ... bit13=1'b0: symbol13 disabled. bit13=1'b1: symbol13 enabled. NWUS phase shift enabled/disabled. 1'b0: Disabled. 1'b1: Enabled. for R16 NWUS phase shift, g value is equal to 14*(u_id+1),u_id is from 0 to 7 Initial value of X1 golden sequence for each subframe, used for scramble for NWUS. Initial value of X2 golden sequence for each subframe, used for scramble for NWUS. Memory address where store teh resource element result of PBCH. Memory address where store the local sequence result. Timer to limit the processing time of locseq gen. DMA Timer, which used to limit the time of one time of DMA transfer. The start address of the external memory space used for store the result of IFFT. The end address of the external memory space used for store the result of IFFT. Reported X1 scramble sequence value when locseq generated done for one sub-frame. Reported X2 scramble sequence value when locseq generated done for one sub-frame. Locseq gen DMA engine status, [9:8]: DMA done status 2'd0: DMA success done; 2'd1: DMA done by DMA stop; 2'd2: DMA done by DMA timerout; 2'd3: reserved. [7]: dma write FIFO ready status, for debug [6]: dma read FIFO1 ready status, for debug [5]: dma read FIFO0 ready status, for debug [4:0]: dma controller state machine, for debug 1'b0: DMA IDLE; 1'b1: DMA Busy. 1'b0: DMA timeout; 1'b1: DMA finish in a setting time normally. bit0: FIFO empty status; bit1: FIFO half empty status; bit2: FIFO full status; bit3: FIFO half full status; 1'b0: LOCSEQ_GEN busy or idle; 1'b1: LOCSEQ_GEN done; write one to clear. 1'b0: LOCSEQ_GEN idle; 1'b1: LOCSEQ_GEN busy; LOCSEQ_GEN time out. 2'b0: no error; 2'b1: locseq type configured error; 2'b2: locseq AHB write memory space over-range; 2'b3: reserved. The count of LOCSEQ is called for PBCH calculation, the count hold 3 if it is more than 3. DSP can write 2'b11 to clear; The count of LOCSEQ is called for NSSS calculation, the count hold 3 if it is more than 3. DSP can write 2'b11 to clear; The count of LOCSEQ is called for NWUS calculation, the count hold 3 if it is more than 3. DSP can write 2'b11 to clear; Symbol power accumulation enable/disable signal and effective at subframe boundary. 1 : enable 0 : disable Switching register to choose input source data for symbol power calculation 0: normal rx data 1: rx data without dc offset Gain used in shift and saturation of accumulation power value. Bit[3:0] Gain 0000 2^-24 (default) 0001 2^-23 0010 2^-22 0011 2^-21 Accumulation length of samples in every symbol. 0: 128 1: 64 2: 32 3: 16 Offset of samples from symbols' boundaries which is the start boundary of agc symbol power calculation. Reading address for DSP to read asp response ram, and this register would auto-increment whenever access the 'rASP_RD_DATA' register PING buffer address: 0~20 PONG buffer address: 21~41 Bit[27:16]: Q DC offset configuration Bit[11:0]: I DC offset configuration Report agc symbol power and DCC done status, write '1' to clear this status Index bit to indicate which buffer is updated of PING-PONG 1: PONG buffer data is updated 0: PING buffer data is updated Data = mem[rASP_RD_ADDR] which is the ASP response memory data content. The ASP_RD_ADDR would auto increase whenever access this register. ASP response Memory address range is 0-41 Address(0~6,21~27): symbol power, bit[15:0] for symbol 0,2,4,6,8,10,12 and bit[31:16] for symbol 1,3,5,7,9,11,13 Address(7~20,28~41):dc_offset value, bit[15:0] for I and bit[31:16] for Q Forward/Inverse FFT transform computing selection PING-PONG memory selection 1'b0: Memory0; 1'b1: Memory1. alphaFFT scaling, it can be implemented by bit shift, 3'd0: 2^-3 3'd1: 2^-2 3'd2: 2^-1 3'd3: 2^0 (default) 3'd4: 2^1 3'd5: 2^2 3'd6: 2^3 3'd7: 2^4 alphaFFT_amp_out scaling for amplitude square output, it can be implemented by bit shift, 3'd0: 2^-3 3'd1: 2^-2 3'd2: 2^-1 3'd3: 2^0 (default) 3'd4: 2^1 3'd5: 2^2 3'd6: 2^3 3'd7: 2^4 IFFT Output amptitude data 1'b0: IFFT output normal data(I+j*Q); 1'b1: IFFT output amptitude data(I^2+Q^2). FFT start indication, when write 1 to this register, a high active pulse will be generated and input to FFT engine to start FFT calculation. FFT done status, write 1 clear. An error grant is received when FFT request memory write bus to store FFT result. Bit1: DSP control error; Bit0: Accelerator memory access error. This register is used to check the range of FFT/IFFT input, 1'b1: absolute maximum FFT/IFFT input less than 32, in this case, the resolution of FFT/IFFT output will loss 1bit; 1'b0: normally. NPRS accelerator 1 Start Maximum time out value in 61.44Mhz unit Mode selection: 2'b00: copy + dot product 2'b01: dot product 2'b10: copy Copy Source memory before sequence dot product 0: Memory 0 1: Memory 1 Copy memory with bit-reversed address write location enable 0: Disable 1: Enable Destination memory after sequence dot product 0: Memory 0 1: Memory 1 Dot Product from memory 5 to memory 0/1 with bit-reversed address write location enable 0: Disable 1: Enable Conjugate Sequence data Enable 0: Disable 1: Enable Conjugate FFT data Enable 0: Disable 1: Enable Dot Product output bit shift (default:3) 0: s16.13 1: s16.12 2: s16.11 3: s16.10 4: s16.9 5: s16.8 6: s16.7 7: s16.6 Destination memory after CP 0: Memory 5 1: Memory 4 2: Memory 7 3: Not available Operation length -1 Default : (511) Sequence Memory Start Offset Address Sequence Memory Start Offset Address (This bit is read write 1 clear) 0: No Done 1: Done If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error Read/Write process in Memory 0/1 (FFT/IFFT input/output memory) 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion Read/Write process in Memory 5 (Copied FFT memory) Read process in Memory 4 (Sequence memory) Read/Write process in Memory 7 (Copied FFT memory) 0: Normal 1: Error Fine IFFT Start Offset Address for copy memory 7 Fine IFFT START A pulse to grigger the Fine IFFT NPRS Coarse Timing Result Range is from 0 to 272 Fine IFFT calculation offset. Range is from 0 to 95. Fine IFFT calculation length. Range is from 1 to 96. Fine IFFT output a+bj scaling 3'd0:x2^0(default) 3'd1:x2^-1 3'd2:x2^-2 3'd3:x2^-3 3'd4:x2^-4 3'd5:x2^-5 3'd6:x2^-6 3'd7:x2^-7 Fine IFFT output power scaling 3'd0:x2^-3 3'd1:x2^-2 3'd2:x2^-1 3'd3:x2^0 (default) 3'd4:x2^1 3'd5:x2^2 3'd6:x2^3 3'd7:x2^4 Fine IFFT output selection 1'b0: Output IFFT result: a+bj 1'b1: Output power result: a^2+b^2 Fine IFFT input data control 1'b0: Input data in inverse order 1'b1: Input data in inverse order and swap bit0~bit255 with bit256~bit511 Fine IFFT input data start address Fine IFFT output data start address Fine IFFT calculation done status. 1'b1: Fine IFFT calculation done 1'b0: Fine IFFT is idle or under calculating Fine IFFT output buffer status 1'b1: Fine IFFT output buffer is over written 1'b0: Fine IFFT output buffer is normal Fine IFFT calculation done status. 1'b1: Fine IFFT calculation done 1'b0: Fine IFFT is idle or under calculating The start address of memory where FFT command stored. Figure 5.4 2 shows the FFT command format. Pulse that high asserted which start CA FFT calculation. Once start, HW will perform FFT calculation High active pulse, when asserted, HW accelerator continue to finish FFT calculation based on current FFT command, then stop. 0: FFT command format0, whose length is 9 DWs. 1: FFT command format1, whose length is 10 DWs which include the information of DC offset cancellation and calculation. DMA timer, maximum DMA time limited. CA FFT timer, limited the time from DSP program CA FFT start to HW finish all of FFT calculation in FFT commands The start address in share memory used for CA_FFT, co-use with i_ ca_fft_mem_space_end, all of AHB access cycle whose address is out of the range will be rejected. The end address in share memory used for CA_FFT, co-use with i_ ca_fft_mem_space_start, all of AHB access cycle whose address is out of the range will be rejected. [9:8]: DMA done status 0: DMA success done; 1: DMA done by DMA stop; 2: DMA done by DMA timeout; 3: Reserved. [7]: dma write FIFO ready status, for debug [6]: dma read FIFO1 ready ststus, for debug [5]: dma read FIFO0 ready status, for debug [4:0]: dma controller state machine, for debug 1: DMA busy; 0: DMA IDLE. 1: DMA timer out 0: DMA finish in a setting time normally. FFT FIFO status Bit0: FIFO empty Bit1: FIFO half empty Bit2: FIFO full Bit3: FIFO half full 0: CA FFT idle; 1: CA FFT busy. 1: CA FFT done 0: CA FFT ongoing or idle. When SW start CA FFT, CA FFT timer begin to count, and stop when CA FFT done, during this time, if timer count reach to rDMA_TIMER, it reports time out. 0: no time out. 1: CA FFT calculation does not finish in a setting time, and time out. FFT command error, asserted when FFT command format error, write 1 clear 0: FFT command valid; 1: FFT command invalid; 2: DMA address out of range which set by [rCA_FFT_MEM_SPACE_START, rCA_FFT_MEM_SPACE_END]. 3: Reserved. Indicated which the ongoing FFT is triggered by which FFT Command. Indicated which loop counter is a FFT command is served. The start address of memory where FFT command stored. Figure 5.4 2 shows the FFT command format. A circular buffer is provided for DSP to program IFFT command data, the register defines the depth of this memory. The depth of command in memory is programmed in unit of byte, each IFFT command occupy 4 DWs, which is 16 bytes, so the programmed number always is times of 16. 0: Software mode. Hardware accelerator performs FFT calculation according to FFT command. DSP need to make sure the data is transmitted before start next IFFT calculation. 1: Hardware mode. Hardware accelerator automatically performs FFT calculation by monitoring the data dump number form TX_DUMP module. 0: DSP can not write ZC twiddle RAM; 1: DSP can write ZC twiddle RAM. Zadoff-CHU sequence length, prime number, default value 43. RACH sub-carrier offset, default value is equal to 42. Conifigured value = rZC_SEQ_LEN -1; 0: PRACH symbol generation without pi rotate at odd symbol; 1: PRACH symbol generateion with pi rotate at odd symbol. Pulse that high asserted which start CA IFFT calculation. Once start, HW will perform DFT/IFFT calculation High active pulse, when asserted, HW accelerator continue to finish IFFT calculation based on current FFT command, then stop. DMA timer, maximum DMA time limited. CA IFFT timer, limited the time from DSP program CA IFFT start to HW finish all of IFFT calculation in IFFT commands The start address in share memory used for CA_IFFT, co-use with rCA_FFT_MEM_SPACE_END, all of AHB access cycle whose address is out of the range will be rejected. The end address in share memory used for CA_IFFT, co-use with rCA_IFFT_MEM_SPACE_START, all of AHB access cycle whose address is out of the range will be rejected. [9:8]: DMA done status 0: DMA success done; 1: DMA done by DMA stop; 2: DMA done by DMA timeout; 3: Reserved. [7]: dma write FIFO ready status, for debug [6]: dma read FIFO1 ready ststus, for debug [5]: dma read FIFO0 ready status, for debug [4:0]: dma controller state machine, for debug 1: DMA busy; 0: DMA IDLE. 1: DMA timer out 0: DMA finish in a setting time normally. FFT FIFO status Bit0: FIFO empty Bit1: FIFO half empty Bit2: FIFO full Bit3: FIFO half full 0: CA IFFT idle; 1: CA IFFT busy. 1: CA FFT done 0: CA FFT ongoing or idle. When SW start CA IFFT, CA IFFT timer begin to count, and stop when CA IFFT done, during this time, if timer count reach to rDMA_TIMER, it reports time out. 0: no time out. 1: CA IFFT calculation does not finish in a setting time, and time out. Asserted which IFFT command format error. 0: no error 1: current IFFT command invalid 2: next IFFT command invalid 3: DMA address out of range. Indicated which the ongoing IFFT is triggered by which IFFT Command. Indicated which loop counter is a IFFT command is served. CA DUMP underflow, asserted when CA DUMP symbol cnt is more than IFFT finished symbol cnt, which means no data for tx dump to transmit. When asserted, it need DSP write 1 to clear. TX Gain for CA0. TX Gain for CA1. TX Gain for CA2. TX Gain for CA3. TX Gain for CA4. TX Gain for CA6. TX Gain for CA6. TX Gain for CA7. TX Gain for CA8. TX Gain for CA9. TX Gain for CA10. TX Gain for CA11. TX Gain for CA12. TX Gain for CA13. TX Gain for CA14. TX Gain for CA15. Pulse, which start the engine of SS. Base address of memroy where store the command of smartscheduler. The length of command. Mode select for finish fetching smartscheduler command. 1'b0: Command length mode. 1'b1: Instruction mode. The base address of NB APB bus, for register programing The base address of NB AHB bus, for memory programming. Timer which is set to limit the time of smartscheduler processing. The status of DMA Engine. DMA busy status. 1'b0: DMA idle; 1'b1: DMA busy Indicated whether DMA timeout, unused. DMA FIFO STATUS. [0]: FIFO empty; [1]: FIFO half empty; [2]: FIFO full; [3]: FIFO half full. Current command index. The current state of smartscheder control state machine. whether smartscheduler is in waiting NB accelerator done. 1'b1: smartscheduler is in waiting NB accelerator done. 1'b0: smartscheduler is not in waiting NB accelerator done. The command word which is executing. 1'b0: Smartscheduler busy if it is started, otherwise, it is in idle 1'b1: Smartscheduler processing done; 1'b0: Smartscheduler idle; 1'b1: Smartscheduler busy. 2'b00: No error; 2'b1: SS command configured error. 1'b0: no time out; 1'b1: Smartscheduler does not finish in a setting time. Indicated the number of command is excuted when smartscheduler done. Smartscheduler is restarted when it is busy; SP accelerator start Maximum time out value for TX bit level processing in 61.44Mhz unit Number of Candidate 0: 1 candidate 1: 2 candidate 2: 3 candidate 3: 4 candidate Descramble enable 0: Disable 1: enable De-rotation Enable 0: Disable 1: Enable Demapping LLR format selection 0: 8.0x2^-5 1: 8.0x2^-4 2: 8.0x2^-3 3: 8.0x2^-2 4: 8.0x2^-1 5: 8.0x2^0 6: 8.0x2^1 7: 8.0x2^2 PDCCH AL1 enable 0: disable 1: enable Demap size 0 Demap size 1 Demap size 3 Demap size 2 Configuration input buffer start address 0 SP output memory start address SP output memory start address for last X1/X2 state value (This bit is write 1 clear) 0: No Done 1: Done If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion 0: Normal 1: Error 0: Normal 1: Error 0: Idle 1: On-going Maximum time out value for TX channel-interleaver and scrambling in 61.44Mhz unit. Start control: 0: Trigger by SW start 1: Trigger by HW start. Channel interleaver enable 0: Disable 1: Enable. Scramble enable 0: Disable 1: Enable. TX channel-interleaver and scrambling accelerator 2 start. Bit selection memory start address. Scramble memory start output address. Ncb minus NCB - 3ND. K0 minus: K0 position without dummy bit.. Row size for ch-interleaver. Modulation type 0: BPSK 1: QPSK. Column size in each resource unit: (NUL_sym-1)* Nul_slot. scrambling size in current subframe. scrambling X1. scrambling X2. Last scrambling state in X1. Last scrambling state in X2. (This bit is read write 1 clear) 0: No Done 1: Done. If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion 0: Normal 1: Error PUSCH offset1 for 3.75K process delay PUSCH offset0 for 15K process delay PRACH format0,1 offset for process delay PRACH format2 offset for process delay TA Value the advance time of PRACH start adjustment When PRACH_USER_DEFINE_EN = 1'b1, SW is able to set CP length by configured, which length is from 0 to 128 When PRACH_USER_DEFINE_EN = 1'b1, SW is able to change the transmit sequence number 1'b1:DSP configure to change the CP length and repetition number of sequence 1'b0:PRACH CP length and repetition number is based on definition in 36.211 RF delay from NBIOT_CORE to chip output PUSCH Enable PRACH Enable Delta CP adjustment TX frame mode for PUSCH Module type TX Buffer idx PUSCH Tone mode Shorten PUSCH Enable PUSCH Subcarrier POsition Type of prach 0: format 0 (cp length 66.7us) 1: format 1 (cp length 266.7us) 2: format 2 (cp length 800us) 3: reserved PAPR reduction enable 0: Normal 1: Tone 6 lower PAPR enable 2: Tone 6 upper PAPR enable 3: Tone 12 PAPR enable TX Gain Bit selection for final tx doout 0: S14.11 1: S14.10 2: S14.9 3: S14.8 thetal symbol incremental step value symbol number modulo 2 memory bus access error TX Status, 2'b00: IDLE; 2'b01: PRACH; 2'b10: PUSCH 3.75K; 2'b11: PUSCH 15K Subframe index of NPRACH or NPUSCH transmitted Bit[0]:Indicator Error 0:Normal 1:Error Bit[2:1]: TX buffer index for corresponding ready error (For checking TX_MDD data buffer ready or not) TX Clear HW buffer ready Write 1 Clear Remark: It should program before the first subframe of TX_MDD start PRACH sub-carrier index 0~147 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH Nxt Command Read Pointer Reserved TX dout checksum TX dout Checksum Enable Configurable Number of zero data padded at the end of TX transmission LPF1 coefficient0 Reserved LPF1 coefficient1 Reserved LPF1 coefficient2 Reserved LPF1 coefficient3 Reserved LPF1 coefficient4 Reserved LPF1 coefficient5 Reserved LPF2 coefficient0 Reserved LPF2 coefficient1 Reserved LPF2 coefficient2 Reserved LPF2 coefficient3 Reserved LPF2 coefficient4 Reserved LPF2 coefficient5 Reserved PAPR T12 coefficient0 Reserved PAPR T12 coefficient1 Reserved PAPR T12 coefficient3 Reserved PAPR T12 coefficient2 Reserved PAPR T12 coefficient5 Reserved PAPR T12 coefficient4 Reserved PAPR T12 coefficient7 Reserved PAPR T12 coefficient6 Reserved PAPR T12 coefficient10 Reserved PAPR T12 coefficient8 Reserved PAPR T12 coefficient11 Reserved PAPR T12 coefficient10 Reserved PAPR T06 coefficient0 Reserved PAPR T06 coefficient1 Reserved PAPR T06 coefficient3 Reserved PAPR T06 coefficient2 Reserved PAPR T06 coefficient5 Reserved PAPR T06 coefficient4 Reserved Pulse, which start the engine of TX_MDD. Work Mode of TX_MDD. 1'b0: Software mode; 1'b1: Hardware mode. Enable of Modulation/DFT. 1'b0: Modulation/DFT diabled. 1'b1: Modulation/DFT enabled. Enable of modulation. 1'b0: Modulation disabled; 1'b1: Modulation enabled. Enable of DMRS. 1'b0: DMRS generation disabled. 1'b1: DMRS generation enabled. PUSCH Format. 1'b0: PUSCH format1; 1'b1: PUSCH format2. Slot number in a subframe. set slot number to 1 when 3.75KHz. set slot number to 2 when 15KHz. Modulation Type. 1'b0: BPSK; 1'b1: QPSK. Sub-carrier number,which is 1, 3, 6, 12. Symbol bit map for DMRS. rDMRS_SYMB_BMP[n]==1'b0: this symbol is for PUSCH or NULL; rDMRS_SYMB_BMP[n]==1'b1: this symbol is for DMRS; n=0,1,2,...6. Symbol bit map for DFT. rDFT_SYMB_BMP[n]==1'b0: this symbol is for DMRS or NULL; rDFT_SYMB_BMP[n]==1'b1: this symbol is for PUSCH. n=0,1,2,...6. Scheduling request. 1'b0: scheduling request disabled. 1'b1: scheduling request enabled.. Triple memory index for Resource mapping. For positive scheduling request, which be transmitted use NPUSCH format2, configured each SF. Allocated carrier index for PUSCH transmission. The start address of memory5 which store the result of accelerator tx_chsc. DMRS cyclic shift index, it came from high level configuration. 3-tone: threeToneCyclicShift=0,1,2. 6-tone: sixToneCyclicShift=0,1,2,3. 12-tone: twelveToneCyclicShift=0. used for multi-tone. TS36211, Table 5.5.2.2.1-2, sequence index. rORTH_SEQ_IDX[1:0]: for slot0; rORTH_SEQ_IDX[3:2]: for slot1. Sequence index of DMRS, we also can treat is as slot index as it increased slot by slot. Sequence group number, u. rBASE_SEQ_IDX[4:0]: u for slot0; rBASE_SEQ_IDX[9:5]: u for slot1, slot 1 is not same as slot0 when group hopping enabled. Binary sequence c(n) for slot n and slot n+1, for single tone of PUSCH. Timer which is set to limit the time of tx_mdd processing. Tx MDD done status. 1'b0: TX MDD ongoing/IDLE; 1'b1: TX MDD done. 1'b0: the data in memory are invalid or has been read by SW; 1'b1: the data in memory are valid. after HW write data to this memory, this bit will be set by HW; after SW read data from this memory, this bit will be clear by SW. 1'b0: the data in memory are invalid or has been read by SW; 1'b1: the data in memory are valid. after HW write data to this memory, this bit will be set by HW; after SW read data from this memory, this bit will be clear by SW. 1'b0: the data in memory are invalid or has been read by SW; 1'b1: the data in memory are valid. after HW write data to this memory, this bit will be set by HW; after SW read data from this memory, this bit will be clear by SW. 1'b0: This memory never over-wrote; 1'b1: This memory had beed over-wrote, which means HW write memory, but the data in memory has not been read. 1'b0: This memory never over-wrote; 1'b1: This memory had beed over-wrote, which means HW write memory, but the data in memory has not been read. 1'b0: This memory never over-wrote; 1'b1: This memory had beed over-wrote, which means HW write memory, but the data in memory has not been read. 1'b0: TX MDD idle; 1'b1: TX MDD busy. 1'b0: TX MDD modulation idle; 1'b1: TX MDD modulation busy. 1'b0: TX MDD DFT idle; 1'b1: TX MDD DFT busy. 1'b0: TX MDD DMRS generation idle; 1'b1: TX MDD DMRS generation busy. [3:2]: Modulation memory bus error; [1:0]: RSE memory bus error. 1'b0: TX MDD does not timeout; 1'b1: TX MDD timeout. Maximum time out value for pusch encoder in 61.44Mhz unit. Endian SWAP control for bit, byte and word. Write this register will trigger pusch encoder start TB Size for PUSCH. Alpha init value for QPP interleaver. Alpha Step value for QPP interleaver. Rd address to DSP memory for pusch encoder. WR address to DSP memory for pusch encoder. (This bit is read write 1 clear) 0: No Done 1: Done. Indicate overwritten happen for pusch encoder 0: Normal 1: Error Bit 0: DSP control bus error, 0-Normal, 1-Error Bit 1: accelerator memory access collusion, 0-Normal, 1-Error 0: Normal 1: Error Start trigger of one sequential decoding of viterbi decoder which is generated by writing '1' to this register Payload size of CBs to be decoded in one sequential decoding Indicate the number(1~4) of coded blocks to be decoded in one sequential decoding process Function of de-interleaving in hardware enable/disable 1: Enable 0: Disable CRC mask checking enable/disable(for RNTI and antenna port number) 1: Enable 0: Disable Indicate the CRC type of sequential decoding 1:24 0:16 Reserved bits List viterbi mode enable/disable 1: Enable 0: Disable This register indicates the start address of viterbi output odd buffer for payload. This register indicates the start address of viterbi output even buffer for payload. This register indicates the start address of data in viterbi input ram. Indicate CRC mask1(for RNTI and antenna port number) Indicate CRC mask0(for RNTI and antenna port number) Indicate CRC mask1(for RNTI and antenna port number) Indicate CRC mask0(for RNTI and antenna port number) Reorder the 32bit data written to viterbi output buffer 2:Reverse the word sequence in the Dword(1Dword) 1: Reverse the byte sequence in every word(2words). 0: Reverse the bit sequence in every byte(4bytes). In a sequential decoding process, if the corresponding time counter exceeds this set value of rVD_TIMECNT_LIMIT, bit4 of rVD_DEC_SATUS will be set to 1 and sent to high layer. Indicate even/odd viterbi output buffer to be written by decoder: 1: odd output buffer 0: even output buffer Bit width of output scaling data's fractional part(S8.y) Bit width of input scaling data's fractional part(S16.x) This register(U8.7) is multiplied by scaling input data(S16.x) Bitmap of CRC masks(0~3) used in blind decoding for the CB3 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB2 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB1 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB0 to be decoded Subframe index of current subframe on which DSP configure the decoding start siganl 'rVD_DEC_START' 15: Antenna number for candidate CB3(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB3 15: Antenna number for candidate CB2(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB2 15: Antenna number for candidate CB1(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB1 15: Antenna number for candidate CB0(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB0 CRC checking result of the corresponding code block for output buffer odd, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 1: good 0: fail If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB [31:28] for CB3(28:MASK0, 29:MASK1, 30:MASK2, 31:MASK3) [27:24] for CB2(24:MASK0, 25: MASK1, 26: MASK2, 27: MASK3) [23:20] for CB1(20: MASK0, 21: MASK1, 22: MASK2, 23: MASK3) [19:16] for CB0(16: MASK0, 17: MASK1, 18: MASK2, 19: MASK3) And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB [28] for CB3 [24] for CB2 [20] for CB1 [16] for CB0 CRC check result of the corresponding code block for output buffer even, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 1: good 0: fail If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB [15:12] for CB3(12: MASK0, 13: MASK1, 14: MASK2, 15: MASK3) [11:8] for CB2(8: MASK0, 9: MASK1, 10: MASK2, 11: MASK3) [7:4] for CB1(4: MASK0, 5: MASK1, 6: MASK2, 7: MASK3) [3:0] for CB0(0: MASK0, 1: MASK1, 2: MASK2, 3: MASK3) And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB [12] for CB3 [8] for CB2 [4] for CB1 [0] for CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Report some configurations to MCU for output buffer even [31:20] Report payload size [19:0] Report configuration of register 'rVD_CANDI_CFG' Report some configurations to MCU for output buffer even [31:20] Report payload size [19:0] Report configuration of register 'rVD_CANDI_CFG' Result of checking in case that the decoded data is all zero 1: All zero 0 : Not zero data. Bit[23:16] for output even buffer: [17:16] for CB0, bit16 indicates list Viterbi 1st path, bit17 indicates list Viterbi 2nd path(if 2nd path is needed ) [19:18] for CB1, bit18 indicates list Viterbi 1st path, bit19 indicates list Viterbi 2nd path(if 2nd path is needed ) [21:20] for CB2, bit20 indicates list Viterbi 1st path, bit21 indicates list Viterbi 2nd path(if 2nd path is needed ) [23:22] for CB3, bit22 indicates list Viterbi 1st path, bit23 indicates list Viterbi 2nd path(if 2nd path is needed ) Bit[31:24]for output odd buffer; [25:24] for CB0, bit24 indicates list Viterbi 1st path, bit25 indicates list Viterbi 2nd path(if 2nd path is needed ) [27:26] for CB1, bit26 indicates list Viterbi 1st path, bit27 indicates list Viterbi 2nd path(if 2nd path is needed ) [29:28] for CB2, bit28 indicates list Viterbi 1st path, bit29 indicates list Viterbi 2nd path(if 2nd path is needed ) [31:30] for CB3, bit30 indicates list Viterbi 1st path, bit31 indicates list Viterbi 2nd path(if 2nd path is needed ) For NPDSCH, only bit[17:16] and bit[25:24] are used for CB0. Viterbi-in ram reading error Viterbi output buffer writing error This bit indicate that the time counter is exceed the limit of set value 3: This bit is to indicate that the odd memory is overwritten or not before 'UPDATED' is cleared. 2: This bit is to indicate that the even memory is overwritten or not before 'UPDATED' is cleared. 1: This bit is to indicate that the odd memory is updated or not. 0: This bit is to indicate that the even memory is updated or not. Result of checking in case that the decoded data is all zero 1: All zero 0 : Not zero data. Bit[23:16] for output even buffer: [17:16] for CB0, bit16 indicates list Viterbi 1st path, bit17 indicates list Viterbi 2nd path(if 2nd path is needed ) [19:18] for CB1, bit18 indicates list Viterbi 1st path, bit19 indicates list Viterbi 2nd path(if 2nd path is needed ) [21:20] for CB2, bit20 indicates list Viterbi 1st path, bit21 indicates list Viterbi 2nd path(if 2nd path is needed ) [23:22] for CB3, bit22 indicates list Viterbi 1st path, bit23 indicates list Viterbi 2nd path(if 2nd path is needed ) Bit[31:24]for output odd buffer; [25:24] for CB0, bit24 indicates list Viterbi 1st path, bit25 indicates list Viterbi 2nd path(if 2nd path is needed ) [27:26] for CB1, bit26 indicates list Viterbi 1st path, bit27 indicates list Viterbi 2nd path(if 2nd path is needed ) [29:28] for CB2, bit28 indicates list Viterbi 1st path, bit29 indicates list Viterbi 2nd path(if 2nd path is needed ) [31:30] for CB3, bit30 indicates list Viterbi 1st path, bit31 indicates list Viterbi 2nd path(if 2nd path is needed ) For NPDSCH, only bit[17:16] and bit[25:24] are used for CB0. Viterbi-in ram reading error Viterbi output buffer writing error This bit indicate that the time counter is exceed the limit of set value 3: This bit is to indicate that the odd memory is overwritten or not before 'UPDATED' is cleared. 2: This bit is to indicate that the even memory is overwritten or not before 'UPDATED' is cleared. 1: This bit is to indicate that the odd memory is updated or not. 0: This bit is to indicate that the even memory is updated or not. 0/1: gclk 2: rc_26m_div 3: xtal26m pclk_lptop source select: 0: rc26m 1: rc26m_div 2: xtal52m_div 3: clk_32k_root clk_32k_root source select: 0: clk_32k from pmic 1: clk_32k_div 32k divider work mode. 0: normal mode, 1: low power mode. clk_xtal6p5m gen 32k enable 32k divider normal mode step 32k divider lp mode step Lp mode value Lp mode direct control Update the Step Offset Value for 32k divider disable uart1 clock uart1 clock source select: 0: clk_32k_root 1: clk_xtal6p5m 2: clk_xtal52m 3: clk_rc26m_div bit type is changed from w1c to rc. uart1 clock divider update uart1 clock divider denom uart1 clock divider num disable uart2 clock uart2 clock source select: 0: clk_32k_root 1: clk_xtal6p5m 2: clk_xtal52m 3: clk_rc26m_div bit type is changed from w1c to rc. uart2 clock divider update uart2 clock divider denom uart2 clock divider num bit type is changed from w1c to rc. rc26m clock divider update rc26m clock divider denom rc26m clock divider num rc26m power on direct control 0x1: enable 0x1: disable 0x0: low current bias 0x1: high current bias osc tuning res: 0x0 min res 0x1 min+res1 �� 0x15 max res osc tuning cap: 0x0 min cap 0x1 min+cap1 �� 0x7 max cap bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. 0: mode1 1: mode2 soft confirm pu_done bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. 0: pd 1: pu 2: lp 0: pd 1: lp 0: active 2: sleep 3: psm 1: pm2 power down ram vrf_pd_time pm2 wakeup wait adie pu time, default is 2ms time delay before dbb reset release, reg value * 30us, default is 4ms default is 2.5ms ram vce power down direct control ram pgen direct control ram retention direct control 0: rc26m 1: xtal26m bit type is changed from w1c to rc. bit type is changed from w1c to rc. cmd_mipi_sr[15:0] cmd_mipi_sr[31:16] data_mipi_sr[15:0] data_mipi_sr[31:16] data_out[15:0] data_out[31:16] REVERSED data_valid_byte[3:0] REVERSED mipi_master_busy In read mode this register contains the sample received on the Rx chain. I component is located on bit[15:0] and Q component is located on bit[31:16].
This register accesses to the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data sample arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur.
The data written[29:0] into this register is the data transmitted. Any attempt to write data when the FIFO is full results in the write data being lost. Turn on/off the rf_if interface Turn on/off the DigRF mode Rx Fifo Overflow interrupt Enable Calibration bypass Rx swap I/Q Force Rx On. This bit is used only with the analog option. Force Decimator On Force start of calibation in receive mode
Writing a 1 to this bit launch the calibration phase. Write only bit, this bit doesn't need to be cleared. Writing a 1 to this bit resets and flush the receive Fifo.
Write only bit, this bit doesn't need to be cleared. Tx Fifo Overflow interrupt Enable Tx Fifo Underflow interrupt Enable: Force DAC On. This bit is used only with the analog option. Force DAC Off. This bit is used only with the analog option. Force Tx Oen. This bit is used only with the analog option. Force GMSK On. Tx swap I/Q. This bit is used only with the analog option. Writing a 1 to this bit resets and flush the transmit Fifo.
Write only bit, this bit doesn.t need to be cleared. Rx rate for DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
0 = No inversion
1 = Invert clock polarity Tx mode for the DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
0 = No inversion
1 = Invert clock polarity Shift input sample in DigRF mode only.
The Rx sample are on 16-bit, this field select a variable of bit among 16.
000 = 16-bit selected
001 = 15-bit selected
010 = 14-bit selected
011 = 13-bit selected
100 = 12-bit selected Select the sample alignement in DigRF mode only..
0 = MSB aligned sample
1 = LSB aligned sample Those bits indicate the number of data available in the Rx Fifo. Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. Rx overflow cause register
This bit indicates that an interruption was generated when the Rx fifo is overflow.
This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. Tx overflow cause register
This bit indicates that an interruption was generated when the Tx fifo is overflow.
This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. Tx underflow cause register
This bit indicates that an interruption was generated when the Tx fifo is underflow.
This bit is cleared when the Tx_underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. This bit indicates that the receiver received a new sample when the FIFO was already full.
The new sample is discarded. This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written This bit indicates that the user tried to write on the FIFO while it was already full.
This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written This bit indicates that the modulator tried to read on the FIFO while it was empty.
This bit is cleared when the Tx_Underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written Clear Rx Interrupt Overflow interrupt. Clear Tx Interrupt Overflow interrupt. Clear Tx Interrupt Underflow interrupt. Number of symbol to transmit 0 for GMSK, 1 for 8PSK Indicate an end of the transmit for this current burst Rx offset measured after calibration for I channel Rx offset measured after calibratio for Q channel Rx Gain digital Rx Gain analog Rx Gain enable Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Burst size on AHB bus
0 = Single access
1 = burst Access (4 words). Set FIFO mode .
0 = no fifo mode, transfer stop when the current transfer counter reaches zero. Channel must be re-enabled for future transfer.
1 = Fifo mode, when the current AHB address counter reaches the end address of the FIFO. AHB address counter is reloaded with the initial value. In FIFO mode channel is not disabled at the end of the transfer. In no fifo mode the channel is automatically disabled at the end of the transfer. In fifo mode the channel is disabled only when disabled write is performed in the control register. When 1 the fifo is empty Cause interrupt half tc when fifo mode is enable. Half of TC interrupt when fifo mode is enable status bit. Cause interrupt End of TC. Cause interrupt End of FIFO. Cause interrupt Half Transfer Count (This interruption is generated when the IFC has transferred 96 word). End of TC interrupt status bit. End of FIFO interrupt status bit. Half TC interrupt status bit. Current value of transfer counter. AHB Start Address. The last page address of the FIFO, it is the first address not used for the FIFO. The start address of the FIFO is specified by the register AHB_ADDR and the last page address of the FIFO is specified by this field. The size of the fifo (END_ADDR - START_ADDR) must be a multiple of burst of 4x32-bits. Transfer Count
In no FIFO mode, this bit indicated the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per transfer.
In FIFO mode this field define, after how many transfer an interrupt in generated. End TC Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. Half TC Mask interrupt. When one this interrupt is enabled NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is enabled Write one to clear end of TC interrupt. Write one to clear end of FIFO interrupt. Write one to clear end of Half TC interrupt. Write one to clear end of Half TC (the real one) interrupt. Current AHB address value. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Burst size on AHB bus
0 = Single access
1 = burst Access (4 words). Set FIFO mode .
0 = no fifo mode, transfer stop when the current transfer counter reaches zero. Channel must be re-enabled for future transfer.
1 = Fifo mode, when the current AHB address counter reaches the end address of the FIFO. AHB address counter is reloaded with the initial value. In FIFO mode channel is not disabled at the end of the transfer. In no fifo mode the channel is automatically disabled at the end of the transfer. In fifo mode the channel is disabled only when disabled write is performed in the control register. When 1 the fifo is empty Cause interrupt half tc when fifo mode is enable. Half of TC interrupt when fifo mode is enable status bit. Cause interrupt End of TC. Cause interrupt End of FIFO. Cause interrupt Half Transfer Count (This interruption is generated when the IFC has transferred 96 word). End of TC interrupt status bit. End of FIFO interrupt status bit. Half TC interrupt status bit. Current value of transfer counter. AHB Start Address. The last page address of the FIFO, it is the first address not used for the FIFO. The start address of the FIFO is specified by the register AHB_ADDR and the last page address of the FIFO is specified by this field. The size of the fifo (END_ADDR - START_ADDR) must be a multiple of burst of 4x32-bits. Transfer Count
In no FIFO mode, this bit indicated the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per transfer.
In FIFO mode this field define, after how many transfer an interrupt in generated. End TC Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. Half TC Mask interrupt. When one this interrupt is enabled NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is enabled Write one to clear end of TC interrupt. Write one to clear end of FIFO interrupt. Write one to clear end of Half TC interrupt. Write one to clear end of Half TC (the real one) interrupt. Current AHB address value. dump the 'data from dfe to nb core' to mem when the bit is 1, dump only when nb-core comes an pulse ,capture the set data numbers ,then stop when the bit is 0, dump all bit normal dump mode when the bit is 1, downsample enable when the bit is 0, disable get data from mem, simu the data format from dfe to nb core get data from mem, simu the data format from nbcore to dfe feed data rate 1.92MHz=0x20 192KHz=0x140, 96KHz=0x280, 38.4KHz=0x640, 32KHz=0x780 fifo empty siganl fifo empty signal clr feed fifo point clr dump fifo point when the bit is 1, nb use the rf_dma when the bit is 0, 2g use the rf_dma dump_ovfl irq dump_udfl irq feed_ovfl irq feed_udfl irq dump_ovfl when ifc is still working irq dump_udfl when ifc is still working irq dump_ovfl mask dump_udfl mask feed_ovfl mask feed_udfl mask dump_ovfl when ifc is still working mask dump_udfl when ifc is still working mask dump_ovfl before mask irq source dump_udfl before mask irq source feed_ovfl before mask irq source feed_udfl before mask irq source dump_ovfl when ifc is still working irq source dump_udfl when ifc is still working irq source dump_ovfl clr irq dump_udfl clr irq feed_ovfl clr irq feed_udfl clr irq dump_ovfl when ifc is still working clr irq dump_udfl when ifc is still working clr irq reserved Interface reset , expect apb/ spi reg, active low bit [15:0] of RFPLL SDM frequency for GSM RX and NB RX/TX bit [31:16] of RFPLL SDM frequency for GSM RX and NB RX/TX bit [34:32] of RFPLL SDM frequency for GSM RX and NB RX/TX reserved load SDM frequency of all PLLs(RFPLL, mcupll, NPLL) to RTL at the same time, write 0 before assert it reserved bypass freq_enable, i.e., SDM frequency of RFPLL takes effect immidiately when it is loaded into regsiter sdm rfpll dither_bypass_xcvsdm dividing ratio of RFPLL feedback clock to generate 26MHz clock used by GSM TX logic of DFE: 0b000: 182M divided by 7 0b001: 208M divided by 8 0b010: 234M divided by 9 0b011: 260M divided by 10 0b100: 26M with no division 0b101: 52M divided by 2 others: 208M divided by 8 reserved select for TX using RFPLL SDM: 0b0: GSM RX or NB RX or NB TX without PolarIQ. SDM frequency is from registers that are xcvsdm_reg2/1/0 0b1: GSM TX or NB TX with PolarIQ. SDM frequency is from DFE GSM former and PolarIQ split reset of RFPLL SDM, active low decimal bit width selection of RFPLL SDM output. It should be fixed to 3'h2 in 8809nez. 0b000: int divide 0b001: 1 bit decimal divide 0b010: 2 bits decimal divide 0b011: 3 bit decimal divide others: bypass SDM feedback clock inverse used by RFPLL SDM 0b0: no inverse 0b1: inverse reserved direct conrol of analog pu_npll value of analog pu_npll. It takes affect when pu_npll_dr1 is 0b1 direct conrol of baseband pu_npll value of baseband pu_npll. It takes affect when pu_npll_dr is 0b1 bit [31:16] of NPLL SDM frequency bit [15:0] of NPLL SDM frequency reserved bypass freq_enable, i.e., SDM frequency of NPLL takes effect immidiately when it is loaded into regsiter 0b0: no bypass 0b1: bypass decimal bit width selection of NPLL SDM output. It should be fixed to 3'b011 in 8809nez. 0b000: int divide 0b001: 1 bit decimal divide 0b010: 2 bits decimal divide 0b011: 3 bit decimal divide others: bypass SDM dither bypass of NPLL SDM 0b0: no bypass 0b1: bypass feedback clock inverse used by NPLL SDM 0b0: no inverse 0b1: inverse direct conrol of NPLL SDM reset reset of NPLL SDM, active low. It takes affect when npll_sdm_resetn_dr is 0b1 the time to release reset of NPLL SDM after pu_npll assert. 0b00: 10us 0b01: 12us 0b10: 15us 0b11: 40us no use reserved select of 30.72MHz clock of NPLL to ADC enable of 30.72MHz clock of NPLL to ADC enable of 61.44MHz clock of NPLL to DFE select of 61.44MHz clock of NPLL to DFE enable pu_npll from baseband NPLL pu status NPLL lock status NPLL SDM reset status NPLL sdm_clk_sel status NPLL clock status NPLL locked status reserved reserved software reset of logics to control NPLL pu and pd, active low the time to open NPLL clocks after pu_npll assert. 0b000: 10us+50us+1us 0b000: 10us+60us+1us 0b000: 10us+70us+1us 0b000: 10us+80us+1us 0b000: 10us+90us+1us 0b000: 10us+100us+1us NPLL locked time. 0b00: 1us 0b01: 2us 0b10: 3us 0b11: 4us reserved direct value of npll_clk2dig_en direct value of npll_clk_adc_en direct value of npll_clk2dig_sel direct value of npll_clk_adc_sel direct control of npll_clk2dig_en direct control of npll_clk_adc_en direct control of npll_clk2dig_sel direct control of npll_clk_adc_sel direct value of npll_clk_rstb direct control of npll_clk_rstb direct value of npll_sdm_clk_sel direct control of npll_sdm_clk_sel rfpll_cal: target freq[15:8] rfpll_cal: target freq[7:0] rfpll_cal: [12:8]: xcvpll_vco_bits[12:8] in software [13]: reserved [14]: xcvpll_cnt_enable in software [15]: xcvpll_cal_enable in software rfpll_cal: reset, active low rfpll_cal: [0]: pll_cal_hd, select haredare(1) or software(0) [1]: xcvpll_cal_opt [3:2]: xcvpll_cnt_delay_sel [6:4]: xcvpll_init_delay rfpll_cal: reserved rfpll_cal: xcvpll_vco_bits[7:0] in software rfpll_cal xcv_pll_cal_en rfpll_cal xcv_pll_cnt_en rfpll_cal xcvpll_cal_ready rfpll_cal xcvpll_vco_bits ADC LDO input ref calibration: 0: 659mV 7:750mV 15:851mV ADC CP LDO output calibration: 000:0.923V 001:0.947V 010:0.973V 011:1.000V 100:1.028V 101:1.059V 110:1.091V ADC LDO output calibration: 00: 910mV 01: 950mV 10: 982mV 11: 1.017V ADC power ripple adjust NB IQADC test bus ctrl signal: 011: 0000001 010: 0000010 001: 0000100 000: 0001000 100: 0010000 101: 0100000 110: 1000000 NB ADC test enable high 0x1:enable; 0x0:disable NB ADC CLK Polarity 0x0:falling edge align data 0x1:rising edge align data NB IQADC Delay adjust, mux: 00: I0 01: I1 NB IQ ADC reserved bits NB IQ ADC Loop time ctrl signal NB IQ ADC MSB time ctrl signal: 00: 30ps 01: 45ps 10,11: 58ps NB ADC Conversion step control NB ADC Conversion step control NB ADC Common mode voltage control: 011: 0000001 010: 0000010 001: 0000100 000: 0001000 100: 0010000 101: 0100000 110: 1000000. 0001000:700mV Adjust the delay time of adc vin signal: 00: delay 27ps 01: delay 54ps 10: delay 81ps 11: 108ps Adjust the adc reference voltage Adjust the adc reference voltage driving strength NB TX DAC Power resistor adjust signal NB TX DAC bias current control DAC Adapt DATA format selection ,low normal operation DAC Adapt iq swap control 0x0:disable 0x1:enable NB TX DAC reserved bit reserved reserved reserved reserved reserved reserved reserved clock selection of xcv_cal_clk[2] clock selection of xcv_cal_clk[1] clock selection of xcv_cal_clk[0]. 0b000: 26MHz/1024 0b001: 26MHz/512 0b010: 26MHz/256 0b011: 26MHz/128 0b100: 26MHz/64 0b101: 26MHz/32 0b110: 26MHz/16 0b111: 26MHz/8 clock inverse of xcv_cal_clk and inernal clocks clock enable of xcv_cal_clk and inernal clocks chip id0 reserved chip id1 revision_id reseved mcupll NPLL for eco for eco for eco for eco reserved reserved reserved reserved reserved reserved clk2 output pull down, 0x1 pull down to avss, 0x0 output enable vctrl test enable, 0x1 enable, 0x0 disable regulator output voltage selction frequency band selction, 0x0: low band; 0x1:high band frequency band selction, 000:min low band; 111:max high band cp current selction, 000:min current; 111:max current divider ratio vcdl dither enable, 1 enable, 0 disable vcdl dither mode selction mdll refclk test enable 0x1: enable;0x0:disable adjust digreg output voltage��Gray Code�� 0xC��0.8V adjust number of resistors connected to vcore: 0x4:100 �� refclk doubler enable�� 0x0:26MHz 0x1:52MHz reserved registers 1: r<0>:cp current x2 enable 0:disable 1:enable r<1>:ck to test driver enable 0:disable 1:enable reserved registers 2 source of din/pcon 0x0:din/pcon from sdm 0x1:din=8*(1+refmulti2_en),pcon=0 sdmclk sent to SDM in dfe enable: 0x0:enable sdmclk 0x1:disable sdmclk select sdm clk or fbc as fbc,always 0 charge pump output current control: current=(1.67+0.835*control_bits_decimal)uA vco freq range: 00:270~410M 11:300~520M 0x0:normal vcont 0x1:pull vcont of vco to high(avdd) 0x0:normal vcont 0x1:pull vcont of vco to low(avss) output buffer div ratio: 0x1:6/12(CLKDFE/CLKADC) 0x4:8/16(CLKDFE/CLKADC) select signal to be tested: 0x0:clk test 0x1:dvddrc 0x2:vcont 0x3:vcovdd software calibrates digreg output voltage: bit<2:0>: ref volatege��0x4 0.8V bit<3>:toggle signal bit<4>:calibration enable charge pump offset current: offset current=(0.625*control_bits_decimal)uA charge pump offset current enable: 0x0:disable offset current 0x1:enable offset current select clock to be test: 0x0:vco clk 0x1:sdm_clk pll test output enable: 0x0:enable 0x1:disable digreg calibration indicator: 0x0:smaller than ref voltage 0x1:bigger than ref voltage modulator enable 0x1:enable; 0x0:disable da enable gate voltage control 0x0: disable 0x1: enable supply on supply on reset reset modulator bias based on filter or self 0x1:filter 0x0:self modulator output voltage control 0x0 n:0.73V p:0.53V 0x1 n:1V p:0.22V 0x3 n:1.1V p:0.05V 0x7 n:1.13V p:0.03 modulator lsb gain control (dB) 0x7:-33; 0x6:-34.7; 0x5:-37.14; 0x4:-39.55; 0x3:-41.94; 0x2:-44.32; 0x1:-44.32; 0x0:-44.32; det path enable 0x0:disable; 0x1:enable; self nbias control 0x0:0.48V; ... 0x3F:1.18V self pbias control 0x0:0V; ... 0x3F:0.75V da gain control(dB) 0x0: -----; 0x1: -----; 0x2: -60.7; 0x3: -54.7; 0x4: -48.7; 0x5: -42.6; 0x6: -36.6; 0x7: -30.5; 0x8: ------; 0x9: -28.5; 0xA: -22.5; 0xB: -16.5; 0xC: -10.5; 0xD: -4.5; 0xE: 1.5; 0xF: 7.5; band cap tune da bias tune high power mode(PA on) / low power mode(PA off) loft mode on(1) / off(0) rg_nb_lo_ldo_cal pmos power switch bias from 0.9V to 1.05V tia input_cm control�� 0x0: vcmi=205mV 0x1: vcmi=220mV 0x2: vcmi=235mV 0x3: vcmi=250mV(default) 0x4: vcmi=265mV 0x5: vcmi=280mV 0x6: vcmi=295mV 0x7: vcmi=310mV tia_output_cm control; 0x0: vcmo=400mV 0x1: vcmo=450mV 0x2: vcmo=500mV 0x3: vcmo=550mV(default) 0x4: vcmo=600mV 0x5: vcmo=650mV 0x6: vcmo=700mV 0x7: vcmo=750mV tia output swing tuning; Rf diff vpp 0x1: 0.86k 0.4v 0x2: 1.75k 0.8v(default) 0x3: 3.5k 1.6v choose RX path signals choose tia output signals tia_op bias tuning; 0x0: IBP10u=5u(default) 0x1: IBP10u=6.25u 0x2: IBP10u=7.5u 0x3: IBP10u=8.75u 0x4: IBP10u=10u 0x5: IBP10u=11.25u 0x6: IBP10u=12.5u 0x7: IBP10u=13.75u select ibg or ic_vtr bypass tia_input filter_op bias tuning; 0x0: IC5U=3u 0x1: IC5U=3.6u 0x2: IC5U=5u(default) 0x3: IC5U=7.5u filter_tia Cf tuning; 0x0: 1.27p 0x1: 1.27p+45f 0x2: 1.27p+90f 0x15:1.27+45f��15=1.945p filter gain ctrl�� 0x0: 0dB 0x1: 1dB 0x2: 2dB 0x10:10dB(default) class AB output stage enhance filter orders or bypass�� 0x0: bypass 0x1: 1st_order 0x2: 3st_order(default) signal in phase or inverting transmission signal in phase or inverting transmission vco ldo reference voltage control signal 0000 650mV 0111 750mV 1111 850mV vco ldo output voltage control signal 000 900mV 001 925mV 010 950mV 011 975mV 100 1V 101 1.025V 110 1.05V 111 1.1V vco bias RC control signal 00 5M 01 10M 10 15M 11 20M vco cbank aux control signal 0 40f 15 200f vco control signal for HP/LP mode,1 for LP mode,0 for HP mode. lo ldo reference voltage control signal 0000 650mV 0111 750mV 1111 850mV lo ldo output voltage control signal 000 850mV 100 900mV 111 950mV lo div mode control signal, 00 for div8, 01 for div6, 10 for div4, 11 for div2 lo div mode control signal, 00 for div8, 01 for div6, 10 for div4, 11 for div2 lo trx ldo reference voltage control signal 0000 650mV 0111 750mV 1111 850mV lo trx ldo output voltage control signal 000 850mV 100 900mV 111 950mV lo trx div mode control signal, 00 for div8, 01 for div6, 10 for div4, 11 for div2 DET PATH att tune Ox0:min att= -8 dB ... Ox7:max att= -17 Db 0x8~0xf: reserved Res ATT gain control 0x0: -36dB 0x1: -30dB �� 0x6: 0dB 0x7~0xf: reserved reserved use gpio pad to do tx/rx chain test 0x0 close the test switch 0x15 open the test swtich VCO test buffer selection 0x0: mdll 0x1: tx lo 0x2: rx lo 0x3: none VCO test buffer strength 0x0: weak 0x1: medium 0x2: strong 0x3: strongest VCO test buffer enable 0x0:enable 0x1:disable LNA LDO output voltage control 0x0 0.91V; 0x1 0.93V; 0x2 0.95V; 0x3 0.97V; 0x4 0.99V; 0x5 1.01V; 0x6 1.03V; 0x7 1.05V LNA bias current control 0x0:4mA; 0x1:4.5mA; 0x2:5mA; 0x3:5.5mA LNA band select 0x0: LB; 0x1: HB LNA gain control; 0x5:61db; 0x4:55db; 0x3:49db; 0x2:40db; 0x1:31db; 0x0:22db reserved bit LNA cascode transistor gate voltage control 0x0: nbias 0.65 pbias 0.35 0x1: nbias 0.68 pbias 0.38 0x2: nbias 0.71 pbias 0.41 0x3: nbias 0.74 pbias 0.46 0x4: nbias 0.77 pbias 0.49 0x5: nbias 0.8 pbias 0.52 0x6: nbias 0.83 pbias 0.55 0x7: nbias 0.86 pbias 0.758 LNA input VBIS resistor control 0x0:60k; ox1:30k LNA low gain ATT network tune; to fine tune the gain step(9dB) between gaincode=3 and gaincode=2; RX MIXER LO Vbias control; 0x0:0.85v; ��; 0x7:1.05v RX PGA ibias control; 0x0:1.4mA; 0x1:1.6mA; 0x2:1.8mA; 0x3:2mA RX PGA input resistor control; 0x0:0 �� 0x7:200 RX bandwidth res control; 0x0:min ; 0x1:min+6dB; 0x2:min+12dB; 0x3:min+18dB:0x4:min+24dB RX bandwidth cap control; 0x0:min gain; 0x1:min+6dB; 0x2:min+12dB; 0x3:min+18dB RX PGA gain control; 0x0:min ; 0x1:min+6dB; 0x2:min+12dB; 0x3:min+18dB;0x4:min+24dB RX PGA bypass enable; 0x0:disable; 0x1:enable RX DCOC I path current control; 0x0:minimun output current; �� 0xFF:maximum output current RX DCOC Q path current control; 0x0:minimun output current; ��. 0xFF:maximum output current RX DCOC current resolution control; 0x0:10uA/bit; 0x1:20uA/bit; 0x2:40uA/bit; 0x3:80uA/bit Opamp bias control�� 0x0: 3u 0x1: 3.6u 0x2: 5u 0x3: 7.5u Opamp drive strength�� [0]: the 1th opamp //1, LP enable [1]: the 2th opamp //1, LP enable [2]: the 3th opamp //1, LP enable frist stage gain :default 15dB 0x0: 6dB 0x1: 7dB 0x2: 8dB 0x3: 9dB 0x4: 10dB 0x5: 11dB 0x6: 12dB 0x7: 13dB 0x8: 14dB 0x9: 15dB other: 6dB second stage gain: defalut 18dB 0x0: 0dB 0x1: 6dB 0x2: 12dB 0x3: 18dB IF ctrl 0x0: 0 0x1: 100KHz 0x2: 200KHz filter BW ctrl Filter I path & Q Path swap Filter aux_path(calibration path) enable 0x0: disable 0x1: enable Filter clk edge selection Filter calibration mode 0x0: lowpass mode 0x1: bandpass mode Filter BW calibration enable 0x0: disable 0x1: enable reserved bit RFPLL reserved bit Power switch for Sinc Filter 1111 POWER OFF/HighZ 1000 default 0000 LowZ Power switch for REF generation, 208M/26M/52M 1111 POWER OFF/HighZ 1000 default 0000 LowZ Power switch for PFD div&ref seperated dvdd 1111 POWER OFF/HighZ 1000 default 0000 LowZ Power switch for pfd out 1111 POWER OFF/HighZ 1000 default 0000 LowZ PLL regulator1 vout ctrl:0.9+15mV*BIN2DEC(REG_Vctrl-1000) PLL regulator2 vout ctrl:0.9+15mV*BIN2DEC(REG_Vctrl-1000) PLL regulator div2 vout ctrl:0.9+15mV*BIN2DEC(REG_Vctrl-1000) PLL regulator prescaler vout ctrl:0.9+15mV*BIN2DEC(REG_Vctrl-1000) PLL ref x2 PLL ref source: 0 for MDLL, 1 for 26M sdm clk source: 0 for fbc, 1 for fref afc clk source: 0 for ref, 1 for refb div modulus sync clk sel pfd output res afc initial cbank setting:< *6>(cal_bit<1:0>),< *6>(cal_bit<0:1>) afc enable afc counter enable open loop enable sinc filter switch aux sel notch bypass enable sinc filter path number/ KVCO cp current bit lpf r1, 00 7k 10 1.2k//7k 01 0.8k//7k 11 1.2k//0.8k//7k lpf r1 aux sinc mode sel low power mode, 1 for iot charge pump current temperature tracking code from spi 1111 -40 680 ohm 1000 40 540 ohm 0001 120 330 ohm charge pump current temperature tracking code from THM DET block, enable signal 1 code from THM DET 0 code from software rfpll reference 208M clock pulser generation, pulse width ~ 400 ps LDO 2nd stage output current enable signal 0 only ON when FC==1 1 always ON charge pump current temperature tracking code. Read from CP control word. bandgap power up 0x0:disable 0x1:enable bandgap enable 0x0:enable 0x1:disable bg current calibration @different process corner TT ,FS,SF: 0x7; FF:0xe; SS:0x2 thermal bias switch 0x0:disable 0x1:enable reserved bit themal top chip enable LDO output voltage control Ox0: 0.91V 0x1: 0.93V 0x2: 0.95V 0x3: 0.97V Ox4: 0.99V 0x5: 1.01V 0x6: 1.03V 0x7: 1.05V reserved bit choose thm DAC input 0x0:DAC input=RG_NB_THM_DAC_TEST[7:0]; 0x1:DAC input from digital for thm calibraiton 0x0:dac range: 331mV~754mV 0x1: dac_range:377m V~804mV Themal det test mode en themal test signal choose: 0x0:vbe out 0x1:vdac out RG_NB_THM_RESERVED[15]:RG_NB_THM_DIV_SET,set thm digital clk div ratio: 0x0 div ratio=64, 0x1 div ratio=512; RG_NB_THM_RESERVED[14:12]:RG_NB_THM_HYS_SET,set temperature change for interrupt signal out; RG_NB_THM_RESERVED[11:8]:RG_NB_THM_DET_SET,set auto test time interval; RG_NB_THM_RESERVED[7]:RG_NB_THM_INT_RESET,reset AD_TS_INT; RG_NB_THM_RESERVED[6:0]:reserved; themal div CLK output interrupt signal testing result valid signal themal data output,valid on the clock rising edge themal test data output power detector tuning vcm1(VDD=0.9V) Ox0:VDD*7/39 Ox1:VDD*8/39 Ox2:VDD*9/39 Ox3:VDD*10/39 Ox4:VDD*11/39 Ox5:VDD*12/39 Ox6:VDD*13/39=300 mV Ox7:VDD*14/39 power detector tuning vcm2(VDD=0.9V) Ox0:VDD*15/44=306.8 mV Ox1:VDD*16/44=327.3 mV Ox2:VDD*17/44=347.7 mV Ox3:VDD*18/44=368.2 mV Ox4:VDD*19/44=388.6 mV Ox5:VDD*20/44=409.1 mV Ox6:VDD*21/44=429.5 mV Ox7:VDD*22/44=450.0 mV pd att tune Ox0:min att= -8 dB ... Ox7:max att= -17 dB tia gain control Ox0:min tia gain 0x1:min+2dB 0x2:min+4dB 0x3:min+6dB square circuit bias current control Ox0: 12uA 0x1: 15uA 0x2: 18uA 0x3: 21uA Ox4: 24uA 0x5: 27uA 0x6: 30uA 0x7: 33uA diff to single opa bias current control Ox0: 3uA 0x1: 3.75uA 0x2: 5uA 0x3: 7.5uA output cm voltage control Ox0: 367.5mV 0x1: 400mV 0x2: 435mV 0x3: 469mV 0 bypass 1 enable diff to single opa ab output current 0:90uA;1:30uA 0x1 enable 0x0 disable reserved themal top chip enable LDO output voltage control Ox0: 0.91V 0x1: 0.93V 0x2: 0.95V 0x3: 0.97V Ox4: 0.99V 0x5: 1.01V 0x6: 1.03V 0x7: 1.05V reserved bit choose thm DAC input 0x0:DAC input=RG_NB_THM_DAC_TEST[7:0]; 0x1:DAC input from digital for thm calibraiton 0x0:dac range: 331mV~754mV 0x1: dac_range:377m V~804mV Themal det test mode en themal test signal choose: 0x0:vbe out 0x1:vdac out RG_NB_THM_RESERVED[15]:RG_NB_THM_DIV_SET,set thm digital clk div ratio: 0x0 div ratio=64, 0x1 div ratio=512; RG_NB_THM_RESERVED[14:12]:RG_NB_THM_HYS_SET,set temperature change for interrupt signal out; RG_NB_THM_RESERVED[11:8]:RG_NB_THM_DET_SET,set auto test time interval; RG_NB_THM_RESERVED[7]:RG_NB_THM_INT_RESET,reset AD_TS_INT; RG_NB_THM_RESERVED[6:0]:reserved; themal div CLK output interrupt signal testing result valid signal themal data output,valid on the clock rising edge themal test data output power detector tuning vcm1(VDD=0.9V) Ox0:VDD*7/39 Ox1:VDD*8/39 Ox2:VDD*9/39 Ox3:VDD*10/39 Ox4:VDD*11/39 Ox5:VDD*12/39 Ox6:VDD*13/39=300 mV Ox7:VDD*14/39 pd att tune Ox0:min att ... Ox7:max att tia gain control Ox0:min tia gain 0x1:min+2dB 0x2:min+4dB 0x3:min+6dB square circuit bias current control Ox0: 12uA 0x1: 15uA 0x2: 18uA 0x3: 21uA Ox4: 24uA 0x5: 27uA 0x6: 30uA 0x7: 33uA output cm voltage control Ox0: 367.5mV 0x1: 400mV 0x2: 435mV 0x3: 469mV 0 bypass 1 enable 0x1 enable 0x0 disable Enable the rf spi 1 = Enable 0 = Disable (will finish current command anyway) Chip select polarity 1 = the chip select is active low 0 = the chip select is active high DigRF Read style mode 1 = DigRF Read style mode (read after CS disabled) 0 = SPI Read mode (read during write) DigRF style clocked back to back mode 1 = clocked back to back transfers using turnarround timing only when more data are present in the FIFO. 0 = stop the clock between each access according to CS_End_Hold and CS_Pulse_Min timings Input mode 1 = Record input data to input FIFO 0 = No input data SPI Clock polarity 1 = the clock disabled level is high, and the first edge is a falling edge. 0 = the clock disabled level is low, and the first edge is a rising edge. Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the Transfer start and the first clock edge. Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the Transfer start and the first data out. Transfer start to first data in sampled delay value from 0 to 3 is the number of spi clock half period between the Transfer start and the first data sampled in. The DI_Delay only specify the sampling time, for frame size, the counter is based on the DO_Delay even in DigRF read mode. Transfer start to CS activation delay value from 0 to 3 is the number of spi clock half period between the Transfer start and the CS activation edge. Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer (DO) and the CS deactivation edge. Not used for Clocked_Back2Back mode Number of data in the frame, or number of out data in DigRF read mode. The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits) The frame size is given for the number of data, the actual number of clock pulses might be greater. First if Clock_Delay < DO_Delay an extra clock pulse is generated, second in case of DigRF read or back2back, some more clock pulses will be generated. Chip select deactivation to new start of transfer minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new transfer start (transfer will start only if more data are available in the transmit FIFO) Not used for Clocked_Back2Back mode When DigRF input mode: The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits) When Normal SPI input mode: When 0: regular mode, SPI_DO pin as output only; Other: Value from 1 to 31 is the number of data out to transfert before the SPI_DO pin switch to input; TurnAround time: end of write frame to start of read frame delay (in cycles) value from 0 to 3 is the number of spi clock period between the end of the output frame (without the DO_Delay) and the Input Frame start. Also used for Clocked_Back2Back mode, when Clocked_Back2Back=1 and there is more data available in the transmit FIFO: value from 0 to 3 is the number of spi clock period between the end of the frame (without the DO_Delay) and the start of the new frame. (It can also be seen as the number of spi clock period between the end of the last data bit and the start of the new data bit.) The SPI activity status 1 = A transfer is in progress 0 = The transfer is done Error status 1 = a new command (or gain) has been requested while a command was in progress. 0 = No error Write 1 to clear. The Gain Table overflow status. 1 = Too many data has been written in the table Writing a 1 clear the overflow status. The Gain Table underflow status. 1 = a next gain request has been received while the read pointer was already at the top of the table. Writing a '1' clear the underflow status. Command FIFO level, number of command in the FIFO The command FIFO overflow status. 1 = Too many data has been written in the FIFO Writing a 1 clear the overflow status. The command FIFO underflow status. 1 = Data has been requested to read while the FIFO was empty Writing a 1 clear the underflow status. Command FIFO level, number of bytes in the FIFO The command data FIFO overflow status. 1 = Too many data has been written in the FIFO Writing a 1 clear the overflow status. The command data FIFO underflow status. 1 = Data has been requested to read while the FIFO was empty Writing a 1 clear the underflow status. Receive FIFO level, number of bytes in the FIFO The receive FIFO overflow status. 1 = Too many data has been written in the FIFO Writing a 1 clear the overflow status. The receive FIFO underflow status. 1 = Data has been requested to read while the FIFO was empty Writing a 1 clear the underflow status. Read in the receive FIFO Writing this register will write to Cmd_Data fifo (same as Cmd_Data register). This is because this address is used by the IFC channels to access the fifos. Writing 1 send the next command in the Cmd FIFO (This replace the TCU next cmd signal) Writing 1 flush both Cmd, and cmd_data FIFO, don't do it when SPI is active (transfer in progress) Writing 1 flush the receive data FIFO, don't do it when SPI is active (transfer in progress) Writing 1 place the read pointer at the beginning of the gain table. don't do it when SPI is active (transfer in progress) Writing 1 place the write pointer at the beginning of the gain table allowing to fill the table. Writing 1 change all the ouputs of the SPI interface to drive a logical '0'. This mode stops when a new command is requested to be send (by TCU) or when writting 0 to this register. This mode is useful when powering off the tranciever chip connected to the RF_SPI. Write the size in bytes of the next command in the FIFO Write 1 to mark the command. Marked commands are discarded if Enable_Rf_Spi_Marked_Cmd is low in the tcu register. Write in the Command data FIFO Size of a Gain command in bytes. Write in the Gain Table (the pointer auto increments) Cmd_Data_DMA_Done IRQ Cause bit 1 = the IRQ was triggered by the end of the DMA transfer to the cmd FIFO. To clear it write 1 in this bit or Cmd_Data_DMA_Done_Status bit. Cmd_FIFO_empty IRQ Cause bit 1 = the IRQ was triggered because the Cmd_FIFO is empty. To clear it, fill the FIFO. Cmd_Threshold IRQ Cause bit 1 = the IRQ was triggered because the Cmd_FIFO level is below the Cmd_Threshold. To clear it, fill the FIFO. Rx_FIFO_full IRQ Cause bit 1 = the IRQ was triggered because the Rx_Data_FIFO is full. To clear it, read from the FIFO. Rx_Threshold IRQ Cause bit 1 = the IRQ was triggered because the Rx_Data_FIFO level is over the Rx_Threshold. To clear it, read from the FIFO. Error IRQ Cause bit 1 = the IRQ was triggered because an error occured. Read the Status register to check the kind of error. To clear it, clear it in the Status register. Cmd_Data_DMA_Done IRQ Status bit 1 = the end of the DMA transfer to the cmd FIFO occured. To clear it write 1 in this bit or Cmd_Data_DMA_Done_Cause bit. Cmd_FIFO_empty IRQ Status bit 1 = the Cmd_FIFO is empty. Cmd_Threshold IRQ Status bit 1 = the Cmd_FIFO level is bellow the Cmd_Threshold. Rx_FIFO_full IRQ Status bit 1 = the Rx_Data_FIFO is full. Rx_Threshold IRQ Status bit 1 = the Rx_Data_FIFO level is over the Rx_Threshold. Error IRQ Status bit 1 = an error occured. Read the Status register to check the kind of error. Cmd_Data_DMA_Done IRQ Mask bit 1 = the Cmd_Data_DMA_Done IRQ is enabled 0 = the Cmd_Data_DMA_Done IRQ is disabled Cmd_FIFO_empty IRQ Mask bit 1 = the Cmd_FIFO_empty IRQ is enabled 0 = the Cmd_FIFO_empty IRQ is disabled Cmd_Threshold IRQ Mask bit 1 = the Cmd_Threshold IRQ is enabled 0 = the Cmd_Threshold IRQ is disabled Rx_FIFO_full IRQ Mask bit 1 = the Rx_FIFO_full IRQ is enabled 0 = the Rx_FIFO_full IRQ is disabled Rx_Threshold IRQ Mask bit 1 = the Rx_Threshold IRQ is enabled 0 = the Rx_Threshold IRQ is disabled Error IRQ Mask bit 1 = the Error IRQ is enabled 0 = the Error IRQ is disabled Command FIFO Threshold, number of command in the FIFO bellow which the Cmd_Threshold_IRQ is triggered. Receive FIFO Threshold, number of bytes in the FIFO above which the Rx_Threshold_IRQ is triggered. Clock Divider The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2 When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz. for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. Base address of block in int_Rom patched (corresponding data are read from int_SRam) Rom patch Ram Space Used for store the patch instead of rom, when patch is valid Enables the SIM Card IF module Selects the parity generation/detection Parity Error Receive Feed-through
0 = Don't store bytes with detected parity errors
1 = Feed-through bytes with detected parity errors Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer.
0 = Enable NULL character filtering, NULL characters are not reported if not data.
1 = Disable NULL character filtering. NULL characters (0x60) are transferred to the SCI data buffer. Manual SCI Clock Stop control. Manually starts and stops the SCI clock. This bit must be set to '1' when Autostop mode is enabled.
0 = Enable the SCI clock
1 = Disable SCI clock Enables automatic clock shutdown when command is complete. Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol.
0 = Auto clock control not enabled. SCI clock controlled by SCI_Clockstop bit
1 = Auto clock control enabled. Sets the transmission and reception bit order:
0 = LSB is sent/recieved first (Direct convention)
1 = MSB is sent/received first (Inverse convention) Logic Level Invert:
0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit. (Direct convention)
1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit. (Inverse convention) Parity Error signal length. This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU
0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU
1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU Enable or disable parity error checking on the receive data
0 = Disable parity error checking
1 = Enable parity error checking Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown)
0 = Stop clock at low level
1 = Stop clock at high level tunning the sample local. Automatic Reset Generator. Write a '1' to this bit to initiate an automatic reset procedure on the SIM. Write '0' to switch back to SCI_Reset control (bit 20). An ARG interrupt will be generated if the ARG process succeeded or failed. The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected. This bit needs to be cleared between ARG attempts. Automatic format detection. This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention.
1 = Enable TS detection and automatic convention settings programming
0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention 1 = Enable automatic resend of characters when Tx parity error is detected
0 = Disable automatic resend 1 = pulldown
0 = pullup Direct connection to the SIM card reset pin. This is overridden when ARG_H is enabled
0 = SCI_Reset low voltage
1 = SCI Reset high voltage This selects between two delay times for the automatic clock stop startup and shutdown:
0 = short delay
Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks
1 = long delay
Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks Input data average enable.
0 = Disable
1 = Enable auto clear. Allows fine control of the parity check position during the parity error time period. These bits are reserved and must be written as '00' for the SCI module to work properly:
"11" = Ser In <- Ser Out loopback
"10" = Ser In <- Ser In (unmasked)
others = Ser In <- Ser In masked with Txing_H (normal mode) Returns the status of the Rx FIFO:
0 = Rx FIFO empty
1 = There is at least 1 character in the Rx FIFO Returns the status of the Tx FIFO:
0 = Tx FIFO is full
1 = There is at least 1 free spot in the Tx FIFO Returns the status of the automatic format detection after reset:
0 = TS character has not been detected in the ATR
1 = TS character has been detected and SCI module is using the automatic convention settings

This bit is cleared when the AFD_En bit is cleared Returns the status of the automatic reset procedure:
0 = ARG detection has failed
1 = ARG detection has detected that the SIM has responded to the reset

This bit is used in conjunction with the ARG interrupt. The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process. This bit can be used to determine the success or failure. This is the status of the Reset pin when automatic reset generation is enabled. This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection') Status of the control signal to the clock control module. This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready'
0 = SCI clock may be on or off but is not ready for use
1 = SCI clock is on and ready for use Status bit of the Sci clock.
0 = Sci clock is ON
1 = Sci clock is OFF A receive parity error was detected. Reading this register clears the bit. A transmit parity error was detected. Reading this register clears the bit. The internal receive FIFO has reached an overflow condition. Reading this register clears the bit. The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit. Returns the state of the clock management state machine when AutoStop mode is enabled. This value is '00' when manual mode is selected. Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. Reading this register will read from the receive data FIFO. Clock divider for generating the baud clock from the SCI clock. This value must match the value used by the SIM card whose default value is 0x174. Speed mode enable.
0 = Low speed mode
1 = High speed mode(372/32, 372/64, 512/64) Rx_clk_cnt wrap value. Secondary clock divider for generating 16x baud clock. Main clock divider to generate the SCI clock. This value should be calculated as follows:
MainDiv = Clk_Sys/(2xSCI_Clk) - 1
where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification. Inverts the polarity of the SCI clock to the SIM card only.
0 = No inversion
1 = Invert external SCI clock Inverts SCI clock to the SIM card .
0 = No inversion
1 = Invert external SCI clock This value should be programmed with the number of expected characters to receive. It will be decremented each time a character is actually received and should be 0 when the transfer is complete. If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero. When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete. This should be used for multi-transfer commands where the clock must not be shut down until the command is complete. This bit must be programmed for each transfer.
1 = Keep clock on
0 = Allow clock shutdown when transfer is complete This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters. This should be programmed depending on the SIM's ATR. The total ETU guard time will be ChGuard + 1. Turnaround guard time configuration. This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character. The minimum time specified in the SIM recommendation is 16 ETU. The number of ETUs can be calculated using the following formula:
Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard Work Waiting Time factor. A timeout will be generated when the WWT is exceeded. The WWT is calculated by:
WWT = 960 x WI x (F/Fi)
where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS.
The SCI_WI value must be calculated as follows:
SCI_WI = WI * D
Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure. Number of times to try resending character when the SIM indicates a parity error. Value of the character to be filtered. 0x60 is the NULL character in the SIM protocol. If character filtering is enabled, the first 0x60 character that is received by the SIM during a transfer will not be recorded. The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data. This filter has no effect on characters within the datastream. Clear RX FIFO. Clear TX FIFO. UNDOCUMENTED FEATURE Number of expected Rx characters, as programmed in the RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. Number of expected Rx characters, as programmed in the RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is a READ ONLY register that returns the logical and of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt. Bits 21:16 return the status of the interrupt which is the interrupt state before the mask is applied. These bits should only be used for debugging. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt. Set this bit to 1'b0, then when pa_en = 1,sci stops work. Status of pa_en. Status of write operation. Status of write operation. Status of write operation. Status of write operation. Status of write operation. after thold0, pull down rst after thold1, pull down clk and io after thold2, fsm into ST3. (unused) Controls the big endian or little endian of the FIFO data.
Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
"000": the order is not changed.
Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D".
"001": reversed on byte.
Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A".
"010": reversed on half word.
Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B".
"010": reversed on bit.
Byte3="B0",Byte2="30,Byte1="D0",Byte0="50".
"100": reversed on bit.
Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
Active Low. Write to the transmit FIFO Read in the receive FIFO SD/MMC operation begin register, active high.
When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. SD/MMC operation suspend register, active high. '1'indicates having a response,'0'indicates no response. Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. '1' indicates data operation, which includes read and write. '1' means write operation,'0' means read operation. '1'means multiple block data operation. '1' means the SD/MMC operation is not over. '1' means SD/MMC is busy. '1' means the data line is busy. '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. Response CRC checks error register '1' means response CRC check error. '1' means the card has no response to command. CRC check for SD/MMC write operation
"101" transmission error
"010" transmission right
"111" flash programming error 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. SDMMC DATA 3 value. SD/MMC command register. SD/MMC command argument register, write data to the SD/MMC card. SD/MMC response index register. Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. 95 to 64 bit response argument of R2. 63 to 32 bit response argument of R2. 31 to 0 bit response argument of R2. SD/MMC data width:
0x1: 1 data line
0x2: 2 reserved
0x4: 4 data lines
0x8: 8 data lines SD/MMC size of one block:
0-1:reserved
2: 1 word
3: 2 words
4: 4 words
5: 8 words
6: 16 words

11: 512 words
12-15 reserved Block number that wants to transfer. '1' means no response. '1' means CRC error of response. '1' means CRC error of reading data. '1' means CRC error of writing data. '1' means data transmission is over. '1' means tx dma done. '1' means rx dma done. '1' means DAT1_IN is low when not DL_busy. '1' means DAT0_IN is low when not DL_busy. '1' means no response is the source of interrupt. '1' means CRC error of response is the source of interrupt. '1' means CRC error of reading data is the source of interrupt. '1' means CRC error of writing data is the source of interrupt. '1' means the end of data transmission is the source of interrupt. '1' means tx dma done is the source of interrupt. '1' means rx dma done is the source of interrupt. '1' means DAT1_IN is the source of interrupt. '1' means DAT0_IN is the source of interrupt. When no response, '1' means INT is disable. When CRC error of response, '1' means INT is disable. When CRC error of reading data, '1' means INT is disable. When CRC error of writing data, '1' means INT is disable. When data transmission is over, '1' means INT is disable. when tx dma done, '1' means INT is disabled. '1' means rx dma done, '1' means INT is disabled. '1' means DAT1 is low when not DL_busy, '1' means INT is disabled. '1' means DAT0 is low when not DL_busy, '1' means INT is disabled. Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). This register may delay the mclk output. When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. Invert Mclk. Controls the big endian or little endian of the FIFO data.
Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
"000": the order is not changed.
Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D".
"001": reversed on byte.
Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A".
"010": reversed on half word.
Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B".
"010": reversed on bit.
Byte3="B0",Byte2="30,Byte1="D0",Byte0="50".
"100": reversed on bit.
Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
Active Low. Write to the transmit FIFO Read in the receive FIFO SD/MMC operation begin register, active high.
When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. SD/MMC operation suspend register, active high. '1'indicates having a response,'0'indicates no response. Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. '1' indicates data operation, which includes read and write. '1' means write operation,'0' means read operation. '1'means multiple block data operation. '1' means the SD/MMC operation is not over. '1' means SD/MMC is busy. '1' means the data line is busy. '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. Response CRC checks error register '1' means response CRC check error. '1' means the card has no response to command. CRC check for SD/MMC write operation
"101" transmission error
"010" transmission right
"111" flash programming error 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. SDMMC DATA 3 value. SD/MMC command register. SD/MMC command argument register, write data to the SD/MMC card. SD/MMC response index register. Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. 95 to 64 bit response argument of R2. 63 to 32 bit response argument of R2. 31 to 0 bit response argument of R2. SD/MMC data width:
0x1: 1 data line
0x2: 2 reserved
0x4: 4 data lines
0x8: 8 data lines SD/MMC size of one block:
0-1:reserved
2: 1 word
3: 2 words
4: 4 words
5: 8 words
6: 16 words

11: 512 words
12-15 reserved Block number that wants to transfer. '1' means no response. '1' means CRC error of response. '1' means CRC error of reading data. '1' means CRC error of writing data. '1' means data transmission is over. '1' means tx dma done. '1' means rx dma done. '1' means no response is the source of interrupt. '1' means CRC error of response is the source of interrupt. '1' means CRC error of reading data is the source of interrupt. '1' means CRC error of writing data is the source of interrupt. '1' means the end of data transmission is the source of interrupt. '1' means tx dma done is the source of interrupt. '1' means rx dma done is the source of interrupt. When no response, '1' means INT is disable. When CRC error of response, '1' means INT is disable. When CRC error of reading data, '1' means INT is disable. When CRC error of writing data, '1' means INT is disable. When data transmission is over, '1' means INT is disable. when tx dma done, '1' means INT is disabled. '1' means rx dma done, '1' means INT is disabled. Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). This register may delay the mclk output. When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. Invert Mclk. configure the range (1-18) of code number registers configure the refreshed cycle in pclk domain when change output data from another code number register. this is a pulse signal this is a pulse signal hardware enable and software clear. pattern 0 output. pattern 1 output. pattern 2 output. pattern 3 output. pattern 4 output. pattern 5 output. pattern 6 output. pattern 7 output. pattern 8 output. pattern 9 output. pattern 10 output. pattern 11 output. pattern 12 output. pattern 13 output. pattern 14 output. pattern 15 output. pattern 16 output. pattern 17 output. pattern 0 of pin_oen. pattern 1 of pin_oen. pattern 2 of pin_oen. pattern 3 of pin_oen. pattern 4 of pin_oen. pattern 5 of pin_oen. pattern 6 of pin_oen. pattern 7 of pin_oen. pattern 8 of pin_oen. pattern 9 of pin_oen. pattern 10 of pin_oen. pattern 11 of pin_oen. pattern 12 of pin_oen. pattern 13 of pin_oen. pattern 14 of pin_oen. pattern 15 of pin_oen. pattern 16 of pin_oen. pattern 17 of pin_oen. bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. Port 0 read channel address miss int enable 1: Enable 0: Disable bit type is changed from wr to rw. Port 0 write channel address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read channel address miss int write-clear bit type is changed from wc to rc. Port 0 write channel address miss int write-clear Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal control bb_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nbiot_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control cipher_f8_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control bb_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nbiot_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control cipher_f8_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access bit type is changed from wr to rw. id0 mstid_0 master id control bit type is changed from wr to rw. id0 mstid_1 master id control bit type is changed from wr to rw. id0 mstid_2 master id control bit type is changed from wr to rw. id0 mstid_3 master id control bit type is changed from wr to rw. id0 mstid_4 master id control bit type is changed from wr to rw. id0 mstid_5 master id control bit type is changed from wr to rw. id0 mstid_6 master id control bit type is changed from wr to rw. id0 mstid_7 master id control bit type is changed from wr to rw. id1 mstid_0 master id control bit type is changed from wr to rw. id1 mstid_1 master id control bit type is changed from wr to rw. id1 mstid_2 master id control bit type is changed from wr to rw. id1 mstid_3 master id control bit type is changed from wr to rw. id1 mstid_4 master id control bit type is changed from wr to rw. id1 mstid_5 master id control bit type is changed from wr to rw. id1 mstid_6 master id control bit type is changed from wr to rw. id1 mstid_7 master id control bit type is changed from wr to rw. clk_gate_bypass bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. Port 0 read channel address miss int enable 1: Enable 0: Disable bit type is changed from wr to rw. Port 0 write channel address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read channel address miss int write-clear bit type is changed from wc to rc. Port 0 write channel address miss int write-clear Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal control sci1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_rf_spi_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_tcu_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rf_if_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rf_interface_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dfe_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rffe_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control bb_ifc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sci1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_rf_spi_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_tcu_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rf_if_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rf_interface_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dfe_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rffe_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control bb_ifc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access bit type is changed from wr to rw. id0 mstid_0 master id control bit type is changed from wr to rw. id0 mstid_1 master id control bit type is changed from wr to rw. id0 mstid_2 master id control bit type is changed from wr to rw. id0 mstid_3 master id control bit type is changed from wr to rw. id0 mstid_4 master id control bit type is changed from wr to rw. id0 mstid_5 master id control bit type is changed from wr to rw. id0 mstid_6 master id control bit type is changed from wr to rw. id0 mstid_7 master id control bit type is changed from wr to rw. id1 mstid_0 master id control bit type is changed from wr to rw. id1 mstid_1 master id control bit type is changed from wr to rw. id1 mstid_2 master id control bit type is changed from wr to rw. id1 mstid_3 master id control bit type is changed from wr to rw. id1 mstid_4 master id control bit type is changed from wr to rw. id1 mstid_5 master id control bit type is changed from wr to rw. id1 mstid_6 master id control bit type is changed from wr to rw. id1 mstid_7 master id control bit type is changed from wr to rw. id2 mstid_0 master id control bit type is changed from wr to rw. id2 mstid_1 master id control bit type is changed from wr to rw. id2 mstid_2 master id control bit type is changed from wr to rw. id2 mstid_3 master id control bit type is changed from wr to rw. id2 mstid_4 master id control bit type is changed from wr to rw. id2 mstid_5 master id control bit type is changed from wr to rw. id2 mstid_6 master id control bit type is changed from wr to rw. id2 mstid_7 master id control bit type is changed from wr to rw. id3 mstid_0 master id control bit type is changed from wr to rw. id3 mstid_1 master id control bit type is changed from wr to rw. id3 mstid_2 master id control bit type is changed from wr to rw. id3 mstid_3 master id control bit type is changed from wr to rw. id3 mstid_4 master id control bit type is changed from wr to rw. id3 mstid_5 master id control bit type is changed from wr to rw. id3 mstid_6 master id control bit type is changed from wr to rw. id3 mstid_7 master id control bit type is changed from wr to rw. clk_gate_bypass bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. Port 0 read channel address miss int enable 1: Enable 0: Disable bit type is changed from wr to rw. Port 0 write channel address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read channel address miss int write-clear bit type is changed from wc to rc. Port 0 write channel address miss int write-clear Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal control uart1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pwr_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_lps_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_wdt_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ifc1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pwr_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control nb_lps_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_wdt_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ifc1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access bit type is changed from wr to rw. id0 mstid_0 master id control bit type is changed from wr to rw. id0 mstid_1 master id control bit type is changed from wr to rw. id0 mstid_2 master id control bit type is changed from wr to rw. id0 mstid_3 master id control bit type is changed from wr to rw. id0 mstid_4 master id control bit type is changed from wr to rw. id0 mstid_5 master id control bit type is changed from wr to rw. id0 mstid_6 master id control bit type is changed from wr to rw. id0 mstid_7 master id control bit type is changed from wr to rw. id1 mstid_0 master id control bit type is changed from wr to rw. id1 mstid_1 master id control bit type is changed from wr to rw. id1 mstid_2 master id control bit type is changed from wr to rw. id1 mstid_3 master id control bit type is changed from wr to rw. id1 mstid_4 master id control bit type is changed from wr to rw. id1 mstid_5 master id control bit type is changed from wr to rw. id1 mstid_6 master id control bit type is changed from wr to rw. id1 mstid_7 master id control bit type is changed from wr to rw. id2 mstid_0 master id control bit type is changed from wr to rw. id2 mstid_1 master id control bit type is changed from wr to rw. id2 mstid_2 master id control bit type is changed from wr to rw. id2 mstid_3 master id control bit type is changed from wr to rw. id2 mstid_4 master id control bit type is changed from wr to rw. id2 mstid_5 master id control bit type is changed from wr to rw. id2 mstid_6 master id control bit type is changed from wr to rw. id2 mstid_7 master id control bit type is changed from wr to rw. id3 mstid_0 master id control bit type is changed from wr to rw. id3 mstid_1 master id control bit type is changed from wr to rw. id3 mstid_2 master id control bit type is changed from wr to rw. id3 mstid_3 master id control bit type is changed from wr to rw. id3 mstid_4 master id control bit type is changed from wr to rw. id3 mstid_5 master id control bit type is changed from wr to rw. id3 mstid_6 master id control bit type is changed from wr to rw. id3 mstid_7 master id control bit type is changed from wr to rw. clk_gate_bypass port0 default address, bit 0 ~ 27. bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. Port 0 read channel address miss int enable 1: Enable 0: Disable bit type is changed from wr to rw. Port 0 write channel address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read channel address miss int write-clear bit type is changed from wc to rc. Port 0 write channel address miss int write-clear Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal control i2c2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_dma_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rom_patch_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control psram_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control med_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_sec_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_pub_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control efuse_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi_flash_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spiflash_ext_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_if_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control keypad_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control seg_lcd_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_dma_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rom_patch_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control psram_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control med_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_sec_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_pub_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control efuse_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi_flash_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spiflash_ext_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_if_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control keypad_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control seg_lcd_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access bit type is changed from wr to rw. id0 mstid_0 master id control bit type is changed from wr to rw. id0 mstid_1 master id control bit type is changed from wr to rw. id0 mstid_2 master id control bit type is changed from wr to rw. id0 mstid_3 master id control bit type is changed from wr to rw. id0 mstid_4 master id control bit type is changed from wr to rw. id0 mstid_5 master id control bit type is changed from wr to rw. id0 mstid_6 master id control bit type is changed from wr to rw. id0 mstid_7 master id control bit type is changed from wr to rw. id1 mstid_0 master id control bit type is changed from wr to rw. id1 mstid_1 master id control bit type is changed from wr to rw. id1 mstid_2 master id control bit type is changed from wr to rw. id1 mstid_3 master id control bit type is changed from wr to rw. id1 mstid_4 master id control bit type is changed from wr to rw. id1 mstid_5 master id control bit type is changed from wr to rw. id1 mstid_6 master id control bit type is changed from wr to rw. id1 mstid_7 master id control bit type is changed from wr to rw. id2 mstid_0 master id control bit type is changed from wr to rw. id2 mstid_1 master id control bit type is changed from wr to rw. id2 mstid_2 master id control bit type is changed from wr to rw. id2 mstid_3 master id control bit type is changed from wr to rw. id2 mstid_4 master id control bit type is changed from wr to rw. id2 mstid_5 master id control bit type is changed from wr to rw. id2 mstid_6 master id control bit type is changed from wr to rw. id2 mstid_7 master id control bit type is changed from wr to rw. id3 mstid_0 master id control bit type is changed from wr to rw. id3 mstid_1 master id control bit type is changed from wr to rw. id3 mstid_2 master id control bit type is changed from wr to rw. id3 mstid_3 master id control bit type is changed from wr to rw. id3 mstid_4 master id control bit type is changed from wr to rw. id3 mstid_5 master id control bit type is changed from wr to rw. id3 mstid_6 master id control bit type is changed from wr to rw. id3 mstid_7 master id control bit type is changed from wr to rw. id4 mstid_0 master id control bit type is changed from wr to rw. id4 mstid_1 master id control bit type is changed from wr to rw. id4 mstid_2 master id control bit type is changed from wr to rw. id4 mstid_3 master id control bit type is changed from wr to rw. id4 mstid_4 master id control bit type is changed from wr to rw. id4 mstid_5 master id control bit type is changed from wr to rw. id4 mstid_6 master id control bit type is changed from wr to rw. id4 mstid_7 master id control bit type is changed from wr to rw. id5 mstid_0 master id control bit type is changed from wr to rw. id5 mstid_1 master id control bit type is changed from wr to rw. id5 mstid_2 master id control bit type is changed from wr to rw. id5 mstid_3 master id control bit type is changed from wr to rw. id5 mstid_4 master id control bit type is changed from wr to rw. id5 mstid_5 master id control bit type is changed from wr to rw. id5 mstid_6 master id control bit type is changed from wr to rw. id5 mstid_7 master id control bit type is changed from wr to rw. clk_gate_bypass bit type is changed from wr to rw. 0: don't response error; 1: response error bit type is changed from wr to rw. Port 0 read channel address miss int enable 1: Enable 0: Disable bit type is changed from wr to rw. Port 0 write channel address miss int enable 1: Enable 0: Disable bit type is changed from wc to rc. Port 0 read channel address miss int write-clear bit type is changed from wc to rc. Port 0 write channel address miss int write-clear Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal control sci2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control debug_uart_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart4_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart5_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sdmmc2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2s_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ifc2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control debug_host_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sci2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control debug_uart_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart4_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart5_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sdmmc2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2s_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ifc2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control debug_host_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access bit type is changed from wr to rw. id0 mstid_0 master id control bit type is changed from wr to rw. id0 mstid_1 master id control bit type is changed from wr to rw. id0 mstid_2 master id control bit type is changed from wr to rw. id0 mstid_3 master id control bit type is changed from wr to rw. id0 mstid_4 master id control bit type is changed from wr to rw. id0 mstid_5 master id control bit type is changed from wr to rw. id0 mstid_6 master id control bit type is changed from wr to rw. id0 mstid_7 master id control bit type is changed from wr to rw. id1 mstid_0 master id control bit type is changed from wr to rw. id1 mstid_1 master id control bit type is changed from wr to rw. id1 mstid_2 master id control bit type is changed from wr to rw. id1 mstid_3 master id control bit type is changed from wr to rw. id1 mstid_4 master id control bit type is changed from wr to rw. id1 mstid_5 master id control bit type is changed from wr to rw. id1 mstid_6 master id control bit type is changed from wr to rw. id1 mstid_7 master id control bit type is changed from wr to rw. id2 mstid_0 master id control bit type is changed from wr to rw. id2 mstid_1 master id control bit type is changed from wr to rw. id2 mstid_2 master id control bit type is changed from wr to rw. id2 mstid_3 master id control bit type is changed from wr to rw. id2 mstid_4 master id control bit type is changed from wr to rw. id2 mstid_5 master id control bit type is changed from wr to rw. id2 mstid_6 master id control bit type is changed from wr to rw. id2 mstid_7 master id control bit type is changed from wr to rw. id3 mstid_0 master id control bit type is changed from wr to rw. id3 mstid_1 master id control bit type is changed from wr to rw. id3 mstid_2 master id control bit type is changed from wr to rw. id3 mstid_3 master id control bit type is changed from wr to rw. id3 mstid_4 master id control bit type is changed from wr to rw. id3 mstid_5 master id control bit type is changed from wr to rw. id3 mstid_6 master id control bit type is changed from wr to rw. id3 mstid_7 master id control bit type is changed from wr to rw. clk_gate_bypass spi flash command to send. spi flash address to send. spi flash modebit,set 0xA0 to enable continuous read. spi flash spi read/write block size. spi flash data to send. spi send byte, 1: quad send 0: spi send. spi flash busy. tx fifo empty. tx fifo full. rx fifo empty. rx fifo data count. spi flash read back data. spi flash read mode from AHB. spi flash wprotect pin. spi flash hold pin. device is winbond or xm chip. spi flash read sample delay cycles. spi flash clock divider. spi flash send command using quad lines. rx fifo_clr,self clear. tx fifo_clr,self clear. spi flash cs num. single chip spi flash size. spi flash is 128m flash. quad read command. fast read command. read command. protect_byte, must be 0x55 when program this register. disable read from ahb. Enable the module and activate the chip select selected by CS_sel field. Selects the active CS. When set to 1 the inputs are activated, else only the output is driven and no data are stored in the receive FIFO. Notes: The Input_mode bit status is also readable onto the bit rxtx_buffer[31]. The spi clock polarity when '0' the clock disabled level is low, and the first edge is a rising edge. When '1' the clock disabled level is high, and the first edge is a falling edge. Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first clock edge. Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first data out Transfer start to first data in sample delay value from 0 to 3 is the number of spi clock half period between the CS activation and the first data in sampled. NOTE: DI_Delay must be less or equal to DO_Delay + CS_Delay + 2. In other words DI_Delay can be 3 only if DO_Delay and CS_Delay are not both equal to 0. Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer and CS deactivation Chip select deactivation to reactivation minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new CS activation (CS will activate only if more data are available in the transmit FIFO) Frame Size The frame size is the binary value of this register + 1 valid value are 3 to 63 (frame size 4 to 64bits) OE delay When 0: regular mode, SPI_DO pin as output only. Value from 1 to 63 is the number of data out to transfert before the SPI_DO pin switch to input. Selects the active CS and Input_reg either from the ctrl or rxtx_buffer register. If SPI FIFO 8b or 32b, when set to "0": CS from CS_sel and INPUT from Input_mode in the register ctrl. Only if SPI FIFO 32b, when set to "1": CS and INPUT from SPI DATA.(Do not work for FIFO8b) Selects the input line to be used as SPI data in.(Not used for SPI3) when "00" the SPI_DI_0 is used. When "01" the SPI_DI_1 is used. When "10" the SPI_DI_2 is used. When "11" reserved. '1' when a transfer is in progress. The receive FIFO overflow irq cause. Writing a '1' clear the receive overflow status and cause. The transmit FIFO threshold irq cause. The transmit Dma Done irq cause. Writing a '1' clear the transmit Dma Done status and cause. The receive FIFO threshold irq cause. The receive Dma Done irq cause. Writing a '1' clear the receive Dma Done status and cause. The transmit FIFO overflow status. Writing a '1' clear the transmit overflow status and cause. The receive FIFO underflow status. Writing a '1' clear the receive underflow status and cause. The receive FIFO overflow status. Writing a '1' clear the receive overflow status and cause. The transmit FIFO threshold status. The transmit Dma Done status. Writing a '1' clear the transmit Dma Done status and cause. The receive FIFO threshold status. The receive Dma Done status. Writing a '1' clear the receive Dma Done status and cause. Transmit FIFO Space Number of empty spot in the FIFO Receive FIFO level Number of DATA in the FIFO Writing '1' flush both FIFO, don't do it when SPI is active (transfer in progress) Spi1 fifo size (rxtx_buffer): 8bits. Spi2 fifo size (rxtx_buffer): 8bits. Spi3 fifo size (rxtx_buffer): 32bits. Write to the transmit FIFO Read in the receive FIFO. Chip Select on which write the data written in the Fifo. Data in bit [30:29] Data out bit [30:29] Set this bit to one when the data received while sending this peculiar data are expected to be kept in the FIFO, otherwise no data is recorded in the FIFO. Data in bit [31] Data out bit [31] Chip select polarity Clock Divider The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2 When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz. for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. MMC Pattern value for RX pattern match mode. Enable the pattern mode. Select the RX pattern matching mode when the pattern_mode is enabled( set 1). Used for SD/MMC SPI mode. When TX stream mode is enabled, once the TX fifo is empty, all new bits send have the value of this bit. Enable the TX stream mode. Used for SD/MMC SPI mode. When enabled, this mode provide infinite bit stream for sending, after fifo is empty the extra bits generated all have the same value. The value is in tx_stream_bit. Allow to automatically clear the tx_stream_mode when Rx_Dma_Done is set. Mask the receive FIFO overflow irq Mask the transmit FIFO threshold irq Mask the transmit Dma Done irq Mask the receive FIFO threshold irq Mask the receive DMA Done irq Transmit FIFO threshold this threshold is used to generate the irq. Receive FIFO threshold this threshold is used to generate the irq. This field indicates which standard channel to use. Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel. Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. When non-secure cpu read this register, the return value will automatic exlude the secure channel. 00000 = use Channel0 00001 = use Channel1 00010 = use Channel2 ... 01111 = use Channel15 11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example: 0000_0000 = All channels disabled 0000_0001 = Ch0 enabled 0000_0010 = Ch1 enabled 0000_0100 = Ch2 enabled 0000_0101 = Ch0 and Ch2 enabled 0000_0111 = Ch0, Ch1 and Ch2 enabled all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status . 0= The debug channel is running (not idle) 1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example: 0000_0000 = All channels registers can be accessed by secure master or non-secure master. 0000_0001 = Ch0 registers can only be accessed by secure master. 0000_0010 = Ch1 registers can only be accessed by secure master. 0000_0100 = Ch2 registers can only be accessed by secure master. 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. ...... all 1 = all channels registers can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example: 0000_0000 = All channels dma are non-secure master. 0000_0001 = Ch0 dma is secure master. 0000_0010 = Ch1 dma is secure master. 0000_0100 = Ch2 dma is secure master. 0000_0101 = Ch0 and Ch2 dma are secure master. 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. ...... all 1 = all channels dma are secure master. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB Exchange the write data to fifo halfword MSB or LSB Set Auto-disable mode 0 = when TC reach zero the channel is not automatically released. 1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size 0= 8-bit peripheral 1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel. This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved. The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. . Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer. For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. This field indicates which standard channel to use. Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel. Secure cpu can use all channels, but non-secure cpu only can use non-secure channel. Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec. When non-secure cpu read this register, the return value will automatic exlude the secure channel. 00000 = use Channel0 00001 = use Channel1 00010 = use Channel2 ... 01111 = use Channel15 11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example: 0000_0000 = All channels disabled 0000_0001 = Ch0 enabled 0000_0010 = Ch1 enabled 0000_0100 = Ch2 enabled 0000_0101 = Ch0 and Ch2 enabled 0000_0111 = Ch0, Ch1 and Ch2 enabled all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status . 0= The debug channel is running (not idle) 1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example: 0000_0000 = All channels registers can be accessed by secure master or non-secure master. 0000_0001 = Ch0 registers can only be accessed by secure master. 0000_0010 = Ch1 registers can only be accessed by secure master. 0000_0100 = Ch2 registers can only be accessed by secure master. 0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master. 0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master. ...... all 1 = all channels registers can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example: 0000_0000 = All channels dma are non-secure master. 0000_0001 = Ch0 dma is secure master. 0000_0010 = Ch1 dma is secure master. 0000_0100 = Ch2 dma is secure master. 0000_0101 = Ch0 and Ch2 dma are secure master. 0000_0111 = Ch0, Ch1 and Ch2 dma are secure master. ...... all 1 = all channels dma are secure master. This register indicates dbghost channel dma is secure master. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB Exchange the write data to fifo halfword MSB or LSB Set Auto-disable mode 0 = when TC reach zero the channel is not automatically released. 1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size 0= 8-bit peripheral 1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel. This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved. The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4. . Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer. For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. System Rom Space This rom is used for XCPU boot code. System Rom Space This rom is used for XCPU boot code. System Ram Space System Ram Space Nb Ram Space PSRAM Space In-package PSRAM FLASH Space In-package FLASH Internal TCO mapping Clear TCO 0 : set the TCO 0 to the inactive state To clear TCO n, use event 2*n Set TCO 0 : set the TCO 0 to the active state To set TCO n, use event 2*n+1 ... stop modulation starts modulation and output on IQ DAC disable IQ ADC enable IQ ADC stop recording IQ samples start recording IQ samples Clear RF_PDN Set RF_PDN Send RF spi command Start Ramp 0 Start Ramp 1 Start Ramp 2 Start Ramp 3 Start Ramp 4 End of the WakeUp Mode Start of Rf_spi Transfer End of Rf_spi Transfer Trigger BCPU TCU irq 0 Trigger BCPU TCU irq 1 Trigger XCPU TCU irq 0 Trigger XCPU TCU irq 1 Trigger XCPU TCU irq 2 Trigger XCPU TCU irq 3 Trigger XCPU TCU irq 4 Trigger XCPU TCU irq 5 Trigger XCPU TCU irq 6 Trigger XCPU TCU irq 7 Trigger XCPU TCU irq 8 Trigger XCPU TCU irq 9 Trigger XCPU TCU irq 10 Trigger XCPU TCU irq 11 Trigger XCPU TCU irq 12 Trigger XCPU TCU irq 13 Trigger XCPU TCU irq 14 Trigger XCPU TCU irq 15 Value loaded into the TCU counter when the Load bit is set to 1 Subframe alue loaded into the TCU counter when the Load bit is set to 1 Writing a 1 to this bit will load the TCU with the TCU loadval value Writing a 0 has no effect Writing a 1 to enable run tcu wakeup function in lowpower skip frame Writing a 0 to disable TCU counter wrap value. The TCU counter returns to 0 when this value is reached TCU subframe counter wrap value. The TCU subframe counter returns to 0 when this value is reached TCU counter current value TCU counter current sf value Writing 1 transfer the programmed events to the active area. Writing 1 to this bit with one of the ForceLatch bit will force the corresponding Active Area to receive no events (i.e. clear it) instead of transfering the programmed area. writing 1 to clear the corresponding programmed area. Writing 1 clears the Program Area Configure the TCO polarity Error Status: become 1 when writing to Program Area while the TCU is coping the Program Area to the Active Area. In this case the write is ignored. Write 1 to clear it. This bit allows to access directly the active area for debug purposes Writing 1 disable the events that affect corresponding TCO. Reading return the actual enable state. Writing 1 disable the events that affect corresponding TCO. Reading return the actual enable state. Writing 1 disable the events SEND_SPI_CMD. Reading return the actual enable state. Writing 1 disable the events NEXT_GAIN. Reading return the actual enable state. Writing 1 disable the events FIRST_GAIN. Reading return the actual enable state. Writing 1 disable the events NEXT_FC. Reading return the actual enable state. Writing 1 disable the corresponding Ramp event. Reading return the actual enable state. Writing 1 disable the events RX_SOC. Reading return the actual enable state. Writing 1 disable the events DIGRF_STB. Reading return the actual enable state. Writing 1 disable the events RFSPI_START. Reading return the actual enable state. Writing 1 disable the events RFSPI_END. Reading return the actual enable state. Writing 1 disable the marked rf spi commands (cf RF SPI). Reading return the actual enable state. Writing 1 disable the corresponding BCPU TCU irq event. Reading return the actual enable state. Writing 1 disable the corresponding XCPU TCU irq event. Reading return the actual enable state. Writing 1 enable the events that affect corresponding TCO. Reading return the actual enable state. Writing 1 enable the events that affect corresponding TCO. Reading return the actual enable state. Writing 1 enable the events SEND_SPI_CMD. Reading return the actual enable state. Writing 1 enable the events NEXT_GAIN. Reading return the actual enable state. Writing 1 enable the events FIRST_GAIN. Reading return the actual enable state. Writing 1 enable the events NEXT_FC. Reading return the actual enable state. Writing 1 enable the corresponding Ramp event. Reading return the actual enable state. Writing 1 enable the events RX_SOC. Reading return the actual enable state. Writing 1 enable the events DIGRF_STB. Reading return the actual enable state. Writing 1 enable the events RFSPI_START. Reading return the actual enable state. Writing 1 enable the events RFSPI_END. Reading return the actual enable state. Writing 1 enable the marked rf spi commands (cf RF SPI). Reading return the actual enable state. Writing 1 enable the corresponding BCPU TCU irq event. Reading return the actual enable state. Writing 1 enable the corresponding XCPU TCU irq event. Reading return the actual enable state. Writing 1 set corresponding TCO to the active state (The actual line state also depends on TCO_Polarity). Reading returns the actual state of all TCOs. Writing 1 set corresponding TCO to the inactive state (The actual line state also depends on TCO_Polarity). Reading returns the actual state of all TCOs. qbit divider, qbit freq is clk_tcu divided by (Qbit_Div + 1). Enable Clk_TCU same with Clk_Sys. Enable the 208kHz pulse generation for DAI Simple. (!) When enabling the clock field Enable_Qbit should also be enabled. Enable the Quarter bit generation (required for normal TCU operation) 1 when the IRQ was triggered because the tcu counter synchronization is done. Write 1 in cause or status bit to clear. 1 when the tcu counter synchronization is done. Write 1 in cause or status bit to clear. when 1 the LPS_IRQ_TCU_Sync_Done is enabled. enable sync tcu counter to global counter function. tcu counter load value when synchronized. tcu counter load subframe value when synchronized. TCU counter value when rfspi conflict happen Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. Number of snapshot. enable subframe mask bits auto clear. write 1 to clear the corresponding subframe mask bit. write 1 to set the corresponding subframe mask bit. subframe mask value. The event Id will be executed when the TCU counter reaches the value programmed in Event time field of this register. Event to be executed when the TCU counter reaches the programmed event time. Value loaded to OS timer. Write '1' to this bit will enable OS timer. When read, the value is what we have written to this bit, it changes immediately after been written. Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock. '1' indicates OS timer enabled. '0' indicates OS timer not enabled. Read this bit will get the information if OS timer interruption clear operation is finished or not. '1' indicates OS timer interruption clear operation is on going. '0' indicates no OS timer interruption clear operation is on going. Write '1' to this bit will set OS timer to repeat mode. When read, get the information if OS timer is in repeat mode. '1' indicates OS timer in repeat mode. '0' indicates OS timer not in repeat mode. Write '1' to this bit will set OS timer to wrap mode. When read, get the information if OS timer is in wrap mode. '1' indicates OS timer in wrap mode. '0' indicates OS timer not in wrap mode. Write '1' to this bit will load the initial value to OS timer. Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. This bit enables interval IRQ mode. '0': hw delay timer does not generate interval IRQ. '1': hw delay timer generate an IRQ each interval. interval of generating an HwTimer IRQ. "00": interval of 1/8 second. "01": interval of 1/4 second. "10": interval of 1/2 second. "11": interval of 1 second. Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF_FFFFFFFF. Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF_FFFFFFFF. Set mask for OS timer IRQ. Set mask for hardwre delay timer wrap IRQ. Set mask for hardwre delay timer interval IRQ. Clear mask for OS timer IRQ. Clear mask for hardwre delay timer wrap IRQ. Clear mask for hardwre delay timer interval IRQ. Clear OS timer IRQ. Clear hardware delay timer wrap IRQ. Clear hardware delay timer interval IRQ. OS timer IRQ cause. hardware delay timer wrap IRQ cause. hardware delay timer interval IRQ cause. OS timer IRQ status. hardware delay timer wrap IRQ status. hardware delay timer interval IRQ status. Allows to turn off the UART: 0 = Disable 1 = Enable Number of data bits per character (least significant bit first), if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0). 0 = one stop bit is transmitted in the serial data. 1 = two stop bits are generated and transmitted in the serial data out. Parity is enabled when this bit is set. Controls the parity format when parity is enabled: 00 = an odd number of received 1 bits is checked, or transmitted (the parity bit is included). 01 = an even number of received 1 bits is checked or transmitted (the parity bit is included). 10 = a space is generated and received as parity bit. 11 = a mark is generated and received as parity bit. Controls whether enable or disable soft flow ctrl function. 0 = disable flow ctrl function 1 = enable flow ctrl function Controls whether enable or disable auto baud rate function. 0 = disable auto baud rate function 1 = enable auto baud rate function Number of data bits per character (least significant bit first), if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16. 0 = (BCLK = SCLK / 16) 1 = (BCLK = SCLK / 4) 2 = (BCLK = SCLK / 3) When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details). Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept. Length of a break, in number of bits. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. Those bits indicate the number of space available in the Tx Fifo. at_match flag '0' = AT is detected successfully. '1' = at is detected successfully. When auto_enable is 0,this bit is cleared to 0. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. This bit indicates that the UART is receiving a byte. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. character miscompare flag '0' = AT or at compare failed. '1' = AT or at compare successfully. When auto_enable is 0,this bit is cleared to 0. auto baud locked flag '0' = baud rate is detected failed. '1' = baud rate is detected successfully. When auto_enable is 0,this bit is cleared to 0. This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value. current value of the Uart_CTS line. '1' = Tx not allowed. '0' = Tx allowed. Auto mode ratio flag. Mask tx enable flag. Current value of the DTR line. This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early. The UART_RECEIVE_BUFFER register is a read-only register that contains the data byte received on the serial input port. This register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Clear to send signal change detected. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Pulse detected on Uart_Dma_Tx_Done_H signal. Pulse detected on Uart_Dma_Rx_Done_H signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Rising edge detected on the UART_DTR signal. Falling edge detected on the UART_DTR signal. Auto function fail. When rx transfer num equals to transfer threshold, there is a interrupt flag. When tx transfer num equals to transfer threshold, there is a interrupt flag. This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. This interrupt is generated when sw flow ctrl is enabled and rx char is xon. This interrupt is generated when start bit is detected. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Reset control: Write one in this register. This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register. This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register. This interrupt is generated when auto function fail. Reset control: Write 0 in auto_enable. This interrupt is generated when rx transfer num is not less than transfer threshold. Reset control: Write 1 in this register. This interrupt is generated when tx transfer num is not less than transfer threshold. Reset control: Write 1 in this register. This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. Reset control: Write 1 in this register. This interrupt is generated when sw flow ctrl is enabled and rx char is xon. Reset control: Write 1 in this register. This interrupt is generated when start is detected. Reset control: Write 1 in this register. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Defines the empty threshold level at which the Data Available Interrupt will be generated. The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Defines the empty threshold level at which the Data Needed Interrupt will be generated. The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC). The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. Ring indicator. When write '1', set RI bit. When read, get RI bit value. Data carrier detect. When write '1', set DCD bit. When read, get DCD bit value. Data set ready. When write '1', set RI bit. When read, get RI bit value. Sends a break signal by holding the Uart_Tx line low until this bit is cleared. When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Controls the Uart_RTS output. 0 = the Uart_RTS will be inactive high (Rx not allowed). 1 = the Uart_RTS will be active low (Rx allowed). Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared. Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared. Ring indicator. When write '1', clear RI bit. When read, get RI bit value. Data carrier detect. When write '1', clear DCD bit. When read, get DCD bit value. Data set ready. When write '1', clear RI bit. When read, get RI bit value. Sends a break signal by holding the Uart_Tx line low until this bit is cleared. When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Controls the Uart_RTS output. 0 = the Uart_RTS will be inactive high. 1 = the Uart_RTS will be active low. Auto mode ratio. XON character value. XOFF character value. Count Value for 1st TimeOut Count Value for 2nd TimeOut Watchdog response mode.
0 = Generate a system reset.
1 = First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset. Reset pulse length in number of wdt clock cycles. The range of values available is 1 to 8 clk cycles.
3'b000 - 1 clk cycle
3'b001 - 2 clk cycles
3'b010 - 3 clk cycles
...
3'b111 - 8 clk cycles This register is used to restart/stop the WDT counter. As a safety feature to prevent accidental restarts/stops, write 8'h76 to restart and 8'h34 to stop.
When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. A pulse to clear interrupt.
When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. This register shows the word status of the WDT.
0 = The watchdog counter is idle/stopped.
1 = The watchdog counter runs. This register shows the interrupt status of the WDT.
0 = Interrupt is inactive.
1 = Interrupt asserts. ROM base FOR ARM SYS RAM base FOR ARM NB RAM base FOR ARM FLASH base FOR ARM PSRAM8 base FOR ARM System APB1 base FOR ARM System APB2 base FOR ARM Baseband APB base FOR ARM MED base FOR ARM