AON_SOFT_RST_CTRL0 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release CLKEN_LTE LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on LTE module function clock software register control bit 0:off 1:on CLKEN_LTE_INTF LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on LTE module interface clock software register control bit 0:off 1:on RSTCTRL_LTE LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE module reset software register control bit 0:no reset 1:reset LTE_AUTOGATE_MODE 0: LTE module clock auto gating individual 1: LTE modules invide into two parties : "uplink" and "downlink", and auto gating individual LTE_AUTOGATE_EN 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable LTE_AUTOGATE_DELAY_NUM When LTE autogating function enable, After module "running" signal was pull down, a counter begin to count from zero.LTE modules clock will be gated when the counter counts to this number value. AON_LPC_CTRL waiting time of bus entered low power mode,calculated by bus clock waiting time of bus entered normal power mode,calculated by bus clock 0: disable 1: enable 0: disable 1: enable AON_CLOCK_EN0 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable AON_CLOCK_EN1 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable AON_CLOCK_AUTO_SEL0 AON_CLOCK_AUTO_SEL1 AON_CLOCK_AUTO_SEL2 AON_CLOCK_AUTO_SEL3 AON_CLOCK_FORCE_EN0 AON_CLOCK_FORCE_EN1 AON_CLOCK_FORCE_EN2 AON_CLOCK_FORCE_EN3 AON_SOFT_RST_CTRL1 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release 1:reset 0:reset release MIPI_CSI_CFG_REG CFG_CLK_UART2 CFG_CLK_UART3 CFG_CLK_DEBUG_HOST RC_CALIB_CTRL write 1 to clear interrupt. Read data always be "0". 0:disable interrupt 1:enable interrupt 0:disable 1:enable write 1 to enable RC caliberation, clear to 0 automatically when caliberation done. RC_CALIB_TH_VAL RC_CALIB_OUT_VAL EMMC_SLICE_PHY_CTRL 1:enable 0:disable 1:sel lte dbgio 0:sel emmc DMA_REQ_CTRL 1:sel cp axidma 0:sel ap axidma 1:sel cp axidma 0:sel ap axidma APT_TRIGGER_SEL 1:sel lte_up_rfctrl[3] 0:sel rf_gpio[9] AHB2AHB_AB_FUNCDMA_CTRL AHB2AHB_AB_FUNCDMA_STS AHB2AHB_AB_DAP_CTRL AHB2AHB_AB_DAP_STS AHB2AXI_PUB_CTRL AHB2AXI_PUB_STS AXI2AXI_PUB_STS_0 AXI2AXI_PUB_STS_1 AHB2AHB_AB_AON2LPS_CTRL AHB2AHB_AB_AON2LPS_STS AHB2AHB_AB_LPS2AON_CTRL AHB2AHB_AB_LPS2AON_STS SYSCTRL_REG0 1: enable rf_dig clock 0: disable rf_dig clock 1: output to PMIC 26M clock enable 0: output to PMIC 26M clock disable 1: IIS_PLL reference clock enable 0: IIS_PLL reference clock disable 1: MPLL reference clock enable 0: MPLL reference clock disable 1: APLL reference clock enable 0: APLL reference clock disable 1: aud_sclk clock output invert(source from clk_audio) 0: aud_sclk clock output do not invert(source from clk_audio) usb20 utmi_width_sel value usb20 con testmode value usb20 iddig value 1: sel usbphy signal to controller; 0: sel sysctrl register signal(usb20_vbus_valid_sw) to controller. 1:valid 0:not valid 1: USB exit suspend mode after xtal 26m stable 0: USB exit suspend mode not rely on the status of xtal 26m 0: sel ptest_func_clk to instead pll output clock in ptest mode 1: use pll output clock in ptest mode 1:nandflash 0:norflash PLLS_STS CFG_AON_ANTI_HANG 1: sel software force register bit 0: sel hardware signal 1: disable downstream path of aon to rf 0: no disable downstream path of aon to rf 1: sel software force register bit 0: sel hardware signal 1: disable downstream path of aon to cp 0: no disable downstream path of aon to cp 1: sel software force register bit 0: sel hardware signal 1: disable downstream path of aon to ap 0: no disable downstream path of aon to ap 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: sel software force register bit 0: sel hardware signal 1: disable downstream path of aon to psram 0: no disable downstream path of aon to psram 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: enable error response 0: always response OK CFG_AON_QOS R-channel QOS value of AON W-channel QOS value of AON AON_AHB_MTX_SLICE_AUTOGATE_EN “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. “1”: clock auto gating enable. “0”: clock auto gating disable. DAP_DJTAG_EN_CFG “1”: enable dap djtag. “0”: dap djtag enable by dap jtag chain. LTE_AHB2AHB_SYNC_CFG “1”: enable cpu2phy通路ahb2ahb_sync auto clock gating. “0”: disable cpu2phy通路ahb2ahb_sync auto clock gating. “1”: enable cpu2phy通路ahb2ahb_sync write early_resp_en. “0”: disable cpu2phy通路ahb2ahb_sync write early_resp_en.. “1”: enable dma2phy通路ahb2ahb_sync auto clock gating. “0”: disable dma2phy通路ahb2ahb_sync auto clock gating. “1”: enable dma2phy通路ahb2ahb_sync write early_resp_en. “0”: disable dma2phy通路ahb2ahb_sync write early_resp_en.. CFG_AON_IO_CORE_IE_0 CFG_AON_IO_CORE_IE_1 CFG_AON_IO_CORE_IE_2 CFG_AON_IO_CORE_IE_3 SCC_TUNE_LMT_CFG VOLT_TUNE_VAL_MAX[7:5]: 3'b000 : DCDC 0.6V 3'b001 : DCDC 0.7V 3'b010 : DCDC 0.8V 3'b011 : DCDC 0.9V 3'b100 : DCDC 1.0V 3'b101 : DCDC 1.1V 3'b110 : DCDC 1.2V 3'b111 : DCDC 1.3V VOLT_TUNE_VAL_MAX[4:0] represent 0.1V/32. The result voltage = VOLT_TUNE_VAL_MAX[7:5] + VOLT_TUNE_VAL_MAX[4:0]*3mV Same to VOLT_TUNE_VAL_MAX SCC_TUNE_STATUS the voltage give to A_DIE for voltage setting: VOLT_TUNE_VAL[7:5]:change the voltage 100mv for each step; VOLT_TUNE_VAL[4:0]:change the voltage about 3mv each step the current voltage of A_DIE,observed through ADI bus: 3'b000 : DCDC 0.6V 3'b001 : DCDC 0.7V 3'b010 : DCDC 0.8V 3'b011 : DCDC 0.9V 3'b100 : DCDC 1.0V 3'b101 : DCDC 1.1V 3'b110 : DCDC 1.2V 3'b111 : DCDC 1.3V SCC_CFG Voltage Tune/Obs 0 Interface Select Voltage Tune/Obs 1 Interface Select not used in Whale stop tuning the voltage stop observating of voltage SCC_TUNE_STEP_CFG voltage set down step,fine tuning voltage set up step,fine tuning SCC_WAIT_CFG the time that SCC state_machine remain RND_INTVAL_WAIT the time that SCC state_machine remain VOLT_STB_WAIT SCC_INT_CFG mask status of interrupt caused by tune over mask status of interrupt caused by tune voltage over flow or under flow raw status of interrupt caused by tune over raw status of interrupt caused by tune voltage over flow or under flow clear the interrupt caused by SCC done interrupt clear the interrupt caused by SCC tune error interrupt software configuration to enable the interrupt of SCC software configuration to enable the error interrupt SCC_TUNE_MARK the boundary that need to tune down voltage the boundary that need to tune up voltage SCC_FSM_STS SCC Finite State Machine current state SCC_ROSC_MODE SCC IDEL CTRL SCC Voltage Tuning Bypass SCC Initialization Pattern Fail Halt Bypass SCC ROSC Report Read Control OSC through all the chain in preselected sequence OSC through a sequence in preselected chain REPEAT The RUN Operation SCC_ROSC_CFG SCC ROSC Oscillation duration SCC ROSC Ring Select SCC ROSC Sequence Select SCC ROSC Chain Select SCC_ROSC_CTRL SCC ROSC Report To Read ROSC Gross Ring Enable ROSC RUN SCC_ROSC_RPT Initialization Pattern Fail SCC ROSC REPORT VALID Selected ROSC Setting: GRE + RING number rosc SCC_ROSC_SW_RST SCC ROSC Chain Reset, Active Low DJTAG_IR_LEN the instruction register length DJTAG_DR_LEN the data register length DJTAG_IR DJTAG_DR DR_PAUSE_RECOV the signal to recover from PAUSE state DJTAG_RND_EN the signal to start DJTAG scan DJTAG_UPD_DR DJTAG_DAP_MUX_CTRL_SOFT_RST reset of dap mux control chain soft_cnt_done0_cfg apll_1000m_soft_cnt_done counter wait for source stable mempll_1000m_soft_cnt_done counter wait for source stable audio_pll_122m_soft_cnt_done counter wait for source stable xtal_26m_soft_cnt_done counter wait for source stable xtal_lp_26m_soft_cnt_done counter wait for source stable rc26m_78m_soft_cnt_done counter wait for source stable pll_wait_sel0_cfg apll_1000m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control mempll_1000m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control audio_pll_122m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control xtal_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control xtal_lp_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control rc26m_78m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control pll_wait_sw_ctl0_cfg apll_1000m_wait_force_en pll wait's enable sw control mempll_1000m_wait_force_en pll wait's enable sw control audio_pll_122m_wait_force_en pll wait's enable sw control xtal_26m_wait_force_en pll wait's enable sw control xtal_lp_26m_wait_force_en pll wait's enable sw control rc26m_78m_wait_force_en pll wait's enable sw control div_en_sel0_cfg apll_div_1000m_90m9_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_500m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_250m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_125m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_62m5_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_31m2_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_333m3_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_166m7_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_200m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control apll_div_1000m_100m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control audio_div_pll_122m_30m7_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control mempll_div_1000m_500m_auto_gate_sel pre div clock's enable select. 0: soft register control 1: hw auto control div_en_sw_ctl0_cfg apll_div_1000m_90m9_force_en pre div clock's enable sw control apll_div_1000m_500m_force_en pre div clock's enable sw control apll_div_1000m_250m_force_en pre div clock's enable sw control apll_div_1000m_125m_force_en pre div clock's enable sw control apll_div_1000m_62m5_force_en pre div clock's enable sw control apll_div_1000m_31m2_force_en pre div clock's enable sw control apll_div_1000m_333m3_force_en pre div clock's enable sw control apll_div_1000m_166m7_force_en pre div clock's enable sw control apll_div_1000m_200m_force_en pre div clock's enable sw control apll_div_1000m_100m_force_en pre div clock's enable sw control audio_div_pll_122m_30m7_force_en pre div clock's enable sw control mempll_div_1000m_500m_force_en pre div clock's enable sw control gate_en_sel0_cfg cgm_rtc_32k_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_500m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_400m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_250m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_167m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_125m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_100m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_62_5m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_31_25m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rtc_32k_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_400m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_200m_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_lp_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_400m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_333m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_250m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_200m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_167m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_125m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_100m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_62_5m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_31_25m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_audiopll_122_88m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_audiopll_30_72m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_mempll_500m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control gate_en_sel1_cfg cgm_apll_500m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_400m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_250m_pub_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_167m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_125m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_apll_62_5m_gnss_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_xtal_26m_rf_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control gate_en_sw_ctl0_cfg cgm_rtc_32k_ap_force_en clock gating enable sw control cgm_rc_26m_ap_force_en clock gating enable sw control cgm_xtal_26m_ap_force_en clock gating enable sw control cgm_apll_500m_ap_force_en clock gating enable sw control cgm_apll_400m_ap_force_en clock gating enable sw control cgm_apll_250m_ap_force_en clock gating enable sw control cgm_apll_167m_ap_force_en clock gating enable sw control cgm_apll_125m_ap_force_en clock gating enable sw control cgm_apll_100m_ap_force_en clock gating enable sw control cgm_apll_62_5m_ap_force_en clock gating enable sw control cgm_apll_31_25m_ap_force_en clock gating enable sw control cgm_rtc_32k_cp_force_en clock gating enable sw control cgm_xtal_26m_cp_force_en clock gating enable sw control cgm_apll_400m_cp_force_en clock gating enable sw control cgm_apll_200m_cp_force_en clock gating enable sw control cgm_rc_26m_aon_force_en clock gating enable sw control cgm_xtal_26m_aon_force_en clock gating enable sw control cgm_xtal_lp_26m_aon_force_en clock gating enable sw control cgm_apll_400m_aon_force_en clock gating enable sw control cgm_apll_333m_aon_force_en clock gating enable sw control cgm_apll_250m_aon_force_en clock gating enable sw control cgm_apll_200m_aon_force_en clock gating enable sw control cgm_apll_167m_aon_force_en clock gating enable sw control cgm_apll_125m_aon_force_en clock gating enable sw control cgm_apll_100m_aon_force_en clock gating enable sw control cgm_apll_62_5m_aon_force_en clock gating enable sw control cgm_apll_31_25m_aon_force_en clock gating enable sw control cgm_audiopll_122_88m_aon_force_en clock gating enable sw control cgm_audiopll_30_72m_aon_force_en clock gating enable sw control cgm_rc_26m_pub_force_en clock gating enable sw control cgm_xtal_26m_pub_force_en clock gating enable sw control cgm_mempll_500m_pub_force_en clock gating enable sw control gate_en_sw_ctl1_cfg cgm_apll_500m_pub_force_en clock gating enable sw control cgm_apll_400m_pub_force_en clock gating enable sw control cgm_apll_250m_pub_force_en clock gating enable sw control cgm_xtal_26m_gnss_force_en clock gating enable sw control cgm_apll_167m_gnss_force_en clock gating enable sw control cgm_apll_125m_gnss_force_en clock gating enable sw control cgm_apll_62_5m_gnss_force_en clock gating enable sw control cgm_xtal_26m_rf_force_en clock gating enable sw control monitor_wait_en_status0_cfg monitor_wait_en_status , 0:apll_1000m, 1:mempll_1000m, 2:audio_pll_122m, 3:xtal_26m, 4:xtal_lp_26m, 5:rc26m_78m monitor_div_auto_en_status0_cfg monitor_div_auto_en_status , 0:apll_div_1000m_90m9, 1:apll_div_1000m_500m, 2:apll_div_1000m_250m, 3:apll_div_1000m_125m, 4:apll_div_1000m_62m5, 5:apll_div_1000m_31m2, 6:apll_div_1000m_333m3, 7:apll_div_1000m_166m7, 8:apll_div_1000m_200m, 9:apll_div_1000m_100m, 10:audio_div_pll_122m_30m7, 11:mempll_div_1000m_500m monitor_gate_auto_en_status00_cfg monitor_gate_auto_en_status10_cfg monitor_gate_auto_en_status1 , 32:cgm_apll_500m_pub, 33:cgm_apll_400m_pub, 34:cgm_apll_250m_pub, 35:cgm_xtal_26m_gnss, 36:cgm_apll_167m_gnss, 37:cgm_apll_125m_gnss, 38:cgm_apll_62_5m_gnss, 39:cgm_xtal_26m_rf analog_apll_APLL_CTRL1 analog_apll_APLL_CTRL2 analog_apll_APLL_INT_Value analog_apll_APLL_CCS_CTRL analog_apll_APLL_KSTEP analog_apll_ANA_BIAS analog_apll_ANA_BIAS1 analog_apll_REG_SEL_CFG_0 analog_mpll_APLL_CTRL1 analog_mpll_APLL_CTRL2 analog_mpll_APLL_INT_Value analog_mpll_APLL_CCS_CTRL analog_mpll_APLL_KSTEP analog_mpll_ANA_BIAS analog_mpll_ANA_BIAS1 analog_mpll_REG_SEL_CFG_0 analog_iis_pll_APLL_CTRL1 analog_iis_pll_APLL_CTRL2 analog_iis_pll_APLL_INT_Value analog_iis_pll_APLL_CCS_CTRL analog_iis_pll_APLL_KSTEP analog_iis_pll_ANA_BIAS analog_iis_pll_ANA_BIAS1 analog_iis_pll_REG_SEL_CFG_0 analog_efuse4k_EFUSE_PIN_PW_CTL analog_efuse4k_REG_SEL_CFG_0 analog_efuse2k_EFUSE_PIN_PW_CTL analog_efuse2k_REG_SEL_CFG_0 analog_usb20_USB20_TEST_PIN analog_usb20_USB20_UTMI_CTL1 analog_usb20_USB20_BATTER_PLL analog_usb20_USB20_UTMI_CTL2 analog_usb20_USB20_TRIMMING analog_usb20_REG_SEL_CFG_0 analog_osc_26m_APLL_CTRL analog_osc_26m_REG_SEL_CFG_0 cgm_aon_ahb_div_cfg cgm_aon_ahb_div: clk_aon_ahb = clk_src/(div +1), default value = 2'h0 cgm_aon_ahb_sel_cfg cgm_aon_ahb_sel: clk_aon_ahb source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: apll_100m, 4: gnss_pll_133m, 5: apll_167m, 6: gnss_pll_198m, 7: apll_200m, default: 3'h1 cgm_uart2_bf_div_sel_cfg cgm_uart2_bf_div_sel: clk_uart2_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, 4: apll_31_25m, 5: apll_125m, 6: gnss_pll_133m, 7: apll_167m, default: 3'h1 cgm_uart3_bf_div_sel_cfg cgm_uart3_bf_div_sel: clk_uart3_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, 4: apll_31_25m, 5: apll_125m, 6: gnss_pll_133m, 7: apll_167m, default: 3'h1 cgm_debug_host_bf_div_sel_cfg cgm_debug_host_bf_div_sel: clk_debug_host_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, default: 2'h1 cgm_audio_div_cfg cgm_audio_div: clk_audio = clk_src/(div +1), default value = 4'h0 cgm_audio_sel_cfg cgm_audio_sel: clk_audio source , 0: xtal_26m, 1: rc26m_78m, 2: audio_pll_30_72m, 3: apll_31_25m, 4: gnss_pll_33_25m, 5: apll_62_5m, default: 3'h0 cgm_codec_mclock_div_cfg cgm_codec_mclock_div: clk_codec_mclock = clk_src/(div +1), default value = 4'h0 cgm_codec_mclock_sel_cfg cgm_codec_mclock_sel: clk_codec_mclock source , 0: xtal_26m, 1: rc26m_78m, 2: audio_pll_30_72m, 3: apll_31_25m, 4: gnss_pll_33_25m, 5: apll_62_5m, default: 3'h0 cgm_i2s_bck_bf_div_div_cfg cgm_i2s_bck_bf_div_div: clk_i2s_bck_bf_div = clk_src/(div +1), default value = 12'hf cgm_i2s_bck_bf_div_sel_cfg cgm_i2s_bck_bf_div_pad_sel: reserved, no use. cgm_i2s_bck_bf_div_sel: clk_i2s_bck_bf_div source , 0: xtal_26m, 1: rc26m_78m, 2: gnss_pll_133m, 3: audio_pll_122_88m, 4: apll_167m, default: 3'h0 cgm_out_div_cfg cgm_out_div: clk_out = clk_src/(div +1), default value = 8'h0 cgm_out_sel_cfg cgm_out_sel: clk_out source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: audio_pll_122_88m, 4: gnss_pll_133m, 5: apll_167m, default: 3'h1 cgm_efuse_sel_cfg cgm_efuse_sel: clk_efuse source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, default: 2'h1 cgm_adi_sel_cfg cgm_adi_sel: clk_adi source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_78m, default: 2'h1 cgm_dap_sel_cfg cgm_dap_sel: clk_dap source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 cgm_djtag_tck_sel_cfg cgm_djtag_tck_pad_sel: clock source from pad, high active, default: 1'h0 cgm_djtag_tck_sel: clk_djtag_tck source , 0: rtc_32k, 1: xtal_26m, default: 1'h0 cgm_swcgm_hw_sel_cfg cgm_swcgm_hw_pad_sel: clock source from pad, high active, default: 1'h0 cgm_gpt2_sel_cfg cgm_gpt2_sel: clk_gpt2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 cgm_i2c3_sel_cfg cgm_i2c3_sel: clk_i2c3 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_200m, default: 3'h1 cgm_usb_ref_sel_cfg cgm_usb_ref_sel: clk_usb_ref source , 0: rtc_32k, 1: xtal_26m, default: 1'h1 cgm_usb_ahb_div_cfg cgm_usb_ahb_div: clk_usb_ahb = clk_src/(div +1), default value = 2'h0 cgm_usb_ahb_sel_cfg cgm_usb_ahb_sel: clk_usb_ahb source , 0: rtc_32k, 1: xtal_26m, 2: apll_125m, 3: gnss_pll_133m, 4: apll_167m, 5: apll_200m, default: 3'h1 cgm_spi2_div_cfg cgm_spi2_div: clk_spi2 = clk_src/(div +1), default value = 3'h0 cgm_spi2_sel_cfg cgm_spi2_pad_sel: clock source from pad, high active, default: 1'h0 cgm_spi2_sel: clk_spi2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_78m, 3: gnss_pll_133m, 4: apll_167m, default: 3'h1 cgm_scc_sel_cfg cgm_scc_pad_sel: clock source from pad, high active, default: 1'h0 cgm_sdio_2x_div_cfg cgm_sdio_2x_div: reserved, no use. cgm_sdio_2x_sel_cfg cgm_sdio_2x_sel: clk_sdio_2x source , 0: xtal_26m, 1: rc26m_78m, 2: apll_333m, 3: gnss_pll_397m, 4: apll_400m, default: 3'h0 cgm_sdio_1x_div_cfg cgm_sdio_1x_div: clk_sdio_1x = clk_src/(div +1), default value = 1'h1 cgm_busy_src_monitor_cfg0 cgm_busy_src_monitor_cfg1 cgm_busy_src_monitor_cfg2 cgm_busy_src_monitor_cfg3 Transmit word or Receive word Write data to this address initiates a character transmission through TX FIFO Read this address retrieve data from RX fifo Clock divisor Clock divisor bit 0 to 15 Specify the clock ratio between spi_sck and clk_spi. If clk_spi runs at 48 MHz, and spi_sck runs at 12MHz, SPI_CLKD should be 1, spi_sck = clk_spi/2(n+1). If IS_FST bit is assert, the valid SPI_CLKD is 0, 1, 2 and 3. Configure register This register is used to configuration of the SPI interface Sync_polarity, positive or negative pulse for SPI or 3-wire mode ,read command polarity “1” : sync mode “1” : spi_sck reverse 1 bit chip select. “0”: cs0 is valid “1”: cs0 is invalid In default, The input data is shifted high order first into the chip; the output data is shifted out high order first from the Most Significant Bit (MSB) on SO. When this bit is set, the data will be shift out or in from the LSB Transmit data bit number. “0” : 32 bits per word “1” : 1 bits per word … “31”: 31 bits per word “1” enable TX data shift out at clock neg-edge “1” enable RX data shift in at clock neg-edge Configure register This register is used to configuration of the SPI interface “00” : default(follow before version) “01” : spi do stay 0 value when in idle “10” : spi do stay 1 value when in idle “11” : spi do stay last-bit value when in idle 1:is tx mode 0:not tx mode 1:is rx mode 0:not rx mode S8 CD or SYNC signal maps to csn number “0x0001” selects csn0 as cd signal “0x0010” selects csn1 as cd signal In SPI_HS it must be 0x0000 and disable sync and s8 mode “1” : enable S8 mode 3-wire Melody timing 1, csn high mode enable “1” : enable 3-wire mode 3-wire mode, w/r control position or the sync pulse position(the pulse will locates on top of bit N) Configure register This register is used to configuration of the SPI interface 0:DMA TX and RX REQ independent 1:DMA TX REQ are depended on RX REQ status 0: tx_dma_req keep 1 until receiving the tx_dma_ack 1: tx_dma_req is “1” when tx_empty is “1”,else “0” 0: rx_dma_req keep 1 until receiving the rx_dma_ack 1: rx_dma_req is “1” when rx_full is “1”,else “0” “0” : working on only receive mode, when rxf_realfull is high, SPI will be held until rxf_realfull is low “1” : no holding “1” enable DMA mode “0” : master “1” : slave, only support microplus mode Read data start bit, used for 3 wire mode and 3 wire 9bit RW mode. The 3 wire 9bit RW mode reuse this config registers, it indicated read data start position. RXF watermark SPI RX FIFO FULL/EMPTY watermark Receive FIFO data empty threshold. Relative with rx_fifo_empty interrupt Receive FIFO data full threshold. Relative with rx_fifo_full interrupt Configure register This register is used to configuration of the SPI interface working in only receive mode, “0” : SPI send all 0 to slave “1” : SPI send all 1 to slave working in only receive mode, “0” : SPI send all 0 to slave “1” : SPI send all 1 to slave “0” : normal mode “1” : fast mode Both for matser mode and slave mode,and in master mode SPI_SCK must be quicker than 1/8 spi_clk Phase delay. Relate to fast mode. When in normal mode, this bit is not used . Only used for slave mode “1” Mask out the first clock pulse in SPI mode Sync_half, sync width is half spi_sck cycle Number of data words ready to receive in “receive only” mode. Only used for master mode. Configure register This register is used to configuration of the SPI interface For master, transmit data interval, programmable n from 0 to 65535, delay is (n*4+3) clock cycle. For slave, max receive data interval. If the slave has not sampled the edge of spi_clk in the interval(n*4+3), slave will stop the receive process and send timout interrupt Interrupt enable SPI interrupt enable register Rx end interrupt enable Tx end interrupt enable txf_empty interrupt enable Rxf_full interrupt enable Slave mode timeout interrupt enable Rx_overrun_reg interrupt enable Tx_fifo_full interrupt enable Rx_fifo_empty interrupt enable Rx_fifo_full interrupt enable Interrupt clear SPI interrupt clear register Rx data end interrupt clear Tx data end interrupt clear Write “1” clear slave mode timeout interrupt Write “1” clear Rx_overrun_reg interrupt Write “1” clear Tx_fifo_empty interrupt Write “1” clear Tx_fifo_full interrupt Write “1” clear Rx_fifo_empty interrupt Write “1” clear Rx_fifo_full interrupt Raw status SPI interrupt raw status Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. Raw txf_empty interrupt, This bit is set when the number of tx fifo data byte is less than the tx empty watermark value. Auto cleared when the condition disappears. Raw rxf_full interrupt.This bit is set when the number of rx fifo data byte is larger than the rx full watermark value. Auto cleared when the condition disappears. Raw slave mode time out interrupt Raw Rx_overrun_reg interrupt Txf_empty_w(for debug) Raw Tx_fifo_full interrupt Raw rx_fifo_empty interrupt Rxf_full_r(for debug) Mask status SPI interrupt mask status Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. Txf_empty interrupt mask status. Rxf_full interrupt mask status. Slave mode time out interrupt mask status Rx_overrun_reg interrupt mask status Tx_fifo_full interrupt mask status Rx_fifo_empty interrupt mask status RXF address SPI RX FIFO write address and read address RX FIFO write address RX FIFO read address latch SPI status SPI status register Spi_cs(for debug) Spi_sck(for debug) Spi_txd(for debug) Spi_rxd(for debug) “1” transmit process “0” idle state TX FIFO has no data TX FIFO is real full. (not relates to TX full threshold) RX FIFO has no data RX FIFO is real full. (not relates to TX full threshold) This bit is set when the number of TX FIFO data byte is less than the TX empty interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of TX FIFO data byte is larger than the TX full interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of RX FIFO data byte is less than the RX empty interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of RX FIFO data byte is larger than the RX full interrupt watermark value. Auto cleared when the condition disappears. DSP Register This register is used for DSP control Write data switch. 2’b0: WDATA=PDATA; 2’b1: WDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; 2’b2: WDATA={PDATA[15:0],PDATA[31:16]}; 2’b3: WDATA={PDATA[23:16], PDATA[31:24], PDATA[7:0], PDATA[15:8]}; Read data switch. 2’b0: RDATA=PDATA; 2’b1: RDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; 2’b2: RDATA={PDATA[15:0],PDATA[31:16]}; This register is used for DSP control RX conunter monitor This register is used to observe the status working in only receive mode as master TXF configuration This register is used to configuration of the SPI interface TX FIFO data empty threshold. Relative with rx_fifo_empty interrupt TX FIFO data full threshold. Relative with rx_fifo_full interrupt TXF address This register is used to configuration of the SPI interface TX FIFO write address TX FIFO read address FIFO reset configuration Used to reset TX/RX FIFO “1” : reset all FIFOs. FIFO address will changed to 0 Configure register This register is used to configuration of the SPI interface 1: two data line function enable 0: two data line function disable 1: enable RGB565 data format 0: disable RGB565 data format 1: enable RGB666 data format 0: disable RGB666 data format 1: enable RGB888 data format 0: disable RGB888 data format 1: SPI slave in Low speed mode 0: SPI slave in High speed mode Used when SPI slave in High speed mode. 1: enable spi slave rtx 0: disable spi slave rtx Use for 3 wire 9bit RW mode and 4 wire 8bit RW mode (SPI_MODE=5 or SPI_MODE=6). 0: Data in and data out of SPI share one IO (SDA). 1: Data in and data out of SPI use separated IO (SDI, SDO). 1: enable ahb2apb bridge read hold when rx fifo empty 0: disable ahb2apb bridge read hold 1: enable ahb2apb bridge write hold when tx fifo full 0: disable ahb2apb bridge write hold 1: select fmark as the dma request 0: select software dma request Used for master only 0: SPI_MODE disable 1: 3 wire 9 bit, cd bit, SDI/SDO share one IO 2: 3 wire 9 bit, cd bit, SDI, SDO 3: 4 wire 8 bit, cd pin, SDI/SDO share one IO 4: 4 wire 8 bit, cd pin, SDI, SDO 5: 3 wire 9bit RW mode, 9 bit command and 8 bit read data, cd bit is enable. Design for LCD driver. 6: 4 wire 8bit RW mode, 8bit command and 8 bit read data. Use CD PAD indicates command or data. Design for LCD driver. CSN select control: 0: CSN 0 1: CSN 1 2: CSN 2 3: CSN 3 CSN IE output set(only slave) 0: not support csn input 1: support csn intput Statue Register Used to observe csn error 1: indicates csn occurring a exception csn for slave Configure Register Used for configure SPI interface Spi tx cd bit: 0: indicates command 1: indicates data Use for 4 wire 8bit RW mode. Determine CD PAD high or low in read data phase. Second data line of two data line function select bit: 0: CD PAD as second data line 1: DI PAD as second data line Two data line RGB data format mode: 0: 1pixel mode 1: 2/3 pixel mode 2-data-line switch. Only valid in 2-data-line mode(DATA_LINE2_EN set to 1): 0: use spi_do as first data line,spi_di as second data line. 1: use spi_di as first data line, spi_do as second data line. Spi tx dummy clock length Indicates tx data length from tx fifo, High 4 bits of spi tx data length Configure register This register is used to configuration of the SPI interface Indicates: spi tx data length from tx fifo, Low 16bit of tx data length Configure register SPI status register Spi rx dummy clock length Indicates receives data length from slave, high 4 bits of spi rx data length Configure register This register is used to configuration of the SPI interface Indicates: spi receives data length from slave, Low 16bit of rx data length Configure register This register is used to configuration of the SPI interface Software TX data request, for write LCD Software RX data request, for read LCD Statue Register Used to observe TX data counter Tx data cnt Statue Register Used to observe TX statue tx dummy counter tx data counter Statue Register Used to observe RX data counter Rx data cnt Statue Register Used to observe RX statue rx dummy counter rx data counter Statue Register Used to observe spi version Spi version refclk_sel Input triger number count enable slave_mode trigger select auto preload value Center-aligned mode select 00: disable , other:enable counter dir , 0: cnt ++ , 1: cnt -- one pulse mode, 0:disable 1:enable update disable, 0:disable, 1:enable clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass counter enable, 0: disbale, 1:enable slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable bit type is changed from w1c to rc. user trigger gen no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[24] 0: output enable, 1 output disable bit[25] 0: use ti4, 1: use ti3 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[17] 0: output enable, 1 output disable bit[16] 0: use ti3, 1: use ti4 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 ti4 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti4 prescale, 01:0 div2, 10: div4, others: bypass ti3 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti3 prescale, 01:0 div2, 10: div4, others: bypass ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti2 prescale, 01:0 div2, 10: div4, others: bypass ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti1 prescale, 01:0 div2, 10: div4, others: bypass ti4 polarity ti4 enable ti3 polarity ti3 enable ti2 polarity ti2 enable ti1 polarity ti1 enable cnt_value cnt prescale value cnt max value ic1 capture value ic2 capture value ic3 capture value ic4 capture value ic1 compare value ic2 compare value ic3 compare value ic4 compare value cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 bit type is changed from w1c to rc. trig gens, when counter works in slave mode bit type is changed from w1c to rc. bit type is changed from w1c to rc. Spinlock Total Status Register Spinlock Master ID Registers Spinlock Individual Status Registers Read 0x0000_0000, Request and get the lock. Read 0x0000_0001, Request but does not get the lock. Write Unlock Token, Unlock the lock. Write not Unlock Token, takes no effect. Spinlock Version ID Register cgm_ap_a5_div_cfg cgm_ap_a5_div: clk_ap_a5 = clk_src/(div +1), default value = 2'h0 cgm_ap_a5_sel_cfg cgm_ap_a5_sel: clk_ap_a5 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_400m, 5: apll_500m, default: 3'h1 cgm_ap_bus_div_cfg cgm_ap_bus_div: clk_ap_bus = clk_src/(div +1), default value = 2'h1 cgm_uart4_bf_div_sel_cfg cgm_uart4_bf_div_sel: clk_uart4_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 cgm_uart5_bf_div_sel_cfg cgm_uart5_bf_div_sel: clk_uart5_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 cgm_uart6_bf_div_sel_cfg cgm_uart6_bf_div_sel: clk_uart6_bf_div source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: apll_31_25m, 4: apll_125m, 5: gnss_pll_133m, 6: apll_167m, default: 3'h1 cgm_spiflash1_sel_cfg cgm_spiflash1_sel: clk_spiflash1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_500m, default: 3'h1 cgm_spiflash2_sel_cfg cgm_spiflash2_sel: clk_spiflash2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_397m, 4: apll_500m, default: 3'h1 cgm_camera_pix_div_cfg cgm_camera_pix_div: clk_camera_pix = clk_src/(div +1), default value = 11'h7 cgm_camera_pix_sel_cfg cgm_camera_pix_sel: clk_camera_pix source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 cgm_camera_ref_div_cfg cgm_camera_ref_div: clk_camera_ref = clk_src/(div +1), default value = 11'h7 cgm_camera_ref_sel_cfg cgm_camera_ref_sel: clk_camera_ref source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 cgm_camera_csi_div_cfg cgm_camera_csi_div: clk_camera_csi = clk_src/(div +1), default value = 11'h7 cgm_camera_csi_sel_cfg cgm_camera_csi_sel: clk_camera_csi source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_57m, 4: apll_62_5m, 5: apll_500m, default: 3'h1 cgm_camera_csi_data_hs_sel_cfg cgm_camera_csi_data_hs_pad_sel: clock source from pad, high active, default: 1'h0 cgm_spi1_sel_cfg cgm_spi1_sel: clk_spi1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_133m, 4: apll_167m, default: 3'h1 cgm_i2c1_sel_cfg cgm_i2c1_sel: clk_i2c1 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 cgm_i2c2_sel_cfg cgm_i2c2_sel: clk_i2c2 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 cgm_gpt3_sel_cfg cgm_gpt3_sel: clk_gpt3 source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, 3: gnss_pll_198_5m, 4: apll_250m, default: 3'h1 cgm_26m_sel_cfg cgm_26m_sel: clk_26m source , 0: rtc_32k, 1: xtal_26m, 2: rc26m_26m, default: 2'h1 cgm_busy_src_monitor_cfg0 cgm_busy_src_monitor_cfg1 cgm_busy_src_monitor_cfg2 cgm_busy_src_monitor2, 64:(cgm_uart5_bf_div_sel_ac == 3) & cgm_busy_uart5_bf_div 65:(cgm_uart6_bf_div_sel_ac == 3) & cgm_busy_uart6_bf_div 66:cgm_busy_ap_a5_sel_0 & cgm_busy_ap_a5_src 67:(cgm_uart4_bf_div_sel_ac == 0) & cgm_busy_uart4_bf_div 68:(cgm_uart5_bf_div_sel_ac == 0) & cgm_busy_uart5_bf_div 69:(cgm_uart6_bf_div_sel_ac == 0) & cgm_busy_uart6_bf_div 70:cgm_busy_spiflash1_sel_0 & cgm_busy_spiflash1 71:cgm_busy_spiflash2_sel_0 & cgm_busy_spiflash2 72:(cgm_camera_pix_sel_ac == 0) & cgm_busy_camera_pix 73:(cgm_camera_ref_sel_ac == 0) & cgm_busy_camera_ref 74:(cgm_camera_csi_sel_ac == 0) & cgm_busy_camera_csi 75:(cgm_spi1_sel_ac == 0) & cgm_busy_spi1 76:(cgm_i2c1_sel_ac == 0) & cgm_busy_i2c1 77:(cgm_i2c2_sel_ac == 0) & cgm_busy_i2c2 78:(cgm_gpt3_sel_ac == 0) & cgm_busy_gpt3 79:cgm_busy_32k 80:(cgm_26m_sel_ac == 0) & cgm_busy_26m CLK_AP_MODE0 Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; CLK_AP_EN0 When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; CLK_AP_MODE1 Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; CLK_AP_EN1 When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; CLK_AP_MODE2 Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; Clock Gating Mode. 0 : Clock Auto Gating ; 1 : Clock Manual Gating ; CLK_AP_EN2 When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; When Clock Manual Gating Mode. 0 : Manual Clock Disable Gating ; 1 : Manual Clock Enable Gating ; AP_RST0 Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; AP_RST1 Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; Soft Reset. Active High; 0 : in normal mode; 1 : Reset; AP_RST2 Soft Reset. Active High; 0 : in normal mode; 1 : Reset; M0_LPC M1_LPC M2_LPC M3_LPC M4_LPC M5_LPC M6_LPC M7_LPC M8_LPC M9_LPC S0_LPC S1_LPC S2_LPC S3_LPC S4_LPC S5_LPC S6_LPC MAIN_LPC CACHE_EMMC_SDIO arcache of emmc awcache of emmc MISC_CFG 1: If camera fifo is almost full, disable clk_camera_out 1: clk_camera_out enable 1: invert pix clk polarity. 0: keep pix clk polarity. ap ifc dma not operate error response from bus med read data from bus instead of flash gic400 cfgsdisable CHIP_PROD_ID production id bond id metal id CFG_QOS0 lzma_awqos lzma_arqos emmc_awqos emmc_arqos ce_awqos ce_arqos ap_a5_awqos ap_a5_arqos CFG_QOS1 aon_awqos aon_arqos ap_ifc_awqos ap_ifc_arqos usb_awqos usb_arqos gouda_awqos gouda_arqos CFG_QOS2 ap_axidma_awqos ap_axidma_arqos med_awqos med_arqos DEBUG_MONITOR med dbg bus select XHB_AWSPARSE ap2aon xhb400 awsparse spiflash2 xhb400 awsparse spiflash1 xhb400 awsparse ap_ahb xhb400 awsparse CLK_MNT26M_TH0 monitor counter number of rc26m CLK_MNT26M_TH1 monitor interval counter number of rc26m CLK_MNT26M_TH2 monitor counter number of xtal26m, low limited CLK_MNT26M_TH3 monitor counter number of xtal26m, high limited CLK_MNT32K_TH0 monitor counter number of 32k clock, low limited CLK_MNT32K_TH1 monitor counter number of 32k clock, high limited CLK_MNT_CTRL CFG_BRIDGE CGM_GATE_AUTO_SEL0 CGM_GATE_AUTO_SEL1 CGM_GATE_AUTO_SEL2 CGM_GATE_AUTO_SEL3 CGM_GATE_FORCE_EN0 CGM_GATE_FORCE_EN1 CGM_GATE_FORCE_EN2 CGM_GATE_FORCE_EN3 MNT_GATE_EN_STATUS0 MNT_GATE_EN_STATUS1 MNT_GATE_EN_STATUS2 MNT_GATE_EN_STATUS3 MNT_CGM_BUSY_STATUS0 MNT_CGM_BUSY_STATUS1 MNT_CGM_BUSY_STATUS2 MNT_CGM_BUSY_STATUS3 MNT_CGM_BUSY_STATUS4 CFG_CLK_UART4 numerator denominator CFG_CLK_UART5 numerator denominator CFG_CLK_UART6 numerator denominator CFG_CLK_SPIFLASH1 select spiflash1 controller clock frequency. default 26MHz CFG_CLK_SPIFLASH2 select spiflash2 controller clock frequency. default 26MHz CFG_CLK_APCPU_DBGEN 1: clock div disable; 0: clock div enable; 0: no div; 1: 2div; 2: 3div; 3: 4div; 4: 5div; 5: 6div; 6: 7div; 7: 8div; LP_FORCE SLEEP_CTRL 1: when ap_sys enter deepsleep, this bit can bypass ap_a5 wfi signal, only care about slp_req signal. 1: when ap_a5 enter wfi, the ap_a5 clock will auto switch to rc26MHz and the bus clock will auto change along with the ap_a5 clock. 1: when ap_a5 enter wfi, ap_a5 clk will be stopped. 1: when ap_a5 enter wfi, the ap_a5 clock will auto switch to xtal26MHz and the bus clock will auto change along with the ap_a5 clock. 1: when ap_sys enter deepsleep, this bit can prevent fiq/irq from waking up ap_a5 exit wfi. LIGHT_SLEEP_BYPASS0 LIGHT_SLEEP_BYPASS1 ANTI_HANG 1: ap a5 can receive error response from matrix; 0: error response from matrix to ap a5 will be masked; lzma/ap_imem/ap_busmon/apb_reg/gouda/tiimer1/timer2/i2c1/i2c2/gpt3/ap_clk uart4/uart5/uart6/sdmmc/camera/ap_ifc med/ce_pub/ce_sec/emmc/spi1 spiflash1/spiflash2/ap_axidma/usb AP_APB_RSD0 AP_APB_RSD1 AP_APB_RSD2 AP_APB_RSD3 AP2PUB_BRIDGE_STATUS AP2PUB_BRIDGE_DEBUG axi bus status and dma work state status axi write data channel ready axi write address channel ready axi read address channel ready dma is working,and CPU can't access ce registers except ce_clear register. dma write port state: 4'd0: idle 4'd1: write burst calculate 4'd2: write burst calculate data number 4'd3: write burst wait enough data 4'd4: write burst start 4'd5: write burst execute 4'd6: write burst wait burst end 4'd7: write burst end dma read port state: 4'd0: idle 4'd1: read burst wait enough buffer space 4'd2: read burst wait one cycle 4'd3: read burst start 4'd4: read burst execute 4'd5: read burst wait burst end 4'd6: read burst done pka cmd fifo is non-empty cmd fifo is non-empty interrupt raw status is valid ce in error status dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 3'd0: idle 3'd1: pka read instruction start 3'd2: pka load start 3'd3: pka wait done 3'd4: pka send done 3'd5: pka jump judgement dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done aes module state rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish sm4 state: 3'd0: idle 3'd1: generate key 3'd2: round start 3'd3: rounding 3'd4: xts generate key 3'd5: xts round start 3'd6: xts rounding 3'd7: done wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait tdes module state tdes module status: [3:0]: des run cycle counter [4]: des key check error generate wvalid state: 4'd0: idle 4'd1: wait enough data 4'd2: generate wvalid 4'd3: wait enough data when bursting 4'd4: wait wready for next burst data efuse access status: 5'd0: idle 5'd1: read selec between hmac and symmetric 5'd2: trng write start 5'd3: hmac session key read start 5'd4: trng write 5'd5: hmac read 5'd6: symmetric key1 read start 5'd7: symmetric key2 read start 5'd8: symmetric key1 read 5'd9: symmetric key2 read 5'd10: done 5'd11: hmac session key read 5'd12: read huk after write err 5'd13: trng write next 5'd15: iram key done 5'd16: pka non-symmetric key read start 5'd17: pka non-symmetric key read 5'd18: pka non-symmetric key write start 5'd19: pka non-symmetric key write 5'd20: pka non-symmetric key write next 5'd21: ce read non-symmetric key after write err 3'd0: idle 3'd1: pka store start 3'd2: pka wait done 3'd3: pka send done 3'd4: pka jump judgement dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 5'd20: pka store start 5'd21: pka wait done 5'd22: pka send done 5'd23: pka jump judgement [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait hash module state 0 hash module state 1 hash module status: [2:0]: hash state 3'd0: idle 3'd1: data request 3'd2: no-hmac 3'd3: hmac key 3'd4: first hmac message 3'd5: second hmac message 3'd6: digest out [8:3]: hash run cycle ce module clock enable force fde aes clock enable force pub rng autogate clock enable pub trng clock enable force chacha engine clock enable force poly engine clock enable force rng autogate clock enable force aes key expan autogate clock enable force dma axi autogate clock enable force dma ctrl autogate clock enable force apb regbank autogate clock enable simon speck clock enable pka clock enable chacha poly clock enable sm4 clock enable trng clock enable des clock enable hash clock enable fde aes clock enable aes clock enable dma_main clock enable ce interrupt enable enable pka load efuse addr is out of range int enable pka store efuse addr is out of range int enable pka load or store length is zero int enable ce pka one task done flag enable can't fime prime int enable divisor zero int enable ce use efuse error int enable ce pka one cmd done int enable ce pka store done int enable rng/trng int enable tdes key check error int enable src/dst length error int enable the efuse huk check zero int enable the efuse huk check unstable int enable one command done int ce interrupt status pka load efuse addr is out of range pka store efuse addr is out of range,when the int is valid , ap clear it ,and then need reset the ce pka load or store length is zero ce pka one task done flag can't fime prime flag divisor zero flag ce use efuse error flag ce pka one cmd done flag ce pka store done flag ce rng/trng int status ce tdes key check error int status src/dst length error int status when ce write the huk parameters, the efuse ctrl response the error, then ce will check the write huk parameters is 0 or not; if it is 0, then intrrupt when ce write the huk parameters, the efuse ctrl response the error, then ce will check the write huk parameters is 0 or not; if it is not 0 & is unstable, then intrrupt one command done int status, ce interrupt clear clear pka load efuse addr is out of range int clear pka store efuse addr is out of range int clear pka load or store length is zero int clear ce pka one task done flag clear can't fime prime int clear divisor zero int clear ce use efuse error flag clear ce pka one cmd done flag clear ce pka store done flag clear tdes key check error int status clear error int status clear the huk is zero int clear the huk is unstable int clear one command done int status, start ce start ce one fo the AES/SM4/HASH cipher module clear ce reset ce status one fo the AES/SM4/HASH cipher module aes work mode cfg 1: don’t update key, 0: update key 0: rtl rotation, 1: no-rotation 00: key 128bits,01:192bits,10,11:256bits 0000:ECB,0001:CBC,0010:CTR,0011:XTS,0100:CMAC,0101:GCM,0110:GMAC,0111:CCM,1000:CBCMAC,1001:CFB,1010:OFB aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid 0:encode,1:decode aes module enable tdes work mode cfg 0: disable, 1: enable even/odd check 0:odd check,1:even check 00:ECB,01:CBC 0:encode,1:decode tdes module enable hash work mode cfg sha3 shake out length 00: normal hash; 01: ipad ;10: opad; 11: reserved hash work module, 5’d0: Doesn’t work 5’d1: MD5 5’d2: SHA-1 mode 5’d3: SHA-224 mode 5’d4: SHA-256 mode 5’d5: SHA-384 mode 5’d6: SHA-512 mode 5’d7: SHA-512/224 mode 5’d8: SHA-512/256 mode 5’d9: SM3 mode 5’d10: SHA3-224 5’d11: SHA3-256 5’d12: SHA3-384 5’d13: SHA3-512 5’d14: SHA3-SHAKE128 5’d15: SHA3-SHAKE256 hash module enable chacha poly work mode cfg 00:chacha20 ; 01:poly1305; 10:AEAD_CHACHA20_POLY1305 0:encrypt,1:decrypt chacha poly module enable simon speck work mode cfg 1: don’t update key, 0: update key 00: key 128bits,01:192bits,10:256bits 000:ECB,001:CBC,010:CTR,100:CFB,101:OFB 0:speck; 1:simon 0:encrypt,1:decrypt chacha poly module enable ce basic configure switch source high 32bits and low 32bits switch destination high 32bits and low 32bits source data switch of one word destination data switch of one word 0:disable hdcp mode, 1: enable hdcp mode list update iv/sec/cnt flag data end in link list mode list end flag 0: isn't aad list 1: is aad list 0: aad no-end list 1: aad end list wait axi B channel bready 0:normal mode, 1: iram key or secure ddr key 0: normal mode, 1: aes/sm4 key from session key 0: normal mode, 1: aes/sm4 key from efuse 1: all crypto key in ddr/iram; 0: from registers 0:normal mode, 1: bypass ce 0: std flag 1: std aad flag 0: std aad no-end flag 1: std aad end flag std end flag 0: enable cmd int output: 1: don't output int 0: dump from ddr; 1: don't dump 0: rcv from ddr; 1: don't rcv 0:std mode, 1: link mode dma read port node data length source address high 4bits; or aes mac aad address high 4bits source fragment length of each node; or aes mac aad length dma write port node data length destination address high 4bits destination fragment length of each node dma source address dma destination address dma one length ce_list_ptr high 4bits first list length,support max 256 nodes dma list pointer aes tdes rsa key length aes hmac key address high 4bits aes hmac key length aes tdes rsa key address aes tag length aes tag address high 4bits aes tag length aes tag address aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter key1 key1 key1 key1 key1 key1 key1 key1 key2 key2 key2 key2 key2 key2 key2 key2 sm4 work mode cfg 1: don’t update key, 0: update key 0: rtl rotation, 1: no-rotation 000:ECB,001:CBC,010:CTR,011:XTS,100:CFB,101:OFB 0:encode,1:decode sm4 module enable IP version r4 px pka work mode cfg pka instruction address high 4bits switch source high 32bits and low 32bits switch destination high 32bits and low 32bits source data switch of one word destination data switch of one word find prime counter threshold pka register number select; 0: 32, 1:16 pka module enable pka register length01 ce pka register length1 ce pka register length0 pka register length23 ce pka register length3 ce pka register length2 pka instruction pointer divisor zero ce pka infinity point ce pka mod inv error ce pka add/sub carry can't fime prime 1: pka one cmd instruction done 1: pka store instruction done pka instruction pointer pka debug info pka debug info pka debug info pka debug info ce performace counter ce use flag the signal only can be confgi in the security apb,when the ce write the huk parameter,the bit should be 1'b1; when the siganl is high ,then flag the pub aes/sm4/hash is catch the cmd from the pub cmd buf or the pub is working when the siganl is high ,then flag the sec aes/sm4/hash is catch the cmd from the sec cmd buf or the sec is working ce sec or pub use the ce aes/sm4/hash cicpher module axi bus cache axi read port outstanding number axi write port outstanding number axi bus wcache axi bus rcache cmd stop ctrl to restart 1: stop command is valid 0: to execute next cmd; 1: finish current cmd,then stop to restart 1: stop command is valid 0: to execute next cmd; 1: finish current cmd,then stop axi prot sel reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable pka side sel; 1: enable pka side axi sel reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable sec side sel; 1: enable sec side axi sel ce performace counter high 32 bit RNG module enable RNG module enable if the signal is high,then the rng data come from cpu. if the signal is high,then the osc rings sel signal come from rf_rng_src_sel_enable. if the signal is high,then the osc rings is auto choose to work the signal control which osc ring is work,when the least bit is high,then the first one osc ring is choose as the entropy. trng source test enable the rst signal to the exotic trng module the signal can change when the trng is work ,which can control the trng start or stop by cpu. trng source enable RNG module enable bit: 1:enbale RNG module to generate random number when auto mode is not enable RNG module config RNG module config Threshold bit value for random data , indicates that the cycle of the src_en is high, the max value is 12'hFFF. when the data_in is 0,the test result should be 1,and the data_in is 1,the test result should be 0; Threshold value for rng_data_valid, indicates that when rng_data_valid high, there area at least number of rng_data_valid_threshold words in SRAM，the max value is 4'hf. ce_rng_exotic_fault_rst_sel: 1'b0:the rst generated by the fault signal, 1'b1:don't generated the rst signal,the rst signal come from the cpu local RNG entropty source select when it's 1,the the post process module need data bitwith is 440bit,else is 256bit the signal select the trng data come from exotic or local trng module 1:exotic 0:local select entropy source,the range is 0x0 to 0x7 RNG data for cpu to read RNG data for cpu to read time interval between two samples time interval between two samples enable first level sample sample period between two samples, the value is from 0 to 255 sample period between two samples, the value is from 0 to 255 post process functions select post process functions select when it's 1,the the PRNG data xor with trng data when it's 1,the the final post process module is enable when it's 1,the the xor process module is enable when it's 1,the the cycle_code module is enable when it's 1,the the lfsr module is enable post data path 1 enable post data path 0 enable rng work status rng work status rand data number when keygen done 2'b01:Instantiate ; 2'b10:Reseed ; 2'b11:Genarate. when it's 1,cpu can send next 64bit pattern when it's 1,the drbg KAT test fail DRBG KAT test done when it's 1,the start-up/on-demand test fail(1024 sample) start-up/on-demand test done the result of test mode when it's 1,indicate that the drbg test result data in 0x260 register is valid (cpu can read to check) 2'b01: C [439:0] ; 2'b10: V[439:0] ; 2'b11: reseed_counter[31:0]. Corresponds to the data of each process in [15:14] . the fifo status the exotic rng module status when high indicates that RNG module has generate 256 bits random data when high indicates that auto mode is ongoing, CPU can't access rng_data register rng time out counter rng time out counter rng interrupt enable rng interrupt enable enable continuous health test interrupt enable sram short interrupt enable timeout interrupt enable process2 interrupt enable process1 interrupt enable process0 interrupt rng interrupt status rng interrupt status continuous health test interrupt status sram_short_interrrupt status timeout interrrupt status process2 interrrupt status process1 interrrupt status process0 interrrupt status rng interrupt clear rng interrupt clear clear continuous health test interrupt clear sram short interrupt clear timeout interrupt clear process2 interrupt clear process1 interrupt clear process0 interrupt RNG module work mode RNG module work mode PRNG work mode: 1: Auto Seed update Mode 0: Mannual seed update Mode RNG module work mode: 10: PRNG mode 01: TRNG mode 00：11: Mixed mode for TRNG PRNG mode seed update config PRNG mode seed update config When Write to 1, PRNG will update seed to PRNG_SEED_CONFIG register value PRNG mode seed update config PRNG mode seed update config RNG Bit Rate RNG Bit Rate RNG Bit Counter RNG Bit number each 10000 clock cycle SRAM data numuber threshold SRAM data numuber threshold SRAM data numuber threshold, rng_sram_data_residue_num rng_sram_data_residue_num rng_sram_data_residue_num exotic fault counter rng exotic fault counter config config the fault counter and read the counter drbg seed count drbg seed count config the drbg seed after certain time config ring ring number config ring ring number config ring ring number config ring ring number rng_health_test_config rng_health_test_config default:11'd607(freq 0/1 in 1024) default:6'd47 (conse 48 0/1) [23] open drbg test(on-demand test) open es test(on-demand test) ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_h ce_rng_drbg_test_pattern_h raw_random_number raw_random_number ce_rng_drbg_sha256_result ce_rng_drbg_sha256_result session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS ce secure key work mode trng output random data for secure key flag;when 256bits HUK output into efuse,the bit will be zero. cpu access secure key flag;the falling edge is to let efuse controller sync data into efuse memory secure key length configure for key in efuse feature,when read key from efuse, need know this key length secure key2 start read address of efuse memory secure key1 start read address of efuse memory need to read secure key2 from efuse;when need two key(key1 and key2), this bit should be set. ce huk key config HUK key initial address HUK key length ce pka key config PKA private key end address,default value depends on the parameter value passed by AP to CE top,this register writing funciton is standing off . PKA private key start address,default value depends on the parameter value passed by AP to CE top ,this register writing funciton is standing off . ce_cmd_fifo_entry ce_cmd_fifo_status ce_rcv_addr_lo ce_dump_addr_lo ce_dump_addr_hi ce dump address hi ce rcv address hi ce_finish_cmd_cnt ce_pka_cmd_fifo_entry ce_pka_cmd_fifo_status pka cmd dma source address pka store dma destination address pka store high 19bits addr pka load address pka load high 19bits addr ce_pka_finish_cmd_cnt start ce pka start ce pka clear ce pka reset ce pka status ce_pka_rng_force_ssb_bit force the prime ssb bit is 1 ce_pka_ctrl_operate_bit this bit control the store inst, 1:when the bit set 1, then the store data from pka ram to ddr don't have any limit; when the bit set 0, then the store inst need judge the buf can store out or not, the store register index can config through the pka load_rng inst; pka write efuse and read efuse work status bit[23]:reserved bit[22]:pka read efuse cmd vaild; bit[21]:pka write efuse cmd vaild; bit[20]:used to control pka load FSM state jump; bit[19]:indicates pka would read efuse when the huk is reading or writing efuse; bit[18]:indicates pka would write efuse when the huk is reading or writing efuse; bit[17]:indicates huk would read efuse when the pka is reading or writing efuse; bit[16]:indicates huk would write efuse when the pka is reading or writing efuse; depend on read pka private key length,ce top starts to count,when this count depend on write pka private key length,ce top starts to count axi bus status and dma work state status axi write data channel ready axi write address channel ready axi read address channel ready dma is working,and CPU can't access ce registers except ce_clear register. dma write port state: 4'd0: idle 4'd1: write burst calculate 4'd2: write burst calculate data number 4'd3: write burst wait enough data 4'd4: write burst start 4'd5: write burst execute 4'd6: write burst wait burst end 4'd7: write burst end dma read port state: 4'd0: idle 4'd1: read burst wait enough buffer space 4'd2: read burst wait one cycle 4'd3: read burst start 4'd4: read burst execute 4'd5: read burst wait burst end 4'd6: read burst done fde cmd fifo is non-empty cmd fifo is non-empty interrupt raw status is valid ce in error status dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 3'd0: idle 3'd1: pka read instruction start 3'd2: pka load start 3'd3: pka wait done 3'd4: pka send done 3'd5: pka jump judgement dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done aes module state rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish dma control main read port state: 5'd0: idle 5'd1: read key/hmac key/aad start 5'd2: wait read key/hmac key/aad done 5'd3: read key/hmac key/aad, send done 5'd4: read key/hmac key/aad done 5'd5: STD read start 5'd6: STD wait done 5'd7: STD send done 5'd8: STD done,then judgement 5'd9: STD pause 5'd10: STD done 5'd11: LLIST read list 5'd12: LLIST read list wait done 5'd13: LLIST read list send done 5'd14: LLIST read list done 5'd15: LLIST read node 5'd16: LLIST read node wait 5'd17: LLIST read node done 5'd18: LLIST node execution 5'd19: LLIST node execution, wait done 5'd20: LLIST node execution, send done 5'd21: LLIST node execution done 5'd22: LLIST judge next state 5'd23: LLIST pause 5'd24: LLIST done 5'd25: read session key start 5'd26: read session key done rdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish sm4 state: 3'd0: idle 3'd1: generate key 3'd2: round start 3'd3: rounding 3'd4: xts generate key 3'd5: xts round start 3'd6: xts rounding 3'd7: done wdma data status: 2'd0: idle 2'd1: read start 2'd2: read wait 2'd3: read finish [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait tdes module state tdes module status: [3:0]: des run cycle counter [4]: des key check error generate wvalid state: 4'd0: idle 4'd1: wait enough data 4'd2: generate wvalid 4'd3: wait enough data when bursting 4'd4: wait wready for next burst data efuse access status: 5'd0: idle 5'd1: read selec between hmac and symmetric 5'd2: trng write start 5'd3: hmac session key read start 5'd4: trng write 5'd5: hmac read 5'd6: symmetric key1 read start 5'd7: symmetric key2 read start 5'd8: symmetric key1 read 5'd9: symmetric key2 read 5'd10: done 5'd11: hmac session key read 5'd12: read huk after write err 5'd13: trng write next 5'd15: iram key done 5'd16: pka non-symmetric key read start 5'd17: pka non-symmetric key read 5'd18: pka non-symmetric key write start 5'd19: pka non-symmetric key write 5'd20: pka non-symmetric key write next 5'd21: ce read non-symmetric key after write err 3'd0: idle 3'd1: pka store start 3'd2: pka wait done 3'd3: pka send done 3'd4: pka jump judgement dma control main write port state: 5'd0: idle 5'd1: STD hash start 5'd2: STD start 5'd3: STD wait done 5'd4: STD send done 5'd5: STD next state judgement 5'd6: STD pause 5'd7: STD done 5'd8: LLIST check node buffer status 5'd9: LLIST load node 5'd10: LLIST load node wait 5'd11: LLIST load node update parameter 5'd12: LLIST load node done 5'd13: LLIST hash start 5'd14: LLIST start 5'd15: LLIST wait done 5'd16: LLIST send done 5'd17: LLIST next start judgement 5'd18: LLIST pause 5'd19: LLIST done 5'd20: pka store start 5'd21: pka wait done 5'd22: pka send done 5'd23: pka jump judgement [3:0]: aes read counter; [7:4]: aes work state 4'd0: idle 4'd1: key expand 4'd2: xts encrypto tweek 4'd3: enc/decrpto select 4'd4: wait 4'd5: one block done 4'd6: xts encrypto tweek post 4'd7: xts encrypto tweek pre ' 4'd8: zero encrypto 4'd9: aad ghash 4'd10: length ghash 4'd11: gcm wait hash module state 0 hash module state 1 hash module status: [2:0]: hash state 3'd0: idle 3'd1: data request 3'd2: no-hmac 3'd3: hmac key 3'd4: first hmac message 3'd5: second hmac message 3'd6: digest out [8:3]: hash run cycle ce module clock enable force fde aes clock enable force pub rng autogate clock enable pub trng clock enable force chacha engine clock enable force poly engine clock enable force rng autogate clock enable force aes key expan autogate clock enable force dma axi autogate clock enable force dma ctrl autogate clock enable force apb regbank autogate clock enable simon speck clock enable pka clock enable chacha poly clock enable sm4 clock enable trng clock enable des clock enable hash clock enable fde aes clock enable aes clock enable dma_main clock enable ce interrupt enable enable src/dst length error int enable one command done int enable src/dst length error int enable one command done int enable rng/trng int enable tdes key check error int ce interrupt status src/dst length error int status one command done int status, src/dst length error int status one command done int status, ce rng/trng int status ce tdes key check error int status ce interrupt clear src/dst length error int status one command done int status, clear error int status clear one command done int status, clear tdes key check error int status start ce start ce clear ce reset ce status aes work mode cfg 1: don’t update key, 0: update key 0: rtl rotation, 1: no-rotation 00: key 128bits,01:192bits,10,11:256bits 0000:ECB,0001:CBC,0010:CTR,0011:XTS,0100:CMAC,0101:GCM,0110:GMAC,0111:CCM,1000:CBCMAC,1001:CFB,1010:OFB aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid 0:encode,1:decode aes module enable tdes work mode cfg 0: disable, 1: enable even/odd check 0:odd check,1:even check 00:ECB,01:CBC 0:encode,1:decode tdes module enable hash work mode cfg sha3 shake out length 00: normal hash; 01: ipad ;10: opad; 11: reserved hash work module, 5’d0: Doesn’t work 5’d1: MD5 5’d2: SHA-1 mode 5’d3: SHA-224 mode 5’d4: SHA-256 mode 5’d5: SHA-384 mode 5’d6: SHA-512 mode 5’d7: SHA-512/224 mode 5’d8: SHA-512/256 mode 5’d9: SM3 mode 5’d10: SHA3-224 5’d11: SHA3-256 5’d12: SHA3-384 5’d13: SHA3-512 5’d14: SHA3-SHAKE128 5’d15: SHA3-SHAKE256 hash module enable chacha poly work mode cfg 00:chacha20 ; 01:poly1305; 10:AEAD_CHACHA20_POLY1305 0:encrypt,1:decrypt chacha poly module enable simon speck work mode cfg 1: don’t update key, 0: update key 00: key 128bits,01:192bits,10:256bits 000:ECB,001:CBC,010:CTR,100:CFB,101:OFB 0:speck; 1:simon 0:encrypt,1:decrypt chacha poly module enable ce basic configure switch source high 32bits and low 32bits switch destination high 32bits and low 32bits source data switch of one word destination data switch of one word 0:disable hdcp mode, 1: enable hdcp mode list update iv/sec/cnt flag data end in link list mode list end flag 0: isn't aad list 1: is aad list 0: aad no-end list 1: aad end list wait axi B channel bready 0:normal mode, 1: iram key or secure ddr key 0: normal mode, 1: aes/sm4 key from session key 1: all crypto key in ddr/iram; 0: from registers 0:normal mode, 1: bypass ce 0: std flag 1: std aad flag 0: std aad no-end flag 1: std aad end flag std end flag 0: enable cmd int output: 1: don't output int 0: dump from ddr; 1: don't dump 0: rcv from ddr; 1: don't rcv 0:std mode, 1: link mode dma read port node data length source address high 4bits; or aes mac aad address high 4bits source fragment length of each node; or aes mac aad length dma write port node data length destination address high 4bits destination fragment length of each node dma source address dma destination address dma one length ce_list_ptr high 4bits first list length,support max 256 nodes dma list pointer aes tdes rsa key length aes hmac key address high 4bits aes hmac key length aes tdes rsa key address aes tag length aes tag address high 4bits aes tag length aes tag address aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter key1 key1 key1 key1 key1 key1 key1 key1 key2 key2 key2 key2 key2 key2 key2 key2 sm4 work mode cfg 1: don’t update key, 0: update key 0: rtl rotation, 1: no-rotation 000:ECB,001:CBC,010:CTR,011:XTS,100:CFB,101:OFB 0:encode,1:decode sm4 module enable IP version r4 px ce performace counter ce use flag when the siganl is high ,then flag the pub aes/sm4/hash is catch the cmd from the pub cmd buf or the pub is working when the siganl is high ,then flag the sec aes/sm4/hash is catch the cmd from the sec cmd buf or the sec is working ce sec or pub use the ce aes/sm4/hash cicpher module axi bus cache axi read port outstanding number axi write port outstanding number axi bus wcache axi bus rcache cmd stop ctrl fde to restart 1: fde stop command is valid 0:fde to execute next cmd; 1: fde finish current cmd,then stop to restart 1: stop command is valid 0: to execute next cmd; 1: finish current cmd,then stop axi prot sel reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable fde side sel; 1: enable fde side axi sel reserved 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: non_prot; 1: prot; 0: disable pub side sel; 1: enable pub side axi sel ce performace counter high 32 bit RNG module enable RNG module enable if the signal is high,then the rng data come from cpu. if the signal is high,then the osc rings sel signal come from rf_rng_src_sel_enable. if the signal is high,then the osc rings is auto choose to work the signal control which osc ring is work,when the least bit is high,then the first one osc ring is choose as the entropy. trng source test enable the rst signal to the exotic trng module the signal can change when the trng is work ,which can control the trng start or stop by cpu. trng source enable RNG module enable bit: 1:enbale RNG module to generate random number when auto mode is not enable RNG module config RNG module config Threshold bit value for random data , indicates that the cycle of the src_en is high, the max value is 12'hFFF. when the data_in is 0,the test result should be 1,and the data_in is 1,the test result should be 0; Threshold value for rng_data_valid, indicates that when rng_data_valid high, there area at least number of rng_data_valid_threshold words in SRAM，the max value is 4'hf. ce_rng_exotic_fault_rst_sel: 1'b0:the rst generated by the fault signal, 1'b1:don't generated the rst signal,the rst signal come from the cpu local RNG entropty source select when it's 1,the the post process module need data bitwith is 440bit,else is 256bit the signal select the trng data come from exotic or local trng module 1:exotic 0:local select entropy source,the range is 0x0 to 0x7 RNG data for cpu to read RNG data for cpu to read time interval between two samples time interval between two samples enable first level sample sample period between two samples, the value is from 0 to 255 sample period between two samples, the value is from 0 to 255 post process functions select post process functions select when it's 1,the the PRNG data xor with trng data when it's 1,the the final post process module is enable when it's 1,the the xor process module is enable when it's 1,the the cycle_code module is enable when it's 1,the the lfsr module is enable post data path 1 enable post data path 0 enable rng work status rng work status rand data number when keygen done 2'b01:Instantiate ; 2'b10:Reseed ; 2'b11:Genarate. when it's 1,cpu can send next 64bit pattern when it's 1,the drbg KAT test fail DRBG KAT test done when it's 1,the start-up/on-demand test fail(1024 sample) start-up/on-demand test done the result of test mode when it's 1,indicate that the drbg test result data in 0x260 register is valid (cpu can read to check) 2'b01: C [439:0] ; 2'b10: V[439:0] ; 2'b11: reseed_counter[31:0]. Corresponds to the data of each process in [15:14] . the fifo status the exotic rng module status when high indicates that RNG module has generate 256 bits random data when high indicates that auto mode is ongoing, CPU can't access rng_data register rng time out counter rng time out counter rng interrupt enable rng interrupt enable enable continuous health test interrupt enable sram short interrupt enable timeout interrupt enable process2 interrupt enable process1 interrupt enable process0 interrupt rng interrupt status rng interrupt status continuous health test interrupt status sram_short_interrrupt status timeout interrrupt status process2 interrrupt status process1 interrrupt status process0 interrrupt status rng interrupt clear rng interrupt clear clear continuous health test interrupt clear sram short interrupt clear timeout interrupt clear process2 interrupt clear process1 interrupt clear process0 interrupt RNG module work mode RNG module work mode PRNG work mode: 1: Auto Seed update Mode 0: Mannual seed update Mode RNG module work mode: 10: PRNG mode 01: TRNG mode 00：11: Mixed mode for TRNG PRNG mode seed update config PRNG mode seed update config When Write to 1, PRNG will update seed to PRNG_SEED_CONFIG register value PRNG mode seed update config PRNG mode seed update config RNG Bit Rate RNG Bit Rate RNG Bit Counter RNG Bit number each 10000 clock cycle SRAM data numuber threshold SRAM data numuber threshold SRAM data numuber threshold, rng_sram_data_residue_num rng_sram_data_residue_num rng_sram_data_residue_num exotic fault counter rng exotic fault counter config config the fault counter and read the counter drbg seed count drbg seed count config the drbg seed after certain time config ring ring number config ring ring number config ring ring number config ring ring number rng_health_test_config rng_health_test_config default:11'd607(freq 0/1 in 1024) default:6'd47 (conse 48 0/1) [23] open drbg test(on-demand test) open es test(on-demand test) ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_l ce_rng_drbg_test_pattern_h ce_rng_drbg_test_pattern_h raw_random_number raw_random_number ce_rng_drbg_sha256_result ce_rng_drbg_sha256_result session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS session key from secure OS ce_cmd_fifo_entry ce_cmd_fifo_status ce_rcv_addr_lo ce_dump_addr_lo ce_dump_addr_hi ce dump address hi ce rcv address hi ce_finish_cmd_cnt ce_fde_aes_cmd_fifo_entry ce_fde_aes_cmd_fifo_status ce_fde_aes_rcv_addr_lo ce_fde_aes_dump_addr_lo ce_fde_aes_dump_addr_hi ce fde_aes cipher dump address hi,or aes tag address high 4bits ce fde_aes cipher rcv address hi ce_fde_aes_finish_cmd_cnt start fde_aes cipher ce start fde_aes cipher ce(TDES/AES/SM4/SM1/SM7/GHASH) clear fde_aes cipher ce reset ce fde_aes cipher status fde_aes cipher work mode cfg aes mac ctr inc mode: 00: normal mode; 01: low 64bit is valid 00: key 128bits,01:192bits,10,11:256bits 0: rtl rotation, 1: no-rotation(sm4/aes) 0000:ECB,0001:CBC,0010:CTR,0011:XTS 0:encode,1:decode fde_aes cipher module enable ce fde_aes cipher basic configure ce fde iv auto add 1‘b1 each 512Byte msg fde_aes switch source high 32bits and low 32bits fde_aes switch destination high 32bits and low 32bits fde_aes cipher source data switch of one byte fde_aes cipher destination data switch of one byte list update iv/sec/cnt flag fde_aes cipher data end in link list mode fde_aes cipher list end flag 0:normal mode, 1: iram key or secure ddr key 0: normal mode, 1: aes key from session key 1: fde_aes cipher all crypto key in ddr/iram,and the iv also come from drr except the link list mode; 0:fde_aes cipher from registers fde_aes cipher std end flag 0: fde_aes cipher enable cmd int output: 1: don't output int 0:fde_aes cipher dump from ddr; 1:fde_aes cipher don't dump 0:fde_aes cipher rcv from ddr; 1:fde_aes cipher don't rcv 0:fde_aes cipher std mode, 1:fde_aes cipher link mode fde_aes cipher dma one length ce_fde_aes_list_ptr high 4bits fde_aes cipher first list length,support max 40 nodes fde_aes cipher dma list pointer fde_aes cipher dma read port node data length fde_aes cipher destination address high 4bits fde_aes cipher source address high 4bits; or aes mac aad address high 4bits fde_aes cipher source fragment length of each node; or aes mac aad length fde_aes cipher dma source address fde_aes cipher dma destination address fde aes key length fde aes key address high 4bits fde aes key length fde aes key address fde aes dst ddr select axi awprot under key in iram mode 0: non_sec 1: sec ce fde aes dummy register ce fde aes dummy register aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter aes tdes iv sector counter fde key1 fde key1 fde key1 fde key1 fde key1 fde key1 fde key1 fde key1 fde key2 fde key2 fde key2 fde key2 fde key2 fde key2 fde key2 fde key2 fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS fde session key from secure OS DMA Block Count Block Size and Count Transfer blocks size. This register specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. 0x0000: no data transfer 0x0001: 1 byte Argument Transfer mode and command Set to indicate the host whether card will send boot ack 1’b1: send boot ack 1’b0: not send boot ack Set to begin drive low cmd line and waiting to receive boot data block 1’b1: Drive cmd line low 1’b0: not drive cmd line Command index, set to the command number (CMD0-63, ACMD0-63) Commend type. There are three types of special commands, Suspend, Resume and Abort. These bits shall bet set to 00b for all other commands. 00: Normal 01/10: Reserved 11: Abort Data present select 0: no data present 1: data present This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0 for the following: 1. Commands using only CMD line (e.g., CMD52) 2. Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b, e.g., CMD38) 3. Resume Command Command index check enable 0: disable 1: enable If this bit is set to 1, the HC shall check the index field in the Response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked. Command CRC check enable 0: disable 1: enable If this bit is set to 1, the HC shall check the CRC field in the Response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked Sub Command Flag 0: Main Command 1: Sub Command Response type select 00: no response 01: response length 136 10: response length 48 11: response length 48, check Busy after response Response Interrupt Disable 0: Response Interrupt is enabled. 1: Response Interrupt is disabled. Support response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0 and waits Command Complete Interrupt and then checks the response register. If Host Controller checks response error, sets this bit to 1 and sets Response Error Check Enable to 1, Command Complete Interrupt is disabled by this bit regardless of Command Complete Signal Enable Response Error Check Enable 0: Response Error check is disabled 1: Response Error check is enabled. Support response error check function to avoid overhead of response error check by Host driver. Only R1 or R5 can be checked. If Host Driver check response error, this bit is set to 0 and Response Interrupt Disable is set to 0, If Host Controller checks response error, sets this bit to 1 and sets Response Interrupt Disable to 1. Response Type R1/R5 selects either R1 or R5 response type. If an error is detected, Response Error Interrupt is generated in the Error Interrupt Status register. Response Type R1/R5 0: R1 (Memory) 1: R5 (SDIO) When response error check is enabled, this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO. Error Statues checked in R1 Bit: 19/20/21/23/25/26/29/30/31 Response Flags Checked in R5: Bit: 0/1/3/7 Multiple/single block select 0: single block 1: multiple blocks Data transfer direction select 0: write (Host to Card) 1: read (Card to Host) Auto CMD enable 00: disable 01: Auto CMD12 Enable 10: Auto CMD23 Enable 11: Auto CMD auto select 1: Auto CMD12 Enable: Multiple block transfers for memory require CMD12 to stop the transaction. When this bit is set to 1, the HC shall issue CMD12 automatically when last block transfer is completed. The HD shall not set this bit to issue commands that do not require CMD12 to stop data transfer. 2: Auto CMD23 Enable: When this bit field is set to 10b, the Host Controller issues a CMD23 automatically before issuing a command specified in the Command Register 3: Auto CMD auto select. When this mode select, selection of auto CMD depends on setting of CMD23 Enable in the Host Ctrl 2 register which indicated whether card support CMD23. If CMD23 Enable=1, auto CMD23 is used and if CMD23 Enable=0, auto CMD12 is used. Use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. Block count enable (This design not support infinite mode, so it is always 1) DMA enable (This design not support NO-DMA mode, so it is always 1) RESP0 RESP1 RESP2 RESP3 DMC AXI channel 0 configuration register Sub Command Flag 0: Main Command 1: Sub Command CMD line signal level. This status is used to check CMD line level to recover from errors, and for debugging DAT [3:0] line signal level. This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT [0]. [23]: for DAT[3] [22]: for DAT[2] [21]: for DAT[1] [20]: for DAT[0] Read transfer active. This status is used for detecting completion of a read transfer. This bit is set to 1 for either of the following conditions: 1. After the end bit of the read command 2. When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer This bit is cleared to 0 for either of the following conditions: 1. When the last data block as specified by block length is transferred to the system. 2. When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop at Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 0: no valid data 1: transferring data Write transfer active. This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: 1. After the end bit of the write command 2. When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer This bit is cleared in either of the following cases: 1. After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) 2. After getting a CRC status of any block where data transmission is about to be stopped by a Stop at Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop at Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 0: no valid data 1: transferring data This bit selects 32B or 64B size when splitting AXI burst to DDR bursts. 0 : only 32byte split size 1 : dynamic split size, 32B or 64B, based on AXI transactions DAT line active. This bit indicates whether one of the DAT line on SD bus is in use. 0: DAT line inactive 1: DAT line active Command inhibit (DAT) This status bit is generated if either the DAT Line Active or the Read Transfer Active is 1. If this bit is 0, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (e.g., R1b, R5b type). Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt status register. Note: The SD Host Driver can save registers in the range of 0x0000 ~ 0x000D for a suspend transaction after this bit has changed from 1 to 0. 0: can issue command that uses the DAT line 1: cannot issue command that uses the DAT line Command inhibit (CMD) If this bit is 0, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the Command register (0x000F) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the HC cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1 and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. SD Host Control Register1 Interrupt at block gap. This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. Read wait control. The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise, the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1 or DAT line conflict may occur. If this bit is set to 0, Suspend/Resume cannot be supported. 0: disable read wait control 1: enable read wait control SD8 bit mode Extended Data Transfer Width This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controller by Data Transfer Width in the Host Control 1 register. 1: 8-bit Bus Width 0: Bus Width is Selected by Data Transfer Width DMA Select 2’b00: SDMA is select 2’b01: Reserved 2’b10: ADMA2 is select 2’b11: ADMA2/3 is select Data transfer width, SD1 or SD4. This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. 0: 1-bit mode 1: 4-bit mode SD Control Register2 Hardware reset for card 1: Normal work 0: card reset , should be set back to 1 manually Software reset for DAT line. Only part of data circuit is reset. DMA circuit is also reset. The following registers and bits are cleared by this bit: • Buffer Data Port Register:  Buffer is cleared and initialized. • Present State register:  Buffer Read Enable  Buffer Write Enable  Read Transfer Active  Write Transfer Active  DAT Line Active  Command Inhibit (DAT) • Block Gap Control register:  Continue Request  Stop At Block Gap Request • Normal Interrupt Status register  Buffer Read Ready  Buffer Write Ready  Block Gap Event Transfer Complete 0: work 1: reset Software reset for CMD line. Only part of command circuit is reset. The following registers and bits are cleared by this bit: • Present State register  Command Inhibit (CMD) • Normal Interrupt Status register  Command Complete 0: work 1: reset Software reset for all. This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the HD shall set this bit to 1 to reset the HC. The HC shall reset this bit to 0 when Capabilities registers are valid and the HD can read them. Additional use of Software Reset for All may not affect the value of the Capabilities registers. If this bit is set to 1, the SD card shall reset itself and must be reinitialized by the HD. 0: work 1: reset Data timeout counter value. This value determines the interval by which DAT line timeouts are detected. Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate timeout generation. Timeout clock frequency will be generated by dividing the base clock TMCLK by this value. When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). 0000: TMCLK * 2^(16) 0001: TMCLK * 2^(17) … 1110: TMCLK * 2^(30) 1111: TMCLK * 2^(31) SDCLK/RCLK Frequency Select If Freq_div = 0:Base clk Freq_div = 1:Base clk/2 Freq_div = 2:Base clk/4 Freq_div = 3:Base clk/6 …… Freq_div= n:Base clk/(2*n) SDCLK/RCLK Frequency Select[9:8] SD clock enable. The HC shall stop SDCLK when writing this bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared. 0: disable 1: enable Internal clock stable. This bit is set to 1 when SD clock is stable after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is 1.Note: This is useful when using PLL for a clock oscillator that requires setup time. 0: not ready 1: ready Internal clock enable. This bit is set to 0 when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go to the very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the HC shall set Internal Clock Stable in this register to 1. This bit shall not affect card detection. 0: stop 1: oscillate Note: It is recommended to set this bit to 0 before changing the clock source, and then set it to 1 after the changing is done. But changing the frequency divider need not to set this bit to 0. Normal and error interrupt status AXI Bus Error 0: no error 1: error Response Error 0: no error ADMA Error 0: no error 1: error Auto CMD12 error. This occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed from 0 to 1. This bit is set to 1 also when Auto CMD12 is not executed due to the previous command error. 0: no error 1: error Data end bit error. This occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status. 0: no error 1: error Data CRC error. This occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than “010”. 0: no error 1: error Data timeout error. This occurs when detecting one of the following timeout conditions. 1. Busy Timeout for R1b, R5b type 2. Busy Timeout after Write CRC status 3. Write CRC status Timeout 4. Read Data Timeout 0: no error 1: timeout Command index error. This occurs if a Command Index error occurs in the Command Response. 0: no error 1: error Command end bit error. This occurs when detecting that the end bit of a command response is 0. 0: no error 1: end bit error generated Command CRC error. Command CRC Error is generated in two cases. 1. If a response is returned and the Command Timeout Error is set to 0, this bit is set to 1 when detecting a CRC error in the command response 2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 levels on the CMD line at the next SDCLK edge, then the HC shall abort the command (stop driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line conflict. 0: no error 1: CRC error generated Command timeout error. This occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC. 0: no error 1: timeout Error Interrupt If any of the bits in the Error Interrpt Status register are set, then this bit is set. Therefore the Host Driver can efficiently test for an error by checking this bit first. This bit is read only. 0: no error 1: error ADMA3 Complete Card interrupts. Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the interrupt to the Host system. When this status has been set and the HD needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status register shall be set to 0 in order to clear the card interrupt statuses latched in the HC and stop driving the Host System. After completion of the card interrupt service (the reset factor in the SD card and the interrupt signal may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again. 0: no card interrupt 1: card interrupt generated DMA interrupt. This status is set if the HC detects the Host DMA Interrupt. 0: no DMA interrupt 1: DMA interrupt generated Transfer complete. This bit is set when a read/write transaction is completed. Read Transaction: This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (after the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop at Block Gap Request in the Block Gap Control register (after valid data has been read to the Host System). Write Transaction: This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop at Block Gap Request in the Block Gap Control register and data transfers completed (after valid data is written to the SD card and the busy signal is released). 0: no data transfer complete 1: data transfer complete Command complete. This bit is set when getting the end bit of the command response (except auto CMD12 and auto CMD23). Note: Command Timeout Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly. 0: no command complete 1: command complete Normal and error interrupt status enable AXI Bus Error status enable Response Error status enable ADMA Error status enable Auto CMD12 error status enable Data end bit error status enable Data CRC error status enable Data timeout error status enable Command index error status enable Command end bit error status enable Command CRC error status enable Command timeout error status enable ADMA3 Complete status enable Card interrupt status enable DMA interrupt status enable Transfer complete status enable Command complete status enable Normal and error interrupt signal enable AXI Bus Error signal enable Response Error signal enable ADMA Error signal enable Auto CMD12 error signal enable Current limit error signal enable Data end bit error signal enable Data CRC error signal enable Data timeout error signal enable Command index error signal enable Command end bit error signal enable Command CRC error signal enable Command timeout error signal enable ADMA3 transfer complete signal enable Card interrupt signal enable DMA interrupt signal enable Transfer complete signal enable Command complete signal enable Host controller 2 and Auto CMD12 error status The system address is 32 bit or 64 bits 0: 32 bit address 1: 64 bit address This design is host version 4 CMD23 Enable This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. Refer to Auto CMD Enable in the Transfer Mode Register 0: AutoCMD auto select CMD12 1: AutoCMD auto select CMD23 The ADMA2 length mode is 26 bit or 16bit 0: 16 bit data length mode 1: 26 bit data length mode UHS Mode Select This field is used to select one of UHS-I mode and effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the SD_CTRL3 register is set to 1, Host controller sets SDCLK Frequency Select, Clock Generator Select in the Clock Control register according to Preset Value registers. In this case, one of preset value registers is selected by this field. Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again. 4’b0000: SDR12 4’b0001: SDR25 4’b0010: SDR50 4’b0011: SDR104 4’b0100: DDR50 4’b0101: HS200 4’b0110: HS400 4’b0111: HS401 (EMMC5.1) HS400 mode 4’b1000: DDR200, SD6.0 Command not issued error. Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error ([4:1]) in this register. 0: no error 1: not issued Auto CMD index error. This occurs if the Command Index error occurs in response to a command. 0: no error 1: error Auto CMD end bit error. This occurs when detecting that the end bit of command response is 0. 0: no error 1: end bit error generated Auto CMD CRC error. This occurs when detecting a CRC error in the command response. 0: no error 1: CRC error generated Auto CMD timeout error. This occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits ([4:2]) are meaningless. 0: no error 1: timeout Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error. This bit is not set because it is not necessary to issue auto cmd12. Setting this bit to 1 means the Host Controller cannot issue auto cmd12 to stop memory multiple block data transfer due to some error. If this bit is set to 1. Other error status bits are meaningless. Capabilities Slot Type 2’b00: Removable Card Slot Asynchronous Interrupt Support 1’b0:Asynchronous Interrupt Not Supported 64 bit System Bus Support 1’b0 64 bit System Bus Support 64 bit System Bus Support 1’b0 64 bit System Bus Support Voltage support 1.8 V. 0: 1.8 V not supported 1: 1.8 V supported Voltage support 3.0 V. 0: 3.0 V not supported 1: 3.0 V supported Voltage support 3.3 V. 0: 3.3 V not supported 1: 3.3 V supported Suspend/resume support. This bit indicates whether the HC supports Suspend/Resume function. If this bit is 0, the Suspend and Resume mechanism is not supported and the HD shall not issue either Suspend/Resume command. 0: not supported 1: supported DMA support. This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly. 0: DMA not supported 1: DMA supported High speed support. This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz 0: high speed not supported 1: high speed supported ADMA2 Support 1’b0: ADMA2 is not supported 1’b1: ADMA2 is supported 8-bit Support for Device 1’b1: 8-bit Bus Width Supported This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. 00: 512 bytes 01: 1024 bytes 10: 2048 bytes 11: 4096 bytes This value indicates the base (maximum) clock frequency for the SD clock. The unit is MHz If the real frequency is 16.5 MHz, a larger value shall be set, i.e., 010001b (17 MHz) because the HD uses this value to calculate the clock divider value and it shall not exceed the upper limit of the SD clock frequency. The supported range is 10 to 63 MHz If these bits are all 0, the Host System has to get information via another method. 0: get information via another method (Registry Entry) 1: 1 MHz 2: 2 MHz … FF: 255 MHz This bit shows the unit of base clock frequency used to detect Data Timeout Error. 0: kHz 1: MHz This bit shows the base clock frequency used to detect Data Timeout Error. 0: get information via another method 1: 1 MHz 2: 2 MHz … 63: 63 MHz Capabilities 2 ADMA3 is support DDR50 Support 1’b0: DDR50 is Supported SDR104 Support 1’b0 : SDR104 is Supported SDR50 Support 1’b0: SDR50 is Supported Force event register Force Event for Auto CMD Error Force Event for tuning Error Force Event for Response Error Force Event for Data End Bit Error Force Event for Data CRC Error Force Event for Data Timeout Error Force Event for Command Index Error Force Event for Command End Bit Error Force Event for Command CRC Error Force Event for Command Time Out Error Force Event for Command Not Issued By Auto CMD12 Error Force Event for Auto CMD Index Error Force Event for Auto CMD End Bit Error Force Event for Auto CMD Timeout Error Force Event for Auto CMD Timeout Error Force Event for Auto CMD 12 Not Executed 1: Interrupt is generated 0: No Interrupt ADMA Error State register If BRESP = SLVERR or DECERR, then BRESP_ERR is occurred, and this register will indicted the type of Error. 00: OKAY 01: EXOKAY 10: SLVERR 11: DECERR If RRESP = SLVERR or DECERR, then RRESP_ERR is occurred, and this register will indicted the type of Error. 00: OKAY 01: EXOKAY 10: SLVERR 11: DECERR ADMA Length Mismatch Error 1: Error 0: No Error This error occurs in the following 2 cases: 1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length 2) Total data length cannot be divided by the block length. ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer. 2’b00: ST_STOP (Stop DMA), Points next of the error descriptor. 2’b01: ST_FDS (Fetch Descriptor), Points the error descriptor 2’b10: Reserved 2’b11: ST_TFR (Transfer Data), Points the next of the error descriptor ADMA2 System Address Low registers ADMA2 System Address High registers ADMA3 System Address Low registers ADMA3 System Address High registers Host version number This status indicates the Host Controller Spec Version. The upper and lower 4 bits indicate the version. 00: SD Host Specification version 1.0 01 SD Host Specification Version 2.0 02 SD Host Specification Version 3.0 03 SD Host Specification Version 4.0 04 SD Host Specification Version 4.1 Others: reserved One slot, it is equal to the int_to_arm EMMC PHY DLL CFG registers Cycles to wait DLL locked signals. Read negedge delay cell select 0:use user defined value from CLKNEGRD_DLY_ VAL 1:use dll generated value which referenced form CLKNEGRD_DLY_ VAL Read posedge delay cell select 0:use user defined value from CLKPOSRD_DLY_VAL 1:use dll generated value which referenced form CLKPOSRD_DLY_VAL Read cmd delay cell select 0:use user defined value from CLKCMDRD_DLY_VAL 1:use dll generated value which referenced form CLKCMDRD_DLY_VAL write delay cell select 0:use user defined value from CLKDATWR_DLY_VAL 1:use dll generated value which referenced form CLKDATWR_DLY_VAL DLL Clock source selection 0: Select 1x clock 1: Select 2x clock DLL enable signal 0:DLL disable 1:DLL enable DLL clear signal 1:clear DLL Don’t support in this version DLL output delay value enable DLL start enable signal, this bit should be write to 1’b0 when it is enabled to 1’b1 DLL lock mode: 0: full cycle lock mode 1: half cycle lock mode DLL count initial value, DLL use it as the initial value to count the delay value. DLL change threshold value, DLL update rd/wr/cmd delay line value if the DLL count delta bigger then DLL_CPST_THRESHOLD DLL phase interval , DLL use it as the interval of phase 1 and phase2 OUPUT clock phase select EMMC PHY DLL DLY registers Clock Read Data Negedge Delay Value Based Phase is same as PHY Clock Refer to description of CLKDATWR_DLY_VAL Clock Read Data Posedge Delay Value Based Phase is same as PHY Clock Refer to description of CLKDATWR_DLY_VAL Clock Read Command Line Delay Value Based Phase is same as PHY Clock Refer to description of CLKDATWR_DLY_VAL Clock Data Write Line Delay Value Based Phase is invert of PHY Clock When DLL_DATWR_CPST_EN is enable, This register is act as proportion of DLL clock cycle. E.g.(when DLL_DATWR _CPST_EN==1) If CLKDATWR _DLY_ VAL ==’h40, it means delay ‘h40/’h100 ≈ 1/4 cycle. If CLKDATWR_DLY_ VAL ==’h80, it means delay ‘h80/’h100F ≈ 1/2 cycle. EMMC PHY DLL Offset Read registers Clock Read Data Negedge Delay Invert Refer to description of CLKDATWR_DLY_OFFSET Clock Read Data Posedge Delay Invert Refer to description of CLKDATWR_DLY_OFFSET Clock Read Command Line Delay Invert Refer to description of CLKDATWR_DLY_OFFSET Clock Data Write Line Delay Invert Data Write Delay offset. The highest bit indicates if it is add or sub. OFFSET [4]=0: CLKDATWR_DLY_VAL + OFFSET [3:0] OFFSET [4]=1: CLKDATWR_DLY_VAL – OFFSET [3:0]. If DLL_DATWR _CPST_EN==1, the offset is added after the proportion. E.g. If Clock cycle (CYC)== 5ns CLKDATWR _DLY_ VAL (VAL) ==’h40, CLKDATWR_DLY_OFFSET (OFSET) == ‘h6, DLL_CNT(CNT) == ‘h20 it means delay: (VAL/’h100)*CYC + (CYC * OFSET) / CN = (‘h40/’h100)*5ns + (5ns * ‘h6) / ‘h20 ≈2.2ns EMMC PHY DLL STS0 registers Reserved for vender asic only Reserved for vender asic only If use DLL, software should wait this value to 1’b1 If use DLL, soft ware should wait DLL_LOCKED to 1’b1 and at that time ,this bit is 1’b0 Reserved for vender asic only Reserved for vender asic only DLL delay cell counts of 1 cycle EMMC PHY DLL STS1 registers Reserved for vender asic only Reserved for vender asic only Reserved for vender asic only Reserved for vender asic only EMMC Buffer Processing System Low address EMMC Buffer Processing System High address EMMC Buffer Processing Block Count EMMC IO Processing Block Count EMMC Processing ADMA2 Low address EMMC Processing ADMA2 High address EMMC Processing ADMA3 Low address EMMC Processing ADMA3 High address EMMC Busy/CRC Status Position registers Control the Output clock SD_CLK auto gating 0: disable auto gating 1: enable auto gating Control the internal clock auto gating 0: disable auto gating 1: enable auto gating Reserved for vender asic only Reserved for vender asic only Reserved for vender asic only Master PROT attributes. It directly maps to the AXI master bus. AWPROT_emmc and ARPROT_emmc port. Control the Output enable of clock SD_CLK 0: Clock OE is 0 1: Clock OE is 1 Control the Input enable of clock SD_CLK, 0: Clock IE is 0 1: Clock IE is 1 CRC Status Position Force Enable 0: use default value 1: use CRCSTS_POSI value (Debug or designer set only) Read Busy Position Force Enable 0: use default value 1: use READ_BUSY_POSI value (Debug or designer set only) CRC Status Position Adjustment This register can adjust the sample position of CRC status, the need of this register is because of the HS200 or HS400 read data or CRC status may delay more cycles than legacy mode When CRCSTS_POSI_FORCE is set 1 this register is valid, else the actual value is used internal set value. Read Busy Position Adjustment This register can adjust the sample position of read busy, the need of this register is because of the HS200 or HS400 read data or CRC status may delay more cycles than legacy mode. When controller is read busy, the moment of stopping clock may be adjust through this register. When READ_BUSY_POSI_FORCE is set 1 this register is valid, else the actual value is used internal set value. EMMC CRC Error Status registers (Debug only) Bit[15] : Neg 7 Bit[14] : neg 6 Bit[13] : neg 5 Bit[12] : neg 4 Bit[11] : neg 3 Bit[10] : neg 2 Bit[9] : neg 1 Bit[8] : neg 0 Bit[7] : pos 7 Bit[6] : pos 6 Bit[5] : pos 5 Bit[4] : pos 4 Bit[3] : pos 3 Bit[2] : pos 2 Bit[1] : pos 1 Bit[0] : pos 0 The BIT[15:8] just used in DDR mode. EMMC FSM Debug0 register This bit indicate whether the pad clock is working or stop. 0: clock is stopped. 1: clock is working (Debug only) (Debug only) (Debug only) EMMC FSM Debug1 register (Debug only) (Debug only) (Debug only) (Debug only) EMMC FSM Debug2 register (Debug only) (Debug only) DLL USED BACKUP SIGNAL Oe_ext_optional( Reserved for vender asic only) Force slice en value( Reserved for vender asic only) Force slice enable( Reserved for vender asic only) Force dll use backup mode value( Reserved for vender asic only) Force dll use backup mode( Reserved for vender asic only) refclk_sel Input triger number count enable slave_mode trigger select auto preload value Center-aligned mode select 00: disable , other:enable counter dir , 0: cnt ++ , 1: cnt -- one pulse mode, 0:disable 1:enable update disable, 0:disable, 1:enable clock fdts didiver, 01: divided by 2 10:divided by 4, other:bypass counter enable, 0: disbale, 1:enable slave mode select: 100: slave mode, 101:gate mode, 110:trig mode, others disable bit type is changed from w1c to rc. user trigger gen no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[9] 0: output enable, 1 output disable bit[8] 0: use ti2, 1: use ti1 no used yet output compare mode: 000: freeze, 001: when cnt eq ccr, output1, 010: when cnt eq ccr, output1 011:,when cnt eq ccr, output reversal, 100: force 0, 101: force , 110, pwm mode1, 111, pwm mode2 compare value preload 0: disable, 1:enable no used yet channel source sel, bit[0] 0: output enable, 1 output disable bit[1] 0: use ti2, 1: use ti1 ti2 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti2 prescale, 01:0 div2, 10: div4, others: bypass ti1 filter , 0000:bypass, 0001:clk=pclk, N=2, 0010:clk=pclk, N=4, 0011:clk=pclk, N=8, ti1 prescale, 01:0 div2, 10: div4, others: bypass ti2 polarity ti2 enable ti1 polarity ti1 enable cnt_value cnt prescale value cnt max value ic1 capture value ic2 capture value ic1 compare value ic2 compare value cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode cnt reach max when dir = 0, cnt reach zeror when dir = 1 trig gens, when counter works in slave mode bit type is changed from w1c to rc. cnt reach max when dir = 0, cnt reach zeror when dir = 1 bit type is changed from w1c to rc. trig gens, when counter works in slave mode bit type is changed from w1c to rc. bit type is changed from w1c to rc. med_ch0_work_cfg 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch0; 0:disable ch0; med_ch0_base_addr_cfg the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 med_ch0_addr_size_cfg the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF med_ch0_read_addr_remap the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 med_ch1_work_cfg 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch1; 0:disable ch1; med_ch1_base_addr_cfg the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 med_ch1_addr_size_cfg the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF med_ch1_read_addr_remap the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 med_ch2_work_cfg 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch2; 0:disable ch2; med_ch2_base_addr_cfg the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 med_ch2_addr_size_cfg the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF med_ch2_read_addr_remap the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 med_ch3_work_cfg 1:bypass enable,don't encryption & decryption 0:bypass disable,do encryption & decryption 1:enable ch3; 0:disable ch3; med_ch3_base_addr_cfg the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 med_ch3_addr_size_cfg the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF med_ch3_read_addr_remap the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu read address is 0x1000_0024,then after med , then address is is 0x2000_0024 med_write_addr_remap the address only config the 32byte align addr, the low 5bit addr come from the med accept martix addr; for example, the reg config is 0x100_000,cpu write address is 0x1000_0024,then after med , then address is is 0x2000_0024 med_write_base_addr_cfg the base address must 32byte align, then the addr can delete the low 5bit; for example, base addr is 0x1000_0000, soft ware can config 0x80_0000 med_write_addr_size_cfg the size only support max 16MB, and must 32byte align, then the size value can delete the low 5bit; for example, size is 1MB,0xFFFFF, then soft ware can config is 0x7FFF med_clr 1:active,clear the 0x118 address bit31~bit12; 1:active,clear the simon core 1:active,clear the med inner write ram 1:active,clear the med inner read ram med_work_mode can force the med clk gate always on, then the clk freerun when the med send cmd to write flash data, and the slave happen bus error, then the med will back the slave bus error to master. when the med send cmd to read flash data, and the slave happen bus error, then the med will back the slave bus error to master. enable the med module ahb bus error,when the master access to med, and the access address is error, the med will generate the buss error to master. 1:sel the key from efuse, 0: key from soft ware med_int_en enable med ahb addr out of range all channel enable med error response int enable med channel3 addr error int enable med channel2 addr error int enable med channel1 addr error int enable med channel0 addr error int enable med write done int emd_int_raw med ahb addr out of range all channel status med error response int status med channel3 addr error int status med channel2 addr error int status med channel1 addr error int status med channel0 addr error int status med write done int status med_int_clear clear med ahb addr out of range all channel status clear med error response int clear med channel3 addr error int clear med channel2 addr error int clear med channel1 addr error int clear med channel0 addr error int clear med write done int med_error_addr med_status0 med_status1 med_status2 med_status3 med_soft_key Transmit word or Receive word Write data to this address initiates a character transmission through TX FIFO Read this address retrieve data from RX fifo Clock divisor Clock divisor bit 0 to 15 Specify the clock ratio between spi_sck and clk_spi. If clk_spi runs at 48 MHz, and spi_sck runs at 12MHz, SPI_CLKD should be 1, spi_sck = clk_spi/2(n+1). If IS_FST bit is assert, the valid SPI_CLKD is 0, 1, 2 and 3. Configure register This register is used to configuration of the SPI interface Sync_polarity, positive or negative pulse for SPI or 3-wire mode ,read command polarity “1” : sync mode “1” : spi_sck reverse 1 bit chip select. “0”: cs0 is valid “1”: cs0 is invalid In default, The input data is shifted high order first into the chip; the output data is shifted out high order first from the Most Significant Bit (MSB) on SO. When this bit is set, the data will be shift out or in from the LSB Transmit data bit number. “0” : 32 bits per word “1” : 1 bits per word … “31”: 31 bits per word “1” enable TX data shift out at clock neg-edge “1” enable RX data shift in at clock neg-edge Configure register This register is used to configuration of the SPI interface “00” : default(follow before version) “01” : spi do stay 0 value when in idle “10” : spi do stay 1 value when in idle “11” : spi do stay last-bit value when in idle 1:is tx mode 0:not tx mode 1:is rx mode 0:not rx mode S8 CD or SYNC signal maps to csn number “0x0001” selects csn0 as cd signal “0x0010” selects csn1 as cd signal In SPI_HS it must be 0x0000 and disable sync and s8 mode “1” : enable S8 mode 3-wire Melody timing 1, csn high mode enable “1” : enable 3-wire mode 3-wire mode, w/r control position or the sync pulse position(the pulse will locates on top of bit N) Configure register This register is used to configuration of the SPI interface 0:DMA TX and RX REQ independent 1:DMA TX REQ are depended on RX REQ status 0: tx_dma_req keep 1 until receiving the tx_dma_ack 1: tx_dma_req is “1” when tx_empty is “1”,else “0” 0: rx_dma_req keep 1 until receiving the rx_dma_ack 1: rx_dma_req is “1” when rx_full is “1”,else “0” “0” : working on only receive mode, when rxf_realfull is high, SPI will be held until rxf_realfull is low “1” : no holding “1” enable DMA mode “0” : master “1” : slave, only support microplus mode Read data start bit, used for 3 wire mode and 3 wire 9bit RW mode. The 3 wire 9bit RW mode reuse this config registers, it indicated read data start position. RXF watermark SPI RX FIFO FULL/EMPTY watermark Receive FIFO data empty threshold. Relative with rx_fifo_empty interrupt Receive FIFO data full threshold. Relative with rx_fifo_full interrupt Configure register This register is used to configuration of the SPI interface working in only receive mode, “0” : SPI send all 0 to slave “1” : SPI send all 1 to slave “0” : normal mode “1” : fast mode Both for matser mode and slave mode,and in master mode SPI_SCK must be quicker than 1/8 spi_clk Phase delay. Relate to fast mode. When in normal mode, this bit is not used . Only used for slave mode “1” Mask out the first clock pulse in SPI mode Sync_half, sync width is half spi_sck cycle “1”:receive data only. The bit should be written at last. Only used for master mode Number of data words ready to receive in “receive only” mode. Only used for master mode. Configure register This register is used to configuration of the SPI interface For master, transmit data interval, programmable n from 0 to 65535, delay is (n*4+3) clock cycle. For slave, max receive data interval. If the slave has not sampled the edge of spi_clk in the interval(n*4+3), slave will stop the receive process and send timout interrupt Interrupt enable SPI interrupt enable register Rx end interrupt enable Tx end interrupt enable txf_empty interrupt enable Rxf_full interrupt enable Slave mode timeout interrupt enable Rx_overrun_reg interrupt enable Tx_fifo_full interrupt enable Rx_fifo_empty interrupt enable Rx_fifo_full interrupt enable Interrupt clear SPI interrupt clear register Rx data end interrupt clear Tx data end interrupt clear Write “1” clear slave mode timeout interrupt Write “1” clear Rx_overrun_reg interrupt Write “1” clear Tx_fifo_empty interrupt Write “1” clear Tx_fifo_full interrupt Write “1” clear Rx_fifo_empty interrupt Write “1” clear Rx_fifo_full interrupt Raw status SPI interrupt raw status Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. Raw txf_empty interrupt, This bit is set when the number of tx fifo data byte is less than the tx empty watermark value. Auto cleared when the condition disappears. Raw rxf_full interrupt.This bit is set when the number of rx fifo data byte is larger than the rx full watermark value. Auto cleared when the condition disappears. Raw slave mode time out interrupt Raw Rx_overrun_reg interrupt Txf_empty_w(for debug) Raw Tx_fifo_full interrupt Raw rx_fifo_empty interrupt Rxf_full_r(for debug) Mask status SPI interrupt mask status Raw rx data end interrupt, this bit is set when spi controller received RX_DATA_LEN data from slave. Raw tx data end interrupt,this bit is set when spi controller send TX_DATA_LEN data. Txf_empty interrupt mask status. Rxf_full interrupt mask status. Slave mode time out interrupt mask status Rx_overrun_reg interrupt mask status Tx_fifo_full interrupt mask status Rx_fifo_empty interrupt mask status RXF address SPI RX FIFO write address and read address RX FIFO write address RX FIFO read address latch SPI status SPI status register Spi_cs(for debug) Spi_sck(for debug) Spi_txd(for debug) Spi_rxd(for debug) “1” transmit process “0” idle state TX FIFO has no data TX FIFO is real full. (not relates to TX full threshold) RX FIFO has no data RX FIFO is real full. (not relates to TX full threshold) This bit is set when the number of TX FIFO data byte is less than the TX empty interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of TX FIFO data byte is larger than the TX full interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of RX FIFO data byte is less than the RX empty interrupt watermark value. Auto cleared when the condition disappears. This bit is set when the number of RX FIFO data byte is larger than the RX full interrupt watermark value. Auto cleared when the condition disappears. DSP Register This register is used for DSP control Write data switch. 2’b0: WDATA=PDATA; 2’b1: WDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; 2’b2: WDATA={PDATA[15:0],PDATA[31:16]}; 2’b3: WDATA={PDATA[23:16], PDATA[31:24], PDATA[7:0], PDATA[15:8]}; Read data switch. 2’b0: RDATA=PDATA; 2’b1: RDATA={PDATA[7:0], PDATA[15:8], PDATA[23:16], PDATA[31:24]}; 2’b2: RDATA={PDATA[15:0],PDATA[31:16]}; This register is used for DSP control RX conunter monitor This register is used to observe the status working in only receive mode as master TXF configuration This register is used to configuration of the SPI interface TX FIFO data empty threshold. Relative with rx_fifo_empty interrupt TX FIFO data full threshold. Relative with rx_fifo_full interrupt TXF address This register is used to configuration of the SPI interface TX FIFO write address TX FIFO read address FIFO reset configuration Used to reset TX/RX FIFO “1” : reset all FIFOs. FIFO address will changed to 0 Configure register This register is used to configuration of the SPI interface 1: two data line function enable 0: two data line function disable 1: enable RGB565 data format 0: disable RGB565 data format 1: enable RGB666 data format 0: disable RGB666 data format 1: enable RGB888 data format 0: disable RGB888 data format 1: SPI slave in Low speed mode 0: SPI slave in High speed mode Used when SPI slave in High speed mode. 1: enable spi slave rtx 0: disable spi slave rtx Use for 3 wire 9bit RW mode and 4 wire 8bit RW mode (SPI_MODE=5 or SPI_MODE=6). 0: Data in and data out of SPI share one IO (SDA). 1: Data in and data out of SPI use separated IO (SDI, SDO). 1: enable ahb2apb bridge read hold when rx fifo empty 0: disable ahb2apb bridge read hold 1: enable ahb2apb bridge write hold when tx fifo full 0: disable ahb2apb bridge write hold 1: select fmark as the dma request 0: select software dma request Used for master only 0: SPI_MODE disable 1: 3 wire 9 bit, cd bit, SDI/SDO share one IO 2: 3 wire 9 bit, cd bit, SDI, SDO 3: 4 wire 8 bit, cd pin, SDI/SDO share one IO 4: 4 wire 8 bit, cd pin, SDI, SDO 5: 3 wire 9bit RW mode, 9 bit command and 8 bit read data, cd bit is enable. Design for LCD driver. 6: 4 wire 8bit RW mode, 8bit command and 8 bit read data. Use CD PAD indicates command or data. Design for LCD driver. CSN select control: 0: CSN 0 1: CSN 1 2: CSN 2 3: CSN 3 CSN IE output set(only slave) 0: not support csn input 1: support csn intput Statue Register Used to observe csn error 1: indicates csn occurring a exception csn for slave Configure Register Used for configure SPI interface Spi tx cd bit: 0: indicates command 1: indicates data Use for 4 wire 8bit RW mode. Determine CD PAD high or low in read data phase. Second data line of two data line function select bit: 0: CD PAD as second data line 1: DI PAD as second data line Two data line RGB data format mode: 0: 1pixel mode 1: 2/3 pixel mode 2-data-line switch. Only valid in 2-data-line mode(DATA_LINE2_EN set to 1): 0: use spi_do as first data line,spi_di as second data line. 1: use spi_di as first data line, spi_do as second data line. Spi tx dummy clock length Indicates tx data length from tx fifo, High 4 bits of spi tx data length Configure register This register is used to configuration of the SPI interface Indicates: spi tx data length from tx fifo, Low 16bit of tx data length Configure register SPI status register Spi rx dummy clock length Indicates receives data length from slave, high 4 bits of spi rx data length Configure register This register is used to configuration of the SPI interface Indicates: spi receives data length from slave, Low 16bit of rx data length Configure register This register is used to configuration of the SPI interface Software TX data request, for write LCD Software RX data request, for read LCD Statue Register Used to observe TX data counter Tx data cnt Statue Register Used to observe TX statue tx dummy counter tx data counter Statue Register Used to observe RX data counter Rx data cnt Statue Register Used to observe RX statue rx dummy counter rx data counter Statue Register Used to observe spi version Spi version protocol_version Protocol Type Protocol Subtype Beacon Destination address high Beacon Source address high BSSID address high Beacon sequence control Wlan rssi value RX mode enable signal,0:enable,1:disable beacon type,should be 00 beacon type,should be 1000 hold enable from apb,0:disable,1:enable,wlan interrupt can only be cleared by software when this bit set 1 and the walue of registers is kept until the interrupt is cleared Wlan rssi value data receive ready interrupt Beacon frame control Beacon duratin Beacon interval Beacon Capbility information Beacon SSID Elment ID Beacon SSID length patch_addrs00地址对应的patch功能使能 对ROM地址patch_addrs00进行读写时转换到RAM的固定地址中（0x10100000-0x1010000f） patch_addrs01地址对应的patch功能使能 对ROM地址patch_addrs01进行读写时转换到RAM的固定地址中（0x10100010-0x1010001f） patch_addrs02地址对应的patch功能使能 对ROM地址patch_addrs02进行读写时转换到RAM的固定地址中（0x10100020-0x1010002f） patch_addrs03地址对应的patch功能使能 对ROM地址patch_addrs03进行读写时转换到RAM的固定地址中（0x10100030-0x1010003f） patch_addrs04地址对应的patch功能使能 对ROM地址patch_addrs04进行读写时转换到RAM的固定地址中（0x10100040-0x1010004f） patch_addrs05地址对应的patch功能使能 对ROM地址patch_addrs05进行读写时转换到RAM的固定地址中（0x10100050-0x1010005f） patch_addrs06地址对应的patch功能使能 对ROM地址patch_addrs06进行读写时转换到RAM的固定地址中（0x10100060-0x1010006f） patch_addrs07地址对应的patch功能使能 对ROM地址patch_addrs07进行读写时转换到RAM的固定地址中（0x10100070-0x1010007f） patch_addrs08地址对应的patch功能使能 对ROM地址patch_addrs08进行读写时转换到RAM的固定地址中（0x10100080-0x1010008f） patch_addrs09地址对应的patch功能使能 对ROM地址patch_addrs09进行读写时转换到RAM的固定地址中（0x10100090-0x1010009f） patch_addrs10地址对应的patch功能使能 对ROM地址patch_addrs10进行读写时转换到RAM的固定地址中（0x101000a0-0x101000af） patch_addrs11地址对应的patch功能使能 对ROM地址patch_addrs11进行读写时转换到RAM的固定地址中（0x101000b0-0x101000bf） patch_addrs12地址对应的patch功能使能 对ROM地址patch_addrs12进行读写时转换到RAM的固定地址中（0x101000c0-0x101000cf） patch_addrs13地址对应的patch功能使能 对ROM地址patch_addrs13进行读写时转换到RAM的固定地址中（0x101000d0-0x101000df） patch_addrs14地址对应的patch功能使能 对ROM地址patch_addrs14进行读写时转换到RAM的固定地址中（0x101000e0-0x101000ef） patch_addrs15地址对应的patch功能使能 对ROM地址patch_addrs15进行读写时转换到RAM的固定地址中（0x101000f0-0x101000ff） patch_addrs16地址对应的patch功能使能 对ROM地址patch_addrs16进行读写时转换到RAM的固定地址中（0x10100100-0x1010010f） patch_addrs17地址对应的patch功能使能 对ROM地址patch_addrs17进行读写时转换到RAM的固定地址中（0x10100110-0x1010011f） patch_addrs18地址对应的patch功能使能 对ROM地址patch_addrs18进行读写时转换到RAM的固定地址中（0x10100120-0x1010012f） patch_addrs19地址对应的patch功能使能 对ROM地址patch_addrs19进行读写时转换到RAM的固定地址中（0x10100130-0x1010013f） patch_addrs20地址对应的patch功能使能 对ROM地址patch_addrs20进行读写时转换到RAM的固定地址中（0x10100140-0x1010014f） patch_addrs21地址对应的patch功能使能 对ROM地址patch_addrs21进行读写时转换到RAM的固定地址中（0x10100150-0x1010015f） patch_addrs22地址对应的patch功能使能 对ROM地址patch_addrs22进行读写时转换到RAM的固定地址中（0x10100160-0x1010016f） patch_addrs23地址对应的patch功能使能 对ROM地址patch_addrs23进行读写时转换到RAM的固定地址中（0x10100170-0x1010017f） patch_addrs24地址对应的patch功能使能 对ROM地址patch_addrs24进行读写时转换到RAM的固定地址中（0x10100180-0x1010018f） patch_addrs25地址对应的patch功能使能 对ROM地址patch_addrs25进行读写时转换到RAM的固定地址中（0x10100190-0x1010019f） patch_addrs26地址对应的patch功能使能 对ROM地址patch_addrs26进行读写时转换到RAM的固定地址中（0x101001a0-0x101001af） patch_addrs27地址对应的patch功能使能 对ROM地址patch_addrs27进行读写时转换到RAM的固定地址中（0x101001b0-0x101001bf） patch_addrs28地址对应的patch功能使能 对ROM地址patch_addrs28进行读写时转换到RAM的固定地址中（0x101001c0-0x101001cf） patch_addrs29地址对应的patch功能使能 对ROM地址patch_addrs29进行读写时转换到RAM的固定地址中（0x101001d0-0x101001df） patch_addrs30地址对应的patch功能使能 对ROM地址patch_addrs30进行读写时转换到RAM的固定地址中（0x101001e0-0x101001ef） patch_addrs31地址对应的patch功能使能 对ROM地址patch_addrs31进行读写时转换到RAM的固定地址中（0x101001f0-0x101001ff） pagespy功能使能 监控读操作使能 监控写操作使能 pagespy监控的开始地址 pagespy监控的结束地址 pagespy功能使能 监控读操作使能 监控写操作使能 pagespy监控的开始地址 pagespy监控的结束地址 pagespy功能使能 监控读操作使能 监控写操作使能 pagespy监控的开始地址 pagespy监控的结束地址 pagespy功能使能 监控读操作使能 监控写操作使能 pagespy监控的开始地址 pagespy监控的结束地址 pagespy返回的标志位，监控地址段内产生读或写操作时为1 监控地址段内产生读操作时为1 监控地址段内产生写操作时为1 返回该读或写操作的CPU的ID号 pagespy返回的标志位，监控地址段内产生读或写操作时为1 监控地址段内产生读操作时为1 监控地址段内产生写操作时为1 返回该读或写操作的CPU的ID号 pagespy返回的标志位，监控地址段内产生读或写操作时为1 监控地址段内产生读操作时为1 监控地址段内产生写操作时为1 返回该读或写操作的CPU的ID号 pagespy返回的标志位，监控地址段内产生读或写操作时为1 监控地址段内产生读操作时为1 监控地址段内产生写操作时为1 返回该读或写操作的CPU的ID号 raw interrupt status Register raw interrupt status Register interrupt enable Register interrupt enable Register masked interrupt status Register masked interrupt status Register interrupt clear Register interrupt clear Register tempurature control register tempurature control register 1: frac freq div mode 0: integer freq div mode 1: ext osc static mode 0: ext tsx static mode 1: sw config ,ext tsx/osc static mode 0: ext tsx/osc swtich mode 1: External OSC option 0: Internal OSC option 0:hardware mode 1:software mode osc left shift control of tempurature offset left shift control of tempurature offset 1:first do OSC 0:first do TSX 1: switch osx tsx enable 0: switch osx tsx disable 1: OSC option 0: TSX option 1: External TSX option 0: Internal TSX option 1: enable osc internal thermal ADS synchronous reset 1: sample the osc adc data at the posedge of adc clock 0: sample the osc dac data at the negedge of adc clock 1: enable internal thermal ADS synchronous reset 1: sample the adc data at the posedge of adc clock 0: sample the dac data at the negedge of adc clock enable the osc filter filter in the calculation(update) enable the tsx filter filter in the calculation(update) enable the thermal ADC data dump to Memory enable the osc calcualtion of tempurature compensation enable the tsx calcualtion of tempurature compensation the length of intergration the length of intergration the length of intergration the coef0 of frequency calculation the coef1 of frequency calculation c0 of frequency bias calculation the coef1 of frequency calculation the coef2 of frequency calculation c0 of frequency bias calculation the coef2 of frequency calculation the coef3 of frequency calculation c2of frequency bias calculation the coef3 of frequency calculation the coef4 of frequency calculation c0 of frequency bias calculation the reserved register of frequency calculation the reserved register of frequency calculation the configur register of external sigma-delta ADC over resampling the configur register of external sigma-delta ADC over resampling external TSX over resampling output divider clk second inverse position. external TSX over resampling output divider clk initial inverse position. external TSX over resampling resampling ration over origin signma delta ADC working clk frequency. For example, the origin sampling clk and resmapling clk is 6.5M and 26M, and the ratio is 4 .then the value of this register should be ration-1 =3. external TSX over resampling first pulse generate postion in delay chain. Typital is 1 external TSX over resampling best sampling positon . external TSX over resampling output divider clk init value. external TSX over resampling delay chain sync mode select. 1: high first 0: low first external TSX over resampling work enable offset of osc frequency calculation offset of osc frequency calculation offset of osc frequency calculation the coef0 of osc frequency calculation the coef1 of osc frequency calculation c0 of osc frequency calculation the freq bias cal val reg in software mode the freq bias cal val reg in software mode software calculation frequency bias update.Write to this reg will gen an plus. software calculation frequency bias the counter of frequency calculation done the counter of frequency calculation done the counter of tempurature calculation done the counter of tempurature calculation done the coef1 of osc frequency calculation the coef2 of osc frequency calculation c1 of osc frequency calculation the coef2 of osc frequency calculation the coef3 of osc frequency calculation c2 of osc frequency bias calculation the coef3 of osc frequency calculation the coef4 of osc frequency calculation c3 of osc frequency bias calculation switch ctrl switch ctrl osc_data_num tsx_data_num adc delay num the configur register of external sigma-delta ADC over resampling(frac freq div) the configur register of external sigma-delta ADC over resampling(frac freq div) external TSX/OSC over resampling output divider neg clk inverse position. external TSX/OSC over resampling output divider pos clk inverse position. external TSX/OSC over resampling first pulse generate postion in delay chain. Typital is 1 external TSX/OSC over resampling resampling ration over origin signma delta ADC working clk frequency. For example, the origin sampling clk and resmapling clk is 26/3.5M and 26M, and the ratio is 3.5 .then the value of this register should be ration*2-1 =6. 1: neg clk sample 0: pos clk sample external TSX/OSC over resampling delay chain sync mode select. 1: high first 0: low first external TSX/OSC over resampling work enable the status reg of frequency bias calculation the status reg of frequency bias calculation hardware calculation frequency bias update.Write to this reg will gen an plus hardware calculation frequency bias value the status reg of tempurature calculation the status reg of tempurature calculation hardware calculation frequency bias update.Write to this reg will gen an plus hardware integration value of calculation tempurature the status reg of frequency bias calculation the status reg of frequency bias calculation hardware calculation frequency bias update.Write to this reg will gen an plus hardware calculation frequency bias value the status reg of tempurature calculation the status reg of tempurature calculation hardware calculation frequency bias update.Write to this reg will gen an plus hardware integration value of calculation tempurature the status reg of tempurature calculation the status reg of tempurature calculation hardware calculation frequency bias update.Write to this reg will gen an plus hardware integration value of calculation tempurature osc_cal_post ctrl osc_cal_post ctrl osc_cal_post ctrl osc_cal_post ctrl 0 is osc_freq_bias_pre, 1 is osc_freq_bias_post t2reset_cnt th clear osc t2reset_cnt tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl 0 is tsx_freq_bias_pre, 1 is tsx_freq_bias_post clear osc t2reset_cnt tsx_cal_post ctrl tsx_cal_post ctrl t2reset_cnt th tsx_cal_post ctrl tsx_cal_post ctrl t2reset_cnt th tsx_cal_post ctrl tsx_cal_post ctrl t2reset_cnt th tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl tsx_cal_post ctrl freq_bias_rpt0 freq_bias_rpt0 freq_bias_rpt1 freq_bias_rpt1 freq_bias_rpt2 freq_bias_rpt2 freq_bias_rpt3 freq_bias_rpt3 freq_bias_rpt4 freq_bias_rpt4 1：cp cpu访问lte时软件控制的防挂死功能使能 1：cp cpu访问lte时防挂死功能由软件控制；0：由硬件控制 1：cp访问lte dma时软件控制的防挂死功能使能 1：cp访问lte dma时防挂死功能由软件控制；0：由硬件控制 1：cp访问psram时软件控制的防挂死功能使能 1：cp访问psram时防挂死功能由软件控制；0：由硬件控制 1：cp访问gnss时软件控制的防挂死功能使能 1：ifc2cp的异步桥auto gate使能 1：ifc发送数据到异步桥后，就可返回responds,把不可缓存的写操作视作可缓存的写操作 axi的wstrb（指示哪8bitS有效信号）转到ahb指示信号,作为AHB的awsparse信号 1：tsx_sclk的异步桥auto gate使能 1：tsx_mclk的异步桥auto gate使能 1：总线传数据到buffer，未从buffer输出完成，就可返回responds，把不可缓存的写操作视作可缓存的写操作 1：aon2cp_sclk的异步桥auto gate使能 1：aon2cp_mclk的异步桥auto gate使能 1：aon到cp传输数据到buffer，未从buffer输出完成，就可返回responds，把不可缓存的写操作视作可缓存的写操作 axi的wstrb（指示哪8bitS有效信号）转到ahb指示信号，作为AHB的awsparse信号 axi的wstrb（指示哪8bitS有效信号）转到ahb指示信号，作为AHB的awsparse信号 ifc写数据总线的优先级 ifc读数据总线的优先级 axidma写数据总线的优先级 axidma读数据总线的优先级 f8写数据总线的优先级 f8读数据总线的优先级 cp a5写数据总线的优先级 cp a5读数据总线的优先级 lte dma写数据总线的优先级 lte dma读数据总线的优先级 lte cpu写数据总线的优先级 lte cpu读数据总线的优先级 aon m写数据总线的优先级 aon m读数据总线的优先级 1：lpc_main的wakeup功能使能，无需等待外设的cactive信号便可唤醒时钟 1：s6的强制关闭总线使能打开，保证当前传输完成 1：s5的强制关闭总线使能打开，保证当前传输完成 1：s4的强制关闭总线使能打开，保证当前传输完成 1：s3的强制关闭总线使能打开，保证当前传输完成 1：s2的强制关闭总线使能打开，保证当前传输完成 1：s1的强制关闭总线使能打开，保证当前传输完成 1：s0的强制关闭总线使能打开，保证当前传输完成 1：main的强制关闭总线使能打开，保证当前传输完成 1：m4的强制关闭总线使能打开，保证当前传输完成 1：m3的强制关闭总线使能打开，保证当前传输完成 1：m2的强制关闭总线使能打开，保证当前传输完成 1：m1的强制关闭总线使能打开，保证当前传输完成 1：m0的强制关闭总线使能打开，保证当前传输完成 1:s6的控制低功耗使能打开 1:s5的控制低功耗使能打开 1:s4的控制低功耗使能打开 1:s3的控制低功耗使能打开 1:s2的控制低功耗使能打开 1:s1的控制低功耗使能打开 1:s0的控制低功耗使能打开 1:main的控制低功耗使能打开 1:m4的控制低功耗使能打开 1:m3的控制低功耗使能打开 1:m2的控制低功耗使能打开 1:m1的控制低功耗使能打开 1:m0的控制低功耗使能打开 m0退出低功耗模式后延迟几个cycle后打开clk m0总线没有传输后，等多少的cycle进入低功耗模式 · m1退出低功耗模式后延迟几个cycle后打开clk m1总线没有传输后，等多少的cycle进入低功耗模式 m2退出低功耗模式后延迟几个cycle后打开clk m2总线没有传输后，等多少的cycle进入低功耗模式 · m3退出低功耗模式后延迟几个cycle后打开clk m3总线没有传输后，等多少的cycle进入低功耗模式 m4退出低功耗模式后延迟几个cycle后打开clk m4总线没有传输后，等多少的cycle进入低功耗模式 · s0退出低功耗模式后延迟几个cycle后打开clk s0总线没有传输后，等多少的cycle进入低功耗模式 s1退出低功耗模式后延迟几个cycle后打开clk s1总线没有传输后，等多少的cycle进入低功耗模式 · s2退出低功耗模式后延迟几个cycle后打开clk s2总线没有传输后，等多少的cycle进入低功耗模式 s3退出低功耗模式后延迟几个cycle后打开clk s3总线没有传输后，等多少的cycle进入低功耗模式 · s4退出低功耗模式后延迟几个cycle后打开clk s4总线没有传输后，等多少的cycle进入低功耗模式 s5退出低功耗模式后延迟几个cycle后打开clk s5总线没有传输后，等多少的cycle进入低功耗模式 · s6退出低功耗模式后延迟几个cycle后打开clk s6总线没有传输后，等多少的cycle进入低功耗模式 1：clk_thm_osc时钟反向 1：clk_thm_tsx时钟反向 1：freq_bias的ch3时钟开启 1：freq_bias的ch2时钟开启 1：freq_bias的ch1时钟开启 1：freq_bias的ch0时钟开启 1：a5收到axi bresp和rresp时忽略 1：ifc总线respond返回error时忽略 1:wlan_iq使用同步后的信号；0：wlan_iq使用未作同步的信号 1：cgm_cp_ahb总线使能 1：cgm_cp_axi总线使能 1：cgm_cp_a5总线使能 1：cgm_cp_update的使能打开 1：cgm_cp_ahb分频的使能打开 1:cgm_cp_axi分频的使能打开 1：cgm_cp_axi选择哪个分频信号 1：freq_bias_ahb时钟打开；0：freq_bias_ahb时钟关闭 1：aon2cp_ahb时钟打开；0：aon2cp_ahb时钟关闭 1：cp_ahb_ifc时钟打开；0：cp_ahb_ifc时钟关闭APB Master use, can auto gate 1：cp_apb_ifc时钟打开；0：cp_apb_ifc时钟关闭APB DMA master use 1:dap时钟打开；0：dap时钟关闭 1：freq_bias_func时钟打开；0：freq_bias_func时钟关闭 1：wlan_11b时钟打开；0：wlan_11b时钟关闭 1：busmon_func时钟打开；0：busmon_func时钟关闭 1：sci2_func时钟打开；0：busmon时钟关闭 1：sci2_conf时钟打开；0：sci2_conf时钟关闭 1：sci2_mod时钟打开；0：sci2_mod时钟关闭 1：sci1_func时钟打开；0：sci1_func时钟关闭 1：sci1_conf时钟打开；0：sci1_conf时钟关闭 1：sci1_mod时钟打开；0：sci1_mod时钟关闭 1：timer3_mod时钟打开；0：timer3_mod时钟关闭 1：timer3_conf时钟打开；0：timer3_conf时钟关闭 1：timer4_mod时钟打开；0：timer4_mod时钟关闭 1：timer4_conf时钟打开；0：timer4_conf时钟关闭 1：sysram_conf时钟打开；0：sysram_conf时钟关闭 1：axidma时钟打开；0：axidma时钟关闭 1：ahb_ch3时钟打开；0：ahb_ch3时钟关闭 1：ahb_ch2时钟打开；0：ahb_ch2时钟关闭 1：ahb_ch1时钟打开；0：ahb_ch1时钟关闭 1：ahb_ch0时钟打开；0：ahb_ch0时钟关闭 1：ahb_ch_dbg时钟打开；0：ahb_ch_dbg时钟关闭 1：ahb_f8时钟打开；0：ahb_f8时钟关闭 1：ahb_irq1时钟打开；0：ahb_irq1时钟关闭 1：ahb_irq0时钟打开；0：ahb_irq0时钟关闭 1:clk_thm_osc_gen时钟打开；0：clk_thm_osc_gen时钟关闭 1:clk_thm_tsx_gen时钟打开；0：clk_thm_tsx_gen时钟关闭 1:clk_gnss_tsx_gen时钟打开；0：clk_gnss_tsx_gen时钟关闭 1:clk_gnss_tsx_mux时钟打开；0：clk_gnss_tsx_mux时钟关闭 1:clk_wcn_11b_adc_gen时钟打开；0：clk_wcn_11b_adc_gen时钟关闭 1:clk_wdg_32k_gen时钟打开；0：clk_wdg_32k_gen时钟关闭 1:clk_timer_26m_gen时钟打开；0：clk_timer_26m_gen时钟关闭 1:clk_wcn_11b_dfe_gen时钟打开；0：clk_wcn_11b_dfe_gen时钟关闭 1：rst_osc_26m通过软件复位 1：rst_tsx_ab_m通过软件复位 1:async_bridge_cp_soft_rst通过软件复位 1:cp_ltedma_async_soft_rst_to_lte通过软件复位 1:cp_ltecpu_async_soft_rst_to_lte通过软件复位 1：rst_cp2aon_aon通过软件复位 1：rst_cp2gnss_cp通过软件复位 1：rst_aon2cp_aon通过软件复位 1：rst_timer4_26m通过软件复位 1：rst_sci1通过软件复位 1：rst_sci2通过软件复位 1：rst_busmon_apb通过软件复位 1：rst_busmon_m0通过软件复位 1：rst_busmon_m1通过软件复位 1：rst_busmon_m2通过软件复位 1：rst_busmon_m3通过软件复位 1：rst_busmon_m4通过软件复位 1：rst_wlan_apb通过软件复位 1：rst_f8通过软件复位 1：rst_axidma通过软件复位 1：rst_imem_axi通过软件复位 1：rst_imem_apb通过软件复位 1：rst_timer3通过软件复位 1：rst_irq0通过软件复位 1：rst_irq1通过软件复位 1：rst_a5dbg通过软件复位 1：rst_a5cs通过软件复位 1：rst_a5通过软件复位 1:cp_axi的auto_gate使能 1:cp_a5的auto_gate使能 1:cp2freq_ahb的auto_gate使能 1:ifc2cp_ahb的auto_gate使能 1:aon2cp_ahb的auto_gate使能 1:cp_sci2的auto_gate使能 1:cp_sci1的auto_gate使能 1:cp_ifc的auto_gate使能 1:cp_ifc_ch3的auto_gate使能 1:cp_ifc_ch2的auto_gate使能 1:cp_ifc_ch1的auto_gate使能 1:cp_ifc_ch0的auto_gate使能 1:cp_ifc_ch_dbg的auto_gate使能 · 1:rst_cp_apbreg通过软件复位 cp ltecpu的trans idle信号，1：表示此模块监控地端口已经完成所有传输 cp ltecpu的pwr_handshk_clk_req信号 cp ltecpu的axi_detector_overflow信号 cp ltedma的trans idle信号，1：表示此模块监控地端口已经完成所有传输 cp ltedma的pwr_handshk_clk_req信号 cp ltedma的axi_detector_overflow信号 cp psram的trans idle信号，1：表示此模块监控地端口已经完成所有传输 cp psram的pwr_handshk_clk_req信号 cp psram的axi_detector_overflow信号 1:所有slave的deep_sleep使能打开 1:所有master的deep_sleep使能打开 1：cp的deep_sleep的ack信号 1：cp的light sleep使能关闭 1：s6的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s5的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s4的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s3的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s2的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s1的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：s0的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：main的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：m4的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：m3的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：m2的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：m1的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1：m0的lpc处于busy状态，lpc的输入时钟需要退出gated状态 1:s6已经进入低功耗模式 1:s5已经进入低功耗模式 1:s4已经进入低功耗模式 1:s3已经进入低功耗模式 1:s2已经进入低功耗模式 1:s1已经进入低功耗模式 1:s0已经进入低功耗模式 1:main已经进入低功耗模式 1:m4已经进入低功耗模式 1:m3已经进入低功耗模式 1:m2已经进入低功耗模式 1:m1已经进入低功耗模式 1:m0已经进入低功耗模式 1：s6 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s5 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s4 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s3 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s2 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s1 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：s0 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：main lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：m4 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：m3 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：m2 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：m1 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 1：m0 lpc进入Low_powe状态，且此时被lp_force强制维持在LP状态，知道lp_force=0 cp_dbg的monitor信号 master4占用总线信号 master4写占用总线信号 master4读占用总线信号 master3占用总线信号 master3写占用总线信号 master3读占用总线信号 master2占用总线信号 master2写占用总线信号 master2读占用总线信号 master1占用总线信号 master1写占用总线信号 master1读占用总线信号 master0占用总线信号 master0写占用总线信号 master0读占用总线信号 master4锁死 master3锁死 master2锁死 master1锁死 master0锁死 1:cp deep sleep请求不等待CP-A5进入WFI，强制force LPC 1:进入light sleep后，不管wlan是否有传输都进入light sleep功能 1:进入light sleep后，不管timer4是否有传输都进入light sleep功能 1:进入light sleep后，不管timer3是否有传输都进入light sleep功能 1:进入light sleep后，不管sci2是否有传输都进入light sleep功能 1:进入light sleep后，不管sci1是否有传输都进入light sleep功能 1:进入light sleep后，不管s6是否有传输都进入light sleep功能 1:进入light sleep后，不管s5是否有传输都进入light sleep功能 1:进入light sleep后，不管s4是否有传输都进入light sleep功能 1:进入light sleep后，不管s3是否有传输都进入light sleep功能 1:进入light sleep后，不管s2是否有传输都进入light sleep功能 1:进入light sleep后，不管s1是否有传输都进入light sleep功能 1:进入light sleep后，不管s0是否有传输都进入light sleep功能 1:进入light sleep后，不管m4是否有传输都进入light sleep功能 1:进入light sleep后，不管m3是否有传输都进入light sleep功能 1:进入light sleep后，不管m2是否有传输都进入light sleep功能 1:进入light sleep后，不管m1是否有传输都进入light sleep功能 1:进入light sleep后，不管m0是否有传输都进入light sleep功能 1:进入light sleep后，不管main_lpc是否有传输都进入light sleep功能 1:进入light sleep后，不管m4_lpc是否有传输都进入light sleep功能 1:进入light sleep后，不管m3_lpc是否有传输都进入light sleep功能 1:进入light sleep后，不管m2_lpc是否有传输都进入light sleep功能 1:进入light sleep后，不管m1_lpc是否有传输都进入light sleep功能 1:进入light sleep后，不管m0_lpc是否有传输都进入light sleep功能 1：cp的light sleep功能关闭 1：进入deep sleep后，cpu不再接收中断 wlan内部状态信号 wlan内部状态信号 wlan内部状态信号 wlan内部状态信号 main退出低功耗模式后延迟几个cycle后打开clk main总线没有传输后，等多少的cycle进入低功耗模式 1:cp可通过硬件传数据到rf_bitmap模块，且该模块的数据可以不通过总线直接传到cp 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，中间16bits【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，低16bits【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 Bitmap wptr写指针，软件latch使能后更新，判断到valid为1后有效 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，高16bits【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 AHB_EB0 NEW，clk_mtx_dump使能信号，GNSS dump数据处理模块使用 原L6第4bit，用于控制GNSS MTX时钟，下式中蓝色字体为该EB信号，cgm_gnss_mtx_en为MTX时钟使能信号： cgm_gnss_mtx_en = ~cp2gnss_lp_stat | gnss_mtx_en cp2gnss_lp_stat为CP-sys的LPC状态信号 NEW，RFAD_SPI模块功能时钟使能信号 NEW，RFAD_SPI模块总线时钟使能信号 原L6第8bit，PPS模块功能时钟使能信号 原L6第7bit，PPS模块总线时钟使能信号 原L6第6bit，RFT模块功能时钟使能信号 原L6第5bit，RFT模块总线时钟使能信号 NEW，GNSS2PSRAM异步桥LPC时钟使能信号 NEW，clk_top的总线时钟使能，最好不要关掉 GNSS_BB_enable NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE NOT CHANGE FUN_TEST_MODE NOT CHANGE AHB_SYS_CTL6 NOT CHANGE PLATFORM_ID PROJECT_ID DERIVED_ID NOT USE，Change the reset value NOT USE，Change the reset value MANUFACTURE_ID NOT USE，Change the reset value NOT USE，Change the reset value IMPLEMENTATION_ID NOT USE，Change the reset value NOT USE，Change the reset value CGM_EN_CTRL 原L6第8bit，GNSS_wrap RTC时钟使能 NEW，GNSS_wrap ADC时钟使能 NEW，GNSS_wrap bb_pp时钟使能 NEW, GNSS_wrap AE_clk使能信号 NEW，GNSS_wrap gnss_clk时钟使能 GNSS2PSRAM_LPC_CFG gnss2psram异步桥LPC的使能信号 LPC收到开时钟请求后，等待cycle数，一般保持默认不懂 LPC收到关时钟请求后，等待cycle数，一般保持默认不懂 GNSS2PSRAM_LPC_STATUS LPC状态信号，只读 GNSS2PSRAM_LPC_FORCE LPC的force信号，可以强制开关经过LPC的时钟 force_ack信号，只读 SOFT_RST NEW，dump逻辑的软复位信号，写1复位 原L6第20bit，GNSS_wrap的软复位，写1复位 原L6第19bit，RFT模块软复位，写1复位 原L6第4bit，PPS模块软复位，写1复位 NEW，LPC模块软复位，写1复位 NEW，RFAD_SPI软复位，写1复位 PWR_ON_RSTN_INDEX NOT CHANGE，外部低噪声放大器使能信号 RAM_EMA NOT CHANGE NOT USE FPGADEBUG SLEEP_STATUS NOT CHANGE AUTO_GATE_CTRL0 AUTO_GATE_CTRL1 AUTO_GATE_CTRL2 AUTO_GATE_CTRL3 AUTO_GATE_STATUS0 AUTO_GATE_STATUS1 AUTO_GATE_STATUS2 AUTO_GATE_STATUS3 LATCH_PULSE_NUM GNSS输出的RTC_latch与CPU_latch信号的脉冲拓宽配置，可根据同步时钟频率配置不同脉宽，也可以默认15 ADC_IQ_HOLD_SEL GNSS hold时需要将IQ数据切成0，需要RF-sys提供hold使能信号，该使能信号有同步和非同步两种方式，当该bit为1的时候选非同步方式，0即为同步后使能信号将IQ切成0 ASYNC_BRIDGE_DBG_SINGAL_W ASYNC_BRIDGE_DETECTOR_OVERFLOW 异步桥overflow状态信号，只读 GPS_COEXIST_IN GNSS_wrap的GPS共存信号 AXI_REG_SLICE_DS_FORCE AXI anti_hang功能 AXI anti_hang功能，默认选择dowm_sream_disable_force，写0表示选择AXI通路下游的ISO_EN AXI_REG_SLICE_DS_FORCE GNSS to PSRAM AWQOS config GNSS to PSRAM ARQOS config AXI_REG_SLICE_DS_FORCE AHB Anti_hang err resp en，active high，force to resp err cgm_gnss_mtx_sel_cfg clk_mtx_sel 0: 26m, 1: 62.5m, 2: 125m, 3: 133m, 4: 158m, 5:167m cgm_gnss_bb_pp_sel_cfg clk_bb_pp_sel not use cgm_gnss_adc_sel_cfg clk_adc_sel cgm_busy_src_monitor_cfg0 cgm_busy_monitor cgm_busy monitor SPI_CFG 0: write ; 1 : read 两次相邻操作，SE无效时最小时间，sclk时钟个数的一半 读分频系数：4 + FRQ_DIV_RD*2 读分频系数：4 + FRQ_DIV_WR*2 半双工读数据时片选信号反相使能 0：不反向；1：反相 双工模式选择，0：半；1：全 接受数据时模式选择 0：3线（只支持半双工读）；1：4线 SPI半双工读选择间隔第几个SPI时钟采样，default：2 读数据采样沿 0：相反沿采数据，与发送沿为反相沿（全双工时必须为0） 1：同沿采数据，与发送沿为同一沿 片选使能控制选择 0：片选在时钟之前有效（normal） 1：片选在时钟之后有效（DIG_RF） SPI时钟相位控制 0:数据采样发生在时钟奇数沿 1：数据采样发生在时钟偶数沿 SPI时钟极性控制 0：SPI接口在IDLE状态时，时钟为低电平； 1：SPI接口在IDLE状态时，时钟为高电平； SPI片选极性控制 0：SPI片选低有效 1：SPI片选高有效 SPI接收数据长度，default = 16bit SPI发送数据长度，default = 32bit SPI_RXDATA SPI_IMMDATA SPI_STATUS 1：SPI正在传输；0：传输完成 Reserved address for Power Pad control registers Power control pin[MS] for power [V_MMC_18_30] Power control pin[MSOUT] for power [V_MMC_18_30] Power control pin[MSEN] for power [V_MMC_18_30] Power control pin[MS] for power [V_LCD_18_33] Power control pin[MSOUT] for power [V_LCD_18_33] Power control pin[MSEN] for power [V_LCD_18_33] Power control pin[MS] for power [VDDIO_18_33] Power control pin[MSOUT] for power [VDDIO_18_33] Power control pin[MSEN] for power [VDDIO_18_33] Power control pin[MS] for power [VSIM0] Power control pin[MSOUT] for power [VSIM0] Power control pin[MSEN] for power [VSIM0] Power control pin[MS] for power [VSIM1] Power control pin[MSOUT] for power [VSIM1] Power control pin[MSEN] for power [VSIM1] Power control pin[MS] for power [VLPVDDIO1833_1] Power control pin[MSOUT] for power [VLPVDDIO1833_1] Power control pin[MSEN] for power [VLPVDDIO1833_1] Power control pin[MS] for power [LPVDDIO_18_33] Power control pin[MSOUT] for power [LPVDDIO_18_33] Power control pin[MSEN] for power [LPVDDIO_18_33] Global Pin control registers Global Pin control registers Global Pin control registers Global Pin control registers Global Pin control registers Global Pin control registers Pad u_RFDIG_GPIO_7 control Function Mode select 0: rf_gpio7 3: lte_gpo_8 Pad u_RFDIG_GPIO_6 control Function Mode select 0: rf_gpio6 3: lte_gpo_7 Pad u_RFDIG_GPIO_5 control Function Mode select 0: rf_gpio5 3: lte_gpo_5 Pad u_RFDIG_GPIO_4 control Function Mode select 0: rf_gpio4 3: lte_gpo_4 Pad u_RFDIG_GPIO_3 control Function Mode select 0: rf_gpio3 3: lte_gpo_3 Pad u_RFDIG_GPIO_2 control Function Mode select 0: rf_gpio2 3: lte_gpo_2 Pad u_u_RFDIG_GPIO_1 control Function Mode select 0: rffe_sda 1: rf_gpio1 3: lte_gpo_1 Pad u_RFDIG_GPIO_0 control Function Mode select 0: rffe_sck 1: rf_gpio0 3: lte_gpo_0 Pad u_KEYIN_4 control Function Mode select 0: keyin_4 1: gpio_8 2: pwm_0 3: pwm_4 4: i2c_m2_scl 6: debug_bus_12 7: uart_5_rxd Pad u_KEYOUT_5 control Function Mode select 0: keyout_5 1: gpio_11 2: pwm_3 3: uart_4_txd 7: uart_5_rts Pad u_KEYIN_5 control Function Mode select 0: keyin_5 1: gpio_9 2: pwm_1 3: pwm_5 4: i2c_m2_sda 7: uart_5_txd Pad u_KEYOUT_4 control Function Mode select 0: keyout_4 1: gpio_10 2: pwm_2 3: uart_4_rxd 7: uart_5_cts Pad u_UART_1_RTS control Function Mode select 0: uart_1_rts 1: pwm_3 2: pwm_11 3: uart_2_rxd 4: gpio_15 Pad u_UART_1_TXD control Function Mode select 0: uart_1_txd 1: gpio_13 Pad u_UART_1_RXD control Function Mode select 0: uart_1_rxd 1: gpio_12 Pad u_UART_1_CTS control Function Mode select 0: uart_1_cts 1: gpio_14 2: pwm_10 3: uart_2_txd Pad u_GPIO_0 control Function Mode select 0: gpio_0 1: spi_2_clk 3: uart_1_rxd 4: uart_3_rxd 5: pwm_8 6: debug_clk 7: uart_2_rxd Pad u_GPIO_3 control Function Mode select 0: gpio_3 1: spi_2_di_1 3: uart_1_rts 4: uart_4_txd 5: pwm_11 6: debug_bus_2 7: uart_2_rts Pad u_GPIO_2 control Function Mode select 0: gpio_2 1: spi_2_dio_0 3: uart_1_cts 4: uart_4_rxd 5: pwm_10 6: debug_bus_1 7: uart_2_cts Pad u_GPIO_1 control Function Mode select 0: gpio_1 1: spi_2_cs_0 3: uart_1_txd 4: uart_3_txd 5: pwm_9 6: debug_bus_0 7: uart_2_txd Pad u_GPIO_7 control Function Mode select 0: gpio_7 1: pwm_2 2: i2c_m2_sda 3: uart_6_txd 4: uart_3_txd Pad u_GPIO_6 control Function Mode select 0: gpio_6 1: pwm_1 2: i2c_m2_scl 3: uart_6_rxd 4: uart_3_rxd Pad u_GPIO_5 control Function Mode select 0: gpio_5 1: pwm_0 3: uart_5_txd 4: uart_3_rts 5: test_clkout 6: debug_bus_4 Pad u_GPIO_4 control Function Mode select 0: gpio_4 1: spi_2_cs_1 3: uart_5_rxd 4: uart_3_cts 5: pwm_12 6: debug_bus_3 Pad u_ADI_SDA control Function Mode select 0: ADI_SDA Pad u_ADI_SCL control Function Mode select 0: ADI_SCL Pad u_RESETB control Function Mode select 0: RESETB Pad u_OSC_32K control Function Mode select 0: OSC_32K Pad u_PMIC_EXT_INT control Function Mode select 0: PMIC_EXT_INT Pad u_CHIP_PD control Function Mode select 0: CHIP_PD Pad u_PTEST control Pad u_CLK26M_PMIC control Function Mode select 0: clk26m_pmic Pad u_SIM_1_RST control Function Mode select 0: sim_1_rst 1: gpio_32 2: pwm_6 Pad u_SIM_1_DIO control Function Mode select 0: sim_1_dio 1: gpio_31 2: pwm_5 Pad u_SIM_1_CLK control Function Mode select 0: sim_1_clk 1: gpio_30 2: pwm_4 Pad u_SIM_0_RST control Function Mode select 0: sim_0_rst Pad u_SIM_0_DIO control Function Mode select 0: sim_0_dio Pad u_SIM_0_CLK control Function Mode select 0: sim_0_clk Pad u_SW_CLK control Function Mode select 0: ap_jtag_tck 1: gpio_24 3: spi_1_clk 4: sdmmc2_clk 6: tsx_adc_ch_sel Pad u_SW_DIO control Function Mode select 0: ap_jtag_tms 1: gpio_25 3: spi_1_cs_0 4: sdmmc2_cmd 6: tsx_adc_clk Pad u_DEBUG_HOST_TX control Function Mode select 0: ap_jtag_tdo 1: gpio_27 2: debug_host_tx 3: spi_1_di_1 4: sdmmc2_data_1 6: osc_adc_clk Pad u_DEBUG_HOST_RX control Function Mode select 0: ap_jtag_tdi 1: gpio_26 2: debug_host_rx 3: spi_1_dio_0 4: sdmmc2_data_0 6: tsx_adc_ch_data Pad u_DEBUG_HOST_CLK control Function Mode select 0: ap_jtag_trst 1: gpio_28 2: debug_host_clk 3: spi_1_cs_1 4: sdmmc2_data_2 6: osc_adc_data Pad u_CAMERA_RST_L control Function Mode select 0: camera_rst_l 1: pwm_6 2: i2c_m3_scl 3: gpio_44 6: debug_bus_2 8: DBG_DO_11 Pad u_SPI_CAMERA_SCK control Function Mode select 0: spi_camera_sck 1: pwm_9 2: gpio_18 3: aud_da_d1 6: debug_bus_7 Pad u_SPI_CAMERA_SI_1 control Function Mode select 0: spi_camera_si_1 1: i2c_m2_sda 2: spi_camera_si_0 3: spi_camera_ssn 6: debug_bus_6 Pad u_SPI_CAMERA_SI_0 control Function Mode select 0: spi_camera_si_0 1: i2c_m2_scl 2: spi_camera_si_1 3: gpio_47 6: CTS 8: DBG_CLK Pad u_CAMERA_REF_CLK control Function Mode select 0: camera_ref_clk 1: pwm_8 2: gpio_46 6: debug_bus_4 8: DBG_TRIG Pad u_CAMERA_PWDN control Function Mode select 0: camera_pwdn 1: pwm_7 2: i2c_m3_sda 3: gpio_45 6: debug_bus_3 7: GPADC_IN3 8: DBG_DO_12 Pad u_I2S_SDAT_I control Function Mode select 0: i2s1_sdat_i 1: pwm_10 2: gpio_21 3: aud_ad_d0 4: i2c_m3_scl 8: DBG_DO_15 Pad u_I2S1_SDAT_O control Function Mode select 0: i2s1_sdat_o 1: pwm_11 2: gpio_22 3: aud_sclk 4: i2c_m3_sda Pad u_I2S1_LRCK control Function Mode select 0: i2s1_lrck 1: i2c_m3_sda 2: gpio_20 3: aud_ad_sync 8: DBG_DO_14 Pad u_I2S1_BCK control Function Mode select 0: i2s1_bck 1: i2c_m3_scl 2: gpio_19 3: aud_da_d0 8: DBG_DO_13 Pad u_I2S1_MCLK control Function Mode select 0: i2s1_mclk 1: gpio_46 Pad u_I2C_M2_SCL control Function Mode select 0: i2c_m2_scl 1: pwm_4 2: gpio_42 3: aud_da_sync 6: debug_bus_0 8: DBG_DO_9 Pad u_I2C_M2_SDA control Function Mode select 0: i2c_m2_sda 1: pwm_5 2: gpio_43 3: aud_da_d1 6: debug_bus_1 8: DBG_DO_10 Pad u_Nand_sel control Function Mode select 0: Nand_sel Pad u_KEYOUT_3 control Function Mode select 0: keyout_3 1: gpio_35 3: i2c_m1_sda 6: debug_clk Pad u_KEYOUT_2 control Function Mode select 0: keyout_2 1: gpio_34 3: i2c_m1_scl 6: debug_bus_15 Pad u_KEYOUT_1 control Function Mode select 0: keyout_1 1: gpio_33 2: uart_6_txd 3: pwm_7 6: debug_bus_14 Pad u_KEYOUT_0 control Function Mode select 0: keyout_0 1: gpio_32 2: uart_6_rxd 3: pwm_6 6: debug_bus_13 Pad u_KEYIN_3 control Function Mode select 0: keyin_3 1: gpio_31 2: uart_4_txd 6: debug_bus_11 Pad u_KEYIN_2 control Function Mode select 0: keyin_2 1: gpio_30 2: uart_4_rxd 6: debug_bus_10 Pad u_KEYIN_1 control Function Mode select 0: keyin_1 1: gpio_29 2: pwm_15 6: debug_bus_9 Pad u_KEYIN_0 control Function Mode select 0: keyin_0 1: gpio_28 2: pwm_14 6: debug_bus_8 Pad u_LCD_RSTB control Function Mode select 0: lcd_rstb 2: gpio_41 6: debug_bus_11 Pad u_LCD_FMARK control Function Mode select 0: lcd_fmark 1: spi_flash1_sio_3 2: gpio_40 6: debug_bus_10 7: GPADC_IN2 8: DBG_DO_8 Pad u_SPI_LCD_SELECT control Function Mode select 0: spi_lcd_select 1: spi_flash1_sio_2 2: gpio_39 6: debug_bus_9 8: DBG_DO_7 Pad u_SPI_LCD_CS control Function Mode select 0: spi_lcd_cs 1: spi_flash1_sio_1 2: gpio_38 6: debug_bus_8 8: DBG_DO_6 Pad u_SPI_LCD_CLK control Function Mode select 0: spi_lcd_clk 1: spi_flash1_sio_0 2: gpio_37 6: debug_bus_7 8: DBG_DO_5 Pad u_SPI_LCD_SDC control Function Mode select 0: spi_lcd_sdc 1: spi_flash1_cs 2: gpio_36 6: debug_bus_6 7: GPADC_IN1 8: DBG_DO_4 Pad u_SPI_LCD_SIO control Function Mode select 0: spi_lcd_sio 1: spi_flash1_clk 2: gpio_35 6: debug_bus_5 8: DBG_DO_3 Pad u_SDMMC1_RST control Function Mode select 0: SDMMC1_RST 1: gpio_36 Pad u_SDMMC1_DATA_7 control Function Mode select 0: SDMMC1_DATA_7 1: gpio_27 2: pwm_13 3: i2c_m2_sda 4: spi_1_cs_1 5: uart_4_txd 6: spi_flash1_sio_3 7: timestamp_out 8: dbgio_data7 Pad u_SDMMC1_DATA_6 control Function Mode select 0: SDMMC1_DATA_6 1: gpio_26 2: pwm_12 3: i2c_m2_scl 4: spi_1_di_1 5: uart_4_rxd 6: spi_flash1_sio_2 7: timestamp_in 8: dbgio_data6 Pad u_SDMMC1_DATA_5 control Function Mode select 0: SDMMC1_DATA_5 1: gpio_25 2: i2c_m1_sda 3: timestamp_out 4: spi_1_dio_0 5: uart_4_rts 6: spi_flash1_sio_1 7: PPS_OUT 8: dbgio_data5 Pad u_SDMMC1_DATA_4 control Function Mode select 0: SDMMC1_DATA_4 1: gpio_24 2: i2c_m1_scl 3: timestamp_in 4: spi_1_cs_0 5: uart_4_cts 6: spi_flash1_sio_0 7: Lna_en 8: dbgio_data4 Pad u_SDMMC1_DATA_3 control Function Mode select 0: SDMMC1_DATA_3 1: gpio_21 2: spi_camera_sck 3: pwm_15 4: spi_1_clk 5: uart_3_txd 6: spi_flash1_cs 8: dbgio_data3 Pad u_SDMMC1_DATA_2 control Function Mode select 0: SDMMC1_DATA_2 1: gpio_20 2: spi_camera_si_1 3: spi_camera_si_0 4: spi_2_cs_1 5: uart_3_rxd 6: spi_flash1_clk 8: dbgio_data2 Pad u_SDMMC1_DATA_1 control Function Mode select 0: SDMMC1_DATA_1 1: gpio_19 2: spi_camera_si_0 3: spi_camera_si_1 4: spi_2_di_1 5: uart_5_txd 6: uart_6_rts 8: dbgio_data1 Pad u_SDMMC1_DATA_0 control Function Mode select 0: SDMMC1_DATA_0 1: gpio_18 2: camera_ref_clk 3: i2c_m1_sda 4: spi_2_dio_0 5: uart_5_rxd 6: uart_6_cts 8: dbgio_data0 Pad u_SDMMC1_CMD control Function Mode select 0: SDMMC1_CMD 1: gpio_17 2: camera_pwdn 3: i2c_m1_scl 4: spi_2_cs_0 5: uart_2_txd 6: uart_6_txd 8: dbgio_cmd Pad u_SDMMC1_CLK control Function Mode select 0: SDMMC1_CLK 1: gpio_16 2: camera_rst_l 3: pwm_14 4: spi_2_clk 5: uart_2_rxd 6: uart_6_rxd 8: dbgio_clk Pad u_UART_2_RTS control Function Mode select 0: uart_2_rts 1: gpio_34 2: uart_2_rxd 3: i2c_m3_sda 4: uart_4_txd Pad u_UART_2_CTS control Function Mode select 0: uart_2_cts 1: gpio_33 2: uart_2_txd 3: i2c_m3_scl 4: uart_4_rxd Pad u_UART_2_TXD control Function Mode select 0: uart_2_txd 1: i2c_m1_sda 2: pwm_13 3: gpio_32 4: uart_3_txd Pad u_UART_2_RXD control Function Mode select 0: uart_2_rxd 1: i2c_m1_scl 2: pwm_12 3: gpio_31 4: uart_3_rxd Pad u_I2C_M1_SDA control Function Mode select 0: i2c_m1_sda 1: gpio_30 2: uart_4_txd 4: rf_gpio8 Pad u_I2C_M1_SCL control Function Mode select 0: i2c_m1_scl 1: gpio_29 2: uart_4_rxd 4: rf_gpio9 Pad u_GPIO_23 control Function Mode select 0: gpio_23 1: spi_flash1_sio_3 2: pwm_9 3: sdmmc2_data_3 4: rf_gpio8 Pad u_GPIO_22 control Function Mode select 0: gpio_22 1: spi_flash1_sio_2 2: spi_2_cs_1 3: sdmmc2_data_2 4: rf_gpio9 5: osc_adc_data Pad u_GPIO_21 control Function Mode select 0: gpio_21 1: spi_flash1_sio_1 2: spi_2_di_1 3: sdmmc2_data_1 5: osc_adc_clk Pad u_GPIO_20 control Function Mode select 0: gpio_20 1: spi_flash1_sio_0 2: spi_2_dio_0 3: sdmmc2_data_0 4: pwm_15 5: tsx_adc_ch_data Pad u_GPIO_19 control Function Mode select 0: gpio_19 1: spi_flash1_cs 2: spi_2_cs_0 3: sdmmc2_cmd 4: pwm_14 5: tsx_adc_clk Pad u_GPIO_18 control Function Mode select 0: gpio_18 1: spi_flash1_clk 2: spi_2_clk 3: sdmmc2_clk 4: pwm_13 5: tsx_adc_ch_sel 6: digrf_strobe_s_o Pad u_GPIO_17 control Function Mode select 0: gpio_17 1: uart_3_rxd 2: pwm_8 3: i2c_m3_sda 5: PPS_OUT 6: uart_2_rts Pad u_GPIO_16 control Function Mode select 0: gpio_16 1: uart_3_txd 2: pwm_7 3: i2c_m3_scl 4: sdmmc2_data_3 5: Lna_en 6: uart_2_cts Pad u_M_SPI_D_3 control Function Mode select 0: M_SPI_D_3 Pad u_M_SPI_D_2 control Function Mode select 0: M_SPI_D_2 Pad u_M_SPI_D_1 control Function Mode select 0: M_SPI_D_1 Pad u_M_SPI_D_0 control Function Mode select 0: M_SPI_D_0 Pad u_M_SPI_CS control Function Mode select 0: M_SPI_CS Pad u_M_SPI_CLK control Function Mode select 0: M_SPI_CLK Pad u_RFDIG_GPIO_7 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_6 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_5 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_4 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_3 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_2 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_u_RFDIG_GPIO_1 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RFDIG_GPIO_0 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_4 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_5 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_5 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_4 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_1_RTS control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_1_TXD control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_1_RXD control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_1_CTS control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_0 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_3 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_2 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_1 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_7 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_6 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_5 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_4 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_ADI_SDA control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_ADI_SCL control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_RESETB control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode Pad u_OSC_32K control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_PMIC_EXT_INT control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_CHIP_PD control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_PTEST control Pad u_CLK26M_PMIC control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_1_RST control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_1_DIO control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_1_CLK control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_0_RST control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_0_DIO control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SIM_0_CLK control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SW_CLK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SW_DIO control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_DEBUG_HOST_TX control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_DEBUG_HOST_RX control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_DEBUG_HOST_CLK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_CAMERA_RST_L control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_CAMERA_SCK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_CAMERA_SI_1 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_CAMERA_SI_0 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode Pad switch control, 1-->analog, 0-->digital 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_CAMERA_REF_CLK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_CAMERA_PWDN control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2S_SDAT_I control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2S1_SDAT_O control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2S1_LRCK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2S1_BCK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2S1_MCLK control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2C_M2_SCL control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2C_M2_SDA control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_Nand_sel control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_3 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_2 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_1 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYOUT_0 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_3 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_2 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_1 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_KEYIN_0 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_LCD_RSTB control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_LCD_FMARK control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_LCD_SELECT control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_LCD_CS control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_LCD_CLK control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_LCD_SDC control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SPI_LCD_SIO control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_RST control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_7 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_6 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_5 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_4 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_3 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_2 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_1 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_DATA_0 control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_CMD control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_SDMMC1_CLK control 'drv' control for normal mode 0: Driven strength 3mA 1: Driven strength 6mA 2: Driven strength 9mA 3: Driven strength 12mA 4: Driven strength 15mA 5: Driven strength 18mA 6: Driven strength 21mA 7: Driven strength 24mA 8: Driven strength 27mA 9: Driven strength 30mA 10: Driven strength 33mA 11: Driven strength 36mA 12: Driven strength 39mA 13: Driven strength 42mA 14: Driven strength 45mA 15: Driven strength 48mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_2_RTS control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_2_CTS control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_2_TXD control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_UART_2_RXD control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2C_M1_SDA control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_I2C_M1_SCL control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_23 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_22 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_21 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_20 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_19 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_18 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_17 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_GPIO_16 control 'drv' control for normal mode 0: Driven strength 2mA 1: Driven strength 4mA 2: Driven strength 6mA 3: Driven strength 8mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_D_3 control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_D_2 control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_D_1 control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_D_0 control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_CS control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode Pad u_M_SPI_CLK control 'drv' control for normal mode 0: Driven strength 4mA 1: Driven strength 9mA 2: Driven strength 13mA 3: Driven strength 18mA 4: Driven strength 22mA 5: Driven strength 27mA 6: Driven strength 32mA 7: Driven strength 39mA Sub-System deepsleep enable 'wpus' control for normal mode 'se' control for normal mode 'wpu' control for normal mode 'wpdo' control for normal mode 'wpu' control for deepsleep mode 'wpdo' control for deepsleep mode 'ie' control for deepsleep mode 'oe' control for deepsleep mode PWRCTRL_HWEN power domain shutdown/on controled by hardware signal or sofeware register. CP power domain control by: 0:software register 1:hardware signal from IDLE_LPS module AP power domain control by: 0:software register 1:hardware signal from IDLE_LPS module AP_PWR_CTRL Register control AP power domani on/off. AP power domain software register control bit 0:off 1:on CP_PWR_CTRL Register control CP power domani on/off. CP power domain software register control bit 0:off 1:on PUB_PWR_CTRL Register control PUB power domani on/off. PUB power domain whil be shutdown when bit[2:0]=2'b11,otherwise power on. PUB power domain poll register bit for CP A5 0:poll to power on 1:poll to shutdown PUB power domain poll register bit for AP A5 0:poll to power on 1:poll to shutdown RF_PWR_CTRL Register control RF power domani on/off. RF power domain software register control bit 0:off 1:on USB_PWR_CTRL Register control USB power domani on/off. USB power domain software register control bit 0:off 1:on LTE_PWR_CTRL Register control LTE power domani on/off. LTE power domain software register control bit 0:off 1:on GNSS_PWR_CTRL Register control GNSS power domani on/off. GNSS power domain software register control bit 0:off 1:on AP_PWR_STAT AP power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on CP power domain state. CP power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on PUB_PWR_STAT PUB power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on RF_PWR_STAT RF power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on USB_PWR_STAT USB power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on LTE_PWR_STAT LTE power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on GNSS_PWR_STAT GNSS power domain state. If power state is stable 0:not stable 1:stable Current power state of power domain 0:off 1:on STATE_DELAY Power domain control state machine delay value between two states. Power domain control state machine delay value between two states, counts with 26MHz clock. PD_M_DELAY Power switch mather chain delay value. Power switch mather chain delay value, counts with 26MHz clock. PD_D_DELAY Power switch daughter chain delay value. Power switch daughter chain delay value, counts with 26MHz clock. PSRAM_HOLD_CTRL Control latch the value of PSRAM IO from PSRAM controller. 0:not latch 1:latch SLP_BYPASS Control bypass the sleep handshake action when shutdown power domain. 0:not bypass 1:bypass 0:not bypass 1:bypass 0:not bypass 1:bypass 0:not bypass 1:bypass 0:not bypass 1:bypass 0:not bypass 1:bypass 0:not bypass 1:bypass SLP_TIMEOUT_FLAG Flag of power domain sleep handshake action timeout.Write "1" to clear relevant bit. 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur 0:timeout not occur 1:timeout occur PWRCTRL_INT_EN_AP 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output PWRCTRL_INT_EN_CP 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output 0:disable irq signal output 1:enable irq signal output PWRCTRL_SM_STATE The state value of the power domain state machine. 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state 4'h1:CLK_DISA 4'h2:ISO_HOLD 4'h3:RESET 4'h4:PREPON_REQ 4'h5:PWR_OFF 4'h6:PON_REQ 4'h7:ISO_RELEASE 4'h8:RST_RELEASE 4'h9:CLK_ENA 4'ha:PWR_ON 4'hb:PREPOFF_REQ 4'hc:POFF_REQ 4'hd:BUS_HANDSHAKE others:error state LPS_CTRL_AP AP sleep enable register(Enable AP sleep when writing 0x49444c45 to this register, accessed by software only.) Enable AP sleep 0:disable 1:enable AP_SIG_EN signal of low power related enable register ap_pow_on_en ctrl 1:enable 0:disable ap_cg_en ctrl 1:enable 0:disable ap_pd_pll_en ctrl 1:enable 0:disable ap_pd_xtal_en ctrl 1:enable 0:disable ap_chip_pd_en ctrl 1:enable 0:disable AP_LPS_SIG_TIME low power related time control register The time from enable clock to obtain clock The time of PLL from power saving state to output normal clock. The time of OSC circuit from power saving state to normal state. The time of PMIC boost stabilization. LPS_CTRL_CP CP sleep enable register(Enable CP sleep when writing 0x49444c45 to this register, accessed by software only.) Enable CP sleep 0: disable 1: enable CP_PM2_STA mark pm2 pm2 sta 1:PM2 valid 0:PM2 invalid CP_SIG_EN signal of low power related enable register cp_pow_on_en ctrl 1:enable 0:disable cp_cg_en ctrl 1:enable 0:disable cp_pd_pll_en ctrl 1:enable 0:disable cp_pd_xtal_en ctrl 1:enable 0:disable cp_chip_pd_en ctrl 1:enable 0:disable CP_LPS_SIG_TIME low power related time control register The time from enable clock to obtain clock The time of PLL from power saving state to output normal clock. The time of OSC circuit from power saving state to normal state. The time of PMIC boost stabilization. PM2_OFF_TIME low power related time control register Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. AON_CLOCK_EN0 low power related time control register Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. PM2_ON_OFF_TIME low power related time control register Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. Power domain control state machine delay value between two states, counts with 32KHz clock. AP_PM2_STA mark pm2 pm2 sta 1:PM2 valid 0:PM2 invalid AP_PM2_MODE_EN AP PM2 enable AP enable PM2 mode 0:enable PM2 mode 1:disable PM2 mode AON_SIG_EN AON CTRL signal enable pd_aon_shutdown_d_b ctrl 1:enable 0:disable pd_aon_shutdown_m_b ctrl 1:enable 0:disable pd_aon_mem ctrl 1:enable 0:disable rst_aon_en ctrl 1:enable 0:disable pd_aon_iso ctrl 1:enable 0:disable clk_en_aon ctrl 1:enable 0:disable SLEEP_PROT_TIME The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. ELIMINATE_JITTER Eliminate jitter delay register Emilinate the jitter from awake signal when writing 1 to correspond bits. AP_LPS_STA awake valid 0：invalid 1：valid AP_POW_ACK sta(ap exit sleep mode) 0：POW_ACK value 1：POW_ACK value AP_LPS end sta 0:not sleep 1:sleep AP_SYS state 0: normal working 1: low power mode CP_INTEN t9_irq enable 1: enable 0: disable t8_irq enable 1: enable 0: disable t7_irq enable 1: enable 0: disable load_irq enable 1: enable 0: disable ap_sys_awk_irq enable 1: enable 0: disable cp_sys_awk_irq enable 1: enable 0: disable tstamp_irq enable 1: enable 0: disable t6_irq enable 1: enable 0: disable t5_irq enable 1: enable 0: disable t4 enable 1: enable 0: disable t3_irq enable 1: enable 0: disable t2_irq enable 1: enable 0: disable t1_irq_enable 1: enable 0: disable p2_irq enable 1: enable 0: disable p1_irq enable 1: enable 0: disable CP_INT_STA clear cp interrupt state register when writing 1 to correspond bits. AP_INTEN ap interrupt enable register t9_irq enable 1: enable 0: disable t8_irq enable 1: enable 0: disable t7_irq enable 1: enable 0: disable tstamp_irq enable 1: enable 0: disable load_irq enable 1: enable 0: disable ap_sys_awk_irq enable 1: enable 0: disable cp_sys_awk_irq enable 1: enable 0: disable t6_irq enable 1: enable 0: disable t5_irq enable 1: enable 0: disable t4 enable 1: enable 0: disable t3_irq enable 1: enable 0: disable t2_irq enable 1: enable 0: disable t1_irq_enable 1: enable 0: disable p2_irq enable 1: enable 0: disable p1_irq enable 1: enable 0: disable AP_INT_STA ap interrupt state clear ap interrupt state register when writing 1 to correspond bits. AP_AWK_EN AP wakeup enable register P2_AWK_EN wakeup enable 0: disable 1: enable T6_AWK_EN wakeup enable 0: disable 1: enable T5_AWK_EN wakeup enable 0: disable 1: enable T4_AWK_EN wakeup enable 0: disable 1: enable T3_AWK_EN wakeup enable 0: disable 1: enable T2_AWK_EN wakeup enable 0: disable 1: enable T1_AWK_EN wakeup enable 0: disable 1: enable P1_AWK_EN wakeup enable 0: disable 1: enable AWK23_EN wakeup enable 0: disable 1: enable AWK22_EN wakeup enable 0: disable 1: enable AWK21_EN wakeup enable 0: disable 1: enable AWK20_EN wakeup enable 0: disable 1: enable AWK19_EN wakeup enable 0: disable 1: enable AWK18_EN wakeup enable 0: disable 1: enable AWK17_EN wakeup enable 0: disable 1: enable AWK16_EN wakeup enable 0: disable 1: enable AWK15_EN wakeup enable 0: disable 1: enable AWK14_EN wakeup enable 0: disable 1: enable AWK13_EN wakeup enable 0: disable 1: enable AWK12_EN wakeup enable 0: disable 1: enable AWK11_EN wakeup enable 0: disable 1: enable AWK10_EN wakeup enable 0: disable 1: enable AWK9_EN wakeup enable 0: disable 1: enable AWK8_EN wakeup enable 0: disable 1: enable AWK7_EN wakeup enable 0: disable 1: enable AWK6_EN wakeup enable 0: disable 1: enable AWK5_EN wakeup enable 0: disable 1: enable AWK4_EN wakeup enable 0: disable 1: enable AWK3_EN wakeup enable 0: disable 1: enable AWK2_EN wakeup enable 0: disable 1: enable AWK1_EN wakeup enable 0: disable 1: enable AWK0_EN wakeup enable 0: disable 1: enable AP_AWK_ST CP_AWK_EN CP wakeup enable register P2_AWK_EN wakeup enable 0: disable 1: enable T6_AWK_EN wakeup enable 0: disable 1: enable T5_AWK_EN wakeup enable 0: disable 1: enable T4_AWK_EN wakeup enable 0: disable 1: enable T3_AWK_EN wakeup enable 0: disable 1: enable T2_AWK_EN wakeup enable 0: disable 1: enable T1_AWK_EN wakeup enable 0: disable 1: enable P1_AWK_EN wakeup enable 0: disable 1: enable AWK23_EN wakeup enable 0: disable 1: enable AWK22_EN wakeup enable 0: disable 1: enable AWK21_EN wakeup enable 0: disable 1: enable AWK20_EN wakeup enable 0: disable 1: enable AWK19_EN wakeup enable 0: disable 1: enable AWK18_EN wakeup enable 0: disable 1: enable AWK17_EN wakeup enable 0: disable 1: enable AWK16_EN wakeup enable 0: disable 1: enable AWK15_EN wakeup enable 0: disable 1: enable AWK14_EN wakeup enable 0: disable 1: enable AWK13_EN wakeup enable 0: disable 1: enable AWK12_EN wakeup enable 0: disable 1: enable AWK11_EN wakeup enable 0: disable 1: enable AWK10_EN wakeup enable 0: disable 1: enable AWK9_EN wakeup enable 0: disable 1: enable AWK8_EN wakeup enable 0: disable 1: enable AWK7_EN wakeup enable 0: disable 1: enable AWK6_EN wakeup enable 0: disable 1: enable AWK5_EN wakeup enable 0: disable 1: enable AWK4_EN wakeup enable 0: disable 1: enable AWK3_EN wakeup enable 0: disable 1: enable AWK2_EN wakeup enable 0: disable 1: enable AWK1_EN wakeup enable 0: disable 1: enable AWK0_EN wakeup enable 0: disable 1: enable CP_AWK_ST CP_LPS_STA CP AKW valid 0:disvalid 1:valid CP_POW_ACK sta(sleep end) 0：LOW 1：HIGH CP_LPS end sta 0:don't sleep 1:IDLE end paging awk（just P1 awk） 0:no paging awk 1:paging awk SYS state 0: normal working 1: low power mode CP_P1_TIME CP_P2_TIME LPS_T_TIME1 LPS_T_TIME2 LPS_T_TIME3 LPS_T_TIME4 LPS_T_TIME5 LPS_T_TIME6 LOAD_EN load_time enable 1:enable 0:disable LPS_32K_REF 32K reference counter REF_32K_FNL REF_32K CONT clocked register LPS_TPCTRL time stamp register 0: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. 1:time stamp loop 1: enable 0: disable LPS_TP_STA 1:tstamp saved 0:nothing LOAD_TIME MON_SEL mon15_sel: 00: select t5_awk 01: select awake[5] 10: select awake[12] 11: select awake[21] mon14_sel: 00: select t4_awk 01: select awake[4] 10: select awake[11] 11: select awake[20] mon13_sel: 00: select t3_awk 01: select awake[3] 10: select awake[10] 11: select awake[19] mon12_sel: 00: select t2_awk 01: select awake[2] 10: select awake[9] 11: select awake[18] mon11_sel: 00: select t1_awk 01: select awake[1] 10: select awake[8] 11: select awake[17] mon10_sel: 00: select p2_int 01: select awake[0] 10: select awake[7] 11: select awake[16] mon9_sel: 00: select p1_awk 01: select chip_pd 10: select awake[6] 11: select awake[15] mon8_sel: 00: select awake[22] 01: select awake[23] 10: select t6_awk 11: select awake[14] mon7_sel: 00: select ap_chip_pd 01: select cp_ship_pd 10: select pd_aon_shutdown_d_b. 11: select awake[13] mon6_sel: 00: select ap_pd_xtal 01: select cp_pd_xtal 10: select pd_aon_shutdown_m_b. 11: select t6_int. mon5_sel: 00: select ap_pd_pll 01: select cp_pd_pll 10: select pd_aon_mem. 11: select t5_int. mon4_sel: 00: select ap_lps_cg 01: select cp_lps_cg 10: select rst_aon_n. 11: select t4_int. mon3_sel: 00: select ap_pow_on_ack 01: select cp_pow_on_ack 10: select pd_aon_iso. 11: select t3_int. mon2_sel: 00: select ap_pow_on 01: select cp_pow_on 10: select clk_en_aon. 11: select t2_int. mon1_sel: 00: select idst_ap 01: select idst_cp. 10: select idst_aon 11: select t1_int mon0_sel: 00: select idct_ap. 01: select idct_cp. 10: select pm2_mode_en. 11: select p1_int LPS_RES0 LPS_RES1 LPS_RES2 LPS_RES3 LPS_RES4 LPS_RES5 LPS_RES6 LPS_RES7 LPS_RES8 LPS_RES9 LPS_RES10 LPS_RES11 CP_P1_EN paging timer en 1:enable 0:disable CP_P2_TEN awake timer en 1:enable 0:disable LPS_T1_EN target_time en 1:enable 0:disable LPS_T2_EN target_time en 1:enable 0:disable LPS_T3_EN target_time en 1:enable 0:disable LPS_T4_EN target_time en 1:enable 0:disable LPS_T5_EN target_time en 1:enable 0:disable LPS_T6_EN target_time en 1:enable 0:disable AP_AWK_EN1 T9_AWK_EN wakeup enable 0: disable 1: enable T8_AWK_EN wakeup enable 0: disable 1: enable T7_AWK_EN wakeup enable 0: disable 1: enable AP_AWK_ST1 clear ap wake state register when writing 1 to correspond bits. CP_AWK_EN1 T9_AWK_EN wakeup enable 0: disable 1: enable T8_AWK_EN wakeup enable 0: disable 1: enable T7_AWK_EN wakeup enable 0: disable 1: enable CP_AWK_ST1 clear ap wake state register when writing 1 to correspond bits. LPS_T_TIME7 LPS_T_TIME8 LPS_T_TIME9 LPS_T7_EN target_time en 1:enable 0:disable LPS_T8_EN target_time en 1:enable 0:disable LPS_T9_EN target_time en 1:enable 0:disable CP_PM2_MODE_EN CP PM2 enable CP enable PM2 mode 0:enable PM2 mode 1:disable PM2 mode user_gate_force_off lps_ahb_ana_wrap3_force_off force clk on, default : 1'b0 lps_ahb_idle_lps_force_off force clk on, default : 1'b0 lps_ahb_pwrctrl_func_force_off force clk on, default : 1'b0 lps_ahb_pwrctrl_intf_force_off force clk on, default : 1'b0 lps_ahb_keypad_osc_force_off force clk on, default : 1'b0 lps_ahb_keypad_always_force_off force clk on, default : 1'b0 lps_ahb_keypad_force_off force clk on, default : 1'b0 lps_ahb_apb_reg_force_off force clk on, default : 1'b0 lps_ahb_gpt1_force_off force clk on, default : 1'b0 lps_ahb_gpio_mod_force_off force clk on, default : 1'b0 lps_ahb_gpio1_force_off force clk on, default : 1'b0 lps_ahb_uart1_force_off force clk on, default : 1'b0 lps_ahb_uart1_always_force_off force clk on, default : 1'b0 lps_ahb_uart1_mod_force_off force clk on, default : 1'b0 lps_ahb_to_aon_force_off force clk on, default : 1'b0 lps_32k_fr_force_off force clk on, default : 1'b0 uart1_bf_div_uart1_always_force_off force clk on, default : 1'b0 uart1_bf_div_uart1_force_off force clk on, default : 1'b0 user_gate_auto_gate_en lps_ahb_ana_wrap3_auto_gate_en auto gate en, default : 1'b1 lps_ahb_idle_lps_auto_gate_en auto gate en, default : 1'b1 lps_ahb_pwrctrl_func_auto_gate_en auto gate en, default : 1'b1 lps_ahb_pwrctrl_intf_auto_gate_en auto gate en, default : 1'b1 lps_ahb_keypad_osc_auto_gate_en auto gate en, default : 1'b1 lps_ahb_keypad_always_auto_gate_en auto gate en, default : 1'b1 lps_ahb_keypad_auto_gate_en auto gate en, default : 1'b1 lps_ahb_apb_reg_auto_gate_en auto gate en, default : 1'b1 lps_ahb_gpt1_auto_gate_en auto gate en, default : 1'b1 lps_ahb_gpio_mod_auto_gate_en auto gate en, default : 1'b1 lps_ahb_gpio1_auto_gate_en auto gate en, default : 1'b1 lps_ahb_uart1_auto_gate_en auto gate en, default : 1'b1 lps_ahb_uart1_always_auto_gate_en auto gate en, default : 1'b1 lps_ahb_uart1_mod_auto_gate_en auto gate en, default : 1'b1 lps_ahb_to_aon_auto_gate_en auto gate en, default : 1'b1 lps_32k_fr_auto_gate_en auto gate en, default : 1'b1 uart1_bf_div_uart1_always_auto_gate_en auto gate en, default : 1'b1 uart1_bf_div_uart1_auto_gate_en auto gate en, default : 1'b1 cgm_uart1_bf_div_sel_cfg cgm_uart1_bf_div_sel: clk_uart1_bf_div source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_26m, default: 2'h1 cgm_lps_ahb_sel_cfg cgm_lps_ahb_sel: clk_lps_ahb source , 0: rtc_32k, 1: xtal_lp_26m, 2: xtal_26m, 3: rc26m_26m, default: 2'h1 cgm_busy_src_monitor_cfg0 cgm_busy_src_monitor0, 0:(cgm_uart1_bf_div_sel_ac == 2) & cgm_busy_uart1_bf_div 1:cgm_busy_lps_ahb_sel_2 & cgm_busy_lps_ahb 2:(cgm_uart1_bf_div_sel_ac == 1) & cgm_busy_uart1_bf_div 3:cgm_busy_lps_ahb_sel_1 & cgm_busy_lps_ahb 4:(cgm_uart1_bf_div_sel_ac == 3) & cgm_busy_uart1_bf_div 5:cgm_busy_lps_ahb_sel_3 & cgm_busy_lps_ahb 6:(cgm_uart1_bf_div_sel_ac == 0) & cgm_busy_uart1_bf_div 7:cgm_busy_lps_32k 8:cgm_busy_lps_ahb_sel_0 & cgm_busy_lps_ahb soft_cnt_done0_cfg rc26m_26m_soft_cnt_done counter wait for source stable pll_wait_sel0_cfg rc26m_26m_wait_auto_gate_sel pll wait's enable select. 0: sort register control 1: hw auto control pll_wait_sw_ctl0_cfg rc26m_26m_wait_force_en pll wait's enable sw control gate_en_sel0_cfg cgm_rtc_32k_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_ap_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rtc_32k_cp_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rtc_32k_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_aon_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rtc_32k_lps_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control cgm_rc_26m_lps_auto_gate_sel clock gating enable select. 0: soft register control 1: hw(pmu) auto control gate_en_sw_ctl0_cfg cgm_rtc_32k_ap_force_en clock gating enable sw control cgm_rc_26m_ap_force_en clock gating enable sw control cgm_rtc_32k_cp_force_en clock gating enable sw control cgm_rtc_32k_aon_force_en clock gating enable sw control cgm_rc_26m_aon_force_en clock gating enable sw control cgm_rtc_32k_lps_force_en clock gating enable sw control cgm_rc_26m_lps_force_en clock gating enable sw control monitor_wait_en_status0_cfg monitor_wait_en_status , 0:rc26m_26m monitor_gate_auto_en_status0_cfg monitor_gate_auto_en_status , 0:cgm_rtc_32k_ap, 1:cgm_rc_26m_ap, 2:cgm_rtc_32k_cp, 3:cgm_rtc_32k_aon, 4:cgm_rc_26m_aon, 5:cgm_rtc_32k_lps, 6:cgm_rc_26m_lps module enable module enable Reserved Enable. Active High; 0 : Disable ; 1 : Enable ; mtx_cfg Enable. Active High; 0 : Disable ; 1 : Enable ; pagespy Enable. Active High; 0 : Disable ; 1 : Enable ; Soft Reset Soft Reset Reserved Soft Reset. Active High; 0 : Keep module in normal mode; 1 : Reset module; mtx_cfg Soft Reset. Active High; 0 : Keep module in normal mode; 1 : Reset module; dmc400 Soft Reset. Active High; 0 : Keep module in normal mode; 1 : Reset module; pagespy Soft Reset. Active High; 0 : Keep module in normal mode; 1 : Reset module; debug_ctrl debug_ctrl psram sleep ctrl psram sleep ctrl half_slp_reg enable force_reg force_en wait_num psram gate_sel psram gate_sel gate_auto_sel psram gate_force psram gate_force gate_force_en cgm_psram cgm_psram cgm_psram_2x_sel cgm_psram_2x_div cgm_psram_1x_div lpc_ctrl0 lpc_ctrl0 pu_num lp_num lpc_ctrl1 lpc_ctrl1 lp_force lp_eb pub_anti_hang pub_anti_hang 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: enable error response 0: always response OK 1: select fw ID 0: select matrix id monitor_clock_status monitor_clock_status monitor_cgm_busy_status monitor_gate_en_status debug_status debug_status 1: use external resetn 0: use sw/enable generated internal resetn for rxdp 0: clk_dac 1: clk_dac invert 0: clk_adc 1: clk_adc invert 0:no use 1:no use 2:LTE-1.4M 3:LTE-3M 4:LTE-5M 5:LTE-10M 6:LTE-15M 7:LTE-20M 8:no use 0:30.72MHz 1:61.44MHz 2:122.88MHz 0: IF mode 1: ZF mode 0: registers module clk gating enabled; 1: registers module clk always on; new add for debug, should not config 0: RX CIC1 doesn't work in loft mode; 1: RX CIC1 works in loft mode sw controlled resetn for rxdp 0: assert reset 1: not reset DFE clock shift control. Change in 8910m, when clock_shift enable, only config this bit, no need config rxdp_rc or txdp_rc (deleted) 0: clock shift disabled 1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency clock enable for BB LTE @122.88MHz clock enable for DFE NB/WT/LTE TX clock enable for DFE RX clock enable for DAC clock eanble for ADC Start to load DC value, active high. Before next load, set it low firstly IQ swap in DC module 0: no swap 1. swap Hold DC accumulator calculation in DC calibration mode This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. Load DC value in calibration mode to debug port, only used for debug purpose DC module work mode. 0: DC calibration mode 1: DC cancel mode DC real part value used in cancel mode DC image part value used in cancel mode Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Slow convergence control, work with conv_mode_ct_rg register Fast convergence control, work with conv_mode_ct_rg register Duration time of DC calibration, which is based on sample unit DC convergence loop mode selection. 0: fast 1: slow 2: fast->slow 3: fast->hold load rxdp_gain_ct to DFE. Write it to 1b'0 before assert it; new add, when [12]=0, need use this bit bypass rxdp_gain_ct_load; new add, 1: direct use [10:0] in static adjust agc gain 0: use [10:0] need load first for dynamic adjust agc gain Gain BB control. [-24db, 47.9375db], step=1/16db; change the step from 1/8db to 1/16db Bit [15:0] of RX group delay coefficient 0 Bit [19:16] of RX group delay coefficient 0 Bit [15:0] of RX group delay coefficient 1 Bit [19:16] of RX group delay coefficient 1 Bit [15:0] of RX group delay coefficient 2 Bit [19:16] of RX group delay coefficient 2 Bit [15:0] of RX group delay coefficient 3 1: LP 0: BP Bit [19:16] of RX group delay coefficient 3 Read rate of DFE ADC FIFO, which depends on RX mode. 8910m move 0x0060[12:7] to here[6:1] 5'h00: GGE 5'h01: NB/WT Write enable of DFE ADC FIFO, active high Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high Real part of DC value, it is stable when rxdp_dcc_val_reg is high Image part of DC value, it is stable when rxdp_dcc_val_reg is high Data enable of Notch DC 0: disable 1: enable Coefficient a for real part of Notch DC Coefficient a for image part of Notch DC Coefficient k of Notch DC mrrm bandwidth selection Data enable of Notch H 1st core 0: disable 1: enable Data enable of Notch H 2nd core 0: disable 1: enable Coefficient a for real part of Notch H 1st core Coefficient a for image part of Notch H 1st core Coefficient a for real part of Notch H 2nd core Coefficient a for image part of Notch H 2nd core Coefficient k of Notch H 1st core Coefficient k of Notch H 2nd core Coefficient COEF0 of ACI filter Coefficient COEF1 of ACI filter Coefficient COEF2 of ACI filter Coefficient COEF3 of ACI filter Coefficient COEF4 of ACI filter Coefficient COEF5 of ACI filter Coefficient COEF6 of ACI filter Coefficient COEF7 of ACI filter Coefficient COEF8 of ACI filter Coefficient COEF9 of ACI filter Coefficient COEF10 of ACI filter Coefficient COEF11 of ACI filter Coefficient COEF12 of ACI filter Coefficient COEF13 of ACI filter Coefficient COEF14 of ACI filter Coefficient COEF15 of ACI filter Coefficient COEF16 of ACI filter Coefficient COEF17 of ACI filter Coefficient COEF18 of ACI filter Coefficient COEF19 of ACI filter Coefficient COEF20 of ACI filter Coefficient COEF21 of ACI filter Coefficient COEF22 of ACI filter Coefficient COEF23 of ACI filter Bit [15:0] of frequency offset for Mixer Bit [23:16] of frequency offset for Mixer RSSI3 enable RSSI3 ushift value Outband RSSI enable Inband RSSI enable Outband RSSI ushift value Inband RSSI ushift value start inband RSSI max and min measurement timer count[15:0] for max and min measurement report after start timer count[31:16] for max and min measurement report after start start to load max and min measurement report. Before next load, set it low firstly valid of max and min measurement report inband RSSI min value inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear indication to read instant measurement report valid of instant measurement report inband RSSI instant value start outband RSSI max and min measurement timer count[15:0] for max and min measurement report after start timer count[31:16] for max and min measurement report after start indication to read max and min measurement report valid of max and min measurement report outband RSSI min value outband RSSI max value interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear indication to read instant measurement report valid of instant measurement report outband RSSI instant value for WD outband RSSI instant value for UP outband RSSI instant value for DN Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter Group Delay Equ Notch(DC) Mixer RC DC Calib.&Cancel Deci.CIC1 dnhb2 imbc mrrm Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter Group Delay Equ Notch(DC) Mixer RC DC Calib.&Cancel Deci.CIC1 dnhb2 imbc mrrm instant value of rxdp_dcc_re, new add for debug instant value of rxdp_dcc_im, new add for debug instant value of rssi_reg_ib_rssi, new add for debug instant value of rssi_reg_wd_ob_rssi, new add for debug instant value of rssi_reg_up_ob_rssi, new add for debug instant value of rssi_reg_dn_ob_rssi, new add for debug start RSSI3 max and min measurement timer count[15:0] for max and min measurement report after start timer count[31:16] for max and min measurement report after start start to load max and min measurement report. Before next load, set it low firstly valid of max and min measurement report RSSI3 min value RSSI3 max value, it is stable when rssi_max_min_val_reg_rssi3 is high interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear indication to read instant measurement report valid of instant measurement report RSSI3 instant value instant value of rssi_reg_rssi3, new add for debug load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it, new add, when [12]=0, need use this bit bypass txdp_wedge_gain_ct_load; new add, 1: direct use [10:0] in static adjust agc gain 0: use [10:0] need load first for dynamic adjust agc gain Gain control of NB/WT TX. [-24db, 47.9375db], step=1/16db; change the step from 1/8db to 1/16db Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Coefficient 4 of ACLR filter, new add Coefficient 5 of ACLR filter, new add Coefficient 6 of ACLR filter, new add Coefficient 7 of ACLR filter, new add resource of clk_dac when test mode. 00: clk_122p88m 01: clk_61p44m 10: clk_30p72m 11: clk_adc_gge_nb enable clk_dac when test mode 0: clk_dac is from function mode 1: clk_dac is from test mode txdp_delay Coefficient 0 of ACLR filter, new add Coefficient 1 of ACLR filter, new add Coefficient 2 of ACLR filter, new add Coefficient 3 of ACLR filter, new add Bit [15:0] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX no use no use no use no use no use BB TX data loopback to BB RX BB RX IQ swap. 1: swap; 0: normal BB TX IQ swap. 1: swap; 0: normal ADC IQ swap. 1: swap; 0: normal DAC IQ swap. 1: swap; 0: normal BB RX. 0: two's complement 1: offset binary BB TX. 0: two's complement 1: offset binary RF ADC. 0: two's complement 1: offset binary RF DAC. 0: two's complement 1: offset binary instant value of txdp_loft_rssi_err valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high start to load the result of temper_dout. Before next load, set it low firstly bandwidth select no use temper_dout value clock enable for temper divide mode of clock from analog for Temcomp 0: not divide 1: 1/2 divide 2: 1/4 divide 3: 1/8 divide clock invert for Temcomp 0: clock invert disable 1: clock invert enable Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter instant value of temper_dout valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high start to load the result of temper_dout. Before next load, set it low firstly bandwidth select no use temper_dout value clock enable for temper divide mode of clock from analog for Temcomp 0: not divide 1: 1/2 divide 2: 1/4 divide 3: 1/8 divide clock invert for Temcomp 0: clock invert disable 1: clock invert enable Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter instant value of temper_dout dfe_sw_clkgate_en swap of dfe_monitor[15:8] and dfe_monitor[7:0] dfe_monitor select The offset on DAC real part The offset on DAC image part The DAC real part on test mode The DAC image part on test mode select of function DAC data or test DAC data 00/01: select function DAC data including sine waveform 10: select test DAC data in txdp 11: select test DAC data in txdp enable sine generation module enable of test DAC data in rxdp select of test DAC data in rxdp enable of test DAC data in txdp select of test DAC data in txdp sine amp sine frequency[15:0] LOFT LOFT sine frequence[22:16] UPHBF(3) UPHBF(2) Group Delay Equ. AMPM of DPD Whole DPD RC Gain CFR UPHBF(1) ACLR LPF ampequ, new add UPHBF(3) UPHBF(2) Group Delay Equ. AMPM of DPD Whole DPD RC Gain CFR UPHBF(1) ACLR LPF ampequ all zero bits, reserved for ECO all one bits, reserved for ECO all one bits, reserved for ECO pwr_rf_ushift_rg pwr_rf_start_rg pwr_rf_polar_rg 1: clk always on, 0: clk gating by hardware 1: clk always on, 0: clk gating by hardware 1: clk always on, 0: clk gating by hardware determine dac bits position when test mode. 0:[11:0], 1:[12:1], 2:[13:2], 3:[14:3], 4:[15:4] Bit [11:0] of coefficient 0 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 1 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 2 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 3 of ampequ. for NB/LTE/eMTC TX Bit [27:12] of gain for ampequ. for NB/LTE/eMTC TX, must config for all tx, init value 0x400 Bit [11:0] of gain for ampequ. It works with register txdp_ampequ_g_rg read interval for FIFO A, new add change with different rx mode read interval for FIFO B, new add change with different rx mode FIFO dump full FIFO dump empty FIFO txdp_rc full FIFO txdp_rc empty FIFO rxdp_rc full FIFO rxdp_rc empty FIFO ADC full FIFO ADC empty, this FIFO used between ADC and DFE FIFO B full FIFO B empty, this FIFO used when LVDS RX for adc-dfe-lvds-bb FIFO A full FIFO A empty, this FIFO used when normal RX or LVDS TX for adc-dfe-lvds-bb clock frequency select when dump FIFO write 0000: clk_122p88m_m 0001: clk_adc 001x: clk_245p76m 01xx: clk_245p76m_m 1xxx: clk_pwd valid width select when dump 00: 1 cycle period (245.76M) 01: 2 cycle period (245.76M) 10: 3 cycle period (245.76M) 11: 4 cycle period (245.76M) enable dump dump node selection. It works with register sel_clk_dump_w for correct clock. 0: dump RX data from DFE, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref 1: dump TX data from BB, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref 2: dump RXDP data, sel_clk_dump_w can be clk_rxdp/clk_rxdp_m 3: dump TXDP data, sel_clk_dump_w can be clk_txdp/clk_245p76m_m(clk_txdp_m)/clk_pwd others: dump data from LVDS, sel_clk_dump_w can be can be lvds2dfe_clk Coefficient 8 of ACLR filter, new add Coefficient 9 of ACLR filter, new add Coefficient 10 of ACLR filter, new add Coefficient 11 of ACLR filter, new add Coefficient 12 of ACLR filter, new add Coefficient 13 of ACLR filter, new add Coefficient 14 of ACLR filter, new add Coefficient 15 of ACLR filter, new add Coefficient 16 of ACLR filter, new add Coefficient 17 of ACLR filter, new add Coefficient 18 of ACLR filter, new add Coefficient 19 of ACLR filter, new add Coefficient 20 of ACLR filter, new add Coefficient 21 of ACLR filter, new add Coefficient 22 of ACLR filter, new add Coefficient 23 of ACLR filter, new add Start to load DC value, active high. Before next load, set it low firstly IQ swap in DC module 0: no swap 1. swap Hold DC accumulator calculation in DC calibration mode This register is used. Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. Load DC value in calibration mode to debug port, only used for debug purpose DC module work mode. 0: DC calibration mode 1: DC cancel mode DC real part value used in cancel mode DC image part value used in cancel mode Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Slow convergence control, work with conv_mode_ct_rg register Fast convergence control, work with conv_mode_ct_rg register Duration time of DC calibration, which is based on sample unit DC convergence loop mode selection. 0: fast 1: slow 2: fast->slow 3: fast->hold Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high Real part of DC value, it is stable when pwd_dcc_val_reg is high Image part of DC value, it is stable when pwd_dcc_val_reg is high instant value of rxdp_dcc_re, new add for debug instant value of rxdp_dcc_im, new add for debug 1:选择LTE BBPLL tuned 122.88M，0：选择晶体untuned 26M 软件调整122.88m计数周期生效时刻选择0：下帧起效；1：当帧起效 软件调整122.88m计数周期使能，生效时刻可选 软件调整122.88M counter计数值使能，立即生效 软件Latch 122.88m counter使能 GNSS RTC/CPU/EM Latch 122.88m counter使能 Tuned 122.88M counter计数清零 Tuned 122.88M counter计数使能 软件latch bitmap wptr写指针和循环计数值使能 GNSS RTC/CPU/EM Latch bitmap wptr写指针和循环计数值使能 清除bitmap循环到0，清除wptr写指针 Bitmap功能开关使能 Bitmap循环周期设置，默认为0-127循环，最大0-255循环,Bitmap功能启动前需要配置完毕，启动过程中不支持修改 122.88M计数中断产生周期设置，默认为1ms；如果是26M，1ms对应值是0x658F 122.88M计数中断产生周期设置，默认为1ms；如果是26M，1ms对应值是0x0 软件调整122.88M/26M counter计数值，立即生效 软件调整122.88M/26M counter计数值，立即生效 软件调整122.88M/26M counter计数值，立即生效 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 122.88M/26M counter计数值，GNSS RTC/CPU/EM Latch、软件Latch使能后更新，共48bit，【17：0】为1ms计数循环，【21：18】为10ms计数循环，【48：22】为计满循环，格式同LTE Frame timer3 Bitmap wptr写指针，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 Bitmap置位计数值，软件latch使能后更新，判断到valid为1后有效 LTE-GNSS信息交互bit寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 Bitmap软件置位寄存器，保留软件使用 bandgap trim ISM TXABB LDO output voltage selection ISM TXABB LDO output voltage control signal 000 0.84V 100 0.96V 001 0.87V 101 0.99V 010 0.9V 110 1.02V 011 0.93V 111 1.05V Top LevelShIft LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol VDD_input 00 1.8V 01 1.5V 10 1.2V 11 1.2V LNA ldo power up LNA ldo fast charge en RX ABB ldo power up RX ABB ldo fast charge en ADC LDO bias enable ADC LDO enable TX filter ldo power up TX filter ldo fast charge en DAC LDO enable DAC LDO fast charge PWDADC LDO bias enable, only used in ditital domain PWDADC LDO enable, only used in digital domain rxpll gro ldo bias en rxpll gro ldo en RXPLL presc ldo power up RXPLL presc ldo fast charge en RXPLL RDAC ldo digital power up RXPLL RDAC ldo vref power up RXPLL RDAC ldo fast charge en RX VCO ldo power up RX VCO ldo fast charge en RX VCO ldo load en RX VCO buffer ldo power up RX VCO buffer ldo fast charge en RX VCO buffer ldo load en RX VCO TC power up RX VCO TC fast charge en txpll gro ldo bias en txpll gro ldo en TXPLL presc ldo power up TXPLL presc ldo fast charge en TXPLL RDAC ldo digital power up TXPLL RDAC ldo vref power up TXPLL RDAC ldo fast charge en TX VCO ldo power up TX VCO ldo fast charge en TX VCO ldo load en TX VCO buffer ldo power up TX VCO buffer ldo fast charge en TX VCO buffer ldo load en TX VCO TC power up TX VCO TC fast charge en Pu of bandgap pu_mdll_bb mdll start up TO AVDDDCXO_18 & AVSS_CLK pu xdrv buffer rxvco_bias_en rxvco_ibias_en rxvcoh pu rxvcol pu rxvco_pkdet enable pu_rxpll_presc_bb pu_rxpll_gro_bb pu_rxpll_rdac_bb rxpll_gro_rstn_bb rxpll_rdac reset LNA power up lna peak detector enable RX PGA enable rx pga peak detector enable RX PGA DCDC IDAC power up RX filter DCDC IDAC power up RX filter OPA negative reset RX filter enable rx mixer power up tia power up ADC enable ADC enable ADC enable ADC enable ADC reset negative txvco_bias_en txvco_ibias_en txvcoh pu txvcol pu peak detector enable pu_txpll_presc_bb txpll RDAC power up txpll_gro_rstn_bb txpll RDAC reset TX filter reset negative DAC power up control DAC reset negative TX mixer work on enable TX filter power up control to AVDDRF_18 & AVSS_CLK txrf power on conrol to AVDDRF_18 & AVSS_CLK TX PA driver work on enable to AVDDRF_18 & AVSS_CLK power detector power up PWDADC reset negative PWD PGA power up PWDADC enable PWDADC enable PWDADC enable PWDADC enable PWD reset negative to AVDDRF_18 & AVSS_CLK power detector power up delay TX filter power up delay to AVDDRF_18 & AVSS_CLK txrf power on conrol delay Frequency division ratio of loop, 5~10. Dither control enable mdll_band_bit_bb mdll_band_sel_bb Dither control bit mdll_cp_ibit_bb Dither control mode selection Reset voltage control Frequency division 1/2/4 of clock output buffer 01 /1; 10 /2; 11 /4; mdll_refclk_test_en_bb mdll_vctrl_test_en_bb disable_refclk_rxpll_bb disable_refclk_txpll_bb ptat current enable, for tsenadc. TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK tbd tbd tbd tbd tbd varactor bias reverse seleted tbd tbd tbd rxvco_lcl_div1 rxvco_lcl_div2 rxvco lte en FBDIV LDO VREF TRIM，默认值750mV FBDIV LDO VOUT，默认值950mV FBDIV LDO镜像极点，1.2V VDD配2 GRO Master LDO VREF TRIM，默认值750mV GRO Master LDO VOUT，默认值950mV GRO Master LDO CP TRIM GRO Master Slave LDO VDDRES RDAC DIG LDO VREF TRIM,默认值750mV RDAC DIG LDO VOUT,默认值950mV RDAC DIG LDO 镜像极点, 1.2V VDD配2 RDAC VREF LDO VREF TRIM,默认值750mV RDAC VREF LDO VOUT,默认值880mV RDAC VREF LDO 镜像极点, 1.2V VDD配2 FBDIV VDDRES <3> 根据mdll选择slave ldo是否需要并入额外的nmos，mdll<4，配置为1；mdll>=4，配置为0； <4> rxpll_gro_ldo_in_trim_en [15]mod23_enb   [14]mod3_dly_more [13:4]clk_sample & clk_dig dly  [3:2]pfd死区时间 [1:0]gro mode [1:0]clk_en for tdc cal [2]在gro mode3时选择dn_en=0或者up_en的反； reserved vlow sel, 0~1/3vh, 1~1/5vh 3~1/9vh 7~0 rdac clk edge sel rxpll_fbdiv sdm clk & ndiv load dly,0~dly more rxpll_sdmclk_sel_bb RXPLL open loop enable TBD LNA wifi selection LNA lte hb 1 selection LNA lte hb 2 selection LNA lte mb 1 selection LNA lte mb 2 selection LNA lte mb 3 selection LNA lte mb 4 selection LNA lte mb 5 selection LNA lte gnss selection LNA lte lb 1 selection LNA lte lb 2 selection LNA lte lb 3 selection LNA lte lb 4 selection LNA lte lb 5 selection rxmixer LO signal selection, high for 5g VCO, low for 4g VCO; rxmixer LO signal selection, high for rx VCO, low for tx VCO; lna_power_res_control LNA LDO bypass, work at 1.2V LNA LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol LNA LDO output voltage control signal 000 0.825V; 001 0.85V; 010 0.875; V011 0.9V; 100 0.925V; 101 0.95V; 110 0.975V; 111 1.0V; lna gain0, not used LNA Feedback resistor enable LNA peak detector threshold level control signa tbd tbd LNA peak detector threshold level control signal. LNA input matching capbank tune Lo dc level high mode Lo dc level for lte mode Rin of tia. 00 for 50ohm, 11 for 250ohm Tia bypass mode LNA mixer matching capbank tune high band2 LNA mixer matching capbank tune middle band3 RX ABB LDO output voltage control signal 000 0.825V; 001 0.85V; 010 0.875; V011 0.9V; 100 0.925V; 101 0.95V; 110 0.975V; 111 1.0V; RX ABB LDO ripple cancelling cap control signal to mitigate VDD variation effect conotrol Current of pga. 00 for 1.2mA, 11 for 3.5mA, 01 and 10 for 1.8mA. Rs control, 1st pole and 2nd pole control, only valid when pga_blk_mode=1 控制补偿电容大小，00 for 100f，01 and 10 for 200f，11 for 300f 控制补偿电容大小，00 is invalid，01 and 10 for 150fF，11 for 300fF. Bw control, 000 for 700KHz, 101 for 10MHz Cf control, 1st pole control, only valid when pga_blk_mode=1 Gsm blokcer mode enable or test model for external control the capacitor and resistor in pga Rpre control, blk fliter bw control, only valid when pga_blk_mode=1 2nd pole control, only valid when pga_blk_mode=1 Bw tune. 000 for 0.8*bw, 111 for 1.5*bw. 控制带宽，并tuning带宽，512*40fF tbd tbd LNA peak detector threshold level control signal. time for charge and discharge bias current of the pkd op ldo vout ctrl word pga op vocm ctrl word Dc offset calibration Dc offset calibration Dc offset calibration range aux input for filter enable bandwith selection bandwith tuning IQ swap, not use bandpass mode enable, set 0 center frequency selection (not use) anti_kick_back_filter_bw_control 控制补偿电容大小，00 for 100f，01 and 10 for 200f，11 for 300f 控制补偿电容大小，00 is invalid，01 and 10 for 150fF，11 for 300fF. RX filter bias current select 带宽档位控制 and tuning 带宽档位控制 and tuning ADC LDO for charge pump output voltage control signal ADC LDO input voltage control signal ADC LDO output voltage control signal Rst time control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv Signal in delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv CLOCK OUT polarity,0:rising edge,1:falling edge Compare time control Loop delay time control MSB compare time control Noise shaping charge set time control Noise shaping enable Offset control Offset control Offset control Offset control Offset control Offset control Ns common mode voltage control Offset control Offset control Residual compare enable Sample clock delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv STB control ADC vcm calibration common mode voltage control Vrp reference voltage control Vrp control TBD Ns slap control ADC input short for calibration Rst time control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv Signal in delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv CLOCK OUT polarity,0:rising edge,1:falling edge Compare time control Loop delay time control MSB compare time control Noise shaping charge set time control Noise shaping enable Ns slap control Ns common mode voltage control Offset control Offset control Offset control Offset control Offset control Offset control Offset control PWDADC input short for calibration Offset control Residual compare enable Sample clock delay control, 00:0*inv, 01:2*inv, 10:4*inv, 11:6*inv STB control PWDADC clk selection common mode voltage control Vrp reference voltage control Vrp control PWDADC vcm calibration lna gain control lna bias control LNA common gate bias select. Pga gain control, 11 for 4k Rf, 00 for 0.5k Rf. filter gain selection Rf of lna for impendance matching [4] rxflt_bypass [3:2] pga_dcoc_ictrl_bit<1:0> [1:0] flt_dcoc_ictrl_bit<1:0> TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD tbd tbd tbd tbd tbd varactor bias reverse seleted tbd tbd tbd txvco_lcl_div1 txvco_lcl_div2 txvco_tx_en_bb txvco_rxlte_en_bb txvco_gnss_en_bb txvco_rx_div1_en_bb txrfdiv_div2_en_bb txrfdiv_div4_en_bb txrfdiv_lte_en_bb txrfdiv_pwd_en_bb FBDIV LDO VREF TRIM，默认值750mV FBDIV LDO VOUT，默认值950mV FBDIV LDO镜像极点，1.2V VDD配2 GRO Master LDO VREF TRIM，默认值750mV GRO Master LDO VOUT，默认值950mV GRO Master LDO CP TRIM GRO Master Slave LDO VDDRES RDAC DIG LDO VREF TRIM,默认值750mV RDAC DIG LDO VOUT,默认值950mV RDAC DIG LDO 镜像极点, 1.2V VDD配2 RDAC VREF LDO VREF TRIM,默认值750mV RDAC VREF LDO VOUT,默认值880mV RDAC VREF LDO 镜像极点, 1.2V VDD配2 FBDIV VDDRES <3> 根据mdll选择slave ldo是否需要并入额外的nmos，mdll<4，配置为1；mdll>=4，配置为0； <4> txpll_gro_ldo_in_trim_en [15]mod23_enb   [14]mod3_dly_more [13:4]clk_sample & clk_dig dly  [3:2]pfd死区时间 [1:0]gro mode [1:0]clk_en for tdc cal [2]在gro mode3时选择dn_en=0或者up_en的反； reserved vlow sel, 0~1/3vh, 1~1/5vh 3~1/9vh 7~0 rdac clk edge sel rxpll_fbdiv sdm clk & ndiv load dly,0~dly more rxpll_sdmclk_sel_bb RXPLL open loop enable TBD 45 degree slice enable 45 degree signal output enable to AVDDRF_18 & AVSS_CLK driver and mixer slice control to AVDDRF_18 & AVSS_CLK driver gain setting mixer input rc filter attenuation to AVDDRF_18 & AVSS_CLK 0 deg driver gain compensation setting to AVDDRF_18 & AVSS_CLK +45 deg driver gain compensation setting to AVDDRF_18 & AVSS_CLK -45 deg driver gain compensation setting to AVDDRF_18 & AVSS_CLK pad gm current bias tuning to AVDDRF_18 & AVSS_CLK pad mgtr voltage bias tuning to AVDDRF_18 & AVSS_CLK pad cascade voltage bias tuning to AVDDRF_18 & AVSS_CLK output switch size control to AVDDRF_18 & AVSS_CLK output switch size control to AVDDRF_18 & AVSS_CLK 45 degree load banlance for filter to AVDDRF_18 & AVSS_CLK attenuation before mixer for band difference to AVDDRF_18 & AVSS_CLK high band branch1 enable to AVDDRF_18 & AVSS_CLK high band branch2 enable to AVDDRF_18 & AVSS_CLK low band branch1 enable to AVDDRF_18 & AVSS_CLK low band branch2 enable to AVDDRF_18 & AVSS_CLK frequence selection for different band. to AVDDRF_18 & AVSS_CLK frequence selection for different band. Ulb driver banlun deQ tuning TBD TBD caplatch enable cal_clk edge selection TBD TBD ibias current control TX filter output CM ctrl input high pass freq. control test mode enable filter bandwidth control filter bandwidth tuning control TX filter output buffer current control Vp_diff 00/01：300mv;10：600mv;11：750mv dac_auxout_en_bb dac_iout_en_bb bit[0]:en for tx bit[1]:en for test 0: negative;1: positive vhigh control, 000:600mv, 001:644mv, 010:692mv, 011:738mv, 100:788mv, 101:835mv, 110:882mv, 111:930mv; dac_core_bit_bb tia input common mode voltage, 00:450mv, 01:550mv, 10:650mv, 11:750mv TBD TBD LDO LDO out voltage control TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Dc offset calibration rxflt input Dc offset calibration rxflt input [0] LTE_TX_VCO_DIV_BUF_EN [1] LTE_TX_VCO_RX_DIV1_EN to AVDDRF_18 & AVSS_CLK power detector mixer gain selection Pwd pga dc offset calibration pwd_cal_i_done_bb Pwd pga dc offset calibration enable Pwd pga dc offset calibration pwd_cal_q_done_bb Pwd pga dc offset calibration enable TO AVDDDCXO_18 & AVSS_CLK LDO enable TO AVDDDCXO_18 & AVSS_CLK LDO fast charge TO AVDDDCXO_18 & AVSS_CLK TS power up TO AVDDDCXO_18 & AVSS_CLK Voltage measurement mode TO AVDDDCXO_18 & AVSS_CLK Voltage measurement mode TO AVDDDCXO_18 & AVSS_CLK Voltage measurement mode TO AVDDDCXO_18 & AVSS_CLK Chopper enable TO AVDDDCXO_18 & AVSS_CLK Chopper clock select TO AVDDDCXO_18 & AVSS_CLK ADC reference selection TO AVDDDCXO_18 & AVSS_CLK The SDMADC bias current. 000 is 2uA. TO AVDDDCXO_18 & AVSS_CLK VBE control, which is used to calibrate the non-linearity of temperature sensor. TO AVDDDCXO_18 & AVSS_CLK Reset TO AVDDDCXO_18 & AVSS_CLK TS Test mode  power up TO AVDDDCXO_18 & AVSS_CLK VBE non linearity calibration using another SDMADC TO AVDDDCXO_18 & AVSS_CLK Biploar core beta dependance calibration TO AVDDDCXO_18 & AVSS_CLK ADC CLK select. 00 1/8 MCLK; 01 1/4 MCLK; 10 1/2 MCLK; 11 MCLK TO AVDDDCXO_18 & AVSS_CLK Clk edge selected for MCLK TO AVDDDCXO_18 & AVSS_CLK Clk edge selected for internal MCLK divider. TO AVDDDCXO_18 & AVSS_CLK LDO psr improved TO AVDDDCXO_18 & AVSS_CLK LDO output voltage seltect for 1.5V [0] additional control bit for pwd_pga_cap_bit [1] ISO signal for clk26m_lp_uart, 0 for isolation, vcore_top domain revid TX IF test interface open enable DAC out test interface open enable CLK of PLL test enable to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK Band gap iref test switch enable TX VCO ldo vref test switch enable TX VCOBUF ldo vref test switch enable RX ABB ldo vref test switch enable RX VCO ldo vref test switch enable RX VCOBUF ldo vref test switch enable txvco_test_en rx_5g_test_en rx_4g_test_en rx_lo_test_en to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK to VDDIO & AVSS_CLK RX PLL RDAC ldo vref test switch enable TX PLL RDAC ldo vref test switch enable ADC INPUT TEST EN rxiq calibration signal divide by 2 enable rxiq calibration signal divide by 4 enable rxiq calibration signal ATT CTRL 0:cal sig from padrv; 1: cal sig from ext pa; ed ptat current source adjust ed bg current source adjust rxiq calibration signal ATT adjust from AVDDRF_12_RF & AVSS_RF TX dc cal output I from AVDDRF_12_RF & AVSS_RF TX dc cal output Q from AVDDRF_12_LNA & AVSS_LNA LNA peak detector output signal from AVDDRF_12_LNA & AVSS_LNA LNA peak detector output signal from AVDDRF_12_CLK & AVSS_RXABB RX PGA peak detector output signal from AVDDRF_12_RX & AVSS_LNA RX VCO peak detector output from AVDDRF_12_RF & AVSS_RF TX VCO peak detector output RXPLL lock flag, generated by DLPF; TXPLL lock flag, generated by DLPF; TO AVDDDCXO_18 & AVSS_CLK ADCLDO enable TO AVDDDCXO_18 & AVSS_CLK LDO output setting TO AVDDDCXO_18 & AVSS_CLK LDO trim setting(VREF) TO AVDDDCXO_18 & AVSS_CLK CHOP CLK setting 00:/8192 01:/4096 10:/2048 11:/1024 TO AVDDDCXO_18 & AVSS_CLK SAMPLE CLK setting 00:/4 01:/4 10:/2 11:/1 TO AVDDDCXO_18 & AVSS_CLK ADC BIAS setting 00:10uA 01:5uA 10:15uA 11:20uA TO AVDDDCXO_18 & AVSS_CLK ADC CAPCHOP CK enable TO AVDDDCXO_18 & AVSS_CLK ADC CHOP CK enable TO AVDDDCXO_18 & AVSS_CLK ADC sample edge select: 0:positive edge 1:negative edge TO AVDDDCXO_18 & AVSS_CLK ADC enable TO AVDDDCXO_18 & AVSS_CLK ADC input RC enable TO AVDDDCXO_18 & AVSS_CLK ADC offset cancel enable TO AVDDDCXO_18 & AVSS_CLK ADC reset signal, 0 to reset TO AVDDDCXO_18 & AVSS_CLK ADC input UGBUF enable TO AVDDDCXO_18 & AVSS_CLK ADC_input CM setting TO AVDDDCXO_18 & AVSS_CLK ADC_output CM setting TO AVDDDCXO_18 & AVSS_CLK CLK_TSEN_TEST channel select enable: 0: choose CLK path from 1.8V CLK_TSEN_26M 1: choose CLK path from 0.9V CLK_TSEN_TEST TO AVDDDCXO_18 & AVSS_CLK ADC BIAS setting 00:10uA 01:5uA 10:15uA 11:20uA TO AVDDDCXO_18 & AVSS_CLK ADC UGBUF CHOP CK enable TO AVDDDCXO_18 & AVSS_CLK ADC_UGBUF GBW setting TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK TO AVDDDCXO_18 & AVSS_CLK [0]:pu_xtal from BB;[1]pu xtal from reg 32k gen div step_offset Normal mode 32k gen div step_offset LP mode pu_xtal cycle select 2'b00: 4us; 2'b01:8us; 2'b10:12us; 2'b11:20us enable clk 26m lp uart to lps enable clk 26m lp to analog BBPLL2 ref clk 26m enable BBPLL1 ref clk 26m enable clk_26m_interface enable RFPLL refcal clk 26m pwdadc clk 26m enable xtal_osc_ibit lp mode xtal_osc_ibit normal mode xtal_cfix_bit lp mode xtal_cfix_bit normal mode xtal_fixi_bit lp mode xtal_fixi_bit normal mode xdrv aux1 parameter XTAL parameter xdrv parameter CADC bit lp mode CADC bit normal mode RTC RTC normal mode switch to PSM counter normal mode switch to PSM counter CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器会产生中断给riscv CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 CP-A5写此寄存器不会产生中断给riscv，仅用于信息存储 riscv中断清除bit，写1清0 riscv中断清除bit，写1清0 riscv中断状态指示bit riscv中断状态指示bit riscv中断使能bit，高有效 riscv中断使能bit，高有效 riscv原始中断状态指示bit riscv原始中断状态指示bit riscv中断源头选择bit，详见riscv中断列表 BBPLL1 AFC频偏调整寄存器 BBPLL1 AFC频偏调整寄存器 BBPLL2 AFC频偏调整寄存器 BBPLL2 AFC频偏调整寄存器 BBPLL1 AFC调整使能bit BBPLL1 AFC调整使能bit reserved，不使用 reserved，不使用 BBPLL1初始频偏 BBPLL1初始频偏 BBPLL2初始频偏 BBPLL2初始频偏 plls1 ldo output. TBD plls1_cpbias_bit_bb plls1_cpc_ibit_bb plls1_cpr_ibit_bb TBD plls1 ldo enable plls1 ldo fast charge enable [8]:clk fbc inv [9]:ref clk 52m [10]:freq update RXPLL cal state, ECO plls2 ldo output. TBD plls2_cpbias_bit_bb plls2_cpc_ibit_bb plls2_cpr_ibit_bb TBD plls2 ldo enable plls2 ldo fast charge enable [8]:clk fbc inv [9]:ref clk 52m [10]:freq update 送给模拟的分配时钟系数 送给模拟的分配时钟系数 送给模拟的分配时钟系数 送给模拟的分配时钟系数 送给模拟的分配时钟反向 送给模拟的分配时钟使能bit sdm rstn sdm input divN offset en sdm dither for frac spur sdm clk inv 0 sel int, 1sel 1bit frac, 2sel 2bit frac. 3sel 3bit frac afc for vco wait time control 0 for 8bit cband calibration, 3 for 11bit cband calibration afccounter counttime control: 0--2^5/26M 1--2^6/26M 2--2^7/26M 3--2^8/26M a-afc bypass cal top rstn aac bypass vco pkd wait time control: 0--500ns 1--750ns 2--1us 3--1.25us aac cal done vcobias adder control: 0--1 1--2 2--3 3--4 aac cal init delay control,1~1us pll agc rstn pll agc en pll agc counttime control afc charging delay control, 0~0, 7~3.5us vco calibration start signal 0 sel a-afc cbank, 1 sel d-afc cbank 0 for auto afc; 1 for manual vco cbank spi 0 for auto aac; 1 for manual vco bias spi 0 for auto ; 1 for manual pll loop open en 0 for auto ; 1 for manual afccounter enable control, high active 0 for auto ; 1 for manual afccounter rst control, high active 0 for auto ; 1 for manual vco peakdetector en a-afc start signal aac start signal aac state cal top state agc cal done signal a-afc cal done signal aac cal done signal cal top cal done signal, same as afc cal done a-afc err min, for debug vco cbank pll loop en afccount en afccount rst vco pkd en vco bias afccount output fot a-afc & agc vco pkd output fot aac sdm rstn sdm input divN offset en sdm dither for frac spur sdm clk inv 0 sel int, 1sel 1bit frac, 2sel 2bit frac. 3sel 3bit frac afc for vco wait time control 0 for 8bit cband calibration, 3 for 11bit cband calibration afccounter counttime control: 0--2^5/26M 1--2^6/26M 2--2^7/26M 3--2^8/26M a-afc bypass cal top rstn aac bypass vco pkd wait time control: 0--500ns 1--750ns 2--1us 3--1.25us aac cal done vcobias adder control: 0--1 1--2 2--3 3--4 aac cal init delay control: pll agc rstn pll agc en pll agc counttime control afc charging delay control, 0~0, 7~3.5us vco calibration start signal 0 sel a-afc cbank, 1 sel d-afc cbank 0 for auto afc; 1 for manual vco cbank spi 0 for auto aac; 1 for manual vco bias spi 0 for auto ; 1 for manual pll loop open en 0 for auto ; 1 for manual afccounter enable control, high active 0 for auto ; 1 for manual afccounter rst control, high active 0 for auto ; 1 for manual vco peakdetector en vco cbank pll loop en afccount en afccount rst vco pkd en vco bias afccount output fot a-afc & agc vco pkd output fot aac peak detector功能硬件检测到adc_en为1后自动打开，不需要配置软件使能bit peak detector中断清除 peak detector软件使能bit peak detector中断状态bit peak detector信号时钟同步后的状态 peak detector信号原始输入状态 peak detector中断循环检测周期 peak detector中断循环检测周期 peak detector中断循环检测周期 peak detector中断循环检测周期 peak detector中断检测触发周期 peak detector中断检测触发周期 peak detector中断检测触发周期 peak detector中断检测触发周期 cmd_mipi_sr[15:0] cmd_mipi_sr[31:16],when write this reg,start the RFFE data_mipi_sr[15:0] data_mipi_sr[31:16] data_out_mipi[15:0] data_out_mipi[31:16] data_valid_byte[3:0] master_busy_mipi_dly cmd_done_status DLPF notch bypass status3 1: notch bypass when the value of dlpf_det_status is less than 3 DLPF sdm bypass DLPF notch bypass status2 1: notch bypass when the value of dlpf_det_status is less than 2 gro mode tdc cal clk out inverse gro mode phase err clk out inverse gro mode tdc cal reg clk inverse gro mode phase err reg clk inverse DLPF MDLL mode 000: 26x2MHz 001: 26x3MHz 010: 26x4MHz 011: 26x5MHz 100: 26x6MHz 101: 26x7MHz 110: 26x8MHz 111: 26x9MHz DLPF notch bypass DLPF output clock inverse DLPF input clock inverse DLPF lock mode enable DLPF DLPF output direct control DLPF output direct value DLPF afc phase offset DLPF kdco phase offset DLPF gain kp afc DLPF gain ki afc DLPF gain kp 2m DLPF gain ki 2m DLPF gain kp 200k DLPF gain ki 200k DLPF IIR0 gain0[15:0] DLPF IIR0 gain1[15:0] DLPF IIR1 gain0[15:0] DLPF IIR1 gain1[15:0] DLPF IIR1 gain1[16] DLPF IIR1 gain0[16] DLPF IIR0 gain1[16] DLPF IIR0 gain0[16] dlpf_diff_sel value is set to reserved value afc_diff_thr[15:0] afc_diff_thr[31:16] minimum value of afc_cnt_thr is 5 lock_2m_diff_thr[15:0] lock_2m_diff_thr[31:16] minimum value of lock_2m_cnt_thr is 5 lock_200k_diff_thr[15:0] lock_200k_diff_thr[31:16] minimum value of lock_200k_cnt_thr is 5 timer0_cnt[15:0] timer0_cnt[31:16] timer1_cnt[15:0] timer1_cnt[31:16] timer2_cnt[15:0] timer2_cnt[31:16] DLPF capture enable to dump internal values real time afc_code DLPF detect status read time kdco_code captured afc_code captured kdco_code tdc_code dlpf_sum0[15:0] dlpf_sum0[31:16] dlpf_sum0[38:32] iir0_data[15:0] iir0_data[31:16] iir1_data[15:0] iir1_data[31:16] 1: pu_bbpll2 by reg 0: pu_bbpll2 by idle hw 1:寄存器配置打开BBPLL2 1:寄存器配置打开BBPLL1 1：打开clk 26m aux1 1：打开clk 26m tsx adc时钟 1：打开clk 26m osc adc时钟 1：寄存器配置lte rx on，为bitmap模块冲突使用，功能同TXRX硬件送出的lte rx on 1：lte抢占gnss射频指示bit，送给gnss后，gnss模块内部iq置0 1：gnss中断屏蔽bit 1：gnss adc时钟选择gnss pll 66/33m 0：gnss adc时钟选择wifi pll 66/33m，在LTE紧急抢占gnss射频时，打开bbpll1稳定后，时钟切换到bbpll1 1：gnss adc使用wifi pll 66/33m时钟前使能 1：gnss pp时钟选择gnss pll 66/33m 0：gnss pp时钟选择wifi pll 66/33m，在LTE紧急抢占gnss射频时，打开bbpll1稳定后，时钟切换到bbpll1 1：gnss pp使用wifi pll 66/33m时钟前使能 1：capture gnss ae/te指针 1：送给LTE的IQ源头置0 1：送给WIFI的IQ源头置0 1：送给GNSS的IQ源头置0 1:riscv ram时钟auto gate使能 1：aon访问rf的ahb async bridge slave端时钟auto gate使能 1：aon访问rf的ahb async bridge master端时钟auto gate使能 1：aon访问rf的ahb async bridge early response使能 1：rf访问aon的ahb async bridge slave端时钟auto gate使能 1：rf访问aon的ahb async bridge master端时钟auto gate使能 1：rf访问aon的ahb async bridge early response使能 1：power detector adc时钟反向 1:adda test mode=5,rxdlpf mode, debug data sel dafc and tdc_code 0:adda test mode=5,rxdlpf mode, debug data sel kdco and tdc_code 1:adda test mode=4,txdlpf mode, debug data sel dafc and tdc_code 0:adda test mode=4,txdlpf mode, debug data sel kdco and tdc_code 1：osc温度计adc时钟反向 1：tsx温度计adc时钟反向 1：rf analog 测试pad输出使能 0：rf analog 测试pad输出high-z 1：riscv接收AHB response error屏蔽 dfe dump数据截位选择： 000：原始dfe dump数据输出 001：低4位丢弃 001：低3位丢弃 010：低2位丢弃 011：低1位丢弃 1：adc输入时钟反沿 1：输出给rf analog的rtc时钟反沿 1：输出给rf analog的dac时钟反沿 1：输出给rf analog的dac时钟使能 1：rxdlpf复位 1：txdlpf复位 1：dfe osc temper复位 1：dfe tsx temper复位 1：dfe pwd复位 1：dfe tx通道复位 1：dfe rx通道复位 1：dfe clkrst复位 no use 1：mipi时钟选择13m 0：mipi时钟选择26m 1：usid改变时多发一条trigger命令 1：送给rf analog的osc 26m时钟auto gate使能 1：送给rf analog的tsx 26m时钟auto gate使能 1：送给rf analog的bbpll2 122.88m时钟auto gate使能 1：送给rf analog的bbpll2 245.76m时钟auto gate使能 1：送给rf analog的bbpll1 80m时钟auto gate使能 1：aon访问rf通路的AHB async bridge时钟auto gate使能 1：rf访问aon通路的AHB async bridge时钟auto gate使能 1：dfe源头245.76m时钟使能，always 1 1：rf dig使用的26m时钟使能，always 1 1：rf_dig的ahb时钟使能，always 1 1：ahb时钟自动切换使能，当rg_cgm_chb_sel【1：0】配置选择到的时钟对应PLL源头未打开，ahb时钟自动切换到26m 00：dcxo 26m 01：wifi bbpll 80m 10：lte bbpll 122.88m 11：gnss pll 133m 1：ATE模式下的tsen bist模块时钟使能 1：送到PAD的tsx时钟使能 1：送给DFE的tsx时钟使能 1：送到PAD的osc时钟使能 1：dfe osc时钟源头使能 1：dfe adc时钟源头使能 1：dfe pwd时钟源头使能 1：peak detector功能26m时钟使能 1：bbpll2 sdm模块26m时钟使能 1：bbpll1 sdm模块26m时钟使能 1：txpll calibration模块26m时钟使能 1：rxpll calibration模块26m时钟使能 1：rf interface reg模块26m时钟使能 1：rffe接口和功能时钟使能 1：rtc接口时钟使能 1：rf bitmap模块时钟使能 1：wdg模块时钟使能 1：timer模块时钟使能 1：riscv时钟使能 1：aon访问rf AHB通路时钟使能 1：rf访问aon AHB通路时钟使能 1：txdlpf接口时钟使能 1：rxdlpf接口时钟使能 1：spi2ahb模块接口时钟使能 1：riscv ram接口时钟使能 1：rf interface reg模块ahb接口时钟使能 1：dfe模块接口时钟使能 1：总线matrix时钟使能 1：rxdlpf gro out2时钟源头使能 1：rxdlpf gro out1时钟源头使能 1：txdlpf gro out2时钟源头使能 1：txdlpf gro out1时钟源头使能 1：rxpll sdm时钟源头使能 1：txpll sdm时钟源头使能 1：lte bbpll sdm时钟源头使能 1：wifi bbpll sdm时钟源头使能 1：osc时钟稳定时间等待功能bypass 0：硬件判断到pu和enable拉高后自动打开 1：tsx时钟稳定时间等待功能bypass 0：硬件判断到pu和enable拉高后自动打开 1：adc时钟稳定时间等待功能bypass 0：硬件判断到pu和enable拉高后自动打开 1：bbpll2时钟稳定时间等待功能bypass 0：硬件判断到pu和lock拉高后自动打开 1：bbpll2时钟稳定时间等待功能bypass 0：硬件判断到pu和lock拉高后自动打开 1：bbpll1时钟稳定时间等待功能bypass 0：硬件判断到pu和lock拉高后自动打开 1：gnss pll时钟稳定时间等待功能bypass 0：硬件判断到pu和lock拉高后自动打开 1：gnss pll时钟稳定时间等待功能bypass 0：硬件判断到pu和lock拉高后自动打开 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：软件不参与时钟稳定时间判断，由硬件决定 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：当wait auto gate sel=0时，软件强制打开对应时钟 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：硬件auto gating使能 1：当auto gate sel=0时，软件强制打开对应时钟 1：当auto gate sel=1时，软件强制打开对应时钟 1：当auto gate sel=2时，软件强制打开对应时钟 1：当auto gate sel=3时，软件强制打开对应时钟 1：当auto gate sel=4时，软件强制打开对应时钟 1：当auto gate sel=5时，软件强制打开对应时钟 1：当auto gate sel=6时，软件强制打开对应时钟 1：当auto gate sel=7时，软件强制打开对应时钟 1：当auto gate sel=8时，软件强制打开对应时钟 1：当auto gate sel=9时，软件强制打开对应时钟 1：当auto gate sel=10时，软件强制打开对应时钟 1：当auto gate sel=11时，软件强制打开对应时钟 1：当auto gate sel=12时，软件强制打开对应时钟 1：当auto gate sel=14时，软件强制打开对应时钟 1：当auto gate sel=15时，软件强制打开对应时钟 1：当auto gate sel=16时，软件强制打开对应时钟 1：当auto gate sel=17时，软件强制打开对应时钟 1：当auto gate sel=18时，软件强制打开对应时钟 1：当auto gate sel=19时，软件强制打开对应时钟 1：当auto gate sel=20时，软件强制打开对应时钟 1：当auto gate sel=21时，软件强制打开对应时钟 1：当auto gate sel=22时，软件强制打开对应时钟 1：当auto gate sel=23时，软件强制打开对应时钟 1：当auto gate sel=24时，软件强制打开对应时钟 1：当auto gate sel=25时，软件强制打开对应时钟 1：当auto gate sel=26时，软件强制打开对应时钟 1：当auto gate sel=27时，软件强制打开对应时钟 1：当auto gate sel=28时，软件强制打开对应时钟 1：ATE模式使用的tsen bist模块复位 1：bitmap模块复位 1：rf访问aon的AHB async bridge复位 1：aon访问rf的AHB async bridge复位 1：dfe寄存器模块复位 1：rf interface模块clk div复位 1：rf interface模块irq handler复位 1：rf interface模块peak det复位 1：rf interface模块寄存器复位 1：spi2ahb模块复位 1：riscv访问rf dig rtc接口复位 1：rf analog reg模块复位 1：rffe模块复位 1：wdg模块复位 1：timer0模块复位 1：rxdlpf模块寄存器复位 1：txdlpf模块寄存器复位 1：riscv ram模块接口复位 1：riscv模块debug功能复位 1：riscv核复位 1：rfdig gpio输出值 1：rfidg gpio输入使能 1：当rg_simc_pa_en=0时，PA大功率发射时simc auto gate功能软件使能 1：APC发射功率超过rg_simc_pa_on_th门限时，产生simc auto gate信号送给simc simc功能PA发射功率门限 1：sysctrl模块寄存器软复位 1：送给rf analog的gro rst信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 1：rf analog送给dlpf的dlpf rstn信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 1：送给rf analog的vco pkdet功能由AAFC校准产生的vco pkdet硬件决定，软件不参与 1：送给rf analog的open_en信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 1：送给rf analog的gro rst信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 1：rf analog送给dlpf的dlpf rstn信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 1：送给rf analog的vco pkdet功能由AAFC校准产生的vco pkdet硬件决定，软件不参与 1：送给rf analog的open_en信号由AAFC校准产生的OPEN_EN硬件决定，软件不参与 adda测试模式选择： 000：adc测试模式，数据不经过dfe直接到ram 001：adc测试模式，数据经过dfe直接到ram 010：dfe dump数据到ram 011：dac测试模式 100：txdlpf测试模式 101：txdlpf测试模式 110：rxdlpf测试模式 111：rxdlpf测试模式 1：进入adda测试模式 1：dac测试模式数据从ram自动发出不经过dfe 0：dac测试模式数据从ram发出后经过dfe 1：adda测试读写数据使能 1：adda测试模式复位 rfdig gpio输入信号 rfdig monitor信号寄存器可读 wifi agc gain table0，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table1，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table2，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table3，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table4，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table5，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table6，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table7，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table8，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table9，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table10，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table11，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table12，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table13，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table14，硬件根据wlan基带输出的auto gac index自动选择 wifi agc gain table15，硬件根据wlan基带输出的auto gac index自动选择 wlan基带输出的auto gac index，寄存器可读 1：WIFI接收模式，送给rf analog的agc gain由auto gac index选择wifi_gain0-15寄存器，送给rf analog的wifi gain pga/rxflt dccal i/q选择寄存器 0：LTE和GNSS模式，送给rf analog的agc gain、pga/rxflt dccal i/q由软件配置 00：送给rf analog的pga I路校准信号选择寄存器 01：送给rf analog的pga I路校准信号选择dfe输出的dac sine补码 10：送给rf analog的pga I路校准信号选择dfe输出的dac sine原码 11：送给rf analog的pga I路校准信号选择0 00：送给rf analog的pga Q路校准信号选择寄存器 01：送给rf analog的pga Q路校准信号选择dfe输出的dac sine补码 10：送给rf analog的pga Q路校准信号选择dfe输出的dac sine原码 11：送给rf analog的pga Q路校准信号选择0 送给rf analog的pga I路校准信号选择dfe输出的dac sine补上固定offset 送给rf analog的pga Q路校准信号选择dfe输出的dac sine补上固定offset 经过ahb clk自动切换后的ahb freq sel值，只读 硬化的乘法器输出 1：txpll gro上电选择硬件时序 1：rxpll gro上电选择硬件时序 txpll/rxpll gro上电稳定时间 LTE2GNSS RX时：adc_enh_bb_force=0，强制关闭ADC使能，即adc_enh_bb=0；adc_enh_bb_force=1，ADC使能恢复，受rg_adc_auto_ctrl_en或软件寄存器控制 LTE2GNSS RX时：adc_clk_enh_bb_force=0，强制关闭ADC时钟使能，即adc_clk_enh_bb=0；adc_clk_enh_bb_force=1，ADC时钟使能恢复，受rg_adc_auto_ctrl_en或软件寄存器控制 1：adc开关选择硬件时序 adc bias拉高稳定时间 adc clk enh拉高稳定时间 1：pwdadc开关选择硬件时序 pwdadc bias拉高稳定时间 pwdadc clk enh拉高稳定时间 wifi gain table0对应的Q路pga dc校准补偿值 wifi gain table0对应的I路pga dc校准补偿值 wifi gain table1对应的Q路pga dc校准补偿值 wifi gain table1对应的I路pga dc校准补偿值 wifi gain table2对应的Q路pga dc校准补偿值 wifi gain table2对应的I路pga dc校准补偿值 wifi gain table3对应的Q路pga dc校准补偿值 wifi gain table3对应的I路pga dc校准补偿值 wifi gain table4对应的Q路pga dc校准补偿值 wifi gain table4对应的I路pga dc校准补偿值 wifi gain table5对应的Q路pga dc校准补偿值 wifi gain table5对应的I路pga dc校准补偿值 wifi gain table6对应的Q路pga dc校准补偿值 wifi gain table6对应的I路pga dc校准补偿值 wifi gain table7对应的Q路pga dc校准补偿值 wifi gain table7对应的I路pga dc校准补偿值 wifi gain table8对应的Q路pga dc校准补偿值 wifi gain table8对应的I路pga dc校准补偿值 wifi gain table9对应的Q路pga dc校准补偿值 wifi gain table9对应的I路pga dc校准补偿值 wifi gain table10对应的Q路pga dc校准补偿值 wifi gain table10对应的I路pga dc校准补偿值 wifi gain table11对应的Q路pga dc校准补偿值 wifi gain table11对应的I路pga dc校准补偿值 wifi gain table12对应的Q路pga dc校准补偿值 wifi gain table12对应的I路pga dc校准补偿值 wifi gain table13对应的Q路pga dc校准补偿值 wifi gain table13对应的I路pga dc校准补偿值 wifi gain table14对应的Q路pga dc校准补偿值 wifi gain table14对应的I路pga dc校准补偿值 wifi gain table15对应的Q路pga dc校准补偿值 wifi gain table15对应的I路pga dc校准补偿值 wifi gain table0对应的Q路rxflt dc校准补偿值 wifi gain table0对应的I路rxflt dc校准补偿值 wifi gain table1对应的Q路rxflt dc校准补偿值 wifi gain table1对应的I路rxflt dc校准补偿值 wifi gain table2对应的Q路rxflt dc校准补偿值 wifi gain table2对应的I路rxflt dc校准补偿值 wifi gain table3对应的Q路rxflt dc校准补偿值 wifi gain table3对应的I路rxflt dc校准补偿值 wifi gain table4对应的Q路rxflt dc校准补偿值 wifi gain table4对应的I路rxflt dc校准补偿值 wifi gain table5对应的Q路rxflt dc校准补偿值 wifi gain table5对应的I路rxflt dc校准补偿值 wifi gain table6对应的Q路rxflt dc校准补偿值 wifi gain table6对应的I路rxflt dc校准补偿值 wifi gain table7对应的Q路rxflt dc校准补偿值 wifi gain table7对应的I路rxflt dc校准补偿值 wifi gain table8对应的Q路rxflt dc校准补偿值 wifi gain table8对应的I路rxflt dc校准补偿值 wifi gain table9对应的Q路rxflt dc校准补偿值 wifi gain table9对应的I路rxflt dc校准补偿值 wifi gain table10对应的Q路rxflt dc校准补偿值 wifi gain table10对应的I路rxflt dc校准补偿值 wifi gain table11对应的Q路rxflt dc校准补偿值 wifi gain table11对应的I路rxflt dc校准补偿值 wifi gain table12对应的Q路rxflt dc校准补偿值 wifi gain table12对应的I路rxflt dc校准补偿值 wifi gain table13对应的Q路rxflt dc校准补偿值 wifi gain table13对应的I路rxflt dc校准补偿值 wifi gain table14对应的Q路rxflt dc校准补偿值 wifi gain table14对应的I路rxflt dc校准补偿值 wifi gain table15对应的Q路rxflt dc校准补偿值 wifi gain table15对应的I路rxflt dc校准补偿值 DLPF notch bypass status3 1: notch bypass when the value of dlpf_det_status is less than 3 DLPF sdm bypass DLPF notch bypass status2 1: notch bypass when the value of dlpf_det_status is less than 2 gro mode tdc cal clk out inverse gro mode phase err clk out inverse gro mode tdc cal reg clk inverse gro mode phase err reg clk inverse DLPF MDLL mode 000: 26x2MHz 001: 26x3MHz 010: 26x4MHz 011: 26x5MHz 100: 26x6MHz 101: 26x7MHz 110: 26x8MHz 111: 26x9MHz DLPF notch bypass DLPF output clock inverse DLPF input clock inverse DLPF lock mode enable DLPF DLPF output direct control DLPF output direct value DLPF afc phase offset DLPF kdco phase offset DLPF gain kp afc DLPF gain ki afc DLPF gain kp 2m DLPF gain ki 2m DLPF gain kp 200k DLPF gain ki 200k DLPF IIR0 gain0[15:0] DLPF IIR0 gain1[15:0] DLPF IIR1 gain0[15:0] DLPF IIR1 gain1[15:0] DLPF IIR1 gain1[16] DLPF IIR1 gain0[16] DLPF IIR0 gain1[16] DLPF IIR0 gain0[16] dlpf_diff_sel value is set to reserved value afc_diff_thr[15:0] afc_diff_thr[31:16] minimum value of afc_cnt_thr is 5 lock_2m_diff_thr[15:0] lock_2m_diff_thr[31:16] minimum value of lock_2m_cnt_thr is 5 lock_200k_diff_thr[15:0] lock_200k_diff_thr[31:16] minimum value of lock_200k_cnt_thr is 5 timer0_cnt[15:0] timer0_cnt[31:16] timer1_cnt[15:0] timer1_cnt[31:16] timer2_cnt[15:0] timer2_cnt[31:16] DLPF capture enable to dump internal values real time afc_code DLPF detect status read time kdco_code captured afc_code captured kdco_code tdc_code dlpf_sum0[15:0] dlpf_sum0[31:16] dlpf_sum0[38:32] iir0_data[15:0] iir0_data[31:16] iir1_data[15:0] iir1_data[31:16] REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_1 REG_RD_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_1 REG_WR_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_CTRL_ADDR_ARRAY8 BIT_CTRL_ADDR_ARRAY8 the addr[32:0] of bit control array8 BIT_CTRL_ADDR_ARRAY9 BIT_CTRL_ADDR_ARRAY9 the addr[32:0] of bit control array9 BIT_CTRL_ADDR_ARRAY10 BIT_CTRL_ADDR_ARRAY10 the addr[32:0] of bit control array10 BIT_CTRL_ADDR_ARRAY11 BIT_CTRL_ADDR_ARRAY11 the addr[32:0] of bit control array11 BIT_CTRL_ADDR_ARRAY12 BIT_CTRL_ADDR_ARRAY12 the addr[32:0] of bit control array12 BIT_CTRL_ADDR_ARRAY13 BIT_CTRL_ADDR_ARRAY13 the addr[32:0] of bit control array13 BIT_CTRL_ADDR_ARRAY14 BIT_CTRL_ADDR_ARRAY14 the addr[32:0] of bit control array14 BIT_CTRL_ADDR_ARRAY15 BIT_CTRL_ADDR_ARRAY15 the addr[32:0] of bit control array15 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY15 BIT_CTRL_ARRAY15 REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_1 REG_RD_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_1 REG_WR_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_1 REG_RD_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_2 REG_RD_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_1 REG_WR_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_2 REG_WR_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_WR_CTRL_ADDR_ARRAY0 BIT_WR_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_WR_CTRL_ADDR_ARRAY1 BIT_WR_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_WR_CTRL_ADDR_ARRAY2 BIT_WR_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_WR_CTRL_ADDR_ARRAY3 BIT_WR_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_WR_CTRL_ADDR_ARRAY4 BIT_WR_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_WR_CTRL_ADDR_ARRAY5 BIT_WR_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_WR_CTRL_ADDR_ARRAY6 BIT_WR_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_WR_CTRL_ADDR_ARRAY7 BIT_WR_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_WR_CTRL_ADDR_ARRAY8 BIT_WR_CTRL_ADDR_ARRAY8 the addr[32:0] of bit control array8 BIT_WR_CTRL_ADDR_ARRAY9 BIT_WR_CTRL_ADDR_ARRAY9 the addr[32:0] of bit control array9 BIT_WR_CTRL_ADDR_ARRAY10 BIT_WR_CTRL_ADDR_ARRAY10 the addr[32:0] of bit control array10 BIT_WR_CTRL_ADDR_ARRAY11 BIT_WR_CTRL_ADDR_ARRAY11 the addr[32:0] of bit control array11 BIT_WR_CTRL_ADDR_ARRAY12 BIT_WR_CTRL_ADDR_ARRAY12 the addr[32:0] of bit control array12 BIT_WR_CTRL_ADDR_ARRAY13 BIT_WR_CTRL_ADDR_ARRAY13 the addr[32:0] of bit control array13 BIT_WR_CTRL_ADDR_ARRAY14 BIT_WR_CTRL_ADDR_ARRAY14 the addr[32:0] of bit control array14 BIT_WR_CTRL_ADDR_ARRAY15 BIT_WR_CTRL_ADDR_ARRAY15 the addr[32:0] of bit control array15 BIT_WR_CTRL_ARRAY0 BIT_WR_CTRL_ARRAY0 BIT_WR_CTRL_ARRAY1 BIT_WR_CTRL_ARRAY1 BIT_WR_CTRL_ARRAY2 BIT_WR_CTRL_ARRAY2 BIT_WR_CTRL_ARRAY3 BIT_WR_CTRL_ARRAY3 BIT_WR_CTRL_ARRAY4 BIT_WR_CTRL_ARRAY4 BIT_WR_CTRL_ARRAY5 BIT_WR_CTRL_ARRAY5 BIT_WR_CTRL_ARRAY6 BIT_WR_CTRL_ARRAY6 BIT_WR_CTRL_ARRAY7 BIT_WR_CTRL_ARRAY7 BIT_WR_CTRL_ARRAY8 BIT_WR_CTRL_ARRAY8 BIT_WR_CTRL_ARRAY9 BIT_WR_CTRL_ARRAY9 BIT_WR_CTRL_ARRAY10 BIT_WR_CTRL_ARRAY10 BIT_WR_CTRL_ARRAY11 BIT_WR_CTRL_ARRAY11 BIT_WR_CTRL_ARRAY12 BIT_WR_CTRL_ARRAY12 BIT_WR_CTRL_ARRAY13 BIT_WR_CTRL_ARRAY13 BIT_WR_CTRL_ARRAY14 BIT_WR_CTRL_ARRAY14 BIT_WR_CTRL_ARRAY15 BIT_WR_CTRL_ARRAY15 RESET_SYS_SOFT RESET_LPS_SOFT EFUSE_POR_READ_DISABLE reference "efuse_design_specification.docx" LPS_CLK_EN 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable LPS_CLK_AUTO_SEL LPS_CLK_FORCE_EN LPS_CLK_GATE_EN_STATUS LPS_CLK_BUSY_STATUS CFG_CLK_UART1 CFG_CLK_RC26M CFG_DEBUG_BOND_OPTION CFG_PSRAM_HALF_SLP 0: PSRAM macro do not in half-sleep mode when PSRAM controller power-down 1: PSRAM macro in half-sleep mode when PSRAM controller power-down CFG_LPS_AHB_CLOCK_SEL 0:rtc_32k 1:xtal_lp_26m 2:xtal_26m 3:rc_26m CFG_UART1_CLOCK_SEL 0:rtc_32k 1:xtal_lp_2tm 2:xtal_26m 3:rc_26m CFG_GPT_LITE_CLOCK_SEL 0:rtc_32k 1:xtal_lp_2tm 2:xtal_26m 3:rc_26m CFG_BOOT_MODE This contains the state of boot mode pins latched during Reset. bit 0: Force download. bit 1: EMMC boot. bit 2: Unused. CFG_RESET_ENABLE 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable RESET_CAUSE 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable CFG_PLLS 0: select hardware auto control signal 1: select bbpll_pd_force as control signal 0: power-up 1: power-down select hardware control mode:(valid when iispll_clkout_en_sel bit is "0") 0: idle_lps output signal control 1: clock plan signal auto control 0: select hardware auto control signal 1: select iispll_clkout_en_force as control signal 0: disable 1: enable 0: select hardware auto control signal 1: select iispll_pd_force as control signal 0: power-up 1: power-down 0: MPLL clock is not selected in PUB_SYS 1: MPLL clock is secected in PUB_SYS select hardware control mode:(valid when mpll_clkout_en_sel bit is "0") 0: idle_lps output signal control 1: clock plan signal auto control 0: select hardware auto control signal 1: select mpll_clkout_en_force as control signal 0: disable 1: enable 0: select hardware auto control signal 1: select mpll_pd_force as control signal 0: power-up 1: power-down 0: APLL clock is not selected in AP_SYS 1: APLL clock is secected in AP_SYS 0: APLL clock is not selected in CP_SYS 1: APLL clock is secected in CP_SYS 0: APLL clock is not selected in PUB_SYS 1: APLL clock is secected in PUB_SYS 0: APLL clock is not selected in AON_SYS 1: APLL clock is secected in AON_SYS select hardware control mode:(valid when apll_clkout_en_sel bit is "0") 0: idle_lps output signal control 1: clock plan signal auto control 0: select hardware auto control signal 1: select apll_clkout_en_force as control signal 0: disable 1: enable 0: select hardware auto control signal 1: select apll_pd_force as control signal 0: power-up 1: power-down APLL_WAIT_NUMBER From PLL_CLKOUT_EN posedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_PD negedge to PLL_RST negedge,use 26M clock count. MPLL_WAIT_NUMBER From PLL_CLKOUT_EN negedge to PLL_PRECHARGE negedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_PD negedge to PLL_RST negedge,use 26M clock count. IISMPLL_WAIT_NUMBER From PLL_CLKOUT_EN negedge to PLL_PRECHARGE negedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_RST negedge to PLL_PRECHARGE posedge(if pll_precharge_en set to "1"),use 26M clock count. From PLL_PD negedge to PLL_RST negedge,use 26M clock count. AON_IRAM_CTRL AON_IRAM2 PU_DELAY port value AON_IRAM1 PU_DELAY port value AON_IRAM0 PU_DELAY port value AON_IRAM2 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode AON_IRAM1 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode AON_IRAM0 hardware control. It work when chip in deep-sleep, and recover to normal mode when wake-up: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode AON_IRAM2 software control: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode AON_IRAM1 software control: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode AON_IRAM0 software control: 00: normal mode 01: retention mode 10: shut-down mode 11: normal mode 1: AON_IRAM2 control by aon_iram2_ctrl_hw[1:0] 0: AON_IRAM2 control by aon_iram2_ctrl_sw 1: AON_IRAM1 control by aon_iram1_ctrl_hw[1:0] 0: AON_IRAM1 control by aon_iram1_ctrl_sw 1: AON_IRAM0 control by aon_iram0_ctrl_hw[1:0] 0: AON_IRAM0 control by aon_iram0_ctrl_sw IOMUX_G4_FUNC_SEL_LATCH This bit will be set to "1" by hardware to latch G4 pad function select when deepsleep, software should write "0" to release after iomux reinitial. CFG_POR_USB_PHY power on reset,reset all state machines, 1: the transmit and receive FSM are reset, 0: the transmit and receive FSM are operational 1: ISO Cell Enable, signals will be gated and output iso value 0: ISO Cell Disable, normal mode Digital in USBPHY Power gating control (large switch), when power up ,need delay 100us after PD_S set to 1'b0; “1”: power gating the USB2.0 CORE “0”: enable the CORE power Digital in USBPHY Power gating control (small switch) “1”: power gating the USB2.0 CORE power “0”: enable the CORE power EFS_POR_READ_BLOCK3 EFS_POR_READ_BLOCK89 RC26M_PU_CTRL “1”: power up “0”: power down “1”: hw mode, RC26M PU controlled by "pd_xtal" hardware signal from IDLE_LPS module. “0”: sw mode, RC26M PU controlled by "rc26m_pu_sw" register bit. AON_AHB_LP_CTRL “0”: xtal_26m “1”: rc26m “1”: Aon ahb clock auto switch to 26M (bit[5] decide witch clock switch to) when CP_SYS in lightsleep mode(with also bit4 is "1"), and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. “0”: Disable. “1”: Aon ahb clock auto switch to 26M (bit[5] decide witch clock switch to) when AP_SYS in lightsleep mode(with also bit5 is "1"), and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. “0”: Disable. “0”: xtal_26m “1”: rc26m “1”: Aon ahb clock auto switch to RC32K when chip in deepsleep mode, and switch back when wake-up (bit[3] decide witch clock switch back to). Hardware control signal is "pd_pll" from IDLE_LPS module. “0”: Disable. “1”: Aon ahb clock auto switch to 26M (bit[3] decide witch clock switch to) when chip in deepsleep mode, and switch back to the clock witch software set(see "cgm_aon_ahb_sel_cfg" register at address 0x51508828) when wake-up. Hardware control signal is "pow_on" from IDLE_LPS module. “0”: Disable. “1”: Lps ahb clock auto switch to RC32K when chip in deepsleep mode, and switch back to the clock witch software set(see "CFG_LPS_AHB_CLOCK_SEL" register at address 0x51705030) when wake-up. Hardware control signal is "pd_pll" from IDLE_LPS module. “0”: Disable. USB_UART_SWJ_SHARE_CFG “1”: uart or swj in use “0”: USB in use “1”: swj in use(with bit1 also set to "1"). “0”: uart in use(with bit1 also set to "1"). PU_CLK26M_LP_ISO_CFG “1”: ISO cell no work. “0”: ISO work, signal clk_26m_lp clamp to "0". CFG_IO_DEEP_SLEEP 0 : software mode: dslp_io_sys1 and dslp_wp_sys1 signal controlled by bit[2] and bit[3] of this register. 1 : hardware mode: dslp_io_sys1 and dslp_wp_sys1 signal controlled by idst_cp signal of IDLE_LPS module. 0 : software mode: dslp_io_sys0 and dslp_wp_sys0 signal controlled by bit[0] and bit[1] of this register. 1 : hardware mode: dslp_io_sys0 and dslp_wp_sys0 signal controlled by idst_ap signal of IDLE_LPS module. pinmux dslp_wp_sys5 signal control. pinmux dslp_io_sys5 signal control. pinmux dslp_wp_sys4 signal control. pinmux dslp_io_sys4 signal control. pinmux dslp_wp_sys3 signal control. pinmux dslp_io_sys3 signal control. pinmux dslp_wp_sys2 signal control. pinmux dslp_io_sys2 signal control. pinmux dslp_wp_sys1 signal control. pinmux dslp_io_sys1 signal control. pinmux dslp_wp_sys0 signal control. pinmux dslp_io_sys0 signal control. CFG_LPS_IO_CORE_IE CFG_SIMC_IO 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal 0: sel hardware signal 1: sel software signal software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" software control signal, valid when related sel bit is "1" REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_1 REG_RD_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_2 REG_RD_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_3 REG_RD_CTRL_3 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_1 REG_WR_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_2 REG_WR_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_3 REG_WR_CTRL_3 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 REG_RD_CTRL_0 REG_RD_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_1 REG_RD_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_RD_CTRL_2 REG_RD_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_0 REG_WR_CTRL_0 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_1 REG_WR_CTRL_1 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. REG_WR_CTRL_2 REG_WR_CTRL_2 control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. control reg read security attribute: 0: Non security. 1: Security. BIT_CTRL_ADDR_ARRAY0 BIT_CTRL_ADDR_ARRAY0 the addr[32:0] of bit control array0 BIT_CTRL_ADDR_ARRAY1 BIT_CTRL_ADDR_ARRAY1 the addr[32:0] of bit control array1 BIT_CTRL_ADDR_ARRAY2 BIT_CTRL_ADDR_ARRAY2 the addr[32:0] of bit control array2 BIT_CTRL_ADDR_ARRAY3 BIT_CTRL_ADDR_ARRAY3 the addr[32:0] of bit control array3 BIT_CTRL_ADDR_ARRAY4 BIT_CTRL_ADDR_ARRAY4 the addr[32:0] of bit control array4 BIT_CTRL_ADDR_ARRAY5 BIT_CTRL_ADDR_ARRAY5 the addr[32:0] of bit control array5 BIT_CTRL_ADDR_ARRAY6 BIT_CTRL_ADDR_ARRAY6 the addr[32:0] of bit control array6 BIT_CTRL_ADDR_ARRAY7 BIT_CTRL_ADDR_ARRAY7 the addr[32:0] of bit control array7 BIT_CTRL_ADDR_ARRAY8 BIT_CTRL_ADDR_ARRAY8 the addr[32:0] of bit control array8 BIT_CTRL_ADDR_ARRAY9 BIT_CTRL_ADDR_ARRAY9 the addr[32:0] of bit control array9 BIT_CTRL_ADDR_ARRAY10 BIT_CTRL_ADDR_ARRAY10 the addr[32:0] of bit control array10 BIT_CTRL_ADDR_ARRAY11 BIT_CTRL_ADDR_ARRAY11 the addr[32:0] of bit control array11 BIT_CTRL_ADDR_ARRAY12 BIT_CTRL_ADDR_ARRAY12 the addr[32:0] of bit control array12 BIT_CTRL_ADDR_ARRAY13 BIT_CTRL_ADDR_ARRAY13 the addr[32:0] of bit control array13 BIT_CTRL_ADDR_ARRAY14 BIT_CTRL_ADDR_ARRAY14 the addr[32:0] of bit control array14 BIT_CTRL_ADDR_ARRAY15 BIT_CTRL_ADDR_ARRAY15 the addr[32:0] of bit control array15 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY0 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY1 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY2 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY3 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY4 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY5 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY6 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY7 BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY8 BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY9 BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY10 BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY11 BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY12 BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY13 BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY14 BIT_CTRL_ARRAY15 BIT_CTRL_ARRAY15 port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. Interrupt enable reg Interrupt enable reg Port 0 read channel address miss int enable 1: Enable 0: Disable Port 0 write channel address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read channel address miss int write-clear Port 0 write channel address miss int write-clear Original interrupt reg %d Original interrupt reg %d Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Final interrupt reg %d Final interrupt reg %d Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal rd 0 sec control rd 0 sec control control uart1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control idle_lps_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control apb_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control keypad_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pwrctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rtc_timer_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control lps_ifc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 0 sec control wr 0 sec control control uart1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control idle_lps_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control apb_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control keypad_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pwrctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control rtc_timer_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control lps_ifc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access id0 first_addr control id0 first_addr control id0 last_addr control id0 last_addr control id0 mstid_0 master id control id0 mstid_0 master id control id0 mstid_1 master id control id0 mstid_1 master id control id0 mstid_2 master id control id0 mstid_2 master id control id0 mstid_3 master id control id0 mstid_3 master id control id0 mstid_4 master id control id0 mstid_4 master id control id0 mstid_5 master id control id0 mstid_5 master id control id0 mstid_6 master id control id0 mstid_6 master id control id0 mstid_7 master id control id0 mstid_7 master id control id1 first_addr control id1 first_addr control id1 last_addr control id1 last_addr control id1 mstid_0 master id control id1 mstid_0 master id control id1 mstid_1 master id control id1 mstid_1 master id control id1 mstid_2 master id control id1 mstid_2 master id control id1 mstid_3 master id control id1 mstid_3 master id control id1 mstid_4 master id control id1 mstid_4 master id control id1 mstid_5 master id control id1 mstid_5 master id control id1 mstid_6 master id control id1 mstid_6 master id control id1 mstid_7 master id control id1 mstid_7 master id control clk_gate_bypass clk_gate_bypass 0: don't response error; 1: response error. clk_gate_bypass port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. Interrupt enable reg Interrupt enable reg Port 0 read channel address miss int enable 1: Enable 0: Disable Port 0 write channel address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read channel address miss int write-clear Port 0 write channel address miss int write-clear Original interrupt reg %d Original interrupt reg %d Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Final interrupt reg %d Final interrupt reg %d Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal rd 0 sec control rd 0 sec control control uart4_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart5_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart6_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sdmmc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control camera_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_ifc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 0 sec control wr 0 sec control control uart4_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart5_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart6_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sdmmc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control camera_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_ifc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access id0 first_addr control id0 first_addr control id0 last_addr control id0 last_addr control id0 mstid_0 master id control id0 mstid_0 master id control id0 mstid_1 master id control id0 mstid_1 master id control id0 mstid_2 master id control id0 mstid_2 master id control id0 mstid_3 master id control id0 mstid_3 master id control id0 mstid_4 master id control id0 mstid_4 master id control id0 mstid_5 master id control id0 mstid_5 master id control id0 mstid_6 master id control id0 mstid_6 master id control id0 mstid_7 master id control id0 mstid_7 master id control id1 first_addr control id1 first_addr control id1 last_addr control id1 last_addr control id1 mstid_0 master id control id1 mstid_0 master id control id1 mstid_1 master id control id1 mstid_1 master id control id1 mstid_2 master id control id1 mstid_2 master id control id1 mstid_3 master id control id1 mstid_3 master id control id1 mstid_4 master id control id1 mstid_4 master id control id1 mstid_5 master id control id1 mstid_5 master id control id1 mstid_6 master id control id1 mstid_6 master id control id1 mstid_7 master id control id1 mstid_7 master id control id2 first_addr control id2 first_addr control id2 last_addr control id2 last_addr control id2 mstid_0 master id control id2 mstid_0 master id control id2 mstid_1 master id control id2 mstid_1 master id control id2 mstid_2 master id control id2 mstid_2 master id control id2 mstid_3 master id control id2 mstid_3 master id control id2 mstid_4 master id control id2 mstid_4 master id control id2 mstid_5 master id control id2 mstid_5 master id control id2 mstid_6 master id control id2 mstid_6 master id control id2 mstid_7 master id control id2 mstid_7 master id control id3 first_addr control id3 first_addr control id3 last_addr control id3 last_addr control id3 mstid_0 master id control id3 mstid_0 master id control id3 mstid_1 master id control id3 mstid_1 master id control id3 mstid_2 master id control id3 mstid_2 master id control id3 mstid_3 master id control id3 mstid_3 master id control id3 mstid_4 master id control id3 mstid_4 master id control id3 mstid_5 master id control id3 mstid_5 master id control id3 mstid_6 master id control id3 mstid_6 master id control id3 mstid_7 master id control id3 mstid_7 master id control id4 first_addr control id4 first_addr control id4 last_addr control id4 last_addr control id4 mstid_0 master id control id4 mstid_0 master id control id4 mstid_1 master id control id4 mstid_1 master id control id4 mstid_2 master id control id4 mstid_2 master id control id4 mstid_3 master id control id4 mstid_3 master id control id4 mstid_4 master id control id4 mstid_4 master id control id4 mstid_5 master id control id4 mstid_5 master id control id4 mstid_6 master id control id4 mstid_6 master id control id4 mstid_7 master id control id4 mstid_7 master id control id5 first_addr control id5 first_addr control id5 last_addr control id5 last_addr control id5 mstid_0 master id control id5 mstid_0 master id control id5 mstid_1 master id control id5 mstid_1 master id control id5 mstid_2 master id control id5 mstid_2 master id control id5 mstid_3 master id control id5 mstid_3 master id control id5 mstid_4 master id control id5 mstid_4 master id control id5 mstid_5 master id control id5 mstid_5 master id control id5 mstid_6 master id control id5 mstid_6 master id control id5 mstid_7 master id control id5 mstid_7 master id control clk_gate_bypass clk_gate_bypass 0: don't response error; 1: response error. clk_gate_bypass port0 default address, bit 0 ~ 26. port0 default address, bit 0 ~ 26. Interrupt enable reg Interrupt enable reg Port 0 read channel address miss int enable 1: Enable 0: Disable Port 0 write channel address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read channel address miss int write-clear Port 0 write channel address miss int write-clear Original interrupt reg %d Original interrupt reg %d Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Final interrupt reg %d Final interrupt reg %d Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal rd 0 sec control rd 0 sec control control emmc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control lzma_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_imem_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_busmon_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control apb_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gouda_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_0_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_wd_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer5_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_clk_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access rd 1 sec control rd 1 sec control control spiflash1_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spiflash2_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gouda_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_axidma_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control usb_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control med_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_pub_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_sec_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 0 sec control wr 0 sec control control emmc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control lzma_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_imem_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_busmon_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control apb_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gouda_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_0_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_wd_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer1_1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control timer5_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_clk_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 1 sec control wr 1 sec control control spiflash1_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spiflash2_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gouda_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ap_axidma_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control usb_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control med_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_pub_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ce_sec_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access id0 first_addr control id0 first_addr control id0 last_addr control id0 last_addr control id0 mstid_0 master id control id0 mstid_0 master id control id0 mstid_1 master id control id0 mstid_1 master id control id0 mstid_2 master id control id0 mstid_2 master id control id0 mstid_3 master id control id0 mstid_3 master id control id0 mstid_4 master id control id0 mstid_4 master id control id0 mstid_5 master id control id0 mstid_5 master id control id0 mstid_6 master id control id0 mstid_6 master id control id0 mstid_7 master id control id0 mstid_7 master id control id1 first_addr control id1 first_addr control id1 last_addr control id1 last_addr control id1 mstid_0 master id control id1 mstid_0 master id control id1 mstid_1 master id control id1 mstid_1 master id control id1 mstid_2 master id control id1 mstid_2 master id control id1 mstid_3 master id control id1 mstid_3 master id control id1 mstid_4 master id control id1 mstid_4 master id control id1 mstid_5 master id control id1 mstid_5 master id control id1 mstid_6 master id control id1 mstid_6 master id control id1 mstid_7 master id control id1 mstid_7 master id control id2 first_addr control id2 first_addr control id2 last_addr control id2 last_addr control id2 mstid_0 master id control id2 mstid_0 master id control id2 mstid_1 master id control id2 mstid_1 master id control id2 mstid_2 master id control id2 mstid_2 master id control id2 mstid_3 master id control id2 mstid_3 master id control id2 mstid_4 master id control id2 mstid_4 master id control id2 mstid_5 master id control id2 mstid_5 master id control id2 mstid_6 master id control id2 mstid_6 master id control id2 mstid_7 master id control id2 mstid_7 master id control id3 first_addr control id3 first_addr control id3 last_addr control id3 last_addr control id3 mstid_0 master id control id3 mstid_0 master id control id3 mstid_1 master id control id3 mstid_1 master id control id3 mstid_2 master id control id3 mstid_2 master id control id3 mstid_3 master id control id3 mstid_3 master id control id3 mstid_4 master id control id3 mstid_4 master id control id3 mstid_5 master id control id3 mstid_5 master id control id3 mstid_6 master id control id3 mstid_6 master id control id3 mstid_7 master id control id3 mstid_7 master id control id4 first_addr control id4 first_addr control id4 last_addr control id4 last_addr control id4 mstid_0 master id control id4 mstid_0 master id control id4 mstid_1 master id control id4 mstid_1 master id control id4 mstid_2 master id control id4 mstid_2 master id control id4 mstid_3 master id control id4 mstid_3 master id control id4 mstid_4 master id control id4 mstid_4 master id control id4 mstid_5 master id control id4 mstid_5 master id control id4 mstid_6 master id control id4 mstid_6 master id control id4 mstid_7 master id control id4 mstid_7 master id control id5 first_addr control id5 first_addr control id5 last_addr control id5 last_addr control id5 mstid_0 master id control id5 mstid_0 master id control id5 mstid_1 master id control id5 mstid_1 master id control id5 mstid_2 master id control id5 mstid_2 master id control id5 mstid_3 master id control id5 mstid_3 master id control id5 mstid_4 master id control id5 mstid_4 master id control id5 mstid_5 master id control id5 mstid_5 master id control id5 mstid_6 master id control id5 mstid_6 master id control id5 mstid_7 master id control id5 mstid_7 master id control clk_gate_bypass clk_gate_bypass 0: don't response error; 1: response error. clk_gate_bypass port0 default address, bit 0 ~ 15. port0 default address, bit 0 ~ 15. Interrupt enable reg Interrupt enable reg Port 0 read channel address miss int enable 1: Enable 0: Disable Port 0 write channel address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read channel address miss int write-clear Port 0 write channel address miss int write-clear Original interrupt reg %d Original interrupt reg %d Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Final interrupt reg %d Final interrupt reg %d Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal rd 0 sec control rd 0 sec control control uart2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dbg_uart_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aif_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_ifc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dbg_host_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 0 sec control wr 0 sec control control uart2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control uart3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dbg_uart_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aif_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_ifc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dbg_host_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access id0 first_addr control id0 first_addr control id0 last_addr control id0 last_addr control id0 mstid_0 master id control id0 mstid_0 master id control id0 mstid_1 master id control id0 mstid_1 master id control id0 mstid_2 master id control id0 mstid_2 master id control id0 mstid_3 master id control id0 mstid_3 master id control id0 mstid_4 master id control id0 mstid_4 master id control id0 mstid_5 master id control id0 mstid_5 master id control id0 mstid_6 master id control id0 mstid_6 master id control id0 mstid_7 master id control id0 mstid_7 master id control id1 first_addr control id1 first_addr control id1 last_addr control id1 last_addr control id1 mstid_0 master id control id1 mstid_0 master id control id1 mstid_1 master id control id1 mstid_1 master id control id1 mstid_2 master id control id1 mstid_2 master id control id1 mstid_3 master id control id1 mstid_3 master id control id1 mstid_4 master id control id1 mstid_4 master id control id1 mstid_5 master id control id1 mstid_5 master id control id1 mstid_6 master id control id1 mstid_6 master id control id1 mstid_7 master id control id1 mstid_7 master id control clk_gate_bypass clk_gate_bypass 0: don't response error; 1: response error. clk_gate_bypass port0 default address, bit 0 ~ 26. port0 default address, bit 0 ~ 26. Interrupt enable reg Interrupt enable reg Port 0 read channel address miss int enable 1: Enable 0: Disable Port 0 write channel address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read channel address miss int write-clear Port 0 write channel address miss int write-clear Original interrupt reg %d Original interrupt reg %d Port 0 read channel address miss original int 1: Address Miss 0: Normal Port 0 write channel address miss original int 1: Address Miss 0: Normal Final interrupt reg %d Final interrupt reg %d Port 0 read channel address miss final int 1: Address Miss 0: Normal Port 0 write channel address miss final int 1: Address Miss 0: Normal rd 0 sec control rd 0 sec control control idle_timer_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_clk_pre_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_clk_core_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aud_2ad_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control djtag_cfg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dmc400_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control psram_phy_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pagespy_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pub_apb_reg_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dap_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pub_nic_gpv_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access rd 1 sec control rd 1 sec control control spinlock_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_sp0_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_sp1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control efuse_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control tzpc_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap1_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control mon_ctrl_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio2_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c3_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control scc_top_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sysmail_rd_sec rd security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 0 sec control wr 0 sec control control idle_timer_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_clk_pre_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aon_clk_core_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control aud_2ad_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control spi2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpt1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control djtag_cfg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control iomux_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dmc400_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control psram_phy_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pagespy_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pub_apb_reg_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control dap_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control pub_nic_gpv_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access wr 1 sec control wr 1 sec control control spinlock_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_sp0_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control adi_mst_sp1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control efuse_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control tzpc_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sys_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control ana_wrap1_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control mon_ctrl_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control gpio2_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control i2c3_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control scc_top_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access control sysmail_wr_sec wr security attribute: 2'b00: security/non-security can't access 2'b01: security access only 2'b10: non-security access ony 2'b11: security/non-security access id0 first_addr control id0 first_addr control id0 last_addr control id0 last_addr control id0 mstid_0 master id control id0 mstid_0 master id control id0 mstid_1 master id control id0 mstid_1 master id control id0 mstid_2 master id control id0 mstid_2 master id control id0 mstid_3 master id control id0 mstid_3 master id control id0 mstid_4 master id control id0 mstid_4 master id control id0 mstid_5 master id control id0 mstid_5 master id control id0 mstid_6 master id control id0 mstid_6 master id control id0 mstid_7 master id control id0 mstid_7 master id control id1 first_addr control id1 first_addr control id1 last_addr control id1 last_addr control id1 mstid_0 master id control id1 mstid_0 master id control id1 mstid_1 master id control id1 mstid_1 master id control id1 mstid_2 master id control id1 mstid_2 master id control id1 mstid_3 master id control id1 mstid_3 master id control id1 mstid_4 master id control id1 mstid_4 master id control id1 mstid_5 master id control id1 mstid_5 master id control id1 mstid_6 master id control id1 mstid_6 master id control id1 mstid_7 master id control id1 mstid_7 master id control id2 first_addr control id2 first_addr control id2 last_addr control id2 last_addr control id2 mstid_0 master id control id2 mstid_0 master id control id2 mstid_1 master id control id2 mstid_1 master id control id2 mstid_2 master id control id2 mstid_2 master id control id2 mstid_3 master id control id2 mstid_3 master id control id2 mstid_4 master id control id2 mstid_4 master id control id2 mstid_5 master id control id2 mstid_5 master id control id2 mstid_6 master id control id2 mstid_6 master id control id2 mstid_7 master id control id2 mstid_7 master id control id3 first_addr control id3 first_addr control id3 last_addr control id3 last_addr control id3 mstid_0 master id control id3 mstid_0 master id control id3 mstid_1 master id control id3 mstid_1 master id control id3 mstid_2 master id control id3 mstid_2 master id control id3 mstid_3 master id control id3 mstid_3 master id control id3 mstid_4 master id control id3 mstid_4 master id control id3 mstid_5 master id control id3 mstid_5 master id control id3 mstid_6 master id control id3 mstid_6 master id control id3 mstid_7 master id control id3 mstid_7 master id control id4 first_addr control id4 first_addr control id4 last_addr control id4 last_addr control id4 mstid_0 master id control id4 mstid_0 master id control id4 mstid_1 master id control id4 mstid_1 master id control id4 mstid_2 master id control id4 mstid_2 master id control id4 mstid_3 master id control id4 mstid_3 master id control id4 mstid_4 master id control id4 mstid_4 master id control id4 mstid_5 master id control id4 mstid_5 master id control id4 mstid_6 master id control id4 mstid_6 master id control id4 mstid_7 master id control id4 mstid_7 master id control id5 first_addr control id5 first_addr control id5 last_addr control id5 last_addr control id5 mstid_0 master id control id5 mstid_0 master id control id5 mstid_1 master id control id5 mstid_1 master id control id5 mstid_2 master id control id5 mstid_2 master id control id5 mstid_3 master id control id5 mstid_3 master id control id5 mstid_4 master id control id5 mstid_4 master id control id5 mstid_5 master id control id5 mstid_5 master id control id5 mstid_6 master id control id5 mstid_6 master id control id5 mstid_7 master id control id5 mstid_7 master id control clk_gate_bypass clk_gate_bypass 0: don't response error; 1: response error. clk_gate_bypass mst_filter_id0 mst_filter_id0 mst_filter_id1 mst_filter_id1 mst_filter_id2 mst_filter_id2 mst_filter_id3 mst_filter_id3 mst_filter_id4 mst_filter_id4 mst_filter_id5 mst_filter_id5 mst_filter_id6 mst_filter_id6 mst_filter_id7 mst_filter_id7 Interrupt enable reg Interrupt enable reg read/write channel address miss int enable 1: Enable 0: Disable Original interrupt reg Original interrupt reg read/write channel address miss original int 1: Address Miss 0: Normal Interrupt status reg Interrupt status reg read/write channel address miss final int 1: Address Miss 0: Normal Interrupt write-clear reg Interrupt write-clear reg read/write channel address miss int write-clear debug register debug register debug register debug register when miss, latch hauser response error reg responce error reg read/write channel address miss int write-clear mst_filter_id0 mst_filter_id0 mst_filter_id1 mst_filter_id1 mst_filter_id2 mst_filter_id2 mst_filter_id3 mst_filter_id3 mst_filter_id4 mst_filter_id4 mst_filter_id5 mst_filter_id5 mst_filter_id6 mst_filter_id6 mst_filter_id7 mst_filter_id7 Interrupt enable reg Interrupt enable reg read/write channel address miss int enable 1: Enable 0: Disable Original interrupt reg Original interrupt reg read/write channel address miss original int 1: Address Miss 0: Normal Interrupt status reg Interrupt status reg read/write channel address miss final int 1: Address Miss 0: Normal Interrupt write-clear reg Interrupt write-clear reg read/write channel address miss int write-clear debug register debug register debug register debug register when miss, latch hauser response error reg responce error reg read/write channel address miss int write-clear default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). clock gate bypass clock gate bypass 0: don't response error; 1: response error. clock gate bypass Interrupt enable reg Interrupt enable reg Port 0 write address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 write address miss int write-clear Original interrupt reg Original interrupt reg Port 0 write address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 write address miss final int 1: Address Miss 0: Normal Interrupt enable reg Interrupt enable reg Port 0 read address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read address miss int write-clear Original interrupt reg Original interrupt reg Port 0 read address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 read address miss final int 1: Address Miss 0: Normal Debug address register for port 0 write channel Debug address register for port 0 write channel Port 0 write channel address, 1K-Byte Debug id register for port 0 write channel Debug id register for port 0 write channel Port 0 write channel id, MSB is prot[1] Debug address register for port 0 read channel Debug address register for port 0 read channel Port 0 read channel address, 1K-Byte Debug id register for port 0 read channel Debug id register for port 0 read channel Port 0 read channel id, MSB is prot[1] Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). clock gate bypass clock gate bypass 0: don't response error; 1: response error. clock gate bypass Interrupt enable reg Interrupt enable reg Port 0 write address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 write address miss int write-clear Original interrupt reg Original interrupt reg Port 0 write address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 write address miss final int 1: Address Miss 0: Normal Interrupt enable reg Interrupt enable reg Port 0 read address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read address miss int write-clear Original interrupt reg Original interrupt reg Port 0 read address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 read address miss final int 1: Address Miss 0: Normal Debug address register for port 0 write channel Debug address register for port 0 write channel Port 0 write channel address, 1K-Byte Debug id register for port 0 write channel Debug id register for port 0 write channel Port 0 write channel id, MSB is prot[1] Debug address register for port 0 read channel Debug address register for port 0 read channel Port 0 read channel address, 1K-Byte Debug id register for port 0 read channel Debug id register for port 0 read channel Port 0 read channel id, MSB is prot[1] Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default r address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). default w address 0 register(1K-Byte address, bit 26 ~ bit 10). clock gate bypass clock gate bypass 0: don't response error; 1: response error. clock gate bypass Interrupt enable reg Interrupt enable reg Port 0 write address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 write address miss int write-clear Original interrupt reg Original interrupt reg Port 0 write address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 write address miss final int 1: Address Miss 0: Normal Interrupt enable reg Interrupt enable reg Port 0 read address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read address miss int write-clear Original interrupt reg Original interrupt reg Port 0 read address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 read address miss final int 1: Address Miss 0: Normal Debug address register for port 0 write channel Debug address register for port 0 write channel Port 0 write channel address, 1K-Byte Debug id register for port 0 write channel Debug id register for port 0 write channel Port 0 write channel id, MSB is prot[1] Debug address register for port 0 read channel Debug address register for port 0 read channel Port 0 read channel address, 1K-Byte Debug id register for port 0 read channel Debug id register for port 0 read channel Port 0 read channel id, MSB is prot[1] Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) Segment 6 first address, the actual address should right shift 10-bit (1K-Byte) Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) Segment 6 last address, the actual address should right shift 10-bit (1K-Byte) Segment 6 Read Master ID select 0~31 Segment 6 Read Master ID select 0~31 Segment 6 Read Master ID select 32~63 Segment 6 Read Master ID select 32~63 Segment 6 Read Master ID select 64~95 Segment 6 Read Master ID select 64~95 Segment 6 Read Master ID select 96~127 Segment 6 Read Master ID select 96~127 Segment 6 Read Master ID select 128~159 Segment 6 Read Master ID select 128~159 Segment 6 Read Master ID select 160~191 Segment 6 Read Master ID select 160~191 Segment 6 Read Master ID select 192~223 Segment 6 Read Master ID select 192~223 Segment 6 Read Master ID select 224~255 Segment 6 Read Master ID select 224~255 Segment 6 Write Master ID select 0~31 Segment 6 Write Master ID select 0~31 Segment 6 Write Master ID select 32~63 Segment 6 Write Master ID select 32~63 Segment 6 Write Master ID select 64~95 Segment 6 Write Master ID select 64~95 Segment 6 Write Master ID select 96~127 Segment 6 Write Master ID select 96~127 Segment 6 Write Master ID select 128~159 Segment 6 Write Master ID select 128~159 Segment 6 Write Master ID select 160~191 Segment 6 Write Master ID select 160~191 Segment 6 Write Master ID select 192~223 Segment 6 Write Master ID select 192~223 Segment 6 Write Master ID select 224~255 Segment 6 Write Master ID select 224~255 Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) Segment 7 first address, the actual address should right shift 10-bit (1K-Byte) Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) Segment 7 last address, the actual address should right shift 10-bit (1K-Byte) Segment 7 Read Master ID select 0~31 Segment 7 Read Master ID select 0~31 Segment 7 Read Master ID select 32~63 Segment 7 Read Master ID select 32~63 Segment 7 Read Master ID select 64~95 Segment 7 Read Master ID select 64~95 Segment 7 Read Master ID select 96~127 Segment 7 Read Master ID select 96~127 Segment 7 Read Master ID select 128~159 Segment 7 Read Master ID select 128~159 Segment 7 Read Master ID select 160~191 Segment 7 Read Master ID select 160~191 Segment 7 Read Master ID select 192~223 Segment 7 Read Master ID select 192~223 Segment 7 Read Master ID select 224~255 Segment 7 Read Master ID select 224~255 Segment 7 Write Master ID select 0~31 Segment 7 Write Master ID select 0~31 Segment 7 Write Master ID select 32~63 Segment 7 Write Master ID select 32~63 Segment 7 Write Master ID select 64~95 Segment 7 Write Master ID select 64~95 Segment 7 Write Master ID select 96~127 Segment 7 Write Master ID select 96~127 Segment 7 Write Master ID select 128~159 Segment 7 Write Master ID select 128~159 Segment 7 Write Master ID select 160~191 Segment 7 Write Master ID select 160~191 Segment 7 Write Master ID select 192~223 Segment 7 Write Master ID select 192~223 Segment 7 Write Master ID select 224~255 Segment 7 Write Master ID select 224~255 default r address 0 register(1K-Byte address, bit 22 ~ bit 10). default r address 0 register(1K-Byte address, bit 22 ~ bit 10). default r address 0 register(1K-Byte address, bit 22 ~ bit 10). default w address 0 register(1K-Byte address, bit 22 ~ bit 10). default w address 0 register(1K-Byte address, bit 22 ~ bit 10). default w address 0 register(1K-Byte address, bit 22 ~ bit 10). clock gate bypass clock gate bypass 0: don't response error; 1: response error. clock gate bypass Interrupt enable reg Interrupt enable reg Port 0 write address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 write address miss int write-clear Original interrupt reg Original interrupt reg Port 0 write address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 write address miss final int 1: Address Miss 0: Normal Interrupt enable reg Interrupt enable reg Port 0 read address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read address miss int write-clear Original interrupt reg Original interrupt reg Port 0 read address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 read address miss final int 1: Address Miss 0: Normal Debug address register for port 0 write channel Debug address register for port 0 write channel Port 0 write channel address, 1K-Byte Debug id register for port 0 write channel Debug id register for port 0 write channel Port 0 write channel id, MSB is prot[1] Debug address register for port 0 read channel Debug address register for port 0 read channel Port 0 read channel address, 1K-Byte Debug id register for port 0 read channel Debug id register for port 0 read channel Port 0 read channel id, MSB is prot[1] Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 default r address 0 register(1K-Byte address, bit 16 ~ bit 10). default r address 0 register(1K-Byte address, bit 16 ~ bit 10). default r address 0 register(1K-Byte address, bit 16 ~ bit 10). default w address 0 register(1K-Byte address, bit 16 ~ bit 10). default w address 0 register(1K-Byte address, bit 16 ~ bit 10). default w address 0 register(1K-Byte address, bit 16 ~ bit 10). clock gate bypass clock gate bypass 0: don't response error; 1: response error. clock gate bypass Interrupt enable reg Interrupt enable reg Port 0 write address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 write address miss int write-clear Original interrupt reg Original interrupt reg Port 0 write address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 write address miss final int 1: Address Miss 0: Normal Interrupt enable reg Interrupt enable reg Port 0 read address miss int enable 1: Enable 0: Disable Interrupt write-clear reg Interrupt write-clear reg Port 0 read address miss int write-clear Original interrupt reg Original interrupt reg Port 0 read address miss original int 1: Address Miss 0: Normal Final interrupt reg Final interrupt reg Port 0 read address miss final int 1: Address Miss 0: Normal Debug address register for port 0 write channel Debug address register for port 0 write channel Port 0 write channel address, 1K-Byte Debug id register for port 0 write channel Debug id register for port 0 write channel Port 0 write channel id, MSB is prot[1] Debug address register for port 0 read channel Debug address register for port 0 read channel Port 0 read channel address, 1K-Byte Debug id register for port 0 read channel Debug id register for port 0 read channel Port 0 read channel id, MSB is prot[1] Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default first address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Segment default last address, the actual address should right shift 10-bit (1K-Byte) Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 0~31 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 32~63 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 64~95 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 96~127 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 128~159 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 160~191 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 192~223 Default Segment Read Master ID select 224~255 Default Segment Read Master ID select 224~255 Default Segment write Master ID select 0~31 Default Segment write Master ID select 0~31 Default Segment write Master ID select 32~63 Default Segment write Master ID select 32~63 Default Segment write Master ID select 64~95 Default Segment write Master ID select 64~95 Default Segment write Master ID select 96~127 Default Segment write Master ID select 96~127 Default Segment write Master ID select 128~159 Default Segment write Master ID select 128~159 Default Segment write Master ID select 160~191 Default Segment write Master ID select 160~191 Default Segment write Master ID select 192~223 Default Segment write Master ID select 192~223 Default Segment write Master ID select 224~255 Default Segment write Master ID select 224~255 Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 first address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 last address, the actual address should right shift 10-bit (1K-Byte) Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 0~31 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 32~63 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 64~95 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 96~127 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 128~159 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 160~191 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 192~223 Segment 0 Read Master ID select 224~255 Segment 0 Read Master ID select 224~255 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 0~31 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 32~63 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 64~95 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 96~127 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 128~159 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 160~191 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 192~223 Segment 0 Write Master ID select 224~255 Segment 0 Write Master ID select 224~255 Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 first address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 last address, the actual address should right shift 10-bit (1K-Byte) Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 0~31 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 32~63 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 64~95 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 96~127 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 128~159 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 160~191 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 192~223 Segment 1 Read Master ID select 224~255 Segment 1 Read Master ID select 224~255 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 0~31 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 32~63 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 64~95 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 96~127 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 128~159 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 160~191 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 192~223 Segment 1 Write Master ID select 224~255 Segment 1 Write Master ID select 224~255 Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 first address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 last address, the actual address should right shift 10-bit (1K-Byte) Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 0~31 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 32~63 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 64~95 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 96~127 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 128~159 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 160~191 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 192~223 Segment 2 Read Master ID select 224~255 Segment 2 Read Master ID select 224~255 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 0~31 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 32~63 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 64~95 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 96~127 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 128~159 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 160~191 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 192~223 Segment 2 Write Master ID select 224~255 Segment 2 Write Master ID select 224~255 Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 first address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 last address, the actual address should right shift 10-bit (1K-Byte) Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 0~31 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 32~63 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 64~95 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 96~127 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 128~159 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 160~191 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 192~223 Segment 3 Read Master ID select 224~255 Segment 3 Read Master ID select 224~255 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 0~31 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 32~63 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 64~95 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 96~127 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 128~159 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 160~191 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 192~223 Segment 3 Write Master ID select 224~255 Segment 3 Write Master ID select 224~255 Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 first address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 last address, the actual address should right shift 10-bit (1K-Byte) Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 0~31 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 32~63 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 64~95 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 96~127 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 128~159 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 160~191 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 192~223 Segment 4 Read Master ID select 224~255 Segment 4 Read Master ID select 224~255 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 0~31 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 32~63 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 64~95 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 96~127 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 128~159 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 160~191 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 192~223 Segment 4 Write Master ID select 224~255 Segment 4 Write Master ID select 224~255 Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 first address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 last address, the actual address should right shift 10-bit (1K-Byte) Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 0~31 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 32~63 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 64~95 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 96~127 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 128~159 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 160~191 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 192~223 Segment 5 Read Master ID select 224~255 Segment 5 Read Master ID select 224~255 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 0~31 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 32~63 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 64~95 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 96~127 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 128~159 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 160~191 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 192~223 Segment 5 Write Master ID select 224~255 Segment 5 Write Master ID select 224~255 rd 0 sec control rd 0 sec control control master emmc_rd_sec rd security operation: 00: Non security operation. 01/10: assign to master arprot[1] 11:Security operation control master lzma_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master gouda_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master usb_rd_sec rd security operation: 0: Non security operation. 1: Security operation. wr 0 sec control wr 0 sec control control master emmc_wr_sec wr security operation: 00: Non security operation. 01/10: assign to master arprot[1] 11:Security operation control master lzma_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master gouda_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master usb_wr_sec wr security operation: 0: Non security operation. 1: Security operation. rd 0 sec control rd 0 sec control control master cp_sys_aon_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master rf_sys_aon_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master dap_aon_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master fdma_aon_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master cp_sys_pub_rd_sec rd security operation: 0: Non security operation. 1: Security operation. control master gnss_sys_pub_rd_sec rd security operation: 0: Non security operation. 1: Security operation. wr 0 sec control wr 0 sec control control master cp_sys_aon_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master rf_sys_aon_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master dap_aon_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master fdma_aon_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master cp_sys_pub_wr_sec wr security operation: 0: Non security operation. 1: Security operation. control master gnss_sys_pub_wr_sec wr security operation: 0: Non security operation. 1: Security operation. OTG function address/Powe/TX interrupt register EP x TX Interrupt. Signals that the Transmit interrupt has been received from this endpoint Soft Connect. If Soft Connect/Disconnect feature is enabled, then the USB D+/D- lines are enabled when this bit is set by the CPU and tri-stated when this bit is cleared by the CPU. Note: Only valid in Peripheral Mode HS Enable. When set by the CPU, the core will negotiate for High-speed mode when the device is reset by the hub. If not set, the device will only operate in Full-speed mode. HS Mode. When set, this read-only bit indicates High-speed mode successfully negotiated during USB reset. In Peripheral Mode, becomes valid when USB reset completes (as indicated by USB reset interrupt). In Host Mode, becomes valid when Reset bit is cleared. Remains valid for the duration of the session. Reset. This bit is set when Reset signaling is present on the bus. Note: This bit is Read/Write from the CPU in Host Mode but Read-Only in Peripheral Mode. Resume. Set by the CPU to generate Resume signaling when the function is in Suspend mode. The CPU should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, this bit is also automatically set when Resume signaling from the target is detected while the core is suspended. Suspend Mode. In Host mode, this bit is set by the CPU to enter Suspend mode. In Peripheral mode, this bit is set on entry into Suspend mode. It is cleared when the CPU reads the interrupt register, or sets the Resume bit above. Enable Suspend M. Set by the CPU to enable the SUSPENDM output Function address OTG RX interrupt register/TX interrupt enable register EP x TX Interrupt Mask EP x RX Interrupt (x=0 to15)Signals that the Receive interrupt has been received from this endpoint. 0: Masks the Transmit interrupt from the endpoint x 1: The interrupt is allowed OTG RX interrupt enable/Common USB interrupt register VBUS Error Enable.Enables the VBUS interrupt bit in OTG_INTUSB Session Request Enable.Enables the SREQ interrupt bit in OTG_INTUSB Disconnect Enable.Enables the DISCON interrupt bit in OTG_INTUSB Connect Enable.Enables the CONN interrupt bit in OTG_INTUSB Start of Frame Enable.Enables the SOF interrupt bit in OTG_INTUSB Reset/Babble Enable.Enables the RST interrupt bit in OTG_INTUSB Resume Enable.Enables the RES interrupt bit in OTG_INTUSB Suspend Enable.Enables the SUSP interrupt bit in OTG_INTUSB VBUS Error. Set when VBus drops below the VBus Valid threshold during a session. Note: Only valid in Peripheral mode. Session Request. Set when Session Request signaling has been detected. Note: Only valid when the core is A-device. Disconnect.HOST: Set when a device disconnect is detected (HOSTDISCON going high). PERIPHERAL: Set when a session ends. Connect. Set when a device connection is detected (HOSTDISCON signal going low). Note: Only valid in Host mode. Start of Frame.Set when a new frame starts. Reset/Babble PERIPHERAL: Set when Reset signaling is detected on the USB. HOST: Set when babble condition is detected. Resume. Set when Resume signaling is detected on the bus while the core is in Suspend mode. Suspend. Set when Suspend signaling is detected on the bus. Note: Only valid in Peripheral mode. EP x RX Interrupt Mask (x = 1 to 15) 0: Masks the Receive interrupt from the endpoint x 1: Allows the interrupt OTG frame number/INDEX/Test Mode register Force Host.he Application Software sets this bit to instruct the core to enter Host mode when the Session bit is set, regardless of whether it is connected to any peripheral. The state of the CID input, Host Disconnect and Line State signals are ignored. The core will then remain in Host mode until the Session bit is cleared, even if a device is disconnected, and if the Force_Host bit remains set, will re-enter Host mode the next time the Session bit is set. While in this mode, the status of the HOSTDISCON signal from the PHY may be read from bit 7 of the DevCtl register.The operating speed is determined from the FHS and FFS bits as follows: 00 : Low speed 01 : Full speed 10: High speed 11: undefined FIFO Aceess.The CPU sets this bit to transfer the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO. The bit is cleared automatically. Force full-speed.This bit forces the core into full-speed mode when it receives a USB reset. Force high-speed.This bit forces the core into high-speed mode when it receives a USB reset. Test Packet.The CPU sets this bit to enter the Test_Packet test mode. In this mode, the MUSBMHDRC repetitively transmits on the bus a 53-byte test packet, the form of which is defined in the Universal Serial Bus Specification Revision 2.0, Section 7.1.20. The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before the test mode is entered. Note: Only valid in high-speed mode Test K-state.The CPU sets this bit to enter the Test_K test mode. In this mode, the MUSBMHDRC transmits a continuous K on the bus. Note: Only valid in high-speed mode Test J-state.The CPU sets this bit to enter the Test_J test mode. In this mode, the MUSBMHDRC transmits a continuous J on the bus. Note: Only valid in high-speed mode. Test SE0/NAK.The CPU sets this bit to enter the Test_SE0_NAK test mode. In this mode, the MUSBMHDRC remains in High-speed mode but responds to any valid IN token with a NAK. Note: Only valid in high-speed mode. Endpoint Number.This field programs the current active endpoint Current frame number.Shows the current frame number EP0 control and status register Host:Dis Ping, The CPU writes a 1 to this bit to instruct the core not to issue PING tokens in data and status phases of a high-speed Control transfer (for use with devices that do not respond to PING).. Device:Reserved Host:Data Toggle Write Enable, The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see Data Toggle bit, below). This bit is automatically cleared once the new value is written. Device:Reserved Host:Data toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If D10 is high, this bit may be written with the required setting of the data toggle. If D10 is low, any value written to this bit is ignored. Device:Reserved Host:Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Note: FlushFIFO has no effect unless TxPktRdy or RxPktRdy is set. Device:Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Note: FlushFIFO has no effect unless TxPktRdy or RxPktRdy is set. Host:NAK Timeout This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLimit0 register. The CPU should clear this bit to allow the endpoint to continue. Device:Serviced RX Packet Ready. The software sets this bit in order to clear the Rx Packet Ready (RRDY) bit. Writing zero has no effect. Device:Serviced Setup End. The software sets this bit in order to clear the Setup End (STE) bit. Writing zero has no effect. Host:StatusPkt The CPU sets this bit at the same time as the TxPktRdy or ReqPkt bit is set, to perform a status stage transaction. Setting this bit ensures that the data toggle is set to 1 so that a DATA1 packet is used for the Status Stage transaction. Device:Send Stall. The software sets this bit to terminate the current transaction. The STALL handshake will be transmitted and after that this bit is cleared automatically. Host:ReqPkt. The CPU sets this bit to request an IN transaction. It is cleared when RxPktRdy is set. Device:Setup End. This bit will be set when a control transaction ends before the Data End (DE) bit has been set. An interrupt will be generated and the FIFO flushed at this time. The bit is cleared by the software setting the Serviced Setup End (SSE) bit. Host:Error. This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral. The CPU should clear this bit. An interrupt is generated when this bit is set. Device:Data End. The software sets this bit when: – Setting TRDY for the last data packet. – Clearing RRDY after unloading the last data packet. – Setting TRDY for a zero length data packet. This bit is cleared automatically. Writing zero has no effect. Host:SetupPkt The CPU sets this bit, at the same time as the TxPktRdy bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The software should clear this bit. Host:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Device:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Host:TxPktRdy The CPU sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled). Device:TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Host:RxPktRdy This bit is set when a data packet has been received. An interrupt is generated (if enabled) when this bit is set. The CPU should clear this bit when the packet has been read from the FIFO. Device:RX Packet Ready. This bit is set when the data packet is received. An interrupt is generated when RRDY is set (unless disabled). This bit can be cleared by software by setting SRDY bit. Multiple Maximum payload transmitted.Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received/EP0 type register Frames to NAK Operation speed 00: Unused 01: High 10: Full 11: Low EP0 bytes received OTG core configuration register Bulk Pkt Amalgation.When set, the automatic amalgamation of bulk packets is selected Bulk Pkt Spliting.When set, the automatic splitting of bulk packets is selected Big Endian.When set, it indicates Big Endian ordering is selected. High-bandwidth ISO Support.When set to 1 indicates High-bandwidth RX ISO Endpoint Support selected. High-bandwidth ISO Support.When set to 1 indicates High-bandwidth TX ISO Endpoint Support selected. Dynamic FIFO Sizing.When set to 1 indicates Dynamic FIFO Sizing option selected. Soft Connect.When set to 1 indicates Soft Connect/Disconnect option selected. UTMI datawidth 0: 8 bits; 1: 16 bits. OTG device control/MISC/TX FIFO size/RX FIFO size register Double Packet Buffering. Defines whether the double-packet buffering is set for a selected endpoint. When set, the double-packet buffering is turned on. Endpoint RX FIFO Size. This field defines the RX FIFO size for a selected endpoint (and therefore a maximum packet size that is allowed before any splitting within the FIFO of Bulk/High- Bandwidth packets prior to transmission).RX FIFO Size (Bytes): Double Packet Buffering. Defines whether the double-packet buffering is set for a selected endpoint. When set, the double-packet buffering is turned on. Endpoint TX FIFO Size. This field defines the TX FIFO size for a selected endpoint (and therefore a maximum packet size that is allowed before any splitting within the FIFO of Bulk/High- Bandwidth packets prior to transmission).TX FIFO Size (Bytes): If DPB = 1, the size of the TX FIFO will be twice the size defined in this field. current interrupt is none DMA related. current interrupt is DMA related. B-Device.This bit indicates whether the core is operating as the A-Device or the B-Device. Only valid while a session is in progress. 0: A-Device 1: B-Device Note: If the core is in Force_Host mode (i.e. a session has been started with OTG_TM.Testmode.FRH = 1), this bit will indicate the state of the HOSTDISCON input signal from the transceiver. Full Speed.Full Speed. This bit is set when a full-speed or high-speed device has been detected being connected to the port. (High-speed devices are distinguished from full-speed by checking for high-speed chirps when the device is reset.) Only valid in Host mode. Low Speed.Low Speed. This bit is set when a low-speed device has been detected being connected to the port. Only valid in Host mode. VBUS.These bits encode the current VBUS level as follows: 00: Below SessionEnd Host Mode.This Read-only bit is set when the core is acting as a Host. Host Request.Host Request. When set, the core will initiate the Host Negotiation when Suspend mode is entered. It is cleared when Host Negotiation is completed. Session.When operating as an A-Device, this bit is set or cleared by the software to start or end a session.When operating as a B-Device, this bit is set/cleared by the core when a session starts/ends. It may also be set by the software to initiate the SRP. When the core is in Suspend mode, the bit may be cleared by the software to perform a software disconnect. OTG TX/RX FIFO address register FIFO Start Address. This field defines the start address of the endpoint FIFO in units of 8 bytes as follows. 13’h000 0000 13’h001 0008 13’h002 0010 …… …… 13’h1FFF FFF8 FIFO Start Address. This field defines the start address of the endpoint FIFO in units of 8 bytes as follows. 13’h000 0000 13’h001 0008 13’h002 0010 …… …… 13’h1FFF FFF8 OTG hardware version number register Major Version number.Returns 6d02 Minor Version number. Returns 10d000 OTG EP/RAM/link/VPLEN INFO register VBUS Pulse Length. Sets the duration of the VBus pulsing charge in units of 546.1 us (the default setting corresponds to 32.77ms). Note: When working in FS Interface mode, the timer values will be different: units of 682.62 us and the default value of 40.96 ms Connect/Disconnect Delay. Sets the wait to be applied to allow for the user s connect/disconnect filter in units of 533.3ns (the default setting corresponds to 2.667us). Note: When working in FS Interface mode, the timer values will be different: units of 666.63 ns and the default value of 3.33 us ID Pullup Delay. Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms (the default setting corresponds to 52.43ms). Note: When working in FS Interface mode, the timer values will be different: units of 5.46 ms and the default value of 65.54 ms number of DMA channel width of RAM DATA bus number of RX_EP number of TX_EP OTG HS/FS/LS time buffer register Reset All FFs in the XCLK clock domain. When a 1b1 is written to this bit, the XCLK clock domain reset will be asserted within a minimum delay of 7 cycles of the AHB clock. The output NRSTXO will be asynchronously asserted and synchronously de-asserted with respect to XCLK. This register is self clearing and always reads zero. Reset All FFs in the AHB clock domain. When a 1b1 is written to this bit, the AHB clock domain reset will be asserted within a minimum delay of 7 cycles of the AHB clock. The output NRSTO will be asynchronously asserted and synchronously de-asserted with respect to AHB clock. This register is self clearing and always reads zero. LS Time Buffer. Sets for Low-speed transactions the time before EOF to stop beginning new transactions, in units of 1.067 us (the default setting corresponds to 121.6 us). FS Time Buffer. Sets for Full-speed transactions the time before EOF to stop beginning new transactions, in units of 533.3 ns (the default setting corresponds to 63.46 us). HS Time Buffer. Sets for High-speed transactions the time before EOF to stop beginning new transactions, in units of 133.3 ns (the default setting corresponds to 17.07 us) OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG RX FUNCTION Address/HUB Address/HUB port register HUB port number 1= multiple transaction translator 0= single transaction translato The address of hub address of the target function OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG TX MAXPKTSIZE/CONTROL STATUS register Auto Reset.If the CPU sets this bit, TRDY will be automatically set when data of the maximum packet size (value in OTG_TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TRDY will have to be set manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host: Reserved Device: Isochronous Transfers. The CPU sets this bit to enable the TX endpoint for Isochronous transfers, and clears it to enable the TX endpoint for Bulk or Interrupt transfers. Mode.The CPU sets this bit to enable the endpoint direction as TX, and clears the bit to enable it as RX. This bit has any effect only where the same endpoint FIFO is used for both TX and RX transactions. DMA Request Enable.The CPU sets this bit to enable the DMA request for the TX endpoint. Force Data Toggle.The CPU sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. This can be used by Interrupt TX endpoints that are used to communicate rate feedback for Isochronous endpoints. Dma Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Host:Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the TX Endpoint data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Device:While D6(ISO)=1, The TX endpoint is enabled to do ISO transfer, this bit is meaningless. While D6(ISO)=0, ‘1: CPU sets this bit to enable the TX endpoint to do INT transfer ‘0: CPU sets this bit to enable the TX endpoint to do BULK transfer Data Toggle.When read, this bit indicates the current state of the TX Endpoint data toggle. If DRM is high, this bit may be written with the required setting of the data toggle. If DRM is low, any value written to DT is ignored. Host: NAK Timeout.This bit will be set when the TX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the OTG_TXINTV register. The CPU should clear this bit to allow the endpoint to continue. Note: Valid only for Bulk endpoints. Device:Incomplete. When the endpoint is being used for high-bandwidth Isochronous/Interrupt transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts. Note: In anything other than a high-bandwidth transfer, this bit will always return zero. Clear Data Toggle. The CPU writes a 1 to this bit to reset the endpoint data toggle to 0. Host: RX Stall. This bit is set when a STALL handshake is received. The FIFO is flushed and the TRDY bit is cleared (see below). The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TxPktRdy bit is cleared (see below). The CPU should clear this bit. Host: Setup Packet. The CPU sets this bit, at the same time as the TRDY bit is set, to send a SETUP token instead of an OUT token for the transaction. Note: Setting this bit also clears the Data Toggle. Device: Send Stall. The CPU sets this bit to issue a STALL handshake to an IN token. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO. The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint TX FIFO. The FIFO pointer is reset and the TRDY bit (below) is cleared. Host: Error. The core sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received. The CPU should clear this bit. Note: An interrupt is generated when the bit is set.Valid only when the endpoint is operating in Bulk or Interrupt mode. Device:Underrun. The core sets this bit if an IN token is received when TxPktRdy is not set. The CPU should clear this bit. FIFO Not Empty.The core sets this bit when there is at least 1 packet in the Tx FIFO. TX Packet Ready. The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is generated (if enabled) when the bit is cleared. Multiplier.See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX MAXPKTSIZE/CONTROL STATUS register Host: Auto clear.If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Device: Auto Set. If the CPU sets this bit then the RRDY bit will be automatically cleared when a packet of (OTG_RXMAXP) bytes has been unloaded from the Rx FIFO. When packets of less than the maximum packet size are unloaded, RRDY will have to be cleared manually. Note: This bit should not be set for high-bandwidth Isochronous endpoints. Host:Auto Request.If the CPU sets this bit, the RPK bit will be automatically set when the RRDY bit is cleared. Device:ISO. The CPU sets this bit to enable the RX endpoint for Isochronous transfers, and clears it to enable the RX endpoint for Bulk/Interrupt transfers. DMA Request Enable.The CPU sets this bit to enable the DMA request for the RX endpoint. Disable NYET.The CPU sets this bit to disable the sending of NYET handshakes. When set, all successfully received RX packets are ACKd including at the point at which the FIFO becomes full. Note: This bit only has any effect in high-speed mode, in which mode it should be set for all Interrupt endpoints. DMA Request Mode.The CPU sets this bit to select DMA Request Mode 1 and clears it to select DMA Request Mode 0. Data Toggle Write Enable.The CPU writes a 1 to this bit to enable the current state of the Endpoint 0 data toggle to be written (see DT bit, below). This bit is automatically cleared once the new value is written. Data Toggle.When read, this bit indicates the current state of the Endpoint 0 data toggle. If DWE is high, this bit may be written with the required setting of the data toggle. If DWE is low, any value written to DT is ignored. Incomp RX.This bit will be set in a high-bandwidth Isochronous transfer if the packet received is incomplete. It will be cleared when RRDY is cleared. In anything other than a high-bandwidth Isochronous transfer, this bit always returns 0. Note: If USB protocols are followed correctly, this bit should never be set. The bit becoming set indicates a failure of the associated Peripheral device to behave correctly. Clear Data Toggle.When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Host:RX Stall.RX Stall. When a STALL handshake is received, this bit is set and an interrupt is generated. The CPU should clear this bit. Device:Sent Stall. This bit is set when a STALL handshake is transmitted. The CPU should clear this bit. Host: Request Packet.Request Packet. The CPU writes a 1 to this bit to request an IN transaction. It is cleared when RRDY is set. Device:Send Stall. The CPU writes a 1b to this bit to issue a STALL handshake. The CPU clears this bit to terminate the stall condition. Note: This bit has no effect where the endpoint is being used for Isochronous transfers. Flush FIFO.The software writes a 1b to this bit to flush the next packet to be transmitted from the endpoint RX FIFO. The FIFO pointer is reset and the RRDY bit is cleared. Note: FF bit has no effect unless RRDY is set. Also note that, if the FIFO is double-buffered, FF may need to be set twice to completely clear the FIFO. Host:Data Error/NAK Timeout.When operating in ISO mode, this bit is set when RRDY is set if the data packet has a CRC or bit-stuff error and cleared when RRDY is cleared. In Bulk mode, this bit will be set when the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RxInterval register. The CPU should clear this bit to allow the endpoint to continue. Device:Data Error. This bit is set when RRDY is set if the data packet has a CRC or bit-stuff error. It is cleared when RRDY is cleared. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. Host: Error.The USB sets this bit when 3 attempts have been made to receive a packet and no data packet has been received. The CPU should clear this bit. An interrupt is generated when the bit is set. Note: This bit is only valid when the Tx endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. Device:Overrun. This bit is set if an OUT packet cannot be loaded into the Rx FIFO. The CPU should clear this bit. Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. FIFO Full.This bit is set when no more packets can be loaded into the RX FIFO. RX Packet Ready.RX Packet Ready. This bit is set when a data packet has been received. The CPU should clear this bit when the packet has been unloaded from the RX FIFO. An interrupt is generated when the bit is set. Multiplier. See spec. Maximum Payload Transmitted. This fields defines (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in full-speed and high-speed operations. OTG RX bytes received counter/transaction control/TX polling interval register TX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected TX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. Endpoint RX Count. The number of bytes received in RX FIFO.RXCNT is a 7-bit field in case of Endpoint 0. OTG RX transaction control/polling interval register RX Polling Interval/NAK Limit. For Interrupt and Isochronous transfers, this field defines the polling interval for the currently-selected RX endpoint.For Bulk mode, this field sets the number of frames/microframes after which the endpoint should timeout on receiving a stream of NAK responses. Operating Speed. Operating speed of the target device: 00: Unused 01: High 10: Full 11: Low Protocol. This bit selects the required protocol for the TX endpoint: 00: Control 01: Isochronous 10: Bulk 11: Interrupt Target Endpoint Number. The CPU should set this value to the endpoint number contained in the TX endpoint descriptor returned to the OTG Controller during device enumeration. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX packet count register enable the pre-define-RX-data-length RXPKTCNT Control.Sets the number of packets of size MaxPacketSize that are to be transferred in a block transfer. Only used in Host mode when AutoReq is set. Has no effect in Device mode or when AutoReq is not set. OTG RX/TX double packet buffer disable register EPx Receive Double Buffer Disable EPx Receive Double Buffer Disable OTG chirp timeout control/high-speed resume register The delay from the end of High Speed resume signaling to enabling UTM normal operating mode. The default value corresponds to a delay of 3us Configurable Chirp Timeout timer, the default value corresponds to a delay of 1.1ms. OTG HS BUS TURN around/FIFO timeout check/FIFO timeout count/external control registers 1= wait for tx data sent on usb bus 1= set flushFIFO, all rx FIFO pointers, status for MCU&USB Of each buff will be clear 0 = set flushFIFO,rx pointers, status forr current buff of MCU side will be clear. 1= set flushFIFO, all tx FIFO pointers, status for MCU&USB Of each buff will be clear 0 = set flushFIFO, tx pointers, status forr current buff of MCU side will be clear. 1= enable OTG SRP protocol 0= disable OTG SRP protocol While HOST_force_en =1 1= DEVICE mode 0 = HOST mode (no function if HOST_force_en =0) Setting the mode force host or device,1=SW force enable/0= SW force disable Setting the check number of data in FIFO Setting the period of check data in FIFO Setting the mode of fifochecck adjust the setting of HS bus turn around timing out setting OTG TX LISTEND interrupt status/enable register When ‘1’, the TX_listend_int15 will function When ‘1’, the TX_listend_int14 will function When ‘1’, the TX_listend_int13 will function When ‘1’, the TX_listend_int12 will function When ‘1’, the TX_listend_int11 will function When ‘1’, the TX_listend_int10 will function When ‘1’, the TX_listend_int9 will function When ‘1’, the TX_listend_int8 will function When ‘1’, the TX_listend_int7 will function When ‘1’, the TX_listend_int6 will function When ‘1’, the TX_listend_int5 will function When ‘1’, the TX_listend_int4 will function When ‘1’, the TX_listend_int3 will function When ‘1’, the TX_listend_int2 will function When ‘1’, the TX_listend_int1 will function When TX EP15 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP14 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP13 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP12 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP11 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP10 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP9 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP8 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP7 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP6 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP5 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP4 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP3 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP2 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. When TX EP1 send the data in the list end NOD (transferred by DMA), a TX interrupt will launch, and this bit will be set to 1. OTG TX LISTEND interrupt clear register When ‘1’, the TX_listend_int15 will be cleared When ‘1’, the TX_listend_int14 will be cleared When ‘1’, the TX_listend_int13 will be cleared When ‘1’, the TX_listend_int12 will be cleared When ‘1’, the TX_listend_int11 will be cleared When ‘1’, the TX_listend_int10 will be cleared When ‘1’, the TX_listend_int9 will be cleared When ‘1’, the TX_listend_int8 will be cleared When ‘1’, the TX_listend_int7 will be cleared When ‘1’, the TX_listend_int6 will be cleared When ‘1’, the TX_listend_int5 will be cleared When ‘1’, the TX_listend_int4 will be cleared When ‘1’, the TX_listend_int3 will be cleared When ‘1’, the TX_listend_int2 will be cleared When ‘1’, the TX_listend_int1 will be cleared OTG endpoint enable register When ‘1’, the Endpoint15 (both TX/RX) will function When ‘1’, the Endpoint14 (both TX/RX) will function When ‘1’, the Endpoint13 (both TX/RX) will function When ‘1’, the Endpoint12 (both TX/RX) will function When ‘1’, the Endpoint11 (both TX/RX) will function When ‘1’, the Endpoint10 (both TX/RX) will function When ‘1’, the Endpoint9 (both TX/RX) will function When ‘1’, the Endpoint8 (both TX/RX) will function When ‘1’, the Endpoint7 (both TX/RX) will function When ‘1’, the Endpoint6 (both TX/RX) will function When ‘1’, the Endpoint5 (both TX/RX) will function When ‘1’, the Endpoint4 (both TX/RX) will function When ‘1’, the Endpoint3 (both TX/RX) will function When ‘1’, the Endpoint2 (both TX/RX) will function When ‘1’, the Endpoint1 (both TX/RX) will function global enable global enable control register This value requires one-hot or all zero. [1:0] user channel; [2] train 1 ; [3] : train 2 Funnel overflow flag Funnel overflow flag register funnel async fifo empty status funnel overflow flag clear. funnel async fifo full flag interrupte enable fifo_overflow interrupt interrupte status dbgio control Software reset. 0: work 1: reset Dbgio source clock select 1’h0: 200MHz 1’b1: 140MHz Dbgio ddr mode enable The max length of data package control register "fsm_cut_off_len +1" is the max length of data package between any SYNC & CRC package, keep the value equals to (33N+32) where N is integer or zero. The max length of data wait cycle register "fsm_data_wait_len +1" is the max length of data wait cycle time when gearbox fifo is almost empty DBGIO PHY DLL CFG DBGIO PHY DLL CFG registers Cycles to wait DLL locked signals. write delay cell select 0:use user defined value from CLKDATWR_DLY_VAL 1:use dll generated value which referenced form CLKDATWR_DLY_VAL DLL Clock source selection 0: Select 1x clock 1: Select 2x clock DLL enable signal 0:DLL disable 1:DLL enable DLL clear signal 1:clear DLL Don’t support in this version DLL output delay value enable DLL start enable signal, this bit should be write to 1’b0 when it is enabled to 1’b1 DLL lock mode: 0: full cycle lock mode 1: half cycle lock mode DLL count initial value, DLL use it as the initial value to count the delay value. DLL change threshold value, DLL update rd/wr/cmd delay line value if the DLL count delta bigger then DLL_CPST_THRESHOLD DLL phase interval , DLL use it as the interval of phase 1 and phase2 OUPUT clock phase select DBGIO PHY DLL DLY DBGIO PHY DLL DLY registers Clock Data Write Line Delay Value Based Phase is invert of PHY Clock When DLL_DATWR_CPST_EN is enable, DBGIO PHY DLL Offset Read DBGIO PHY DLL Offset Read registers Clock Data Write Line Delay Invert Data Write Delay offset. The highest bit indicates if it is add or sub. OFFSET [4]=0: CLKDATWR_DLY_VAL + OFFSET [3:0] OFFSET [4]=1: CLKDATWR_DLY_VAL – OFFSET [3:0]. If DLL_DATWR _CPST_EN==1, the offset is added after the proportion. E.g. If Clock cycle (CYC)== 5ns CLKDATWR _DLY_ VAL (VAL) ==’h40, CLKDATWR_DLY_OFFSET (OFSET) == ‘h6, DLL_CNT(CNT) == ‘h20 it means delay: (VAL/’h100)*CYC + (CYC * OFSET) / CN = (‘h40/’h100)*5ns + (5ns * ‘h6) / ‘h20 ≈2.2ns DBGIO PHY DLL STS0 registers DBGIO PHY DLL STS0 registers Reserved for vender asic only Reserved for vender asic only If use DLL, software should wait this value to 1’b1 If use DLL, soft ware should wait DLL_LOCKED to 1’b1 and at that time ,this bit is 1’b0 Reserved for vender asic only Reserved for vender asic only DLL delay cell counts of 1 cycle DBGIO PHY DLL STS1 DBGIO PHY DLL STS1 registers Reserved for vender asic only DBGIO PHY DLL BACKUP DBGIO PHY DLL BACKUP registers Oe_ext_optional( Reserved for vender asic only) Force slice en value( Reserved for vender asic only) Force slice enable( Reserved for vender asic only) Force dll use backup mode value( Reserved for vender asic only) Force dll use backup mode( Reserved for vender asic only) Which channel be used Which channel be used If one channel is used, corresponding bit will be 1, otherwise is 0. Which channel use source sync mode If one channel uses source sync mode, corresponding bit will be 1, otherwise is 0. Which channel use handshake mode If one channel uses handshake mode, corresponding bit will be 1, otherwise is 0. Which channel use LA mode If one channel uses LA mode, corresponding bit will be 1, otherwise is 0. LA channel sample rate control register Sample rate of the LA channel is "(sample_rate + 1) / 16" This setting can't exceed 0xa, due to the ideal bandwidth limitation. IP version IP version R0p1 监控控制寄存器 Monitor运行启动位 0：停止监控或监控已完成。 1：开始监控或监控正在进行。 注:BUS Monitor总开关，除连续监控模式外，其他监控模式下，当监控完成后，该位自动清零。 监控控制寄存器 监控特定地址段范围外的写操作使能位 0：不使能； 1：使能； BUSY信号输出设置 1：随监控启动输出 0：一直输出 RBUSY信号输出设置 1：随监控启动输出 0：一直输出 WBUSY信号输出设置 1：随监控启动输出 0：一直输出 监控特定地址段范围内的写操作使能位 1：开启功能 0：不开启功能 监控访问命令数量达到设置值 1：开启功能 0：不开启功能 连续监控功能： 1：开启功能 0：不开启功能 监控设定时间段访问量： 1：开启功能 0：不开启功能 监控总线锁死 1：开启功能 0：不开启功能 监控总中断使能 0：不使能中断。 1：使能中断。 注：监控设定时间段与监控设定访问量这两个功能同时开启时，任何一个条件达到，就停止总线负荷的监控，总线挂死与特定地址特定数据的监控功能照常； 特定地址的监控功能开启时，MON_M0_ADDR_WID保留的是第一次条件触发的ID号；监控特定地址范围内与监控特定地址范围外的功能不能都使能；当监控特定地址范围内的功能使能后，任何访问四段设定地址段的写操作都会触发中断；当监控特定地址范围外的功能使能后，任何访问四段设定地址段以外的DDR地址（0x0-0x1fff_ffff）写操作都会触发中断，即监控地址段范围外的功能只限于DDR的地址，寄存器的地址不在监控之内；如果监控的地址段少于四段，需将四段地址寄存器均配齐全，多余的地址寄存器段需与前面任一有效地址配置相同值。 连续监控功能使能后，每隔设定时间段产生一个中断，并继续监控；“连续监控功能”与“监控设定时间段访问量”两个功能只能支持一个。 监控控制寄存器 访问命令限定寄存器 中断使能寄存器 MASTER0访问设定地址段中断使能 0：不使能中断。 1：使能中断。 访问命令数达到设定数目中断使能 0：不使能中断。 1：使能中断。 计数时间到达设定值中断使能 0：不使能中断。 1：使能中断。 LOCK中断使能 0：不使能中断。 1：使能中断。 中断标志寄存器 监控设定时间段模式下，监控时间结束中断 0：无中断。 1：有中断。 MASTER0访问特定地址段中断 0：无中断。 1：有中断。 MASTER4读访问命令达到指定数中断 0：无中断。 1：有中断 MASTER4写访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER3读访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER3写访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER2读访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER2写访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER1读访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER1写访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER0读访问命令达到指定数中断 0：无中断。 1：有中断。 MASTER0写访问命令达到指定数中断 0：无中断。 1：有中断。 连续监控模式下，设定时间到达中断 0：无中断。 1：有中断。 MASTER4总线锁死 0：无中断。 1：有中断。 MASTER3总线锁死 0：无中断。 1：有中断。 MASTER2总线锁死 0：无中断。 1：有中断。 MASTER1总线锁死 0：无中断。 1：有中断。 MASTER0总线锁死 0：无中断。 1：有中断。 MASTER0监控第一段起始地址寄存器 MASTER0写特定地址段时ID号寄存器 MASTER0监控第一段起始地址寄存器 写特定地址段的ID号 注: MON_START_ADDR, MON_END_ADDR两个寄存器用于设置MASTER0监控地址段的起始和结束地址;，其中起始地址应该大于等于结束地址；当MASTER0访问该地址段时,ADDR_INT会置位,如果该中断使能则产生中断 总线挂死时间寄存器 总线挂死判定时间 注：一个访问该寄存器的设定时间内未完成访问，即认定为总线挂死 通道0读命令计数器 通道0读数据计数器 通道0读数据计数器 通道0写数据计数器 通道1读命令计数器 通道1读数据计数器 通道1读数据计数器 通道1写数据计数器 通道2读命令计数器 通道2读数据计数器 通道2读数据计数器 通道2写数据计数器 通道3读命令计数器 通道3读数据计数器 通道3读数据计数器 通道3写数据计数器 通道4读命令计数器 通道4读数据计数器 通道4读数据计数器 通道4写数据计数器 MASTER0监控第二段起始地址寄存器 MASTER0监控第二段结束地址寄存器 MASTER0监控第三段起始地址寄存器 MASTER0监控第三段结束地址寄存器 MASTER0监控第四段起始地址寄存器 MASTER0监控第四段结束地址寄存器 MASTER0写特定地址段事件发生时的地址寄存器 phy initial complete configuration phy enable clk_ag_rd enable clk_ag_wr enable clk_ag enable clk_fg enable all clk enable software configure axi channel slave port cwakeup software configure axi channel master port cwakeup low power interface m0 ch or all ch select burst length 256byte limit for freq of 26m,52m and 109m wb955 128byte wrapper limit winbond memory sample rwds time psram is winbond memory 64Mb or 256Mb psram dq width x8 or x16 select psram is ap memory 256Mb or not select psram is winbond hyperbus or not select winbond memory mr write data not use This bit indicates ad slice 1 cpst is in IDLE status. This bit indicates ad slice 0 cpst is in IDLE status. phy input data This field indicates the cycles to wait the DLL lock internal signals This bit use to clear dll error automaticly This field is the sum of the delay cells from phase1 to phase2. This field is the threshold to start one compensation This bit enables the DLL. select input clock of dll for ad slice This bit write 1 to clear ad slice This bit is used to enable automatic compensation when all bank auto refresh. This bit is used to start compensation one time. This bit enables the DLL compensation. This bit enables DLL automatically clear when in low power state This field is to reset DLL This field is set if DLL error happens This field indicates DLL is locked or not This fields show the state of DLL FSM This bit indicates ad slice 0 cpst is in IDLE status. This field indicate the count of delay cells for one clk_dmc cycle This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field controls delay value of CEN output delay line This field controls delay value of CLK output delay line This field controls delay value of D3 output delay line This field controls delay value of D2 output delay line This field controls delay value of D1 output delay line This field controls delay value of D0 output delay line This field controls delay value of D7 output delay line This field controls delay value of D6 output delay line This field controls delay value of D5 output delay line This field controls delay value of D4 output delay line This field controls delay value of D3 input delay line This field controls delay value of D2 input delay line This field controls delay value of D1 input delay line This field controls delay value of D0 input delay line This field controls delay value of D7 input delay line This field controls delay value of D6 input delay line This field controls delay value of D5 input delay line This field controls delay value of D4 input delay line This field controls delay value of DQS input delay line This field controls delay value of DQM input delay line This field controls delay value of DQS output delay line dll max count for frequency set 3 dll max count for frequency set 2 dll max count for frequency set 1 dll max count for frequency set 0 dll min count for frequency set 3 dll min count for frequency set 2 dll min count for frequency set 1 dll min count for frequency set 0 This field controls IO source of CS 0:from psram internal logic 1:from register This field controls IO source of CLK 0:from psram internal logic 1:from register This field controls IO source of DQS 0:from psram internal logic 1:from register This field controls IO source of DQM 0:from psram internal logic 1:from register This field controls IO source of D7 0:from psram internal logic 1:from register This field controls IO source of D6 0:from psram internal logic 1:from register This field controls IO source of D5 0:from psram internal logic 1:from register This field controls IO source of D4 0:from psram internal logic 1:from register This field controls IO source of D3 0:from psram internal logic 1:from register This field controls IO source of D2 0:from psram internal logic 1:from register This field controls IO source of D1 0:from psram internal logic 1:from register This field controls IO source of D0 0:from psram internal logic 1:from register This field controls IO source of CS ie 0:from psram internal logic 1:from register This field controls IO source of CLK ie 0:from psram internal logic 1:from register This field controls IO source of DQS ie 0:from psram internal logic 1:from register This field controls IO source of DQM ie 0:from psram internal logic 1:from register This field controls IO source of D7 ie 0:from psram internal logic 1:from register This field controls IO source of D6 ie 0:from psram internal logic 1:from register This field controls IO source of D5 ie 0:from psram internal logic 1:from register This field controls IO source of D4 ie 0:from psram internal logic 1:from register This field controls IO source of D3 ie 0:from psram internal logic 1:from register This field controls IO source of D2 ie 0:from psram internal logic 1:from register This field controls IO source of D1 ie 0:from psram internal logic 1:from register This field controls IO source of D0 ie 0:from psram internal logic 1:from register This field controls IO source of CS oe 0:from psram internal logic 1:from register This field controls IO source of CLK oe 0:from psram internal logic 1:from register This field controls IO source of DQS oe 0:from psram internal logic 1:from register This field controls IO source of DQM oe 0:from psram internal logic 1:from register This field controls IO source of D7 oe 0:from psram internal logic 1:from register This field controls IO source of D6 oe 0:from psram internal logic 1:from register This field controls IO source of D5 oe 0:from psram internal logic 1:from register This field controls IO source of D4 oe 0:from psram internal logic 1:from register This field controls IO source of D3 oe 0:from psram internal logic 1:from register This field controls IO source of D2 oe 0:from psram internal logic 1:from register This field controls IO source of D1 oe 0:from psram internal logic 1:from register This field controls IO source of D0 oe 0:from psram internal logic 1:from register This field set value of CEN IO output This field set value of CLK IO output This field set value of DQS IO output This field set value of DQM IO output This field set value of D7 IO output This field set value of D6 IO output This field set value of D5 IO output This field set value of D4 IO output This field set value of D3 IO output This field set value of D2 IO output This field set value of D1 IO output This field set value of D0 IO output not use This field indicates the cycles to wait the DLL lock internal signals This bit use to clear dll error automaticly This field is the sum of the delay cells from phase1 to phase2. This field is the threshold to start one compensation This bit enables the DLL. select input clock of dll for ad slice This bit write 1 to clear ad slice This bit is used to enable automatic compensation when all bank auto refresh. This bit is used to start compensation one time. This bit enables the DLL compensation. This bit enables DLL automatically clear when in low power state This field is to reset DLL not use This field is set if DLL error happens This field indicates DLL is locked or not This fields show the state of DLL FSM This bit indicates ad slice 0 cpst is in IDLE status. This field indicate the count of delay cells for one clk_dmc cycle This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field enables the delay line to be compensated automatically by DLL This field enables to plus or to minus the offset value when DLL CPST, 0: Plus offset 1: Minus offset This fields are used to set the offset quarter delay value of DLL CPST This field indicate the quarter count of delay This field controls quarter delay value of delay line This fields are used to set the offset delay value of DLL CPST This field indicate the raw count of delay This field controls delay value of delay line This field controls delay value of CEN output delay line This field controls delay value of CLK output delay line This field controls delay value of D3 output delay line This field controls delay value of D2 output delay line This field controls delay value of D1 output delay line This field controls delay value of D0 output delay line This field controls delay value of D7 output delay line This field controls delay value of D6 output delay line This field controls delay value of D5 output delay line This field controls delay value of D4 output delay line This field controls delay value of D3 input delay line This field controls delay value of D2 input delay line This field controls delay value of D1 input delay line This field controls delay value of D0 input delay line This field controls delay value of D7 input delay line This field controls delay value of D6 input delay line This field controls delay value of D5 input delay line This field controls delay value of D4 input delay line This field controls delay value of DQS input delay line This field controls delay value of DQM input delay line This field controls delay value of DQS output delay line not use dll max count for frequency set 3 dll max count for frequency set 2 dll max count for frequency set 1 dll max count for frequency set 0 dll min count for frequency set 3 dll min count for frequency set 2 dll min count for frequency set 1 dll min count for frequency set 0 This field controls IO source of CS 0:from psram internal logic 1:from register This field controls IO source of CLK 0:from psram internal logic 1:from register This field controls IO source of DQS 0:from psram internal logic 1:from register This field controls IO source of DQM 0:from psram internal logic 1:from register This field controls IO source of D7 0:from psram internal logic 1:from register This field controls IO source of D6 0:from psram internal logic 1:from register This field controls IO source of D5 0:from psram internal logic 1:from register This field controls IO source of D4 0:from psram internal logic 1:from register This field controls IO source of D3 0:from psram internal logic 1:from register This field controls IO source of D2 0:from psram internal logic 1:from register This field controls IO source of D1 0:from psram internal logic 1:from register This field controls IO source of D0 0:from psram internal logic 1:from register This field controls IO source of CS ie 0:from psram internal logic 1:from register This field controls IO source of CLK ie 0:from psram internal logic 1:from register This field controls IO source of DQS ie 0:from psram internal logic 1:from register This field controls IO source of DQM ie 0:from psram internal logic 1:from register This field controls IO source of D7 ie 0:from psram internal logic 1:from register This field controls IO source of D6 ie 0:from psram internal logic 1:from register This field controls IO source of D5 ie 0:from psram internal logic 1:from register This field controls IO source of D4 ie 0:from psram internal logic 1:from register This field controls IO source of D3 ie 0:from psram internal logic 1:from register This field controls IO source of D2 ie 0:from psram internal logic 1:from register This field controls IO source of D1 ie 0:from psram internal logic 1:from register This field controls IO source of D0 ie 0:from psram internal logic 1:from register This field controls IO source of CS oe 0:from psram internal logic 1:from register This field controls IO source of CLK oe 0:from psram internal logic 1:from register This field controls IO source of DQS oe 0:from psram internal logic 1:from register This field controls IO source of DQM oe 0:from psram internal logic 1:from register This field controls IO source of D7 oe 0:from psram internal logic 1:from register This field controls IO source of D6 oe 0:from psram internal logic 1:from register This field controls IO source of D5 oe 0:from psram internal logic 1:from register This field controls IO source of D4 oe 0:from psram internal logic 1:from register This field controls IO source of D3 oe 0:from psram internal logic 1:from register This field controls IO source of D2 oe 0:from psram internal logic 1:from register This field controls IO source of D1 oe 0:from psram internal logic 1:from register This field controls IO source of D0 oe 0:from psram internal logic 1:from register This field set value of CEN IO output This field set value of CLK IO output This field set value of DQS IO output This field set value of DQM IO output This field set value of D7 IO output This field set value of D6 IO output This field set value of D5 IO output This field set value of D4 IO output This field set value of D3 IO output This field set value of D2 IO output This field set value of D1 IO output This field set value of D0 IO output This field use to select clkdmem_out 0:clkdmem_out invert 1:clkdmem_out This field use to select f0/f1/f2/f3 register This field use to select dqs ie delay cycle This field use to select dqs oe delay cycle This field use to select dqs out delay cycle This field use to select dqs gate delay cycle This field use to select data ie delay cycle This field use to select data oe delay cycle This field use to select dqs ie delay cycle This field use to select dqs oe delay cycle This field use to select dqs out delay cycle This field use to select dqs gate delay cycle This field use to select data ie delay cycle This field use to select data oe delay cycle This field use to select dqs ie delay cycle This field use to select dqs oe delay cycle This field use to select dqs out delay cycle This field use to select dqs gate delay cycle This field use to select data ie delay cycle This field use to select data oe delay cycle This field use to select dqs ie delay cycle This field use to select dqs oe delay cycle This field use to select dqs out delay cycle This field use to select dqs gate delay cycle This field use to select data ie delay cycle This field use to select data oe delay cycle This field use to select dll in saturate mode This field use to select dll in half mode This field use to select dll in x1 or x2 clk mode dll counts setting for fast lock indicate the count of dll state This field is used to configure DLL searching start value This field use to select dll in saturate mode This field use to select dll in half mode This field use to select dll in x1 or x2 clk mode dll counts setting for fast lock indicate the count of dll state This field is used to configure DLL searching start value This field use to select dll in saturate mode This field use to select dll in half mode This field use to select dll in x1 or x2 clk mode dll counts setting for fast lock indicate the count of dll state This field is used to configure DLL searching start value This field use to select dll in saturate mode This field use to select dll in half mode This field use to select dll in x1 or x2 clk mode dll counts setting for fast lock indicate the count of dll state This field is used to configure DLL searching start value This field use to set psram memory burst This field use to set rcd timing This field use to set rddata_en timing This field use to set phywrlat timing This field use to set cph_wr timing This field use to set cph_rd_optm timing This field use to set cph_rd timing This field use to set cmd data oe extend cycle This field use to set wdata oe extend cycle This field use to set dqs oe extend cycle This field use to set xphs timing This field use to set rddata valid sync cycle This field use to set rddata late cycle This field use to set rddata early cycle This field use to set winbond reset rp cycle This field use to set winbond reset rh cycle not use This field use to enable dmc read gate training This field use to enable phy read gate training This field use to enable dmc read data eye training This field use to enable phy read data eye training This field use to enable dmc write training This field use to enable phy write training This field use to define type3 max number of cycles of idle time on DFI control This field use to define type2 max number of cycles of idle time on DFI control This field use to define type1 max number of cycles of idle time on DFI control This field use to define type0 max number of cycles of idle time on DFI control This field use to select phyupd type This field use to enable phy-initiated update record read memory register data enable read memory register data0 read memory register data1 ads1 read command send int enable ads1 write command send int enable ads1 mr read command send int enable ads1 mr write command send int enable ads1 reset command send int enable ads0 read command send int enable ads0 write command send int enable ads0 mr read command send int enable ads0 mr write command send int enable ads0 reset command send int enable ads1 rddata timeout int enable ads0 rddata timeout int enable ads1 dll unlock int enable ads0 dll unlock int enable ads1 read command send int clear ads1 write command send int clear ads1 mr read command send int clear ads1 mr write command send int clear ads1 reset command send int clear ads0 read command send int clear ads0 write command send int clear ads0 mr read command send int clear ads0 mr write command send int clear ads0 reset command send int clear ads1 rddata timeout int clear ads0 rddata timeout int clear ads1 dll unlock int clear ads0 dll unlock int clear ads1 read command send int status ads1 write command send int status ads1 mr read command send int status ads1 mr write command send int status ads1 reset command send int status ads0 read command send int status ads0 write command send int status ads0 mr read command send int status ads0 mr write command send int status ads0 reset command send int status ads1 rddata timeout int status ads0 rddata timeout int status ads1 dll unlock int status ads0 dll unlock int status ads1 dll unlock cnt clear ads0 dll unlock cnt clear ads0 dll unlock cnt overflow status ads0 dll unlock cnt value ads1 dll unlock cnt overflow status ads1 dll unlock cnt value Interrupt flag Register0 Interrupt flag Register0 Interrupt mask Register0 Interrupt mask Register1 中断屏蔽置1寄存器0 中断屏蔽置1寄存器1 中断屏蔽清0寄存器0 中断屏蔽清0寄存器1 全局中断屏蔽寄存器 Global interrupt enable BIT 0：Interrupt is decided by corresponding mask bit 1：Maks all Interrupt 中断选择寄存器0 中断选择寄存器1 IRQ中断状态寄存器 IRQ中断状态寄存器 IRQ中断源寄存器 IRQ interrupt source code 0000000：IRQ0 0000001：IRQ1 0000010：IRQ2 …… 0111111：IRQ63 IRQ中断控制寄存器 Clear interrupt status bit 0：no operation 1：clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low FIQ中断状态寄存器 FIQ中断状态寄存器 FIQ中断源寄存器 fiq interrupt source code 0000000：FIQ0 0000001：FIQ1 0000010：FIQ2 …… 0111111：FIQ63 FIQ中断控制寄存器 Clear interrupt status bit 0：no operation 1：clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio 中断优先级配置寄存器 Interrupt prio 0：Interrupt prio 0 1：Interrupt prio 1 …… 7：Interrupt prio 7 Prio 0 is corrosponed to the highist prio general used register security visit enable 0：security 1：unsecurity response error stop function enable 0：enable 1：disable the number of outstanding that can be send out 0: 2 1: 3 2: 4 multe-channel transport priority mode control 0: there is no priority in the channels, using polling to DMA data 1: smaller channel number has high-priority.high-priority move data before low-priority channels interrupt control bit 0: no interruption occurs when all logical channels finish 1: interruption occurs when all logical channels finish the control bit of logical channel transport finish 0: don't stop all the channel,or automatically clear after setting 1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. stop status 0: not finish 1: finish the channel number of the final transmission 0000: channel 0 just finished the transmission 0001: channel 1 just finished the transmission 0010: channel 2 just finished the transmission …… 1011: channel 11 just finished the transmission others: nonentity 逻辑通道传输停止中断状态位 0：逻辑通道传输停止中断未产生 1：逻辑通道传输停止产生中 channel 11 interrupts state 0: the channel 11 has not been interrupted, or the interrupt bit has been cleared 1: channel 11 is interrupted channel 10 interrupts state 0: the channel 10 has not been interrupted, or the interrupt bit has been cleared 1: channel 10 is interrupted channel 9 interrupts state 0: the channel 9 has not been interrupted, or the interrupt bit has been cleared 1: channel 9 is interrupted channel 8 interrupts state 0: the channel 8 has not been interrupted, or the interrupt bit has been cleared 1: channel 8 is interrupted channel 7 interrupts state 0: the channel 7 has not been interrupted, or the interrupt bit has been cleared 1: channel 7 is interrupted channel 6 interrupts state 0: the channel 6 has not been interrupted, or the interrupt bit has been cleared 1: channel 6 is interrupted channel 5 interrupts state 0: the channel 5 has not been interrupted, or the interrupt bit has been cleared 1: channel 5 is interrupted channel 4 interrupts state 0: the channel 4 has not been interrupted, or the interrupt bit has been cleared 1: channel 4 is interrupted channel 3 interrupts state 0: the channel 3 has not been interrupted, or the interrupt bit has been cleared 1: channel 3 is interrupted channel 2 interrupts state 0: the channel 2 has not been interrupted, or the interrupt bit has been cleared 1: channel 2 is interrupted channel 1 interrupts state 0: the channel 1 has not been interrupted, or the interrupt bit has been cleared 1: channel 1 is interrupted channel 0 interrupts state 0: the channel 0 has not been interrupted, or the interrupt bit has been cleared 1: channel 0 is interrupted state of IRQ 23 generate requests of moving data 0: IRQ 23 does not generate requests of moving data 1: IRQ 23 generate requests of moving data state of IRQ 22 generate requests of moving data 0: IRQ 22 does not generate requests of moving data 1: IRQ 22 generate requests of moving data state of IRQ 21 generate requests of moving data 0: IRQ 21 does not generate requests of moving data 1: IRQ 21 generate requests of moving data state of IRQ 20 generate requests of moving data 0: IRQ 20 does not generate requests of moving data 1: IRQ 20 generate requests of moving data state of IRQ 19 generate requests of moving data 0: IRQ 19 does not generate requests of moving data 1: IRQ 19 generate requests of moving data state of IRQ 18 generate requests of moving data 0: IRQ 18 does not generate requests of moving data 1: IRQ 18 generate requests of moving data state of IRQ 17 generate requests of moving data 0: IRQ 17 does not generate requests of moving data 1: IRQ 17 generate requests of moving data state of IRQ 16 generate requests of moving data 0: IRQ 16 does not generate requests of moving data 1: IRQ 16 generate requests of moving data state of IRQ 15 generate requests of moving data 0: IRQ 15 does not generate requests of moving data 1: IRQ 15 generate requests of moving data state of IRQ 14 generate requests of moving data 0: IRQ 14 does not generate requests of moving data 1: IRQ 14 generate requests of moving data state of IRQ 13 generate requests of moving data 0: IRQ 13 does not generate requests of moving data 1: IRQ 13 generate requests of moving data state of IRQ 12 generate requests of moving data 0: IRQ 12 does not generate requests of moving data 1: IRQ 12 generate requests of moving data state of IRQ 11 generate requests of moving data 0: IRQ 11 does not generate requests of moving data 1: IRQ 11 generate requests of moving data state of IRQ 10 generate requests of moving data 0: IRQ 10 does not generate requests of moving data 1: IRQ 10 generate requests of moving data state of IRQ 9 generate requests of moving data 0: IRQ 9 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 8 generate requests of moving data 0: IRQ 8 does not generate requests of moving data 1: IRQ 8 generate requests of moving data state of IRQ 7 generate requests of moving data 0: IRQ 7 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 6 generate requests of moving data 0: IRQ 6 does not generate requests of moving data 1: IRQ 6 generate requests of moving data state of IRQ 5 generate requests of moving data 0: IRQ 5 does not generate requests of moving data 1: IRQ 5 generate requests of moving data state of IRQ 4 generate requests of moving data 0: IRQ 4 does not generate requests of moving data 1: IRQ 4 generate requests of moving data state of IRQ 3 generate requests of moving data 0: IRQ 3 does not generate requests of moving data 1: IRQ 3 generate requests of moving data state of IRQ 2 generate requests of moving data 0: IRQ 2 does not generate requests of moving data 1: IRQ 2 generate requests of moving data state of IRQ 1 generate requests of moving data 0: IRQ 1 does not generate requests of moving data 1: IRQ 1 generate requests of moving data state of IRQ 0 generate requests of moving data 0: IRQ 0 does not generate requests of moving data 1: IRQ 0 generate requests of moving data state of ACK 23 generate requests of moving data 0: ACK 23 does not generate requests of moving data 1: ACK 23 generate requests of moving data state of ACK 22 generate requests of moving data 0: ACK 22 does not generate requests of moving data 1: ACK 22 generate requests of moving data state of ACK 21 generate requests of moving data 0: ACK 21 does not generate requests of moving data 1: ACK 21 generate requests of moving data state of ACK 20 generate requests of moving data 0: ACK 20 does not generate requests of moving data 1: ACK 20 generate requests of moving data state of ACK 19 generate requests of moving data 0: ACK 19 does not generate requests of moving data 1: ACK 19 generate requests of moving data state of ACK 18 generate requests of moving data 0: ACK 18 does not generate requests of moving data 1: ACK 18 generate requests of moving data state of ACK 17 generate requests of moving data 0: ACK 17 does not generate requests of moving data 1: ACK 17 generate requests of moving data state of ACK 16 generate requests of moving data 0: ACK 16 does not generate requests of moving data 1: ACK 16 generate requests of moving data state of ACK 15 generate requests of moving data 0: ACK 15 does not generate requests of moving data 1: ACK 15 generate requests of moving data state of ACK 14 generate requests of moving data 0: ACK 14 does not generate requests of moving data 1: ACK 14 generate requests of moving data state of ACK 13 generate requests of moving data 0: ACK 13 does not generate requests of moving data 1: ACK 13 generate requests of moving data state of ACK 12 generate requests of moving data 0: ACK 12 does not generate requests of moving data 1: ACK 12 generate requests of moving data state of ACK 11 generate requests of moving data 0: ACK 11 does not generate requests of moving data 1: ACK 11 generate requests of moving data state of ACK 10 generate requests of moving data 0: ACK 10 does not generate requests of moving data 1: ACK 10 generate requests of moving data state of ACK 9 generate requests of moving data 0: ACK 9 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 8 generate requests of moving data 0: ACK 8 does not generate requests of moving data 1: ACK 8 generate requests of moving data state of ACK 7 generate requests of moving data 0: ACK 7 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 6 generate requests of moving data 0: ACK 6 does not generate requests of moving data 1: ACK 6 generate requests of moving data state of ACK 5 generate requests of moving data 0: ACK 5 does not generate requests of moving data 1: ACK 5 generate requests of moving data state of ACK 4 generate requests of moving data 0: ACK 4 does not generate requests of moving data 1: ACK 4 generate requests of moving data state of ACK 3 generate requests of moving data 0: ACK 3 does not generate requests of moving data 1: ACK 3 generate requests of moving data state of ACK 2 generate requests of moving data 0: ACK 2 does not generate requests of moving data 1: ACK 2 generate requests of moving data state of ACK 1 generate requests of moving data 0: ACK 1 does not generate requests of moving data 1: ACK 1 generate requests of moving data state of ACK 0 generate requests of moving data 0: ACK 0 does not generate requests of moving data 1: ACK 0 generate requests of moving data REQ 7搬数请求状态 000：REQ 7未产生搬数请求 001：REQ 7产生1次搬数请求 …… 111：REQ 7产生7次搬数请求 REQ 6搬数请求状态 000：REQ 6未产生搬数请求 001：REQ 6产生1次搬数请求 …… 111：REQ 6产生7次搬数请求 REQ 5搬数请求状态 000：REQ 5未产生搬数请求 001：REQ 5产生1次搬数请求 …… 111：REQ 5产生7次搬数请求 REQ 4搬数请求状态 000：REQ 4未产生搬数请求 001：REQ 4产生1次搬数请求 …… 111：REQ 4产生7次搬数请求 REQ 3搬数请求状态 000：REQ 3未产生搬数请求 001：REQ 3产生1次搬数请求 …… 111：REQ 3产生7次搬数请求 REQ 2搬数请求状态 000：REQ 2未产生搬数请求 001：REQ 2产生1次搬数请求 …… 111：REQ 2产生7次搬数请求 REQ 1搬数请求状态 000：REQ 1未产生搬数请求 001：REQ 1产生1次搬数请求 …… 111：REQ 1产生7次搬数请求 REQ 0搬数请求状态 000：REQ 0未产生搬数请求 001：REQ 0产生1次搬数请求 …… 111：REQ 0产生7次搬数请求 REQ 11搬数请求状态 000：REQ 11未产生搬数请求 001：REQ 11产生1次搬数请求 …… 111：REQ 11产生7次搬数请求 REQ 10搬数请求状态 000：REQ 10未产生搬数请求 001：REQ 10产生1次搬数请求 …… 111：REQ 10产生7次搬数请求 REQ 9搬数请求状态 000：REQ 9未产生搬数请求 001：REQ 9产生1次搬数请求 …… 111：REQ 9产生7次搬数请求 REQ 0搬数请求状态 000：REQ 8未产生搬数请求 001：REQ 8产生1次搬数请求 …… 111：REQ 8产生7次搬数请求 channel 11 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 10 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 9 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 8 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 7 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 6 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 5 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 4 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 3 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 2 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 1 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 0 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0：disable 1：enable security visit 0：security 1：unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 …… 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission …… 01111: IRQ15 trigger transmission …… 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte response error interrupt flag 0：unset 1：set response error status 0：unset 1：set data linked list is paused 0: not paused 1: paused the linked list is completed 0: not completed 1: completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed scatter-gather pause the number of scatter-gather transfers completed 0x0000: 0 …… 0xFFFF: 65535 times scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit …… 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable scatter-gather function enable 0: disable 1: enable AXIDMA 各通道运行位置位寄存器 channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel AXIDMA 各通道运行位清除寄存器 clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel F8 模块上行配置寄存器 F8算法类型和只做搬数选择： 000：只搬数，不做加解密 001：AES加解密，并搬数 010：snow3G加解密，并搬数 011：zuc加解密，并搬数 100：Kasumi加解密，并搬数 101-111：Reversed F8算法中断使能位 0：F8 算法/搬数在整个多块group结束后，不产生中断； 1：F8 算法/搬数在整个多块group结束后，产生中断 F8算法启动控制位 0：不启动F8 算法，或完成后自动清零； 1：启动F8算法 F8上行group首地址寄存器 F8上行group个数寄存器 F8上行状态寄存器 0：F8算法/搬数，未完成或未开始 1：F8算法/搬数，已完成 F8 模块下行配置寄存器 F8算法类型和只做搬数选择： 000：只搬数，不做加解密 001：AES加解密，并搬数 010：snow3G加解密，并搬数 011：zuc加解密，并搬数 100：Kasumi加解密，并搬数 101-111：Reversed F8算法中断使能位 0：F8 算法/搬数在整个多块group结束后，不产生中断； 1：F8 算法/搬数在整个多块group结束后，产生中断 F8算法启动控制位 0：不启动F8 算法，或完成后自动清零； 1：启动F8算法 F8下行group首地址寄存器 F8下行group个数寄存器 F8下行状态寄存器 0：F8算法/搬数，未完成或未开始 1：F8算法/搬数，已完成 F9配置寄存器 AXI写outstanding能力设置,不能配置为2‘b11 AXI读outstanding能力设置,不能配置为2‘b11 F9算法类型选择： 00：AES完整性算法 01：AES完整性算法 10：snow3G完整性算法 11：zuc完整性算法 F9算法中断使能位 0：F9 算法/搬数在整个多块group结束后，不产生中断； 1：F9 算法/搬数在整个多块group结束后，产生中断 F9算法启动控制位 0：不启动F9 算法，或完成后自动清零； 1：启动F9算法 F9 group首地址寄存器 F9状态寄存器 0：F9未完成或未开始 1：F9已完成 F9 结果寄存器 F8 信令配置寄存器 F8算法类型和只做搬数选择： 000：只搬数，不做加解密 001：AES加解密，并搬数 010：snow3G加解密，并搬数 011：zuc加解密，并搬数 100：Kasumi加解密，并搬数 101-111：Reversed F8算法中断使能位 0：F8 信令加解密单次group完成后，不产生中断； 1：F8 信令加解密单次group完成后，产生中断 F8算法启动控制位 0：不启动F8 算法，或完成后自动清零； 1：启动F8算法 F8信令group首地址寄存器 F8信令状态寄存器 0：F8信令未完成或未开始 1：F8信令已完成 状态指示寄存器 0：F9信令未完成或未开始 1：F9信令已完成 0：F8信令未完成或未开始 1：F8信令已完成 0：F8上行未完成或未开始 1：F8上行已完成 0：F8下行未完成或未开始 1：F8下行已完成 CP sleep enable register(Enable CP sleep when writing 0x49444c45 to this register, accessed by software only.) Enable CP sleep 0: disable 1: enable AP sleep enable register(Auto cleared by hardware after the system awakup) Enable AP sleep(Auto cleared to be 0 when the system is awaked) 0: disable 1: enable System sleep enable register Enable AP sleep 0: disable 1: enable Enable CP sleep 0: disable 1: enable Slssp counter wrap value. WCN lp enable register Default value when the enable bit was disabled. Enable bit of wcn idle_cg 0: disable 1: enable Enable bit of wcn pd_pll 0: disable 1: enable Enable bit of wcn pd_xtal 0: disable 1: enable Enable bit of wcn chip_pd 0: disable 1: enable Timer sleep enable (writing 0x49444c45 to this register to enable timer sleep.) Enable Timer sleep(Auto clear to be 0 when timer is awaked) 0: disable 1: enable Sleep threshold register Threshold register M1: when the signal pow_on_ack is low, both gsm and lte timer are sleeped, and the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP state. Threshold register M2: when idct_sys1 and idct_sys2 are set to be1, the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP_PRE state. Take over TCU enable register Enable mode(TCU suspend and this bits are clear to be 0 when take over is started) 00: disbale or already release TCU. 01: take over TCU immediately 10: take over at gsm frame interrupt. 11: no effect. Restart TCU register restart TCU when gsm counter reach this register restart mode(this bits clear to be 0 when TCU restarts) 00: disable 01: restart TCU immediately 10: restart TCU when gsm frame interrupt occurred. 11: restart TCU when gsm framc equal to TC_END_FRAMC. TIMER wakeup register Timer wakeup enable(software accessed only) 0: disable 1: enable Lp_pu_done register TCU restart enable(software accessed only) Output to the port gsm_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. gsm frame interrupt enable set register gsm_frame_irq enable 1: enable 0: disable gsm frame interrupt state register cleared by writing 1 to correspond bit LTEM1 frame interrupt enable register ltem1_frame3_irq enable 1: enable 0: disable ltem1_frame2_irq enable 1: enable 0: disable ltem1_frame1_irq enable 1: enable 0: disable LTEM1 interrupt state register cleared by writing 1 to correspond bit LTEM2 frame interrupt enable register ltem2_frame3_irq enable 1: enable 0: disable ltem2_frame2_irq enable 1: enable 0: disable ltem2_frame1_irq enable 1: enable 0: disable LTEM2 interrupt state register cleared by writing 1 to correspond bit IDLE state register ltem3 timer state 0: running at 122.88M 1: running at 32K NB timer state 0: running at 61.44M 1: running at 32K H circuit state 0: not work 1: at wok ltem2 timer state 0: running at 122.88M 1: running at 32K ltem1 timer state 0: running at 122.88M 1: running at 32K GSM timer state 0: running at 26M 1: running at 32K SYS state 0: normal working 1: low power mode H circuit control register Runtime of H circuit, the length is 2^h_run_time(number of 32k clocks) Automatic computing mode enable(loop computing until disabled) 0: disable 1: enable Invocation pattern(compute only one time, automatic clear to be 0 when finished.) 0: disable 1: enable H value register The length of sys clock in 2^h_run_time 32k cycles H value register The cycles number of 26M in 2^h_run_time 32k cycles H value register The cycles number of 122.88M in of 2^h_run_time 32k cycles wakeup enable register signal nb_lp_pu_reach wakeup enable 0: disable 1: enable signal gsm_lp_pu_reach wakeup enable 0: disable 1: enable sofware wakeup enable 0: disable 1: enable OSW2 wakeup enable 0: disable 1: enable OSW1 wakeup enable 0: disable 1: enable pad_gpio1 wakeup enable 0: disable 1: enable uart3_irq wakeup enable 0: disable 1: enable pad_uart3_rxd wakeup enable 0: disable 1: enable gpt2_irq wakeup enable 0: disable 1: enable mailbox_irq wakeup enable 0: disable 1: enable gpio2_irq wakeup enable 0: disable 1: enable uart2_irq wakeup enable 0: disable 1: enable pad_uart2_rxd wakeup enable 0: disable 1: enable pmic_irq wakeup enable 0: disable 1: enable usb_irq wakeup enable 0: disable 1: enable pad_uart1_rxd wakeup enable 0: disable 1: enable Uart1_irq wakeup enable 0: disable 1: enable Gpio1_irq wakeup enable 0: disable 1: enable Keyboard wakeup enable 0: disable 1: enable gpt1_irq wakeup enable 0: disable 1: enable Pad_gpio6 wakeup enable 0: disable 1: enable wakeup state(can be cleared by writing 1 to correspond bits) pow_dfe_ack state 0: pow_dfe_ack is 0 when system exit IDLE 1: pow_dfe_ack is 1 when system exit IDLE Threshold M1 state 1: pow_ack not meet threshold M1 or pow_ack not feedback in sleep period 0: meet threshold M1 pow_ack state 0: pow_ack is 0 when system exit IDLE 1: pow_ack is 1 when system exit IDLE system exit idle state 0: sys not enter idle 1: sys enter idle state IDLE sleep wakeup state 0: awaked before the sleep warp time 1: awaked at the sleep warp time Signal nb_lp_pu_reach wakeup state 0: this signal not generated 1: this signal generated Signal gsm_lp_pu_reach wakeup state 0: this signal not generated 1: this signal generated software wakeup state 0: software wakeupup signal not generated 1: software wakeupup system. OSW2 wakeup state 0: this signal not generated 1: this signal generated OSW1 wakeup state 0: this signal not generated 1: this signal generated AWK15 wakeup state 0: this signal not generated 1: this signal generated AWK14 wakeup state 0: this signal not generated 1: this signal generated AWK13 wakeup state 0: this signal not generated 1: this signal generated AWK12 wakeup state 0: this signal not generated 1: this signal generated AWk11 wakeup state 0: this signal not generated 1: this signal generated AWk10 wakeup state 0: this signal not generated 1: this signal generated AWK9 wakeup state 0: this signal not generated 1: this signal generated AWK8 wakeup state 0: this signal not generated 1: this signal generated AWK7 wakeup state 0: this signal not generated 1: this signal generated AWK6 wakeup state 0: this signal not generated 1: this signal generated AWK5 wakeup state 0: this signal not generated 1: this signal generated AWK4 wakeup state 0: this signal not generated 1: this signal generated AWk3 wakeup state 0: this signal not generated 1: this signal generated AWk2 wakeup state 0: this signal not generated 1: this signal generated AWK1 wakeup state 0: this signal not generated 1: this signal generated AWK0 wakeup state 0: this signal not generated 1: this signal generated software wakeup signal 0: not effect 1: wakeup system (accessed by software only, this bit shold clear bu software when system is awaked.) OSW1 TIMER enable 1: enable 0: disable osw1 wrap value OSW1 Timer current value IDLE GSM frame register IDLE LTEM1frame register Number of frames ltem1 sleeped. Number of sub-frames ltem1 sleeped. IDLE LTEM2 frame register Number of frames ltem2 sleeped Number of sub-frames ltem2 sleeped. IDLE LTE frame length register LTE sleep frame length, suggest keep the default value. IDLE LTE sub-frame length register LTE sleep sub-frame length, suggest keep the default value. signal of low power related enable register Idle_cg_en enable 1: enable. 0: disable. Pd_pll_en enable 1: enable 0: disable pd_xtal_en enable 1: enable. 0: disable. chip_pd_en enable 1: enable. 0: disable. low power related time control register The time from enable clock to obtain clock The time of PLL from power saving state to output normal clock. The time of OSC circuit from power saving state to normal state. The time of PMIC boost stabilization. 32K reference counter cp interrupt enable register em_latch_irq enable 1: enable 0: disable cpu_latch_irq enable 1: enable 0: disable rtc_latch_irq enable 1: enable 0: disable load_end_irq enable 1: enable 0: disable timer_idle_irq enable 1: enable 0: disable target_irq enable 1: enable 0: disable nb_pu_reach_irq enable 1: enable 0: disable nb_tc_end_irq enable 1: enable 0: disable nb_tc_start_irq enable 1: enable 0: disable sys_awk _irq enable 1: enable 0: disable Timer_awk_irq_enable 1: enable 0: disable gsm_pu_reach_irq enable 1: enable 0: disable gsm_tc_end_irq enable 1: enable 0: disable gsm_tc_start_irq enable 1: enable 0: disable osw1_irq enable 1: enable 0: disable tstamp_irq enable 1: enable 0: disable idle_frame_irq enable 1: enable 0: disable idle_h_irq enable 1: enable 0: disable layout_irq enable 1: enable 0: disable cp interrupt enable set register set cp interrupt enable register when writing 1 to correspond bits. cp interrupt enable clear register clear cp interrupt enable register when writing 1 to correspond bits. cp interrupt state clear interrupt state register when writing 1 to correspond bits. ap interrupt enable register em_latch_irq enable 1: enable 0: disable cpu_latch_irq enable 1: enable 0: disable rtc_latch_irq enable 1: enable 0: disable load_end_irq enable 1: enable 0: disable timer_idle_irq enable 1: enable 0: disable target_irq enable 1: enable 0: disable nb_pu_reach_irq enable 1: enable 0: disable sys_awk _irq enable 1: enable 0: disable Timer_awk_irq_enable 1: enable 0: disable gsm_pu_reach_irq enable 1: enable 0: disable osw2_irq enable 1: enable 0: disable ap interrupt enable set register set ap interrupt enable register when writing 1 to correspond bits. ap interrupt enable clear register clear ap interrupt enable register when writing 1 to correspond bits. ap interrupt state clear ap interrupt state register when writing 1 to correspond bits. LTEM1 high-level frame number register Ltem1 high-level frame number value LTE-M1 frame number LTE-M1 sub-frame number LTE-M1 frame offset register frame adjust time 0: adjust at next frame interrupt 1: adjust frame immetiately frame adjust direction 0: postive 1: negative LTE-M1 frame offest value (Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) LTE-M1 high-level frame read register LTE-M1 high-level frame value LTE-M1 frame read register LTE-M1 radio frame value LTE-M1 sub-frame value LTE-M1 counter LTE-M1 counter value LTE-M1 frame length register LTE-M1 frame length LTE-M1 frame length adjust register adjust time 0: adjust immetiately 1: adjust at next ltem frame interrupt LTE-M1 adjuste frame length. current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. LTE-M1 radio frame value time stamp register LTE-M1 high-level frame value time stamp register LTE-M1 sub-frame time stamp register LTE-M1 frame stamp value LTE-M1 counter time stamp register LTE-M1 stamp counter LTE-M2 high-level frame register LTE-M2 high-level frame value LTE-M2 radio frame value LTE-M2 sub-frame value LTE-M2 frame offset adjust register adjust time. 0: adjust at next frame interrupt 1: adjust frame immetiately adjust direction 0: postive 1: negative Frame offest value(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value at the time of frame interrupt genereted. otherwise write b-1 into this register then current frame minus this value at the time of frame interrupt generated.) LTE-M2 high-level frame read register LTE-M2 super read frame value LTE-M2 frame read register LTE-M2 radio frame read value LTE-M2 sub-frame read value LTE-M counter LTE-M counter LTE-M2 frame length LTE-M2 frame length value LTE-M2 frame length adjust register adjust time 0: adjust immetiately 1: adjust at next ltem frame interrupt LTE-M2 adjuste frame length. current Ltem frame length load the register when write happens,then backed the LFRAML at the time of lte frame interrupt occurred. LTE-M2 radio frame time stamp register LTE-M2 high-level frame time stamp register LTE-M2 sub-frame time stamp register LTE-M2 frame stamp value LTE-M2 counter time stamp register LTE-M2 stamp counter GSM frame register GSM frame value GSM frame offset adjust register adjust direction 0: postive 1: negative frame offest value (Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 into this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) GSM frame overflow register GSM frame overflow value LTE-M high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. LTE-M frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN LTE-M counter locked register LTE-M couner locked value LTE-M high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. LTE-M frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN LTE-M counter locked register LTE-M counter locked value GSM frame lock register GSM frame locked value GSM counter lock register GSM counter locked value time stamp register lock signal 000: ltem1 frame interrupt. 001: ltem2 frame interrupt. 010: gsm frame interrupt. 011: negative of 32k clock. 100: nb frame interrput. others: gsm frame interrupt. lock way 00: disable lock 01: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. 10: time stamp when lock signal comes after that bit 5 and 4 clear to be 0. 11: time stamp loop 1: time stamp immediately. 0: not effect current task planning time register task planning time register Layoutt register descending unit. 15’h0000: 1 15’h0001: 2 15’h0002: 3 …… 15’h7fff: 32768 Layout count time selection 0: ltem1 timer 1: ltem2 timer task planning 1: start task planing 0: end timing (The control bit is clear automatically after the timer is finished, and the software can be clear to bestop counting.) LTEM1 frame interrupt delay register 1 LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTEM1 frame interrupt delay register 2 LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTEM2 frame interrupt delay register 1 LTE-M2 frame interrupt delay, take ltem2_framc as a reference. LTEM2 frame interrupt delay register 2 LTE-M2 frame interrupt delay, take ltem2_framc as a reference. sub-frame interrupt enable register Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. TIMER enable register GNSS_LTE-M timer enable 0: disable 1: enable NB timer enable 0: disable 1: enable LTE-M timer enable 0: disable 1: enable (note: this timer is the reference lte timer.) GSM timer enable 0: disable 1: enable LTE-M2 timer enable 0: disable 1: enable LTE-M1 timer enable 0: disable 1: enable IDLE frame interrupt state register(can be clear by writing 1 to correspond bit) GNSS_LTE-M frame interrupt state 0: No interrupt occurred 1: interrupt occurred NB frame interrupt state 0: No interrupt occurred 1: interrupt occurred reference lte frame interrupt state 0: No interrupt occurred 1: interrupt occurred GSM frame interrupt state 0: No interrupt occurred 1: interrupt occurred LTE-M2 frame interrupt state 0: No interrupt occurred 1: interrupt occurred LTE-M1 frame interrupt state 0: No interrupt occurred 1: interrupt occurred IDLE LTE-M1 frame configuration register enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt frame number interrupt occurred when current frame reach this register. IDLE LTE-M2 frame configuration register enable(this bit is cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register. IDLE GSM frame configuration register enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_GSM IDLE REF_LTE frame configuration register IDLE REF LTE frame enable register enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable REF_LTE frame register REF_LTE frame locked register REF_LTE counter locked register reference lte counter locked value REF_32K CONT clocked register REF_LTE counter register reference lte counter GSM frame length GSM frame length value OSW2 configuration register 1: enable OSW2 timer 0: disable OSW2 Timing start value OSW2 counter register IDLE GSM frame interrupt counter setting register IDLE GSM frame interrupt generated when GSM frame counter reach GSM_FRAME_GSM and GSM counter equal to this register. LTEM1 interrupt delay setting register 3 LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTEM2 interrupt delay setting register 3 LTE-M2 frame interrupt delay, take ltem2_framc as a reference. idle time select register 1: select pd_xtal, 0: select chip_pd IDLE time register H value register The cycles number of 26M in 2^h_run_time 32k cycles H value register The cycles number of 122.88M in of 2^h_run_time 32k cycles Take over NB TCU enable register Enable mode(NB TCU suspend and this bits are cleared by hardware when take over started) 00: disbale or already release TCU. 01: take over TCU immediately 10: take over at gsm frame interrupt. 11: no effect. Restart NB TCU register restart TCU when gsm counter reach this register restart mode(this bits cleared when TCU restarts) 00: disable 01: restart TCU immediately 10: restart TCU when gsm frame interrupt occurred. 11: restart TCU when gsm framc equal to TC_END_FRAMC. Nb_lp_pu_done register TCU restart enable(accessed by software only.) Output to the port nb_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. H value register The cycles number of 61.44M in the length of 2^h_run_time 32k cycles H value register The cycles number of 61.44M in the length of 2^h_run_time 32k cycles IDLE NB frame register NB frame interrupt enable register nb_frame_irq enable 1: enable 0: disable NB frame interrupt state register cleared by writing 1 to correspond bit NB frame register NB frame value NB frame length NB frame length value NB frame offset adjust register adjust direction 0: postive 1: negative frame offest value (Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b- 1 to this register then current frame minus this value when frame interrupt occurred.) NB frame overflow register NB frame overflow value NB frame lock register NB frame locked value NB counter lock register NB counter locked value IDLE NB frame configuration register enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_NB IDLE NB frame interrupt counter setting register IDLE NB frame interrupt generated when NB frame counter reach IDLE_FRAME_NB and NB counter equal to this register. wakeup enable set register set wakeup enable register by writing 1 to correspond bits. wakeup enable clear register clear wakeup enable register by writing 1 to correspond bits. GSM framc read register Read enable register. This bit should be set first when read the value of GSM counter, then rd_enable bit cleared by hardware after locked the GSM counter. GSM framc NB framc read register Read enable register. This bit should be set first when read the value of NB counter, then rd_enable bit cleared by hardware after locked the NB counter. NB framc Eliminate jitter configuration register Eliminate jitter delay register Emilinate the jitter from awake signal when writing 1 to correspond bits. GGE low power Scheme selection signal 0: use RDA8909 LP Scheme 1: use IDLE module of LP Scheme NB low power Scheme selection signal 0: use RDA8909 LP Scheme 1: use IDLE module of LP Scheme 1:disbale PLL 0:enable PLL 1:disable PLL 0:enbale PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL set corresponding bits of PD_PLL_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits clean corresponding bits of PD_PLL_SW 0:Invariance of corresponding bits 1:clean corresponding bits select hardware signal or software register to control the PLL output clk switch 1:software register(bit6 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit5 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit4 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit3 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit2 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit1 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit0 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) set corresponding bits of PD_PLL_SEL 0:Invariance of corresponding bits 1:set 1 of corresponding bits clean corresponding bits of PD_PLL_SEL 0:Invariance of corresponding bits 1:clean corresponding bits 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk set corresponding bits of IDLE_CG_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits clean corresponding bits of IDLE_CG_SW 0:Invariance of corresponding bits 1:clean corresponding bits select hardware signal or software register to control the PLL output clk switch 1:software register(bit6 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit5 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit4 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit3 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit2 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit1 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit0 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) set corresponding bits of IDLE_CG_SEL 0:Invariance of corresponding bits 1:set 1 of corresponding bits clean corresponding bits of IDLE_CG_SEL 0:Invariance of corresponding bits 1:clean corresponding bits 1:control the RF_DIG enter in IDLE 0:control the RF_DIG exit to the IDLE select the hardware signal or software register to control the RF_DIG enter in or extit to IDLE model. 1:software register(RF_IDLE_ENABLE_SW) 0:hardware signal( pow_on signal invert of IDLE module) IDLE moduel reserved register 0 IDLE moduel reserved register 1 IDLE moduel reserved register 2 IDLE moduel reserved register 3 IDLE moduel reserved register 4 IDLE moduel reserved register 5 IDLE moduel reserved register 6 IDLE moduel reserved register 7 RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal UART module reset control: 0: reset； 1: reset release。 UART module clock control: 0: disable； 1: enable。 PSRAM IO LATCH: 0: release PSRAM PAD 1: no release PSRAM PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after PSRAM initialization when AP wake-up from deep sleep. LPDDR IO LATCH: 0: release LPDDR PAD 1: no release LPDDR PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after LPDDR initialization when AP wake-up from deep sleep. IDLE moduel reserved register 8 IDLE moduel reserved register 9 IDLE moduel reserved register 10 IDLE moduel reserved register 11 mon15_sel: 00: select nb_en. 01: select awk_sys_valid. 10: select awake[7]. 11: select target_timer_stat[1]. mon14_sel: 00: select gsm_en. 01: select wcn_chip_pd. 10: select awake[6]. 11: select target_timer_stat[0]. mon13_sel: 00: select wake_timer. 01: select wcn_pd_xtal. 10: select awake[5]. 11: select target_timer_enable. mon12_sel: 00: select timer_en_nb. 01: select wcn_pd_pll. 10: select awake[4]. 11: select nb_frame_int. mon11_sel: 00: select timer_en_gsm. 01: select wcn_idle_cg. 10: select awake[3]. 11: nb_lp_pu_done. mon10_sel: 00: select timer_en_ltem2. 01: select nb_en_sel. 10: select awake[2]. 11: select nb_lp_sf_slowrunning. mon9_sel: 00: select timer_en_ltem1. 01: select gsm_en_sel. 10: select awake[1]. 11: select nb_fint. mon8_sel: 00: select idst_nb_timer. 01: select idle_chip_pd. 10: select awake[0]. 11: select gsm_frame_int. mon7_sel: 00: select idst_gsm_timer 01: select idle_pd_xtal. 10: select awk_self. 11: gsm_lp_pu_done. mon6_sel: 00: select idst_ltem2_timer. 01: select idle_pd_pll. 10: select idst_gsm_ltem_timer. 11: select gsm_lp_sf_slowrunning. mon5_sel: 00: select idst_ltem1_timer. 01: select idle_idle_cg. 10: select awk_gsm_ltem_timner. 11: select gsm_fint. mon4_sel: 00: select idct_nb_timer. 01: select pow_on. 10: select idst_sys. 11: select rstctrl_uart. mon3_sel: 00: select idct_gsm_timer. 01: select idct_sys_valid. 10: select nb_lp_pu_reach. 11: select clken_uart. mon2_sel: 00: select idct_ltem2_timer. 01: select idct_ap. 10: select gsm_lp_pu_reach. 11: select psram_latch_reg. mon1_sel: 00: select idct_ltem1_timer 01: select idct_cp. 10: select osw2_awk 11: select lpddr_latch_reg mon0_sel: 00: select idct_timer. 01: select ltem1_fint. 10: select osw1_awk. 11: select ltem2_fint set corresponding bits of MON_SEL 0:Invariance of corresponding bits 1:set corresponding bits clear corresponding bits of MON_SEL 0:Invariance of corresponding bits 1:clear corresponding bits Interrupt generated when the reference 32K counter reach to this register value. 1: disable target timer. 0: enable The locked value of reference 32K when interrupt generated. Indicat the state of target timer in 32K clock domain Indicate the state of target timer in 122.88M clock domain 0:SLOW_CLK and system clk selected by software bit conrtol 1:SLOW_CLK and system clk select by hareware signal control 0:SLOW_CLK selected(between 26M and 32k) by software bit control 1:SLOW_CLK selected(between 26M and 32k) by hareware signal control The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. change H_VAL's time 1:pd_xtal 0:chip_pd 1:tstamp_i[1] 0:tstamp_i[0] 1:perip tstamp 0:inner tstamp 1:tstamp saved 0:nothing LTE-M framl ref adjust register adjust direction 0: postive 1: negative LTE-M framl abs adjust register adjust direction 0: postive 1: negative LTE-M framl ref adjust register adjust direction 0: postive 1: negative LTE-M framl abs adjust register adjust direction 0:postive 1:negative LTE-M1 LOAD change register 0:load_timer from lps 1:TP load LTE-M2 LOAD change register 0:load_timer from lps 1:TP load sub-frame interrupt enable register Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. sub-frame interrupt enable register 1:enable 0:disable 1:enable 0:disable 1:enable 0:disable GNSS_CAPTURE_LTE-M1 high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS_CAPTURE_LTE-M1 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS_CAPTURE_LTE-M1 counter locked register LTE-M couner locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS_CAPTURE_LTE-M1 high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS_CAPTURE_LTE-M1 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS_CAPTURE_LTE-M1 counter locked register LTE-M couner locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS_CAPTURE_LTE-M1 high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS_CAPTURE_LTE-M1 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS_CAPTURE_LTE-M1 counter locked register LTE-M couner locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS_CAPTURE_LTE-M1 high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS_CAPTURE_LTE-M1 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS_CAPTURE_LTE-M1 counter locked register LTE-M couner locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value GNSS CAPTURE LTE-M2 high-level frame lock register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. GNSS CAPTURE LTE-M2 frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN GNSS CAPTURE LTE-M2 counter locked register LTE-M counter locked value LTE-M3 LOAD change register IDLE LTEM3 frame register Number of frames ltem3 sleeped Number of sub-frames ltem3 sleeped. LTEM3 frame interrupt enable register ltem3_frame3_irq enable 1: enable 0: disable ltem3_frame2_irq enable 1: enable 0: disable ltem3_frame1_irq enable 1: enable 0: disable LTEM3 interrupt state register cleared by writing 1 to correspond bit LTEM3 high-level frame number register LTEM3 high-level frame number value LTE-M3 frame number LTE-M3 sub-frame number LTE-M3 frame offset register frame adjust time 0: adjust at next frame interrupt 1: adjust frame immetiately frame adjust direction 0: postive 1: negative LTE-M3 frame offest value (Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) LTE-M3 high-level frame read register LTE-M3 high-level frame value LTE-M3 frame read register LTE-M3 radio frame value LTE-M3 sub-frame value LTE-M3 counter LTE-M3 counter value LTE-M3 frame length register LTE-M3 frame length LTE-M3 frame length adjust register adjust time 0: adjust immetiately 1: adjust at next ltem frame interrupt LTE-M3 adjuste frame length. current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. LTE-M3 radio frame value time stamp register LTE-M3 high-level frame value time stamp register LTE-M3 sub-frame time stamp register LTE-M3 frame stamp value LTE-M3 counter time stamp register LTE-M3 stamp counter LTE-M framl ref adjust register adjust direction 0: postive 1: negative LTE-M framl abs adjust register adjust direction 0: postive 1: negative LTEM3 frame interrupt delay register 1 LTE-M3 frame interrupt delay, take ltem2_framc as a reference. LTEM3 frame interrupt delay register 2 LTE-M3 frame interrupt delay, take ltem3_framc as a reference. LTEM1 interrupt delay setting register 3 LTE-M3 frame interrupt delay, take ltem3_framc as a reference. sub-frame interrupt enable register Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. LTE-M high-level frame locked register LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. LTE-M frame locked register LTE-M frame locked value, lock the register LTEM_CFSR_FN LTE-M counter locked register LTE-M couner locked value IDLE LTE-M3 frame configuration register enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt frame number interrupt occurred when current frame reach this register. 用于选择各个子系统中的监控信号并通过第0根监控信号送出 用于选择各个子系统中的监控信号并通过第1根监控信号送出 用于选择各个子系统中的监控信号并通过第2根监控信号送出 用于选择各个子系统中的监控信号并通过第3根监控信号送出 用于选择各个子系统中的监控信号并通过第4根监控信号送出 用于选择各个子系统中的监控信号并通过第5根监控信号送出 用于选择各个子系统中的监控信号并通过第6根监控信号送出 用于选择各个子系统中的监控信号并通过第7根监控信号送出 monitor_o[0]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[1]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[2]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[3]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[4]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[5]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[6]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 monitor_o[7]选择： 3'h0: 子系统0 3'h1: 子系统1 3'h2: 子系统2 3'h3: 子系统3 3'h4: 子系统4 3'h5: 子系统5 3'h6: 子系统6 3'h7: 子系统7 监控使能 1：使能监控 0：不使能监控 monitor output signal value. power domain shutdown/on controled by hardware signal or sofeware register. sysmail0 interrupt bit set register sysmail0 interrupt clean register sysmail0 interrupt mask register sysmail0 interrupt status register sysmail0 interrupt mask status register sysmail1 Interrupt generate register sysmail1 interrupt bit set register sysmail1 interrupt clean register sysmail1 interrupt mask register sysmail1 interrupt status register sysmail1 interrupt mask status register sysmail2 Interrupt generate register sysmail2 interrupt bit set register sysmail2 interrupt clean register sysmail2 interrupt mask register sysmail2 interrupt status register sysmail2 interrupt mask status register sysmail3 Interrupt generate register sysmail3 interrupt bit set register sysmail3 interrupt clean register sysmail3 interrupt mask register sysmail3 interrupt status register sysmail3 interrupt mask status register sysmail4 Interrupt generate register sysmail4 interrupt bit set register sysmail4 interrupt clean register sysmail4 interrupt mask register sysmail4 interrupt status register sysmail4 interrupt mask status register sysmail5 Interrupt generate register sysmail5 interrupt bit set register sysmail5 interrupt clean register sysmail5 interrupt mask register sysmail5 interrupt status register sysmail5 interrupt mask status register ACK偏移索引 ACK偏移索引 RI的MCS偏移索引 RI的MCS偏移索引 CQI的MCS偏移索引 CQI的MCS偏移索引 初始传输块大小数据量寄存器 PUSCH模块使能时表示PUSCH传输块大小，即传输块CRC添加前的数据量，单位为bit 传输块大小数据量寄存器 PUSCH模块使能时表示PUSCH传输块大小，即传输块CRC添加前的数据量，单位为bit 调制方式寄存器 00：BPSK 01：QPSK 10：16QAM 11：64QAM 冗余版本号 冗余版本号 PUSCH及初传PUSCH占用的带宽（子载波个数） 初传PUSCH占用的带宽（子载波个数） 当前PUSCH占用的带宽（子载波个数） PUSCH及初传PUSCH占用的符号个数 RU个数 初传PUSCH占用符号数：对于CAT1/CATM， 表示1个子帧占用的PUSCH DATA的符号个 数；对于CAT-NB，表示1个RU占用的符号个数 当前PUSCH占用符号数：对于CAT1/CATM，表示1个子帧占用的 PUSCH DATA的符号个数；对于CAT-NB， 表示1个RU占用的符号个数 CQI信息比特数据寄存器 CQI信息比特数据寄存器 CQI信息比特数据及比特长度寄存器 编码前CQI信息最小比特长度 编码前CQI信息比特长度，最大为65 编码前CQI信息比特位64 RI信息比特数据及比特长度寄存器 编码前RI信息比特长度 编码前RI信息 ACK信息比特数据及比特长度寄存器 编码前ACK信息比特长度，最大为4 编码前ACK信息 ACK编码复用绑定选择及扰码序列指示寄存器 0：FDD或TDD的HARQ-ACK复用模式 1：TDD的HARQ-ACK绑定模式 TDD HARQ-ACK绑定模式时，扰码序列的选择索引值 PUCCH格式寄存器 PUCCH格式 000~010：RESERVED 011：格式2 100：格式2a 101：格式2b 110~111：RESERVED U和U逆寄存器 U逆的值 U值 CV寄存器 CV值 生成GOLD序列时第二个序列的初始值寄存器 生成GOLD序列时，第二个序列的初始值 控制寄存器 1：使能PUSCH模块运算完毕后硬件启动ULDFT模块 0：不使能PUSCH模块运算完毕后硬件启动ULDFT模块 00：启动PUSCH运算 01：启动PUCCH UCI编码加扰运算 10：启动PRACH运算 11：启动NPUSCH格式1（NPUSCH格式2不调用PUSCH IP） 与FUNC_SEL联合配置，选择PUSCH UCI或PUCCH UCI，FUNC_SEL为‘00’时选择PUSCH UCI，FUNC_SEL为‘01’时选择PUCCH UCI： 0：不启动UCI编码运算 1：启动UCI编码运算 PUSCH_BUFFER中MEM序号指示 00：PUSCH_BUF1； 01：PUSCH_BUF2； 10：PUSCH_BUF3； 11：PRACH_BUF； 0：不启动PUSCH_BUFFER功能； 1：启动PUSCH_BUFFER功能； PRACH中ZC序列长度指示 0：ZC序列长度为139； 1：ZC序列长度为839； 0：PUSCH中的CRC不对输入数据进行Byte反转 1：PUSCH中的CRC对输入数据进行Byte反转 0：LTE模式下模块中断不使能 1：LTE模式下模块中断使能 0：不启动PUSCH的信道加扰 1：启动PUSCH的信道加扰 0：不启动PUSCH的信道交织 1：启动PUSCH的信道交织 0：不启动PUSCH的Turbo编码和速率匹配 1：启动PUSCH的Turbo编码和速率匹配 0：不启动PUSCH的CRC 1：启动PUSCH的CRC 0：不启动功能模块（LTE模式） 1：启动功能模块（LTE模式） 中断标志寄存器 中断标志 0：功能模块未完成 1：功能模块完成，中断指示 PUCCH format2/2a/2b UCI编码加扰结果 PUCCH format2/2a/2b UCI编码加扰结果 CTRL系统参数寄存器 Schedule SIB1 BR R13（PBML使能时需要配置） PHICH resource（PBML使能时需要配置） PHICH duration（PBML使能时需要配置） 上行带宽指示： 0：1.4Mhz 1：3Mhz； 2：5Mhz； 3：10Mhz； 4：15Mhz； 5：20Mhz 6~7：预留（保护成配置5） Ng的指示： 0：1/6 1：1/2 2：1 3：2 传输模式： 1~:9：tm1,tm2,…,tm9 TDD模式时，特殊子帧配置：0~9（无效保 护成9） 上下行配置：0~6（无效保护成6） 带宽指示： 0：1.4Mhz 1：3Mhz； 2：5Mhz； 3：10Mhz； 4：15Mhz； 5：20Mhz 6~7：预留（保护成配置5） 发射天线数： 0：1发射天线 1：2发射天线 2：4发射天线 3：预留（保护成配置2） CP类型： 0：常规CP 1：扩展CP FDD或TDD指示： 0：TDD 1：FDD CTRL小区ID寄存器 小区ID：0~503 CTRL系统参数寄存器 上行带宽指示： 0：1.4Mhz 1：3Mhz； 2：5Mhz； 3：10Mhz； 4：15Mhz； 5：20Mhz 6~7：预留（保护成配置5） Ng的指示： 0：1/6 1：1/2 2：1 3：2 传输模式： 1~:9：tm1,tm2,…,tm9 TDD模式时，特殊子帧配置：0~9（无效保护成9） 上下行配置：0~6（无效保护成6） 带宽指示： 0：1.4Mhz 1：3Mhz； 2：5Mhz； 3：10Mhz； 4：15Mhz； 5：20Mhz 6~7：预留（保护成配置5） 发射天线数： 0：1发射天线 1：2发射天线 2：4发射天线 3：预留（保护成配置2） CP类型： 0：常规CP 1：扩展CP FDD或TDD指示： 0：TDD 1：FDD CTRL小区ID寄存器 MBSFN ID：0~255 小区ID：0~503 RA-RNTI/TEMP-C-RNTI寄存器 Temp-C-RNTI RA_RNTI C-RNTI/SPS-C-RNTI寄存器 SPS_RNTI C_RNTI TPC-PUCCH-RNTI/TPC-PUSCH-RNTI寄存器 TPC-PUCSH-RNTI TPC-PUCCH-RNTI G_RNTI寄存器 G_RNTI CSI的RS分布配置寄存器0 第2组时域上，一个PRB的CSI-RS的分布指 示，同CSIRS_GROUP1。 第1组时域上，一个PRB的CSI-RS的分布指 示，第0比特到11比特分别指示PRB中RE#0 到RE#11。如果第0比特为1表示RE#0为 CSI-RS，反之则否。 CSI的RS分布配置寄存器1 子帧内含CSI-RS的OFDM符号对业务1（PDSCH业务）的处理指示。Norm-CP时，24到30比特分别表示OFDM#5、6、8、9、10、12和13；Ext-CP时，24到29比特分别表示OFDM#4、5、7、8、10和11；以Norm-CP的第24比特进行说明，如果为1表示OFDM#5上视业务1为不存在；如果为0表示OFDM#5上业务1的数据应避开CSI-RS所占的子载波位置。 第4组时域上，一个PRB的CSI-RS的分布指示，同CSIRS_GROUP1。 第3组时域上，一个PRB的CSI-RS的分布指示，同CSIRS_GROUP1。 PMI配置寄存器 PMI 码本限制集(codebookSubsetRestriction)： 0：PMI表对应bit的行需要计算 1：PMI表对应bit的行不需要计算 PDCCH配置寄存器 每个BIT分布标识： Bit0:1个OFDM符号CFI Bit1:2个OFDM符号CFI Bit2:3个OFDM符号CFI Bit3:4个OFDM符号CFI 0：无效 1：有效 PHICH配置寄存器 HI的OFDM条件选择：0~3 PHICH1使能： 0：使能 1：不使能 PHICH1序列号：0~7 PHICH1组号：0~99 PHICH0使能： 0：使能 1：不使能 PHICH0序列号：0~7 PHICH0组号：0~99 PDCCH配置寄存器 UE空间DCI第二个长度：max57 UE空间DCI第一个长度：max57 COMM空间DCI第二个长度：max57 COMM空间DCI第一个长度：max57 DCILEN选择： 0：硬件表格 1：软件配置 PUSCH增强使能： 0：DCI0 1：DCI0C CSI长度选择： 0：1 1：2 天线选择使能： 0：天线选择不使能 1：天线选择使能 SRS激活： 0：无DCI中SRS_REQ域 1：有DCI中SRS_REQ域 PDCCH盲检个数： 0:1 1:2 2:3 3:4 … 7：8 PDSCH –C/RA/T相关输入信息寄存器 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 PDSCH -SI相关输入信息寄存器 资源分配类型： 0：集中式 1：分布式 冗余版本：0~3 传输块长度：max2216 PDSCH -PAGING相关输入信息寄存器 资源分配类型： 0：集中式 1：分布式 冗余版本：0~3 传输块长度：max2216 CTRL帧号寄存器 超帧号：0~65535 无线帧号:0~1023 子帧号:0~9 DATA帧号寄存器 超帧号：0~65535 无线帧号:0~1023 子帧号:0~9 LDTC CTRL业务配置寄存器 SC-N-RNTI使能： 0：不使能 1：使能 SC-RNTI使能： 0：不使能 1：使能 G-RNTI使能： 0：不使能 1：使能 TPC-PUCCH-RNTI使能： 0：不使能 1：使能 TPC-PUSCH-RNTI使能： 0：不使能 1：使能 Temp-C-RNTI使能： 0：不使能 1：使能 SPS-C-RNTI使能： 0：不使能 1：使能 C-RNTI使能： 0：不使能 1：使能 RA-RNTI使能： 0：不使能 1：使能 P-RNTI使能： 0：不使能 1：使能 SI-RNTI使能： 0：不使能 1：使能 LDTC DATA业务配置寄存器 SC-RNTI使能： 0：不使能 1：使能 G-RNTI使能： 0：不使能 1：使能 Temp-C-RNTI使能： 0：不使能 1：使能 SPS-C-RNTI使能： 0：不使能 1：使能 C-RNTI使能： 0：不使能 1：使能 RA-RNTI使能： 0：不使能 1：使能 P-RNTI使能： 0：不使能 1：使能 SI-RNTI使能： 0：不使能 1：使能 LDTC CTRL控制寄存器 SINR DMA触发使能： 0：不使能 1：使能 PMI DMA触发使能： 0：不使能 1：使能 SINR中断使能： 0：不使能 1：使能 PMI中断使能： 0：不使能 1：使能 PDCCH中断使能： 0：不使能 1：使能 PBCH中断使能： 0：不使能 1：使能 MBMS子帧指示： 0：非MBMS子帧 1：MBMS子帧 CTRL QFQT乒乓选择： 0：第1块乒 1：第2块乓 2：第3块 PBCH计算的起始： 0：非起始 1：起始 SINR使能： 0：使能 1：不使能 PMI计算使能： 0：不使能 1：使能 HI计算使能： 0：不使能 1：使能 PDCCH使能： 0：不使能 1：使能 PBCH使能： 0：不使能 1：使能 LDTC DATA控制寄存器 PDSCH DMA触发使能： 0：不使能 1：使能 PDSCH中断使能： 0：不使能 1：使能 DATA QFQT乒乓选择： 0：第1块乒 1：第2块乓 2：第3块 CSIRS使能： 0：不使能 1：使能 SI的HQBUF选择： 0：选择HQBUF0 1：选择HQBUF1 PDSCH计算的起始： 0：非起始 1：起始 PDS计算的起始： 0：非起始 1：起始 PDSCH使能： 0：不使能 1：使能 LDTC CTRL启动寄存器 启动LDTC模块： 0：不启动或者已经启动并清除 1：启动 LDTC DATA启动寄存器 启动LDTC模块： 0：不启动或者已经启动并清除 1：启动 CTRL标志寄存器 DCI当前子帧检出有效标识： 0：无DCI检出； 1：对应比特的DCI当前子帧检出有效 MIB当前子帧检出有效标识： 0：无MIB检出； 1：对应比特的MIB当前子帧检出有效 SINR完成标志： 0：无中断 1：中断 PMI完成标志： 0：无中断 1：中断 PDCCH完成标志： 0：无中断 1：中断 PBCH完成标志： 0：无中断 1：中断 DATA标志寄存器 PAGING译码结果数据（含CRC校验位），全零标志： 0：数据不为全零 1：数据为全零 PAGING译码CRC标志： 0：CRC校验正确 1：CRC校验错误 SI译码结果数据（含CRC校验位），全零标志： 0：数据不为全零 1：数据为全零 SI译码CRC标志： 0：CRC校验正确 1：CRC校验错误 PDSCH 译码结果数据（含CRC校验位），全零标志： 0：数据不为全零 1：数据为全零 PDSCH 译码CRC标志： 0：CRC校验正确 1：CRC校验错误 PDSCH完成标志： 0：无中断 1：中断 BUF指示寄存器 FH的data使用指示： 0：使用FH0 1：使用FH1 FH的ctrl使用指示： 0：使用FH0 1：使用FH1 DSCHOUT使用指示： 0：使用DSCHOUT0 1：使用DSCHOUT1 FFTBUF使用指示： 0：使用FFTBUF0 1：使用FFTBUF1 ALG_COMM_PARA通用参数寄存器 PDCCH归一化策略门限个数 G的Q值调整因子： 0：Q15 1：Q16 … 7：Q22 HQ 合并方式选择： 0：CC合并 1：IR合并 HQ BUF的比特位宽的大小： 0：4bit 1：6bit SD使用G或者noise进行信号检测计算： 0：用noise计算 1：用GM矩阵 PMI/PWR子带宽带选择： 0：小带宽 1：大带宽 具体见下表描述 CTCG起始位置选择： 0：从OFDM4(包括OFDM4)前有效CRS为样本 1：从OFDM8(包括OFDM8)前有效CRS为样本 CRS G的长度选择： 0：1PRB 1：2PRB CRS频域估计滑动窗长（3或6 PRB） 0：3PRB 1：6PRB UE RS时，处理PRB的个数，取值为1,3 0：不使能 1：使能 CHE频域参数寄存器 乘累加后由16bit数据截取为10bit数据的截取方式选择 0：按接口寄存器配置直接截位 1：最大值归一化截位 乘累加后由16bit数据截取为10bit数据的比特选择： 0x0：截取选择15~6 0x1：截取选择14~5 0x2：截取选择13~4 0x3：截取选择12~3 0x4：截取选择11~2 0x5：截取选择10~1 0x6：截取选择9~0 其他：reserved，不可配置 乘累加后截取16bit数据的比特选择： 0x0：截取选择28~13 0x1：截取选择27~12 0x2：截取选择26~11 0x3：截取选择25~10 0x4：截取选择24~9 0x5：截取选择23~8 0x6：截取选择22~7 0x7：截取选择21~6 0x8：截取选择20~5 0x9：截取选择19~4 0xa：截取选择18~3 0xb：截取选择17~2 0xc：截取选择16~1 0xd：截取选择15~0 其他：Reserved CHE时域参数寄存器 时域估计乘累加后截取比特选择： 0x0：截取选择25~10 0x1：截取选择24~9 0x2：截取选择23~8 0x3：截取选择22~7 0x4：截取选择21~6 0x5：截取选择20~5 0x6：截取选择19~4 0x7：截取选择18~3 0x8：截取选择17~2 0x9：截取选择16~1 0xa：截取选择15~0 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit[99:96]表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit[99:96]表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit[99:96]表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit[99:96]表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 资源占用信息寄存器 前0.5ms资源bitmap指示：对应bit[99:96]表示不同的prb，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 码本索引寄存器 子带8的码本索引 子带7的码本索引 子带6的码本索引 子带5的码本索引 子带4的码本索引 子带3的码本索引 子带2的码本索引 子带1的码本索引 码本索引寄存器 子带16的码本索引 子带15的码本索引 子带14的码本索引 子带13的码本索引 子带12的码本索引 子带11的码本索引 子带10的码本索引 子带9的码本索引 码本索引寄存器 子带24的码本索引 子带23的码本索引 子带22的码本索引 子带21的码本索引 子带20的码本索引 子带19的码本索引 子带18的码本索引 子带17的码本索引 码本索引寄存器 子带25的码本索引 CRS获得的宽带信号功率寄存器 CRS获得的宽带噪声功率寄存器 CRS获得的宽带信号功率AGC寄存器 接收天线1上CRS获得的宽带信号功率AGC CRS获得的宽带噪声功率AGC寄存器 接收天线1上CRS获得的宽带噪声功率AGC DATA截位因子寄存器0 PDCCH的截位方式： 0：固定截位 1：按照最大值动态截位 PBCH的截位方式： 0：固定截位 1：按照下面均值范围动态截位 截位范围值1 截位范围值0 DATA截位因子寄存器2 PDSCH的截位方式： 0：固定截位 1：按照下面均值范围动态截位 截位范围值0 DATA截位因子寄存器3 截位范围值2 截位范围值1 DATA截位因子寄存器4 截位范围值4 截位范围值3 DATA调整因子(CRS)寄存器0 值，用于当OFDM符号上有CELL RS时，对data调整 值，用于当OFDM符号上无CELL RS时，对data调整 DATA调整因子(URS)寄存器1 值，用于当OFDM符号上有CELL RS时，对data调整 值，用于当OFDM符号上无CELL RS时，对data调整 DATA调整因子(URS)寄存器2 值，用于当OFDM符号上有CELL RS时，对data调整 值，用于当OFDM符号上无CELL RS时，对data调整 CTRL噪声值寄存器 CTRL噪声绝对AGC值 噪声绝对AGC值（有符号） CTRL噪声门限寄存器 噪声门限（PDCCH、PBCH） DATA噪声值寄存器 DATA噪声绝对AGC值 噪声绝对AGC值（有符号） DATA噪声门限寄存器 噪声门限（辅业务） 噪声门限（主业务） SDOUT截位因子PBCH输出寄存器0 PDCCH截位INDX值 PBCH截位INDX值3 PBCH截位INDX值2 PBCH截位INDX值1 PBCH截位INDX值0 SDOUT截位因子PDSCH输出寄存器0 截位INDX值7 截位INDX值6 截位INDX值5 截位INDX值4 截位INDX值3 截位INDX值2 截位INDX值1 截位INDX值0 SDOUT截位因子PDSCH输出寄存器1 截位INDX值15 截位INDX值14 截位INDX值13 截位INDX值12 截位INDX值11 截位INDX值10 截位INDX值9 截位INDX值8 SDOUT截位因子PDSCH输出寄存器2 截位INDX值23 截位INDX值22 截位INDX值21 截位INDX值20 截位INDX值19 截位INDX值18 截位INDX值17 截位INDX值16 SDOUT截位因子PDSCH输出寄存器3 截位INDX值31 截位INDX值30 截位INDX值29 截位INDX值28 截位INDX值27 截位INDX值26 截位INDX值25 截位INDX值24 SDOUT截位因子PDSCH输出寄存器4 截位INDX值34 截位INDX值33 截位INDX值32 HARQBUF存储占用指示寄存器 第15块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第14块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第13块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第12块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第11块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第10块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第9块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第8块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第7块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第6块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第5块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第4块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第3块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第2块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第1块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； 第0块HARQBUFFER存储状态指示 0:该块资源已经被释放； 1:该块资源正在被占用； HARQBUF存储进程指示0寄存器 第7块HARQBUFFER存储进程指示:0~15 第6块HARQBUFFER存储进程指示:0~15 第5块HARQBUFFER存储进程指示:0~15 第4块HARQBUFFER存储进程指示:0~15 第3块HARQBUFFER存储进程指示:0~15 第2块HARQBUFFER存储进程指示:0~15 第1块HARQBUFFER存储进程指示:0~15 第0块HARQBUFFER存储进程指示:0~15 HARQBUF存储进程指示1寄存器 第15块HARQBUFFER存储进程指示:0~15 第14块HARQBUFFER存储进程指示:0~15 第13块HARQBUFFER存储进程指示:0~15 第12块HARQBUFFER存储进程指示:0~15 第11块HARQBUFFER存储进程指示:0~15 第10块HARQBUFFER存储进程指示:0~15 第9块HARQBUFFER存储进程指示:0~15 第8块HARQBUFFER存储进程指示:0~15 TURBO参数寄存器 归一化选择：64QAM 0：2倍均值 1：最大值 归一化选择：16QAM 0：2倍均值 1：最大值 归一化选择：QPSK 0：2倍均值 1：最大值 移位使能：64QAM 0：不使能 1：使能 移位使能：16QAM 0：不使能 1：使能 移位使能：QPSK 0：不使能 1：使能 移位迭代次数2 移位迭代次数1 最大译码迭代次数减1 （最大译码次数为9）：0~8 TURBO迭代次数输出寄存器 PAG实际迭代次数-1 SI实际迭代次数-1 PDS第二块实际迭代次数-1 PDS第一块实际迭代次数-1 VIT参数寄存器 掩码使能： 0：不使能 1：使能 CRC类型： 0：CRC16 1：CRC24A DMA触发使能： 0：不使能 1：使能 中断使能： 0：不使能 1：使能 VIT迭代次数 0:1 1:2 2:3 3:4 VIT FA配置寄存器 掩码 PDCCH的false alarm使能 PDCCH的false alarm的重构差异百分比门限(U8Q7) VIT单独调用长度寄存器 VIT长度 VIT单独调用启动寄存器 VIT启动： 0：不启动或者完成 1：启动 VIT标志寄存器 VIT CRC译码结果数据（含CRC校验位），全零标志： 0：数据不为全零 1：数据为全零 VIT CRC校验正确完成标志： 0：正确 1：错误 PBCH完成标志： 0：无中断 1：中断 VIT FA输出寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 CFICH输出寄存器 CFI输出的值： 1~4（1.4M固定加了1后的结果） PHICH输出寄存器 HI1输出的值 HI0输出的值 软件输入CTRL寄存器 软件输入DATA寄存器 软件输出CTRL寄存器 软件输出DATA寄存器 PDSCH重复次数寄存器 PDSCH 第15个进程重传次数指示 PDSCH 第14个进程重传次数指示 PDSCH 第13个进程重传次数指示 PDSCH 第12个进程重传次数指示 PDSCH 第11个进程重传次数指示 PDSCH 第10个进程重传次数指示 PDSCH 第9个进程重传次数指示 PDSCH 第8个进程重传次数指示 PDSCH 第7个进程重传次数指示 PDSCH 第6个进程重传次数指示 PDSCH 第5个进程重传次数指示 PDSCH 第4个进程重传次数指示 PDSCH 第3个进程重传次数指示 PDSCH 第2个进程重传次数指示 PDSCH 第1个进程重传次数指示 PDSCH 第0个进程重传次数指示 SI重复次数寄存器 SI第1个进程重传次数指示 SI第0个进程重传次数指示 PBCH重复次数寄存器 PBCH重传次数指示 运行时间控制寄存器 运行时间控制寄存器 ABIS使能配置寄存器 邻区2天线干扰的情况选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 邻区1天线干扰的情况选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 服务小区天线选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 MultiCell计算使能 0：SingalCell 1：MultiCell ABIS移位因子方式选择： 0：选择软件配置 1：选择DLFFT直接传递 ABIS使能： 0：不使能 1：使能 ABIS的SD PDSCH清零使能： 0：不使能 1：使能 ABIS的SD MPDCCH清零使能： 0：不使能 1：使能 ABIS的SD PBCH清零使能： 0：不使能 1：使能 ABIS小区配置寄存器 检测到干扰邻区的个数： 00：0个干扰邻区 01：1个干扰邻区 10：2个干扰邻区 其他：默认0个干扰邻区 干扰邻区2发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区1发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区2 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区1 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区2 CELL ID值 干扰邻区1 CELL ID值 小区时延值寄存器1 干扰邻区1相对本区时延值（单位TS） 小区时延值寄存器2 干扰邻区2相对本区时延值（单位TS） ABIS干扰移位寄存器 ABIS干扰类型3（邻区1+2）移位值 ABIS干扰类型2（邻区2）移位值 ABIS干扰类型1（邻区1）移位值 ABIS使能配置寄存器 邻区2天线干扰的情况选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 邻区1天线干扰的情况选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 服务小区天线选择： 0：发射天线数为2的情况下：port0和port1都干扰；发射天线数为4的情况下：port0、port1、port2、port3都干扰 1：发射天线数为2的情况下：只有port0干扰；发射天线数为4的情况下：port0、port2、port3都干扰 2：发射天线数为2的情况下：只有port1干扰；发射天线数为4的情况下：port1、port2、port3都干扰 ABIS移位因子方式选择： 0：选择软件配置 1：选择DLFFT直接传递 ABIS使能： 0：不使能 1：使能 ABIS的SD PDSCH清零使能： 0：不使能 1：使能 ABIS的SD MPDCCH清零使能： 0：不使能 1：使能 ABIS的SD PBCH清零使能： 0：不使能 1：使能 ABIS小区配置寄存器 检测到干扰邻区的个数： 00：0个干扰邻区 01：1个干扰邻区 10：2个干扰邻区 其他：默认0个干扰邻区 干扰邻区2发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区2发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区2 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区1 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区2 CELL ID值 干扰邻区1 CELL ID值 小区时延值寄存器 干扰邻区1相对本区时延值（单位TS） 小区时延值寄存器 干扰邻区2相对本区时延值（单位TS） ABIS干扰移位寄存器 ABIS干扰类型3（邻区1+2）移位值 ABIS干扰类型2（邻区2）移位值 ABIS干扰类型1（邻区1）移位值 REIS配置寄存器 REIS使能： 0：不使能 1：使能 REIS的NUM个数 REIS位置寄存器0 REIS1的移位指示 REIS1的RE位置（20M带宽1200个RE的绝对位置） REIS0的移位指示 REIS0的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器1 REIS3的移位指示 REIS3的RE位置（20M带宽1200个RE的绝对位置） REIS2的移位指示 REIS2的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器2 REIS5的移位指示 REIS5的RE位置（20M带宽1200个RE的绝对位置） REIS4的移位指示 REIS4的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器3 REIS7的移位指示 REIS7的RE位置（20M带宽1200个RE的绝对位置） REIS6的移位指示 REIS6的RE位置（20M带宽1200个RE的绝对位置） RBIS参数寄存器 发射天线数为2的情况下，ABIS判决的PORT选择： 0：使用port0 1：使用port1 RBIS使能： 0：不使能 1：使能 RBIS的SD PDSCH清零使能： 0：不使能 1：使能 RBIS的SD MPDCCH清零使能： 0：不使能 1：使能 RBIS的SD PBCH清零使能： 0：不使能 1：使能 RBIS使用直接位置指示： 0：不使用直接位置 1：使用直接位置 RBIS检测个数： 0：1 1：2 2：3 3：4 4：5 RBIS的直接位置 RBIS因子 RBIS检测到干扰所在位置输出寄存器0 RBIS检测出的干扰位置：0~99 RBIS检测出的干扰位置：0~99 RBIS检测出的干扰位置：0~99 RBIS检测出的干扰位置：0~99 RBIS检测到干扰所在位置输出寄存器1 RBIS检测出的干扰位置：0~99 RBIS检测到均值输出寄存器 RBIS检测到均值输出寄存器 RBIS检测出的最大值 加权值寄存器 PBML使能： 0：不使能 1：使能 需要修正的LLR信息长度 需要修正的LLR信息起始位置 LLR修正加权值： 0~255 控制链路状态输出寄存器 控制链路状态输出寄存器 数据链路状态输出寄存器 数据链路状态输出寄存器 CTRL帧号输出寄存器 超帧号：0~65535 无线帧号：0~1023 子帧号：0~9 DATA帧号输出寄存器 超帧号：0~65535 无线帧号：0~1023 子帧号：0~9 PDSCH HARQIN寄存器 主业务CB0在HARQIN MEM0的长度 主业务CB0在HARQIN MEM0的起始 PDSCH HARQIN寄存器 主业务CB0的总长度 主业务CB0在HARQIN MEM1的起始 PDSCH HARQIN寄存器 主业务CB1在HARQIN MEM0的长度 主业务CB1在HARQIN MEM0的起始 PDSCH HARQIN寄存器 主业务CB1的总长度 主业务CB1在HARQIN MEM1的起始 SI HARQIN寄存器 SI业务CB1在HARQIN MEM0的长度 SI业务CB1在HARQIN MEM0的起始 SI HARQIN寄存器 SI业务CB1的总长度 SI业务CB1在HARQIN MEM1的起始 PAGING HARQIN寄存器 PAGING业务CB1在HARQIN MEM0的长度 PAGING业务CB1在HARQIN MEM0的起始 PAGING HARQIN寄存器 PAGING业务CB1的总长度 PAGING业务CB1在HARQIN MEM1的起始 ABIS干扰移位输出寄存器 ABIS干扰类型3（邻区1+2）移位值 ABIS干扰类型2（邻区2）移位值 ABIS干扰类型1（邻区1）移位值 ABIS干扰移位输出寄存器 ABIS干扰类型3（邻区1+2）移位值 ABIS干扰类型2（邻区2）移位值 ABIS干扰类型1（邻区1）移位值 小区时延值寄存器 干扰邻区1相对本区时延值（单位TS） 小区时延值寄存器 干扰邻区2相对本区时延值（单位TS） 小区时延门限值寄存器 干扰邻区相对本区时延门限值（单位TS） DCI0输出寄存器1 DCI0输出寄存器2 DCI0功率寄存器 DCI功率 DCI0 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI0 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI1A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI0 1:DCI1 2:DCI1A 3:DCI1B 4:DCI1C 5:DCI1D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI0 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI0 信息寄存器3 DCI0C中的重复次数指示 调制编码方案 DCI2/DCI2A/DCI2B/DCI2C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI0的循环移位指示 DCI0的CQI指示 DCI2/DCI2A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI0、DCI1A、DCI2B TDD、DCI2C TDD 新数据反转指示 DCI1D POWER OFFSET DAI域 功控参数 DCI0 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI0 信息寄存器5 DCI0 信息寄存器6 DCI0 信息寄存器7 DCI0 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI0 信息寄存器9 DCI0 信息寄存器10 DCI0 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI1输出寄存器1 DCI1输出寄存器2 DCI1功率寄存器 DCI功率 DCI1 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI1 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI1A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI1 1:DCI1 2:DCI1A 3:DCI1B 4:DCI1C 5:DCI1D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI1 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI1 信息寄存器3 DCI1C中的重复次数指示 调制编码方案 DCI2/DCI2A/DCI2B/DCI2C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI1的循环移位指示 DCI1的CQI指示 DCI2/DCI2A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI1、DCI1A、DCI2B TDD、DCI2C TDD 新数据反转指示 DCI1D POWER OFFSET DAI域 功控参数 DCI1 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI1 信息寄存器5 DCI1 信息寄存器6 DCI1 信息寄存器7 DCI1 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI1 信息寄存器9 DCI1 信息寄存器10 DCI1 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI2输出寄存器1 DCI2输出寄存器2 DCI2功率寄存器 DCI功率 DCI2 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI2 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI2A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI2 1:DCI2 2:DCI2A 3:DCI2B 4:DCI2C 5:DCI2D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI2 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI2 信息寄存器3 DCI2C中的重复次数指示 调制编码方案 DCI2/DCI2A/DCI2B/DCI2C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI2的循环移位指示 DCI2的CQI指示 DCI2/DCI2A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI2、DCI2A、DCI2B TDD、DCI2C TDD 新数据反转指示 DCI2D POWER OFFSET DAI域 功控参数 DCI2 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI2 信息寄存器5 DCI2 信息寄存器6 DCI2 信息寄存器7 DCI2 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI2 信息寄存器9 DCI2 信息寄存器10 DCI2 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI3输出寄存器1 DCI3输出寄存器2 DCI3功率寄存器 DCI功率 DCI3 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI3 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI3A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI3 1:DCI3 2:DCI3A 3:DCI3B 4:DCI3C 5:DCI3D 6:DCI3 7:DCI3A 8:DCI3B 9:DCI3C 10:DCI3/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI3 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI3 信息寄存器3 DCI3C中的重复次数指示 调制编码方案 DCI3/DCI3A/DCI3B/DCI3C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI3的循环移位指示 DCI3的CQI指示 DCI3/DCI3A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI3、DCI3A、DCI3B TDD、DCI3C TDD 新数据反转指示 DCI3D POWER OFFSET DAI域 功控参数 DCI3 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI3 信息寄存器5 DCI3 信息寄存器6 DCI3 信息寄存器7 DCI3 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI3 信息寄存器9 DCI3 信息寄存器10 DCI3 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI4输出寄存器1 DCI4输出寄存器2 DCI4功率寄存器 DCI功率 DCI4 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI4 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI4A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI4 1:DCI4 2:DCI4A 3:DCI4B 4:DCI4C 5:DCI4D 6:DCI4 7:DCI4A 8:DCI4B 9:DCI4C 10:DCI4/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI4 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI4 信息寄存器3 DCI4C中的重复次数指示 调制编码方案 DCI4/DCI4A/DCI4B/DCI4C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI4的循环移位指示 DCI4的CQI指示 DCI4/DCI4A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI4、DCI4A、DCI4B TDD、DCI4C TDD 新数据反转指示 DCI4D POWER OFFSET DAI域 功控参数 DCI4 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI4 信息寄存器5 DCI4 信息寄存器6 DCI4 信息寄存器7 DCI4 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI4 信息寄存器9 DCI4 信息寄存器10 DCI4 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI5输出寄存器1 DCI5输出寄存器2 DCI5功率寄存器 DCI功率 DCI5 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI5 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI5A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI5 1:DCI5 2:DCI5A 3:DCI5B 4:DCI5C 5:DCI5D 6:DCI5 7:DCI5A 8:DCI5B 9:DCI5C 10:DCI5/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI5 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI5 信息寄存器3 DCI5C中的重复次数指示 调制编码方案 DCI5/DCI5A/DCI5B/DCI5C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI5的循环移位指示 DCI5的CQI指示 DCI5/DCI5A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI5、DCI5A、DCI5B TDD、DCI5C TDD 新数据反转指示 DCI5D POWER OFFSET DAI域 功控参数 DCI5 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI5 信息寄存器5 DCI5 信息寄存器6 DCI5 信息寄存器7 DCI5 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI5 信息寄存器9 DCI5 信息寄存器10 DCI5 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI6输出寄存器1 DCI6输出寄存器2 DCI6功率寄存器 DCI功率 DCI6 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI6 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI6A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI6 1:DCI6 2:DCI6A 3:DCI6B 4:DCI6C 5:DCI6D 6:DCI6 7:DCI6A 8:DCI6B 9:DCI6C 10:DCI6/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI6 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI6 信息寄存器3 DCI6C中的重复次数指示 调制编码方案 DCI6/DCI6A/DCI6B/DCI6C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI6的循环移位指示 DCI6的CQI指示 DCI6/DCI6A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI6、DCI6A、DCI6B TDD、DCI6C TDD 新数据反转指示 DCI6D POWER OFFSET DAI域 功控参数 DCI6 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI6 信息寄存器5 DCI6 信息寄存器6 DCI6 信息寄存器7 DCI6 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI6 信息寄存器9 DCI6 信息寄存器10 DCI6 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI7输出寄存器1 DCI7输出寄存器2 DCI7功率寄存器 DCI功率 DCI7 LLR寄存器 DCI false alarm软信息为0的个数 DCI false alarm的输出重构差异个数 DCI7 信息寄存器1 天线选择： 0：天线0 1：天线1 DCI7A下： 0：非ORDER 1：ORDER SPS-C-RNTI指示： 0：授权 1：激活 2：释放 3：无效 DCI格式类型： 0:DCI7 1:DCI7 2:DCI7A 3:DCI7B 4:DCI7C 5:DCI7D 6:DCI7 7:DCI7A 8:DCI7B 9:DCI7C 10:DCI7/3A 检出DCI 所用的RNTI指示： 0：RNTI0：SI-RNTI； 1：RNTI1：P-RNTI； 2：RNTI2：RA-RNTI； 3：RNTI3：C-RNTI； 4：RNTI4：SPS-RNTI； 5：RNTI5：T-RNTI； 6：RNTI6：TPCS-RNTI； 7：RNTI7：TPCC-RNTI 8：RNTI8：G-RNTI 9：RNTI9：SC-RNTI 10：RNTI10：SC-N-RNTI 检出DCI是在COMM还是UE空间检出： 0：公共空间 1：UE空间 检出DCI数据的起始地址(index:0~23) 检出DCI所在的L等级指示： 000：L=1; 001：L=2; 010：L=4; 011：L=8; 100：L=12; 101：L=16; 110：L=24; 检出DCI 长度(max38) DCI7 信息寄存器2 选择使用上报的PMI，还是选择使用DCI下发的PMI： 0：选择使用DCI下发的PMI 1：选择使用上报的PMI HARQ进程:0~15 预编码指示：tx2:0~3，tx4:0~15 传输方案： 0：单天线 1：发射分集 2：空间复用 3：PORT7 4：PORT8 5：PORT5 资源分配类型： 0：集中式 1：分布式 Nscid的值(UE业务加扰用)：0~1 冗余版本：0~3 调制格式： 0:QPSK 1:16QAM 2:64QAM 传输块长度：max12216 DCI7 信息寄存器3 DCI7C中的重复次数指示 调制编码方案 DCI7/DCI7A/DCI7B/DCI7C：2码字激活标志： 0：1码字激活 1：2码字激活 DCI7的循环移位指示 DCI7的CQI指示 DCI7/DCI7A：TB到CW的映射是否交叉映射： 0：正常映射 1：交织映射 SRS请求： SRQ高层配置了的情况下：DCI7、DCI7A、DCI7B TDD、DCI7C TDD 新数据反转指示 DCI7D POWER OFFSET DAI域 功控参数 DCI7 信息寄存器4 填充域 资源分配类型： 0：TYPE0 1：TYPE1 Type0的跳频标志指示 Type0/Type1的资源块分配RBA DCI7 信息寄存器5 DCI7 信息寄存器6 DCI7 信息寄存器7 DCI7 信息寄存器8 前0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 DCI7 信息寄存器9 DCI7 信息寄存器10 DCI7 信息寄存器11 后0.5ms资源bitmap指示：对应bit表示不同的prb[99:96]，每个bit的意义如下： 0：某个prb不占用 1：某个prb占用 MIB0输出寄存器1 MIB0的值 MIB0INFO寄存器 MIB 子帧信息 MIB1输出寄存器1 MIB1的值 MIB1INFO寄存器 MIB 子帧信息 MIB2输出寄存器1 MIB2的值 MIB2INFO寄存器 MIB 子帧信息 MIB3输出寄存器1 MIB3的值 MIB3INFO寄存器 MIB 子帧信息 帧号配置寄存器 CATM模式下CELL RS功率计算是否包含OFDM0： 0：不包含OFDM0 1：包含OFDM0 FFT运算每级归一化模式选择： 0：顶满次高位归一化 1：顶满最高位归一化 0：FFT运算每级归一化不使能，FFT倒数第二级截位使能； 1：FFT运算每级归一化使能，FFT倒数第二级截位不使能； 0：DLFFT触发LDTC1或LDTC控制信号 1：DLFFT不触发LDTC1或LDTC控制信号 1：DLFFT输入搬数完成中断使能（到TXRX的中断，每个OFDM符号输入数据搬数完成后发出） 0：DLFFT输入搬数完成中断不使能 0:主卡选择 1:辅卡选择 系统帧号，取值范围0~1023 子帧帧号，取值范围0~9 CAT1模式RS控制寄存器 CELL RS功率最大值&AGC值输出选择： 000：选择第一套输出寄存器 001：选择第二套输出寄存器 010：选择第三套输出寄存器 011：选择第四套输出寄存器 100：选择第五套输出寄存器 其他：默认选择第一套 CAT1模式下CELL RS功率计算是否包含OFDM0： 0：不包含OFDM0 1：包含OFDM0 MBMS业务子帧类型选择： 2’b00：MBMS业务子帧中没有CELLRS信息的符号 2’b01：MBMS业务子帧中有1个CELLRS信息的符号 2’b10：MBMS业务子帧中有2个CELLRS信息的符号 2’b11：硬件会默认为00来进行处理 0：MBMS业务子帧不使能 1：MBMS业务子帧使能 CELLID序号指示 CP类型指示： 0：NORM CP 1：EX CP CELLRS PORT类型指示： 2’b00：port0 2’b01：port0/1 2’b10：port0/1/2/3 2’b11：保留，当CELLPORT_SEL配置为2’b11：硬件会默认为2’b00（prot0）来进行处理 UERS PORT类型指示： 0：port5 1：port7/8 0：CELLRS抽取不使能 1：CELLRS抽取使能 0：UERS抽取不使能 1：UERS抽取使能 CAT1模式CSIRS参数寄存器 若RS类型为CSIRS，则指示CSIRS BITMAP信息 指示CSIRS抽取时第二个CSIRS信息的OFDM符号 指示CSIRS抽取时第一个CSIRS信息的OFDM符号 CAT1模式AGC参数寄存器 MBMS业务子帧时非含CELLRS信息的OFDM符号的输入AGC值 非MBMS业务子帧时输入AGC值或MBMS业务子帧时含CELLRS信息的OFDM符号的输入AGC值 DLFFT控制参数寄存器 0：PBCH抽取不使能 1：PBCH抽取使能 0：CSIRS抽取不使能 1：CSIRS抽取使能 CAT1模式系统参数寄存器 系统带宽PRB索引值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 111：默认6prb 上下行配比，取值范围0~6 0：TDD MODE 1：FDD MODE 特殊子帧配置 ，取值范围 0~9 CAT1模式FFT倒数第二级饱和门限参数寄存器 FFT倒数第二级判饱和的门限个数值（和系统带宽有关），范围0~4096 CATM/NB模式系统参数配置寄存器 NBIOT时，指示NB所在的PRB位置，取值范围0~5 CP类型指示： 0：普通CP 1：扩展CP 上下行配比，取值范围0~6 0：TDD MODE 1：FDD MODE 特殊子帧配置 ，取值范围 0~9 CATM/NB模式RS抽取配置寄存器 CELL RS功率最大值&AGC值输出选择： 000：选择第一套输出寄存器 001：选择第二套输出寄存器 010：选择第三套输出寄存器 011：选择第四套输出寄存器 100：选择第五套输出寄存器 其他：默认选择第一套 0：NB模式时抽取NRS信号 1：NB模式时抽取CRS信号 表示CELLRS或NRS的ID序号值 CELLRS或NRS PORT类型指示： 2’b00：port0 2’b01：port0/1 2’b10：port0/1/2/3 2’b11：默认为2’b10处理 CATM/NB模式零频配置寄存器 窄带带宽是否包含零频点指示： 0：不包含零频点（包含零位置） 1：包含零频点（跳开零位置） CATM模式AGC参数寄存器 CATM模式输入AGC值 ABIS参数配置寄存器 0：传给LDTC1的LLR移位值为0 1：传给LDTC1的LLR移位值为历史值 CTCG起始位置选择： 0：从OFDM4(包括OFDM4)前有效CRS为样本 1：从OFDM8(包括OFDM8)前有效CRS为样本 检测到干扰邻区的个数： 00：0个干扰邻区 01：1个干扰邻区 10：2个干扰邻区 其他：默认0个干扰邻区 干扰邻区2发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区1发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区2 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区1 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区2 CELL ID值 干扰邻区1 CELL ID值 干扰邻区1相对本区时延值寄存器 干扰邻区1相对本区时延值（单位TS） 干扰邻区2相对本区时延值寄存器 干扰邻区2相对本区时延值（单位TS） CRS符号与非CRS符号功率比值寄存器 ABIS开始搜索干扰的起始OFDM符号数（取值范围0~13） CRS符号与非CRS符号功率比值 噪声功率值寄存器 噪声AGC值寄存器 输入噪声功率AGC值 模块工作模式选择寄存器 0：选择DLFFT_INFO_OUT1输出 1：选择DLFFT_INFO_OUT2输出 DLFFT INFO信息输入 0：帧与帧之间比较CRS_POW_MAX值大小并输出POW最大值和对应AGC值 1：帧与帧之间不比较CRS_POW_MAX值大小，只输出当前帧的POW最大值和对应AGC值 0：SOFT_IRT功能不使能 1：SOFT_IRT功能使能 00：CAT1模式 01：CATM模式 10：NB-IOT模式 11：默认CAT1模式 FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~18bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~19bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~20bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~21bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~22bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~23bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~24bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~25bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~26bit 帧号配置寄存器 ATM模式下CELL RS功率计算是否包含OFDM0： 0：不包含OFDM0 1：包含OFDM0 FFT运算每级归一化模式选择： 0：顶满次高位归一化 1：顶满最高位归一化 0：FFT运算每级归一化不使能，FFT倒数第二级截位使能； 1：FFT运算每级归一化使能，FFT倒数第二级截位不使能； 0：DLFFT触发LDTC1或LDTC控制信号 1：DLFFT不触发LDTC1或LDTC控制信号 1：DLFFT输入搬数完成中断使能（到TXRX的中断，每个OFDM符号输入数据搬数完成后发出） 0：DLFFT输入搬数完成中断不使能 0:主卡选择 1:辅卡选择 系统帧号，取值范围0~1023 子帧帧号，取值范围0~9 CAT1模式RS控制寄存器 CELL RS功率最大值&AGC值输出选择： 000：选择第一套输出寄存器 001：选择第二套输出寄存器 010：选择第三套输出寄存器 011：选择第四套输出寄存器 100：选择第五套输出寄存器 其他：默认选择第一套 CELL RS功率计算是否包含OFDM0： 0：不包含OFDM0 1：包含OFDM0 MBMS业务子帧类型选择： 2’b00：MBMS业务子帧中没有CELLRS信息的符号 2’b01：MBMS业务子帧中有1个CELLRS信息的符号 2’b10：MBMS业务子帧中有2个CELLRS信息的符号 2’b11：硬件会默认为00来进行处理 0：MBMS业务子帧不使能 1：MBMS业务子帧使能 CELLID序号指示 CP类型指示： 0：NORM CP 1：EX CP CELLRS PORT类型指示： 2’b00：port0 2’b01：port0/1 2’b10：port0/1/2/3 2’b11：保留，当CELLPORT_SEL配置为2’b11：硬件会默认为2’b00（prot0）来进行处理 UERS PORT类型指示： 0：port5 1：port7/8 0：CELLRS抽取不使能 1：CELLRS抽取使能 0：UERS抽取不使能 1：UERS抽取使能 CAT1模式CSIRS参数寄存器 若RS类型为CSIRS，则指示CSIRS BITMAP信息 指示CSIRS抽取时第二个CSIRS信息的OFDM符号 指示CSIRS抽取时第一个CSIRS信息的OFDM符号 CAT1模式AGC参数寄存器 MBMS业务子帧时非含CELLRS信息的OFDM符号的输入AGC值 非MBMS业务子帧时输入AGC值或MBMS业务子帧时含CELLRS信息的OFDM符号的输入AGC值 DLFFT控制参数寄存器 0：PBCH抽取不使能 1：PBCH抽取使能 0：CSIRS抽取不使能 1：CSIRS抽取使能 CAT1模式系统参数寄存器 系统带宽PRB索引值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 111：默认6prb 上下行配比，取值范围0~6 0：TDD MODE 1：FDD MODE 特殊子帧配置 ，取值范围 0~9 CAT1模式FFT倒数第二级饱和门限参数寄存器 FFT倒数第二级判饱和的门限个数值（和系统带宽有关），范围0~4096 CATM/NB模式系统参数配置寄存器 NBIOT时，指示NB所在的PRB位置，取值范围0~5 CP类型指示： 0：普通CP 1：扩展CP 上下行配比，取值范围0~6 0：TDD MODE 1：FDD MODE 特殊子帧配置 ，取值范围 0~9 CATM/NB模式RS抽取配置寄存器 CELL RS功率最大值&AGC值输出选择： 000：选择第一套输出寄存器 001：选择第二套输出寄存器 010：选择第三套输出寄存器 011：选择第四套输出寄存器 100：选择第五套输出寄存器 其他：默认选择第一套 0：NB模式时抽取NRS信号 1：NB模式时抽取CRS信号 表示CELLRS或NRS的ID序号值 CELLRS或NRS PORT类型指示： 2’b00：port0 2’b01：port0/1 2’b10：port0/1/2/3 2’b11：默认为2’b10处理 CATM/NB模式零频配置寄存器 窄带带宽是否包含零频点指示： 0：不包含零频点（包含零位置） 1：包含零频点（跳开零位置） CATM模式AGC参数寄存器 CATM模式输入AGC值 ABIS参数配置寄存器 0：传给LDTC1的LLR移位值为0 1：传给LDTC1的LLR移位值为历史值 CTCG起始位置选择： 0：从OFDM4(包括OFDM4)前有效CRS为样本 1：从OFDM8(包括OFDM8)前有效CRS为样本 检测到干扰邻区的个数： 00：0个干扰邻区 01：1个干扰邻区 10：2个干扰邻区 其他：默认0个干扰邻区 干扰邻区2发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区1发射天线数： 00：1port 01：2port 10：4port 其他：默认1port 干扰邻区2 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区1 系统带宽值： 000：6prb 001：15prb 010：25prb 011：50prb 100：75prb 101：100prb 其他：默认6prb 干扰邻区2 CELL ID值 干扰邻区1 CELL ID值 干扰邻区1相对本区时延值寄存器 干扰邻区1相对本区时延值（单位TS） 干扰邻区2相对本区时延值寄存器 干扰邻区2相对本区时延值（单位TS） CRS符号与非CRS符号功率比值寄存器 ABIS LLR修正值（取值范围-8~8） ABIS开始搜索干扰的起始OFDM符号数（取值范围0~13） CRS符号与非CRS符号功率比值 噪声功率值寄存器 噪声AGC值寄存器 噪声AGC值 模块工作模式选择寄存器 0：选择DLFFT_INFO_OUT1输出 1：选择DLFFT_INFO_OUT2输出 DLFFT INFO信息输入 0：帧与帧之间比较CRS_POW_MAX值大小并输出POW最大值和对应AGC值 1：帧与帧之间不比较CRS_POW_MAX值大小，只输出当前帧的POW最大值和对应AGC值 0：SOFT_IRT功能不使能 1：SOFT_IRT功能使能 00：CAT1模式 01：CATM模式 10：NB-IOT模式 11：默认CAT1模式 FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~18bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~19bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~20bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~21bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~22bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~23bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~24bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~25bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~26bit DLFFT中断使能控制寄存器 1：备用错误中断3使能 0：备用错误中断3不使能 1：备用错误中断2使能 0：备用错误中断2不使能 1：IDDET Online&Offline冲突错误中断使能 0：IDDET Online&Offline冲突错误中断不使能 1：RXCAPT错误中断使能 0：RXCAPT错误中断不使能 1：RF无数据中断使能 0：RF无数据中断不使能 1：检测上行RF驱动配置异常中断使能 0：检测上行RF驱动配置异常中断不使能 1：检测下行RF驱动配置异常中断使能 0：检测下行RF驱动配置异常中断不使能 1：检测RF少收数据中断使能 0：检测RF少收数据中断不使能 1：检测RF多收数据中断使能 0：检测RF多收数据中断不使能 1：AXIDMA中断使能（送给 AXIDMA，DLFFT的最后一个 OFDM完成后发出） 0：AXIDMA中断不使能 1：DLFFT访问TXRX or LDTC or LDTC1存储器ERROR中断使能 0：DLFFT访问TXRX or LDTCor LDTC1存储器ERROR中断不使能 1：DLFFT中断使能（到核的中断，最后一个OFDM完成后发出） 0：DLFFT中断不使能 1：DLFFT输入搬数完成中断使能（到TXRX的中断，每个OFDM符号输入数据搬数完成后发出） 0：DLFFT输入搬数完成中断不使能 CATM/NB模式FFT倒数第二级饱和门限参数寄存器 FFT倒数第二级判饱和的门限个数值，范围0~4096 模块启动寄存器 0: CATM/NB模式本模块不启动 1: CATM/NB模式本模块启动 0: CAT1模式本模块不启动 1: CAT1模式本模块启动 中断标志寄存器 1：备用错误中断3标志置位 0：备用错误中断3标志未置位 1：备用错误中断2标志置位 0：备用错误中断2标志未置位 1：IDDET Online&Offline冲突错误中断标志置位 0：IDDET Online&Offline冲突错误中断标志未置位 1：RXCAPT错误中断标志置位 0：RXCAPT错误中断标志未置位 1：MEASPWR错误中断标志置位 0： MEASPWR错误中断标志未置位 1：RF无数据中断标志置位 0：RF无数据中断标志未置位 1：SD访问DLFFT存储器错误中断标志置位 0：SD访问DLFFT存储器错误中断标志未置位 1：COEFF访问LDTC中断标志置位 0：COEFF访问LDTC中断标志未置位 1：COEFF访问LDTC1中断标志置位 0：COEFF访问LDTC1中断标志未置位 1：上行RF驱动配置异常中断标志置位 0：上行RF驱动配置异常中断标志未置位 1：下行RF驱动配置异常中断标志置位 0：下行RF驱动配置异常中断标志未置位 1：RF少收数据中断标志置位 0：RF少收数据中断标志未置位 1：RF多收数据中断标志置位 0：RF多收数据中断标志未置位 1：AXIDMA中断标志置位（送给AXIDMA，DLFFT的最后一个OFDM完成后发出） 0：AXIDMA中断未置位 1：写CSI存储器时钟开启失败标志置位 0：写CSI存储器时钟开启失败标志未置位 1：写MMSE存储器时钟开启失败标志置位 0：写MMSE存储器时钟开启失败标志未置位 1：写LDTC存储器时钟开启失败标志置位 0：写LDTC存储器时钟开启失败标志未置位 1：读TXRX存储器时钟开启失败标志置位 0：读TXRX存储器时钟开启失败标志未置位 1：DLFFT中断标志置位（到核的中断标志，最后一个OFDM完成后进行置位） 0：DLFFT中断标志未置位 1：DLFFT输入搬数完成中断标志置位（到TXRX的中断标志，每个OFDM 符号输入数据搬数完成后进行置位） 0：DLFFT输入搬数完成中断标志未置位 OFDM符号计数寄存器 指示当前的OFDM符号数，范围0~13 主辅卡输出寄存器 DLFFT INFO信息输出 2 DLFFT INFO信息输出 1 0：主卡完成 1：辅卡完成 ABIS干扰类型1移位值输出寄存器 ABIS干扰类型1（邻区1）移位值 ABIS干扰类型2移位值输出寄存器 ABIS干扰类型2（邻区2）移位值 ABIS干扰类型3移位值输出寄存器 ABIS干扰类型3（邻区1+2）移位值 CELLRS功率最大值输出寄存器 CELLRS功率最大值AGC输出寄存器 CELLRS功率最大值AGC输出值 CELLRS功率最大值输出寄存器 CELLRS功率最大值AGC输出寄存器 CELLRS功率最大值AGC输出值 CELLRS功率最大值输出寄存器 CELLRS功率最大值AGC输出寄存器 CELLRS功率最大值AGC输出值 CELLRS功率最大值输出寄存器 CELLRS功率最大值AGC输出寄存器 CELLRS功率最大值AGC输出值 CELLRS功率最大值输出寄存器 CELLRS功率最大值AGC输出寄存器 CELLRS功率最大值AGC输出值 模块状态机输出寄存器 TXRX模块归一化因子输出寄存器1 OFDM 7的TXRX模块归一化因子输出 OFDM 6的TXRX模块归一化因子输出 OFDM 5的TXRX模块归一化因子输出 OFDM 4的TXRX模块归一化因子输出 OFDM 3的TXRX模块归一化因子输出 OFDM 2的TXRX模块归一化因子输出 OFDM 1的TXRX模块归一化因子输出 OFDM 0的TXRX模块归一化因子输出 TXRX模块归一化因子输出寄存器1 OFDM 13的TXRX模块归一化因子输出 OFDM 12的TXRX模块归一化因子输出 OFDM 11的TXRX模块归一化因子输出 OFDM 10的TXRX模块归一化因子输出 OFDM 9的TXRX模块归一化因子输出 OFDM 8的TXRX模块归一化因子输出 TXRX模块SOFT IRT因子输出寄存器 TXRX模块SOFT IRT因子1输出 TXRX模块SOFT IRT因子0输出 OFDM符号计数寄存器 ASSERT发生时采到的TXRX_ENABLE信号值 ASSERT发生时当前的OFDM符号数，范围0~13 状态机输出寄存器 ABIS实时计算标志寄存器 0：ABIS当前帧无法完成LLR_OUT3实时计算 1：ABIS当前帧完成LLR_OUT3实时计算 0：ABIS当前帧无法完成LLR_OUT2实时计算 1：ABIS当前帧完成LLR_OUT2实时计算 0：ABIS当前帧无法完成LLR_OUT1实时计算 1：ABIS当前帧完成LLR_OUT1实时计算 启动寄存器 Coeff输出至meas使能 1：使能 0：不使能 Coeff输出至ldtc\ldtc1使能 1：使能 0：不使能 Coeff输出至ldtc\ldtc1 buf选择位 00：输出ldtc buf1 01：输出ldtc buf2 10：输出ldtc buf3 11：无效值 CAT1和CATM模式选择 0：CATM模 1：CAT1模 快速输出模式 0：不使能 1：使能 Port选择位 0：选择Port78 1：选择Port5 中断使能信号： 0：QFQT中断不使能 1：QFQT中断使能 模式选择： 0: NCP 1: ECP 模块使能信号： 0: QFQT模块不使能 1: QFQT模块使能 中断状态寄存器 读写buf冲突的来源 00：来自ldtc buf1 01：来自ldtc buf2 10：来自ldtc buf3 11：来自meas buf 冲突标志 中断状态 0: 未完成系数矩阵求逆 1: 完成系数矩阵求逆 QF参数配置寄存器(在配置QT_CONF之前进行配置) 系统带宽选择 000: 6PRB 001: 15PRB 010: 25PRB 011: 50PRB 100: 75PRB 101: 100PRB Others: RESERVED 6PRB 信噪比 信道类型 00: EPA 01: EVA 10: ETU 11: RESERVED EPA QT参数配置寄存器(在配置QF_CONF之后进行配置) 多普勒值 00：5 01：70 10：300 11: 850 TDD、FDD模式选择 0：TDD 1：FDD 信噪比 特殊子帧指示 0000：SS0 0001：SS1 0010：SS2 0011：SS3 0100：SS4 0101：SS5 0110：SS6 0111：SS7 1000：SS8 1001：SS9 软件输入寄存器 软件输入寄存器 软件输出寄存器 软件输出寄存器 模块使能寄存器 上行定时电路使能 1：使能 0：不使能 下行定时电路使能 1：使能 0：不使能 RAM地址映射寄存器 上行RAM3（指令RAM）的偏移地址 （RAM3起始地址为256+偏移地址） 上行RAM2（SPI RAM）的起始地址 下行RAM3（指令RAM）的偏移地址 （RAM3起始地址为256+偏移地址） 下行RAM2（SPI RAM）的起始地址 GPO立即起效寄存器 上下行使能控制选择 1：本次操作为上行控制 0：本次操作为下行控制 SPI选择控制 1：本次发送数据为SPI 0：本次发送数据为GPO SPI读写控制 1：本次SPI操作为读操作 0：本次SPI操作为写操作 控制射频芯片的直接线 直接发送的RFSPI数据寄存器 SPI 控制寄存器 两次相邻SPI操作，SEN无效需要保证的最小时间（SCLK时钟个数的一半） SPI读时钟产生分频系数控制： 000：4 001：6（default） 010：8 011：10 100：12 101：14 110：16 111：18 SPI写时钟产生分频系数控制： 000：4 001：6（default） 010：8 011：10 100：12 101：14 110：16 111：18 半双工读数据时片选信号反相使能（包括4-W，3-W制的半双工读） 0：不反相 1：反相 双工模式选择（此位仅在 17bit选为4线制时有效） 0：半双工 1：全双工 SPI接收数据时模式选择位： 0：3线模式（只支持半双工读）； 1：4线模式； SPI半双工读数据时选择间隔第几个SPI采样时钟的数据有效 00:0个时钟 01:1个时钟 10:2个时钟 11:3个时钟 读数据采样沿 0：相反沿采数据，与发送沿为相反沿（全双工时必须为0） 1：同沿采数据，与发送沿为同一个沿 片选使能控制选择 0：片选在时钟之前有效（Normal SPI） 1：片选在时钟之后有效（DigRF SPI） SPI时钟相位控制： 0: 数据采样发生在时钟的奇数沿； （外部芯片在奇数沿采数，1开始记数）; 1: 数据采样发生在时钟的偶数沿； （外部芯片在偶数沿采数）; SPI时钟极性控制： 0: SPI接口在IDLE状态时，时钟为低电平； 1: SPI接口在IDLE状态时，时钟为高电平； SPI片选极性控制： 0: SPI片选低有效； 1: SPI片选高有效 SPI接收数据长度（只包括数据位）： 00000: 1-bits 00001: 2-bits …........... 11111: 32-bits SPI发送数据长度：（包括读写比特、地址位和数据位）： 00000: 1-bits 00001: 2-bits …........... 11111: 32-bits SPI 接收数据寄存器 DEBUG寄存器 上行定时错误标识 1：有错误 0：无错误 上行禁止插队错误标识 1：有错误 0：无错误 0：RAM地址超界错误未发生 1：RAM地址超界错误已发生 0：定时时间超限错误未发生 1：定时时间超限错误已发生 （子帧号不是0xf且大于0xA） 上行RAM读地址 下行定时错误标识 1：有错误 0：无错误 下行禁止插队错误标识 1：有错误 0：无错误 0：RAM地址超界错误未发生 1：RAM地址超界错误已发生 0：定时时间超限错误未发生 1：定时时间超限错误已发生 （子帧号不是0xf且大于0xA） 下行RAM读地址 RF GPO control register RFAD帧长控制寄存器 禁止插队机制使能 1：使能 0：不使能 上行帧长使能 下行帧长使能 RFAD帧长值 上行定时错误时FRAMC值寄存器 上行定时错误标识 1：有错误 0：无错误 上行定时错误时FRAMC值 上行定时错误时定时时间寄存器 上行定时错误时定时事件地址 上行定时错误时定时时间值 下行定时错误时FRAMC值寄存器 下行定时错误标识 1：有错误 0：无错误 下行定时错误时FRAMC值 下行定时错误时定时时间寄存器 下行定时错误时定时事件地址 下行定时错误时定时时间值 定时错误时FRAML值状态寄存器 上行定时错误时FRAML值 下行定时错误时FRAML值 上行禁止插队错误状态寄存器 上行插队错误时定时事件地址 上行插队错误时FRAMC值 下行禁止插队错误状态寄存器 下行插队错误时定时事件地址 下行插队错误时FRAMC值 下行存储器 上行存储器 DFT/IDFT控制寄存器 0：ANTI_DROP功能不使能 1：ANTI_DROP功能使能 ANTI_DROP功能截位因子: 0：右移8bit 1：右移7bit DFT/IDFT点数选择的index，0~43分别指示44种点数，index与实际点数的对应关系如下表说明 （不可配置其他值） 00: BPSK调制方式 01: QPSK调制方式 10: 16QAM调制方式 11: 64QAM调制方式 0：DFT/IDFT功能不使能 1：DFT/IDFT功能使能 0：PUSCH调制功能不使能 1：PUSCH调制功能使能 0: 选择DFT运算 1: 选择IDFT运算 PUCCH调制输入数据寄存器 PUCCH调制输入数据d(n) SRS资源映射参数配置寄存器 SRS填零间隔指示： 0：每2个子载波填1个零； 1：每4个子载波填3个零； 起始子载波位置（梳齿位置），取值范围： 00：0； 01：1； 10：2； 11：3； SRS频域映射长度值 第二个SRS符号频域映射起始位置 第一个SRS符号频域映射起始位置 SRS的ZC序列长度寄存器 0：发送特殊子帧时，SRS符号个数为1个 1：发送特殊子帧时，SRS符号个数为2个 第二个SRS发送的OFDM符号位置 第一个SRS发送的OFDM符号位置 只发SRS（特殊子帧）时，子帧起始发送的OFDM符号位置 SRS的ZC序列长度值 PUCCH资源映射参数寄存器 0：TX滤波不使能 1：TX滤波使能 窄带在系统带宽内的起始位置2 窄带在系统带宽内的起始位置1 第二个时隙PUCCH映射起始位置 第一个时隙PUCCH映射起始位置 PUSCH资源映射参数寄存器 PUSCH映射分配类型： 0：资源映射0.5ms； 1：资源映射1ms； 第二段PUSCH频域映射长度值 第一段PUSCH频域映射长度值 第二段PUSCH频域映射起始位置 第一段PUSCH频域映射起始位置 硬化计算参数配置寄存器1 PUSCH DMRS正交码索引取反标志位： 1：取反 0：不取反 PUSCH/PUCCH符号打孔处理指示： 0000：normal 0001：type0_shortend 0010：type1_shortend 0011：type2_shortend 0100：type3_shortend 0101：type4_shortend 0110：type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1：u值跳变 0：u值不跳变 1：v值跳变 0：v值不跳变 连续两个发送帧覆盖TA部分索引值，取值范围0~32 dmrsValue参考信号解调的循环偏移值，取值范围0~7 硬化计算参数配置寄存器2 SRS的小数APC（ ）调整因子 PUSCH/PUCCH/PRACH的小数APC（ ）调整因子 硬化计算参数配置寄存器3 PUCCH格式1/1a/1b的资源索引值，取值范围0~4095 SRS循环移位值 对CAT1/CATM/CAT-NB子载波15kHz，每次调用对应1ms内2个时隙，该参数表示子帧号；对CAT-NB子载波3.75kHz，每次调用对应2ms内1个时隙，该参数表示时隙号 无线帧号，取值范围0~1023 OFDM OFFSET配置寄存器 最后一个OFDM符号的offset值 第一个OFDM符号的offset值 中断使能寄存器 0：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：AXIDMA中断使能 0：AXIDMA中断未使能 1：OFDM符号13中断使能 0：OFDM符号13中断未使能 1：OFDM符号12中断使能 0：OFDM符号12中断未使能 1：OFDM符号11中断使能 0：OFDM符号11中断未使能 1：OFDM符号10中断使能 0：OFDM符号10中断未使能 1：OFDM符号9中断使能 0：OFDM符号9中断未使能 1：OFDM符号8中断使能 0：OFDM符号8中断未使能 1：OFDM符号7中断使能 0：OFDM符号7中断未使能 1：OFDM符号6中断使能 0：OFDM符号6中断未使能 1：OFDM符号5中断使能 0：OFDM符号5中断未使能 1：OFDM符号4中断使能 0：OFDM符号4中断未使能 1：OFDM符号3中断使能 0：OFDM符号3中断未使能 1：OFDM符号2中断使能 0：OFDM符号2中断未使能 1：OFDM符号1中断使能 0：OFDM符号1中断未使能 1：OFDM符号0中断使能 0：OFDM符号0中断未使能 中断标志寄存器 1：OFDM符号13中断标志置位 0：OFDM符号13中断标志未置位 1：OFDM符号12中断标志置位 0：OFDM符号12中断标志未置位 1：OFDM符号11中断标志置位 0：OFDM符号11中断标志未置位 1：OFDM符号10中断标志置位 0：OFDM符号10中断标志未置位 1：OFDM符号9中断标志置位 0：OFDM符号9中断标志未置位 1：OFDM符号8中断标志置位 0：OFDM符号8中断标志未置位 1：OFDM符号7中断标志置位 0：OFDM符号7中断标志未置位 1：OFDM符号6中断标志置位 0：OFDM符号6中断标志未置位 1：OFDM符号5中断标志置位 0：OFDM符号5中断标志未置位 1：OFDM符号4中断标志置位 0：OFDM符号4中断标志未置位 1：OFDM符号3中断标志置位 0：OFDM符号3中断标志未置位 1：OFDM符号2中断标志置位 0：OFDM符号2中断标志未置位 1：OFDM符号1中断标志置位 0：OFDM符号1中断标志未置位 1：OFDM符号0中断标志置位 0：OFDM符号0中断标志未置位 1：读pusch存储器时钟开启失败标志置位 0：读pusch存储器时钟开启失败标志未置位 1：写txrx存储器时钟开启失败标志置位 0：写txrx存储器时钟开启失败标志未置位 OFDM符号填零发送寄存器 指示填零发送的OFDM符号数： 14’b0：没有填零发送 14’b1：符号0填零发送 14’b11：符号0，1填零发送 14’b111：符号0，1，2填零发送 …… DFT/IDFT&FFT/IFFT控制寄存器 0：软件未触发ULDFT启动 1：软件触发ULDFT启动 0：ULDFT启动模式为软件触发 1：ULDFT启动模式为PUSCH模块触发 0：启窗不使能 1：启窗使能 0：SRS产生不使能 1：SRS产生使能 0：FFT输入MEM清零功能不使能 1：FFT输入MEM清零功能使能 1：选择IFFT运算 0：选择FFT运算 1：FFT/IFFT运算使能 0：FFT/IFFT运算不使能 0：功率调整不使能 1：功率调整使能 指示PRACH格式类型： 000：PRACH格式0 001：PRACH格式1 010：PRACH格式2 011：PRACH格式3 100：PRACH格式4 其他：保留 指示PUCCH格式类型： 000：PUCCH格式1 001：PUCCH格式1a 010：PUCCH格式1b 011：PUCCH格式2 100：PUCCH格式2a 101：PUCCH格式2b 其他：保留 0：NPUSCH format 1 1：NPUSCH format2 指示OFDM符号的个数 0：DATADRIVE不使能 1：DATADRIVE使能 指示UL_DFT读PUSCH BUFFER块选择： 00：PUSCH BUFFER1 01：PUSCH BUFFER2 10：PUSCH BUFFER3 11：PUSCH PRA_BUF 指示上行信道发送模式 000：PUSCH 001：PUCCH 010：PRACH 011：SRS 100：NPUSCH 101：NPRACH 其他：保留 FFT/IFFT点数选择 111：保留（不可配） 110：保留（不可配） 101：保留（不可配） 100：2048点 011：1024点 010：512点 001：256点 000：128点 0: 中断不使能 1: 中断使能 SRS的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit PUSCH/PUCCH/PRACH的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit NPUSCH参数寄存器 NPUSCH当前重复传输的第几次，取值范围0~127 子载波个数： 00：1个子载波 01：3个子载波 10：6个子载波 11：12个子载波 NPUSCH 的起始子载波位置，取值范围0~47 当前传输的第几个Nslots单位，取值范围1~160 0: 3.75KHz 1: 15KHz NPUSCH DMRS参数寄存器 首个RU的首个时隙号，取值范围0~19 用于子载波个数为1生成DMRS时，表示第几个时隙，取值范围0~20480 BASE_SEQ_NEXT值，取值范围0~30 CYCLIC_SHIFT值，取值范围0~3 NPRACH参数寄存器 t值，取值范围0~128 frequency location of the first sub-carrier allocated to NPRACH： 000：frequency location为0； 001：frequency location为2； 010：frequency location为12 011：frequency location为18 100：frequency location为24 101：frequency location为34 110：frequency location为36 111：默认为0 being the subcarrier selected by the MAC layer from ，取值范围0-47 FFT/IFFT输入输出数据控制及参数寄存器 采样滤波器输出截取选择 计算组跳频参数，取值范围0~29 PUCCH格式2/2a/2b的资源索引值，取值范围0~1184 参考信号的循环偏移参数值，取值范围0~7 指示CP类型： 0：普通CP 1：扩展CP 0：TDD mode 1：FDD mode 1: 使能按地址位反序输入数据，按拼接好的顺序输出数据 0: 正常输入输出数据 ID配置寄存器 NCS和U所需的GOLD序列时初始值C_INI的计算模式选择： 1：if no value for or is configured by higher layers or the PUSCH transmission corresponds to a Random Access Response Grant or a retransmission of the same transport block as part of the contention based random access procedure 0：otherwise NCS_U_GOLD_MODE为1时，表示 + 的值，取值范围0~532；NCS_U_GOLD_MODE为0时，表示高层所配 的值，取值范围0~509； NCS_U_GOLD_MODE为1时，表示 + 的值，取值范围0~532；NCS_U_GOLD_MODE为0时，表示高层所配 的值，取值范围0~509； 小区ID值，取值范围0~503 PUCCH虚拟ID寄存器 RS使用的虚拟ID PUCCH资源映射配置寄存器 nCsAn混合资源块内格式1/1a/1b使用循环移位数，取值范围0~7 CE_mode指示： 0：CE_modeA 1：CE_modeB 索引值： 00： 为1 01： 为2 10： 为3 11：取00值， 为1 cqiNrb PUCCH格式2/2a/2b占用资源块数，取值范围0~98 系统带宽配置寄存器 CAT1模式下 上行系统带宽索引值： 000：系统带宽为6PRB 001：系统带宽为15PRB 010：系统带宽为25PRB 011：系统带宽为50PRB 100：系统带宽为75PRB 101：系统带宽为100PRB 其他：默认系统带宽为6PRB 参数传递寄存器 0：DMA控制本模块启动不使能 1：DMA控制本模块启动使能 0: 软件参数配置未结束 1: 软件参数配置结束 软件暂停和停止硬件配置寄存器 SW_PAUSE_EN=1时，软件暂停硬件的OFDM符号序号： 14`b0：不暂停 14`b1：OFDM符号0暂停 14`b11：OFDM符号0、1暂停 14`b111：OFDM符号0、1、2暂停 …… SW_PAUSE_EN=1时，软件暂停硬件的策略选择： 0：SW_PAUSE_OFDM设置的OFDM符号的之前暂停 1：SW_PAUSE_OFDM设置的OFDM符号的之后暂停 软件暂停硬件使能信号： 0：软件暂停硬件不使能 1：软件暂停硬件使能 软件立即暂停使能信号： 0：软件立即暂停硬件不使能 1：软件立即暂停硬件使能 软件停止硬件使能信号： 0：软件停止硬件不使能 1：软件停止硬件使能，硬件完成当前OFDM处理后，停止当前子帧的操作 软件暂停标志寄存器 软件暂停硬件标志信号： 0：软件未成功暂停硬件 1：软件成功暂停硬件 软件停止硬件标志信号： 0：软件未成功停止硬件 1：软件成功停止硬件 DFT/IDFT控制寄存器 0：ANTI_DROP功能不使能 1：ANTI_DROP功能使能 ANTI_DROP功能截位因子: 0：右移8bit 1：右移7bit DFT/IDFT点数选择的index，0~43分别指示44种点数，index与实际点数的对应关系如下表说明 （不可配置其他值） 00: BPSK调制方式 01: QPSK调制方式 10: 16QAM调制方式 11: 64QAM调制方式 0：DFT/IDFT功能不使能 1：DFT/IDFT功能使能 0：PUSCH调制功能不使能 1：PUSCH调制功能使能 0: 选择DFT运算 1: 选择IDFT运算 PUCCH调制输入数据寄存器 PUCCH调制输入数据d(n) SRS资源映射参数配置寄存器 SRS填零间隔指示： 0：每2个子载波填1个零； 1：每4个子载波填3个零； 起始子载波位置（梳齿位置），取值范围： 00：0； 01：1； 10：2； 11：3； SRS频域映射长度值 第二个SRS符号频域映射起始位置 第一个SRS符号频域映射起始位置 SRS的ZC序列长度寄存器 0：发送特殊子帧时，SRS符号个数为1个 1：发送特殊子帧时，SRS符号个数为2个 第二个SRS发送的OFDM符号位置 第一个SRS发送的OFDM符号位置 只发SRS（特殊子帧）时，子帧起始发送的OFDM符号位置 SRS的ZC序列长度值 PUCCH资源映射参数寄存器 0：TX滤波不使能 1：TX滤波使能 窄带在系统带宽内的起始位置2 窄带在系统带宽内的起始位置1 第二个时隙PUCCH映射起始位置 第一个时隙PUCCH映射起始位置 PUSCH资源映射参数寄存器 PUSCH映射分配类型： 0：资源映射0.5ms； 1：资源映射1ms； 第二段PUSCH频域映射长度值 第一段PUSCH频域映射长度值 第二段PUSCH频域映射起始位置 第一段PUSCH频域映射起始位置 硬化计算参数配置寄存器1 PUSCH/PUCCH符号打孔处理指示： 0000：normal 0001：type0_shortend 0010：type1_shortend 0011：type2_shortend 0100：type3_shortend 0101：type4_shortend 0110：type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1：u值跳变 0：u值不跳变 1：v值跳变 0：v值不跳变 连续两个发送帧覆盖TA部分索引值，取值范围0~32 dmrsValue参考信号解调的循环偏移值，取值范围0~7 硬化计算参数配置寄存器2 SRS的小数APC（ ）调整因子 PUSCH/PUCCH/PRACH的小数APC（ ）调整因子 硬化计算参数配置寄存器3 PUCCH格式1/1a/1b的资源索引值，取值范围0~4095 SRS循环移位值 对CAT1/CATM/CAT-NB子载波15kHz，每次调用对应1ms内2个时隙，该参数表示子帧号；对CAT-NB子载波3.75kHz，每次调用对应2ms内1个时隙，该参数表示时隙号 无线帧号，取值范围0~1023 OFDM OFFSET配置寄存器 最后一个OFDM符号的offset值 第一个OFDM符号的offset值 中断使能寄存器 0：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：AXIDMA中断使能 0：AXIDMA中断未使能 1：OFDM符号13中断使能 0：OFDM符号13中断未使能 1：OFDM符号12中断使能 0：OFDM符号12中断未使能 1：OFDM符号11中断使能 0：OFDM符号11中断未使能 1：OFDM符号10中断使能 0：OFDM符号10中断未使能 1：OFDM符号9中断使能 0：OFDM符号9中断未使能 1：OFDM符号8中断使能 0：OFDM符号8中断未使能 1：OFDM符号7中断使能 0：OFDM符号7中断未使能 1：OFDM符号6中断使能 0：OFDM符号6中断未使能 1：OFDM符号5中断使能 0：OFDM符号5中断未使能 1：OFDM符号4中断使能 0：OFDM符号4中断未使能 1：OFDM符号3中断使能 0：OFDM符号3中断未使能 1：OFDM符号2中断使能 0：OFDM符号2中断未使能 1：OFDM符号1中断使能 0：OFDM符号1中断未使能 1：OFDM符号0中断使能 0：OFDM符号0中断未使能 OFDM符号填零发送寄存器 指示填零发送的OFDM符号数： 14’b0：没有填零发送 14’b1：符号0填零发送 14’b11：符号0，1填零发送 14’b111：符号0，1，2填零发送 …… DFT/IDFT&FFT/IFFT控制寄存器 0：软件未触发ULDFT启动 1：软件触发ULDFT启动 0：ULDFT启动模式为软件触发 1：ULDFT启动模式为PUSCH模块触发 0：启窗不使能 1：启窗使能 0：SRS产生不使能 1：SRS产生使能 0：FFT输入MEM清零功能不使能 1：FFT输入MEM清零功能使能 1：选择IFFT运算 0：选择FFT运算 1：FFT/IFFT运算使能 0：FFT/IFFT运算不使能 0：功率调整不使能 1：功率调整使能 指示PRACH格式类型： 000：PRACH格式0 001：PRACH格式1 010：PRACH格式2 011：PRACH格式3 100：PRACH格式4 其他：保留 指示PUCCH格式类型： 000：PUCCH格式1 001：PUCCH格式1a 010：PUCCH格式1b 011：PUCCH格式2 100：PUCCH格式2a 101：PUCCH格式2b 其他：保留 0：NPUSCH format 1 1：NPUSCH format2 指示OFDM符号的个数 0：DATADRIVE不使能 1：DATADRIVE使能 指示UL_DFT读PUSCH BUFFER块选择： 00：PUSCH BUFFER1 01：PUSCH BUFFER2 10：PUSCH BUFFER3 11：PUSCH PRA_BUF 指示上行信道发送模式 000：PUSCH 001：PUCCH 010：PRACH 011：SRS 100：NPUSCH 101：NPRACH 其他：保留 FFT/IFFT点数选择 111：保留（不可配） 110：保留（不可配） 101：保留（不可配） 100：2048点 011：1024点 010：512点 001：256点 000：128点 0: 中断不使能 1: 中断使能 SRS的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit PUSCH/PUCCH/PRACH的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit NPUSCH参数寄存器 NPUSCH当前重复传输的第几次，取值范围0~127 子载波个数： 00：1个子载波 01：3个子载波 10：6个子载波 11：12个子载波 NPUSCH 的起始子载波位置，取值范围0~47 当前传输的第几个Nslots单位，取值范围1~160 0: 3.75KHz 1: 15KHz NPUSCH DMRS参数寄存器 首个RU的首个时隙号，取值范围0~19 用于子载波个数为1生成DMRS时，表示第几个时隙，取值范围0~20480 BASE_SEQ_CURR值，取值范围0~30 CYCLIC_SHIFT值，取值范围0~3 NPRACH参数寄存器 t值，取值范围0~128 frequency location of the first sub-carrier allocated to NPRACH： 000：frequency location为0； 001：frequency location为2； 010：frequency location为12 011：frequency location为18 100：frequency location为24 101：frequency location为34 110：frequency location为36 111：默认为0 being the subcarrier selected by the MAC layer from ，取值范围0-47 DFT/IDFT控制寄存器 0：ANTI_DROP功能不使能 1：ANTI_DROP功能使能 ANTI_DROP功能截位因子: 0：右移8bit 1：右移7bit DFT/IDFT点数选择的index，0~43分别指示44种点数，index与实际点数的对应关系如下表说明 （不可配置其他值） 00: BPSK调制方式 01: QPSK调制方式 10: 16QAM调制方式 11: 64QAM调制方式 0：DFT/IDFT功能不使能 1：DFT/IDFT功能使能 0：PUSCH调制功能不使能 1：PUSCH调制功能使能 0: 选择DFT运算 1: 选择IDFT运算 PUCCH调制输入数据寄存器 PUCCH调制输入数据d(n) SRS资源映射参数配置寄存器 SRS填零间隔指示： 0：每2个子载波填1个零； 1：每4个子载波填3个零； 起始子载波位置（梳齿位置），取值范围： 00：0； 01：1； 10：2； 11：3； SRS频域映射长度值 第二个SRS符号频域映射起始位置 第一个SRS符号频域映射起始位置 SRS的ZC序列长度寄存器 0：发送特殊子帧时，SRS符号个数为1个 1：发送特殊子帧时，SRS符号个数为2个 第二个SRS发送的OFDM符号位置 第一个SRS发送的OFDM符号位置 只发SRS（特殊子帧）时，子帧起始发送的OFDM符号位置 SRS的ZC序列长度值 PUCCH资源映射参数寄存器 0：TX滤波不使能 1：TX滤波使能 窄带在系统带宽内的起始位置2 窄带在系统带宽内的起始位置1 第二个时隙PUCCH映射起始位置 第一个时隙PUCCH映射起始位置 PUSCH资源映射参数寄存器 PUSCH映射分配类型： 0：资源映射0.5ms； 1：资源映射1ms； 第二段PUSCH频域映射长度值 第一段PUSCH频域映射长度值 第二段PUSCH频域映射起始位置 第一段PUSCH频域映射起始位置 硬化计算参数配置寄存器1 PUSCH/PUCCH符号打孔处理指示： 0000：normal 0001：type0_shortend 0010：type1_shortend 0011：type2_shortend 0100：type3_shortend 0101：type4_shortend 0110：type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1：u值跳变 0：u值不跳变 1：v值跳变 0：v值不跳变 连续两个发送帧覆盖TA部分索引值，取值范围0~32 dmrsValue参考信号解调的循环偏移值，取值范围0~7 硬化计算参数配置寄存器2 SRS的小数APC（ ）调整因子 PUSCH/PUCCH/PRACH的小数APC（ ）调整因子 硬化计算参数配置寄存器3 PUCCH格式1/1a/1b的资源索引值，取值范围0~4095 SRS循环移位值 对CAT1/CATM/CAT-NB子载波15kHz，每次调用对应1ms内2个时隙，该参数表示子帧号；对CAT-NB子载波3.75kHz，每次调用对应2ms内1个时隙，该参数表示时隙号 无线帧号，取值范围0~1023 OFDM OFFSET配置寄存器 最后一个OFDM符号的offset值 第一个OFDM符号的offset值 中断使能寄存器 0：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：ULDFT访问TXRX或PUSCH存储器ERROR中断不使能 1：AXIDMA中断使能 0：AXIDMA中断未使能 1：OFDM符号13中断使能 0：OFDM符号13中断未使能 1：OFDM符号12中断使能 0：OFDM符号12中断未使能 1：OFDM符号11中断使能 0：OFDM符号11中断未使能 1：OFDM符号10中断使能 0：OFDM符号10中断未使能 1：OFDM符号9中断使能 0：OFDM符号9中断未使能 1：OFDM符号8中断使能 0：OFDM符号8中断未使能 1：OFDM符号7中断使能 0：OFDM符号7中断未使能 1：OFDM符号6中断使能 0：OFDM符号6中断未使能 1：OFDM符号5中断使能 0：OFDM符号5中断未使能 1：OFDM符号4中断使能 0：OFDM符号4中断未使能 1：OFDM符号3中断使能 0：OFDM符号3中断未使能 1：OFDM符号2中断使能 0：OFDM符号2中断未使能 1：OFDM符号1中断使能 0：OFDM符号1中断未使能 1：OFDM符号0中断使能 0：OFDM符号0中断未使能 OFDM符号填零发送寄存器 指示填零发送的OFDM符号数： 14’b0：没有填零发送 14’b1：符号0填零发送 14’b11：符号0，1填零发送 14’b111：符号0，1，2填零发送 …… DFT/IDFT&FFT/IFFT控制寄存器 0：软件未触发ULDFT启动 1：软件触发ULDFT启动 0：ULDFT启动模式为软件触发 1：ULDFT启动模式为PUSCH模块触发 0：启窗不使能 1：启窗使能 0：SRS产生不使能 1：SRS产生使能 0：FFT输入MEM清零功能不使能 1：FFT输入MEM清零功能使能 1：选择IFFT运算 0：选择FFT运算 1：FFT/IFFT运算使能 0：FFT/IFFT运算不使能 0：功率调整不使能 1：功率调整使能 指示PRACH格式类型： 000：PRACH格式0 001：PRACH格式1 010：PRACH格式2 011：PRACH格式3 100：PRACH格式4 其他：保留 指示PUCCH格式类型： 000：PUCCH格式1 001：PUCCH格式1a 010：PUCCH格式1b 011：PUCCH格式2 100：PUCCH格式2a 101：PUCCH格式2b 其他：保留 0：NPUSCH format 1 1：NPUSCH format2 指示OFDM符号的个数 0：DATADRIVE不使能 1：DATADRIVE使能 指示UL_DFT读PUSCH BUFFER块选择： 00：PUSCH BUFFER1 01：PUSCH BUFFER2 10：PUSCH BUFFER3 11：PUSCH PRA_BUF 指示上行信道发送模式 000：PUSCH 001：PUCCH 010：PRACH 011：SRS 100：NPUSCH 101：NPRACH 其他：保留 FFT/IFFT点数选择 111：保留（不可配） 110：保留（不可配） 101：保留（不可配） 100：2048点 011：1024点 010：512点 001：256点 000：128点 0: 中断不使能 1: 中断使能 SRS的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit PUSCH/PUCCH/PRACH的FFT截位因子参数寄存器 FFT第十一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第十级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第九级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第八级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第七级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第六级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第五级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第四级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第三级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第二级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit FFT第一级截位因子指示： 2’b00：截取25~14bit 2’b01：截取26~15bit 2’b10：截取27~16bit 2’b11：截取28~17bit NPUSCH参数寄存器 NPUSCH当前重复传输的第几次，取值范围0~127 子载波个数： 00：1个子载波 01：3个子载波 10：6个子载波 11：12个子载波 NPUSCH 的起始子载波位置，取值范围0~47 当前传输的第几个Nslots单位，取值范围1~160 0: 3.75KHz 1: 15KHz NPUSCH DMRS参数寄存器 首个RU的首个时隙号，取值范围0~19 用于子载波个数为1生成DMRS时，表示第几个时隙，取值范围0~20480 BASE_SEQ_CURR值，取值范围0~30 CYCLIC_SHIFT值，取值范围0~3 NPRACH参数寄存器 t值，取值范围0~128 frequency location of the first sub-carrier allocated to NPRACH： 000：frequency location为0； 001：frequency location为2； 010：frequency location为12 011：frequency location为18 100：frequency location为24 101：frequency location为34 110：frequency location为36 111：默认为0 being the subcarrier selected by the MAC layer from ，取值范围0-47 状态机只读寄存器 TXRX PING存储器空满指示 1：存储器满 0：存储器空 TXRX PANG存储器空满指示 1：存储器满 0：存储器空 子帧级状态机指示 符号级状态机指示 OFDM符号计数只读寄存器 OFDM符号计数，取值范围0~13 ASSERT状态机只读寄存器 ASSERT TXRX PING存储器空满指示 1：存储器满 0：存储器空 ASSERT TXRX PANG存储器空满指示 1：存储器满 0：存储器空 ASSERT子帧级状态机指示 ASSERT符号级状态机指示 OFDM符号计数只读寄存器 ASSERT OFDM符号计数，取值范围0~13 中断标志寄存器 发送完成TRACE中断标志 0：此中断未产生 1：此中断产生 接收完成TRACE中断标志 0：此中断未产生 1：此中断产生 发送完成中断标志 0：此中断未产生 1：此中断产生 发送符号中断标志 0：此中断未产生 1：此中断产生 接收完成中断标志 0：此中断未产生 1：此中断产生 接收符号中断标志 0：此中断未产生 1：此中断产生 中断屏蔽寄存器 发送完成TRACE屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 接收完成TRACE屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 发送完成中断屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 发送符号中断屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 接收完成中断屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 接收符号中断屏蔽位 0：不屏蔽此中断 1：屏蔽此中断 OFDM中断标志位寄存器 0：下行OFDM符号14中断未产生 1：下行OFDM符号14中断产生 0：下行OFDM符号13中断未产生 1：下行OFDM符号13中断产生 0：下行OFDM符号12中断未产生 1：下行OFDM符号12中断产生 0：下行OFDM符号11中断未产生 1：下行OFDM符号11中断产生 0：下行OFDM符号10中断未产生 1：下行OFDM符号10中断产生 0：下行OFDM符号9中断未产生 1：下行OFDM符号9中断产生 0：下行OFDM符号8中断未产生 1：下行OFDM符号8中断产生 0：下行OFDM符号7中断未产生 1：下行OFDM符号7中断产生 0：下行OFDM符号6中断未产生 1：下行OFDM符号6中断产生 0：下行OFDM符号5中断未产生 1：下行OFDM符号5中断产生 0：下行OFDM符号4中断未产生 1：下行OFDM符号4中断产生 0：下行OFDM符号3中断未产生 1：下行OFDM符号3中断产生 0：下行OFDM符号2中断未产生 1：下行OFDM符号2中断产生 0：下行OFDM符号1中断未产生 1：下行OFDM符号1中断产生 0：下行OFDM符号0中断未产生 1：下行OFDM符号0中断产生 接收符号中断使能寄存器 符号级中断使能信号（此比特为1时，符号级中断使能有效；反之，符号级中断使能无效）： 0：中断不使能 1：中断使能 0：最后一个OFDM符号中断不使能 1：最后一个OFDM符号中断使能 0：OFDM符号14中断不使能 1：OFDM符号14中断使能 0：OFDM符号13中断不使能 1：OFDM符号13中断使能 0：OFDM符号12中断不使能 1：OFDM符号12中断使能 0：OFDM符号11中断不使能 1：OFDM符号11中断使能 0：OFDM符号10中断不使能 1：OFDM符号10中断使能 0：OFDM符号9中断不使能 1：OFDM符号9中断使能 0：OFDM符号8中断不使能 1：OFDM符号8中断使能 0：OFDM符号7中断不使能 1：OFDM符号7中断使能 0：OFDM符号6中断不使能 1：OFDM符号6中断使能 0：OFDM符号5中断不使能 1：OFDM符号5中断使能 0：OFDM符号4中断不使能 1：OFDM符号4中断使能 0：OFDM符号3中断不使能 1：OFDM符号3中断使能 0：OFDM符号2中断不使能 1：OFDM符号2中断使能 0：OFDM符号1中断不使能 1：OFDM符号1中断使能 0：OFDM符号0中断不使能 1：OFDM符号0中断使能 系统级配置寄存器 接收DCOC值基准选择 1：软件配置基准值 0：按符号计算基准值 0：接收数据最高比特不翻转 1：接收数据最高比特翻转 0：发送数据最高比特不翻转 1：发送数据最高比特翻转 DFE模式使能信号 0：非DFE模式 1：DFE模式 窄带模式使能信号 0：非窄带模式 1：窄带模式 CAT1模式使能信号 0：非CAT1模式 1：CAT1模式 立即停止配置寄存器 上行立即停止功能 0：不使能 1：使能 下行立即停止功能 0：不使能 1：使能 接收全局配置寄存器 SOFT AFC 功能使能 0：不使能 1：使能 RSSI计算窗长 1：半个符号的data段 0：一个符号的data段 RSSI 值存储位置选择 0: 存储在RSSI_MAX1 1: 存储在RSSI_MAX2 2: 存储在RSSI_MAX3 3: 存储在RSSI_MAX4 4: 存储在RSSI_MAX5 Other:不可配置 半带滤波计算使能 1：使能 0：不使能 OTDOA通路使能 1：使能 0：不使能 offset使用类型标识指示 1：RX使用offset值进行cp长度调整，并传值给相关模块； 0：使用offset余数值传给相关模块； 1：IDDET通路使能 0：IDDET通路不使能 与DLFFT交互机制使能控制（下行 DATA_DRIVE机制） 0：不使能 1：使能 00：普通CP 01：扩展CP 10：无CP（仅用于IDDET场景） 半带FIR乘累加后比特选择： 4’h0：33-22 4’h1：32-21 4’h2：31-20 4’h3：30-19 4’h4：29-18 4’h5：28-17 4’h6：27-16 4’h7：26-15 4’h8：25-14 4’h9：24-13 4’ha：23-12 4’hb：22-11 4’hc：21-10 4’hd：20-9 4’he：19-8 4’hf：18-7 接收TRACE功能使能 1：使能 0：不使能 余数传0标识（measpwr/dlfft offset）： 1：传0； 0：根据offset和offset_ctrl_flag，传余数 测量任务使能控制 0：不使能 1：使能 接收通路归一化计算使能 0：不使能 1：使能 接收均值计算使能： 0：不使能 1：使能 接收通路数据统计使能 0：不使能 1：使能 RSSI计算使能 1：使能 0：不使能 全局接收通路使能 0：不使能 1：使能 接收首个OFDM符号长度修正值 接收首个OFDM符号长度修正值 SOFT AFC调整因子寄存器 AFC软件频偏调整使能 1：使能 0：不使能 AFC软件频偏调整因子 （因子有正负，步长10hz，） RSSI MAX参数寄存器 下一次接收的标志 1：下次接收标志使能 0：下次接收标志不使能 （硬件在AD_ON上升沿清0） RSSI最大值清除标志（硬件立即清0） 1：清除标志使能 0：清除标志不使能 计算RSSI最大值的起点符号号码 接收归一化配置寄存器 指示当前接收使用第几个最大值来进行归一化操作 配置范围1~5 接收饱和数值寄存器 饱和数最大值 当比较点的值大于等于该值时，被判定为饱和数 饱和数最小值 当比较点的值小于等于该值时，被判定为饱和数 接收PRE功能配置寄存器 接收序列点乘参数 接收系统带宽 3’h5: 20M (对应降采样率1/16) 3’h4: 15M (对应降采样率1/16) 3’h3: 10M (对应降采样率1/8) 3’h2: 5M (对应降采样率1/4) 3’h1: 3M (对应降采样率1/2) 3’h0: 1.4M Other:不可配置 接收点乘计算使能 1：使能 0：不使能 FIR滤波使能 1：使能 0：不使能 接收FIR乘累加后比特选择： 5’b00000：34-23 5’b00001：33-22 5’b00010：32-21 5’b00011：31-20 5’b00100：30-19 5’b00101：29-18 5’b00110：28-17 5’b00111：27-16 5’b01000：26-15 5’b01001：25-14 5’b01010：24-13 5’b01011：23-12 5’b01100：22-11 5’b01101：21-10 5’b01110：20-9 5’b01111：19-8 5’b10000：18-7 5’b10001：17-6 5’b10010：16-5 Other：不能配置 接收辅助控制寄存器 接收软件配置因子寄存器 接收直流值配置寄存器 DCOC值更新使能 0：不使能 1：使能 接收直流值I 接收直流值Q 接收增益1配置寄存器 GAIN1使能 0：不使能 1：使能 接收GAIN1值 接收增益2配置寄存器 GAIN2使能 0：不使能 1：使能 接收GAIN2值 接收数据输出配置寄存器 IDDET数据截位起点 2’h0:bit7 2'h1:bit8 2‘h2:bit9 2'h3:bit10 IDDET数据截位终点 3’h0:bit0 3'h1:bit1 3‘h2:bit2 3'h3:bit3 3’h4:bit4 other:reserved OTDOA数据截位起点 2’h0:bit7 2'h1:bit8 2‘h2:bit9 2'h3:bit10 OTDOA数据截位终点 3’h0:bit0 3'h1:bit1 3‘h2:bit2 3'h3:bit3 3’h4:bit4 other:reserved MEASPWR数据截位起点 2’h0:bit7 2'h1:bit8 2‘h2:bit9 2'h3:bit10 MEASPWR数据截位终点 3’h0:bit0 3'h1:bit1 3‘h2:bit2 3'h3:bit3 3’h4:bit4 other:reserved 发送全局配置寄存器 发送回环使能（调试使用） 0：不使能 1：使能 上行DATA_DRIVE机制 0：不使能 1：使能 1：扩展CP 0：普通CP 发送通路使能 0：不使能 1：使能 发送首个OFDM符号长度修正值 发送首个OFDM符号长度修正值配置(-32~31个点) 发送PING数据和CP长度寄存器 发送PING数据和CP长度（长度从0开始） 发送PANG数据和CP长度寄存器 发送PANG数据和CP长度（长度从0开始） 发送POST功能配置寄存器 PRACH使能控制 1：使能 0：不使能 （来自DFT模块，子帧级更新，软件只读） PRACH 格式控制 3‘hx：格式x（x为0~4） （来自DFT模块，子帧级更新，软件只读） 发送序列点乘参数：NB在系统带宽中的起始值 （来自DFT模块，子帧级更新，软件只读） 发送滤波使能； 1：使能 0：不使能 （来自DFT模块，子帧级更新，软件只读） 发送带宽 3’h5: 20M (对应升采样率16) 3’h4: 15M (对应升采样率16) 3’h3: 10M (对应升采样率8) 3’h2: 5M (对应升采样率4) 3’h1: 3M (对应升采样率2) 3’h0: 1.4M Other:不可配置 发送频偏点乘使能： 1：使能 0：不使能 发送FIR乘累加后比特选择： 5’b00000：34-23 5’b00001：33-22 5’b00010：32-21 5’b00011：31-20 5’b00100：30-19 5’b00101：29-18 5’b00110：28-17 5’b00111：27-16 5’b01000：26-15 5’b01001：25-14 5’b01010：24-13 5’b01011：23-12 5’b01100：22-11 5’b01101：21-10 5’b01110：20-9 5’b01111：19-8 5’b10000：18-7 5’b10001：17-6 5’b10010：16-5 Other：不能配置 发送冗余数据数量寄存器 发送冗余数据0个数 8’hff : 255个 8’hfe: 254个 ………… 8’h01: 1个 8’h00: 0个（不发送冗余数据） 接收软件配置因子当前值寄存器 接收饱和数据统计寄存器 接收归一化因子寄存器 接收归一化因子寄存器 RSSI 最大值寄存器1 RSSI 最大值寄存器2 RSSI 最大值寄存器3 RSSI 最大值寄存器4 RSSI 最大值寄存器5 接收直流计算输出值寄存器 接收直流计算输出值I 接收直流计算输出值Q 接收OFDM符号指示寄存器 当前RX_MEM的写地址 AD_ON驱动控制信号 接收运行指示信号 0：运行中 1：未运行 DLFFT功能使能信号 OTDOA功能使能信号 IDDET功能使能信号 MEAS功能使能信号 一次接收过程中CP类型修改 0：无修改 1：有修改 无接收数据异常指示 0：无异常 1：有异常 接收的PING_PANG状态指示 指示当前接收的是第几个OFDM符号 发送FIFO位置寄存器 当前TX_MEM的读地址 DA_ON驱动控制信号 接收运行指示信号 0：未运行 1：运行中 发送FIFO位置寄存器 0：在ping存储器 1：在pang存储器 指示当前发送的是第几个OFDM符号 接收错误时刻状态寄存器 帧号（子帧） 子帧内的TS计数值 符号计数 AD_ON驱动控制信号 接收运行指示信号0：未运行1：运行中 输入的mem选择信号 输出的乒乓信号 CP 类型 发送错误时刻状态寄存器 帧号（子帧） 子帧内的TS计数值 符号计数 DA_ON驱动控制信号 接收运行指示信号 0：未运行 1：运行中 PING RAM选择信号 DFT写PING错误信号 DFT写PANG错误信号 PING读取时空错误信号 PANG读取时空错误信号 RF子帧FRAMC锁存值寄存器 ADON上升沿时的FRAMC值 第一个接收子帧中断时的FRAMC值 RF子帧FRAMC偏差寄存器 本次接收的子帧中断个数 当前的子帧中断和首次子帧中断的FRAMC差值 AD_ON变化时间寄存器 奇数次AD_ON下降沿时间 奇数次AD_ON上升沿时间 偶数次AD_ON下降沿时间 偶数次AD_ON上升沿时间 DA_ON变化时间寄存器 奇数次DA_ON下降沿时间 奇数次DA_ON上升沿时间 偶数次DA_ON下降沿时间 偶数次DA_ON上升沿时间 FFTBUF1中断时间寄存器 第4次FFTBUF1中断时间 第3次FFTBUF1中断时间 第2次FFTBUF1中断时间 第1次FFTBUF1中断时间 FFTBUF2中断时间寄存器 第4次FFTBUF2中断时间 第3次FFTBUF2中断时间 第2次FFTBUF2中断时间 第1次FFTBUF2中断时间 FFT2LDTC中断时间寄存器 第4次FFT2LDTC中断时间 第3次FFT2LDTC中断时间 第2次FFT2LDTC中断时间 第1次FFT2LDTC中断时间 TX FIR3 系数配置寄存器 滤波器A2系数值低8bit 滤波器A1系数值 滤波器A0系数值 TX FIR3 系数配置寄存器 滤波器A5系数值低4bit 滤波器A4系数值 滤波器A3系数值 滤波器A2高4bit系数值 TX FIR3 系数配置寄存器 滤波器A7系数值 滤波器A6系数值 滤波器A5高8bit系数值 TX FIR3 配置寄存器 FIR3滤波器相关系数 FIR3滤波器相关系数 滤波器时钟使能位 滤波器使能位 TX FIR3 配置寄存器 数据有效信号计数 MEASPWR的接收数据控制寄存器1 FDD_TDD指示： 0：FDD 1：TDD TXRX模块的AD_ON拉高接收数据的起点位置， 0~30720*10-1（10ms）(AD ON距离服务小区帧头的距离) MEASPWR的接收数据控制寄存器2 MEASPWR使用的有效数据的长度1~30720*6(6ms) MEASPWR的有效数据控制寄存器 Offset2无效指示 0：offset2配置有效 1：offset2配置无效 MEASPWR使用的有效数据的起点位置 （0~30720*6-1） MEASPWR的ID1时延控制寄存器 ID1基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID2时延控制寄存器 ID2基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID3时延控制寄存器 s MEASPWR的ID4时延控制寄存器 ID4基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID5时延控制寄存器 ID5基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID6时延控制寄存器 ID6基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID7时延控制寄存器 ID7基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR的ID8时延控制寄存器 ID8基于服务小区的同步偏差值 (0~30720*10-1) MEASPWR NB OFSET4寄存器 Nb下offset4值 MEASPWR计算总子帧数寄存器 所有ID3~ID8计算的总子帧个数 0：1 1：2 2：3 …… 511:512 所有ID1和ID2计算的总子帧个数 0：1 1：2 2：3 …… 511:512 IFFT截位因子配置寄存器 IFFT第七级截位因子： 同下 IFFT第六级截位因子： 同下 IFFT第五级截位因子： 同下 IFFT第四级截位因子： 同下 IFFT第三级截位因子： 同下 IFFT第二级截位因子： 同下 IFFT第一级截位因子： 2’b00:截取bit[25:14] 2’b01:截取bit[26:15] 2’b10:截取bit[27:16] 2’b11:截取bit[28:17] MEASPWR IFFT倒数第二级饱和门限个数值寄存器 IFFT倒数第二级饱和门限个数值 MEASPWR中断使能寄存器 ID8 的中断使能，1有效，0无效 bit[28]：样本结束中断使能 bit[29]：门限值到达中断使能 bit[30]：AFC结果输出中断使能 bit[31]:agc_compare门限到达中断使能 ID7 的中断使能，1有效，0无效 bit[24]：样本结束中断使能 bit[25]：门限值到达中断使能 bit[26]：AFC结果输出中断使能 bit[27]:agc_compare门限到达中断使能 ID6 的中断使能，1有效，0无效 bit[20]：样本结束中断使能 bit[21]：门限值到达中断使能 bit[22]：AFC结果输出中断使能 bit[23]:agc_compare门限到达中断使能 ID5 的中断使能，1有效，0无效 bit[16]：样本结束中断使能 bit[17]：门限值到达中断使能 bit[18]：AFC结果输出中断使能 bit[19]:agc_compare门限到达中断使能 ID4 的中断使能，1有效，0无效 bit[12]：样本结束中断使能 bit[13]：门限值到达中断使能 bit[14]：AFC结果输出中断使能 bit[15]:agc_compare门限到达中断使能 ID3 的中断使能，1有效，0无效 bit[8]：样本结束中断使能 bit[9]：门限值到达中断使能 bit[10]：AFC结果输出中断使能 bit[11]:agc_compare门限到达中断使能 ID2 的中断使能，1有效，0无效 bit[4]：样本结束中断使能 bit[5]：门限值到达中断使能 bit[6]：AFC结果输出中断使能 bit[7]:agc_compare门限到达中断使能 ID1 的中断使能，1有效，0无效 bit[0]：样本结束中断使能 bit[1]：门限值到达中断使能 bit[2]：AFC结果输出中断使能 bit[3]:agc_compare门限到达中断使能 MEASPWR中断状态寄存器 ID8 的中断状态，1有效，0无效 bit[28]：样本结束中断状态 bit[29]：门限值到达中断状态 bit[30]：AFC结果输出中断状态 bit[31]:agc_compare门限到达状态 ID7 的中断状态，1有效，0无效 bit[24]：样本结束中断状态 bit[25]：门限值到达中断状态 bit[26]：AFC结果输出中断状态 bit[27]:agc_compare门限到达状态 ID6 的中断状态，1有效，0无效 bit[20]：样本结束中断状态 bit[21]：门限值到达中断状态 bit[22]：AFC结果输出中断状态 bit[23]:agc_compare门限到达状态 ID5 的中断状态，1有效，0无效 bit[16]：样本结束中断状态 bit[17]：门限值到达中断状态 bit[18]：AFC结果输出中断状态 bit[19]:agc_compare门限到达状态 ID4 的中断状态，1有效，0无效 bit[12]：样本结束中断状态 bit[13]：门限值到达中断状态 bit[14]：AFC结果输出中断状态 bit[15]:agc_compare门限到达状态 ID3 的中断状态，1有效，0无效 bit[8]：样本结束中断状态 bit[9]：门限值到达中断状态 bit[10]：AFC结果输出中断状态 bit[11]:agc_compare门限到达状态 ID2 的中断状态，1有效，0无效 bit[4]：样本结束中断状态 bit[5]：门限值到达中断状态 bit[6]：AFC结果输出中断状态 bit[7]:agc_compare门限到达状态 ID1 的中断状态，1有效，0无效 bit[0]：样本结束中断状态 bit[1]：门限值到达中断状态 bit[2]：AFC结果输出中断状态 bit[3]:agc_compare门限到达状态 ID1和ID2的MEASPWR功能控制寄存器 TRMS频域计算功能使能 SIGMA功能使能 DOPPLER功能使能 SINR功能使能 AFC普通模式功能使能 AFC高速模式使能 TRMS功能使能 RSRP功能使能 IRT功能使能 ID3~ID8的MEASPWR功能控制寄存器 TRMS频域计算功能使能 SIGMA功能使能 DOPPLER功能使能 SINR功能使能 AFC普通模式功能使能 AFC高速模式使能 TRMS功能使能 RSRP功能使能 IRT功能使能 MEASPWR AGC差值门限值寄存器 子帧间agc差值门限值，当前子帧agc比前一帧agc大于此值时，将清零前面的计算值，重新开始计算。（无符号数） MEASPWR 窄带参数寄存器 ID3-8的窄带参数：0-15（只有CATM需要） ID2的窄带参数：0-15（只有CATM需要） ID1的窄带参数：0-15（只有CATM需要） MEASPWR ID2的带宽参数寄存器 ID3-8测量带宽参数 0：1.4m 1：3m 2：5m 3：10m 4：15m 5：20m ID3-8系统带宽参数 0：1.4m 1：3m 2：5m 3：10m 4：15m 5：20m ID1-2测量带宽参数 0：1.4m 1：3m 2：5m 3：10m 4：15m 5：20m ID1-2系统带宽参数 0：1.4m 1：3m 2：5m 3：10m 4：15m 5：20m AFC配置寄存器 Afc_factor AFC计算子帧间连续标志 0：不连续 1：连续 连续表示子帧间数据关联进行共轭计算；不连续表示子帧内4个符号进行共轭计算，子帧间无关联。 AFC计算频域相关个数 000：1 001：2 010：3 011：4 100：6： 101：12 Other:1 AFC软纠配置寄存器 ID1 AFC软纠配置因子 Sigpwr配置寄存器 SIGPWR alpha参数 SIGPWR计算时域相关个数 00：1 01：2 11：4 Other：1 ID1-2 SIGPWR计算频域相关个数(按实际数据个数配置） SIGMA配置寄存器 SIGMA alpha参数 SIGMA计算滑动窗长个数，有效取值为1~80 DOPPLER配置寄存器 Id1-2 Doppler alpha参数 Doppler_scale（Q12的有符号数） DOPPLER计算滑动窗长个数，有效取值为1~80 TRMS配置寄存器1 Trms选径门限（无符号的，8q0，正数） 噪声区域选择 0：使用TRMS的Dis_Limit去计算噪声 1：使用RSRP的Dis_Limit去计算噪声 ID3-8抽值标志: 0:连续抽取，相当于注1的L_U16ExtractStepTab_true间隔为1 1：按照注1的L_U16ExtractStepTab_true间隔进行抽取 ID1-2抽值标志: 0:连续抽取，相当于注1的L_U16ExtractStepTab_true间隔为1 1：按照注1的L_U16ExtractStepTab_true间隔进行抽取 信号区域(单边长度，即半径N，信号区域为2N+1) TRMS配置寄存器2 ID1-2信号门限因子（有符号的，16q15，正数） ID1-2噪声门限因子（有符号的，16q10，正数） RSRP配置寄存器1 ID3-8抽值标志 ID1-2抽值标志 ID1-2噪声门限因子beta值（有符号的16Q10，只能配置为正数） 信号区域 RSRP配置寄存器2 ID3-8RSRP的补偿值 ID1-2RSRP的补偿值 L_S32RsrpdB_Temp = L_S32RsrpdB - AGC_Base*16 - RSRPAgcAdjust*16 + L_U16DownSamplingCompensate*16； RSRP配置寄存器3 ID1-2信号门限因子 RSSI Q值；(有符号) RSRP配置寄存器4 FFT和IFFT的Q值变化； 经过FFT和IFFT的放大倍数； IRT参数配置寄存器1 IRT负时延前向保护标志 0：不保护（原8910方案） 1：保护 pow最大值个数 Scale计算使用径数 信号区域 IRT计算时域单次累加样本个数 00：1 01：2 11：4 IRT 参数配置寄存器2 ID1-2信号门限因子 ID1-2噪声门限因子（有符号的，16q10，正数） IRT ID1-2 Scale1门限参数值寄存器 IRT ID1-2 Scale2门限参数值寄存器 IRT ID1-2 Scale4门限参数值寄存器 IRT ID1-2 Scale8门限参数值寄存器 IRT ID1-2 Scale16门限参数值寄存器 IRT ID1-2 Scale32门限参数值寄存器 IRT ID1-2 Scale64门限参数值寄存器 IRT ID1-2 Scale128门限参数值寄存器 IRT ID1-2 Scale256门限参数值寄存器 IRT ID1-2 Scale512门限参数值寄存器 RSSI参数配置寄存器 ID3-8 Rssi补偿值 ID1-2 Rssi补偿值 所有ID的RSSI的计算方式选择： 0：MEASPWR使用的有效数据中有效的OFDM符号计算RSSI 1：MEASPWR使用的有效数据长度的数据计算 MEASPWR的接收数据的AGC寄存器 接收天线的AGC，有符号数 MEASPWR ID1参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 AFC输出步进参数，以实际值减一配置 Crs_rssi归属选择 00：归属一 01：归属二 10：归属三 11：reserved 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 AFC结果输出时间选择 0：同IRT 1：以bit[8:1]配置的子帧数为间隔 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP MEASPWR ID1参数寄存器2 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls Crs_rssi清零控制 有效子帧映射，从bit[25:16]一次对应子帧9-0 OFFLINE模式0步进长度 SINR归属频段设置 000：NA（不使能窄带SINR） 001：频段1 010：频段2 011：频段3 100：频段4 Other：NA AFC关联使能 0：与前一子帧数据关联 1：与前一子帧数据不关联 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID2参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 AFC输出步进参数，以实际值减一配置 Crs_rssi归属选择 00：归属一 01：归属二 10：归属三 11：reserved 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 AFC结果输出时间选择 0：同IRT 1：以bit[8:1]配置的子帧数为间隔 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP MEASPWR ID2参数寄存器2 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls Crs_rssi清零控制 有效子帧映射，从bit[25:16]一次对应子帧9-0 OFFLINE模式0步进长度 AFC关联使能 0：与前一子帧数据关联 1：与前一子帧数据不关联 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID3参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID4参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID5参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID6参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID7参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID8参数寄存器1 FFT的采用定点数截位方式一的前几级级数： 4`b0000：各级都采用截位方式二 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二 …. OFFLINE模式0步进次数 下行首子帧首符号有效指示 0：无效 1：有效 NID值：取值为 0~503 发射天线为2时使用的port指示 0：port 0 and port 1 1：only port 1 发射天线数： 0：1发射天线 1：2发射天线 CP类型： 0：常规CP 1：扩展CP Crs_rssi清零控制 最后一个数据窗标记 滑动窗清零控制 0：不清零 1：清零 重新开始控制位： 0：与前面子帧连续 1：开始全新计算 该位被置1后，在下一子帧将前面的计算结果全部清零，重新开始计算和子帧计数 MEASPWR ID控制寄存器 Offline模式选择 0：模式0多次自动计算模式 1：模式1单次直接配置模式 offline数据选择： 0：使用当前数据 1：使用原始数据 NID1-2参数信息 IRT软纠正使能： 0：不使能 1：使能 AFC软纠正使能： 0：不使能 1：使能 模式选择： 0：CATM 1：CAT1 2：NB 其他：NB_LTE下启动FFT功能 MEASPWR ID控制寄存器 NID_MAP无效指示 0：配置有效 1：配置无效 NID3-8参数信息 Offline与online模式选择： 0：online模式 1：offline模式 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 指示当前窗有效ID，1 有效，0无效 MEASPWR控制寄存器 启动NID8 启动NID7 启动NID6 启动NID5 启动NID4 启动NID3 启动NID2 启动NID1 ID1 AFC输出寄存器 AFC输出结果 ID2 AFC输出寄存器 AFC输出结果 ID3 AFC输出寄存器 AFC输出结果 ID4 AFC输出寄存器 AFC输出结果 ID5 AFC输出寄存器 AFC输出结果 ID1基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID2基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID3基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID4基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID5基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 频段1 SIGPWR输出寄存器 频段2 SIGPWR输出寄存器 频段3 SIGPWR输出寄存器 频段4 SIGPWR输出寄存器 频段5 SIGPWR输出寄存器 频段6 SIGPWR输出寄存器 ID2 SIGPWR输出寄存器 ID3 SIGPWR输出寄存器 ID4 SIGPWR输出寄存器 ID5 SIGPWR输出寄存器 频段1 SIGMA输出寄存器 频段1基准AGC输出寄存器 频段1的SINR LOG值 频段1的SIGMA对应的AGC 频段2 SIGMA输出寄存器 频段2基准AGC输出寄存器 频段2的SINR LOG值 频段2的SIGMA对应的AGC 频段3 SIGMA输出寄存器 频段3基准AGC输出寄存器 频段3的SINR LOG值 频段3的SIGMA对应的AGC 频段4 SIGMA输出寄存器 频段4基准AGC输出寄存器 频段4的SINR LOG值 频段4的SIGMA对应的AGC 窄带总SIGMA输出寄存器 窄带基准AGC输出寄存器 频段5的SINR LOG值 窄带总的SIGMA对应的AGC ID1 SIGMA输出寄存器 ID1基准AGC输出寄存器 频段6的SINR LOG值 ID1的SIGMA对应的AGC ID2 SIGMA输出寄存器 ID2基准AGC输出寄存器 ID2的SINR LOG值 ID2的SIGMA对应的AGC ID3 SIGMA输出寄存器 ID3基准AGC输出寄存器 ID3的SINR LOG值 ID3的SIGMA对应的AGC ID4 SIGMA输出寄存器 ID4基准AGC输出寄存器 ID4的SINR LOG值 ID4的SIGMA对应的AGC ID5 SIGMA输出寄存器 ID5基准AGC输出寄存器 ID5的SINR LOG值 ID5的SIGMA对应的AGC 频段1的SINR输出寄存器 频段2的SINR输出寄存器 频3的SINR输出寄存器 频段4的SINR输出寄存器 窄带总的SINR输出寄存器 ID1的SINR输出寄存器 ID2的SINR输出寄存器 ID3的SINR输出寄存器 ID4的SINR输出寄存器 ID5的SINR输出寄存器 ID1 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID1 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） RSRP线性值寄存器 RSRP功率值寄存器 RSRP功率dB值 RSRP 的Scale值寄存器 RSRP 的Scale的dB值寄存器 Scale的dB值 RSRP 的RSRQ的dB值寄存器 RSRQ的dB值（通道以及OFDM符号拉齐之后的结果） RSRP 的RSSI的线性值寄存器 RSRP 的RSSI的dB值寄存器 RSSI的dB值（通道以及OFDM符号拉齐之后的结果） IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 IRT的delay值寄存器 时延估计值 IRT scale标志寄存器 Irt_scale值是否达到门限标志 1：达到门限 0：未达门限 IRTscale对应的样本数 IRT的Scale值寄存器 ID1 TRMS的Scale值寄存器 时延估计值 ID1 TRMS的Scale值寄存器 时延估计值 ID信息输出寄存器1 ID2信息输出 ID1信息输出 RBIS参数寄存器 ID1-2 RBIS CORRECT使能： 0：不使能 1：使能 ID1-2 RBIS JUDGE使能： 0：不使能 1：使能 ID1-2 RBIS使能： 0：不使能 1：使能 ID1-2 RBIS使用直接位置指示： 0：不使用直接位置 1：使用直接位置 ID1-2 RBIS检测个数： 0：1 1：2 2：3 3：4 4：5 ID1-2 RBIS的直接位置 ID1-2 RBIS因子 RBIS ID1 输出寄存器1 ID1第4强RBI所处PRB索引输出 ID1第3强RBI所处PRB索引输出 ID1第2强RBI所处PRB索引输出 ID1第1强RBI所处PRB索引输出 RBIS ID1输出寄存器2 ID1 RBIS JUDGE个数输出 ID1第5强RBI所处PRB索引输出 RBIS ID1 AVE输出寄存器 RBIS ID1 MAX输出寄存器 ID1 RBIS检测出的最大值 RX_IRT输出寄存器 ID2 offset4值 ID2 RX IRT值 ID1 offset4值 ID1 RX IRT值 DEBUG输出寄存器 1 debug_rev_flag debug_update_flag id_update offset2_update din_id_sel datagen_state datain_state DEBUG输出寄存器 2 inmem_in_act invalid_data_cont inmem_cont DEBUG输出寄存器 3 datain_state_cur func_id_sel pow_state func_state ID6 SIGPWR输出寄存器 ID7 SIGPWR输出寄存器 ID8 SIGPWR输出寄存器 ID6 SIGMA输出寄存器 ID6基准AGC输出寄存器 ID6的SINR LOG值 ID6的SIGMA对应的AGC ID7 SIGMA输出寄存器 ID7基准AGC输出寄存器 ID7的SINR LOG值 ID7的SIGMA对应的AGC ID8 SIGMA输出寄存器 ID8基准AGC输出寄存器 ID8的SINR LOG值 ID8的SIGMA对应的AGC ID6的SINR输出寄存器 ID7的SINR输出寄存器 ID8的SINR输出寄存器 AFC软纠配置寄存器 ID2 AFC软纠配置因子 AFC软纠配置寄存器 ID3 AFC软纠配置因子 AFC软纠配置寄存器 ID4 AFC软纠配置因子 AFC软纠配置寄存器 ID5 AFC软纠配置因子 AFC软纠配置寄存器 ID6 AFC软纠配置因子 AFC软纠配置寄存器 ID7 AFC软纠配置因子 AFC软纠配置寄存器 ID8 AFC软纠配置因子 DOPPLER配置寄存器 Id3-8 Doppler alpha参数 频域TRMS配置寄存器 trmsf_scale(Q12的有效符号） 频域TRMS数据计算间隔 频域TRMS alpha参数 MEASPWR ID3的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 MEASPWR ID4的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 MEASPWR ID5的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 MEASPWR ID6的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 MEASPWR ID7的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 MEASPWR ID8的参数寄存器2 OFFLINE模式0步进长度 Hmmse QF mem选择： 0：固定QF mem 1：动态QF mem IRT scale门限不使能控制 0：使能门限判断 1：不使能门限判断 AFC\POW数据输入选择 00：hls 01：hmmse 10：freqfirst 11：hls 有效子帧映射，从bit[9:0]依次对应子帧9-0 ID1 AFC HST输出寄存器 AFC HST输出结果 ID2 AFC HST输出寄存器 AFC HST输出结果 ID3 AFC HST输出寄存器 AFC HST输出结果 ID4 AFC HST输出寄存器 AFC HST输出结果 ID5 AFC HST输出寄存器 AFC HST输出结果 ID6 AFC HST输出寄存器 AFC HST输出结果 ID7 AFC HST输出寄存器 AFC HST输出结果 ID8 AFC HST输出寄存器 AFC HST输出结果 ID1 SIGPWR输出寄存器 ID2 SIGPWR输出寄存器 ID3 SIGPWR输出寄存器 ID4 SIGPWR输出寄存器 ID5 SIGPWR输出寄存器 ID6 SIGPWR输出寄存器 ID7 SIGPWR输出寄存器 ID8 SIGPWR输出寄存器 ID1 SIGMA输出寄存器 ID2 SIGMA输出寄存器 ID3 SIGMA输出寄存器 ID4 SIGMA输出寄存器 ID5 SIGMA输出寄存器 ID6 SIGMA输出寄存器 ID7 SIGMA输出寄存器 ID8 SIGMA输出寄存器 ID3 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID4 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID5 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID6 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID7 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID8 DOPPLER输出寄存器 hls_agc_base输出 DOPPLER输出 ID1 DOPPLER平滑前输出寄存器1 ID1 DOPPLER平滑前输出寄存器2 ID2 DOPPLER平滑前输出寄存器1 ID2 DOPPLER平滑前输出寄存器2 ID1 TRMS频域输出寄存器 ID2 TRMS频域输出寄存器 ID3 TRMS频域输出寄存器 ID4 TRMS频域输出寄存器 ID5 TRMS频域输出寄存器 ID6 TRMS频域输出寄存器 ID7 TRMS频域输出寄存器 ID8 TRMS频域输出寄存器 ID1 TRMS频域PART1输出寄存器 ID1 TRMS频域PART2输出寄存器 ID2 TRMS频域PART1输出寄存器 ID2 TRMS频域PART2输出寄存器 ID3 TRMS频域PART1输出寄存器 ID3 TRMS频域PART2输出寄存器 ID4 TRMS频域PART1输出寄存器 ID4 TRMS频域PART2输出寄存器 ID5 TRMS频域PART1输出寄存器 ID5 TRMS频域PART2输出寄存器 ID6 TRMS频域PART1输出寄存器 ID6 TRMS频域PART2输出寄存器 ID7 TRMS频域PART1输出寄存器 ID7 TRMS频域PART2输出寄存器 ID8 TRMS频域PART1输出寄存器 ID8 TRMS频域PART2输出寄存器 ID1 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID2 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID3 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID4 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID5 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID6 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID7 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID8 POW最大值寄存器 POW最大值（最大值的bit[23:0]） 最大值位置 ID3 TRMS的Scale值寄存器 时延估计值 ID4 TRMS的Scale值寄存器 时延估计值 ID5 TRMS的Scale值寄存器 时延估计值 ID6 TRMS的Scale值寄存器 时延估计值 ID7 TRMS的Scale值寄存器 时延估计值 ID8 TRMS的Scale值寄存器 时延估计值 REIS配置寄存器 REIS_DC使能 REIS使能： 0：不使能 1：使能 REIS的NUM个数 REIS位置寄存器0 REIS1的RE位置（20M带宽1200个RE的绝对位置） REIS0的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器1 REIS3的RE位置（20M带宽1200个RE的绝对位置） REIS2的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器0 REIS5的RE位置（20M带宽1200个RE的绝对位置） REIS4的RE位置（20M带宽1200个RE的绝对位置） REIS位置寄存器0 REIS7的RE位置（20M带宽1200个RE的绝对位置） REIS6的RE位置（20M带宽1200个RE的绝对位置） OFFLINE模式0选择寄存器 Pos\delay判决选择标志 0：pos 1:delay 门限目标选择： 00：IRT_Scale 01：RSRP_Scale 10：SINR 11：POWMAX_Scale 排序目标选择： 00：IRT_Scale 01：Sigpwr 10：SINR 11：IRT_Scale OFFLINE模式0门限值寄存器 OFFLINE模式0最大值位置寄存器 Id8最佳TBin位置 Id7最佳TBin位置 Id6最佳TBin位置 Id5最佳TBin位置 Id4最佳TBin位置 Id3最佳TBin位置 Id2最佳TBin位置 Id1最佳TBin位置 OFFLINE模式0门限跳出位置寄存器 最佳Tbin位置有效标志，分别对应ID1~ID8 0：无效 1：有效 Offline门限值跳出位置寄存器 如果未达到门限则该寄存器输出为0xF OFFLINE模式1参数寄存器 首符号定义 0：符号0 1：符号4或3 Offline模式1模式选择 00：｛0｝子帧 01：｛0、5｝子帧 10：｛5、0｝子帧 11：｛9，0｝子帧 Offline模式1单次计算子帧数 0：1个 1：2个 Offline模式1计算次数 OFFLINE模式1AGC寄存器1 子帧3 AGC 子帧2 AGC 子帧1 AGC OFFLINE模式1AGC寄存器2 子帧6 AGC 子帧5 AGC 子帧4 AGC OFFLINE模式1AGC寄存器3 子帧9 AGC 子帧8 AGC 子帧7 AGC OFFLINE模式1AGC寄存器4 子帧12 AGC 子帧11 AGC 子帧10 AGC OFFLINE模式1AGC寄存器5 子帧15 AGC 子帧14 AGC 子帧13 AGC OFFLINE模式1AGC寄存器6 子帧18 AGC 子帧17 AGC 子帧16 AGC ID1 CRS_RSSI1最大值寄存器 ID1 CRS_RSSI2最大值寄存器 ID1 CRS_RSSI3最大值寄存器 ID2 CRS_RSSI1最大值寄存器 ID2 CRS_RSSI2最大值寄存器 ID2 CRS_RSSI3最大值寄存器 ID3 CRS_RSSI最大值寄存器 ID4 CRS_RSSI最大值寄存器 ID5 CRS_RSSI最大值寄存器 ID6 CRS_RSSI最大值寄存器 ID7 CRS_RSSI最大值寄存器 ID8 CRS_RSSI最大值寄存器 ID1 CRS_RSSI1AGC寄存器 Crs rssi最大值对应的agc ID1 CRS_RSSI2AGC寄存器 Crs rssi最大值对应的agc ID1 CRS_RSSI3AGC寄存器 Crs rssi最大值对应的agc ID2 CRS_RSSI1AGC寄存器 Crs rssi最大值对应的agc ID2 CRS_RSSI2AGC寄存器 Crs rssi最大值对应的agc ID2 CRS_RSSI3AGC寄存器 Crs rssi最大值对应的agc ID3 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc ID4 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc ID5 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc ID6 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc ID7 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc ID8 CRS_RSSI AGC寄存器 Crs rssi最大值对应的agc HMMSE频域估计窗长指示寄存器 频域估计窗长指示 0：频域估计窗长为3PRB； 1：频域估计窗长为6PRB HMMSE截位参数寄存器 乘累加后截取13bit数据的比特选择： 0x0：截取选择29~17 0x1：截取选择28~16 0x2：截取选择27~15 0x3：截取选择26~14 0x4：截取选择25~13 0x5：截取选择24~12 0x6：截取选择23~11 0x7：截取选择22~10 0x8：截取选择21~9 0x9：截取选择20~8 0xa：截取选择19~7 0xb：截取选择18~6 0xc：截取选择17~5 0xd：截取选择16~4 0xe：截取选择15~3 0xf：截取选择14~2 HMMSE QF MEM使用寄存器 USED_WL_IND QF MEM实际使用指示 00：乒mem； 01：乓mem Other：固定mem ID信息输出寄存器2 ID38信息输出 INMEM使用模式选择寄存器 INMEM使用模式选择： 00： measpwr功能使用 01：OTDOA功能使用 10：等分共享 11：大小共享 ID1基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID2基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID3基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID4基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID5基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID6基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID7基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID8基于AFC HST的RSRP db值输出寄存器 基于AFC HST的RSRP db输出结果 ID1 POWMAX SCALE值寄存器 ID2 POWMAX SCALE值寄存器 ID3 POWMAX SCALE值寄存器 ID4 POWMAX SCALE值寄存器 ID5 POWMAX SCALE值寄存器 ID6 POWMAX SCALE值寄存器 ID7 POWMAX SCALE值寄存器 ID8 POWMAX SCALE值寄存器 ID6 AFC输出寄存器 AFC输出结果 ID7 AFC输出寄存器 AFC输出结果 ID8 AFC输出寄存器 AFC输出结果 ID6基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID7基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID8基于AFC的RSRP db值输出寄存器 基于AFC的RSRP db输出结果 ID3 DOPPLER平滑前输出寄存器1 ID3 DOPPLER平滑前输出寄存器2 ID4 DOPPLER平滑前输出寄存器1 ID4 DOPPLER平滑前输出寄存器2 ID5 DOPPLER平滑前输出寄存器1 ID5 DOPPLER平滑前输出寄存器2 ID6 DOPPLER平滑前输出寄存器1 ID6 DOPPLER平滑前输出寄存器2 ID7 DOPPLER平滑前输出寄存器1 ID7 DOPPLER平滑前输出寄存器2 ID8 DOPPLER平滑前输出寄存器1 ID8 DOPPLER平滑前输出寄存器2 OFFLINE模式1AGC寄存器7 子帧20AGC 子帧19AGC MEASPWR中断关联寄存器 中断关联标志，bit[7:0]分别对应id8-id1 0:不关联 1：关联 MEASPWR中断记录寄存器 同ID1 同ID1 同ID1 同ID1 同ID1 同ID1 同ID1 ID1的中断标志，1有效，0无效 bit[0]：样本结束\offine结束中断标志 bit[1]：门限值达到中断标志 bit[2]：AFC结果输出中断标志 bit[3]：Agc_compare门限达到标志 MEASPWR中断标志寄存器 中断标志，bit[7:0]分别对应id8-id1 0：无效 1：有效 OFFLINE模式0判决位置寄存器1 ID1判决位置3 ID1判决位置2 ID1判决位置1 OFFLINE模式0判决位置寄存器2 ID2判决位置3 ID2判决位置2 ID2判决位置1 OFFLINE模式0判决位置寄存器3 ID3判决位置3 ID3判决位置2 ID3判决位置1 OFFLINE模式0判决位置寄存器4 ID4判决位置3 ID4判决位置2 ID4判决位置1 OFFLINE模式0判决位置寄存器5 ID5判决位置3 ID5判决位置2 ID5判决位置1 OFFLINE模式0判决位置寄存器6 ID6判决位置3 ID6判决位置2 ID6判决位置1 OFFLINE模式0判决位置寄存器7 ID7判决位置3 ID7判决位置2 ID7判决位置1 OFFLINE模式0判决位置寄存器8 ID8判决位置3 ID8判决位置2 ID8判决位置1 RBIS参数寄存器2 ID3-8 RBIS CORRECT使能： 0：不使能 1：使能 ID3-8 RBIS JUDGE使能： 0：不使能 1：使能 ID3-8 RBIS使能： 0：不使能 1：使能 ID3-8 RBIS使用直接位置指示： 0：不使用直接位置 1：使用直接位置 ID3-8 RBIS检测个数： 0：1 1：2 2：3 3：4 4：5 ID3-8 RBIS的直接位置 ID3-8 RBIS因子 RBIS ID2 输出寄存器1 ID2第4强RBI所处PRB索引 ID2第3强RBI所处PRB索引 ID2第2强RBI所处PRB索引 ID2第1强RBI所处PRB索引 RBIS ID2输出寄存器2 ID2 RBIS JUDGE个数 ID2第5强RBI所处PRB索引 RBIS ID2 AVE输出寄存器 RBIS ID2 MAX输出寄存器 ID2 RBIS检测出的最大值 RBIS ID3-8 输出寄存器1 ID3-8第4强RBI所处PRB索引 ID3-8第3强RBI所处PRB索引 ID3-8第2强RBI所处PRB索引 ID3-8第1强RBI所处PRB索引 RBIS ID3-8输出寄存器2 ID3-8 RBIS JUDGE个数 ID3-8第5强RBI所处PRB索引 RBIS ID3-8 AVE输出寄存器 RBIS ID3-8 MAX输出寄存器 ID3-8 RBIS检测出的最大值 IRT ID3-8 Scale1门限参数值寄存器 IRT ID3-8 Scale2门限参数值寄存器 IRT ID3-8 Scale4门限参数值寄存器 IRT ID3-8 Scale8门限参数值寄存器 IRT ID3-8 Scale16门限参数值寄存器 IRT ID3-8 Scale32门限参数值寄存器 IRT ID3-8 Scale64门限参数值寄存器 IRT ID3-8 Scale128门限参数值寄存器 IRT ID3-8 Scale256门限参数值寄存器 IRT ID3-8 Scale512门限参数值寄存器 Sigpwr配置寄存器2 ID3-8 SIGPWR计算频域相关个数（按实际数据个数配置） IRT参数配置寄存器2 ID3-8信号门限因子 id3-8噪声门限因子（有符号的，16q10，正数） TRMS配置寄存器3 ID3-8信号门限因子（有符号的，16q15，正数） ID3-8噪声门限因子（有符号的，16q10，正数） RSRP配置寄存器5 id3-8噪声门限因子beta值（有符号的16Q10，只能配置为正数） ID3-8信号门限因子 RBIS ID1 输入寄存器1 ID1第4强RBI所处PRB索引 ID1第3强RBI所处PRB索引 ID1第2强RBI所处PRB索引 ID1第1强RBI所处PRB索引 RBIS ID1 输入寄存器2 ID1 RBIS JUDGE个数 ID1第5强RBI所处PRB索引 RBIS ID2输入寄存器1 ID2第4强RBI所处PRB索引 ID2第3强RBI所处PRB索引 ID2第2强RBI所处PRB索引 ID2第1强RBI所处PRB索引 RBIS ID2输入寄存器2 ID2 RBIS JUDGE个数 ID2第5强RBI所处PRB索引 RBIS ID3-8输入寄存器1 ID3-8第4强RBI所处PRB索引 ID3-8第3强RBI所处PRB索引 ID3-8第2强RBI所处PRB索引 ID3-8第1强RBI所处PRB索引 RBIS ID3-8输入寄存器2 ID3-8 RBIS JUDGE个数 ID3-8第5强RBI所处PRB索引 启动寄存器 产生DMA请求把以前计算出的累加功率搬入IDDET，用于续接计算。 0:不产生请求 1:产生请求 产生DMA请求把最后一个样本计算出的累加功率存入外部MEM，在续接计算时使用。 0:不产生请求 1:产生请求 非连续模式下样本长度不足5ms+2OFDM时的样本长度： 取值范围：1~9856点 非连续模式下接收数据样本数 4’b000: 数据不足5ms+2OFDM 4’b0001: 1个样本 …… 4’b1111: 15个样本 0: 接收数据非连续 1:接收数据连续 3’b001: PSS粗同步 3’b010: PSS精同步 3’b011: SSS同步 3’b100: 频率精同步和小区有效性判断 3’b101:重同步 3’b110:频点盲搜 TXRX接收数据OFFSET使能 1:OFFSET使能 0:OFFSET不使能 1: TXRX接收数据搬出DMA请求使能; 0: TXRX接收数据搬出DMA请求不使能 1: IDDET模块暂停中 0: IDDET 模块已暂停或暂停未使能 1: IDDET模块启动 0: IDDET 模块不启动 PSS1_CTRL粗同步控制寄存器 RSSI计算使能 PSS输出主节点数.取值范围1~12，纠本地频偏使能时输出5个节点，每个频偏一个；纠本地频偏不使能时最多输出12个节点 最大值个数保存,取值范围1~5 0: ICS流程;1: IDDET流程 0: 定时漂移不使能 0: 定时漂移不使能 0: ID2未知 1: ID2已知为0 2: ID2已知为1 3: ID2已知为2 0: 纠本地频偏不使能 1: 本地频偏尝试为1 2: 本地频偏尝试为3 3: 本地频偏尝试为5 0: 数字AGC不使能 1: 数字AGC使能 0: 输入消直以及搬数使能不使能 1: 输入消直以及搬数使能使能 PSS2_CTRL精同步控制寄存器 RSSI计算使能 精同步计算点数 取值范围1~12 1:定时漂移使能 0:定时漂移不使能 1: 纠本地频偏使能 0: 纠本地频偏不使能 1: 数字AGC使能 0: 数字AGC不使能 1: 接收数据消直使能 0: 接收数据消直不使能 SSS_CTRL无线帧同步控制寄存器 RSSI计算使能 输入位置滑动计算次数 0:不进行左右滑动 1:左右分别滑动1个点 2:左右分别滑动2个点 3:左右分别滑动4个点 0:峰均比排序 1:峰值排序 每个节点输出最大值个数 1~10 NID1值，ID已知时起效 取值范围为0~168 无线帧同步计算点数 ICS和IDDET时取值范围为1~12 1:定时漂移使能 0:定时漂移不使能 0:ICS流程 1: ID DETECT流程 1: ID已知 0: ID未知 1: FDD模式 0: TDD模式 1: 干扰消除使能 0: 干扰消除不使能 1: 干扰消除使能 0: 干扰消除不使能 1: 数字AGC使能 0: 数字AGC不使能 1: 接收数据消直使能 0: 接收数据消直不使能 频率精同步和小区有效性判断控制寄存器 RSSI计算使能 输入位置滑动计算次数 0:不进行左右滑动 1:左右分别滑动1个点 2:左右分别滑动2个点 3:左右分别滑动4个点 频率精同步和小区有效性判断计算点数 取值范围为1~12 频率精同步时，PSS与SSS滑动相关的滑动步长M：取值为0~4 1: FDD模式 0: TDD模式 1: 频偏纠正使能 0: 频偏纠正不使能 1: 频率精同步使能 0: 频率精同步不使能 1:定时漂移使能 0:定时漂移不使能 1: 数字AGC使能 0: 数字AGC不使能 1: 接收数据消直使能 0: 接收数据消直不使能 RESYNC_CTRL重同步控制寄存器 RSSI计算使能 一个样本输入数据长度 0:1ms 1:2ms 2:3ms 3:4ms 4:5ms 00:子帧未知 01: 子帧0 10: 子帧5 最大值个数保存 取值范围1~5 ID1值 取值范围0~167 ID2值 取值范围0~2 0: 数字AGC不使能 1: 数字AGC使能 0: 输入消直以及搬数使能不使能 1: 输入消直以及搬数使能使能 频率移位控制寄存器0 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 频率移位控制寄存器1 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 频率移位控制寄存器2 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 接收数据RSSI移位值 取值范围-8~7 INT_CTRL中断控制寄存器 1:非连续接收单次计算完成断使能 0:完成状态已清除或未产生中断不使能 1: 频率盲搜1个子段搜索完成中断使能 0: 频率盲搜1个子段搜索完成中断不使能 1:RSSI值计算完成中断使能 0: RSSI值计算完成中断不使能 1:暂停中断使能 0: 暂停中断不使能 1: AXIDMA搬数错误中断使能 0: AXIDMA搬数错误中断不使能 1:TXRX接收数据暂停中断使能 0: TXRX接收数据暂停中断不使能 1:重同步完成中断使能 0:重同步完成中断不使能 1:频率精同步和小区有效性判断完成中断使能 0: 频率精同步和小区有效性判断完成中断不使能 1:SSS同步完成中断使能 0: SSS同步完成中断不使能 1:PSS精同步完成中断使能 0: PSS精同步完成中断不使能 1:PSS粗同步完成中断使能 0: PSS粗同步完成中断不使能 PSS精同步/SSS同步接收数据起始位置配置寄存器 粗同步RSSI门限值 PSS粗同步TXRX输入第一个数据的位置为0，PSS精同步和SSS同步TXRX 输入第一个数据相对0位置的值：0~19200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 SAM_NUM_CTRL 样本自适应控制寄存器 计算样本 取值范围0~200 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 样本组对应峰均比判别门限寄存器 样本组对应峰均比判别门限值1 样本组对应峰均比判别门限值0 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 PSS精同步ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 PSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 SSS ID配置寄存器 PSS粗同步计算出的每个ID对应频偏：取值范围-32768~32767 PSS粗同步计算出的每个ID对应的定时漂移：取值范围为-32~31 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)：1：子帧5 0：子帧0 SSS序列的参数 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 频率精同步和ID有效性判断 ID配置寄存器 频率精同步和小区有效性判断参数NID1 取值范围0-167 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS精同步/SSS同步/频率精同步和ID有效性判断ID位置配置寄存器 每个ID的位置 取值范围0~9599 PSS_SSS_FIND配置寄存器 SSSMAX查找半径长度： 可配置为小于10 噪声窗长度选择： 0:31 1:61 2:127 在IDDET PSS流程中，需要在过门限的最强节点的ASSIST_WIN半径内，将找出，MAX_NUM点中是否有未排在前POS_NUM的节点，如果有，把这些节点当做辅节点在最后输出，并保证这些点和POS_NUM中的节点不重复。 多径窗半径长度：2’b00:2 2’b01:4 2’b10:8 others:2 主峰与主峰的间隔半径，同时表示辅峰查找范围半径：可配置为0-127 噪声门限使能 均值的乘以此系数作为噪声门限（Q3）（有符号的非零数） PSS粗同步频偏尝试配置寄存器1 PSS粗同步频偏尝试2 移位位数取值范围-1024~1023 PSS粗同步频偏尝试1 移位位数取值范围-1024~1023 PSS粗同步频偏尝试0 移位位数取值范围-1024~1023 PSS粗同步频偏尝试配置寄存器2 PSS粗同步频偏尝试4 移位位数取值范围-1024~1023 PSS粗同步频偏尝试3 移位位数取值范围-1024~1023 PSS精同步频偏尝试配置寄存器1 PSS精同步频偏尝试 取值范围-4096~4095 PSS精同步频偏尝试配置寄存器2 PSS精同步频偏尝试 取值范围-4096~4095 PSS精同步频偏尝试配置寄存器3 PSS精同步频偏尝试 取值范围-4096~4095 PSS精同步频偏尝试配置寄存器4 PSS精同步频偏尝试 取值范围-4096~4095 RSSI目标值配置寄存器 粗同步定时偏移配置寄存器1 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS粗同步定时漂移移位值 取值范围为-32~31 粗同步定时偏移配置寄存器2 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS粗同步定时漂移移位值 取值范围为-32~31 粗同步定时偏移配置寄存器3 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS粗同步定时漂移移位值 取值范围为-32~31 粗同步定时偏移配置寄存器4 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS粗同步定时漂移移位值 取值范围为-32~31 粗同步定时偏移配置寄存器5 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS粗同步定时漂移移位值 取值范围为-32~31 PSS精同步SSS同步定时偏移增量配置寄存器 定时偏移增量 取值范围为-8~7 定时偏移增量 取值范围为-8~7 定时偏移增量 取值范围为-8~7 定时偏移增量 取值范围为-8~7 FFT截位因子寄存器 指示 FFT/IFFT 中采用定点数截位方式一的前几级级数(干扰消除)： 4`b0000：各级都采用截位方式二； 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二； 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二； … 指示 FFT/IFFT 中采用定点数截位方式一的前几级级数（PSS/SSS同步）： 4`b0000：各级都采用截位方式二； 4`b0001：第一级采用截位方式一，后面几级都采用截位方式二； 4`b0010：第一、二级采用截位方式一，后面几级都采用截位方式二； … 干扰消除的ID配置寄存 干扰小区频偏纠正使能 1：使能 0：不使能 干扰小区频偏纠正因子 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 SSS序列的参数 SSS序列的参数 IC_CFG配置寄存器 干扰小区定时漂移因子 SSS同步时的干扰消除首位置： 在9600点中的位置 截位因子 0：不移位 1：右移1位 2：右移2位 … -1：左移1位 -2：左移2位 … ID频率精同步输出寄存器 0 频率精同步输出结果0 PSS粗同步、PSS精同步、SSS同步过门限有效个数寄存器 SSS同步过门限送给小区有效性判断个数 0：前0个输出有效 1：前1个输出有效 … 12：前12个输出有效 PSS粗同步、PSS精同步、SSS同步过门限有效个数 0：前0个输出有效 1：前1个输出有效 … 12：前12个输出有效 计算样本总数寄存器 PSS粗同步、PSS精同步、SSS同步、频率精同步和小区有效性判断计算结束时使用的样本总数 取值范围0~200 RSSI值输出寄存器 PSS粗同步滑动RSSI值，PSS精同步、SSS同步、频率精同步和小区有效性判断第一个 位置RSSI值 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 SSS IDDET模式下排序后存放位置索引 取值范围0~11 无线帧同步、频率精同步偏移位置 取值范围0-8 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 功率噪声输出寄存器 PSS粗同步、PSS精同步、SSS同步输出噪声 PSS粗同步、PSS精同步、SSS同步输出功率 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 位置输出寄存器 频偏尝试值 PSS粗同步、PSS精同步、SSS同步输出ID位置 ID信息输出寄存器 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 ID信息输出寄存器 定时漂移尝试值 NID1值 取值范围0-167 ID对应的CP类型： 1：EXTEND CP 0：NORMAL CP ID对应的子帧号(SSS本地信号产生使用)： 1：子帧5 0：子帧0 NID2值 取值范围0-2 INT_FLAG标志寄存器 1:非连续接收单次计算完成 0:完成状态已清除或未产生 1:频率盲搜所有子带以及所有频段搜索完成 0:完成状态已清除或未产生 1:频率盲搜1个子段搜索完成 0:完成状态已清除或未产生 1:RSSI值计算完成 0: RSSI值计算完成状态已清除或未产生 1:暂停完成 0: 暂停状态已清除或未产生 1:AXIDMA未能及时搬数产生错误 0:错误状态已清除或未产生 1:TXRX接收数据暂停 0:暂停状态已清除或未产生 1:重同步完成 0: 完成状态清除或未完成 1:频率精同步和小区有效性判断完成 0:完成状态清除或未完成 1:SSS同步完成 0:完成状态清除或未完成 1:PSS精同步完成 0:完成状态清除或未完成 1:PSS粗同步完成 0:完成状态清除或未完成 IDDET状态寄存器 频点状态指示 1：正在进行 0：未启动或已经结束 重同步状态指示 1：正在进行 0：未启动或已经结束 频率精同步和小区有效性判断状态指示 1：正在进行 0：未启动或已经结束 无线帧同步状态指示 1：正在进行 0：未启动或已经结束 PSS精同步状态指示 1：正在进行 0：未启动或已经结束 PSS粗同步状态指示 1：正在进行 0：未启动或已经结束 软件使用寄存器 前次计算样本个数寄存器 前次计算样本个数 0~1023 频率盲搜控制寄存器 0:使用功率排序 1:使用功率窗比值排序 单独FFT使能： 0: 单独FFT不使能 1: 单独FFT(固定1024点)使能,且只做一次FFT，就结束 单独排序使能: 0: 单独排序不使能 1: 单独排序使能,且只做排序，就结束 排序的结束地址1~999 排序的起始地址0~999 接收数据频率选择 0: 5M 1: 10M 2: 20M 其他: 5M 0: 不是最后5ms数据 1: 最后5ms数据 0: 不是首个5ms数据 1: 首个5ms数据 频率盲搜配置寄存器1 功率窗比值时的截位因子配置; 0:截取[19:0],进行保护为20bit的功率 1:截取[20:1],进行保护为20bit的功率 …… 12:截取[31:12],进行保护为20bit的功率 其他:同12的配置; 接收的数据频域计算之后,功率的截位因子配置;I^2+Q^2=PWR(32bit) 0:截取[31:15],进行保护为16bit的功率 1:截取[31:14],进行保护为16bit的功率 …… 15:截取[31:0],进行保护为16bit的功率 当前频段的子带编号 取值范围0~49 当前频段的子带总数 取值范围0~50 20MHz功率窗比值计算使能 0: 不使能 1: 使能 15MHz功率窗比值计算使能 0: 不使能 1: 使能 10MHz功率窗比值计算使能 0: 不使能 1: 使能 5MHz功率窗比值计算使能 0: 不使能 1: 使能 3MHz功率窗比值计算使能 0: 不使能 1: 使能 1.4MHz功率窗比值计算使能 0: 不使能 1: 使能 200KHz功率窗比值计算使能 0: 不使能 1: 使能 功率谱滑动平均窗长,取值为1~11 频率盲搜配置寄存器2 Selectbinnum右边配置，0~511 selectbinnum左边配置，0~511 功率窗比值带宽表START值配置寄存器1 取值范围0~99 取值范围0~99 取值范围0~99 取值范围0~99 功率窗比值带宽表START值配置寄存器2 取值范围0~99 取值范围0~99 取值范围0~99 功率窗比值带宽表END值配置寄存器1 取值范围0~15 取值范围0~15 取值范围0~15 取值范围0~15 取值范围0~15 取值范围0~15 取值范围0~15 功率窗比值带宽表END值配置寄存器2 AGC配置寄存器 取值范围0~127 硬件已经计算的子带的总长度寄存器 当前频段的子带中，硬件已经计算的子带的长度的和值 硬件已经计算的子带的目标AGC寄存器 当前频段的子带中，硬件已经计算的子带的目标AGC ID频率精同步输出寄存器 1 频率精同步输出结果2 频率精同步输出结果1 PSS1_RESYN_CTRL粗同步重同步RSSI计算范围配置寄存器 PSS粗同步、重同步RSSI计算范围结束值，粗同步取值范围：0~4799，重同步取值范围：0~9599 PSS粗同步、重同步RSSI计算范围起始值，粗同步取值范围：0~4799，重同步取值范围：0~9599 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 位置输出寄存器 PSS粗同步最大值RSSI值 1、 PSS粗同步、重同步功率； 2、 PSS粗同步、重同步RSSI值 1、 PSS精同步功率 2、 SSS同步功率 频率精同步和小区有效性判断功率 QF值保存 非乒乓模式MEM1-8 乒乓模式MEM1-11 RF输入数据导出（只读） 用于存放频率盲搜中，每个子带的AGC拉齐之前的功率 第1个子带的PWR1 第1个子带的PWR0 用于存放频率盲搜中，每个子带的长度以及AGC值 第1个子带的长度 第1个子带的AGC CSI启动寄存器 data_drive模式使能。 0：非data_drive 1：data_drive DMA启动CSI模块的使能。 0：不使能 1：使能 CSI模块使能信号。 0：不使能 1：使能 下个子帧的CSI配置寄存器 cp指示。 0：常规 1：扩展 FH输出截位方案。 5’d0：截取fh[11:0] 5’d1：截取fh[12:1] 5’d2：截取fh[13:2] …… 5’d16：截取fh[27:16] others：截取fh[28:17] CSI-RS和CRS的指示。 0：CSI-RS 1：CRS LS/FH/功率计算使能信号。 0：不使能，不计算LS/FH/功率 1：使能，要计算 软件配置的宽带RI，在ri_sel=1时用来计算PMI。 0：RI=1 1：RI=2 计算PMI所用的RI的来源选择。 0：使用硬件计算的宽带RI 1：使用软件配置的RI PMI估算使能信号。 0：不使能，不计算PMI 1：使能，要计算PMI RI估算使能信号。 0：不使能，不计算RI 1：使能，要计算RI 估算RI时是否使用RI历史值的指示。 0：不使用历史值，默认为RI=1 1：使用上个周期的宽带RI值 系统带宽。取值6/15/25/50/75/100PRB 子带带宽。与系统带宽一一对应。total_nrb=6/15/25/50/75/100时，sub_nrb=6/2/2/3/4/4 PRB。 发射天线数。CSI-RS可配置1、2、4、8天线，CRS可配置2、4天线。 0：1天线（只计算功率，不计算RI和PMI） 1：2天线 2：4天线 3：8天线 下个子帧的RI估计门限寄存器 〖((1-th2)/(1+th2))〗^2的值。估计RI时使用的判决门限，取值为大于0小于1的小数。用Q15表示。th2的典型值为40。 〖((1-th1)/(1+th1))〗^2的值。估计RI时使用的判决门限，取值为大于0小于1的小数。用Q15表示。th1的典型值为60。 下个子帧的码本索引寄存器1 RI=2时的2、4天线的码本索引号及8天线的码本索引号i1的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 RI=1时的2、4天线的码本索引号及8天线的码本索引号i1的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 下个子帧的码本索引寄存器2 RI=2时的8天线的码本索引号i2的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 RI=1时的8天线的码本索引号i2的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 下个子帧的中断使能寄存器 物理层主卡标志位 处理完成中断使能。 0：不使能 1：使能 下个子帧的OFDM0的C序列初始值寄存器 OFDM符号0的C序列的初始值，用来计算本地CSI-RS。 下个子帧的OFDM1的C序列初始值寄存器 OFDM符号1的C序列的初始值，用来计算本地CSI-RS。 中断标志寄存器 模块主卡标志输出 处理完成中断标志。 0：未处理完 1：处理完成 软件暂停和停止使能寄存器 当sw_pause_en=1时，软件暂停硬件的策略选择。 0：在开始处理之前暂停 1：在子帧处理结束之后暂停 软件暂停硬件的使能。 0：不暂停 1：暂停，硬件完成当前子帧处理后或开始处理之前，暂停处理，等该使能置为0后再继续 软件停止硬件的使能。 0：不停止 1：停止，硬件在处理子帧前或完成当前子帧处理后，停止处理 软件暂停和停止标志寄存器 软件暂停硬件标志。 0：软件未成功暂停硬件 1：软件成功暂停硬件 软件停止硬件标志。 0：软件未成功停止硬件 1：软件成功停止硬件 宽带RI上报寄存器 系统带宽内总的RI，即对所有PRB的RI按多数原则统计得到的值。 0：RI=1 1：RI=2 宽带PMI上报寄存器 系统带宽内总的PMI，即对所有PRB的PMI按多数原则统计得到的值 接收天线1的宽带信号功率上报寄存器 接收天线1的宽带信号功率和，即对所有子带信号功率累加得到。 接收天线2的宽带信号功率上报寄存器 接收天线2的宽带信号功率和，即对所有子带信号功率累加得到。 接收天线1的宽带噪声功率上报寄存器 接收天线1的宽带噪声功率和，即对所有子带噪声功率累加得到。 接收天线2的宽带噪声功率上报寄存器 接收天线2的宽带噪声功率和，即对所有子带噪声功率累加得到。 当前处理子帧的CSI配置寄存器 cp指示。 0：常规 1：扩展 FH输出截位方案。 5’d0：截取fh[11:0] 5’d1：截取fh[12:1] 5’d2：截取fh[13:2] …… 5’d16：截取fh[27:16] others：截取fh[28:17] CSI-RS和CRS的指示。 0：CSI-RS 1：CRS LS/FH/功率计算使能信号。 0：不使能，不计算LS/FH/功率 1：使能，要计算 软件配置的宽带RI，在ri_sel=1时用来计算PMI。 0：RI=1 1：RI=2 计算PMI所用的RI的来源选择。 0：使用硬件计算的宽带RI 1：使用软件配置的RI PMI估算使能信号。 0：不使能，不计算PMI 1：使能，要计算PMI RI估算使能信号。 0：不使能，不计算RI 1：使能，要计算RI 估算RI时是否使用RI历史值的指示。 0：不使用历史值，默认为RI=1 1：使用上个周期的宽带RI值 系统带宽。取值6/15/25/50/75/100PRB 子带带宽。与系统带宽一一对应。total_nrb=6/15/25/50/75/100时，sub_nrb=6/2/2/3/4/4 PRB。 发射天线数。CSI-RS可配置1、2、4、8天线，CRS可配置2、4天线。 0：1天线（只计算功率，不计算RI和PMI） 1：2天线 2：4天线 3：8天线 当前处理子帧的RI估计门限寄存器 〖((1-th2)/(1+th2))〗^2的值。估计RI时使用的判决门限，取值为大于0小于1的小数。用Q15表示。th2的典型值为40。 〖((1-th1)/(1+th1))〗^2的值。估计RI时使用的判决门限，取值为大于0小于1的小数。用Q15表示。th1的典型值为60。 当前处理子帧的码本索引寄存器1 RI=2时的2、4天线的码本索引号及8天线的码本索引号i1的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 RI=1时的2、4天线的码本索引号及8天线的码本索引号i1的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 当前处理子帧的码本索引寄存器2 RI=2时的8天线的码本索引号i2的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 RI=1时的8天线的码本索引号i2的bitmap。bit0~bit15分别对应索引号0~15，为“1”的比特位对应的索引号有效，需要计算该索引对应的预编码矩阵。 当前处理子帧的中断使能寄存器 处理完成中断使能。 0：不使能 1：使能 当前处理子帧的OFDM0的C序列初始值寄存器 OFDM符号0的C序列的初始值，用来计算本地CSI-RS。 当前处理子帧的OFDM1的C序列初始值寄存器 OFDM符号1的C序列的初始值，用来计算本地CSI-RS。 参数寄存器 本地序列长度：max384 接收数据长度：max2800 ID个数：max10 启动寄存器 模块启动： 1：启动 0：未启动或者已经完成 结果输出寄存器 输出的相关值在乒或者乓： 0：乒 1：乓 最大位置：max：2800 最大ID：max10 MAX输出寄存器 CORR_MAX SUM输出寄存器 中断使能寄存器 中断使能： 0：中断不使能 1：中断使能 中断标志寄存器 中断标志： 0：没有中断 1：产生中断 配置寄存器 使能位 0：不使能 1：使能 配置寄存器 启动抓Dump数据 1：启动 0：不启动 启动抓Tx Trace数据 1：启动 0：不启动 启动抓IDDET offline输入口数据 1：启动 0：不启动 启动抓ODTOA数据 1：启动 0：不启动 启动抓RX输入口数据 1：启动 0：不启动 灌数配置寄存器 灌数长度 启动DL offline灌数 1：启动 0：不启动 分频参数，用于生成灌数输出数据 3’h0:4分频（对应20M/15M带宽） 3’h1:8分频（对应10M带宽） 3’h2:16分频（对应5M带宽） 3’h3:32分频（对应3M带宽） 3’h4:64分频（对应1.4M带宽） Others: 4分频 灌数配置寄存器2 灌数长度 启动IDDET offline灌数 1：启动 0：不启动 分频参数，用于生成灌数输出数据 3’h0:4分频（对应20M/15M带宽） 3’h1:8分频（对应10M带宽） 3’h2:16分频（对应5M带宽） 3’h3:32分频（对应3M带宽） 3’h4:64分频（对应1.4M带宽） Others: 4分频 请求DMA搬数使能寄存器 DMA_req7使能 1：使能 0：不使能 DMA_req6使能 1：使能 0：不使能 DMA_req5使能 1：使能 0：不使能 DMA_req4使能 1：使能 0：不使能 DMA_req3使能 1：使能 0：不使能 DMA_req2使能 1：使能 0：不使能 DMA_req1使能 1：使能 0：不使能 DMA_req0使能 1：使能 0：不使能 中断使能寄存器 Capt_err34中断使能、 1：使能 0：不使能 Capt_err12中断使能、 1：使能 0：不使能 Mem56 finish中断使能、 1：使能 0：不使能 Mem56 pang中断使能 1：使能 0：不使能 Mem56 ping中断使能 1：使能 0：不使能 Mem34 finish中断使能、 1：使能 0：不使能 Mem34 pang中断使能 1：使能 0：不使能 Mem34 ping中断使能 1：使能 0：不使能 Mem12 finish中断使能、 1：使能 0：不使能 Mem12 pang中断使能 1：使能 0：不使能 Mem12 ping中断使能 1：使能 0：不使能 中断使能置位寄存器 Capt_err34中断使能、 1：使能 0：不使能 Capt_err12中断使能、 1：使能 0：不使能 Mem56 finish中断使能、 1：使能 0：不使能 Mem56 pang中断使能 1：使能 0：不使能 Mem56 ping中断使能 1：使能 0：不使能 Mem34 finish中断使能、 1：使能 0：不使能 Mem34 pang中断使能 1：使能 0：不使能 Mem34 ping中断使能 1：使能 0：不使能 Mem12 finish中断使能、 1：使能 0：不使能 Mem12 pang中断使能 1：使能 0：不使能 Mem12 ping中断使能 1：使能 0：不使能 中断使能清零寄存器 Capt_err34中断使能、 1：使能 0：不使能 Capt_err12中断使能、 1：使能 0：不使能 Mem56 finish中断使能、 1：使能 0：不使能 Mem56 pang中断使能 1：使能 0：不使能 Mem56 ping中断使能 1：使能 0：不使能 Mem34 finish中断使能、 1：使能 0：不使能 Mem34 pang中断使能 1：使能 0：不使能 Mem34 ping中断使能 1：使能 0：不使能 Mem12 finish中断使能、 1：使能 0：不使能 Mem12 pang中断使能 1：使能 0：不使能 Mem12 ping中断使能 1：使能 0：不使能 中断状态寄存器 Capt_err34中断 Capt_err12中断 Mem56 finish中断状态 Mem56 pang中断状态 Mem56 ping中断状态 Mem34 finish中断状态 Mem34 pang中断状态 Mem34 ping中断状态 Mem12 finish中断状态、 Mem12 pang中断状态 Mem12 ping中断状态 MEM12中断配置寄存器 Mem12中断配置寄存器 MEM34中断配置寄存器 Mem34中断配置寄存器 MEM12中断配置寄存器 Mem12中断配置寄存器 MEM56中断配置寄存器 Mem56中断配置寄存器 通用控制寄存器 MEM12当前状态寄存器 Mem12 pang读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem12 pang地址 Mem12 ping读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem12 ping地址 MEM34当前状态寄存器 Mem34 pang读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem34 pang地址 Mem34 ping读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem34 ping地址 MEM56当前状态寄存器 Mem56 pang读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem56 pang地址 Mem56 ping读写状态 000：IDLE 001：往MEM灌数据 010：MEM被灌满，没搬出 011：DMA搬数据 100：MEM被搬空 Others: IDLE Mem56 ping地址 抓数EER12状态寄存器 抓数Err的存储器 0：MEM12 Ping 1：MEM12 Pang 抓数Error时的帧号(发生抓数ERR时锁存的帧号 抓数EER34状态寄存器 抓数Err的存储器 0：MEM34 Ping 1：MEM34 Pang 抓数Error时的帧号(发生抓数ERR时锁存的帧号 抓数状态寄存器 otdoa_sta 00：未运行抓数功能 01：正抓取OTDOA 10：硬件finish信号结束抓数 11：软件清capt_cfg使能位结束抓数 iddet_sta 00：未运行抓数功能 01：正抓取IDDET 10：硬件finish信号结束抓数 11：软件清capt_cfg使能位结束抓数 tx_sta 00：未运行抓数功能 01：正抓取TX 10：硬件finish信号结束抓数 11：软件清capt_cfg结束使能位结束抓数 dump_sta 00：未运行抓数功能 01：正抓取DUMP 10：硬件finish信号结束抓数 11：软件清capt_cfg使能位结束抓数 rx_sta 00：未运行抓数功能 01：正抓取RX 10：硬件finish信号结束抓数 11：软件清capt_cfg使能位结束抓数 DL offline灌数状态寄存器1 fill_running_sta 00：未运行灌数功能 01：正灌数 10：硬件搬完len结束灌数 11：软件清fill_cfg使能位结束灌数 out_len 当前HW吐出数据长度（I/Q对数） DL offline灌数状态寄存器2 in_len 当前DMA搬入数据长度（I/Q对数） IDDET offline灌数状态寄存器1 fill_running_sta 00：未运行灌数功能 01：正灌数 10：硬件搬完len结束灌数 11：软件清fill_cfg使能位结束灌数 out_len 当前HW吐出数据长度（I/Q对数） IDDET offline灌数状态寄存器2 in_len 当前DMA搬入数据长度（I/Q对数） DMA状态寄存器 DMA_ACK DMA_REQ AUXADC IP version AUXADC IP version IP version r7p0 ADC ctrl information configure ADC ctrl information configure Auxadc offset function enable 0: disable offset function 1: enable offset function auxadc convert data out average control: 000: disable adc average, output 12bit data and valid after once conversion; 001: adc convert twice and output the average data; 010: adc convert 4 times and output the average data; 011: adc convert 8 times and output the average data; 100: adc convert 16 times and output the average data; 101: adc convert 32 times and output the average data; 110: adc convert 64 times and output the average data; 111: adc convert 128 times and output the average data; the number of SW channel accessing, N+1. AUXADC output code selection: 0: adc_dout = (data-Doff) 1: if adc_offset_cal_en is 0 adc_dout = data if adc_offset_cal_en is 1 adc_dout = data-(Doff-2047) more detail see Function Description ADC 12bits mode 0: ADC in 10bits mode; 1: ADC in 12bits mode. SW channel run, Write '1' to run a SW channel accessing, it is cleared by HW. ADC global enable, 0: ADC module disable; 1: ADC module enable. ADC SW channel configure ADC SW channel configure ADC scale setting for current ADC channel ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC software config channel ID. ADC fast HW channel0 configure ADC fast HW channel0 configure ADC scale setting for current ADC channel current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel1 configure ADC fast HW channel1 configure ADC scale setting for current ADC channel current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel2 configure ADC fast HW channel2 configure ADC scale setting for current ADC channel current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel3 configure ADC fast HW channel3 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel4 configure ADC fast HW channel4 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel5 configure ADC fast HW channel5 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel6 configure ADC fast HW channel6 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC fast HW channel7 configure ADC fast HW channel7 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel0 configure ADC slow HW channel0 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel1 configure ADC slow HW channel1 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel2 configure ADC slow HW channel2 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel3 configure ADC slow HW channel3 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel4 configure ADC slow HW channel4 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel5 configure ADC slow HW channel5 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel6 configure ADC slow HW channel6 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC slow HW channel7 configure ADC slow HW channel7 configure output the analog current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC HW channel accessing dealy ADC HW channel accessing dealy ADC HW channel accessing delay, its unit is ADC clock. It can be use for signal without enough setup time. ADC conversion result ADC conversion result ADC conversion result. ADC interrupt enable ADC interrupt enable ADC interrupt enable, 0: disable; 1: enable. ADC interrupt clear ADC interrupt clear ADC interrupt clear. Write "1" to clear. ADC masked interrupt ADC masked interrupt ADC masked interrupt. ADC raw interrupt ADC raw interrupt ADC raw interrupt. ADC debug information ADC debug information 0~7: fast HW channels; 8: SW channels; 9~16: slow HW channel; 31: no request. ADC accessing state: 0: idle; 1: fast HW request; 2: SW request; 3: slow HW request; 4: wait for fast HW request; 5: wait for slow HW request. ADC internal counter status, 0: idle; 1~n: work or wait counter. ADC fast HW channel timer enable ADC fast HW channel timer enable ADC fast HW channel7 timer enable, 0:disable; 1: enable. ADC fast HW channel6 timer enable, 0:disable; 1: enable. ADC fast HW channel5 timer enable, 0:disable; 1: enable. ADC fast HW channel4 timer enable, 0:disable; 1: enable. ADC fast HW channel3 timer enable, 0:disable; 1: enable. ADC fast HW channel2 timer enable, 0:disable; 1: enable. ADC fast HW channel1 timer enable, 0:disable; 1: enable. ADC fast HW channel0 timer enable, 0:disable; 1: enable. ADC fast HW channel timer working clock divider ADC fast HW channel timer working clock divider ADC fast HW channel timer working clock divider. ADC fast HW channel0 timer threshold ADC fast HW channel0 timer threshold ADC fast HW ch0 timer threshold. ADC fast HW channel1 timer threshold ADC fast HW channel1 timer threshold ADC fast HW ch1 timer threshold. ADC fast HW channel2 timer threshold ADC fast HW channel2 timer threshold ADC fast HW ch2 timer threshold. ADC fast HW channel3 timer threshold ADC fast HW channel3 timer threshold ADC fast HW ch3 timer threshold. ADC fast HW channel4 timer threshold ADC fast HW channel4 timer threshold ADC fast HW ch4 timer threshold. ADC fast HW channel5 timer threshold ADC fast HW channel5 timer threshold ADC fast HW ch5 timer threshold. ADC fast HW channel6 timer threshold ADC fast HW channel6 timer threshold ADC fast HW ch6 timer threshold. ADC fast HW channel7 timer threshold ADC fast HW channel7 timer threshold ADC fast HW ch7 timer threshold. ADC fast HW channel0 data ADC fast HW channel0 data ADC fast HW ch0 data, read twice, and capture the second value. ADC fast HW channel1 data ADC fast HW channel1 data ADC fast HW ch1 data, read twice, and capture the second value. ADC fast HW channel2 data ADC fast HW channel2 data ADC fast HW ch2 data, read twice, and capture the second value. ADC fast HW channel3 data ADC fast HW channel3 data ADC fast HW ch3 data, read twice, and capture the second value. ADC fast HW channel4 data ADC fast HW channel4 data ADC fast HW ch4 data, read twice, and capture the second value. ADC fast HW channel5 data ADC fast HW channel5 data ADC fast HW ch5 data, read twice, and capture the second value. ADC fast HW channel6 data ADC fast HW channel6 data ADC fast HW ch6 data, read twice, and capture the second value. ADC fast HW channel7 data ADC fast HW channel7 data ADC fast HW ch7 data, read twice, and capture the second value. ADC NTC ctrl information ADC NTC ctrl information output to analog output to analog THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration output to analog Aux ADC current sense enable signal, active high, default 0. ADC fast HW channel data valid ADC fast HW channel data valid ADC fast HW channel7 data valid. ADC fast HW channel6 data valid. ADC fast HW channel5 data valid. ADC fast HW channel4 data valid. ADC fast HW channel3 data valid. ADC fast HW channel2 data valid. ADC fast HW channel1 data valid. ADC fast HW channel0 data valid. BLTC control 1. BLTC output select 2. BLTC output select(1: output by SW, 0: output by HW); 3. BLTC output type select (1: normal PWM, 0: breath light); 4, BLTC run enable signal BLTC WLED output value when by SW. BLTC WLED output selection BLTC WLED output type BLTC WLED run BLTC B output value when by SW. BLTC B output selection BLTC B output type BLTC B run BLTC G output value when by SW. BLTC G output selection BLTC G output type BLTC G run BLTC R output value when by SW. BLTC R output selection BLTC R output type BLTC R run BLTC R prescale coefficient PWM prescale coefficient for work clock. BLTC prescale coefficient. BLTC R duty config PWM duty config. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. BLTC R rise/fall config BLTC R rise/fall config Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. BLTC R high/low config BLTC R high/low config Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC G prescale coefficient PWM prescale coefficient for work clock. BLTC prescale coefficient. BLTC G duty config PWM duty config. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. BLTC G rise/fall config BLTC G rise/fall config Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. BLTC G high/low config BLTC G high/low config Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC B prescale coefficient PWM prescale coefficient for work clock. BLTC prescale coefficient. BLTC B duty config PWM duty config. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. BLTC B rise/fall config BLTC B rise/fall config Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. BLTC B high/low config BLTC B high/low config Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC status BLTC status BLTC WLED busy, active high. BLTC B busy, active high. BLTC G busy, active high. BLTC R busy, active high. BLTC R current strength config. BLTC current strength config. Current strength config. BLTC G current strength config. BLTC current strength config. Current strength config. BLTC B current strength config. BLTC current strength config. Current strength config. BLTC WLED current strength config. BLTC current strength config. Current strength config. BLTC WLED prescale coefficient PWM prescale coefficient for work clock. BLTC prescale coefficient. BLTC WLED duty config PWM duty config. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. BLTC WLED rise/fall config BLTC WLED rise/fall config Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. BLTC WLED high/low config BLTC WLED high/low config Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC current strength config. BLTC current strength config. Power down signal Power down signal BLTC version BLTC WLED high/low config bltc version information efuse global control register Control efs_clk gate 1: gate efs_clk Efuse type select, 00:TSMC default Efuse SW programme enable Data read from efuse memory Efuse read data, If SW use efuse controller to send a read command to efuse memory, the return value will store here. Data to be write to efuse memory Efuse data to be write. If SW want to program the efuse memory, the data to be programmed will write to this register before SW issue a PGM command. block index for read, program The efuse memory block index to be read or write. Mode control of efuse memory Write 1 to this bit will clear normal read flag.This bit is self-clear, read this bit will always get 0 Write 1 to this bit start READ mode(read mode).This bit is self-clear, read this bit will always get 0 Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0 Efuse controller internal status “1” indicate EFUSE normal read has been done If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1. “1” indicate efuse memory in standby mode “1” indicate efuse memory in read mode “1” indicate efuse memory in programming mode magic number to protect efuse from un-intentionally programming Magic number, only when this field is 0x7520, the Efuse programming command can be handle. So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : a) PGM_EN =1; b) EFUSE_MAGIC_NUMBER = 0x7520 magic number to protect efuse from un-intentionally programming Magic number, only when this field is 0x6688, the margin read is usable. Write command timing control Config this register to control the timing of writing operation related signals Read command timing control Config this register to control the timing of writing operation related signals EFUSE control version registers Efuse control version register EFUSE POR READ BLK00 should be the efuse macro value EFUSE POR READ BLK01 should be the efuse macro value EFUSE POR READ BLK02 should be the efuse macro value EFUSE POR READ BLK03 should be the efuse macro value EFUSE POR READ BLK04 should be the efuse macro value EFUSE POR READ BLK05 should be the efuse macro value EFUSE POR READ BLK06 should be the efuse macro value EFUSE POR READ BLK07 should be the efuse macro value EFUSE POR READ BLK08 should be the efuse macro value EFUSE POR READ BLK09 should be the efuse macro value EFUSE POR READ BLK10 should be the efuse macro value EFUSE POR READ BLK11 should be the efuse macro value EFUSE POR READ BLK12 should be the efuse macro value EFUSE POR READ BLK13 should be the efuse macro value EFUSE POR READ BLK14 should be the efuse macro value EFUSE POR READ BLK15 should be the efuse macro value EFUSE POR READ BLK16 should be the efuse macro value EFUSE POR READ BLK17 should be the efuse macro value EFUSE POR READ BLK18 should be the efuse macro value EFUSE POR READ BLK19 should be the efuse macro value EFUSE POR READ BLK20 should be the efuse macro value EFUSE POR READ BLK21 should be the efuse macro value EFUSE POR READ BLK22 should be the efuse macro value EFUSE POR READ BLK23 should be the efuse macro value EFUSE POR READ BLK24 should be the efuse macro value EFUSE POR READ BLK25 should be the efuse macro value EFUSE POR READ BLK26 should be the efuse macro value EFUSE POR READ BLK27 should be the efuse macro value EFUSE POR READ BLK28 should be the efuse macro value EFUSE POR READ BLK29 should be the efuse macro value EFUSE POR READ BLK30 should be the efuse macro value EFUSE POR READ BLK31 should be the efuse macro value EFUSE POR READ BLK32 should be the efuse macro value EFUSE POR READ BLK33 should be the efuse macro value EFUSE POR READ BLK34 should be the efuse macro value EFUSE POR READ BLK35 should be the efuse macro value EFUSE POR READ BLK36 should be the efuse macro value EFUSE POR READ BLK37 should be the efuse macro value EFUSE POR READ BLK38 should be the efuse macro value EFUSE POR READ BLK39 should be the efuse macro value EFUSE POR READ BLK40 should be the efuse macro value EFUSE POR READ BLK41 should be the efuse macro value EFUSE POR READ BLK42 should be the efuse macro value EFUSE POR READ BLK43 should be the efuse macro value EFUSE POR READ BLK44 should be the efuse macro value EFUSE POR READ BLK45 should be the efuse macro value EFUSE POR READ BLK46 should be the efuse macro value EFUSE POR READ BLK47 should be the efuse macro value EFUSE POR READ BLK48 should be the efuse macro value EFUSE POR READ BLK49 should be the efuse macro value EFUSE POR READ BLK50 should be the efuse macro value EFUSE POR READ BLK51 should be the efuse macro value EFUSE POR READ BLK52 should be the efuse macro value EFUSE POR READ BLK53 should be the efuse macro value EFUSE POR READ BLK54 should be the efuse macro value EFUSE POR READ BLK55 should be the efuse macro value EFUSE POR READ BLK56 should be the efuse macro value EFUSE POR READ BLK57 should be the efuse macro value EFUSE POR READ BLK58 should be the efuse macro value EFUSE POR READ BLK59 should be the efuse macro value EFUSE POR READ BLK60 should be the efuse macro value EFUSE POR READ BLK61 should be the efuse macro value EFUSE POR READ BLK62 should be the efuse macro value EFUSE POR READ BLK63 should be the efuse macro value EIC_DBNC bits data register, read only EIC_DBNC bits data input EIC_DBNC bits data mask register EIC_DBNC_DATA register can be read if EIC_DBNC_DMSK set “1” EIC_DBNC bits interrupt status register EIC_DBNC bits interrupt status register: “1” high levels trigger interrupts, “0” low levels trigger interrupts. EIC_DBNC bits interrupt enable register EIC_DBNC bits interrupt enable register: “1” corresponding bit interrupt is enabled. “0” corresponding bit interrupt isn't enabled EIC_DBNC bits raw interrupt status register, and it reflects the status of interrupts trigger conditions detection on pins (prior to EIC_DBNC_MIS) EIC bits raw interrupt status register: “1” interrupt condition met “0” condition not met EIC_DBNC bits masked interrupt status register EIC_DBNC bits masked interrupt status register: “1” Interrupt active “0” interrupt not active EIC_DBNC_ bits interrupt clear register EIC_DBNC bits interrupt clear register: “1” clears detected interrupt. “0” has no effect. EIC_DBNC bits trig control register EIC_DBNC bits trig control register: “1”: generate the trig_start pulse “0”: no effect It must set EIC_DBNC_TRIG for using de-bounce function and getting active interrupt. EIC0_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC1_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC2_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC3_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC4_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC5_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC6_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC7_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC8_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC9_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC10_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC11_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC12_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC13_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC14_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond EIC15_DBNC control register 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the one unit is 0.977 （1000/1024） millisecond RTC second counter value RTC second counter value RTC minute counter value RTC minute counter value RTC hour counter value RTC hour counter value RTC day counter value RTC day counter value RTC second counter update RTC second counter update Write new counter value to this register to start a second counter updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC minute counter update RTC minute counter update Write new counter value to this register to start a minute counter updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC hour counter update RTC hour counter update Write new counter value to this register to start an hour counter updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC day counter update RTC day counter update Write new counter value to this register to start a day counter updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC second alarm update RTC second alarm update Write new counter value to this register to start a second alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC minute alarm update RTC minute alarm update Write new counter value to this register to start a minute alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC hour alarm update RTC hour alarm update Write new counter value to this register to start an hour alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC day alarm update RTC day alarm update Write new counter value to this register to start a day alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC interrupt enable and hour format control Day alarm updating complete interrupt enable 0: disable 1: enable Hour alarm updating complete interrupt enable Minute alarm updating complete interrupt enable Second alarm updating complete interrupt enable Day counter updating complete interrupt enable Hour counter updating complete interrupt enable Minute counter updating complete interrupt enable Second counter updating complete interrupt enable Spare register updating complete interrupt enable auxiliary alarm interrupt enable Hour format select 0: The read back hour count is formatted as 0 to 23. 1: The read back hour count is formatted as 0 to 11, and bit 4 represent AM or PM – AM is 0 and PM is 1. alarm interrupt enable day interrupt enable hour interrupt enable minute interrupt enable Second interrupt enable RTC interrupt raw status Day alarm updating complete interrupt raw status Hour alarm updating complete interrupt raw status Minute alarm updating complete interrupt raw status Second alarm updating complete interrupt raw status Day counter updating complete interrupt raw status Hour counter updating complete interrupt raw status Minute counter updating complete interrupt raw status Second counter updating complete interrupt raw status Spare register updating complete interrupt raw status auxiliary alarm interrupt raw status Reserved for debug alarm interrupt raw status day interrupt raw status hour interrupt raw status minute interrupt raw status Second interrupt raw status RTC interrupt clear Day alarm updating complete interrupt clear Write 1 to this bit to clear corresponding interrupt Hour alarm updating complete interrupt clear Minute alarm updating complete interrupt clear Second alarm updating complete interrupt clear Day counter updating complete interrupt clear Hour counter updating complete interrupt clear Minute counter updating complete interrupt clear Second counter updating complete interrupt clear Spare register updating complete interrupt clear Auxiliary alarm interrupt clear alarm interrupt clear day interrupt clear hour interrupt clear minute interrupt clear Second interrupt clear RTC interrupt masked status Day alarm updating complete interrupt masked status Hour alarm updating complete interrupt masked status Minute alarm updating complete interrupt masked status Second alarm updating complete interrupt masked status Day counter updating complete interrupt masked status Hour counter updating complete interrupt masked status Minute counter updating complete interrupt masked status Second counter updating complete interrupt masked status Spare register updating complete interrupt masked status auxiliary alarm interrupt masked status alarm interrupt masked status day interrupt masked status hour interrupt masked status minute interrupt masked status Second interrupt masked status RTC second alarm value RTC second alarm value RTC minute alarm value RTC minute alarm value RTC hour alarm value RTC hour alarm value RTC day alarm value RTC day alarm value RTC spare register value RTC spare register value RTC alarm lock register value RTC spare register update RTC spare register update Write new counter value to this register to start a spare register updating operation in VDDRTC domain. Reading this register can get recent updating value. RTC alarm lock register update Write new counter value to this register to start a register updating operation in VDDRTC domain. Reading this register can get recent updating value. Write 8’hA5 to this register to unlock alarm function, and write other data to lock alarm function. That means, software must 8’hA5 to this register to enable alarm function before using this function. RTC power flag control register RTC power flag register set RTC power flag register clear RTC power flag status RTC power flag status register RTC second auxiliary alarm update RTC second auxiliary alarm register RTC minute auxiliary alarm update RTC minute auxiliary alarm register RTC hour auxiliary alarm update RTC hour auxiliary alarm register RTC day auxiliary alarm update RTC day auxiliary alarm register RTC second counter raw value RTC second counter raw value Only for debug RTC minute counter raw value RTC minute counter raw value Only for debug RTC hour counter raw value RTC hour counter raw value Only for debug RTC second counter raw value RTC day counter raw value Only for debug the IP version of this timer the IP version of this timer the IP version of this timer the IP patch version of this timer timer load value of lower 16 bit timer load value of lower 16 bit timer load value of lower 16 bit. Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. timer load value of higher 16 bit timer load value of higher 16 bit timer load value of higher 16 bit Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. timer control register timer control register timer open bit 0: timer stops 1: timer runs timer mode select 0: one-time mode 1: period mode timer interrupt timer interrupt timer Interrupt clear Write 1 to this bit to clear interrupt timer interrupt masked status timer interrupt raw status timer interrupt enable timer counter shadow value of lower 16 bit for read timer counter shadow value of lower 16 bit for read timer counter of lower 16bit shadow value for read. This read-only register indicates current counter value. The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. timer counter shadow value of higher 16 bit for read timer counter shadow value of higher 16 bit for read timer counter of higher 16bit shadow value for read. This read-only register indicates current counter value. The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. CHIP_ID_LOW CHIP ID low 16 bits,default:a000 CHIP_ID_HIGH CHIP ID high 16 bits,default:8850 MODULE_EN0 TMR module enable 0: Disable the PCLK of timer 1: Enable the PCLK of timer BLTC module enable 0: Disable the PCLK of BLTC 1: Enable the PCLK of BLTC Efuse module enable 0: Disable the PCLK of efuse ctrl 1: Enable the PCLK of efuse ctrl AUXADC module enable 0: Disable the PCLK of AUXADC 1: Enable the PCLK of AUXADC CAL module enable 0: Disable the PCLK of CAL 1: Enable the PCLK of CAL DIG_CLK_EN0 AUXAD clock enable, the clock is connected to AUXADC converter 0: disable AUXAD_CLK 1: enable AUXAD_CLK AUXADC module work clock enable 0: disable clk_adc 1: enable clk_adc Calibration module clock source select 2'b00:RC64K 2'b01:N/A 2'b10:N/A 2'b11:N/A CLK_CAL eanble 0: disable clk_cal 1: enable clk_cal RTC_CLK_EN0 TIMER RTC clock soft enable 0: Disable the RTC clock of timer 1: Enable RTC clock of timer BLTC RTC clock soft enable 0: Disable the RTC clock of BLTC 1: Enable RTC clock of BLTC ARCH RTC clock soft enable 0: Disable the RTC clock of ARCH 1: Enable RTC clock of ARCH SOFT_RST0 BLTC soft reset Efuse soft reset Auxadc soft reset TMR soft reset CAL soft reset XTL_WAIT RGB driver power down enable in chip deep sleep mode 26MHz crystal oscillator wait cycles RG_DVDD_RESERVED1 RG_DVDD_RESERVED0 RG_DVDD_RESERVED1 VBAT_CTRL0 LDOs output selection control. (To AUXADC internal calibration) THM_OTP_CTRL OTP function enable control bit OTP threshold 3'b011: 135C, default LED_CTRL Internal resistor for sink current calibration bit selection 0: From Software Register 1: From Ememory current mode enable "0" disable (default) "1" enable (default) set current level in current mode bit3~bit1 effective, bit0 not used, 1.25/2.5/5/10/20/40/80/160uA 7step sink current adjustment for test enable signale, high effective Defautl 1'b0 sink current calibration bit. 1.25uA/step default 0000000(1.25uA) KPLED_CTRL1 KPLED LDO current limit threshold adjust: default 1'b1 Current control bit. 16 steps (default 4’b0) (0000:0.9mA 0001:1.8mA 0010:2.7mA 0011:3.6mA 0100:4.5mA 0101:5.4mA 0110:6.3mA 0111:7.2mA 1000:16.2mA 1001:22.5mA 1010:29.7mA 1011:37.8mA 1100:46.8mA 1101:56.7mA 1110:67.5mA 1111:79.2mA) KPLED LDO foldback current threshold adjust: default 1'b1 KPLED LDO stability compensation: default 2'b10 KPLED LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 KPLED LDO program bits: 100mV/step, 2.8V~3.5V; default 3.3V, 3'b101 KPLED LDO short protection power down default:0,on LDO_VBAT_CTRL1 LDO_USB current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_USB short protect EN: “0” is disable “1” is enable(default) LDO_USB short current threshold adjust default 1'b1 LDO_USB compensation capacitor and resistor adjust LDO_USB discharge en LDO_VBAT_CTRL2 LDO_VIO33 current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_VIO33 short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_VIO33 compensation capacitor and resistor adjust LDO_VIO33 discharge en LDO_CAMA current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_CAMA short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_CAMA compensation capacitor and resistor adjust LDO_CAMA discharge en LDO_VBAT_CTRL3 LDO_LCD current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_LCD short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_LCD compensation capacitor and resistor adjust LDO_LCD discharge en LDO_MMC current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_MMC short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_MMC compensation capacitor and resistor adjust LDO_MMC discharge en LDO_ANA_CTRL LDO_ANA current limit threshold adjust default 1'b0 LDO_ANA short protect EN: “1” is disable “0” is enable(default) LDO_ANA short current threshold adjust default 1'b0 LDO_ANA compensation capacitor and resistor adjust LDO_ANA bypass application: default 1'b0, no bypass 1'b1, bypass ANA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 ANA LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step LDO_VIO18_CTRL LDO_VIO18 current limit threshold adjust default 1'b0 LDO_VIO18 short protect EN: “0” is disable “1” is enable(default) LDO_VIO18 short current threshold adjust default 1'b1 LDO_VIO18 compensation capacitor and resistor adjust LDO_VIO18 bypass application: default 1'b0, no bypass 1'b1, bypass VIO18 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 VIO18 LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step LDO_VGEN_CTRL1 LDO_MEM current limit threshold adjust default 3'b011 111~000 380mA~240mA 20mA/step LDO_MEM short protect EN: “0” is disable “1” is enable(default) LDO_MEM short current threshold adjust default 1'b1 LDO_MEM compensation capacitor and resistor adjust LDO_MEM bypass application: default 1'b0, no bypass 1'b1, bypass MEM LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 MEM LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step LDO_SPIMEM_CTRL LDO_SPIMEM current limit threshold adjust default 1'b0 LDO_SPIMEM short protect EN: “1” is disable “0” is enable(default) LDO_SPIMEM short current threshold adjust default 1'b0 LDO_SPIMEM compensation capacitor and resistor adjust LDO_SPIMEM bypass application: default 1'b0, no bypass 1'b1, bypass SPIMEM LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 SPIMEM LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step LDO_CAMD_CTRL LDO_CAMD current limit threshold adjust default 1'b011 111~000 380mA~240mA 20mA/step LDO_CAMD short protect EN: “0” is disable “1” is enable(default) LDO_CAMD short current threshold adjust default 1'b1 LDO_CAMD compensation capacitor and resistor adjust LDO_CAMD bypass application: default 1'b0, no bypass 1'b1, bypass CAMD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 VIO18 LDO output voltage select 000000~111111 1.4V~2.1875V 12.5mV/step LDO_RF15_CTRL LDO_RF15 current limit threshold adjust default 1'b0 LDO_RF15 short protect EN: “1” is disable “0” is enable(default) LDO_RF15 short current threshold adjust default 1'b0 LDO_RF15 compensation capacitor and resistor adjust LDO_RF15 bypass application: default 1'b0, no bypass 1'b1, bypass LDO RF15 remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 RF15 LDO output voltage select 000000~111111 1.4V~1.8875V 12.5mV/step LDO_VGEN_CTRL3 LDO_LP18_CTRL LDO_LP18 current limit threshold adjust default 1'b011 111~000 380mA~240mA 20mA/step LDO_LP18 short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_LP18 compensation capacitor and resistor adjust LDO_LP18 discharge en LDO_LP18_RF12_CTRL LDO_RF12 current limit threshold adjust default 1'b0 LDO_RF12 short protect EN: “1” is disable “0” is enable(default) LDO_RF12 short current threshold adjust default 1'b0 RF12 LDO output voltage select 000000~111111 0.8125~1.6V 12.5mV/step LDO_RF12 compensation capacitor and resistor adjust LDO_RF12 bypass application: default 1'b0, no bypass 1'b1, bypass RF12 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 DCDC_CTRL1 DCDC to AUXADC trim channel selection 3'b001: select VCORE 3'b010: select VRF (VRF*18/37) 3'b011: select VPA (VPA*18/68) RG_DCDC_AUXTRIM_SEL[2], internal test mode select: 0: default, internal test mode disable 1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path 3'b100: enpwm_vrf 3'b101: zx_vrf 3'b110: enpwm_vcore 3'b111: zx_vcore test mode control. 1'b0: default, clock output off 1'b1: clock output on phase shift option 1'b0: default, w/i 1/5 phase shift at internal mode 1'b1: uni-phase mode, all ouputs = channel 0 clock selection for each channel RG_CLKOUT_SEL[0]: VCORE clk selection RG_CLKOUT_SEL[1]: VGEN clk selection RG_CLKOUT_SEL[2]: VRF clk selection RG_CLKOUT_SEL[3]: VPA clk selection 0: internal mode, default 1: external mode VCORE_CTRL2 anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense average ratio current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% VCORE_CTRL3 force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x VRF_CTRL0 anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense average ratio current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% VRF_CTRL1 force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x VGEN_CTRL2 soft reset of all dcdc generated clk anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% VGEN_CTRL3 force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode reserved PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x CHGR_CTRL1 Select charger CC mode enable, high effective, Default “0” Battery charging end voltage 00: Vend=4.2V 01: Vend=4.3V 10: Vend=4.4V 11: Vend=4.5V (default 2’b00) Termination charger current programmable bits 00:cc*0.9 01:cc*0.4 10:cc*0.2 11:cc*0.1 control bits of over voltage protection for VCHG. When VCHG is above some level set by these 2 bits, charger power down and CHGR_OVI becomes high. 00: 6.0V 01: 6.5V 10: 7.0V 11: 9.7V Default 2’b01 CC mode charging current 0000:300mA 0001 : 350 0010: 400mA 0011 : 450 0100: 500mA 0101 :550 0110: 600mA 0111: 650 1000: 700mA 1001: 750 1010: 800mA 1011: 900 1100: 1000mA 1101: 1100 1110: 1200mA 1111: 1300 Default4’b0 AUXADC_CTRL THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration Aux ADC current sense enable signal, active high, default 0. AUX ADC channel ATE test scan mode control. 1 for ATE test channel scan, 0 for normal work. For ATE test channel scan, set this reg to 1, and using AUXAD_CS[4:0] to scan channel. AUXADC signal VSS selection, 0: share signal VSS ball with all analog circuit 1: use specific ground ball as signal VSS AUXADC reference source selection, 0: from bandgap current generate internal reference (default) 1: from bandgap voltage reference directly. AUXADC output code selection 0: output ADC 12 bit code with 11bit resolution.(default) 1: output ADC 12 bit original raw measured code. CHGR_STATUS Charging port of NON-DCP status “1” Charging port is NON-DCP “0” Charging port is not NON-DCP Charging detect done after charger insert once The output of the comparator of DCD detection or SDP/NON-DCP detection “1” means DCD pass when doing DCD, or SDP if CHG_DET=0 “0” means DCD fail when doing DCD, or NON-DCP if CHG_DET=0 The output of the comparator of DCP_DET loop “1” means DCP if CHG_DET is “1” “0” means CDP if CHG_DET is “1” The output of the comparator of CHG_DET loop “1” DCP or CDP “0” SDP or NON-DCP Charging port of SDP status “1” Charging port is SDP “0” Charging port is not SDP Charging port of DCP status “1” Charging port is DCP “0” Charging port is not DCP Charging port of CDP status “1” Charging port is CDP “0” Charging port is not CDP Flag when charging current below some level(0.5*full current) in CV mode High effective Charger voltage ready indicator, high effective When VCHG<4.1V: “0” When VCHG>4.3V: “1” Charger present indicator, high effective When VCHG<3.1V: ”0” When VCHG>3.3V: ”1” VCHG over voltage(programmable) flag When VCHG higher than some voltage set by VCHG_OVP_V<5:0> and lasts 2mS, CHGR_OVI=”1” The hysteresis voltage is 600mV. ARCH_EN PCLK_arch enable MCU_WR_PROT_VALUE Arch_en write protect bit status. When mcu_wr_prot_value==16'h3c4d, the bit is "1",else "0" Arch_en write protect value DCDC_CORE_REG1 clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCCORE, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 2 …… 6'h3F: divide by 64 DCDC_GEN_REG1 clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCGEN, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 2 …… 6'h3F: divide by 64 DCDC_VRF_REG1 clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCVRF, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 2 …… 6'h3F: divide by 64 BG_CTRL Band-gap chopping enable: “0”:chopping disable (default) “1”: chopping enable Band-gap test enable: “0”:test disable (default) “1”: test enable LDO_VOSEL1 USB33 LDO output voltage select 000000~111111 1.625V~3.225V 25mv/step CAMA LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step LDO_VOSEL3 MMC LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step VIO33 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step LDO_VOSEL4 LCD LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step LP18 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step LDO_LP18_CTRL1 LDO_LP18 increase feedback current 300nA in ULP mode LDO_LP18 bias current trim in ulp mode;20nA/step LDO_VIO33 increase feedback current 300nA in ULP mode LDO_VIO33 bias current trim in ulp mode;20nA/step RESERVED_REG_CORE reserved for CORE: RG_RESERVED_CORE[0] for ldo ANA cap sel, default 0; RG_RESERVED_CORE[1] for ldo CAMIO cap sel, default 0; RG_RESERVED_CORE[2] for ldo RF18A cap sel, default 0; RG_RESERVED_CORE[3] for ldo RF18B cap sel, default 0; RESERVED_REG1 RESERVED_REG2 LDO_SIM_CTRL0 LDO_SIM1 current limit threshold adjust default 1'b011 000 to 111 current limit increase LDO_SIM1 short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_SIM1 compensation capacitor and resistor adjust LDO_SIM1 discharge en LDO_SIM0 current limit threshold adjust default 1'b011 000 to 111 current limit increase LDO_SIM0 short protect EN: “0” is disable “1” is enable(default) compensation resistor adjust default 1'b1 LDO_SIM0 compensation capacitor and resistor adjust LDO_SIM0 discharge en LDO_SIM_VOSEL SIM0 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step 1.8V=000111 3V=110111 SIM1 LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step 1.8V=000111 3V=110111 SIM_VPA_CTRL0 LDO_SIM0 power down: “1” is power down(default) “0” is power up LDO_SIM1 power down: “1” is power down(default) “0” is power up LDO_SIM0 lower power mode EN: “1” is enable “0” is disable(default) LDO_SIM1 lower power mode EN: “1” is enable “0” is disable(default) VPA low power mode 1'b0: active mode 1'b1: low-power mode DCDC VPA power down 1'b0: DCDC on 1'b1: DCDC power down LDO_SIM_CTRL1 LDOSIM2 power down enable in deep sleep mode LDO SIM1 power down enable in deep sleep mode LDO SIM1 low power mode enable in deep sleep mode 0: Disable 1: Enable LDO SIM0 low power mode enable in deep sleep mode 0: Disable 1: Enable VPA_CTRL0 DCDC VPA reference Bits selection 0: From efuse 1: From Software Register output voltage trim 5'10000: default 1.2V, 18.75mV/step 5'11111: +15 step 5'00000: -16 step VPA_CTRL1 output voltage selection, 25mV/step. 7'h00=0.4V, 7'h7C=3.5V default 7'h78=3.4V VPA_CTRL2 force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off zero-cross offset tuning 2'b00: default 2'b01: +4mV offset 2'b10: -2mV offset 2'b11: -4mV offset anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on APC mode enable 1'b0: default, RG control mode 1'b1: APC mode APC ramp selection 1'b0: default, 2.0x ramp 1'b1: 2.5x ramp bypass mode disable 1'b0: default, auto bypass 1'b1: bypass off bypass force on 1'b0: default, auto bypass 1'b1: force bypass mode on bypass mode threshold 2'b00: default, ~200mV compensation C3 2'b00: default 6.5pF 2'b01: -0.5pF 2'b10: +1pF 2'b11: +0.5pF current limit threshold tuning 2'b00: default 36k 2'b01: 52k 2'b10: 12k 2'b11: 28k current sense multiplier tuning 2'b00: default, x1 2'b01: x0.5 2'b10: x2 2'b11: x1.5 VPA_CTRL3 sawtooth calibration 1'b0: default, auto calibration before power-on 1'b1: calibration manully DVS control 1'b0: default, off 1'b0: on, for DCM down discharge force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode 100% duty selection 1'b0: default, max duty=100% 1'b1: max duty ~95% PFM mode threshold for upper limit 2'b00: default,960mV 2'b01: -40mV 2'b10: +40mV 2'b11: +80mV compensation R2 select 2'b00: default, 960k 2'b01: 880k 2'b10: 1040k 2'b11: 1120k compensation R3 select 2'b00: default, 9k 2'b01: 4.5k 2'b10: 18k 2'b11: 13.5k sawtooth tuning manully 2'b00: default 0.75x 2'b01: 0.875x 2'b10: 0.5x 2'b11: 0.625x high side slew rate control 2'b00: default 2.5x 2'b01: 2x 2'b10: 1.5x 2'b11: 1x low side slew rate control 2'b00: default 2x 2'b01: 1.5x 2'b10: 1.5x 2'b11: 1x DCDC_VPA_REG1 clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCWPA, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 2 …… 6'h3F: divide by 64 MODULE_EN0 PINREG module enable 0: Disable the PCLK of pin registers 1: Enable the PCLK of pin registers RTC_TOPA module enable 0: Disable the PCLK of RTC_TOPA 1: Enable the PCLK of RTC_TOPA PSM module enable 0: Disable the PCLK of PSM 1: Enable the PCLK of PSM EIC module enable 0: Disable the PCLK of EIC 1: Enable the PCLK of EIC WDG module enable 0: Disable the PCLK of watchdog 1: Enable the PCLK of watchdog RTC module enable 0: Disable the PCLK of RTC 1: Enable the PCLK of RTC DIG_CLK_EN0 WDG clk sel 0: clk_wdg_rtc 1: clk_32k_rtc RTC_CLK_EN0 EFS RTC clock soft enable 0: Disable the RTC clock of EFS 1: Enable RTC clock of EFS EIC RTC clock soft enable 0: Disable the RTC clock of EIC 1: Enable RTC clock of EIC Watchdog RTC clock soft enable 0: Disable the RTC clock of Watchdog 1: Enable RTC clock of Watchdo RTC RTC clock soft enable 0: Disable the RTC clock of RTC 1: Enable RTC clock of RTC ARCH RTC clock soft enable 0: Disable the RTC clock of ARCH 1: Enable RTC clock of ARCH SOFT_RST0 EIC soft reset Watchdog soft reset RTC soft reset VBAT_CTRL1 LDO_VBAT ULP reference voltage trim bit LDO_VBAT reference voltage trim bit LDO_VGEN_CTRL3 LDO_VGEN reference voltage trim bit DCDC_CTRL1 internal oscillator enable 1'b0: oscillator off 1'b1: oscillator on oscillator frequency tuning 5'b10000: default 3MHz 5'b01111: -1 step 5'b10001: +1 step 5'b00000: -16 step 5'b11111: +15 step PM2_PD_EN PM2 VCORE ULP mode en 1'b0: disable 1'b1: enable PM2 VIO33 ULP mode en 1'b0: disable 1'b1: enable PM2 LP18 ULP mode en 1'b0: disable 1'b1: enable PM2 VCORE LP mode en 1'b0: disable 1'b1: enable PM2 VGEN LP mode en 1'b0: disable 1'b1: enable PM2 VLP18 LP mode en 1'b0: disable 1'b1: enable PM2 VDCXO LP mode en 1'b0: disable 1'b1: enable PM2 VIO33 LP mode en 1'b0: disable 1'b1: enable PM2 VIO18 LP mode en 1'b0: disable 1'b1: enable VCORE power down en 1'b0: disable 1'b1: enable VGEN power down en 1'b0: disable 1'b1: enable VLP18 power down en 1'b0: disable 1'b1: enable VDCXO power down en 1'b0: disable 1'b1: enable VIO33 power down en 1'b0: disable 1'b1: enable VIO18 power down en 1'b0: disable 1'b1: enable VGEN_CTRL1 output voltage selection, 12.5mV/step. 8'h00= 1.3V default 8'h2c=1.85V LDO_VBAT_CTRL1 CHGR_STATUS Chgr_int enable after CHG_DET_DONE 0: switch DPDM to USB phy when DCP 1: keep to connect charger detector when DCP POWER_PD_SW0 LDO_SPIMEM power down: “1” is power down(default) “0” is power up LDO_USB power down: “1” is power down(default) “0” is power up LDO_ANA power down: “1” is power down(default) “0” is power up LDO_RF12 power down: “1” is power down(default) “0” is power up LDO_LP18 power down: “1” is power down(default) “0” is power up LDO_VIO33 power down: “1” is power down(default) “0” is power up EMM domain power down 1: power down 0: power on LDO of charge pump power down 1: power down 0: power on LDO_DCXO power down 1: power down 0: power on LDO_MEM power down: “1” is power down(default) “0” is power up LDO_VIO18 power down: “1” is power down(default) “0” is power up DCDC power down 1'b0: DCDC on 1'b1: DCDC power down DCDC power down 1'b0: DCDC on 1'b1: DCDC power down DCDC power down 1'b0: DCDC on 1'b1: DCDC power down LDO_MMC power down: “1” is power down(default) “0” is power up Band-gap power down: “1” is power down “0” is power up At reset, should be "1" POWER_PD_HW Power off_sequence enable SOFT_RST_HW register soft reset，write 1 can： 1、 reset total system 2 、power down and up XTAL_RC_CTRL RC Oscillator 32kHz power up 1‘b0: power off 1'b1: power on Crystal 64kHz power up 1‘b0: power off 1'b1: power on Crystal 32kHz capacitor coarse adjust Crystal 32kHz capacitor fine adjust RTC_CTRL LDO RTC output program bits 3'b100: 1.8V (Default) Backup battery output program bits 3'b100: 3.0V default RTC bandgap calibretion bit cover +/-10% step 0.625% acc +/- 0.3125% RG_RTC_RESERVED1 RG_RTC_RESERVED0 RG_RTC_RESERVED1 DVDD_CTRL ULP global bias power down 1'b0: default, power on 1'b1: power down DVDD18 isolation signal used in force mode 1'b1: default isolation DVDD18 power down control used in force mode 1'b0: DVDD18 power switch on 1'b1: DVDD18 power switch off POWON_CTRL Control bit of de-glitch time for battery remove "00" 32us "01" 64us "10" 128us "11" no de-glitch default"00" Over voltage locked-out enable (high effective) Default “1” Over voltage locked-out detecting time 00 : 1ms (default) 01 : 0.5ms 10 : 0.25ms 11 : 2ms Over voltage locked-out threshold 00 : 5.0V (default) 01 : 5.2V 10 : 4.8V 11 : 4.2V over voltage locked-out threshold 00 : 1.9V (default) 01 : 1.95V 10 : 1.85V 11 : 1.8V Battery crash voltage setting: 00: 1.7/2.1V (default) 01: 1.8/2.2V 10: 1.65/2.3V 11: 1.6/2.5V BUA function enable 1'b0: default, off 1'b1: enable PBINT pull-high control 1'b0: with internal pull-high. Default 1'b1: without internal pull-high Power detect enable 1'b0: default, off 1'b1: Power detect on (UVLO/OVLO/VBATLOW) VBATLOW detect enable control at LP mode 1'b0: VBATLOW detect off 1'b1: VBATLOW detect on UVLO detect enable control at LP mode 1'b0: UVLO detect off 1'b1: UVLO detect on KPLED_CTRL0 Key PAD LED driver power down “1” power down (default) “0” enable Keypad LED pull down enable signale, high effective Defautl 1'b0 KPLED LDO power down signal, high effective (Default 1, Off) iload=50mA LDO_KPLED trim bits: 6.25mV/step, 0.7V~0.89375V; default 0.8V, 5'b10000 POWER_PD_SW1 LDO_CAMA power down: “1” is power down(default) “0” is power up LDO_CAMD power down: “1” is power down(default) “0” is power up LDO_LCD power down: “1” is power down(default) “0” is power up LDO_RF15 power down: “1” is power down(default) “0” is power up POWER_LP_SW0 LDO_USB lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_DCXO lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_CAMA lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_CAMD lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_MMC lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_LCD lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_VIO18 lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_ANA lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_MEM lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_SPIMEM lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_RF15 lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_RF12 lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_LP18 lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_VIO33 lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_VOSEL1 DCXO LDO output voltage select 000000~111111 1.625V~3.225V 25mV/step SLP_LDO_ULP_CTRL LDO_VCORE ultra lower power mode EN: “1” is enable “0” is disable(default) LDO_VIO33 ultra lower power mode EN: “1” is enable “0” is disable(default) LDO_LP18 ultra lower power mode EN: “1” is enable “0” is disable(default) LDO_VGEN_CTRL DCDC supplied LDO TRIM CONTROL BITS: 000: cal disable (default) 001: LDO VDDCAMIOcal enable; 010: LDO ANA cal enable; 011: LDO VDDRF18A cal enable; 100: LDO VDDCAMD cal enable; 101: LDO VDDMEM cal enable; 110: LDO VDDCON cal enable; 111: LDO VDDRF18B cal enable; LDO_LP18_VIO33_ULP_EN LDO_VIO33 ultra lower power mode EN(force mode): “1” is enable “0” is disable(default) LDO_LP18 ultra lower power mode EN(force mode): “1” is enable “0” is disable(default) VCORE_CTRL0 output voltage selection 9'b100100000, default 0.9V VCORE_CTRL1 low power mode(force mode) 1'b0: active mode 1'b1: low-power mode Ultra- low power mode(force mode) 1'b0: active mode 1'b1: low-power mode Retention active at ULP mode(force mode) 1'b0: retention off 1'b1: retention active output voltage trimming output voltage trimming at low power mode VRF_CTRL2 VRF low power mode(force mode) 1'b0: active mode 1'b1: low-power mode output voltage selection, 12.5mV/step. 8'h00= 1.3V default 8'h2c=1.85V VRF_CTRL3 output voltage selection, 6.25mV/step. 9'b011010000, default 1.3V VGEN_CTRL0 LP mode VMEM power switch enable: 1'b0:VMEM out 1'b1:VMEM short lp18,lp18 out PM2 LDO VMEM power switch value: 1'b0:VMEM out 1'b1:VMEM short lp18,lp18 out VGEN low power mode(force mode) 1'b0: active mode 1'b1: low-power mode VGEN output voltage trim 5'10000: default 1.2V, 18.75mV/step 5'11111: +15 step 5'00000: -16 step CHGR_CTRL0 “1” Internal charger power down “0” Internal charger power up Charger production test signal,testmode flag "1"ATE test mode, reduce delay time after VCHG insert "0" normal mode Choice of charger external power device 0:PNP+NMOS 1:PMOS+DIODE Default value is 0 VCHG tracking voltage level for automatic input control loop(AICL) 00: 3.8V 01: 3.95V 10: 4.3V 11: 4.5V Default value is 11 Battery sense DAC (CC-CV trans-point control) (default 6’b010000) CHGR_DET_CTRL0 The DP DM path switch control “1” switch to USB phy, BC1P2 detect disable (default) “0” switch to BC1P2, BC1P2 detect enable DP, DM to auxADC select signal: “0”: switch off, no DP/DM to auxADC “1”: switch on, DP/DM to auxADC charger int delay time: 000：0ms 001：64ms 010：2×64ms ….. 111：7×64ms SLP_LDO_PD_CTRL0 LDO VIO18 power down enable in PM1 0: disable 1: enable LDO ANA power down enable in deep sleep mode 0: disable 1: enable LDO RF12 power down enable in deep sleep mode 0: disable 1: enable LDO LP18 power down enable in PM1 0: disable 1: enable LDO DCXO power down enable PM1 0: disable 1: enable LDO VIO33 power down enable in PM1 0: disable 1: enable LDO RF15 power down enable in deep sleep mode 0: disable 1: enable LDO SPIMEM power down enable in deep sleep mode 0: disable 1: enable LDO USB power down enable in PM1 0: disable 1: enable LDO KPLED power down enable in deep sleep mode 0: disable 1: enable LDO MMC power down enable in deep sleep mode 0: disable 1: enable LDO LCD power down enable in deep sleep mode 0: disable 1: enable LDO CAMD power down enable in deep sleep mode 0: disable 1: enable LDO CAMA power down enable in deep sleep mode 0: disable 1: enable SLP_LDO_PD_CTRL1 LDO CP power down enable in PM1 0: disable 1: enable ALL LDO and DCDC power down enable in deep sleep mode 0: disable 1: enable IO PAD sleep enable in deep sleep mode 0: disable 1: enable LDO and DCDC can be controlled by external device if this bit is set 0: disable 1: enable LDO MEM power down enable in PM1 0: disable 1: enable SLP_DCDC_PD_CTRL The number of 32K cycles set reset delay in DCDC CORE power down sleep mode The number of 32K cycles release reset delay in DCDC CORE power down sleep mode DCDC CORE power drop enable in deep sleep mode 0: disable 1: enable DCDC RF power down enable in deep sleep mode 0: disable 1: enable DCDC GEN power down enable in PM1 0: disable 1: enable DCDC_CORE_SLP_CTRL0 delay between two steps in PM1 00:1*32k clock 01:2*32k clock 10:3*32k clock 11:4*32k clock step number in PM1 voltage per step in PM1 00000:0mv 00001:1*3.125mv 00010:2*3.125mv ….. 11111:31*3.125mv DCDC CORE power down enable in deep sleep mode 0: disable 1: enable DCDCCORE step tune enable in deep sleep 0: disable 1: enable DCDC_CORE_SLP_CTRL1 DCDC CORE voltage control in PM1 SLP_DCDC_LP_CTRL DCDC CORE low power mode enable in PM1 0: disable 1: enable DCDC VRF low power mode enable in deep sleep mode 0: disable 1: enable DCDC GEN low power mode enable in PM1 0: disable 1: enable SLP_LDO_LP_CTRL0 LDO RF15 low power mode enable in deep sleep mode 0: disable 1: enable LDO RF12 low power mode enable in deep sleep mode 0: disable 1: enable LDO EMMCCORE low power mode enable in PM1 0: disable 1: enable LDO DCXO low power mode enable in PM1 0: disable 1: enable LDO VIO18 low power mode enable in PM1 0: disable 1: enable LDO ANA low power mode enable in deep sleep mode 0: disable 1: enable LDO MEM low power mode enable in deep sleep mode 0: Disable 1: Enable LDO MMC low power mode enable in deep sleep mode 0: Disable 1: Enable LDO USB low power mode enable in PM1 0: Disable 1: Enable LDO LCD low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CAMD low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CAMA low power mode enable in deep sleep mode 0: Disable 1: Enable SLP_LDO_LP_CTRL1 DCDC CORE voltage control in PM2 LDO LP18 low power mode enable in PM1 0: Disable 1: Enable LDO MEM low power mode enable in PM1 0: Disable 1: Enable RESERVED_REG_RTC RG_RESERVED_RTC[4:0], DCXO trim bit for 32k-less poweroff mode. SW load from Efuse at first time power on. RG_RESERVED_RTC[15:5], reserved DCDC_VLG_SEL DCDC Voltage Program Bits selection 0: From efuse 1: From Software Register DCDC Voltage Trim Bits selection 0: From efuse 1: From Software Register DCDC Voltage Program Bits selection 0: From efuse 1: From Software Register DCDC Voltage Program Bits selection 0: From efuse 1: From Software Register LDO_VLG_SEL0 LDO_VGEN reference voltage trim bit selection 0: From efuse 1: From Software Register LDO_VBAT reference ULP voltage trim bit selection 0: From efuse 1: From Software Register LDO_VBAT reference voltage trim bit selection 0: From efuse 1: From Software Register oscillator frequency tuning selection 0: From efuse 1: From Software Register RTC bandgap calibretion bit selection 0: From efuse 1: From Software Register VRF output voltage selection, 0: From efuse 1: From Software Register output voltage trim selection 0: From efuse 1: From Software Register LDO Voltage trim selection 0: From efuse 1: From Software Register LDO Voltage trim selection 0: From efuse 1: From Software Register CLK32KLESS_CTRL0 RC_MODE write ack flag RC_MODE write ack flag clear, high effective Low power LDO_DCXO power down set in RTC Low power LDO_DCXO power down clear in RTC 0: 32k crystal 1: 32k-less 32K clock select in 32K crystal removal option 0: From XO 1: From RC RC 32K oscillator enable CLK32KLESS_CTRL1 RC 32K mode in battery drop case: 16'h95A5: RC oscillator stop working. Others: RC oscillator keep working. XTL_WAIT_CTRL0 POR_RST_MONITOR When POR reset active, this register is reset to 0 WDG_RST_MONITOR When WDG reset active, this register is reset to 0 POR_PIN_RST_MONITOR When POR_EXT_RST active, this register is reset to 0 POR_SRC_FLAG Setting this bit could disable the 1S debouncing time of power key after boot. register reset flag clear Power on source flag: [0]: Debounced PBINT signal, set when PBINT=0 >50ms, clear when PBINT=1>50ms. [1]: PBINT initiating power-up hardware flag, set when PBINT=0>1s, clear after power down. [2]: reserved. [3]: reserved. [4]: Debounced CHGR_INT signal, set when VCHG=1 >50ms, clear when VCHG=0>50ms. [5]: Charger plug-in initiating power-up hardware flag, set when VCHG=1>1s, clear after power down. [6]: RTC alarm initiating power-up hardware flag [7]: Long pressing power key reboot hardware flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear after power down. [8]: PBINT initiating power-up software flag, set when PBINT=0>1s, clear by pbint_flag_clr. [9]: reserved. [10]: Charger plug-in initiating power-up software flag, set when VCHG=1>1s, clear by chgr_int_flag_clr. [11: External pin reset reboot software flag, set when EXTRSTN=0>30ms, clear by ext_rstn_flag_clr. [12]: Long pressing power key reboot software flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear by pbint_7s_flag_clr. [13]: flag when register reset happened POR_7S_CTRL Write 1’b1 to this bit will clear pbint_7s_flag. Write 1’b1 to this bit will clear ext_rstn_flag. Write 1’b1 to this bit will clear chgr_int_flag. Write 1’b1 to this bit will clear pbint_flag. 1: One-key Reset Mode; 0: Two-key Reset Mode; 0: long reset; 1: short reset; The power key long pressing time threshold: 0~1: 2S 2: 3S 3: 4S 4: 5S 5: 6S 6: 7S 7: 8S 8: 9S 9: 10S 10:11S 11:12S 12: 13S 13:14S 14:15S 15:16S EXT_RSTN PIN function mode when 1key 7S reset 0: EXT_INT 1: RESET RTC register PBINT_7S_AUTO_ON_EN 0: enable 7s reset function; 1: disable 7s reset function; 0: software reset; 1: hardware reset; HWRST_RTC RTC status register, set by HWRST_RTC_SET. Software set this register to test VBAT and RTC power status. SMPL_CTRL0 SMPL mode: [15:13]: SMPL timer threshold 0: 0.25s 1: 0.5s 2: 0.75s …….. 7: 2s [12:0]: SMPL enable 13'h1935: enable Others: disable RTC_RST0 RTC register flag RTC_RST1 RTC register flag RTC_RST2 RTC register flag, reset by RTC_RST, default is 16'hA596 RTC_CLK_STOP rtc time over thresthold value set reset rtc cnt time,default 16s VBAT_DROP_CNT VBAT Drop Time Count MIXED_CTRL Power detect enable 1'b0: default, off 1'b1: Power detect on (UVLO/OVLO/VBATLOW) Battery presence flag to SW and POCV, so need RTC domain "0" no battery "1" battery presence VBAT detect. Active “0” is reset, no need 32K osc (same as BATDET_OK). ALL GPI source debug GPI debug enable ALL_INT debug, if 1, interrupt will be sent Interupt debug enable POR_OFF_FLAG uvlo + ovlo chip power down flag uvlo + ovlo chip power down flag clear uvlo chip power down flag uvlo chip power down flag clear 7s hard chip power down flag 7s hard chip power down flag clear SW chip power down flag SW chip power down flag clear HW chip power down flag HW chip power down flag clear OTP chip power down flag OTP chip power down flag clear SWRST_CTRL0 Software reset certain power enable when ext_rstn valid Software reset certain power enable when pb_7s_rst valid Software reset certain power enable when reg_rst valid Software reset certain power enable when wdg_rst valid register reset enable: 0: disable 1: enable reset LDO to normal mode threshold time 8ms/step,default 8ms SWRST_CTRL1 Software reset LDO_SPIMEM_PD enable when global reset valid 0: disable 1: enable Software reset LDO_VIO18_PD enable when global reset valid 0: disable 1: enable Software reset DCDC_GEN_PD enable when global reset valid 0: disable 1: enable Software reset DCDC_CORE_PD enable when global reset valid 0: disable 1: enable Software reset LDO_MEM_PD enable when global reset valid 0: disable 1: enable Software reset LDO_DCXO_PD enable when global reset valid 0: disable 1: enable Software reset LDO_RF12_PD enable when global reset valid 0: disable 1: enable Software reset LDO_ANA_PD enable when global reset valid 0: disable 1: enable Software reset LDO_RF15_PD enable when global reset valid 0: disable 1: enable Software reset LDO_USB_PD enable when global reset valid 0: disable 1: enable Software reset LDO_EMMCCORE_PD enable when global reset valid FREE_TIMER_LOW low 16 bit value of free timer FREE_TIMER_HIGH high 16 bit value of free timer RESERVED_REG1 voltage per step in PM2 00000:0mv 00001:1*3.125mv 00010:2*3.125mv ….. 11111:31*3.125mv PM1 LDO VMEM power switch value: 1'b0:VMEM out 1'b1:VMEM short lp18,lp18 out OVLO dbnc enable: 0: enable 1: disable UVLO dbnc enable: 0: enable 1: disable PM1 power detect off enable: 0:disable 1:enable PM1 bg_pd off enable: 0:disable 1:enable PM1 OSW3M off enable: 0:disable 1:enable PM1 DVDD_PD off and DVDD_ISO hold enable: 0:disable 1:enable RESERVED_REG2 delay betwwen IO and VCORE when PM1 exits.(IO delay== {2'h0,pm1_sleep_dly2,2'h0}) delay betwwen IO and VCORE when entering PM1.(VCORE delay== {2'h0,pm1_sleep_dly1,2'h0} + 1) if chip_sleep is low,ULP mode can use this value [3:0]:ULP cycle sel 4'h0:2; 4'h1:4; 4'h2:8; … 4'hb:4096. RESERVED_REG3 UVLO dbnc time: 0:1ms 1:61us 2:91.5:us 3:122us …… ff:7.8ms UVLO dbnc time: 0:2ms 1:61us 2:91.5:us 3:122us …… ff:7.8ms RESERVED_REG4 delay betwwen IO and VCORE when PM1 exits.(IO delay== pm1_sleep_dly2) delay betwwen IO and VCORE when entering PM1.(VCORE delay== pm1_sleep_dly1 + 1) RESERVED_REG5 LDO CP power down enable in PM2 0: disable 1: enable delay between two steps in PM2 00:1*32k clock 01:2*32k clock 10:3*32k clock 11:4*32k clock step number in PM2 PM2 power detect off enable: 0:disable 1:enable PM2 bg_pd off enable: 0:disable 1:enable PM2 OSW3M off enable: 0:disable 1:enable PM2 DVDD_PD off and DVDD_ISO hold enable: 0:disable 1:enable LDO USB low power mode enable in PM2 0: disable 1: enable LDO MEM low power mode enable in PM2 0: disable 1: enable LDO USB power down enable in PM2 0: disable 1: enable LDO MEM power down enable in PM2 0: disable 1: enable RESERVED_REG6 select the configuration used under PM2 0: disable 1: enable PWR_WR_PROT_VALUE All power which default on write protect bit status. When mcu_wr_prot_value==16'h6e7f, the bit is "1",else "0" Arch_en write protect value VOL_TUNE_CTRL_CORE clock source for CORE DVFS 0: clock 26M 1: clock 32K delay between two steps 00:1*32k clock or 2us in 26M 01:2*32k clock or 4us in 26M 10:3*32k clock or 8us in 26M 11:4*32k clock or 16us in 26M step number DVFS voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv ….. 11111:31*3.125mv voltage tune start bit voltage tune flag 0:done 1:on going voltage tune enable 0: disable 1: enable SMPL_CTRL1 Set once SMPL timer not expired. Set once SMPL mode write finish Clear SMPL_PWR_ON_FLAG Clear SMPL_MODE_WR_ACK Set once SMPL timer not expired, SMPL enable indication low 16 bits of watchdog value low 16 bits of watchdog value wdg_ld_value_low: low 16 bit of watchdog timer load value wdg_ld_value_high: high 16 bit of watchdog timer load value wdg_ld_value_higher: higher 16 bit of watchdog timer load value wdg_ld_value_low, wdg_ld_value_high and wdg_ld_value_higher are used together.Software should write wdg_ld_value_higher firstly, and then write wdg_ld_value_high, last write wdg_ld_value_low, because writing wdg_ld_value_low can trig loading both wdg_ld_value_low and wdg_ld_value_high to watchdog counter, and writing wdg_ld_value_high cannot trig this event. So software must guarantee wdg_ld_value_high is ready when writing wdg_ld_value_low. In reset mode, software should load new value before timer decrease to 0. In interrupt mode, this value is counting start number. The default value is about 8 seconds. high 16 bits of watchdog value high 16 bits of watchdog value See wdg_ld_value_low description. watchdog control watchdog control Watchdog reset enable bit 0: reset is disabled 1: reset is enabled For reset mode: wdg_rst_en =1, wdg_irq_en=0. For interrupt mode: wdg_rst_en =0, wdg_irq_en=1. For combined mode: wdg_rst_en =1, wdg_irq_en=1. Reset can't be triggered before wdg_rst_raw is cleared. Watchdog version 0: watchdog use old behavior, this is for backward compatibility 1: watchdog uses new behavior, such as multiple loads without checking busy bit, only need to read once to get timer counter value. Watchdog counter open: 0: counter stops. 1: counter runs. Watchdog interrupt enable bit 0: interrupt is disabled 1: interrupt is enabled For reset mode: wdg_rst_en =1, wdg_irq_en=0. For interrupt mode: wdg_rst_en =0, wdg_irq_en=1. For combined mode: wdg_rst_en =1, wdg_irq_en=1. watchdog interrupt clear watchdog interrupt clear Watchdog reset clear Write 1 to this bit to clear reset Read this bit always get 0. Watchdog interrupt clear Write 1 to this bit to clear interrupt Read this bit always get 0. watchdog interrupt raw status watchdog interrupt raw status Watchdog load busy status 0: Watchdog is ready for new loading 1: Last loading is not completed Software must not load new value when this bit is busy, that is, this bit should be checked before any new loading. This bit is set after a new loading, and lasts two or three RTC clock cycles, about 60us - 92us. Watchdog reset raw status. Watchdog reset cannot clear this raw status, Also it can be used to judge if or not system rebooting comes from watchdog reset. Write wdg_rst_clr can clear this raw status. Watchdog interrupt raw status. Watchdog reset cannot clear this raw status. Write wdg_irq_clr can clear this raw status. watchdog interrupt mask status watchdog interrupt mask status Watchdog interrupt masked status low 16 bits of watchdog counter value low 16 bits of watchdog counter value wdg_cnt_low: Low 16 bit of watchdog timer counter value. wdg_cnt_high: Mid 16 bit of watchdog timer counter value. wdg_cnt_higher: High 16 bit of watchdog timer counter value. wdg_cnt_low, wdg_cnt_mid and wdg_cnt_high are used together. This read-only register indicates current counter value. It’s not recommended to read this register in normal usage. Because the counter is in different clock domain with APB, software needs use double-reading method to read this value, like system timer. high 16 bits of watchdog counter value high 16 bits of watchdog counter value See wdg_cnt_low description. watchdog lock control watchdog lock control Watchdog lock control Write 16’hE551 to this register to unlock watchdog. Write other value to this register to lock watchdog If reading this register, bit-0 is lock status, and other bits are reserved. If watchdog is locked, all control registers cannot be written by software. low 16 bits of watchdog counter value for read low 16 bits of watchdog counter value for read wdg_cnt_read_low: Low 16 bit of watchdog timer counter value for read. wdg_cnt_read_high: High 16 bit of watchdog timer counter value for read. wdg_cnt_read_higher: Higher 16 bit of watchdog timer counter value for read. wdg_cnt_read_low and wdg_cnt_read_high are used together. This read-only register indicates current counter value. Read once can get watchdog counter value. No need to double read this reg. Refer to timer’s TIMER0_CNT_RD or TIMER1_CNT_RD high 16 bits of watchdog counter value for read high 16 bits of watchdog counter value for read Refer to wdg_cnt_read_low low 16 bits of watchdog irq value low 16 bits of watchdog irq value wdg_ irq_value_low: Low 16 bit of watchdog irqvalue. wdg_ irq_value_high: High 16 bit of watchdog irqvalue. wdg_ irq_value_higher: Higher 16 bit of watchdog irqvalue. wdg_ irq_value_low and wdg_ irq_value_high are used together. It’s useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 48’0000_h0003_0000, corresponds to 6 seconds, which means reset will occur after irq is 1 for 6 seconds. high 16 bits of watchdog irq value high 16 bits of watchdog irq value wdg_ irq_value_low: Low 16 bit of watchdog irq value. wdg_ irq_value_high: High 16 bit of watchdog irq value. wdg_ irq_value_higher: Higher 16 bit of watchdog irq value. wdg_ irq_value_low, wdg_irq_value_mid and wdg_ irqvalue_high are used together, which means reset will occur after irq is 1 for 6 seconds. It’s useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irq value, an interrupt is generated. Default value of watchdog irqvalue is 48’h0000_0003_0000, corresponds to 6 seconds. higher 16 bits of watchdog value higher 16 bits of watchdog value See wdg_ld_value_low description. higher 16 bits of watchdog counter value higher 16 bits of watchdog counter value See wdg_cnt_low description. higher 16 bits of watchdog counter value for read higher 16 bits of watchdog counter value for read Refer to wdg_cnt_read_low higher 16 bits of watchdog irq value higher 16 bits of watchdog irq value wdg_ irq_value_low: Low 16 bit of watchdog irq value. wdg_ irq_value_high: High 16 bit of watchdog irq value. wdg_ irq_value_higher: Higher 16 bit of watchdog irq value. wdg_ irq_value_low, wdg_irq_value_high and wdg_ irq_value_higher are used together, which means reset will occur after irq is 1 for 6 seconds. It’s useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irq value, an interrupt is generated. Default value of watchdog irqvalue is 48’h0000_0003_0000, corresponds to 6 seconds. if write 0x454e to enable write psm reg, readback only [15] is high psm calibration pre time. The time is from pull DCXO high to OSC 26M stable. unit is (clk_cal_64k_div_th +1)ms psm calibration time 1s/(2^(16-rc_32k_cal_cnt_n))/( rc_32k_cal_cnt_p+1) psm 26m calibration value update down threshold. Value = (1/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) psm 26m calibration value update up threshold Value = (3/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) 1'b1: rtc use psm cal 32K clock in 32K less mode,1'b0:rtc use RC 32K clock in 32K less mode enable psm cal clear psm int status enble psm timer cnt posedge to update psm cnt value software reset psm module, auto clear enable psm timer to wake up sys enable psm alarm function enable charger to power on sys enable pbint2 to power on sys enable pbint1 to power on sys enable ext int to power on sys enable rtc power on time out detect enable psm fsm The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms The time to disable rtc clk in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms The time to reset rtc in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to power off rtc done in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to release reset in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to power on rtc , unit is 4*(clk_cal_64k_div_th +1)ms The time to clock enable in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to release hold ISO in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to mark power on timeout in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to power on rtc done , unit is 4*(clk_cal_64k_div_th +1)ms The low 16 bits threshold of psm time , unit is 10*(clk_cal_64k_div_th +1)ms The high 16 bits threshold of psm time , unit is 10ms The low 16 bits threshold of psm alarm time , unit is 10*(clk_cal_64k_div_th +1)ms The high 16 bits threshold of psm alarm time The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms 0：sel clk_cal_1k；1：sel clk_rc_64k or xtal32k 0：disable ；1：enable LDO_DCXO discharge en LDO_DCXO short protect EN: “0” is disable “1” is enable(default) LDO_DCXO compensation capacitor and resistor adjust compensation resistor adjust LDO_DCXO current limit threshold adjust , 111~000 380mA~240mA 20mA/step DCXO LDO output voltage select, 000000~111111 1.625V~3.225V 25mV/step Psm calibration divider, 1）when rc_64k calib(clude xtal_32k calib use rc_64k por on first time)，it is calculated with rc_32k_cal_cnt_n – log2(clk_cal_64k_div_th+1)；e.g: I. clk_cal_1k=128Hz, cnt_p=0x4,cnt_n=0x8，div_th=0xf；II. clk_cal_1k=1KHz, cnt_p=0x4,cnt_n=0x5，div_th=0x1 2）when 32k_xtal calib，it is calculated with rc_32k_cal_cnt_n-log2(clk_cal_64k_div_th+1)-1；e.g: I. clk_cal_1k=128Hz, cnt_p=0x4,cnt_n=0x8，div_th=0x7；II. clk_cal_1k=1KHz, cnt_p=0x4,cnt_n=0x5，div_th=0x0 3）when 32k_xtal no calib, e.g: I. clk_cal_1k=128Hz,div_th=4'hf； II. clk_cal_1k=1KHz,div_th=4'h0 psm rc 64K divider, the input RC clock is divider to CLK_64K/( clk_cal_64k_div_th+1) Enable watchdog power on chip by internal RC clock Psm cnt updated low 16 bits value, the step of read this value is : (1)enable psm_cnt_update, (2)wait till psm_cnt_update_vld ==1.(psm_fsm_status[6]) Psm cnt updated high 16 bits value psm cnt updated valid when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when psm_cnt_en==1, then if psm cnt get psm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when pbint2_pwr_en==1, then if pbint2 is low, this bit is high, When psm_status_clr is high, this bit is low when pbint1_pwr_en==1, then if pbint1 is low, this bit is high, When psm_status_clr is high, this bit is low when ext_int_en==1, then if ext_int is high, this bit is high, When psm_status_clr is high, this bit is low Only debug use We can use this value to calculate the RC 64K clock real frequency. Rc_64k=( clk_cal_64k_div_th+1)*(2^ rc_32k_cal_cnt_p)*26*10^6/ (psm_cal_cnt*2^9) PBINT or CHGR_INT dbs time,0.244ms step bg pd power on timer,0.244ms step ext rst_n release timer,0.244ms step ext xtl0_en~ext_xtl3_en dbs time，32kHz ext xtl0_en~ext_xtl3_en dbs time，32kHz 0~7:ext_xtl_en0~7 high or low enable to exit psm，0：low vld，1：high vld 0：disable xtal32k clk；1：enable xtal32k 0:clk_32k_xtal not calibra;1:clk_32k_xtal or rc_64k calibra xtl7_flag xtl6_flag xtl5_flag xtl4_flag xtl3_flag xtl2_flag xtl1_flag xtl0_flag 0:xtal_32k por on use xtal_32k,xtal not calibra must configure 0 ;1:xtal_32k por on use rc_64k INT_MASK_STATUS INT_RAW_STATUS INT_EN PIN_ADI_SCLK PIN_ADI_D PIN_EXT_RST_B PIN_ANA_INT PIN_CHIP_SELLP PIN_CLK_32K PIN_PTESTO PIN_CLK26M EXT_XTL_EN0 EXT_XTL_EN1 EXT_XTL_EN2 EXT_XTL_EN3 EXT_XTL_EN4 EXT_XTL_EN5 EXT_XTL_EN6 EXT_XTL_EN7 adi low bits version. adi high bits version,read only. addr mode for access. "00" word mode,means addr[x:2],"01" half word,means addr[x:1], "1x" byte mode, means addr[x:0]. configure write bit flag. addr bit number configure, "00" address is 12 bits, "01" address is 10 bits, "10" address is 15 bits. "1" write uses command mode, in this mode, must first configure channel addr, then data. write channel 0 priority. 0 has lowest priority, 4 has highest priority. read channel 1 priority. 0 has lowest priority, 4 has highest priority. read channel 2 priority. 0 has lowest priority, 4 has highest priority. read channel 3 priority. 0 has lowest priority, 4 has highest priority. read channel 4 priority. 0 has lowest priority, 4 has highest priority. read channel 5 priority. 0 has lowest priority, 4 has highest priority. "1" write command fifo enable. fifo overfolow interrupt mask. fifo overfolow interrupt without mask status. fifo overfolow interrupt with mask status. fifo overfolow interrupt clear. total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len. total adi cmd length = rf_gssi_addr_len + read/write flag. total adi data length . write bit position in frame stream . "1" write means 1, "0" write means 0. "1" hardware auto generate sync, "0" software generates sync. "1" sync is pulse, "0" sync is level. "1" software generates sync. "1" invert output sck. output oen : "1" oen add dummy cycle, "0" oen not add dummy cycle. reserved. "1" output dummy_clock, "0" gate dummy clock. "1" rx sample delay 1 adi clk cycle, "0" delay 0 adi clk cycle. "1" sck always on, "0" audo gate clock. "1" write bit disable, "0" write bit enable. "1" tx data at negedge of sck."0" tx data at posedge of sck. "1" rx data at negedge of sck."0" rx data at posedge of sck. F_sck = F_clk/(2*(rf_gssi_clk_div+1)) sync before data transfer sync end data transfer extral dummy sck extral dummy sck start sequence condition, only used in RFFE master turn around to salve length , only used in RFFE slave turn around to master length , only used in RFFE "1" 2 wires enable configure read address and start a read operation. read data from analog die. read address map to arm_red_cmd[16:2]. 1 means has not been read back. "1" write channel is busy "1" read channel is busy "1" adi operation is busy wfifo full status wfifo empty status wfifo fill data number adi fsm status event 0 wr status event 1 wr status event 2 wr status event 3 wr status the address map to the PMIC chip space, just for write operation the dat to the PMIC chip space, just for write operation This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
Secure cpu can use all channels, but non-secure cpu only can use non-secure channel.
Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec.
When non-secure cpu read this register, the return value will automatic exlude the secure channel.
00000 = use Channel0
00001 = use Channel1
00010 = use Channel2
...
01111 = use Channel15
11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example:
0000_0000 = All channels registers can be accessed by secure master or non-secure master.
0000_0001 = Ch0 registers can only be accessed by secure master.
0000_0010 = Ch1 registers can only be accessed by secure master.
0000_0100 = Ch2 registers can only be accessed by secure master.
0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master.
0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master.
......
all 1 = all channels registers can only be accessed by secure master. This register indicates aif channel register can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example:
0000_0000 = All channels dma are non-secure master.
0000_0001 = Ch0 dma is secure master.
0000_0010 = Ch1 dma is secure master.
0000_0100 = Ch2 dma is secure master.
0000_0101 = Ch0 and Ch2 dma are secure master.
0000_0111 = Ch0, Ch1 and Ch2 dma are secure master.
......
all 1 = all channels dma are secure master. This register indicates aif channel dma is secure master. This register indicates dbghost channel dma is secure master. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB
Exchange the write data to fifo halfword MSB or LSB
Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. The Channel 0 conveys data from the AIF to the memory.
The Channel 1 conveys data from the memory to the AIF.
These Channels only exist with Voice Option. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. When 1 the channel is enabled When 1 the fifo is empty Cause interrupt End of FIFO. Cause interrupt Half of FIFO. Cause interrupt Quarter of FIFO. Cause interrupt Three Quarter of FIFO. Cause interrupt ahb error. End of FIFO interrupt status bit. Half of FIFO interrupt status bit. Quarter of FIFO interrupt status bit. Three Quarter of FIFO interrupt status bit. ahb error interrupt status bit. channel busy status bit. AHB Start Address. This field represent the start address of the FIFO located in RAM. Fifo size in bytes, max 1MBytes.
The size of the fifo must be a multiple of 16 (The four LSB are always zero). END FIFO Mask interrupt. When one this interrupt is enabled. HALF FIFO Mask interrupt. When one this interrupt is enabled. QUARTER FIFO Mask interrupt. When one this interrupt is enabled. THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. ahb_error Mask interrupt. When one this interrupt is enabled. Write one to clear end of fifo interrupt. Write one to clear half of fifo interrupt. Write one to clear Quarter fifo interrupt. Write one to clear Three Quarter fifo interrupt. Write one to clear ahb_error interrupt. Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
Secure cpu can use all channels, but non-secure cpu only can use non-secure channel.
Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec.
When non-secure cpu read this register, the return value will automatic exlude the secure channel.
00000 = use Channel0
00001 = use Channel1
00010 = use Channel2
...
01111 = use Channel15
11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example:
0000_0000 = All channels registers can be accessed by secure master or non-secure master.
0000_0001 = Ch0 registers can only be accessed by secure master.
0000_0010 = Ch1 registers can only be accessed by secure master.
0000_0100 = Ch2 registers can only be accessed by secure master.
0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master.
0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master.
......
all 1 = all channels registers can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example:
0000_0000 = All channels dma are non-secure master.
0000_0001 = Ch0 dma is secure master.
0000_0010 = Ch1 dma is secure master.
0000_0100 = Ch2 dma is secure master.
0000_0101 = Ch0 and Ch2 dma are secure master.
0000_0111 = Ch0, Ch1 and Ch2 dma are secure master.
......
all 1 = all channels dma are secure master. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB
Exchange the write data to fifo halfword MSB or LSB
Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. general used register security visit enable 0:security 1:unsecurity response error stop function enable 0:enable 1:disable the number of outstanding that can be send out 0: 2 1: 3 2: 4 multe-channel transport priority mode control 0: there is no priority in the channels, using polling to DMA data 1: smaller channel number has high-priority.high-priority move data before low-priority channels interrupt control bit 0: no interruption occurs when all logical channels finish 1: interruption occurs when all logical channels finish the control bit of logical channel transport finish 0: don't stop all the channel,or automatically clear after setting 1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. stop status 0: not finish 1: finish the channel number of the final transmission 0000: channel 0 just finished the transmission 0001: channel 1 just finished the transmission 0010: channel 2 just finished the transmission ...... 1011: channel 11 just finished the transmission others: nonentity logic channel stop interrupt status channel 11 interrupts state 0: the channel 11 has not been interrupted, or the interrupt bit has been cleared 1: channel 11 is interrupted channel 10 interrupts state 0: the channel 10 has not been interrupted, or the interrupt bit has been cleared 1: channel 10 is interrupted channel 9 interrupts state 0: the channel 9 has not been interrupted, or the interrupt bit has been cleared 1: channel 9 is interrupted channel 8 interrupts state 0: the channel 8 has not been interrupted, or the interrupt bit has been cleared 1: channel 8 is interrupted channel 7 interrupts state 0: the channel 7 has not been interrupted, or the interrupt bit has been cleared 1: channel 7 is interrupted channel 6 interrupts state 0: the channel 6 has not been interrupted, or the interrupt bit has been cleared 1: channel 6 is interrupted channel 5 interrupts state 0: the channel 5 has not been interrupted, or the interrupt bit has been cleared 1: channel 5 is interrupted channel 4 interrupts state 0: the channel 4 has not been interrupted, or the interrupt bit has been cleared 1: channel 4 is interrupted channel 3 interrupts state 0: the channel 3 has not been interrupted, or the interrupt bit has been cleared 1: channel 3 is interrupted channel 2 interrupts state 0: the channel 2 has not been interrupted, or the interrupt bit has been cleared 1: channel 2 is interrupted channel 1 interrupts state 0: the channel 1 has not been interrupted, or the interrupt bit has been cleared 1: channel 1 is interrupted channel 0 interrupts state 0: the channel 0 has not been interrupted, or the interrupt bit has been cleared 1: channel 0 is interrupted state of IRQ 23 generate requests of moving data 0: IRQ 23 does not generate requests of moving data 1: IRQ 23 generate requests of moving data state of IRQ 22 generate requests of moving data 0: IRQ 22 does not generate requests of moving data 1: IRQ 22 generate requests of moving data state of IRQ 21 generate requests of moving data 0: IRQ 21 does not generate requests of moving data 1: IRQ 21 generate requests of moving data state of IRQ 20 generate requests of moving data 0: IRQ 20 does not generate requests of moving data 1: IRQ 20 generate requests of moving data state of IRQ 19 generate requests of moving data 0: IRQ 19 does not generate requests of moving data 1: IRQ 19 generate requests of moving data state of IRQ 18 generate requests of moving data 0: IRQ 18 does not generate requests of moving data 1: IRQ 18 generate requests of moving data state of IRQ 17 generate requests of moving data 0: IRQ 17 does not generate requests of moving data 1: IRQ 17 generate requests of moving data state of IRQ 16 generate requests of moving data 0: IRQ 16 does not generate requests of moving data 1: IRQ 16 generate requests of moving data state of IRQ 15 generate requests of moving data 0: IRQ 15 does not generate requests of moving data 1: IRQ 15 generate requests of moving data state of IRQ 14 generate requests of moving data 0: IRQ 14 does not generate requests of moving data 1: IRQ 14 generate requests of moving data state of IRQ 13 generate requests of moving data 0: IRQ 13 does not generate requests of moving data 1: IRQ 13 generate requests of moving data state of IRQ 12 generate requests of moving data 0: IRQ 12 does not generate requests of moving data 1: IRQ 12 generate requests of moving data state of IRQ 11 generate requests of moving data 0: IRQ 11 does not generate requests of moving data 1: IRQ 11 generate requests of moving data state of IRQ 10 generate requests of moving data 0: IRQ 10 does not generate requests of moving data 1: IRQ 10 generate requests of moving data state of IRQ 9 generate requests of moving data 0: IRQ 9 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 8 generate requests of moving data 0: IRQ 8 does not generate requests of moving data 1: IRQ 8 generate requests of moving data state of IRQ 7 generate requests of moving data 0: IRQ 7 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 6 generate requests of moving data 0: IRQ 6 does not generate requests of moving data 1: IRQ 6 generate requests of moving data state of IRQ 5 generate requests of moving data 0: IRQ 5 does not generate requests of moving data 1: IRQ 5 generate requests of moving data state of IRQ 4 generate requests of moving data 0: IRQ 4 does not generate requests of moving data 1: IRQ 4 generate requests of moving data state of IRQ 3 generate requests of moving data 0: IRQ 3 does not generate requests of moving data 1: IRQ 3 generate requests of moving data state of IRQ 2 generate requests of moving data 0: IRQ 2 does not generate requests of moving data 1: IRQ 2 generate requests of moving data state of IRQ 1 generate requests of moving data 0: IRQ 1 does not generate requests of moving data 1: IRQ 1 generate requests of moving data state of IRQ 0 generate requests of moving data 0: IRQ 0 does not generate requests of moving data 1: IRQ 0 generate requests of moving data state of ACK 23 generate requests of moving data 0: ACK 23 does not generate requests of moving data 1: ACK 23 generate requests of moving data state of ACK 22 generate requests of moving data 0: ACK 22 does not generate requests of moving data 1: ACK 22 generate requests of moving data state of ACK 21 generate requests of moving data 0: ACK 21 does not generate requests of moving data 1: ACK 21 generate requests of moving data state of ACK 20 generate requests of moving data 0: ACK 20 does not generate requests of moving data 1: ACK 20 generate requests of moving data state of ACK 19 generate requests of moving data 0: ACK 19 does not generate requests of moving data 1: ACK 19 generate requests of moving data state of ACK 18 generate requests of moving data 0: ACK 18 does not generate requests of moving data 1: ACK 18 generate requests of moving data state of ACK 17 generate requests of moving data 0: ACK 17 does not generate requests of moving data 1: ACK 17 generate requests of moving data state of ACK 16 generate requests of moving data 0: ACK 16 does not generate requests of moving data 1: ACK 16 generate requests of moving data state of ACK 15 generate requests of moving data 0: ACK 15 does not generate requests of moving data 1: ACK 15 generate requests of moving data state of ACK 14 generate requests of moving data 0: ACK 14 does not generate requests of moving data 1: ACK 14 generate requests of moving data state of ACK 13 generate requests of moving data 0: ACK 13 does not generate requests of moving data 1: ACK 13 generate requests of moving data state of ACK 12 generate requests of moving data 0: ACK 12 does not generate requests of moving data 1: ACK 12 generate requests of moving data state of ACK 11 generate requests of moving data 0: ACK 11 does not generate requests of moving data 1: ACK 11 generate requests of moving data state of ACK 10 generate requests of moving data 0: ACK 10 does not generate requests of moving data 1: ACK 10 generate requests of moving data state of ACK 9 generate requests of moving data 0: ACK 9 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 8 generate requests of moving data 0: ACK 8 does not generate requests of moving data 1: ACK 8 generate requests of moving data state of ACK 7 generate requests of moving data 0: ACK 7 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 6 generate requests of moving data 0: ACK 6 does not generate requests of moving data 1: ACK 6 generate requests of moving data state of ACK 5 generate requests of moving data 0: ACK 5 does not generate requests of moving data 1: ACK 5 generate requests of moving data state of ACK 4 generate requests of moving data 0: ACK 4 does not generate requests of moving data 1: ACK 4 generate requests of moving data state of ACK 3 generate requests of moving data 0: ACK 3 does not generate requests of moving data 1: ACK 3 generate requests of moving data state of ACK 2 generate requests of moving data 0: ACK 2 does not generate requests of moving data 1: ACK 2 generate requests of moving data state of ACK 1 generate requests of moving data 0: ACK 1 does not generate requests of moving data 1: ACK 1 generate requests of moving data state of ACK 0 generate requests of moving data 0: ACK 0 does not generate requests of moving data 1: ACK 0 generate requests of moving data channel 11 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 10 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 9 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 8 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 7 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 6 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 5 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 4 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 3 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 2 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 1 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 0 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel [9:8]=='b00: select adc input data ; [9:8]=='b01: select dac output loop data ; [9:8]=='b1x: force to zero ; [6]==0: fm input to aif1; [6]=1: audio codec input to aif1; [7]==0: fm input to aif2; [7]=1: audio codec input to aif2; [5:4]=='bx1: aif1 output to audio codec ; [5:4]=='b10: aif2 output to audio codec ; [5:4]=='b00: zero output to audio codec ; ==1: enable adc left channel; ==1: enable dac right channel; ==1: enable adc left channel; ==1: enable adc right channel; ==1: enable mute; ==1: enable soft mute; dac mute counter1 threshold, step is countrolled by counter 0; dac mute counter0 threshold dac fs frequency 0:96K 1:48K 2:44.1K 3:32K 4:24K 5:22.05K 6:16K 7:12K 8:11.025K 9:9.6K 10:8K adc src upsample tap, sample rate=N*4K ==1: enable audio adc parallel data loop to dac parallel data path; ==0: force to 0 to select 26m audio clock; ==1: invert output mclk ; left adc channel dgain 4'hf: 16dB 4'he: 14dB 4'hd: 12dB 4'hc: 10dB 4'hb: 8dB 4'ha: 6dB 4'h9: 4dB 4'h8: 2dB 4'h7: 0dB 4'h6:-2dB 4'h5:-4dB 4'h4:-6dB 4'h3:-8dB 4'h2:-10dB 4'h1:-12dB 4'h0:mute right adc channel dgain 4'hf: 16dB 4'he: 14dB 4'hd: 12dB 4'hc: 10dB 4'hb: 8dB 4'ha: 6dB 4'h9: 4dB 4'h8: 2dB 4'h7: 0dB 4'h6:-2dB 4'h5:-4dB 4'h4:-6dB 4'h3:-8dB 4'h2:-10dB 4'h1:-12dB 4'h0:mute right adc channel dgain 1:sel tone dac tone dgain 0:sel normal dac dgain left dac channel dgain [5:1] = 5'h1f: 05dB 5'h1e: 04dB 5'h1d: 03dB 5'h1c: 02dB 5'h1b: 01dB 5'h1a: 00dB 5'h19: -01dB 5'h18: -02dB 5'h17: -03dB 5'h16: -04dB 5'h15: -05dB 5'h14: -06dB 5'h13: -07dB 5'h12: -08dB 5'h11: -09dB 5'h10: -10dB 5'h0f: -11dB 5'h0e: -12dB 5'h0d: -13dB 5'h0c: -14dB 5'h0b: -15dB 5'h0a: -16dB 5'h09: -17dB 5'h08: -18dB 5'h07: -19dB 5'h06: -20dB 5'h05: -21dB 5'h04: -22dB 5'h03: -23dB 5'h02: -24dB 5'h01: -25dB 5'h00: -26dB [0]:1'b1,+0.5dB [7]:1'b1,+12dB [6]:1'b1,+6dB right dac channel dgain detail see dac_l_nor_dgain[7:0] left dac channel dgain detail see dac_l_nor_dgain[7:0] right dac channel dgain detail see dac_l_nor_dgain[7:0] Enable camera controller,high active. Enable camera controller,high active. "0" = RGB565.
"1" = YUV422.
"2" = Compressed Data.
"3" = Reserved. '0' = keep output camera reset polarity.
'1' = invert output camera reset polarity. '0' = keep output camera power down polarity.
'1' = invert output camera power down polarity. '0' = keep input VSYNC polarity.
'1' = invert input VSYNC polarity. '0' = keep input HREF polarity so data is sampled when HREF high.
'1' = invert input HREF polarity so data is sampled when HREF low. '0' = keep pix clk polarity.
'1' = invert pix clk polarity. '0' = VSYNC irq always exists when Frame decimation is enabled.
'1' = VSYNC irq will drop when Frame data are dropped in decipation. "0"= All frame data will be sent.
"1"= only one frame out of two (1/2) will be sent.
"2"= only one frame out of three (1/3) will be sent.
"3"= only one frame out of four (1/4) will be sent. "0"= Pixel Decimation Disabled.
"1"= Pixel Decimation 1/2.
"2"= Pixel Decimation 1/3.
"3"= Pixel Decimation 1/4. "0"= line Decimation Disabled.
"1"= line Decimation 1/2.
"2"= line Decimation 1/3.
"3"= line Decimation 1/4. Controls the Re-ordering of the FIFO data.
In following table, for input data, right comes before left. So YUYV means V comes first.
for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word.

If Bit 26 is '1', byte2 and byte0 is Y.
If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange.
If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26).

input YUYV, output YUYV: "000"
input YVYU, output YUYV: "001"
input UYVY, output YUYV: "110"
input VYUY, output YUYV: "111"

input YUYV, output UYVY: "010"
input YVYU, output UYVY: "011"
input UYVY, output UYVY: "100"
input VYUY, output UYVY: "101"

input YUYV, output YVYU: "001"
input YVYU, output YVYU: "000"
input UYVY, output YVYU: "111"
input VYUY, output YVYU: "110"

input YUYV, output VYUY: "011"
input YVYU, output VYUY: "010"
input UYVY, output VYUY: "101"
input VYUY, output VYUY: "100"

Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation. This reorder is corrected using Bit 26 infomation. "0"= Cropping Disabled.
"1"= Cropping Enabled.
Note: this bit should set to '0' when bit field "DataFormat" is "10" (compressed data) In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled. Debug only. A RGB565 test card is sent to system bus instead of real data from sensor. '1' = FIFO over-write IRQ status.
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = VSYNC rising edge IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = VSYNC falling edge IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = DMA Done IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = FIFO Empty status, not clear-able. Read in the receive FIFO '1' = FIFO over-write enable '1' = VSYNC rising edge enable '1' = VSYNC falling edge enable '1' = DMA Done enable Write '1' to clear FIFO over-write interrupt Write '1' to clear VSYNC rising edge interrupt Write '1' to clear VSYNC falling edge interrupt Write '1' to clear DMA Done interrupt '1' = FIFO over-write cause '1' = VSYNC rising edge cause '1' = VSYNC falling edge cause '1' = DMA Done cause Power down pin of CMOS sensor . Reset pin of CMOS sensor.
Active Low. For the software to clear FIFO. This bit is auto-reset to 0. Power down pin of CMOS sensor . Reset pin of CMOS sensor. start pixel of cropped window. end pixel of cropped window. start line of cropped window. end line of cropped window. swap camera data output [15:0],[31:16]. spi slave enable. spi master enable. yuv out format. 3'b000: data_serial_mux = {Y0,U0,Y1,V0}; 3'b001: data_serial_mux = {Y0,V0,Y1,U0}; 3'b010: data_serial_mux = {U0,Y0,V0,Y1}; 3'b011: data_serial_mux = {U0,Y1,V0,Y0}; 3'b100: data_serial_mux = {V0,Y1,U0,Y0}; 3'b101: data_serial_mux = {V0,Y0,U0,Y1}; 3'b110: data_serial_mux = {Y1,V0,Y0,U0}; 3'b111: data_serial_mux = {Y1,U0,Y0,V0}; overflow rstn only vsync low. overflow_observe_only_vsync_low. overflow_rstn enable big_end_dis overflow inv control href inv control vsync inv control block_num_per_line[9:0] pixels num of a line line_num_per_frame[9:0] lines num of a frame camera_clk_div_num cts_spi_master_reg ssn_cm inv control sck_cm inv control ssn_spi_oen select, 1:from reg 0: from logic ssn_spi_oenb reg sck_spi_oenb select, 1:from reg 0:from logic sck_spi_oenb reg sdo_spi_swap reg,swap camera_spi_0 and camera_spi_1 clk inv control sck double edge enable ssn_wait_length[7:0] init_wait_length[7:0] word_num_per_block[7:0] ssn_cs_delay[1:0] data_receive_choose_bit[1:0] ready_cs_inv ssn_cs_inv eco_bypass_isp line_wait_length[15:0] line_wait_length block_wait_length[7:0] ssn_high_length[7:0] camera_spi_master no ssn mode enable sdo_line_choose_bit[1:0] 0:1 line 1: 2lines 2:4lines data_size_choose_bit 1: from reg 0:from logic image_height_choose_bit 1: from reg 0:from logic image_width_choose_bit 1: from reg 0:from logic block_num_per_packet[9:0] 0: spi data0 delay 0 1: spi data0 delay 2 cycles spi_cam_clk 2: spi data0 delay 3 cycles spi_cam_clk 3: spi data0 delay 4 cycles spi_cam_clk 0: spi data1 delay 0 1: spi data1 delay 2 cycles spi_cam_clk 2: spi data1 delay 3 cycles spi_cam_clk 3: spi data1 delay 4 cycles spi_cam_clk sync code packet_id_data_start packet_id_line_start packet_id_frame_end packet_id_frame_start line_id[15:0] data_id[7:0] observe_data_size_wrong observe_image_height_wrong observe_image_width_wrong observe_line_num_wrong observe_data_id_wrong image_height[15:0] image_width[15:0] num_d_term_en[7:0] term time reg cur_frame_line_num[12:0] data_lp_in_choose_bit[1:0] clk_lp inv trail_data_wrong_choose_bit 1:secelt trail1 0:select trail0 sync_bypass rdata_bit_inv en hs_sync_find en line_packet_enable ecc_bypass data_lane_choose_bit 1:select lane2 0:select lane1 csi_module_enable num_hs_settle[7:0] set hs settle time lp_data_length_choose_bit[2:0] set data length data_clk_lp_posedge_choose[2:0] select delay cycles clk_lp_ck_inv rclr_mask_en rinc_mask_en hs_enable_mask_en den_csi_inv_bit hsync_csi_inv_bit vsync_csi_inv_bit hs_data2_enable_reg hs_data1_enable_reg hs_data1_enable_choose_bit hs_data1_enable_dr 1:select reg 0:select logic data2_terminal_enable_reg data1_terminal_enable_reg data1_terminal_enable_dr 1:select reg 0:select logic lp_data_interrupt_clr, clear flag lp_cmd_interrupt_clr, clear flag lp_data_clr, clear data out lp_cmd_clr, clear cmd out num_hs_settle_clk[15:0], set hs settle counter num_c_term_en[15:0],set clk term counter clk_lp_in_choose_bit pu_lprx_reg pu_hsrx_reg pu_dr, 1:select reg 0:select logic data_pnsw_reg hs_clk_enable_reg hs_clk_enable_choose_bit hs_clk_enable_dr 1:select reg 0:select logic clk_terminal_enable_reg clk_terminal_enable_dr 1:select reg 0:select logic observe_reg_5_low8_choose ecc_error_flag_reg ecc_error_dr csi_channel_sel two_lane_bit_reverse, reverse high and low 8bit data2_lane_bit_reverse 1:select revert data data1_lane_bit_reverse 1:select revert data data2_hs_no_mask 1:data only valid when sync assert data1_hs_no_mask 1:data only valid when sync assert pu_lprx_d2_reg pu_lprx_d1_reg clk_edge_sel clk_x2_sel single_data_lane_en 1:1lane 0:2lanes num_hs_clk_useful[30:0] hs clk useful counter num_hs_clk_useful_en vc_id_set[1:0] data_lp_inv fifo_rclr_8809p_reg fifo_wclr_8809p_reg hs_sync_16bit_8809p_mode d_term_small_8809p_en data_line_inv_8809p_en hs_enable_8809p_mode sp_to_trail_8809p_en trail_wrong_8809p_bypass rinc_trail_8809p_bypass hs_data_enable_8809p_mode hs_clk_enable_8809p_mode data_type_re_check_en sync_id_reg sync_id_dr csi_observe_choose_bit crc_error_flag_reg crc_error_flag_dr 1:select reg 0:select logic csi_rinc_new_mode_dis data_type_dp_reg[5:0], set data type data_type_le_reg line end type data_type_ls_reg line start type data_type_fe_reg frame end type data_type_fs_reg frame start type 1: only support raw8 0:support more type 1:select reg value data_lane_16bits_mode terminal_2_hs_exchage_8809p terminal_1_hs_exchage_8809p data2_terminal_enable_8809p_dr hs_data2_enable_8809p_dr csi_dout_test_8809p_en csi_dout_test_8809p[7:0] num_d_term_en[15:8] num_hs_settle[15:8] hs_data_state[13:0] phy_data_state[14:0] fifo_wfull_almost fifo_wfull fifo_wempty if observe_reg_5_low8_choose=1, out is data_id[7:0], else out is lp_cmd_out[7:0] lp_data_interrupt_flag lp_data_interrupt_flag phy_clk_state[8:0] fifo_rcount[8:0] crc_error err_ecc_corrected_flag err_data_corrected_flag err_data_zero_flag if observe_reg_5_low8_choose=1, out is csi_observe_mon, else out is lp_data_out[63:32] csi_observe_reg_7[31:0] csi_enable dly_sel_clkn_reg,set clkn delay,to csi analog phy dly_sel_clkp_reg,set clkp delay,to csi analog phy dly_sel_data2_reg,set data2 delay,to csi analog phy dly_sel_data1_reg,set data1 delay,to csi analog phy vth_sel,to csi analog phy Direct FIFO Ram Access. They are enabled only in Bist Mode. rstn of dsp for A ctd block, u2.7 format awb_x1_min[8:0]=[awb_ctd_msb[0],awb_x1_min[7:0]] for A ctd block, u2.7 format awb_x1_max[8:0]=[awb_ctd_msb[1],awb_x1_max[7:0]] for A ctd block, u1.7 format for A ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for D65 ctd block, u1.7 format for D65 ctd block, u1.7 format for D65 ctd block, u2.7 format awb_y5_min[8:0]=[awb_ctd_msb[2],awb_y5_min[7:0]] for D65 ctd block, u2.7 format awb_y5_max[8:0]=[awb_ctd_msb[3],awb_y5_max[7:0]] for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format awb_x1_min[8:0]=[awb_x1_min_msb,awb_x1_min[7:0]] awb_x1_max[8:0]=[awb_x1_max_msb,awb_x1_max[7:0]] awb_y5_min[8:0]=[awb_y5_min_msb,awb_y5_min[7:0]] awb_y5_max[8:0]=[awb_y5_max_msb,awb_y5_max[7:0]] 2d0: awb_adj_sig=1 2d1: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 or cbsum_abs>vld_cnt_cb_thr x2 2d2: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x3 or cbsum_abs>vld_cnt_cb_thr x3 2d3: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 and cbsum_abs>vld_cnt_cb_thr x2 2d3: awb_ratio_lmax=4 2d2: awb_ratio_lmax=2 2d1: awb_ratio_lmax=0 2d0: awb_ratio_lmax= according to the proportion of cnt_max and cnt_lmax vsync_end_reg=[vsync_end_high,vsync_end_low] vsync_end_reg=[vsync_end_high,vsync_end_low] line_num = [line_numH,line_numL] pix_num = [pix_numH,pix_numL] not used here not used here 00:YUV/RAW8(para) 01:RAW8(mipi) 10:RAW10(mipi) line_cnt=[line_cnt_H[1:0], [7:0]] line_cnt=[line_cnt_H[1:0], line_cnt_L] 1: kl 0: kldci () 1: kl 0: kldci 1: ku 0: kudci () 1: ku 0: kudci hist 2 00: 0x98regae_dark_hist_reg 01: 0x98regyave_target_RO_reg other: 0x98regyave_contr_reg kl_ofstx1[4:0] = [kl_ofstx1, 1b0] (kl0x80) ku_ofstx1[4:0] = [ku_ofstx1, 1b0] (kl0x80) dk_histx1[4:0] = [dk_histx1, 1b0] (dhist) br_histx1[4:0] = [br_histx1, 1b0] (bhist) swaeswexp/gainnexphw// sw/hwae,SWae, THR_dark[4:0] = [THR_dark, 1'b0] (ytarget-yave THR_darkae) THR_bright[4:0] = [THR_bright,1'b0](yave-ytargetTHR_brightae) ytarget_dec 2d3:4indexytargetregd[3:0]8index08 2d2:2indexytargetregd[3:0]8index016 2d1:1indexytargetregd[3:0]8index032 2d0:1indexytargetregd[3:0]8index064 ytarget_dec 2d3:4indexytargetregc[7:4]8index_max8 2d2:2indexytargetregc[7:4]8index_max16 2d1:1indexytargetregd[7:4]8index_max32 2d0:1indexytargetregd[7:4]8index_max64 1yave_diff_2frame 1THR_big 1bhist>0@is_dark 1index_ofst @nexp @nexp low_th = [[0], lsc_blc_gain_th[7:6]](nexp=low_th) nexp>(8+high_th) Fixed Ythr of contr = [[7:4], 4d0] 1: dynamic yave (Yave) 0: fixed ythr contr_ythr_reg YaveYthrofst (01) upper@Low gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@Low gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 upper@Mid gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@Mid gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 upper@High gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@High gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 @Low gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 @Mid gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 @High gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 Cb@Low gain0x80 just x1.0 Cr@Low gain0x80 just x1.0 Cb@Mid gain0x80 just x1.0 Cr@Mid gain0x80 just x1.0 Cb@High gain0x80 just x1.0 Cr@High gain0x80 just x1.0 @luma/contr/satur(nexp=low_th) not used here @luma/contr/satur(nexp>(8+high_th)) 4'd0: cc_type = 0; //D65 4'd1: cc_type = 1; //U30 4'd2:if(is_outdoor) cc_type = 0; else cc_type = 1; 4'd3:if(ana_gain>=cc_gain_th) cc_type = 0; else cc_type = 1; 4'd4:if(rgain_bigger) cc_type = 0; //D65 else if(bgain_bigger) cc_type = 1; //U30 4'd5: if(is_outdoor) cc_type = 0; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd6: if(is_outdoor) cc_type = 0; else if(ana_gain=cc_gain_th) cc_type = 0; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd7: if(is_outdoor) cc_type = 0; else if(ana_gain=cc_gain_th) cc_type = 1; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd8: if(r_awb_gain_outr_low_non_A)cc_type = 1; else if(r_awb_gain_out(r_low_non_A+8)) cc_type = 0; 4d9: if(awb_idx_max2) cc_type = 1; else if(awb_idx_max2) cc_type = 0; other: SW driven ( reg1c2) nexp>(8+high_th) 1: 0: r_big_th=[awb_cc_type_th_reg[3:0], 2d0] b_big_th=[awb_cc_type_th_reg[7:4], 2d0] 00: YUV422 01: RGB565 10: raw bayer 11: clip out 00:YUYV 01:YVYU 10:UYVY 11:VYUY (Note:[2] uv_sel 0:UV 1:VU) Case(rgb_mode_reg) @clip out 3'd0: to_n_clp_data 3'd1: y_data 3'd2: cnr_1d_cb 3'd3: cnr_1d_cr 3'd4: c_data 3'd5: yc2r_data 3'd6: yc2g_data 3'd7: yc2b_data Note:rgb_mode_reg[0] is also used to 1, select the line of sub_YUV output not used, sca_reg=1:sub mode bypass vsync_in and hsync_in Line_num=[lin_num_l_reg[5:0], 3d0] Pix_num=[pix_num_l_reg[6:0], 3d0] HsyncNvsync Mvsync top_dummy>16, vtop_dummy=top_dummy-[7:4] 1blc[ku, kl] 1:nexp[3:0] 0:mono_color 1: dpc_out 0: bayer_data 1: enable 0: disable y_gamma_en = is_outdoor ? scg_reg[5] : scg_reg[4] 1: SDI 0: BT.601 1: [ae_ok, nexp_sel[1:0], awb_ok, exp[11:8]] 0: [ae_ok, 1b0, nexp_sel[1:0], awb_ok, exp[10:8]] labview (0x00)0 (0x00)0 (0x00)0 (0x13)19 (0x10)16 (0x08)8 (0x20)32 (0x1c)28 (0x10)16 (0x36)54 (0x30)48 (0x20)32 (0x49)73 (0x43)67 (0x30)48 (0x5a)90 (0x54)84 (0x40)64 (0x6b)107 (0x65)101 (0x50)80 (0x7b)123 (0x75)117 (0x60)96 RW(0x98)152 (0x93)147 (0x80)128 (0xb4)180 (0xb0)176 (0xa0)160 (0xce)206 (0xcb)203 (0xc0)192 (0xe7)231 (0xe6)230 (0xe0)224 0.75 0.8 1.0 r_gain_manual 2.6 format g_gain_manual 2.6 format b_gain_manual 2.6 format 2.6 format 2.6 format 2.6 format 2.6 format also update cc_type,gamma_type,is_outdoor 00: AWB 01: AWB 10: yaveAWB 11: nexpAWB 1: mon ae index 0:mon awb_debug 0yave 1yave 2yave 3yave 07/0f/17/1f Yave 00: y2ave x1.0 01: y2ave x1.5 10: y3ave x1.0 11: y3ave x1.5 1:plus bh 0: only yave 1:plus bh 0: only ywave pcnt_left =[ae_win_start_reg[3:0] ,1'd0] lcnt_top =[ae_win_start_reg[7:4] ,1'd0] ae(yave) win_width = [ae_win_width[7:0], 2'd0] ae(yave) ae_win_height = [ae_win_height[7:0], 1'd0] exp[7:0](ae_enMCUexp_init[6:0]indexae) exp[11:8] 10msexp (ytarget) THR_dark(reg41) THR22index1 THR24index2 THR26index4+ofst0 THR28index8+ofst1 index16 (ytarget) THR_bright(reg41) THR22index1 THR24index2 THR26index4+ofst0 THR28index8+ofst1 index16 Bh = Bh_mean * bh_factor /8 bh_factor = is_outdoor? bh_factor_outdoor : bh_factor_indoor 00: curr frame 01: 2 frame ave 10: 3 frame ave 11: 4 frame ave awb_mon_out[7:0][cbsum_abs_eq, crsum_abs_eq]SWAWB 2.0xr/b 4.0xr/b 0: 1frame or 2frame [ 2] 0:readback blc 1: readback awb [1:0] 0: crsum_abs 1:cbsum_abs 2: vld_cnt 3:awb_idx_lmax and max AWB 3'd0:awb_vld=vld_max||(vld_lmax and awb_ratio_lmax); 3'd1: awb_vld = awb_vld1; 3'd2: awb_vld = awb_vld2; 3'd3: awb_vld = awb_vld3; 3'd4: awb_vld = awb_vld4; 3'd5: awb_vld = awb_vld5; 3'd6: awb_vld =!skin_vld; 3'd7: awb_vld = awb_vld1|awb_vld2|awb_vld3| awb_vld4 | awb_vld5; Y Y_maxAWB Levelawb_stop Levelawb_stop Levelawb_stop Levelawb_stop [7:0]awb_algo_thr Y > cr_abs+cb_abs+awb_algo_reg // 0: (vld_cntawb_vld_thr) 1: (vld_cntawb_vld_thr)and(crsum_absawb_vld_thr)and(cbsum_absawb_vld_thr) 0: awb_stopcb/cr 1: 0: use CTD block to detect skin 1: use cb,cr to detect skin 0: cb+cr 1: cb/cr awb_vld_thr = [awb_ctrl4[7:0], 4'hf] 1: 0 y_low_thr = [1h0, y_thr_reg[7:3], 2'h0] y_high_thr = ~y_low_thr Only for awb_adj, yaveAWB y_low_limit = y_ave_target - [y_lmt_offset_reg[2:0],4'd0] not used here Only for awb_adj, yaveAWB y_high_limit = y_ave_target+ [y_lmt_offset_reg[6:4],4'd0] nexp=low_th not used here nexp>(8+high_th) yave_target (yave_target0) yave_target (yave_target0) not used here 1reg93vbright_hist 1reg94vdark_hist display edge pixel for sharpness Ywave+bhist histYwave bright hist Yave+bhisthistYave exp_out[10:8] nexp_selbnr/dpc/int_dif 00: cr_lt_1x 01: cr_gt_1x 10: cr_gt_2x 11: cr_gt_4x 00: cb_lt_1x 01: cb_gt_1x 10: cb_gt_2x 11: cb_gt_4x 0:crsum (5R B+4G) 1:crsum (5R B+4G) 0:cbsum (3B R+2G) 1:cbsum (3B R+2G) 0: crsum_abs cbsum_abs (crsum) 1: crsum_abs cbsum_abs (cbsum) ae_index Note: regd[5]? ae_vbright_hist : reg75[7]? ae_index[6:0] : awb_debug; YUVnexp vdark_hist Note: regd[6]? ae_vdark_hist : reg5F[1]? nexp[3:0] : mono_color yavehist Vbh_sel[1]? Yave_contr_reg : Vbh_sel[0]? Yave_target_RO_reg : ae_dark_hist NoteVbh_sel[1:0] = reg3d[7:6] 3d0: gamma_type=0 3d1: gamma_type=1 3d2: gamma_type=is_outdoor 3d3: gamma_type=ana_gain>=gamma_gain_th default:gamma_type=gamma_type_sw nexp>(8+high_th) 00:QVGA 240x320 01:QVGA 320x240 10:CIF 352x288 11:VGA 640x480 line_sel = [line_init_H, blc_line_reg[7:0]] lsc gain@ lsc gain@ nexp=low_th nexp>(8+high_th) low_th = [csup_gain_low_th_H, [7:6]](nexp=low_th) 2'd0: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_01] 2'd1: [blc_out0_reg,blc_out1_reg] = [blc_10, blc_11] 2'd2: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_10] 2'd3: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_11] 0: plus 1: minus 00: 1frame 01: 2frame ave 10: 3frame ave 11: 4frame ave blc00_ofst =[blc_init_reg[3:0] , 1'b0] blc01_ofst =[blc_init_reg[7:4] , 1'b0] blc10_ofst =[blc_offset_reg[3:0] , 1'b0] blc11_ofst =[blc_offset_reg[7:4] , 1'b0] High limit of black level pixel blcofst y_cent=[3:0]+240 x_cent=[7:4]+320 CNR CNR 1: 0: edge monitor 3d0: never skip 3d1: skip 2/8 skin point 3d2: skip 3/8 skin point 3d3: skip 4/8 skin point 3d4: skip 5/8 skin point 3d5: skip 6/8 skin point 3d6: skip 7/8 skin point 3d7: skip 8/8 skin point cnr_thr_v = [cnr_thr[2:0], 2'd3] enable cnr_thr_h = [cnr_thr[6:4], 2'd3] enable ~awb_mon_sel? blc_out0_reg : kukl_sel ? kl : awb_mon_out[7:0] ~awb_mon_sel? blc_out1_reg : kukl_sel ? ku : awb_mon_out[15:8] Note: awb_mon_sel = reg1[2] Kukl_sel = reg5F[0] dpc on 1: median 0:adp_median sel=(nexp[3:0]>dpc_ctrl0[3:2])? 1 : dpc_ctrl0[1] This adp_med is used in int_dif_data and nrf_data_out not used here 1:gausian filter 0:median filter bayer nr on cc on 00: always not meet 01: all round point must meet 10: can be one except point 11: can be two except point 00: can be three sign diff with other 01: can be two sign diff with other 10: can be one sign diff with other 11: 8 same sign 1: gausian filter 0:median filter Y_thr @ Y_thr @mid Y_thr @ cfa_v_thr[2:0] not used here cfa_h_thr[2:0] not used here 0: inc 1:dec nexp=low_th @bnr/dpc/int_dif/sharp/cnr not used here nexp>(8+high_th) @bnr/dpc/int_dif/sharp/cnr bnr low frequency str @Low gain @ (ff) bnr high frequency str @Low gain (ff) 4.4 format, 16x ~ 1/16x @Low gain HF bnr low frequency str @Mid gain (ff) bnr high frequency str @Mid gain (ff) 4.4 format, 16x ~ 1/16x @Mid gain HF bnr low frequency str @high gain @ (ff) bnr high frequency str @high gain (ff) 4.4 format, 16x ~ 1/16x @high gain HF 0: 9 1:7 2: 5 3:3 4: median 5: adp_median cfa_h_thr=[intp_cfa_h_thr[7:0], intp_cfa_hv[6:4]] cfa_v_thr=[intp_cfa_v_thr[7:0], intp_cfa_hv[2:0]] gf_lmt_thr=[3d0, intp_gf_lmt_thr_reg] S7 format, before cc S7 format, before cc S7 format, before cc S1.6 format, x1=64, cc00+cc01+cc02=1 S1.6 format, x1=64, cc10+cc11+cc12=1 S1.6 format, x1=64, cc20+cc21+cc22=1 S7 format, after cc S7 format, after cc S7 format, after cc S7 format, before cc S7 format, before cc S7 format, before cc S1.6 format, x1=64, cc00+cc01+cc02=1 S1.6 format, x1=64, cc10+cc11+cc12=1 S1.6 format, x1=64, cc20+cc21+cc22=1 sharp data db/da/d9 sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) 0: delay_df 1: delay_de 2: delay_dd 3: delay_dc 1:ppdif_sum 0:pp_dif (8) plus @Low gain (2.6 format)@ Sharp@Low gain (edge) plus @Mid gain (2.6 format) Sharp@Mid gain (edge) plus @high gain (2.6 format)@ Sharp@high gain (edge) (Ey) 2d0:Ey_H/V/D1/D2 2d1: 2d2: 2d3: (sharpness) 00: if(i_y_data8'ha0) sharp_data = sharp_out[6:2]; else if(i_y_data8'h80) sharp_data = sharp_out[6:1]; else sharp_data = sharp_out[6:0]; 01: 0x80pixelsharpness 10: 0x90pixelsharpness 11: No change AEYin 00:y=yuv_y 01:y=y_gamma // after ygamma 10:y=luma_y_out // after y_luma 11:y=contr_y_out // after y_contr GMYc @low gain GMYc128Ey @low gain GMYc128Ey 4.4 format, 16x ~ 1/16x @low gain HF @Mid gain GMYc128Ey @Mid gain GMYc128Ey 4.4 format, 16x ~ 1/16x @Mid gain HF @high gain GMYc128Ey @high gain GMYc128Ey 4.4 format, 16x ~ 1/16x @high gain HF sinx[7:0]=256*sin(x*pi/180) cosx[7:0]=256*cos(x*pi/180) cosx[7] fixed as 1, As abs(x) = pi/4 1: sinx is negative 0: sinx is positive CNR@Mid gain CNR@Low gain CNR@High gain Center point smaller than around, black point Center point bigger than around, white point E00 E00 E00 max is 3Line E01 E01 E01 max is 7Line E02max is 7F E02 E02 max is 15Line E1 (64) E1 (1E) E2 (64) E2 (2E) E3 (64) E3 (3E) E4 (64) E4 (4E) E5 (64) E5 (5E) E6 (64) E6 (6E) E7 (64) E7 (7E) E8 (64) E8 (8E) E9 (64) E9 (9E) Ea (64) Ea (aE) Eb (64) Eb (bE) Ec (64) Ec (cE) Ed (64) Ed (dE) Y_thr7 (for 2 dead point) @ Y_thr7 (for 2 dead point) @ mid Y_thr7 (for 2 dead point) @ 0: check one black dead point 1: don't check one black dead point 0: check 2 black dead point 1: don't check 2 black dead point 0: don't check 2 dead point 1: check 2 dead point (Note) 0: check one black dead point 1: don't check one black dead point (Note) 0: check 2 black dead point 1: don't check 2 black dead point (Note) 0: don't check 2 dead point 1: check 2 dead point not used here 2E 12 3E 12 4E 12 5E 12 6E 12 7E 12 8E 12 9E 12 awb_win_height = [[7:0],1'd0] //4:3 and keep height as even number blue: 0x72 red: 0xD4 brown:0xAB blue: 0xD4 red: 0x64 brown:0x60 0x20~ff (x1~8) () 0x20~ff (x1~8) () If bhist>bhist_too_big_thr, then bhist_too_big If bhist>bhist_big_thr, then bhist_big Y level of bhist and 4pbhist outdoor_th=[outdoor_th_reg[3:0], 4'd0] non_outdoor_th=[outdoor_th_reg[7:4], 4'd0] Low limit of rgain = [[7:2], 2d0] High limit of rgain = [[7:2], 2d0] Low limit of bgain = [[7:2], 2d0] High limit of bgain = [[7:2], 2d0] awb_win_y_start = [[3:0], 2'd0]; awb_win_x_start = [[7:4], 2'd0]; awb_win_width =[[7:0],2'd0]; //4:3 and keep height as even number Y level of dark_hist for skin for skin for skin for skin for skin for skin for mono color for mono color for mono color for mono color for mono color for mono color 0yave 1yave 2yave 3yave 0yave 1yave 2yave 3yave 0: win yave 1: ywave ae ywave ae ywave QVGA 240x320 :8d60 QVGA 320x240: 8d80 CIF 352x288: 8d88 VGA 640x480: 8d160 QVGA 240x320 :8d80 QVGA 320x240: 8d60 CIF 352x288: 8d72 VGA 640x480: 8d120 0: x1(CIFx1) 1:x1.5 yave pcnt_sta=[[3:0], 1b0] yave lcnt_sta=[[7:4], 1b0] yave Width=[[7:0], 2d0] QVGA 240x320 :10d216 QVGA 320x240: 10d304 CIF 352x288: 10d304 VGA 640x480: 10d596 yave Height=[[7:0], 1d0] QVGA 240x320 :10d304 QVGA 320x240: 10d216 CIF 352x288: 10d216 VGA 640x480: 10d440 not used here 3'd0: is_outdoor = 0; 3'd1: is_outdoor = 1; 3'd2: if(ana_gain==0) begin if(expoutdoor_th) is_outdoor = 1; else if(expnon_outdoor_th) is_outdoor = 0; end else is_outdoor = 0; 3'd3: if(ana_gain==0 and rgain_bigger) begin if(expoutdoor_th) is_outdoor = 1; else if(expnon_outdoor_th) is_outdoor = 0; end else is_outdoor = 0; default: if(vsync_rp_d and sw_update_en) is_outdoor = is_outdoor_sw; 1: when is_outdoor=1, only detect white point at D65 and Indoor CTD block 0: dont care is_outdoor, detect white point at all ctd block awb_stop_cr_pos_level =[[3],awb_stop_reg[7:6]]; awb_stop_cr_neg_level =[[2],awb_stop_reg[5:4]]; awb_stop_cb_pos_level =[[1],awb_stop_reg[3:2]]; awb_stop_cb_neg_level =[[0],awb_stop_reg[1:0]]; awb_adj_again = [2'b11, [5:4]] 1: add awb_algo_thr condition to detect white point@A 0: detect white point according to A ctd block 0: normal(no scale) 1: sub(yuv sub mode) 2: sca_320x240(1/2) 3: sca_176x144(1/3) 4: sca_160x120(1/4) 5: sca352x288(2/3) 6: sca352x288(3/5) 7: 3/4 Ee (64) Ee (eE) Ef (64) Ef (fE) ae_thr_big = [reg1CA[3:0],2d0]@dark ae_thr_big = [reg1CA[7:4],2d0]@bright sharp gain @low gain(2.6 format) sharp gain @medium gain(2.6 format) sharp gain @high gain(2.6 format) sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) Y = Y_min ( AWB) Y level of vbright_hist Y level of vdark_hist This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
Secure cpu can use all channels, but non-secure cpu only can use non-secure channel.
Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec.
When non-secure cpu read this register, the return value will automatic exlude the secure channel.
00000 = use Channel0
00001 = use Channel1
00010 = use Channel2
...
01111 = use Channel15
11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example:
0000_0000 = All channels registers can be accessed by secure master or non-secure master.
0000_0001 = Ch0 registers can only be accessed by secure master.
0000_0010 = Ch1 registers can only be accessed by secure master.
0000_0100 = Ch2 registers can only be accessed by secure master.
0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master.
0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master.
......
all 1 = all channels registers can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example:
0000_0000 = All channels dma are non-secure master.
0000_0001 = Ch0 dma is secure master.
0000_0010 = Ch1 dma is secure master.
0000_0100 = Ch2 dma is secure master.
0000_0101 = Ch0 and Ch2 dma are secure master.
0000_0111 = Ch0, Ch1 and Ch2 dma are secure master.
......
all 1 = all channels dma are secure master. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB
Exchange the write data to fifo halfword MSB or LSB
Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. Address of data to be read or written. These two bits indicates element data size.
when "00" = "byte".
when "01" = "half word".
when "10" = "word". This bit indicates command is read or write.
when "0" = "Read".
when "1" = "Write". Those bits are data to be read or written by IFC. When read, this bit is used for event semaphore.
'0' = no new event should be programed.
'1' = no pending event, new event is authorised.
If host is not enabled, this bit is always '1'. However in this case, any event written will be ignored.
When Write, this bit is the least significant bit for a 32-bit event. These bits combined with bit0 consists a 32-bit event number. If a new event is written before the previous event has been sent, it will be ignored. When '1', force the debug host on, use clock UART if clock host is not detected. This bit indicates if clock host is detected to be on or not.
'0' = no clock host.
'1' = clock host detected. Status which can be written through debug uart interface into a debug host internal register and read by APB. write in this bit will reset h2p status register. Status which can be written by APB and read through debug uart interface as a debug host internal register. when write '1', clear the xcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the xcpu irq status. when write '1', clear the bcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the bcpu irq status. Allows to turn off the UART:
0 = Disable
1 = Enable Number of data bits per character (least significant bit first):
0 = 7 bits
1 = 8 bits
This bit will be masked to '1' if debug host is enabled. Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0).
0 = one stop bit is transmitted in the serial data.
1 = two stop bits are generated and transmitted in the serial data out.
This bit will be masked to '0' if debug host is enabled. Parity is enabled when this bit is set.
This bit will be masked to '0' if debug host is enabled. Controls the parity format when parity is enabled:
00 = an odd number of received 1 bits is checked, or transmitted (the parity bit is included).
01 = an even number of received 1 bits is checked or transmitted (the parity bit is included).
10 = a space is generated and received as parity bit.
11 = a mark is generated and received as parity bit.
These bit will be ignored if debug host is enabled. Sends a break signal by holding the Uart_Tx line low until this bit is cleared.
This bit will be masked to '0' if debug host is enabled. reset rx fifo. reset tx fifo. Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used:
00 = no transmit flow control.
01 = transmit XON1/XOFF1 as flow control bytes
10 = transmit XON2/XOFF2 as flow control bytes
11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes
When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used:
00 = no receive flow control
01 = receive XON1/XOFF1 as flow control bytes
10 = receive XON2/XOFF2 as flow control bytes
11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes

Note: If single XON/XOFF character is used for flow contol, the received XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is received when XOFF is expected.
If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. Otherwise they will be considered as data. This is also the case if XOFF1 is followed by character other than XOFF2.
When soft flow control characters or backslash are encountered in the data file, they will be inverted and a backslash will be added before them. for example, if tx data is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON). When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16.
0 = (BCLK = SCLK / 4)
1 = (BCLK = SCLK / 16)
This bit will be masked to '0' if debug host is enabled. When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details).
This bit will be masked to '0' if debug host is enabled. Controls the Uart_RTS output (not directly in auto flow control mode).
0 = the Uart_RTS will be inactive high
1 = the Uart_RTS will be active low
This bit will be masked to '1' if debug host is enabled. Enables the auto flow control.
In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0), If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register). Tx data flow is stopped If Uart_CTS become inactive high.
If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS bit in CMD_Set register. Uart_CTS will not take effect.

In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0), If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register).
If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit in CMD_Set register. Tx data flow will be stoped when XOFF is received either this bit is enable or disabled.

This bit will be masked to '1' if debug host is enabled. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept.
This bit will be masked to '0' if debug host is enabled. HST TXD output enable. '0' enable. Length of a break, in number of bits.
This bit will be masked to "1011" if debug host is enabled. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. This bit indicates that the UART is receiving a byte. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), This bit is set when the Uart_CTS line changed since the last time this register has been written.
In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), This bit is set when received XON/XOFF status changed since the last time this register has been writtern.
This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), current value of the Uart_CTS line.
'1' = Tx not allowed.
'0' = Tx allowed.
In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), current state of software flow control.
'1' = when XOFF received.
'0' = when XON received. This bit is set when Tx Fifo Reset command is received by CTRL register and is cleared when Tx fifo reset process has finished. This bit is set when Rx Fifo Reset command is received by CTRL register and is cleared when Rx fifo reset process has finished. This bit is set when bit enable is changed from '0' to '1' or from '1' to '0', it is cleared when the enable process has finished. This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling Rx RTS too early. The UART_RECEIVE_BUFFER register is a read-only register that contains the data byte received on the serial input port. This register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Clear to send signal change or XON/XOFF detected. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Pulse detected on Uart_Dma_Tx_Done_H signal. Pulse detected on Uart_Dma_Rx_Done_H signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Defines the threshold level at which the Data Available Interrupt will be generated.
The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Defines the threshold level at which the Data Needed Interrupt will be generated.
The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC).
The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. XON1 character value. Reset Value is CTRL-Q 0x11. XOFF1 character value. Reset Value is CTRL-S 0x13 XON2 character value. XOFF2 character value. These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces: 0 Group 1 interrupts not forward. 1 Group 1 interrupts forwarded, subject to the priority rules. Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces: 0 Group 0 interrupts not forwarded. 1 Group 0 interrupts forwarded, subject to the priority rules. If the GIC implements the Security Extensions, the value of this field is the maximum number of implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111), see Configuration lockdown on page 4-82. If this field is 0b00000 then the GIC does not implement configuration lockdown. If the GIC does not implement the Security Extensions, this field is reserved. Indicates whether the GIC implements the Security Extensions. 0 Security Extensions not implemented. 1 Security Extensions implemented. Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is one more than the value of this field, for example if this field is 0b011, there are four CPU interfaces. If the GIC implements the Virtualization Extensions, this is also the number of virtual CPU interfaces. Indicates the maximum number of interrupts that the GIC supports. If ITLinesNumber=N, the maximum number of interrupts is 32(N+1). The interrupt ID range is from 0 to (number of IDs C 1). For example: 0b00011 Up to 128 interrupt lines, interrupt IDs 0-127. The maximum number of interrupts is 1020 (0b11111). See the text in this section for more information. Regardless of the range of interrupt IDs defined by this field, interrupt IDs 1020-1023 are reserved for special purposes. Product ID An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish product variants, or major revisions of a product. An IMPLEMENTATION DEFINED revision number. Typically, this field is used to distinguish minor revisions of a product. Contains the JEP106 code of the company that implemented the GIC Distributor: Bits [11:8] The JEP106 continuation code of the implementer. For an ARM implementation, this field is 0x4. Bits [7] Always 0. Bits [6:0] The JEP106 identity code of the implementer. For an ARM implementation, bits[7:0] are 0x3B. The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC. Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. Accessible by Secure accesses Only. For each bit: 0 The corresponding interrupt is Group 0. 1 The corresponding interrupt is Group 1.For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_IGROUPRn number, n, is given by n = m DIV 32 b. the offset of the required GICD_IGROUPR is (0x080 + (4*n)) c. the bit number of the required group status bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC. For each bit: Reads 0 The corresponding interrupt is not pending on any processor. 1 a. For PPIs and SGIs, the corresponding interrupt is pendinga on this processor. b. For SPIs, the corresponding interrupt is pendinga on at least one processor. Writes For SPIs and PPIs: 0 Has no effect. 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered Changes the status of the corresponding interrupt to: a.pending if it was previously inactive b.active and pending if it was previously active. Has no effect if the interrupt is already pending. Level sensitive If the corresponding interrupt is not pendinga, changes the status of the corresponding interrupt to: a. pending if it was previously inactive b. active and pending if it was previously active. If the interrupt is already pending: a. because of a write to the GICD_ISPENDR, the write has no effect. b. because the corresponding interrupt signal is asserted, the write has no effect on the status of the interrupt, but the interrupt remains pendinga if the interrupt signal is deasserted. For SGIs, the write is ignored. SGIs have their own Set-Pending registers. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ISPENDR number, n, is given by n = m DIV 32 b. the offset of the required GICD_ISPENDR is (0x200 + (4*n)) c. the bit number of the required Set-pending bit in this register is m MOD 32. The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. For each bit: Reads 0 The corresponding interrupt is not pending on any processor. 1 a. For SGIs and PPIs, the corresponding interrupt is pendinga on this processor. b. For SPIs, the corresponding interrupt is pendinga on at least one processor. Writes For SPIs and PPIs: 0 Has no effect. 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered Changes the status of the corresponding interrupt to: a. inactive if it was previously pending b. active if it was previously active and pending. Has no effect if the interrupt is not pending. Level-sensitive If the corresponding interrupt is pendinga only because of a write to GICD_ISPENDRn, the write changes the status of the interrupt to: a. inactive if it was previously pending b. active if it was previously active and pending. Otherwise the interrupt remains pending if the interrupt signal remains asserted. For SGIs, the write is ignored. SGIs have their own Clear-Pending registers. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32 b. the offset of the required GICD_ICPENDR is (0x280 + (4*n)) c. the bit number of the required Set-pending bit in this register is m MOD 32. The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports. For each bit: Reads 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active. Writes 0 Has no effect. 1 Activates the corresponding interrupt, if it is not already active. If the interrupt is already active, the write has no effect. After a write of 1 to this bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32 b. the offset of the required GICD_ISACTIVERn is (0x300 + (4*n)) c. the bit number of the required Set-active bit in this register is m MOD 32. The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC supports. For each bit: Reads 0 The corresponding interrupt is not activea. 1 The corresponding interrupt is activea. Writes 0 Has no effect. 1 Deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect. After a write of 1 to this bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICACTIVERn number, n, is given by n = m DIV 32 b. the offset of the required GICD_ICACTIVERn is (0x380 + (4*n)) c. the bit number of the required Clear-active bit in this register is m MOD 32. The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the GIC. Each priority field holds a priority value, from an IMPLEMENTATION DEFINED range. The lower the value, the greater the priority of the corresponding interrupt. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_IPRIORITYRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_IPRIORITYRn is (0x400 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. Asserted when the PPI inputs to the Distributor are active. ID 31 nLEGACYIRQ signal ID 30 Non-secure physical timer event ID 29 Secure physical timer event ID 28 nLEGACYFIQ signal ID 27 Virtual timer event ID 26 Hypervisor timer event ID 25 Virtual maintenance interrupt. Returns the status of the IRQS inputs on the Distributor. For each bit: 0 IRQS is LOW 1 IRQS is HIGH. The GICD_NSACRs enable Secure software to permit Non-secure software on a particular processor to create and manage Group 0 interrupts. They provide an access control for each implemented interrupt. If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible values of the field are: 0b00 No Non-secure access is permitted to fields associated with the corresponding interrupt. 0b01 Non-secure write access is permitted to fields associated with the corresponding interrupt in the GICD_ISPENDRn registers. A Non-secure write access to GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding interrupt. 0b10 Adds Non-secure write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDRn registers. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers. 0b11 Adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ITARGETSRn registers. The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are RAZ/WI. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_NSACR number, n, is given by n = m DIV 16 b. the offset of the required GICD_NSACRn is (0xE00 + (4*n)). Determines how the distributor must process the requested SGI: 0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda. 0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the interrupt. 0b10 Forward the interrupt only to the CPU interface of the processor that requested the interrupt. 0b11 Reserved. When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the interrupt. Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface. If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface. Implemented only if the GIC includes the Security Extensions. Specifies the required security value of the SGI: 0 Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface. 1 Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if the SGI is configured as Group 1 on that interface. This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write. The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source processor combination. For each bit: Reads 0 SGI x from the corresponding processor is not pending. 1 SGI x from the corresponding processor is pending. Writes 0 Has no effect. 1 Removes the pending state of SGI x for the corresponding processor. For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_CPENDSGIR register number, n, is given by n = x DIV 4 b. the offset of the required GICD_CPENDSGIR is (0xF10 + (4*n)); c. the SGI Clear-pending field offset, y, is given by y = x MOD 4 d. the required bit in the SGI x Clear-pending field is bit C. The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and source processor combination. For each bit: Reads 0 SGI x for the corresponding processor is not pendinga. 1 SGI x for the corresponding processor is pendinga. Writes 0 Has no effect. 1 Adds the pending state of SGI x for the corresponding processor, if it is not already pending. If SGI x is already pending for the corresponding processor then the write has no effect. For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4 b. the offset of the required GICD_SPENDSGIR is (0xF20 + (4*n)) c. the SGI Set-pending field offset, y, is given by y = x MOD 4 d. the required bit in the SGI x Set-pending field is bit C. Alias of EOImodeNS from the Non-secure copy of this register. Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. In a GIC implementation that includes the Security Extensions, this control applies only to Secure accesses, and the EOImodeNS bit controls the behavior of Non-secure accesses to these registers: 0 GICC_EOIR has both priority drop and deactivate interrupt functionality. Accesses to the GICC_DIR are UNPREDICTABLE. 1 GICC_EOIR has priority drop functionality only. GICC_DIR has deactivate interrupt functionality. Alias of IRQBypDisGrp1 from the Non-secure copy of this register. Alias of FIQBypDisGrp1 from the Non-secure copy of this register. When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass IRQ signal is signaled to the processor: 0 Bypass IRQ signal is signaled to the processor 1 Bypass IRQ signal is not signaled to the processor. When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass FIQ signal is signaled to the processor: 0 Bypass FIQ signal is signaled to the processor 1 Bypass FIQ signal is not signaled to the processor. Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts. 0 To determine any preemption, use: ? the GICC_BPR for Group 0 interrupts ? the GICC_ABPR for Group 1 interrupts. 1 To determine any preemption use the GICC_BPR for both Group 0 and Group 1 interrupts. Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal. 0 Signal Group 0 interrupts using the IRQ signal. 1 Signal Group 0 interrupts using the FIQ signal. The GIC always signals Group 1 interrupts using the IRQ signal. When the highest priority pending interrupt is a Group 1 interrupt, determines both: ? whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID ? whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or returns a spurious interrupt ID. 0 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR or the GICC_HPPIR returns an Interrupt ID of 1022. A read of the GICC_IAR does not acknowledge the interrupt, and has no effect on the pending status of the interrupt. 1 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR or the GICC_HPPIR returns the Interrupt ID of the Group 1 interrupt. A read of GICC_IAR acknowledges and Activates the interrupt. Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor: 0 Disable signaling of Group 1 interrupts. 1 Enable signaling of Group 1 interrupts. Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor: 0 Disable signaling of Group 0 interrupts. 1 Enable signaling of Group 0 interrupts. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor. If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows: 128 supported levels Bit [0] = 0. 64 supported levels Bit [1:0] = 0b00. 32 supported levels Bit [2:0] = 0b000. 16 supported levels Bit [3:0] = 0b0000. The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field. The minimum value of the Binary Point Register depends on which security-banked copy is considered: 0x2 Secure copy 0x3 Non-secure copy For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. The interrupt ID. On a multiprocessor implementation, if the write refers to an SGI, this the CPUID value from the corresponding GICC_IAR access. In all other cases this field SBZ. The Interrupt ID value from the corresponding GICC_IAR access. The current running priority on the CPU interface. On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. In all other cases this field is RAZ. The interrupt ID of the highest priority pending interrupt. See Table 4-42 on page 4-144 for more information about the result of Non-secure reads of the GICC_HPPIR when the GIC implements the Security Extensions. A Binary Point Register for handling Group 1 interrupts. CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. Interrupt ID The interrupt ID. On a multiprocessor implementation, when processing an SGI, this field must contain the CPUID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, access. In all other cases this field SBZ. The Interrupt ID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, access. On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. In all other cases this field is RAZ. The interrupt ID of the highest priority pending interrupt, if that interrupt is a Group 1 interrupt. Otherwise, the spurious interrupt ID, 1023. Active Priorities Registers NonSecure Active Priorities Registers An IMPLEMENTATION DEFINED product identifier. The value of this field depends on the GIC architecture version, as follows: ? 0x1 for GICv1 ? 0x2 for GICv2. An IMPLEMENTATION DEFINED revision number for the CPU interface. Contains the JEP106 code of the company that implemented the GIC CPU interface: Bits [11:8] The JEP106 continuation code of the implementer. Bit [7] Always 0. Bits [6:0] The JEP106 identity code of the implementer. For an SGI in a multiprocessor implementation, this field identifies the processor that requested the interrupt. For all other interrupts this field is RAZ. The interrupt ID Maximum output width in pixels Number of bits coding position in virtual screen Number of bits of fractional part of internal fixed point values Number of bits of internal fixed point values Number of bits for stride storage Starts the image transfer. Autoreset High while image accelerator is busy High while LCD controller is busy High when End Of Frame IRQ has been generated.
To clear it, write 1 in this bit or in eof_status. Unmasked version of eof_cause.
To clear it, write 1 in this bit or in eof_status. EOF interrupt generation mask:
0: EOF IRQ disabled
1: EOF IRQ enabled LCD Region Of Interest Top-Left pixel x-axis LCD Region Of Interest Top-Left pixel y-axis LCD Region Of Interest Bottom-Right pixel x-axis LCD Region Of Interest Bottom-Right pixel y-axis Blue component of the ROI background color Green component of the ROI background color Red component of the ROI background color Input image format
00b: RGB565 pixel packed
01b: YUV4:2:2 pixel packed (UYVY)
10b: YUV4:2:2 pixel packed (YUYV)
11b: YUV4:2:0 planar (IYUV) Image stride in bytes (of Y component for planar formats).
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Defines Layer's activity:
0: Layer disabled
1: Layer active Video Layer (layer 0) Top-Left pixel x-axis position Video Layer (layer 0) Top-Left pixel y-axis position Video Layer (layer 0) Bottom-Right pixel x-axis position Video Layer (layer 0) Bottom-Right pixel y-axis position Number of lines of source image (idem gd_vl_br_ppos.y1 when vertical scaling factor is one). Number of columns of source image (idem gd_vl_br_ppos.x1 when vertical scaling factor is one). Blue component of the Chroma Key Green component of the Chroma Key Red component of the Chroma Key Enables the Chroma Keying Allows a range of color for the Chroma Keying:
000b: exact color match
001b: disregard 1 LSBit of each color component for matching
011b: disregard 2 LSBit of each color component for matching
111b: disregard 3 LSBit of each color component for matching Layer Alpha blending coefficient Layer rotation selection
00b: No rotation
01b: 90 degrees rotation (clockwise)
10b: reserved
11b: reserved Layer depth
00b: Video layer behind all Overlay layers
01b: Video layer between Overlay layers 1 and 0
10b: Video layer between Overlay layers 2 and 1
11b: Video layer on top of all Overlay layers Dword-aligned address of the Y component (or RGB) of the source image Dword-aligned address of the U component of the source image Dword-aligned address of the V component of the source image Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn. Input image format
0: RGB565 pixel packed
1: ARGB8888 pixel packed
others: reserved Image stride in 16-bits word.
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Image stride in 16-bits word.
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Defines Layer's activity:
0: Layer disabled
1: Layer active Overlay Layer (layer X+1) Top-Left pixel x-axis position Overlay Layer (layer X+1) Top-Left pixel y-axis position Overlay Layer (layer X+1) Bottom-Right pixel x-axis position Overlay Layer (layer X+1) Bottom-Right pixel y-axis position Blue component of the Chroma Key Green component of the Chroma Key Red component of the Chroma Key Enables the Chroma Keying Allows a range of color for the Chroma Keying:
000b: exact color match
001b: disregard 1 LSBit of each color component for matching
011b: disregard 2 LSBit of each color component for matching
111b: disregard 3 LSBit of each color component for matching Layer Alpha blending coefficient Dword-aligned address of the source image Destination Selection Output format
000b: 8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB
001b: 8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB
010b: 8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB
011b: reserved
100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB
101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB
110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB
111b: 32-bit - RGB5:6:5 - 1cycle/2pixel - RRRRRGGGGGGBBBBB/RRRRRGGGGGGBBBBB

The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected.
Must set to RGB565 when RAM type destination selected Change Polarity of CS0 signal
0: no change
1: Inverted Change Polarity of CS1 signal
0: no change
1: Inverted Change Polarity of RS signal
0: no change
1: Inverted Change Polarity of WR signal
0: no change
1: Inverted Change Polarity of RD signal
0: no change
1: Inverted Number of command to be send to the LCD command (up to 31) Start command transfer only. Autoreset LCD reset signal. Low active All value are in cycle number of system clock Address setup time (RS to WR, RS to RD) Adress hold time Pulse Width Low level, between 2 and 63. Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). Address destination pointer when memory destination is selected.
The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
This 2D feature allows for in-memory image compositing. data to write or data readen (the readen data is ready when the lcd is not busy) Acesss type selection
0: Command
1: Data Start a single write access. Autoreset Start a single read access (only when LCD output selected). Autoreset. 0:4 line mode 1:3 line mode 2:command mode 3:3 line 2 lane mode tx Mirror enable. . . . . Count value to detect vsync pulse 0:vsync te only 1:vsync and hsync te Pol select Te enable. Te counter value Gouda internal Sram space I2C master enable, high active. I2C master interrupt enable, high active. This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared.

Example:
PCLK_MOD is 52 MHz, desired SCL is 100 KHz.
Prescale = 52MHz / (5 * 100KHz) -1 = 103. IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK. IRQ status bit. TIP, Transfer in progress. '1' when transferring data. '0' when transfer complete. AL,Arbitration lost. This bit is set when the I2C master lost arbitration. Busy,I2C bus busy. '1' after START signal detected. '0' after STOP signal detected. RxACK, Received acknowledge from slave. '1'= "No ACK" received. '0'= ACK received. Byte to transmit via I2C.
for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit.
'1' = reading from slave.
'0' = writing to slave. Last byte received via I2C. ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1'). RD,read from slave, this bit is auto cleared. STO,generate stop condition, this bit is auto cleared. WR,write to slave, this bit is auto cleared. STA,generate (repeated) start condition, this bit is auto cleared. When write '1', clears a pending I2C interrupt. This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
Secure cpu can use all channels, but non-secure cpu only can use non-secure channel.
Non-secure channel means std_ch_reg_sec is 1'b0, don't care about the value of std_ch_dma_sec.
When non-secure cpu read this register, the return value will automatic exlude the secure channel.
00000 = use Channel0
00001 = use Channel1
00010 = use Channel2
...
01111 = use Channel15
11111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
all 1 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode This register indicates which channel register can only be accessed by secure master. One bit per channel, for example:
0000_0000 = All channels registers can be accessed by secure master or non-secure master.
0000_0001 = Ch0 registers can only be accessed by secure master.
0000_0010 = Ch1 registers can only be accessed by secure master.
0000_0100 = Ch2 registers can only be accessed by secure master.
0000_0101 = Ch0 and Ch2 registers can only be accessed by secure master.
0000_0111 = Ch0, Ch1 and Ch2 registers can only be accessed by secure master.
......
all 1 = all channels registers can only be accessed by secure master. This register indicates which channel dma is secure master. One bit per channel, for example:
0000_0000 = All channels dma are non-secure master.
0000_0001 = Ch0 dma is secure master.
0000_0010 = Ch1 dma is secure master.
0000_0100 = Ch2 dma is secure master.
0000_0101 = Ch0 and Ch2 dma are secure master.
0000_0111 = Ch0, Ch1 and Ch2 dma are secure master.
......
all 1 = all channels dma are secure master. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB
Exchange the write data to fifo halfword MSB or LSB
Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Tx or Rx transfer Count, this field indicated the transfer size in bytes which already performed. Writing 1 starts block decode AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset. Decode error flag. Reading 1 indicates block decode error and Lzma should be reset. Decode done flag. Reading 1 indicates block decode done, writing 1 clears. Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1 Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1 Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1 not used Lzma dictionary size in byte lzma block size in byte lzma zip stream lenght in byte 1: refbyte enable; 0: refbyte disable 1: cabac_movebits=5; 0: cabac_movebits=4 1: cabac_totalbits=11; 0: cabac_totalbits=10 current decoding byte position in zip stream current recovering byte position in dictionary Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2) Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size Equals to 1 when a symbol is decoded as match type with length more than 273 Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion Equals to 1 when first symbol in a block is decoded as match type Equals to 1 when zip stream reading byte position exceeds the stream length not used not used Crc of lzma rdma read bytes Crc of lzma wdma write bytes not used not used Base address of lzma rdma Base address of lzma wdma Set the margin between input_buf wrptr and rdptr for pending the decode process bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. Enables the SIM Card IF module Selects the parity generation/detection Parity Error Receive Feed-through
0 = Don't store bytes with detected parity errors
1 = Feed-through bytes with detected parity errors Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer.
0 = Enable NULL character filtering, NULL characters are not reported if not data.
1 = Disable NULL character filtering. NULL characters (0x60) are transferred to the SCI data buffer. Manual SCI Clock Stop control. Manually starts and stops the SCI clock. This bit must be set to '1' when Autostop mode is enabled.
0 = Enable the SCI clock
1 = Disable SCI clock Enables automatic clock shutdown when command is complete. Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol.
0 = Auto clock control not enabled. SCI clock controlled by SCI_Clockstop bit
1 = Auto clock control enabled. Sets the transmission and reception bit order:
0 = LSB is sent/recieved first (Direct convention)
1 = MSB is sent/received first (Inverse convention) Logic Level Invert:
0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit. (Direct convention)
1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit. (Inverse convention) Parity Error signal length. This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU
0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU
1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU Enable or disable parity error checking on the receive data
0 = Disable parity error checking
1 = Enable parity error checking Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown)
0 = Stop clock at low level
1 = Stop clock at high level Automatic Reset Generator. Write a '1' to this bit to initiate an automatic reset procedure on the SIM. Write '0' to switch back to SCI_Reset control (bit 20). An ARG interrupt will be generated if the ARG process succeeded or failed. The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected. This bit needs to be cleared between ARG attempts. Automatic format detection. This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention.
1 = Enable TS detection and automatic convention settings programming
0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention 1 = Enable automatic resend of characters when Tx parity error is detected
0 = Disable automatic resend Direct connection to the SIM card reset pin. This is overridden when ARG_H is enabled
0 = SCI_Reset low voltage
1 = SCI Reset high voltage This selects between two delay times for the automatic clock stop startup and shutdown:
0 = short delay
Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks
1 = long delay
Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks Input data average enable.
0 = Disable
1 = Enable Allows fine control of the parity check position during the parity error time period. Returns the status of the Rx FIFO:
0 = Rx FIFO empty
1 = There is at least 1 character in the Rx FIFO Returns the status of the Tx FIFO:
0 = Tx FIFO is full
1 = There is at least 1 free spot in the Tx FIFO Returns the status of the automatic format detection after reset:
0 = TS character has not been detected in the ATR
1 = TS character has been detected and SCI module is using the automatic convention settings

This bit is cleared when the AFD_En bit is cleared Returns the status of the automatic reset procedure:
0 = ARG detection has failed
1 = ARG detection has detected that the SIM has responded to the reset

This bit is used in conjunction with the ARG interrupt. The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process. This bit can be used to determine the success or failure. This is the status of the Reset pin when automatic reset generation is enabled. This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection') Status of the control signal to the clock control module. This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready'
0 = SCI clock may be on or off but is not ready for use
1 = SCI clock is on and ready for use Status bit of the Sci clock.
0 = Sci clock is ON
1 = Sci clock is OFF A receive parity error was detected. Reading this register clears the bit. A transmit parity error was detected. Reading this register clears the bit. The internal receive FIFO has reached an overflow condition. Reading this register clears the bit. The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit. Returns the state of the clock management state machine when AutoStop mode is enabled. This value is '00' when manual mode is selected. Clock is on, but not ready to be used. Clock is on and ready to be used Clock is still on, but should not be used. Clock is off. Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. Reading this register will read from the receive data FIFO. Clock divider for generating the baud clock from the SCI clock. This value must match the value used by the SIM card whose default value is 0x174. Speed mode enable.
0 = Low speed mode
1 = High speed mode(372/32, 372/64, 512/64) Rx_clk_cnt wrap value. Secondary clock divider for generating 16x baud clock. Main clock divider to generate the SCI clock. This value should be calculated as follows:
MainDiv = Clk_Sys/(2xSCI_Clk) - 1
where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification. Inverts the polarity of the SCI clock to the SIM card only.
0 = No inversion
1 = Invert external SCI clock Inverts the polarity of the SCI clock to the SIM card and internal.
0 = No inversion
1 = Invert external SCI clock This value should be programmed with the number of expected characters to receive. It will be decremented each time a character is actually received and should be 0 when the transfer is complete. If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero. When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete. This should be used for multi-transfer commands where the clock must not be shut down until the command is complete. This bit must be programmed for each transfer.
1 = Keep clock on
0 = Allow clock shutdown when transfer is complete This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters. This should be programmed depending on the SIM's ATR. The total ETU guard time will be ChGuard + 1. Turnaround guard time configuration. This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character. The minimum time specified in the SIM recommendation is 16 ETU. The number of ETUs can be calculated using the following formula:
Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard Work Waiting Time factor. A timeout will be generated when the WWT is exceeded. The WWT is calculated by:
WWT = 960 x WI x (F/Fi)
where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS.
The SCI_WI value must be calculated as follows:
SCI_WI = WI * D
Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure. Number of times to try resending character when the SIM indicates a parity error. Value of the character to be filtered. 0x60 is the NULL character in the SIM protocol. If character filtering is enabled, the first 0x60 character that is received by the SIM during a transfer will not be recorded. The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data. This filter has no effect on characters within the datastream. Clear RX FIFO. Clear TX FIFO. clear RX/TX FIFO Number of expected Rx characters, as programmed in the RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is a READ ONLY register that returns the logical and of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt. Bits 21:16 return the status of the interrupt which is the interrupt state before the mask is applied. These bits should only be used for debugging. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt. Controls the big endian or little endian of the FIFO data.
Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
"000": the order is not changed.
Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D".
"001": reversed on byte.
Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A".
"010": reversed on half word.
Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B".
"010": reversed on bit.
Byte3="B0",Byte2="30,Byte1="D0",Byte0="50".
"100": reversed on bit.
Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
Active Low. Read in the receive FIFO Write to the transmit FIFO SD/MMC operation begin register, active high.
When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. SD/MMC operation suspend register, active high. '1'indicates having a response,'0'indicates no response. Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. '1' indicates data operation, which includes read and write. '1' means write operation,'0' means read operation. '1'means multiple block data operation. '1' means the SD/MMC operation is not over. '1' means SD/MMC is busy. '1' means the data line is busy. '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. Response CRC checks error register '1' means response CRC check error. '1' means the card has no response to command. CRC check for SD/MMC write operation
"101" transmission error
"010" transmission right
"111" flash programming error 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. SDMMC DATA 3 value. SD/MMC command register. SD/MMC command argument register, write data to the SD/MMC card. SD/MMC response index register. Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. 95 to 64 bit response argument of R2. 63 to 32 bit response argument of R2. 31 to 0 bit response argument of R2. SD/MMC data width:
0x1: 1 data line
0x2: 2 reserved
0x4: 4 data lines
0x8: 8 data lines SD/MMC size of one block:
0-1:reserved
2: 1 word
3: 2 words
4: 4 words
5: 8 words
6: 16 words

11: 512 words
12-15 reserved Block number that wants to transfer. '1' means no response. '1' means CRC error of response. '1' means CRC error of reading data. '1' means CRC error of writing data. '1' means data transmission is over. '1' means tx dma done. '1' means rx dma done. '1' means no response is the source of interrupt. '1' means CRC error of response is the source of interrupt. '1' means CRC error of reading data is the source of interrupt. '1' means CRC error of writing data is the source of interrupt. '1' means the end of data transmission is the source of interrupt. '1' means tx dma done is the source of interrupt. '1' means rx dma done is the source of interrupt. When no response, '1' means INT is disable. When CRC error of response, '1' means INT is disable. When CRC error of reading data, '1' means INT is disable. When CRC error of writing data, '1' means INT is disable. When data transmission is over, '1' means INT is disable. when tx dma done, '1' means INT is disabled. '1' means rx dma done, '1' means INT is disabled. Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). This register may delay the mclk output. When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. Invert Mclk. spi flash command to send. spi flash address to send. spi flash modebit,set 0xA0 to enable continuous read. spi flash spi read/write block size. spi flash data to send. spi send byte, 1: quad send 0: spi send. spi flash busy. tx fifo empty. tx fifo full. rx fifo empty. rx fifo data count. read busy. nand int . spiflash_int = nand_int and nand_int_mask . flash rx status. spi flash read mode from AHB. spi flash wprotect pin. spi flash hold pin. spi flash read sample delay cycles. spi flash clock divider. spi flash send command using quad lines. rx fifo_clr,self clear. tx fifo_clr,self clear. spi flash cs num. single chip spi flash size. spi flash is 128m flash. disable read from ahb. sel flash 1, addr[24]. addr[25]. diff 128m diff cmd en. spi_256m. spi_512m. spi_cs1_sel2. spi_1g . spi_2g. spi_4g. spi_cs1_sel3. spi_cs1_sel4. spi_cs1_sel5. quad read command. fast read command. fast read command. protect_byte, must be 0x55 when program this register. Value low 32bits loaded to OS timer. Value high 24bits loaded to OS timer. Write '1' to this bit will enable OS timer.
When read, the value is what we have written to this bit, it changes immediately after been written. Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.

'1' indicates OS timer enabled.
'0' indicates OS timer not enabled. Read this bit will get the information if OS timer interruption clear operation is finished or not.

'1' indicates OS timer interruption clear operation is on going.
'0' indicates no OS timer interruption clear operation is on going. Write '1' to this bit will set OS timer to repeat mode.
When read, get the information if OS timer is in repeat mode.

'1' indicates OS timer in repeat mode.
'0' indicates OS timer not in repeat mode. Write '1' to this bit will set OS timer to wrap mode.
When read, get the information if OS timer is in wrap mode.

'1' indicates OS timer in wrap mode.
'0' indicates OS timer not in wrap mode. Write '1' to this bit will load the initial value to OS timer. Current value low 32bits of OS timer. Current value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. Current locked value low 32bits of OS timer. Current locked value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. This bit enables interval IRQ mode.

'0': hw delay timer does not generate interval IRQ.
'1': hw delay timer generate an IRQ each interval. interval of generating an HwTimer IRQ.

"00": interval of 1/8 second.
"01": interval of 1/4 second.
"10": interval of 1/2 second.
"11": interval of 1 second. Current low 32bits value of the hardware delay timer. Current high 32bits value of the hardware delay timer. Current locked low 32bits value of the hardware delay timer. Current locked high 32bits value of the hardware delay timer. Set mask for OS timer IRQ. Set mask for hardwre delay timer wrap IRQ. Set mask for hardwre delay timer interval IRQ. Clear mask for OS timer IRQ. Clear mask for hardwre delay timer wrap IRQ. Clear mask for hardwre delay timer interval IRQ. Clear OS timer IRQ. Clear hardware delay timer wrap IRQ. Clear hardware delay timer interval IRQ. OS timer IRQ cause. hardware delay timer wrap IRQ cause. hardware delay timer interval IRQ cause. OS timer IRQ status. hardware delay timer wrap IRQ status. hardware delay timer interval IRQ status. Value loaded to OS timer. Write '1' to this bit will enable OS timer.
When read, the value is what we have written to this bit, it changes immediately after been written. Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.

'1' indicates OS timer enabled.
'0' indicates OS timer not enabled. Read this bit will get the information if OS timer interruption clear operation is finished or not.

'1' indicates OS timer interruption clear operation is on going.
'0' indicates no OS timer interruption clear operation is on going. Write '1' to this bit will set OS timer to repeat mode.
When read, get the information if OS timer is in repeat mode.

'1' indicates OS timer in repeat mode.
'0' indicates OS timer not in repeat mode. Write '1' to this bit will set OS timer to wrap mode.
When read, get the information if OS timer is in wrap mode.

'1' indicates OS timer in wrap mode.
'0' indicates OS timer not in wrap mode. Write '1' to this bit will load the initial value to OS timer. Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal. Write '1' to this bit will stop watchdog timer. Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer.
Use this bit to implement the watchog keep alive. Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock.

'1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted.
'0' indicates watchdog timer is not enabled. Load value of watchdog timer. Number of 32kHz Clock before Reset.
This bit enables interval IRQ mode.

'0': hw delay timer does not generate interval IRQ.
'1': hw delay timer generate an IRQ each interval. interval of generating an HwTimer IRQ.

"00": interval of 1/8 second.
"01": interval of 1/4 second.
"10": interval of 1/2 second.
"11": interval of 1 second. Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF. Set mask for OS timer IRQ. Set mask for hardwre delay timer wrap IRQ. Set mask for hardwre delay timer interval IRQ. Clear mask for OS timer IRQ. Clear mask for hardwre delay timer wrap IRQ. Clear mask for hardwre delay timer interval IRQ. Clear OS timer IRQ. Clear hardware delay timer wrap IRQ. Clear hardware delay timer interval IRQ. OS timer IRQ cause. hardware delay timer wrap IRQ cause. hardware delay timer interval IRQ cause. OS timer IRQ status. hardware delay timer wrap IRQ status. hardware delay timer interval IRQ status. Allows to turn off the UART:
0 = Disable
1 = Enable Number of data bits per character (least significant bit first), if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0).
0 = one stop bit is transmitted in the serial data.
1 = two stop bits are generated and transmitted in the serial data out. Parity is enabled when this bit is set. Controls the parity format when parity is enabled:
00 = an odd number of received 1 bits is checked, or transmitted (the parity bit is included).
01 = an even number of received 1 bits is checked or transmitted (the parity bit is included).
10 = a space is generated and received as parity bit.
11 = a mark is generated and received as parity bit. Controls whether enable or disable soft flow ctrl function.
0 = disable flow ctrl function
1 = enable flow ctrl function Controls whether enable or disable auto baud rate function.
0 = disable auto baud rate function
1 = enable auto baud rate function Number of data bits per character (least significant bit first), if {Data_Bits_56, Data_Bits} is 00, the number of data bits is 7; if {Data_Bits_56, Data_Bits} is 01, the number of data bits is 8; if {Data_Bits_56, Data_Bits} is 10, the number of data bits is 5; if {Data_Bits_56, Data_Bits} is 11, the number of data bits is 6; Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16.
0 = (BCLK = SCLK / 16)
1 = (BCLK = SCLK / 4)
2 = (BCLK = SCLK / 3) When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details). Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept. Length of a break, in number of bits. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. Those bits indicate the number of space available in the Tx Fifo. at_match flag
'0' = AT is detected successfully.
'1' = at is detected successfully. When auto_enable is 0,this bit is cleared to 0. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. This bit indicates that the UART is receiving a byte. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. character miscompare flag
'0' = AT or at compare failed.
'1' = AT or at compare successfully. When auto_enable is 0,this bit is cleared to 0. auto baud locked flag
'0' = baud rate is detected failed.
'1' = baud rate is detected successfully. When auto_enable is 0,this bit is cleared to 0. This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value. current value of the Uart_CTS line.
'1' = Tx not allowed.
'0' = Tx allowed. Auto mode ratio flag. Mask tx enable flag. Current value of the DTR line. This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early. The UART_RECEIVE_BUFFER register is a read-only register that contains the data byte received on the serial input port. This register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Clear to send signal change detected. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Pulse detected on Uart_Dma_Tx_Done_H signal. Pulse detected on Uart_Dma_Rx_Done_H signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Rising edge detected on the UART_DTR signal. Falling edge detected on the UART_DTR signal. Auto function fail. When rx transfer num equals to transfer threshold, there is a interrupt flag. When tx transfer num equals to transfer threshold, there is a interrupt flag. This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. This interrupt is generated when sw flow ctrl is enabled and rx char is xon. This interrupt is generated when start bit is detected. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Reset control: Write one in this register. This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register. This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register. This interrupt is generated when auto function fail. Reset control: Write 0 in auto_enable. This interrupt is generated when rx transfer num is not less than transfer threshold. Reset control: Write 1 in this register. This interrupt is generated when tx transfer num is not less than transfer threshold. Reset control: Write 1 in this register. This interrupt is generated when sw flow ctrl is enabled and rx char is xoff. Reset control: Write 1 in this register. This interrupt is generated when sw flow ctrl is enabled and rx char is xon. Reset control: Write 1 in this register. This interrupt is generated when start is detected. Reset control: Write 1 in this register. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Defines the empty threshold level at which the Data Available Interrupt will be generated.
The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Defines the empty threshold level at which the Data Needed Interrupt will be generated.
The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC).
The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. Ring indicator. When write '1', set RI bit. When read, get RI bit value. Data carrier detect. When write '1', set DCD bit. When read, get DCD bit value. Data set ready. When write '1', set RI bit. When read, get RI bit value. Sends a break signal by holding the Uart_Tx line low until this bit is cleared. When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Controls the Uart_RTS output.
0 = the Uart_RTS will be inactive high (Rx not allowed).
1 = the Uart_RTS will be active low (Rx allowed). Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared. Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared. Ring indicator. When write '1', clear RI bit. When read, get RI bit value. Data carrier detect. When write '1', clear DCD bit. When read, get DCD bit value. Data set ready. When write '1', clear RI bit. When read, get RI bit value. Sends a break signal by holding the Uart_Tx line low until this bit is cleared. When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Controls the Uart_RTS output.
0 = the Uart_RTS will be inactive high.
1 = the Uart_RTS will be active low. Auto mode ratio. XON character value. XOFF character value. Number of key in the keypad Number of key in the low data register Number of key in the high data register For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) : For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn): For keys in lines status
0 = Released
1 = Pressed Indicate Key ON pressing status :
0 = Release
1 = Pressed This bit enables key detection. If this bit is '0', the key detection function is disabled. Key ON is an exception, it can be still detected and generate key interrupt even if KP_En = '0', however in this case, the debouncing time configuration in key control register is ignored and the key ON state is considerred to be stable if it keeps same in consecutive 2 cycles of 16KHz clock.

0 = keypad disable
1 = keypad enable De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms. Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. each bit masks one input lines.
'1' = enabled
'0' = disabled
The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset.
Key_In 0: BOOT_MODE_NO_AUTO_PU.
Key_In 1: BOOT_MODE_FORCE_MONITOR.
Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE.
Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE.
Key_In 4: reserved each bit masks one output lines.
'1' = enabled
'0' = disabled This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by event1 (all keys release event).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time.
0 = keypad interval irq disable
1 = keypad interval irq enable keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. keypad event1(all keys release event) IRQ cause. keypad interval irq cause. keypad event0(key press or key release event, not including all keys release which is event1) irq status. keypad event1(all keys release event) irq status. keypad interval irq status. Write '1' to this bit clears key IRQ. Set the direction of the GPIO n. 'Write '1' sets the corresponding GPIO pin as output. 'Write '1' sets the corresponding GPIO pin as input. When write, update the output value. When read, get the input value. Write '1' will set GPIO output value. When read, get the GPIO output value. 'Write '1' clears corresponding GPIO output value. When read, get the GPIO output value. 'Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt. Each bit represents if there is a GPIO interrupt pending. time for which GPIO0 is set to output mode, after a start read DCON command is issued.
The output time = (OUT_TIME+1)*30.5us. time for which GPIO0 should wait before reading DC_ON, after a start read DCON command is issued.
The wait time = (WAIT_TIME+1)*30.5us.
NOTE: wait_time must be strictly greater than out_time; interruption mode of GPIO0 in mode DC_ON detection.
"00" = send IRQ if last read DCON is '0' and now is '1'. "01" = send IRQ if last read DCON is '1' and now is '0'. "11" = send IRQ every time read is ready. Write '1' to set GPIO0 to charger DCON detect mode. Write '1' to set GPO0 to charger watchdog mode. Write '1' to clear charger DCON detect mode of GPIO0. Write '1' to clear the charger watchdog mode of GPO0. Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles. 'Write '1' will set GPO output value. When read, get the GPO output value. 'Write '1' will clear GPO output value. When read, get the GPO output value. 'Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. 'Write '1' will enable debounce mechanism. 'Write '1' will disable debounce mechanism. Write '1' will set interruption mode to level. Write '1' will set interruption mode to edge triggered.