AHB Address bus size AXI Address bus size of DMA_AP System AON Apb Bus Configuration 8910m sys aon apb module id Last of AON Normal slave Num of System Aon Apb Slaves except Debug Host The debug host is placed at last PSEL127 in the IFC Debug host slave id used for ifc channel. System Apb Bus Configuration 8910m sys apb module id Last of Sys APB Normal slave Num of System Apb Slaves System Ahb Bus Configuration 8910m sys ahb module id Num of System Ahb Slaves Aif Apb Bus Configuration 8910m aif apb module id Num of Aif Apb Slaves Aif slave id used for ifc channel. Num of sys ifc dma req Num of aon ifc dma req System IRQ IDs Num of System IRQS IRQ IDs For CP CPU Num of IRQS For CP CPU Other IRQ IDs For CP CPU Num of Other IRQS For CP CPU Below is for compatibility to inherited design and for rtl compiling pass GGE System Apb Bus Configuration 8910m gge sys apb module id Num of GGE System Apb Slaves Num of gge ifc dma req GGE System Apb Bus Configuration 8910m gge bb apb module id Num of GGE Baseband Apb Slaves GGE IRQ IDs Number of GGE Pulse IRQ Num of Gge IRQS Number of GGE BB Level IRQ System RF Apb Bus Configuration 8910m rf apb module id Num of RF Apb Slaves WCN System Apb Bus Configuration 8910m wcn sys apb module id Num of WCN System Apb Slaves #if defined(REG_ADDRESS_FOR_GGE) #define KSEG0(addr) ( (addr) | 0x80000000 ) #define KSEG1(addr) ( (addr) | 0xA0000000 ) #else #define KSEG0(addr) (addr) #define KSEG1(addr) (addr) #endif #define REG_ACCESS_ADDRESS(addr) KSEG1(addr) /* Define access cached or uncached */ #define MEM_ACCESS_CACHED(addr) (assert(0, "NOT SUPPORTED")) #define MEM_ACCESS_UNCACHED(addr) (assert(0, "NOT SUPPORTED")) /* Register access for assembly */ #define BASE_HI(val) (((0xa0000000 | val) & 0xffff8000) + (val & 0x8000)) #define BASE_LO(val) (((val) & 0x7fff) - (val & 0x8000)) /* to extract bitfield from register value */ #define GET_BITFIELD(dword, bitfield) (((dword) & (bitfield ## _MASK)) >> (bitfield ## _SHIFT)) #define EXP2(n) (1<<(n)) #define REG32 volatile unsigned int #define REG16 volatile unsigned short #define REG8 volatile unsigned char #define UINT32 unsigned int #define UINT16 unsigned short #define UINT8 unsigned char #define REG_READ_UINT32( _reg_ ) (*(volatile unsigned int*)(_reg_)) #define REG_WRITE_UINT32( _reg_, _val_) ((*(volatile unsigned int*)(_reg_)) = (unsigned int)(_val_)) #define REG_READ_U64( _reg_ ) (*(volatile unsigned long*)(_reg_)) #define REG_WRITE_U64( _reg_, _val_) ((*(volatile unsigned long*)(_reg_)) = (unsigned long)(_val_)) 0= chip option; 1= FPGA option 0= no baseband; 1= baseband included 0= Nothing; 1= BIST; 2= TEST MASTER 0= no monitor; 1=monitor included 0= no debug host sel register as on test chip; 1=debug host sel register included 0= No VOC ; 1= VOC included 0= No aif channels (0,1) ; 1= All 3 channels 0= No MMI ; 1= MMI included : keypad, PWL/PWT, calendar GPIO/GPO OPTIONS: numbers 0= No DMA ; 1= DMA included 0 = no SPI, no GPADC, no UART1; 1 = SPI, GPADC, UART1 included 0 = no USB; 1 = USB included Ap Ifc Number of generic channel (range 2 to 7) Aon Ifc Number of generic channel (range 2 to 7) Gge Ifc Number of generic channel (range 2 to 7) audio Ifc Number of generic channel (range 0 to 4) 0 = no UART2; 1 = UART2 included number of SPI1 CS number of SPI1 DI size of SPI1 DATA 0 = no SPI2; 1 = SPI2 included number of SPI2 CS number of SPI DI size of SPI2 DATA 0 = no SPI3; 1 = SPI3 included number of SPI3 CS number of SPI DI size of SPI3 DATA 0 = no SDMMC; 1 = SDMMC controller included 0 = no Camera; 1 = Camera controller included 0 = no Gouda; 1 = Gouda included 0 = EBC, 1 = AHBM for membridge internal ram: number of 32k blocks for EBC option only for AHBM option only: address bus size Address of data to be read or written. These two bits indicates element data size.
when "00" = "byte".
when "01" = "half word".
when "10" = "word". This bit indicates command is read or write.
when "0" = "Read".
when "1" = "Write". Those bits are data to be read or written by IFC. When read, this bit is used for event semaphore.
'0' = no new event should be programed.
'1' = no pending event, new event is authorised.
If host is not enabled, this bit is always '1'. However in this case, any event written will be ignored.
When Write, this bit is the least significant bit for a 32-bit event. These bits combined with bit0 consists a 32-bit event number. If a new event is written before the previous event has been sent, it will be ignored. When '1', force the debug host on, use clock UART if clock host is not detected. This bit indicates if clock host is detected to be on or not.
'0' = no clock host.
'1' = clock host detected. Status which can be written through debug uart interface into a debug host internal register and read by APB. write in this bit will reset h2p status register. Status which can be written by APB and read through debug uart interface as a debug host internal register. when write '1', clear the xcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the xcpu irq status. when write '1', clear the bcpu irq level which is programmed in a debug host internal register, this bit is automatic cleared.
when read, get the bcpu irq status. General control signals set. Debug host generated reset. Signal to system control. Active high.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. Force wakeup. Active high.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). When write '1, generate a level IRQ to XCPU. Write '0 is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). When write '1', generate a level IRQ to BCPU. Write '0' is ignored. This IRQ can be cleared by written APB register. When Read, Get the IRQ status.
Write '1' to this bit will set it to '1'.
Reseted by signal sys_rst_others (host). Lock Debug port set.
Write '1' to this bit will set it to '1'.
Reseted by signal rst_host_reg. General control signals clear. Force XCPU Reset signal. Active high. Hold XCPU in reset state until this bit is cleared.
Write '1' to this bit will clear it to '0'.
Reseted by signal rst_host_reg. Force wakeup. Active high.
Write '1' to this bit will clear it to '0'.
Reseted by signal rst_host_reg. Force XCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by XCPU.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Force BCPU breakpoint. Active high. Hold its value until this bit is cleared. When Read, Get the status of Force breakpoint sent back by BCPU.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Lock Debug port clear.
Write '1' to this bit will clear it to '0'.
Reseted by signal sys_rst_others (host). Configure Debug UART Clock divider. Debug host clock divider. The serial clock is generated by dividing 14,7456MHz Host Clock by (CFG_CLK+2). So By default, the serial clock is 14,7456MHz / (2+2) = 3,6864 MHz which corresponds to the 921,6K Baud-rate.
Reseted by signal rst_host_reg. Configure Debug UART. When '1', Disable Normal Uart functional group.
This bit is set to '1' when break.
Reseted by signal rst_host_reg. When '1', Ignore IFC write and read access so only debug host internal is accessible.
This bit is set to '1' when break.
Reseted by signal rst_host_reg. The usage of this bit is deternimed by the specific chip.
Can be used as Debug_Port_Lock register to protect some register change by the regular software while debug hosr is used to set thoses registers to specific values.
Reseted by signal rst_host_reg. When '1', force the Debug Uart to have priority on TX.
Reseted by signal rst_host_reg. Status of CRC. This bit represents that an CRC error has occured in commands received by Debug Host. Once set to '1', it will keep the value until this register is clearred by write '1'.
'0' = no CRC error.
'1' = CRC error.
Reseted by signal sys_rst_others (host). This bit represents if the 16-byte Flow Control FIFO has an overflow error. This status will be kept until a RX break is received.
'0' = no Flow Control Overflow Error.
'1' = Flow Control Overflow Error.
Reseted by signal sys_rst_others (host). Host write, APB readable register. These bits can be read by APB and write by host. Corresponds to APB register STATUS. They can also be reseted to zeros by APB command. (see details in debug host APB register mapping)
Reseted by signal sys_rst_others (host). APB write, Host readable register. These bits can be written by APB and read by host. Corresponds to APB register STATUS.
Write to Bit 0 can reset the P2H status.
Reseted by signal sys_rst_others (host). Debug information of system side AHB bus status. The bit represent Sys Ifc HMBURSREQ. The bit represent Dma HMBURSREQ. The bit represent Sys Ahb2ahb HMBURSREQ. The bit represent Xcpu HMBURSREQ. The bit represent USBC HMBURSREQ. The bit represent GOUDA HMBURSREQ. The bit represent Sys Ifc HMGRANT. The bit represent Dma HMGRANT. The bit represent Sys Ahb2ahb HMGRANT. The bit represent Xcpu HMGRANT. The bit represent USBC HMGRANT. The bit represent GOUDA HMGRANT. Debug information of AHB bus status HSEL. The bit represent Sys MEM_EXT HSEL. The bit represent Sys MEM_INT HSEL. The bit represent Sys Ifc HSEL. The bit represent Sys Ahb2ahb HSEL. The bit represent USBC HSEL. The bit represent GOUDA HSEL. The bit represent XCPU RAM HSEL. The bit represent Sys Ifc HSREADY. The bit represent Sys EBC HSREADY. The bit represent Sys Ahb2ahb HSREADY. The bit represent USBC HSREADY. The bit represent GOUDA HSREADY. The bit represent XCPU RAM HSREADY. The bit represent Sys HSREADY which is sent to all sys AHB slaves. Debug information of baseband side AHB bus status. The bit represent BB Ifc HMBURSREQ. The bit represent Voc HMBURSREQ. The bit represent BB Ahb2ahb HMBURSREQ. The bit represent Bcpu HMBURSREQ. The bit represent BB Ifc HMGRANT. The bit represent Voc HMGRANT. The bit represent BB Ahb2ahb HMGRANT. The bit represent Bcpu HMGRANT. Debug information of AHB bus status HSEL. The bit represent BB MEM HSREADY. The bit represent BB VoC HSREADY. The bit represent BB Sram HSREADY. The bit represent BB Ifc HSREADY. The bit represent BB Ahb2ahb HSREADY. The bit represent BB HREADY which is sent to all BB AHB slaves. Debug information of AHB bus status HSEL. The bit represent BB MEM_EXT HSEL. The bit represent BB MEM_INT HSEL. The bit represent BB VOC HSEL. The bit represent BB Sram HSEL. The bit represent BB Ifc HSEL. The bit represent BB Ahb2ahb HSEL. Represents the split status register of the SYS_AHBC. Represents the split status register of the BB_AHBC. Allows to turn off the UART:
0 = Disable
1 = Enable Number of data bits per character (least significant bit first):
0 = 7 bits
1 = 8 bits
This bit will be masked to '1' if debug host is enabled. Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0).
0 = one stop bit is transmitted in the serial data.
1 = two stop bits are generated and transmitted in the serial data out.
This bit will be masked to '0' if debug host is enabled. Parity is enabled when this bit is set.
This bit will be masked to '0' if debug host is enabled. Controls the parity format when parity is enabled:
00 = an odd number of received 1 bits is checked, or transmitted (the parity bit is included).
01 = an even number of received 1 bits is checked or transmitted (the parity bit is included).
10 = a space is generated and received as parity bit.
11 = a mark is generated and received as parity bit.
These bit will be ignored if debug host is enabled. Sends a break signal by holding the Uart_Tx line low until this bit is cleared.
This bit will be masked to '0' if debug host is enabled. Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. When this field is "00" and SWTX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used:
00 = no transmit flow control.
01 = transmit XON1/XOFF1 as flow control bytes
10 = transmit XON2/XOFF2 as flow control bytes
11 = transmit XON1 and XON2/XOFF1 and XOFF2 as flow control bytes
When this field is "00" and SWRX_flow_Ctrl is also "00", hardwre flow ctrl is used. Otherwise, software flow control is used:
00 = no receive flow control
01 = receive XON1/XOFF1 as flow control bytes
10 = receive XON2/XOFF2 as flow control bytes
11 = receive XON1 and XON2/XOFF1 and XOFF2 as flow control bytes

Note: If single XON/XOFF character is used for flow contol, the received XON/XOFF character will not be put into Rx FIFO. This is also the case if XON is received when XOFF is expected.
If double XON/XOFF characters are expected, the XON1/XOFF1 must followed sequently by XON2/XOFF2 to be considered as patterns, which will not be put into Rx FIFO. Otherwise they will be considered as data. This is also the case if XOFF1 is followed by character other than XOFF2.
When soft flow control characters or backslash are encountered in the data file, they will be inverted and a backslash will be added before them. for example, if tx data is XON(0x11) with BackSlash_En = '1', then uart will send 5Ch(Backslash) + EEh (~XON). When this bit is set the Tx engine terminates to send the current byte and then it stops to send data. Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16.
0 = (BCLK = SCLK / 4)
1 = (BCLK = SCLK / 16)
This bit will be masked to '0' if debug host is enabled. When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details).
This bit will be masked to '0' if debug host is enabled. Controls the Uart_RTS output (not directly in auto flow control mode).
0 = the Uart_RTS will be inactive high
1 = the Uart_RTS will be active low
This bit will be masked to '1' if debug host is enabled. Enables the auto flow control.
In case HW flow control (both swTx_Flow_ctrl=0 and swRx_Flow_Ctrl=0), If Auto_Flow_Control is enabled, Uart_RTS is controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register). Tx data flow is stopped If Uart_CTS become inactive high.
If Auto_Flow_Control is disabled, Uart_RTS is controlled only by the Rx RTS bit in CMD_Set register. Uart_CTS will not take effect.

In case SW flow control(either swTx_Flow_ctrl/=0 or swRx_Flow_Ctrl/=0), If Auto_Flow_Control is enabled, XON/XOFF will be controlled by the Rx RTS bit in CMD_Set register and the UART Auto Control Flow System(flow controlled by Rx Fifo Level and AFC_Level in Triggers register).
If Auto_Flow_Control is disabled, XON/XOFF will be controlled only by Rx RTS bit in CMD_Set register. Tx data flow will be stoped when XOFF is received either this bit is enable or disabled.

This bit will be masked to '1' if debug host is enabled. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept.
This bit will be masked to '0' if debug host is enabled. HST TXD output enable. '0' enable. Length of a break, in number of bits.
This bit will be masked to "1011" if debug host is enabled. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. This bit indicates that the UART is receiving a byte. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), This bit is set when the Uart_CTS line changed since the last time this register has been written.
In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), This bit is set when received XON/XOFF status changed since the last time this register has been writtern.
This bit is cleared when the UART_STATUS register is written with any value. In case HW flow ctrl(both swRx_Flow_Ctrl=0 and swTx_Flow_Ctrl=0), current value of the Uart_CTS line.
'1' = Tx not allowed.
'0' = Tx allowed.
In case SW flow ctrl(either swRx_Flow_Ctrl/=0 or swTx_Flow_Ctrl/=0), current state of software flow control.
'1' = when XOFF received.
'0' = when XON received. This bit is set when Tx Fifo Reset command is received by CTRL register and is cleared when Tx fifo reset process has finished. This bit is set when Rx Fifo Reset command is received by CTRL register and is cleared when Rx fifo reset process has finished. This bit is set when bit enable is changed from '0' to '1' or from '1' to '0', it is cleared when the enable process has finished. This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling Rx RTS too early. The UART_RECEIVE_BUFFER register is a read-only register that contains the data byte received on the serial input port. This register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Clear to send signal change or XON/XOFF detected. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Pulse detected on Uart_Dma_Tx_Done_H signal. Pulse detected on Uart_Dma_Rx_Done_H signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Defines the threshold level at which the Data Available Interrupt will be generated.
The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Defines the threshold level at which the Data Needed Interrupt will be generated.
The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC).
The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. XON1 character value. Reset Value is CTRL-Q 0x11. XOFF1 character value. Reset Value is CTRL-S 0x13 XON2 character value. XOFF2 character value. These characters must respect following constraints: They must be different if used in software control, if BackSlash_En='1', they cannot be '\' and they cannot be complementary to each other, for example neither XON1 = ~XOFF1 nor XON1 = ~'\' is permitted. general used register security visit enable 0:security 1:unsecurity response error stop function enable 0:enable 1:disable the number of outstanding that can be send out 0: 2 1: 3 2: 4 multe-channel transport priority mode control 0: there is no priority in the channels, using polling to DMA data 1: smaller channel number has high-priority.high-priority move data before low-priority channels interrupt control bit 0: no interruption occurs when all logical channels finish 1: interruption occurs when all logical channels finish the control bit of logical channel transport finish 0: don't stop all the channel,or automatically clear after setting 1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. stop status 0: not finish 1: finish the channel number of the final transmission 0000: channel 0 just finished the transmission 0001: channel 1 just finished the transmission 0010: channel 2 just finished the transmission ...... 1011: channel 11 just finished the transmission others: nonentity logic channel stop interrupt status channel 11 interrupts state 0: the channel 11 has not been interrupted, or the interrupt bit has been cleared 1: channel 11 is interrupted channel 10 interrupts state 0: the channel 10 has not been interrupted, or the interrupt bit has been cleared 1: channel 10 is interrupted channel 9 interrupts state 0: the channel 9 has not been interrupted, or the interrupt bit has been cleared 1: channel 9 is interrupted channel 8 interrupts state 0: the channel 8 has not been interrupted, or the interrupt bit has been cleared 1: channel 8 is interrupted channel 7 interrupts state 0: the channel 7 has not been interrupted, or the interrupt bit has been cleared 1: channel 7 is interrupted channel 6 interrupts state 0: the channel 6 has not been interrupted, or the interrupt bit has been cleared 1: channel 6 is interrupted channel 5 interrupts state 0: the channel 5 has not been interrupted, or the interrupt bit has been cleared 1: channel 5 is interrupted channel 4 interrupts state 0: the channel 4 has not been interrupted, or the interrupt bit has been cleared 1: channel 4 is interrupted channel 3 interrupts state 0: the channel 3 has not been interrupted, or the interrupt bit has been cleared 1: channel 3 is interrupted channel 2 interrupts state 0: the channel 2 has not been interrupted, or the interrupt bit has been cleared 1: channel 2 is interrupted channel 1 interrupts state 0: the channel 1 has not been interrupted, or the interrupt bit has been cleared 1: channel 1 is interrupted channel 0 interrupts state 0: the channel 0 has not been interrupted, or the interrupt bit has been cleared 1: channel 0 is interrupted state of IRQ 23 generate requests of moving data 0: IRQ 23 does not generate requests of moving data 1: IRQ 23 generate requests of moving data state of IRQ 22 generate requests of moving data 0: IRQ 22 does not generate requests of moving data 1: IRQ 22 generate requests of moving data state of IRQ 21 generate requests of moving data 0: IRQ 21 does not generate requests of moving data 1: IRQ 21 generate requests of moving data state of IRQ 20 generate requests of moving data 0: IRQ 20 does not generate requests of moving data 1: IRQ 20 generate requests of moving data state of IRQ 19 generate requests of moving data 0: IRQ 19 does not generate requests of moving data 1: IRQ 19 generate requests of moving data state of IRQ 18 generate requests of moving data 0: IRQ 18 does not generate requests of moving data 1: IRQ 18 generate requests of moving data state of IRQ 17 generate requests of moving data 0: IRQ 17 does not generate requests of moving data 1: IRQ 17 generate requests of moving data state of IRQ 16 generate requests of moving data 0: IRQ 16 does not generate requests of moving data 1: IRQ 16 generate requests of moving data state of IRQ 15 generate requests of moving data 0: IRQ 15 does not generate requests of moving data 1: IRQ 15 generate requests of moving data state of IRQ 14 generate requests of moving data 0: IRQ 14 does not generate requests of moving data 1: IRQ 14 generate requests of moving data state of IRQ 13 generate requests of moving data 0: IRQ 13 does not generate requests of moving data 1: IRQ 13 generate requests of moving data state of IRQ 12 generate requests of moving data 0: IRQ 12 does not generate requests of moving data 1: IRQ 12 generate requests of moving data state of IRQ 11 generate requests of moving data 0: IRQ 11 does not generate requests of moving data 1: IRQ 11 generate requests of moving data state of IRQ 10 generate requests of moving data 0: IRQ 10 does not generate requests of moving data 1: IRQ 10 generate requests of moving data state of IRQ 9 generate requests of moving data 0: IRQ 9 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 8 generate requests of moving data 0: IRQ 8 does not generate requests of moving data 1: IRQ 8 generate requests of moving data state of IRQ 7 generate requests of moving data 0: IRQ 7 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 6 generate requests of moving data 0: IRQ 6 does not generate requests of moving data 1: IRQ 6 generate requests of moving data state of IRQ 5 generate requests of moving data 0: IRQ 5 does not generate requests of moving data 1: IRQ 5 generate requests of moving data state of IRQ 4 generate requests of moving data 0: IRQ 4 does not generate requests of moving data 1: IRQ 4 generate requests of moving data state of IRQ 3 generate requests of moving data 0: IRQ 3 does not generate requests of moving data 1: IRQ 3 generate requests of moving data state of IRQ 2 generate requests of moving data 0: IRQ 2 does not generate requests of moving data 1: IRQ 2 generate requests of moving data state of IRQ 1 generate requests of moving data 0: IRQ 1 does not generate requests of moving data 1: IRQ 1 generate requests of moving data state of IRQ 0 generate requests of moving data 0: IRQ 0 does not generate requests of moving data 1: IRQ 0 generate requests of moving data state of ACK 23 generate requests of moving data 0: ACK 23 does not generate requests of moving data 1: ACK 23 generate requests of moving data state of ACK 22 generate requests of moving data 0: ACK 22 does not generate requests of moving data 1: ACK 22 generate requests of moving data state of ACK 21 generate requests of moving data 0: ACK 21 does not generate requests of moving data 1: ACK 21 generate requests of moving data state of ACK 20 generate requests of moving data 0: ACK 20 does not generate requests of moving data 1: ACK 20 generate requests of moving data state of ACK 19 generate requests of moving data 0: ACK 19 does not generate requests of moving data 1: ACK 19 generate requests of moving data state of ACK 18 generate requests of moving data 0: ACK 18 does not generate requests of moving data 1: ACK 18 generate requests of moving data state of ACK 17 generate requests of moving data 0: ACK 17 does not generate requests of moving data 1: ACK 17 generate requests of moving data state of ACK 16 generate requests of moving data 0: ACK 16 does not generate requests of moving data 1: ACK 16 generate requests of moving data state of ACK 15 generate requests of moving data 0: ACK 15 does not generate requests of moving data 1: ACK 15 generate requests of moving data state of ACK 14 generate requests of moving data 0: ACK 14 does not generate requests of moving data 1: ACK 14 generate requests of moving data state of ACK 13 generate requests of moving data 0: ACK 13 does not generate requests of moving data 1: ACK 13 generate requests of moving data state of ACK 12 generate requests of moving data 0: ACK 12 does not generate requests of moving data 1: ACK 12 generate requests of moving data state of ACK 11 generate requests of moving data 0: ACK 11 does not generate requests of moving data 1: ACK 11 generate requests of moving data state of ACK 10 generate requests of moving data 0: ACK 10 does not generate requests of moving data 1: ACK 10 generate requests of moving data state of ACK 9 generate requests of moving data 0: ACK 9 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 8 generate requests of moving data 0: ACK 8 does not generate requests of moving data 1: ACK 8 generate requests of moving data state of ACK 7 generate requests of moving data 0: ACK 7 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 6 generate requests of moving data 0: ACK 6 does not generate requests of moving data 1: ACK 6 generate requests of moving data state of ACK 5 generate requests of moving data 0: ACK 5 does not generate requests of moving data 1: ACK 5 generate requests of moving data state of ACK 4 generate requests of moving data 0: ACK 4 does not generate requests of moving data 1: ACK 4 generate requests of moving data state of ACK 3 generate requests of moving data 0: ACK 3 does not generate requests of moving data 1: ACK 3 generate requests of moving data state of ACK 2 generate requests of moving data 0: ACK 2 does not generate requests of moving data 1: ACK 2 generate requests of moving data state of ACK 1 generate requests of moving data 0: ACK 1 does not generate requests of moving data 1: ACK 1 generate requests of moving data state of ACK 0 generate requests of moving data 0: ACK 0 does not generate requests of moving data 1: ACK 0 generate requests of moving data channel 11 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 10 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 9 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 8 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 7 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 6 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 5 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 4 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 3 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 2 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 1 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 0 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0:disable 1:enable security visit 0:security 1:unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 ...... 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission ...... 01111: IRQ15 trigger transmission ...... 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0:unset 1:set bit type is changed from w1c to rc. response error status 0:unset 1:set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 ...... 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit ...... 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel 1 - fix src address 0 - increament src address 1 - fix dst address 0 - increament dst address 0 - 1 byte 1 - 2 byte 2 - 4 byte write cycles 0 - normal dma mode 1 - dma aes encode mode 5 - dma aes decode mode 2 - dma crc mode source dma address destination dma address number of hsizem crc generator, MSB aligned --no-use 0 - crc8 1 - crc16 3 - crc32 bit0 - input byte reverse bit1 - input bit reverse bit2 - output byte reverse bit3 - output bit reverse aes engine clk on aes key generator clk on crc engine clk on trng engine clk on aes key bit 31:0 aes key bit 63:32 aes key bit 95:64 aes key bit 127:96 aes iv bit 31:0 aes iv bit 63:32 aes iv bit 95:64 aes iv bit 127:96 1 - CBC mode 0 - ECB mode 1 - start aes key calc 0 - after start calc, need written to 0 1 - aes key calc started by every 32bit key change 0 - aes key calc started by mode[1] :default Not used. The mac rd/wr fifo mem used by cios 0: 3'b000 - 1k 28bit mode 4: 3'b100 - 2k 28bit mode 1: 3'b001 - 1k 31bit mode 5: 3'b101 - 2k 31bit mode 2: 3'b010 - 1k 32bit mode 6: 3'b110 - 2k 32bit mode 1 - cios ram can be accessed only by ahb bus 0 - when cios ram input data completely writed by bus, then accessed by cios engine when engine accessed completely, then accessed by bus cios clk on 0 - cios start by cios_ctrl[7] 1 - cios auto start when mod_N load done. 1 - write 1'b1 to start cios compute. 0 - after start compute, need written to 0 cios reg crc initial value, MSB aligned crc output value xored value, LSB aligned crc output value, LSB aligned crc size: 3'd0 - 8bit crc 3'd1 - 16bit crc 3'd2 - 32bit crc low threshold to trigger ififo read from ahb high threshold to switch ififo read to ofifo write low threshold to switch ofifo write to ififo read high threshold to trigger ofifo write to ahb interrupt output, write 1 for clear bit0 - ahb dma done bit1 - prng alert bit2 - trng on fly test failed bit3 - trng start test failed bit4 - trng data ready bit5 - cios done interrupt mask, 1 for disable interrapt bit0 - ahb dma done bit1 - prng alert bit2 - trng on fly test failed bit3 - trng start test failed bit4 - trng data ready bit5 - cios done bit0 - trng enable bit1 - trng mode, 1 for continualy mode, 0 for once bit2 - trng start test enable bit3 - trng on fly test enable bit4 - trng source open bit5 - trng test enable bit6 - trng data mask enable trng source mask bit0 - prng enable bit1 - prng seed load bit2 - prng seed mode bit3 - prng timer enable prng seed prng timer initial value * 2 0 - use 40m/32=1.25MHz clk to sample input data 1 - use dma clk to sample input data prng timer value trng data0 trng data0 mask trng data1 trng data1 mask prng data trng c value trng h value When written to a one, the calculation starts. The complete and complete error bits are cleared when this bit is written with a one. Set to a one when the operation has completed. When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the end byte of the message. When set, the block of data described by MESSAGE_ADDR and MESSAGE_LENGTH includes the starting byte of the message 0x0 - SHA256 processing 0x1 - SHA1 processing 0x2 ~ 0xF - SHA1 processing If set, and interrupt will be generated upon completion of message processing. Swaps intra-word byte order of message words. If set byte addressing is Big Endian. Swaps intra-word byte order of hash values. If set byte addressing is Big Endian. Reserved. The Command register was written with start=1 when the Message Length register held an illegal value. No calculation was executed. Reserved. Starting Byte address of the message block in memory. Byte Length of Message. Maximum of 256K - Message Address[1:0]. HW state. Used for debug only. Umac Interface rd_counter. HW state. Used for debug only. Umac Interface wr_counter. HW state. Used for debug only. Umac Interface umac_state_c. HW state. Used for debug only. Umac Interface sha_state_c. Write 1 to the bit to clear the Interrupt Write 1 to the bit to enable SHA Interrupt SAM Interrupt status Write 1 to restart SHA module SHA Hash Values. The resulting message digest is the concatenation of H0. SHA Hash Values. The resulting message digest is the concatenation of H1. SHA Hash Values. The resulting message digest is the concatenation of H2. SHA Hash Values. The resulting message digest is the concatenation of H3. SHA Hash Values. The resulting message digest is the concatenation of H4. SHA Hash Values. The resulting message digest is the concatenation of H5. SHA Hash Values. The resulting message digest is the concatenation of H6. SHA Hash Values. The resulting message digest is the concatenation of H7. Number of Message bytes processed. Maximum of 0x1FFF_FFFF. Read for status or to save context. Written to restore context. CIOS RAM Space
Used for CIOS Only. Writing 1 starts block decode AXI bus error flag. Reading 1 indicates AXI bus operation fails and Lzma should be reset. Decode error flag. Reading 1 indicates block decode error and Lzma should be reset. Decode done flag. Reading 1 indicates block decode done, writing 1 clears. Writing 1 indicates a interrupt will be generated when lzma_status_reg[2]=1 Writing 1 indicates a interrupt will be generated when lzma_status_reg[1]=1 Writing 1 indicates a interrupt will be generated when lzma_status_reg[0]=1 Lzma dictionary size in byte lzma block size in byte lzma zip stream lenght in byte 1: refbyte enable; 0: refbyte disable 1: cabac_movebits=5; 0: cabac_movebits=4 1: cabac_totalbits=11; 0: cabac_totalbits=10 current decoding byte position in zip stream current recovering byte position in dictionary Equals to 1 when block decode finishes with zip stream reading byte position less than (reg_stream_len-2) Equals to 1 when block decode finishes with block buffer writing byte position exceeds the block size Equals to 1 when a symbol is decoded as match type with length more than 273 Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary size Equals to 1 when a symbol is decoded as match type with reps0 more than dictionary recovery byte postion Equals to 1 when first symbol in a block is decoded as match type Equals to 1 when zip stream reading byte position exceeds the stream length Crc of lzma rdma read bytes Crc of lzma wdma write bytes Base address of lzma rdma Base address of lzma wdma Set the margin between input_buf wrptr and rdptr for pending the decode process F8 00 01AES 10snow3G 11zuc F8 0F8 /group 1F8 /group F8 0F8 1F8 group group bit type is changed from w1c to rc. 0F9 1F9 bit type is changed from w1c to rc. 0F8/ 1F8/ F9 00AES 01AES 10snow3G 11zuc F9 0F9 /group 1F9 /group F9 0F9 1F9 F9 group F9 FSOE SBWE EDIS SPEN DISS DISR MOD_NUMBER = F003H REV_NUMBER = 20H Data Register (Bus address of buffer-32 GPRS_DATA registers are building the on-chip FIFO-buffer) Overflow Status Set to 1 by the GPRS unit when an overflow of the buffer occurs. Can be reset by writing '0' to bit UFL. Underflow Status Set to 1 by the GPRS unit when an underflow of the buffer occurs. Can be reset by writing '0' to bit UFL. Overflow By writing '0' to this bit, bit OFL_STAT will be reset. The current overflow status can be read via bit OFL_STAT. Write Describes the number of on-chip buffer blocks which are free to be written by the microcontroller. Note: If the XOR-combination is disabled by setting bit XOR_DIS in CTRL and ciphering is switched on by setting bit CIPH_CTRL in CTRL this bitfield is set to 0x00. Underflow By writing '0' to this bit, bit UFL_STAT will be reset. The current underflow status can be read via bit UFL_STAT. Read Describes the number of on-chip buffer blocks which have already been processed by the GPRS unit. These blocks can be read by the microcontroller. MAC-I Bits [31:0] CIPH_CTRL Value for the Actual Block in Byte Count Mode 0 Ciphering switched off 1 Ciphering switched on This bit is only valid for BC_EN = "1" (Byte count enabled)! CRC_CTRL Value for Actual Block in Byte Count Mode 0 CRC calculation switched off, necessery for unprotected data stream 1 CRC calculation switched on This bit is only valid for BC_EN = "1" (Byte count enabled)! Byte Counter Value Number of Bytes for the actual block. Only valid if BC_EN = "1"! Polynomial Bits [31:0] FCS Bits [31:0] FRESH Bits [31:0] KC0 Bits [31:0] GEA1/2: Cipher key. GEA3/f8: Input CK to the core function KGCORE (see Section 4.3.9). f9: Integrity key IK. KC1 Bits [31:0] GEA1/2: Cipher key. GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). f9: Integrity key IK. KC2 Bits [31:0] GEA1/2: Cipher key. GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). f9: Integrity key IK. KC3 Bits [31:0] GEA1/2: Cipher key. GEA3/UMTS: Input CK to the core function KGCORE (see Section 4.3.9). f9: Integrity key IK. Input Key Bits [31:0] GEA1/2: Input key for initialization. GEA3/f8: Input CC[31:0] to the core function KGCORE (see Section 4.3.9). f9: Frame dependent input Count-I[31:0]. CB Input CB[4:0] to the core function KGCORE (see Section 4.3.9). CD Input CD[0] to the core function KGCORE (see Section 4.3.9). Note: For f8 and f9 calculation, this bit refers to the input DIRECTION. Input CA[7:0] To the core function KGCORE (see Section 4.3.9). Input CE[15:0] To the core function KGCORE (see Section 4.3.9). Length Bits [31:0] Total number of bits of the input/output bit stream. F9CAL Status This bit is set by writing to bit F9CAL and reset by the GPRS block when the f9 calculation has finished. After this bit is reset by the GPRS block, the MAC can be read by the CPU. 0 F9 calculation finished. 1 F9 calculation ongoing. Offset Indicates the size of the header part to be discarded for UMTS f8 Initilisation Status This bit is only valid for MIN_INT="1"! This bit is set by writing to bit INT_EN and reset by the GPRS block. 0 GPRS_INT0 generation not enabled. 1 GPRS_INT0 generation enabled. XOR Disable By setting this bit, the XOR combination of input data and keystream will be omitted. This bit is valid only for f8 ciphering. 0 XOR combination enabled. If CIPH_CTRL = '0' the GPRS unit can be used DMA copy with bit-shifting. Data register DATA is used for writing the input bit stream. 1 XOR combination disabled. If CIPH_CTRL = '1' no input bit stream has to be written to the data register DATA. The produced keystream can be read from register DATA. Note: This bit in combination with CIPH_CTRL has effect on the DMA BUFIN request generation (see Table 18 and Table 19) GEA3 UMTS Mode 0 GEA3 or UMTS mode not enabled (default). GEA1 or GEA2 mode will be used according to the settings in bit MODE. 1 GEA3 or UMTS mode enabled. GEA3/UMTS f8 or UMTS f9 will be used according to the settings in bit MODE. Note: For GEA3 or UTMS f8 mode additionally bit MODE has to be set to '0' . For UMTS f9 mode bit MODE has to be set to '1' (see Table 21). Initilisation Status This bit is set by writing to bit INIT and reset by the GPRS block. After this bit is reset by the GPRS block, processing of GPRS_DATA is automatically started. During initialisation GPRS_DATA processing is blocked. 0 Initialisation finished. 1 Initialisation ongoing. F9 Calculation Bit The f9 calculation bit can be set to "1" by the MCU before data for a new f9 calculation is written to the GPRS unit. The status of the f9 calculation can be read via bit F9CAL_STAT. 0 No effect. 1 Start the indicator for f9 operation. FIFO Flush 0 No operation (default) 1 Data FIFO DATA is flushed. (This bit need not be reset by software.) Burse Size 000 Burst Size 1 (default) 001 Burst Size 4 010 Burst Size 8 011 Burst Size 16 100 Burst Size 32 Byte Count Enable 0 Byte count feature disabled (default) 1 Byte count feature enabled Buffer In Enable 0 GPRS_BUFIN/GPRS_INT1 not generated (default) 1 GPRS_BUFIN/GPRS_INT1 generation if: WR in STAT >= BURSTSIZE if XOR_DIS = '0' or The bit counter in UMTS f8 mode has reached the value programmed in register LENGTH if XOR_DIS = '1' and CIPH_CTRL = '1'.For details on programming this bit please check Table 18 and Table 19. Buffer Out Enable This bit is only valid for MIN_INT="1"! 0 GPRS_BUFOUT not generated (default) 1 GPRS_BUFOUT generation if: RD in STAT >= BURSTSIZE or BCCC is worked out (only for BC_EN="1") For details on programming this bit please check Table 18. Interrupt Enable This bit is only valid for MIN_INT="1"! The status of this bit can be read via bit INT_STAT. 0 GPRS_INT0 not generated (default) 1 GPRS_INT0 generation if: WR+RD in STAT = 32 (all data in DATA are processed) For details on programming this bit please check Table 18. Note: This bit must not be set for DMA transfers! Minimized Interrupt 0 Minimized interrupt generation frequency disabled (default) 1 Minimized interrupt generation frequency enabled For details on programming this bit please check Table 18. Mode 0 GEA1 ciphering mode if bit GEA3_UMTS is '0' (default) 1 GEA2 ciphering mode if bit GEA3_UMTS is '0' Note: This bit performs different if bit GEA3_UMTS is set! In GEA3/UMTS f8 mode this bit must be '0', in UMTS f9 mode '1' (see Table 21). Cipher Control This bit is only valid for BC_EN = "0" (Byte count disabled)! 0 Ciphering switched off 1 Ciphering switched on Notes: 1. This bit has to be set in all cipher modes (GPRS, UMTS) if the corresponding algorithm (GEA1/2/3, f8) shall be performed! 2. This bit in combination with XOR_DIS has effect on the DMA BUFIN request generation (see Table 18 and Table 19) CRC Control This bit is only valid for BC_EN = "0" (Byte count disabled)! 0 CRC calculation switched off, necessary for unprotected data stream 1 CRC calculation switched on Note: As the CRC was originally implemented for GPRS mode, it is not recommended to use CRC in UMTS mode! Initialisation Bit The initialisation bit is set to "1" by the MCU. The status of this bit can be read via bit INIT_STAT 0 No operation 1 Start of initialization Direction Selects the encoding resp. decoding procedure for GEA1 and GEA2 0 Uplink channel 1 Downlink channel Note: In the UMTS f8 case this bit also indicates how the bitfield OFFSET operates on the ciphering process. Request Flag Set Bit 0 No action 1 Set request flag SRR (no action if CLRR = 1) Written value is not stored. Read returns 0. Request Flag Clear Bit 0 No action 1 Clear request flag SRR (no action if SETR = 1) Written value is not stored. Read returns 0. Service Request Flag 0 No service request pending 1 A service request is pending Service Request Enable Control 0 Service request is disabled 1 Service request is enabled Type-of-Service Control 0 Request CPU service (Service Provider 0) 1 Request DMA service (Service Provider 1) Not all SRN can request DMA service. See column DMA Support in Table Interrupt Source List Request Flag Set Bit 0 No action 1 Set request flag SRR (no action if CLRR = 1) Written value is not stored. Read returns 0. Request Flag Clear Bit 0 No action 1 Clear request flag SRR (no action if SETR = 1) Written value is not stored. Read returns 0. Service Request Flag 0 No service request pending 1 A service request is pending Service Request Enable Control 0 Service request is disabled 1 Service request is enabled Type-of-Service Control 0 Request CPU service (Service Provider 0) 1 Request DMA service (Service Provider 1) Not all SRN can request DMA service. See column DMA Support in Table Interrupt Source List Maximum output width in pixels Number of bits coding position in virtual screen Number of bits of fractional part of internal fixed point values Number of bits of internal fixed point values Number of bits for stride storage Starts the image transfer. Autoreset High while image accelerator is busy High while LCD controller is busy High when End Of Frame IRQ has been generated.
To clear it, write 1 in this bit or in eof_status. Unmasked version of eof_cause.
To clear it, write 1 in this bit or in eof_status. EOF interrupt generation mask:
0: EOF IRQ disabled
1: EOF IRQ enabled LCD Region Of Interest Top-Left pixel x-axis LCD Region Of Interest Top-Left pixel y-axis LCD Region Of Interest Bottom-Right pixel x-axis LCD Region Of Interest Bottom-Right pixel y-axis Blue component of the ROI background color Green component of the ROI background color Red component of the ROI background color Input image format
00b: RGB565 pixel packed
01b: YUV4:2:2 pixel packed (UYVY)
10b: YUV4:2:2 pixel packed (YUYV)
11b: YUV4:2:0 planar (IYUV) Image stride in bytes (of Y component for planar formats).
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Defines Layer's activity:
0: Layer disabled
1: Layer active Video Layer (layer 0) Top-Left pixel x-axis position Video Layer (layer 0) Top-Left pixel y-axis position Video Layer (layer 0) Bottom-Right pixel x-axis position Video Layer (layer 0) Bottom-Right pixel y-axis position Number of lines of source image (idem gd_vl_br_ppos.y1 when vertical scaling factor is one). Number of columns of source image (idem gd_vl_br_ppos.x1 when vertical scaling factor is one). Blue component of the Chroma Key Green component of the Chroma Key Red component of the Chroma Key Enables the Chroma Keying Allows a range of color for the Chroma Keying:
000b: exact color match
001b: disregard 1 LSBit of each color component for matching
011b: disregard 2 LSBit of each color component for matching
111b: disregard 3 LSBit of each color component for matching Layer Alpha blending coefficient Layer rotation selection
00b: No rotation
01b: 90 degrees rotation (clockwise)
10b: reserved
11b: reserved Layer depth
00b: Video layer behind all Overlay layers
01b: Video layer between Overlay layers 1 and 0
10b: Video layer between Overlay layers 2 and 1
11b: Video layer on top of all Overlay layers Dword-aligned address of the Y component (or RGB) of the source image Dword-aligned address of the U component of the source image Dword-aligned address of the V component of the source image Video layer rescaling ratio upon x-axis. This is a 2.8 fixed point number representing the input/output width ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. Video layer rescaling ratio upon y-axis. This is a 2.8 fixed point number representing the input/output height ratio. The Overlay layers have a fixed depth relative to their index. Overlay layer 0 is the first to be drawn (thus the deepest), overlay layer 2 is the last to be drawn. Input image format
0: RGB565 pixel packed
1: ARGB8888 pixel packed
others: reserved Image stride in 16-bits word.
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Image stride in 16-bits word.
This is the length from the beginning of a line to the beginning of the next line (can be different from image width * pixel size). Defines Layer's activity:
0: Layer disabled
1: Layer active Overlay Layer (layer X+1) Top-Left pixel x-axis position Overlay Layer (layer X+1) Top-Left pixel y-axis position Overlay Layer (layer X+1) Bottom-Right pixel x-axis position Overlay Layer (layer X+1) Bottom-Right pixel y-axis position Blue component of the Chroma Key Green component of the Chroma Key Red component of the Chroma Key Enables the Chroma Keying Allows a range of color for the Chroma Keying:
000b: exact color match
001b: disregard 1 LSBit of each color component for matching
011b: disregard 2 LSBit of each color component for matching
111b: disregard 3 LSBit of each color component for matching Layer Alpha blending coefficient Dword-aligned address of the source image Destination Selection Output format
000b: 8-bit - RGB3:3:2 - 1cycle/1pixel - RRRGGGBB
001b: 8-bit - RGB4:4:4 - 3cycle/2pixel - RRRRGGGG/BBBBRRRR/GGGGBBBB
010b: 8-bit - RGB5:6:5 - 2cycle/1pixel - RRRRRGGG/GGGBBBBB
011b: reserved
100b: 16-bit - RGB3:3:2 - 1cycle/2pixel - RRRGGGBBRRRGGGBB
101b: 16-bit - RGB4:4:4 - 1cycle/1pixel - XXXXRRRRGGGGBBBB
110b: 16-bit - RGB5:6:5 - 1cycle/1pixel - RRRRRGGGGGGBBBBB
111b: 32-bit - RGB5:6:5 - 1cycle/2pixel - RRRRRGGGGGGBBBBB/RRRRRGGGGGGBBBBB

The MSB select also the AHB access size (8-bit or 16-bit) when Memory destination is selected.
Must set to RGB565 when RAM type destination selected Change Polarity of CS0 signal
0: no change
1: Inverted Change Polarity of CS1 signal
0: no change
1: Inverted Change Polarity of RS signal
0: no change
1: Inverted Change Polarity of WR signal
0: no change
1: Inverted Change Polarity of RD signal
0: no change
1: Inverted Number of command to be send to the LCD command (up to 31) Start command transfer only. Autoreset LCD reset signal. Low active All value are in cycle number of system clock Address setup time (RS to WR, RS to RD) Adress hold time Pulse Width Low level, between 2 and 63. Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). Address destination pointer when memory destination is selected.
The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
This 2D feature allows for in-memory image compositing. data to write or data readen (the readen data is ready when the lcd is not busy) Acesss type selection
0: Command
1: Data Start a single write access. Autoreset Start a single read access (only when LCD output selected). Autoreset. 0:4 line mode 1:3 line mode 2:command mode 3:3 line 2 lane mode tx Mirror enable. . . . . Count value to detect vsync pulse 0:vsync te only 1:vsync and hsync te Pol select Te enable. Te counter value Gouda internal Sram space Starts the image transfer. Autoreset High while image accelerator is busy High while LCD controller is busy High when End Of Frame IRQ has been generated.
To clear it, write 1 in this bit or in eof_status. Vsync rise interrupt. Vsync fall interrupt Dpi overflow interrupt Frame over interrupt. interrupt. Unmasked version of eof_cause.
To clear it, write 1 in this bit or in eof_status. EOF interrupt generation mask:
0: EOF IRQ disabled
1: EOF IRQ enabled Vsync rise interrupt. Vsync fall interrupt. Dpi overflow interrupt. Frame over interrupt. Mipi interrupt Destination Selection Output format, when Destination is Memory
110b: 16-bit - RGB5:6:5
111b: 32-bit - ARGB8:8:8:8 exchange high byte and low byte, when output data bus width is 16 bit Change Polarity of CS0 signal
0: no change
1: Inverted Change Polarity of CS1 signal
0: no change
1: Inverted Change Polarity of RS signal
0: no change
1: Inverted Change Polarity of WR signal
0: no change
1: Inverted Change Polarity of RD signal
0: no change
1: Inverted gamma enable output data bus width select,when use mcu port
0: 16bit rgb565
1: 18bit rgb666
2: 24bit rgb888 All value are in cycle number of system clock Address setup time (RS to WR, RS to RD) Adress hold time Pulse Width Low level, between 2 and 63. Pulse Width High level, between 2 and 63 (must be > (TAH+TAS) ). Address destination pointer when memory destination is selected.
The addr_dst[1] which correspond to the M_A[0] on the memory interface is used to select between command/data. Address offset (in Bytes) skipped at the end of each line when memory destination is selected.
This 2D feature allows for in-memory image compositing. data to write or data readen (the readen data is ready when the lcd is not busy) Acesss type selection
0: Command
1: Data Start a single write access. Autoreset Start a single read access (only when LCD output selected). Autoreset. 0:4 line mode 1:3 line mode 2:command mode 3:3 line 2 lane mode tx For vsync to hsync setup. whether wait for data, when data is not ready for transfer control outstanding number if this bit is enable and dsi is enable. lcdc will stop at the end of a frame.
this is used to send mipi cmd control actions to take, when fifo underflow arise
bit0:control when fifo is underflow, output zero or data in the fifo.
0:output data in the fifo
1:output zero
bit1:whether clear fifo at the end of a frame, when fifo is underflow.
0:not clear
1:clear 0:24bit 1:16bit. 2:18bit Mipi enable. Rgb panel disable output data. Rgb panel disable output clock. Rgb panel disable output all. 00:rgb565 01:rgb888 10:xrgb8888 11:rgbx8888. 0:RGB 1:BGR. Frame2 use. Frame1 use. Rgb panel enable. Frame0 line step,in byte. Frame 0 valid. Frame1 line step,in byte. Frame 1 valid. Frame2 line step,in byte. Frame 2 valid. Vertical pix num. Horizontal pix num. Data fifo threshold when req axi. Dpi fifo auto reset enable when occur overflow . Dpi fifo reset. Throttle period. delay time between read requests Dpi dma throttle enable. adjust dot clock phase. unit is fast dpi clock Data enable pol. Vsync pol. Hsync pol. Dot clock pol. dot clock div. vsync back porch + vsync display period. vsync back porch num. vsync low pulse width. vsync period - 1. hsync low pulse width. hsync period -1. data enable end. data enable start. 0:8bits to 6bits 1:8bits to 5bits 0:8bits to 6bits 1:8bits to 5bits 0:8bits to 6bits 1:8bits to 5bits 0: bypass mode
1: 2x2 mode
2: 4x4 mode
3: lfsr mode 0: bypass mode
1: 2x2 mode
2: 4x4 mode
3: lfsr mode 0: bypass mode
1: 2x2 mode
2: 4x4 mode
3: lfsr mode linear feedback shift register initial data Count value to detect vsync pulse 0:vsync te only 1:vsync and hsync te Pol select Te enable. count hsync after vsync have been detected. Use to delay between rgb data over and fetch the next frame data. .count by hclk address data will be write to address address data will be write to address address data will be write to address Dsi pll power up Power up dsi Enable digital dsi 1'b1: use the config register value 1'b0: use the compute value of controller 2'b00: x1 2'b01: x2 2'b10: x4 2'b11: hz write '1' to clear sleep out done interrupt write '1' to clear frame done interrupt write '1' to clear rx te(tearing effect) interrupt write '1' to clear rx fifo half full interrupt write '1' to clear rx fifo overflow interrupt write '1' to clear command queue tx end interrupt write '1' to clear rx data end interrupt write '1' to clear rx crc error interrupt write '1' to clear rx ecc error interrupt write '1' to clear rx bta timeout interrupt write '1' to clear contention detect interrupt sleep out done en frame done en rx te(tearing effect) en rx fifo half full en rx fifo overflow en command queue tx end en rx data end en rx crc error en rx ecc error en rx bta timeout en contention detect error en clear the packet header stored in registers from lcd. auto-clear Reset the read pointer of queue which store the long packet payload Reset the write index of fifo which store the data read from lcd Reset the read index of fifo which store the data read from lcd rx fifo empty flag sleep out done flag frame done flag rx te(tearing effect) flag rx fifo half full flag rx fifo overflow flag command queue tx end flag rx data end flag rx crc error flag rx ecc error flag rx bta timeout flag contention detect error flag sleep out done cause frame done cause rx te(tearing effect) cause rx fifo half full cause rx fifo overflow cause command queue tx end cause rx data end cause rx crc error cause rx ecc error cause rx bta timeout cause contention detect error cause receive payload byte0~3 of long packet from lcd
[31:24]: byte3
[23:16]: byte2
[15:8]: byte1
[7:0]: byte0 receive payload of long packet from lcd stored in the FIFO.
The value indicates the word count of FIFO. The value is to count the time that lprx0 and lpcd0 are not equal. config the transmission at cmd mode
[31:24]: data byte 1 of command
[23:16]: data byte 0 of command
[15:8]: data ID of command
[6:5]: cmd_type
2'b00,01: short packet
2'b10,11: long packet
[3:2]: 2'b00,2'b01: cmd_ddr_enable
enable to get long packet payload from ddr
2'b10: cmd_buf_enable
enable to write frame buffer at cmd mode, only for high speed.
2'b11: cmd_reg_enable
enable to get long packet payload from register
bit1: cmd_hs_enable
enable high-speed transmission
bit0: cmd_bta_enable
enable bta config the transmission at cmd mode
[31:24]: data byte 1 of command
[23:16]: data byte 0 of command
[15:8]: data ID of command
[6:5]: cmd_type
2'b00,01: short packet
2'b10,11: long packet
[3:2]: 2'b00,2'b01: cmd_ddr_enable
enable to get long packet payload from ddr
2'b10: cmd_buf_enable
enable to write frame buffer at cmd mode, only for high speed.
2'b11: cmd_reg_enable
enable to get long packet payload from register
bit1: cmd_hs_enable
enable high-speed transmission
bit0: cmd_bta_enable
enable bta config the transmission at cmd mode
[31:24]: data byte 1 of command
[23:16]: data byte 0 of command
[15:8]: data ID of command
[6:5]: cmd_type
2'b00,01: short packet
2'b10,11: long packet
[3:2]: 2'b00,2'b01: cmd_ddr_enable
enable to get long packet payload from ddr
2'b10: cmd_buf_enable
enable to write frame buffer at cmd mode, only for high speed.
2'b11: cmd_reg_enable
enable to get long packet payload from register
bit1: cmd_hs_enable
enable high-speed transmission
bit0: cmd_bta_enable
enable bta read from lcd corresponding cmd queue index
[7:0]:DI
[15:8]: SP data0 or LP WC LS BYTE
[23:16]: SP data1 or LP WC MS BYTE
[24]: ack response
[25]: te response
[26]: lpdt response
[27]: ECC error flag
[28]: LP CRC error flag
[29]: Acknowledge and Error Report flag read from lcd corresponding cmd queue index
[7:0]:DI
[15:8]: SP data0 or LP WC LS BYTE
[23:16]: SP data1 or LP WC MS BYTE
[24]: ack response
[25]: te response
[26]: lpdt response
[27]: ECC error flag
[28]: LP CRC error flag
[29]: Acknowledge and Error Report flag spi flash command to send. spi flash address to send. spi flash modebit,set 0xA0 to enable continuous read. spi flash spi read/write block size. spi flash data to send. spi send byte, 1: quad send 0: spi send. spi flash busy. tx fifo empty. tx fifo full. rx fifo empty. rx fifo data count. read busy. nand int . spiflash_int = nand_int and nand_int_mask . flash rx status. spi flash read mode from AHB. spi flash wprotect pin. spi flash hold pin. spi flash read sample delay cycles. spi flash clock divider. spi flash send command using quad lines. rx fifo_clr,self clear. tx fifo_clr,self clear. spi flash cs num. single chip spi flash size. spi flash is 128m flash. disable read from ahb. sel flash 1, addr[24]. addr[25]. diff 128m diff cmd en. spi_256m. spi_512m. spi_cs1_sel2. spi_1g . spi_2g. spi_4g. spi_cs1_sel3. spi_cs1_sel4. spi_cs1_sel5. quad read command. fast read command. fast read command. protect_byte, must be 0x55 when program this register. Global enable for forwarding pending Group 1 interrupts from the Distributor to the CPU interfaces: 0 Group 1 interrupts not forward. 1 Group 1 interrupts forwarded, subject to the priority rules. Global enable for forwarding pending Group 0 interrupts from the Distributor to the CPU interfaces: 0 Group 0 interrupts not forwarded. 1 Group 0 interrupts forwarded, subject to the priority rules. If the GIC implements the Security Extensions, the value of this field is the maximum number of implemented lockable SPIs, from 0 (0b00000) to 31 (0b11111), see Configuration lockdown on page 4-82. If this field is 0b00000 then the GIC does not implement configuration lockdown. If the GIC does not implement the Security Extensions, this field is reserved. Indicates whether the GIC implements the Security Extensions. 0 Security Extensions not implemented. 1 Security Extensions implemented. Indicates the number of implemented CPU interfaces. The number of implemented CPU interfaces is one more than the value of this field, for example if this field is 0b011, there are four CPU interfaces. If the GIC implements the Virtualization Extensions, this is also the number of virtual CPU interfaces. Indicates the maximum number of interrupts that the GIC supports. If ITLinesNumber=N, the maximum number of interrupts is 32(N+1). The interrupt ID range is from 0 to (number of IDs C 1). For example: 0b00011 Up to 128 interrupt lines, interrupt IDs 0-127. The maximum number of interrupts is 1020 (0b11111). See the text in this section for more information. Regardless of the range of interrupt IDs defined by this field, interrupt IDs 1020-1023 are reserved for special purposes. Product ID An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish product variants, or major revisions of a product. An IMPLEMENTATION DEFINED revision number. Typically, this field is used to distinguish minor revisions of a product. Contains the JEP106 code of the company that implemented the GIC Distributor: Bits [11:8] The JEP106 continuation code of the implementer. For an ARM implementation, this field is 0x4. Bits [7] Always 0. Bits [6:0] The JEP106 identity code of the implementer. For an ARM implementation, bits[7:0] are 0x3B. The GICD_IGROUPR registers provide a status bit for each interrupt supported by the GIC. Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. Accessible by Secure accesses Only. For each bit: 0 The corresponding interrupt is Group 0. 1 The corresponding interrupt is Group 1.For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_IGROUPRn number, n, is given by n = m DIV 32 b. the offset of the required GICD_IGROUPR is (0x080 + (4*n)) c. the bit number of the required group status bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ISENABLERs provide a Set-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Enables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ISENABLER number, n, is given by n = m DIV 32 b.the offset of the required GICD_ISENABLER is (0x100 + (4*n)) c.the bit number of the required Set-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ICENABLERs provide a Clear-enable bit for each interrupt supported by the GIC. For SPIs and PPIs, each bit controls the forwarding of the corresponding interrupt from the Distributor to the CPU interfaces: Reads 0 Forwarding of the corresponding interrupt is disabled. 1 Forwarding of the corresponding interrupt is enabled. Writes 0 Has no effect. 1 Disables the forwarding of the corresponding interrupt. After a write of 1 to a bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a.the corresponding GICD_ICENABLERn number, n, is given by m = n DIV 32 b.the offset of the required GICD_ICENABLERn is (0x180 + (4*n)) c.the bit number of the required Clear-enable bit in this register is m MOD 32. The GICD_ISPENDRs provide a Set-pending bit for each interrupt supported by the GIC. For each bit: Reads 0 The corresponding interrupt is not pending on any processor. 1 a. For PPIs and SGIs, the corresponding interrupt is pendinga on this processor. b. For SPIs, the corresponding interrupt is pendinga on at least one processor. Writes For SPIs and PPIs: 0 Has no effect. 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered Changes the status of the corresponding interrupt to: a.pending if it was previously inactive b.active and pending if it was previously active. Has no effect if the interrupt is already pending. Level sensitive If the corresponding interrupt is not pendinga, changes the status of the corresponding interrupt to: a. pending if it was previously inactive b. active and pending if it was previously active. If the interrupt is already pending: a. because of a write to the GICD_ISPENDR, the write has no effect. b. because the corresponding interrupt signal is asserted, the write has no effect on the status of the interrupt, but the interrupt remains pendinga if the interrupt signal is deasserted. For SGIs, the write is ignored. SGIs have their own Set-Pending registers. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ISPENDR number, n, is given by n = m DIV 32 b. the offset of the required GICD_ISPENDR is (0x200 + (4*n)) c. the bit number of the required Set-pending bit in this register is m MOD 32. The GICD_ICPENDRs provide a Clear-pending bit for each interrupt supported by the GIC. For each bit: Reads 0 The corresponding interrupt is not pending on any processor. 1 a. For SGIs and PPIs, the corresponding interrupt is pendinga on this processor. b. For SPIs, the corresponding interrupt is pendinga on at least one processor. Writes For SPIs and PPIs: 0 Has no effect. 1 The effect depends on whether the interrupt is edge-triggered or level-sensitive: Edge-triggered Changes the status of the corresponding interrupt to: a. inactive if it was previously pending b. active if it was previously active and pending. Has no effect if the interrupt is not pending. Level-sensitive If the corresponding interrupt is pendinga only because of a write to GICD_ISPENDRn, the write changes the status of the interrupt to: a. inactive if it was previously pending b. active if it was previously active and pending. Otherwise the interrupt remains pending if the interrupt signal remains asserted. For SGIs, the write is ignored. SGIs have their own Clear-Pending registers. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICPENDR number, n, is given by n = m DIV 32 b. the offset of the required GICD_ICPENDR is (0x280 + (4*n)) c. the bit number of the required Set-pending bit in this register is m MOD 32. The GICD_ISACTIVERs provide a Set-active bit for each interrupt that the GIC supports. For each bit: Reads 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active. Writes 0 Has no effect. 1 Activates the corresponding interrupt, if it is not already active. If the interrupt is already active, the write has no effect. After a write of 1 to this bit, a subsequent read of the bit returns the value 1. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ISACTIVERn number, n, is given by n = m DIV 32 b. the offset of the required GICD_ISACTIVERn is (0x300 + (4*n)) c. the bit number of the required Set-active bit in this register is m MOD 32. The GICD_ICACTIVERs provide a Clear-active bit for each interrupt that the GIC supports. For each bit: Reads 0 The corresponding interrupt is not activea. 1 The corresponding interrupt is activea. Writes 0 Has no effect. 1 Deactivates the corresponding interrupt, if the interrupt is active. If the interrupt is already deactivated, the write has no effect. After a write of 1 to this bit, a subsequent read of the bit returns the value 0. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICACTIVERn number, n, is given by n = m DIV 32 b. the offset of the required GICD_ICACTIVERn is (0x380 + (4*n)) c. the bit number of the required Clear-active bit in this register is m MOD 32. The GICD_IPRIORITYRs provide an 8-bit priority field for each interrupt supported by the GIC. Each priority field holds a priority value, from an IMPLEMENTATION DEFINED range. The lower the value, the greater the priority of the corresponding interrupt. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_IPRIORITYRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_IPRIORITYRn is (0x400 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ITARGETSRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each field returns a value that corresponds only to the processor reading the register. Processors in the system number from 0, and each bit in a CPU targets field refers to the corresponding processor. For example, a value of 0x3 means that the Pending interrupt is sent to processors 0 and 1. For GICD_ITARGETSR0 to GICD_ITARGETSR7, a read of any CPU targets field returns the number of the processor performing the read. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ITARGETSRn number, n, is given by n = m DIV 4 b. the offset of the required GICD_ITARGETSR is (0x800 + (4*n)) c. the byte offset of the required Priority field in this register is m MOD 4, where: (1) byte offset 0 refers to register bits [7:0] (2) byte offset 1 refers to register bits [15:8] (3) byte offset 2 refers to register bits [23:16] (4) byte offset 3 refers to register bits [31:24]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. The GICD_ICFGRs provide a 2-bit Int_config field for each interrupt supported by the GIC. For Int_config[1], the most significant bit, bit [2F+1], the encoding is: 0 Corresponding interrupt is level-sensitive. 1 Corresponding interrupt is edge-triggered. Int_config[0], the least significant bit, bit [2F], reserved For SGIs: Int_config[1] Not programmable, RAO/WI. For PPIs: Int_config[1] Not programmable, RAZ/WI. For SPIs: Int_config[1] For SPIs, this bit is programmable. A read of this bit always returns the correct value to indicate whether the corresponding interrupt is level-sensitive or edge-triggered. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_ICFGR number, n, is given by n = m DIV 16 b. the offset of the required GICD_ICFGRn is (0xC00 + (4*n)) c. the required Priority field in this register, F, is given by F = m MOD 16, where field 0 refers to register bits [1:0], field 1 refers to bits [3:2], up to field 15 that refers to bits [31:30]. Asserted when the PPI inputs to the Distributor are active. ID 31 nLEGACYIRQ signal ID 30 Non-secure physical timer event ID 29 Secure physical timer event ID 28 nLEGACYFIQ signal ID 27 Virtual timer event ID 26 Hypervisor timer event ID 25 Virtual maintenance interrupt. Returns the status of the IRQS inputs on the Distributor. For each bit: 0 IRQS is LOW 1 IRQS is HIGH. The GICD_NSACRs enable Secure software to permit Non-secure software on a particular processor to create and manage Group 0 interrupts. They provide an access control for each implemented interrupt. If the corresponding interrupt does not support configurable Non-secure access, the field is RAZ/WI. Otherwise, the field is RW and configures the level of Non-secure access permitted when the interrupt is in Group 0. If the interrupt is in Group 1, this field is ignored. The possible values of the field are: 0b00 No Non-secure access is permitted to fields associated with the corresponding interrupt. 0b01 Non-secure write access is permitted to fields associated with the corresponding interrupt in the GICD_ISPENDRn registers. A Non-secure write access to GICD_SGIR is permitted to generate a Group 0 SGI for the corresponding interrupt. 0b10 Adds Non-secure write access permission to fields associated with the corresponding interrupt in the GICD_ICPENDRn registers. Also adds Non-secure read access permission to fields associated with the corresponding interrupt in the GICD_ISACTIVERn and GICD_ICACTIVERn registers. 0b11 Adds Non-secure read and write access permission to fields associated with the corresponding interrupt in the GICD_ITARGETSRn registers. The GICD_NSACRn registers do not support PPI accesses, meaning that GICD_NSACR0 bits [31:16] are RAZ/WI. For interrupt ID m, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_NSACR number, n, is given by n = m DIV 16 b. the offset of the required GICD_NSACRn is (0xE00 + (4*n)). Determines how the distributor must process the requested SGI: 0b00 Forward the interrupt to the CPU interfaces specified in the CPUTargetList fielda. 0b01 Forward the interrupt to all CPU interfaces except that of the processor that requested the interrupt. 0b10 Forward the interrupt only to the CPU interface of the processor that requested the interrupt. 0b11 Reserved. When TargetList Filter = 0b00, defines the CPU interfaces to which the Distributor must forward the interrupt. Each bit of CPUTargetList[7:0] refers to the corresponding CPU interface, for example CPUTargetList[0] corresponds to CPU interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface. If this field is 0x00 when TargetListFilter is 0b00, the Distributor does not forward the interrupt to any CPU interface. Implemented only if the GIC includes the Security Extensions. Specifies the required security value of the SGI: 0 Forward the SGI specified in the SGIINTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface. 1 Forward the SGI specified in the SGIINTID field to a specified CPU interfaces only if the SGI is configured as Group 1 on that interface. This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write. The Interrupt ID of the SGI to forward to the specified CPU interfaces. The value of this field is the Interrupt ID, in the range 0-15, for example a value of 0b0011 specifies Interrupt ID 3. The GICD_CPENDSGIRs provide a clear-pending bit for each supported SGI and source processor combination. For each bit: Reads 0 SGI x from the corresponding processor is not pending. 1 SGI x from the corresponding processor is pending. Writes 0 Has no effect. 1 Removes the pending state of SGI x for the corresponding processor. For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_CPENDSGIR register number, n, is given by n = x DIV 4 b. the offset of the required GICD_CPENDSGIR is (0xF10 + (4*n)); c. the SGI Clear-pending field offset, y, is given by y = x MOD 4 d. the required bit in the SGI x Clear-pending field is bit C. The GICD_SPENDSGIRn registers provide a set-pending bit for each supported SGI and source processor combination. For each bit: Reads 0 SGI x for the corresponding processor is not pendinga. 1 SGI x for the corresponding processor is pendinga. Writes 0 Has no effect. 1 Adds the pending state of SGI x for the corresponding processor, if it is not already pending. If SGI x is already pending for the corresponding processor then the write has no effect. For SGI ID x, generated by CPU C writing to its GICD_SGIR, when DIV and MOD are the integer division and modulo operations: a. the corresponding GICD_SPENDSGIR register number, n, is given by n = x DIV 4 b. the offset of the required GICD_SPENDSGIR is (0xF20 + (4*n)) c. the SGI Set-pending field offset, y, is given by y = x MOD 4 d. the required bit in the SGI x Set-pending field is bit C. Alias of EOImodeNS from the Non-secure copy of this register. Controls the behavior of accesses to GICC_EOIR and GICC_DIR registers. In a GIC implementation that includes the Security Extensions, this control applies only to Secure accesses, and the EOImodeNS bit controls the behavior of Non-secure accesses to these registers: 0 GICC_EOIR has both priority drop and deactivate interrupt functionality. Accesses to the GICC_DIR are UNPREDICTABLE. 1 GICC_EOIR has priority drop functionality only. GICC_DIR has deactivate interrupt functionality. Alias of IRQBypDisGrp1 from the Non-secure copy of this register. Alias of FIQBypDisGrp1 from the Non-secure copy of this register. When the signaling of IRQs by the CPU interface is disabled, this bit partly controls whether the bypass IRQ signal is signaled to the processor: 0 Bypass IRQ signal is signaled to the processor 1 Bypass IRQ signal is not signaled to the processor. When the signaling of FIQs by the CPU interface is disabled, this bit partly controls whether the bypass FIQ signal is signaled to the processor: 0 Bypass FIQ signal is signaled to the processor 1 Bypass FIQ signal is not signaled to the processor. Controls whether the GICC_BPR provides common control to Group 0 and Group 1 interrupts. 0 To determine any preemption, use: ? the GICC_BPR for Group 0 interrupts ? the GICC_ABPR for Group 1 interrupts. 1 To determine any preemption use the GICC_BPR for both Group 0 and Group 1 interrupts. Controls whether the CPU interface signals Group 0 interrupts to a target processor using the FIQ or the IRQ signal. 0 Signal Group 0 interrupts using the IRQ signal. 1 Signal Group 0 interrupts using the FIQ signal. The GIC always signals Group 1 interrupts using the IRQ signal. When the highest priority pending interrupt is a Group 1 interrupt, determines both: ? whether a read of GICC_IAR acknowledges the interrupt, or returns a spurious interrupt ID ? whether a read of GICC_HPPIR returns the ID of the highest priority pending interrupt, or returns a spurious interrupt ID. 0 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR or the GICC_HPPIR returns an Interrupt ID of 1022. A read of the GICC_IAR does not acknowledge the interrupt, and has no effect on the pending status of the interrupt. 1 If the highest priority pending interrupt is a Group 1 interrupt, a read of the GICC_IAR or the GICC_HPPIR returns the Interrupt ID of the Group 1 interrupt. A read of GICC_IAR acknowledges and Activates the interrupt. Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor: 0 Disable signaling of Group 1 interrupts. 1 Enable signaling of Group 1 interrupts. Enable for the signaling of Group 0 interrupts by the CPU interface to the connected processor: 0 Disable signaling of Group 0 interrupts. 1 Enable signaling of Group 0 interrupts. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the processor. If the GIC supports fewer than 256 priority levels then some bits are RAZ/WI, as follows: 128 supported levels Bit [0] = 0. 64 supported levels Bit [1:0] = 0b00. 32 supported levels Bit [2:0] = 0b000. 16 supported levels Bit [3:0] = 0b0000. The value of this field controls how the 8-bit interrupt priority field is split into a group priority field, used to determine interrupt preemption, and a subpriority field. The minimum value of the Binary Point Register depends on which security-banked copy is considered: 0x2 Secure copy 0x3 Non-secure copy For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. The interrupt ID. On a multiprocessor implementation, if the write refers to an SGI, this the CPUID value from the corresponding GICC_IAR access. In all other cases this field SBZ. The Interrupt ID value from the corresponding GICC_IAR access. The current running priority on the CPU interface. On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. In all other cases this field is RAZ. The interrupt ID of the highest priority pending interrupt. See Table 4-42 on page 4-144 for more information about the result of Non-secure reads of the GICC_HPPIR when the GIC implements the Security Extensions. A Binary Point Register for handling Group 1 interrupts. CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. Interrupt ID The interrupt ID. On a multiprocessor implementation, when processing an SGI, this field must contain the CPUID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, access. In all other cases this field SBZ. The Interrupt ID value from the corresponding GICC_AIAR, or Non-secure GICC_IAR, access. On a multiprocessor implementation, if the PENDINTID field returns the ID of an SGI, this field contains the CPUID value for that interrupt. This identifies the processor that generated the interrupt. In all other cases this field is RAZ. The interrupt ID of the highest priority pending interrupt, if that interrupt is a Group 1 interrupt. Otherwise, the spurious interrupt ID, 1023. Active Priorities Registers NonSecure Active Priorities Registers An IMPLEMENTATION DEFINED product identifier. The value of this field depends on the GIC architecture version, as follows: ? 0x1 for GICv1 ? 0x2 for GICv2. An IMPLEMENTATION DEFINED revision number for the CPU interface. Contains the JEP106 code of the company that implemented the GIC CPU interface: Bits [11:8] The JEP106 continuation code of the implementer. Bit [7] Always 0. Bits [6:0] The JEP106 identity code of the implementer. For an SGI in a multiprocessor implementation, this field identifies the processor that requested the interrupt. For all other interrupts this field is RAZ. The interrupt ID Set the direction of the GPIO n.
0 = output
1 = input 'Write '1' sets the corresponding GPIO pin as output. 'Write '1' sets the corresponding GPIO pin as input. When write, update the output value. When read, get the input value. Write '1' will set GPIO output value. When read, get the GPIO output value. 'Write '1' clears corresponding GPIO output value. When read, get the GPIO output value. 'Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt. Each bit represents if there is a GPIO interrupt pending. time for which GPIO0 is set to output mode, after a start read DCON command is issued.
The output time = (OUT_TIME+1)*30.5us. time for which GPIO0 should wait before reading DC_ON, after a start read DCON command is issued.
The wait time = (WAIT_TIME+1)*30.5us.
NOTE: wait_time must be strictly greater than out_time; interruption mode of GPIO0 in mode DC_ON detection.
"00" = send IRQ if last read DCON is '0' and now is '1'. "01" = send IRQ if last read DCON is '1' and now is '0'. "11" = send IRQ every time read is ready. Write '1' to set GPIO0 to charger DCON detect mode. Write '1' to set GPO0 to charger watchdog mode. Write '1' to clear charger DCON detect mode of GPIO0. Write '1' to clear the charger watchdog mode of GPO0. Write '1' to generate a pulse of '0' on GPO0 for 16 CLK_OSC cycles. 'Write '1' will set GPO output value. When read, get the GPO output value. 'Write '1' will clear GPO output value. When read, get the GPO output value. 'Write '1' will set GPIO interrupt mask for rising edge and level high. When read, get the GPIO interrupt mask for rising edge and level high. 'Write '1' will clear GPIO interrupt mask for rising edge and level high. 'Write '1' will enable debounce mechanism. 'Write '1' will disable debounce mechanism. Write '1' will set interruption mode to level. Write '1' will set interruption mode to edge triggered. I2C master enable, high active. I2C master interrupt enable, high active. This register is used to prescale the SCL clock line. Due to the structure of I2C interface, this module uses a 5*SCL clock frequency. Clock_Prescale must be programmed to this 5*SCL clock frequency (minus 1). Change the value of Clock_Prescale only when bit EN is cleared.

Example:
PCLK_MOD is 52 MHz, desired SCL is 100 KHz.
Prescale = 52MHz / (5 * 100KHz) -1 = 103. IRQ Cause bit. This bit is set when one byte transfer has been completed or arbitration is lost, this bit is generated by bit IRQ_Status AND bit IRQ_MASK. IRQ status bit. TIP, Transfer in progress. '1' when transferring data. '0' when transfer complete. AL,Arbitration lost. This bit is set when the I2C master lost arbitration. Busy,I2C bus busy. '1' after START signal detected. '0' after STOP signal detected. RxACK, Received acknowledge from slave. '1'= "No ACK" received. '0'= ACK received. Byte to transmit via I2C.
for Bit 0, In case of a data transfer this bit represents the data's LSB. In case of a slave address transfer this bit represents the RW bit.
'1' = reading from slave.
'0' = writing to slave. Last byte received via I2C. ACK,when master works as a receiver,sent ACK(ACK='0') or NACK(ACK='1'). RD,read from slave, this bit is auto cleared. STO,generate stop condition, this bit is auto cleared. WR,write to slave, this bit is auto cleared. STA,generate (repeated) start condition, this bit is auto cleared. When write '1', clears a pending I2C interrupt. Write 0: disable pagespy; 1: enable pagespy Read 0: pagespy idle; 1: pagespy active Spy interface select, 'b00: interface 0, 'b01: interface 1, 'b10: interface 2, 'b11: interface 3. Enable of One configured time monitor mode. When timer reaches the time threshold, this bit clear to 0 automatically. Enable of long time continuously monitor mode. Enable of a configured access threshold mode. When accesses reaches the threshold, this bit clear to 0 automatically. Enable of address hit mode. Once one access hit the configured address range, this bit clear to 0 automatically. enable monitoring write address hit. enable monitoring read address hit. high 28bit of start address of monitor. high 28bit of end address of monitor. enable timer reach threshold interrupt. enable access reach threshold interrupt enable access hit interrupt In one configured time monitor mode, when timer reach the time threshold, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd In long time continuously monitor mode, when timer reach the time threshold, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd In the configured access threshold monitor mode, when write access num reaches the threshold, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd In the configured access threshold monitor mode, when read access num reaches the threshold, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd In the address hit monitor mode, when one write access hit the address range, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd In the address hit monitor mode, when one read access hit the address range, this interrupt source trigger. Write 1: clear interrupt; 0: ignored Read 1: the one has source triggerd; 0: not source triggerd Write bytes when a monitor finishes in one configured time monitor mode or long time continuously monitor mode. Read bytes when a monitor finishes in one configured time monitor mode or long time continuously monitor mode. Current timer count value interrupt vector for all 16 pagespy channels Enable signal from1 Stage to 2 Stage: 1: 2 Stage work; 0: 2 Stage not work, HOLD state; Inner Enable signal from 2 Stage Control followed module : vad_2stg_probvad_2stg_para_update_feature_minvad_2stg_para_updatemean_adjust. Not Control module vadflag_smooth. 1: Controlled modules work 0: Controlled modules not work 1:vad_dma_req_h is valid 0:vad_dma_req_h is invalid [18]:masked vadflag interrupt [17]:masked wr_full interrupt [16]:masked rd_empty interrupt [14]:raw vadflag interrupt [13]:raw wr_full interrupt [12]:raw rd_empty interrupt Force 2 Stage continue work 1: Force 2 Stage continue work 0: 2Stage normal work (depend vadflag..) Interrupt clear [10]:clear vadflag interrupt [9]:clear wr_full interrupt [8]:clear rd_empty interrupt Enable frame vad_int_pulse(width is 500ns) [18]:mask vadflag interrupt [17]:mask wr_full interrupt [16]:mask rd_empty interrupt 1:write into mem data rate is 16K (hpf_out) 0:write into mem data rate is 8K(hbf_out) 1:Probability four channel coeff(speech_means,noise_means,speech_std,noise_std) 0:Probability four channel coeff from para_update 4 channel output 1:speech_means_adj[i] and noise_means_adj[i] of para_update input is fixed at 100 0:speech_means_adj[i] and noise_means_adj[i] of para_update input is from means_adjust 1:feature_min of noise_mean is fixed at 512 0:feature_min of noise_mean is normal output 1:bypass HPF, note: the output is input reduces hpf_dc_cal 0:normal HPF output The DC of hpf The coeff of hpf The coeff of hpf 1:bypass LPF 0:normal LPF output. The coeff of lpf The coeff of lpf The gain of lpf relative threshold The initial of mean_noise. ABS thd = mean_noise * rela_thd. The cmp_trigger signal depending the comparation between ABS thd and lpf_out's absolute value mean_noise changed in every refresh timer The refresh_timer is more than average_timer 00:begin average_timer = 16'd127 ;cut_bit = 4'd7; end 01:begin average_timer = 16'd255 ;cut_bit = 4'd8; end 10:begin average_timer = 16'd511 ;cut_bit = 4'd9; end 11:begin average_timer = 16'd1023;cut_bit = 4'd10;end unsigned threshold value When LLR[k]*4 > individualtest, vadflag is 1,otherwise 0 unsigned threshold value When sum of all LLR[k] > totaltest, vadflag is 1,otherwise 0 There is a OR relationship with individualtest valdflag smooth module Count the number of successive detected speech frames,no longer count more than 6.After that , when detect no speech frames, smooth the overhead2 frames into speech frames. If less 6, smooth the overhead1 frames into speech frames ditto SFIFO's write address is reset to all 0, high active SFIFO's read address is reset to all 0, high active 0:test_port_s <= {1'b0,speech_stds_0 ,1'b0,speech_means_adj_0 } ; 0: test_port_n <= {1'b0,noise_stds_0 ,1'b0,noise_means_adj_0 } ; {1'b0,speech_stds ,1'b0,speech_means_adj } ; {1'b0,noise_stds ,1'b0,noise_means_adj } Enables the SIM Card IF module Selects the parity generation/detection Parity Error Receive Feed-through
0 = Don't store bytes with detected parity errors
1 = Feed-through bytes with detected parity errors Enable or disable NULL (0x60) character filtering when SIM card sends NULL to reset WWT timer.
0 = Enable NULL character filtering, NULL characters are not reported if not data.
1 = Disable NULL character filtering. NULL characters (0x60) are transferred to the SCI data buffer. Manual SCI Clock Stop control. Manually starts and stops the SCI clock. This bit must be set to '1' when Autostop mode is enabled.
0 = Enable the SCI clock
1 = Disable SCI clock Enables automatic clock shutdown when command is complete. Enabling this will generate the necessary startup and shutdown delays required by the SIM protocol.
0 = Auto clock control not enabled. SCI clock controlled by SCI_Clockstop bit
1 = Auto clock control enabled. Sets the transmission and reception bit order:
0 = LSB is sent/recieved first (Direct convention)
1 = MSB is sent/received first (Inverse convention) Logic Level Invert:
0 = Logic level 0 data is sent/received as '0' or 'A' which is the same as the start bit. (Direct convention)
1 = Logic level 0 data is sent/received as '1' or 'Z' which is the opposite of the start bit. (Inverse convention) Parity Error signal length. This configuration bit can be used to extend the duration of the parity error signal generation from 1 ETU to 1.5 ETU
0 = Parity Error signal duration is 1 ETU starting at 10.5 ETU
1 = Parity Error signal duration is 1.5 ETU starting at 10.5 ETU Enable or disable parity error checking on the receive data
0 = Disable parity error checking
1 = Enable parity error checking Logical value of the clock signal when SCI clock is stopped (either due to automatic shutdown or manual shutdown)
0 = Stop clock at low level
1 = Stop clock at high level Automatic Reset Generator. Write a '1' to this bit to initiate an automatic reset procedure on the SIM. Write '0' to switch back to SCI_Reset control (bit 20). An ARG interrupt will be generated if the ARG process succeeded or failed. The ARG status bit (ARG_Det) must be read to determine if a reset response from the card was detected. This bit needs to be cleared between ARG attempts. Automatic format detection. This bit is generally set in conjunction with the ARG_H bit to enable automatic detection of the data convention.
1 = Enable TS detection and automatic convention settings programming
0 = disable automatic settings and use the register bits (MSBH_LSBL and LLI) to control the convention 1 = Enable automatic resend of characters when Tx parity error is detected
0 = Disable automatic resend Direct connection to the SIM card reset pin. This is overridden when ARG_H is enabled
0 = SCI_Reset low voltage
1 = SCI Reset high voltage This selects between two delay times for the automatic clock stop startup and shutdown:
0 = short delay
Startup/Shutdown : 744 SCI clocks / 1860 SCI clocks
1 = long delay
Startup/Shutdown : (2 x 744) SCI clocks / (2 x 1860) SCI clocks Input data average enable.
0 = Disable
1 = Enable Allows fine control of the parity check position during the parity error time period. Returns the status of the Rx FIFO:
0 = Rx FIFO empty
1 = There is at least 1 character in the Rx FIFO Returns the status of the Tx FIFO:
0 = Tx FIFO is full
1 = There is at least 1 free spot in the Tx FIFO Returns the status of the automatic format detection after reset:
0 = TS character has not been detected in the ATR
1 = TS character has been detected and SCI module is using the automatic convention settings

This bit is cleared when the AFD_En bit is cleared Returns the status of the automatic reset procedure:
0 = ARG detection has failed
1 = ARG detection has detected that the SIM has responded to the reset

This bit is used in conjunction with the ARG interrupt. The ARG interrupt will be generated at the successful or unsuccessful termination of the ARG process. This bit can be used to determine the success or failure. This is the status of the Reset pin when automatic reset generation is enabled. This bit can be used to discover whether the SIM card that has successfully responded to an ARG procedure has an active high or active low reset. (Det means 'Detection') Status of the control signal to the clock control module. This bit respects the startup and shutdown phases, so during these times, the clock may actually be on, but it is not considered to be 'ready'
0 = SCI clock may be on or off but is not ready for use
1 = SCI clock is on and ready for use Status bit of the Sci clock.
0 = Sci clock is ON
1 = Sci clock is OFF A receive parity error was detected. Reading this register clears the bit. A transmit parity error was detected. Reading this register clears the bit. The internal receive FIFO has reached an overflow condition. Reading this register clears the bit. The internal transmit FIFO has reached an overflow condition. Reading this register clears the bit. Returns the state of the clock management state machine when AutoStop mode is enabled. This value is '00' when manual mode is selected. Clock is on, but not ready to be used. Clock is on and ready to be used Clock is still on, but should not be used. Clock is off. Writing to this register will send the data to the SIM card. If automatic clock shutdown is enabled, the appropriate delay will be applied before the data is actually sent. Reading this register will read from the receive data FIFO. Clock divider for generating the baud clock from the SCI clock. This value must match the value used by the SIM card whose default value is 0x174. Speed mode enable.
0 = Low speed mode
1 = High speed mode(372/32, 372/64, 512/64) Rx_clk_cnt wrap value. Secondary clock divider for generating 16x baud clock. Main clock divider to generate the SCI clock. This value should be calculated as follows:
MainDiv = Clk_Sys/(2xSCI_Clk) - 1
where SCI_Clk is in the range of 3-5 MHz as specified in the SIM specification. Inverts the polarity of the SCI clock to the SIM card only.
0 = No inversion
1 = Invert external SCI clock Inverts the polarity of the SCI clock to the SIM card and internal.
0 = No inversion
1 = Invert external SCI clock This value should be programmed with the number of expected characters to receive. It will be decremented each time a character is actually received and should be 0 when the transfer is complete. If a character is sent after the RxCnt reaches zero, the extra character flag will be set but this value will stay at zero. When in automatic clock shutdown mode, this bit can prevent the clock from entering shutdown mode when the transfer is complete. This should be used for multi-transfer commands where the clock must not be shut down until the command is complete. This bit must be programmed for each transfer.
1 = Keep clock on
0 = Allow clock shutdown when transfer is complete This is the extra guard time that can be added to the 2 ETU minimum (and default) guard time between successive transmitted characters. This should be programmed depending on the SIM's ATR. The total ETU guard time will be ChGuard + 1. Turnaround guard time configuration. This value can be used to adjust the delay between the leading edge of a received character and the leading edge of the next transmitted character. The minimum time specified in the SIM recommendation is 16 ETU. The number of ETUs can be calculated using the following formula:
Total Turnaround Time (in ETUs) = 11 + TurnaroundGuard Work Waiting Time factor. A timeout will be generated when the WWT is exceeded. The WWT is calculated by:
WWT = 960 x WI x (F/Fi)
where Fi is the main SCI clock frequency (3-5 MHz) and F is 372 before an enhanced PPS and 512 after an enhanced PPS.
The SCI_WI value must be calculated as follows:
SCI_WI = WI * D
Thus, by default (WI = 10) this value needs to be set to 10 before an EPPS, but needs to be scaled to WI*D=80 after the EPPS procedure. Number of times to try resending character when the SIM indicates a parity error. Value of the character to be filtered. 0x60 is the NULL character in the SIM protocol. If character filtering is enabled, the first 0x60 character that is received by the SIM during a transfer will not be recorded. The purpose of this character is to enable the SIM to reset the WWT counter when the SIM is not ready to send the data. This filter has no effect on characters within the datastream. Clear RX FIFO. Clear TX FIFO. clear RX/TX FIFO Number of expected Rx characters, as programmed in the RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is a READ ONLY register that returns the logical and of the SCI_INT_STATUS register and the SCI_INT_MASK. If any of these bits is '1', the SCI module will generate an interrupt. Bits 21:16 return the status of the interrupt which is the interrupt state before the mask is applied. These bits should only be used for debugging. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This is a WRITE ONLY register that is used to clear an SCI interrupt. Write a '1' to the interrupt that is to be cleared. Writing '0' has no effect. Number of expected Rx characters, as programmed in the SCI_RxCnt register, has been received. Receiver FIFO is half full. No Tx character has been sent NOR any Rx character detected within the WWT timeout. An extra character has been received after the number of characters in SCI_RxCnt has been received. The automatic re-transmit of parity error characters has exceeded the threshold specified in the SCI_Tx_PERT field. End of the ARG sequence. The status register must be read to determine whether the ARG sequence was successful or not. DMA tx done. DMA rx done. This register is READ/WRITE register that enables the desired interrupt. A '1' in a bit position indicates that the corresponding interrupt is enabled and if the interrupt occurs, the SCI will generate a hardware interrupt. Lps Skip Frame Enable.
When enabled the frame interrupt are masked until the programmed number of frames are elapsed.
This is done by masking the frame interrupt line from the regular TCU counter, and counting the frames. Also when activating the LowPower SkipFrame the frame counter is tranfered to the low power counter that will update it based on the 32kHz Clock. Controls the Lps Low Power Counters (counters at 32kHz) usage. Disable the Low Power Counters. The Low Power Counters are started in Skip Frame Mode. In this mode the Low Power Counter are used to maintain the Time base, The Skip Frame Must be enabled as this is the Low Power extention of the Skip Frame feature. Start the calibration. The Low Power Counters are used to Calibrate the 32kHz clock against the System Clock, The Calibration is required to compensate from temperature variation. Note that the Skip Frame can also be enabled during calibration (but not with low power). Enable fake Fint used with wakeupNumber=0. Enable fake Fint when sys_sf_frame_count>=cfg_sf_frame.
Default sys_sf_frame_count>cfg_sf_frame. Lps Skip Frame Ready, status of the state machines to keep valid state between system clock and 32Khz clock.
Must read as '1' before entering Low Power Skip Frame or Calibration mode. '1' when Lps Skip Frame Low Power Counters are Running.
When entering Low Power Skip Frame, the counters are not immediately started, they wait for the nextFrame interrupt. Reading this status allow to know if the counters are running, and the System Clock can be safely disabled. '1' when the Lps Skip Frame Calibration is Done. '1' when the Lps Skip Frame Power-up sequence frame is reached. '1' when tcu counter is restarted. Number of frames to Skip.
If the power up sequence is enabled, frames are skipped until both this number is reached and the powerup sequence has finished.
Note: The power up sequence must be Done before the the frame LPS_SF_Frame ends. Number of frames before activating the Power-up sequence. For LowPower SkipFrame mode: Value to restart TCU (and frame interrupt generation) on the system clock counter after a low power phase.
For Calibration mode: number of 32k cycles for the calibration. Value of the frame period in system clock count. The rate is the number of System Clocks per 32kHz Clocks. Integer part of the rate. Fractional part of the rate. Current number of elapsed frames.
Valid when Skip Frame is Enabled. Value of the system clock counter at the end of calibration (when CalibrationDone is '1' in LPS_SF_Status register).
The hardware behind it is reused during other operation, reading that register at any other time will return an undefined value. 1 when the IRQ was triggered because the calibration is done.
Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the Slow Counter started.
Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the Power-Up frame was reached.
Write 1 in cause or status bit to clear. 1 when the IRQ was triggered because the tcu counter was restarted.
Write 1 in cause or status bit to clear. 1 when the calibration is done.
Write 1 in cause or status bit to clear. 1 when the Slow Counter started.
Write 1 in cause or status bit to clear. 1 when the Power-Up frame was reached.
Write 1 in cause or status bit to clear. 1 when the tcu counter was restarted.
Write 1 in cause or status bit to clear. when 1 the LPS_IRQ_Calibration_Done is enabled. when 1 the LPS_IRQ_Slow_Running is enabled. when 1 the LPS_IRQ_PU_Reached is enabled. when 1 the LPS_IRQ_TCU_Restart is enabled. Enable the module and activate the chip select selected by CS_sel field. Selects the active CS. When set to 1 the inputs are activated, else only the output is driven and no data are stored in the receive FIFO.
Notes: The Input_mode bit status is also readable onto the bit rxtx_buffer[31]. The spi clock polarity
when '0' the clock disabled level is low, and the first edge is a rising edge.
When '1' the clock disabled level is high, and the first edge is a falling edge. Transfer start to first edge delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first clock edge. Transfer start to first data out delay value from 0 to 2 is the number of spi clock half period between the CS activation and the first data out Transfer start to first data in sample delay value from 0 to 3 is the number of spi clock half period between the CS activation and the first data in sampled.
NOTE: DI_Delay must be less or equal to DO_Delay + CS_Delay + 2.
In other words DI_Delay can be 3 only if DO_Delay and CS_Delay are not both equal to 0. Transfer end to chip select deactivation delay value from 0 to 3 is the number of spi clock half period between the end of transfer and CS deactivation Chip select deactivation to reactivation minimum delay value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new CS activation (CS will activate only if more data are available in the transmit FIFO) Frame Size
The frame size is the binary value of this register + 1 valid value are 3 to 31 (frame size 4 to 32bits) OE delay
When 0: regular mode, SPI_DO pin as output only.
Value from 1 to 31 is the number of data out to transfert before the SPI_DO pin switch to input. Selects the active CS and Input_reg either from the ctrl or rxtx_buffer register.
If SPI FIFO 8b or 32b, when set to "0": CS from CS_sel and INPUT from Input_mode in the register ctrl.
Only if SPI FIFO 32b, when set to "1": CS and INPUT from SPI DATA.(Do not work for FIFO8b) Selects the input line to be used as SPI data in.(Not used for SPI3)
when "00" the SPI_DI_0 is used.
When "01" the SPI_DI_1 is used.
When "10" the SPI_DI_2 is used.
When "11" reserved. '1' when a transfer is in progress. The receive FIFO overflow irq cause.
Writing a '1' clear the receive overflow status and cause. The transmit FIFO threshold irq cause. The transmit Dma Done irq cause.
Writing a '1' clear the transmit Dma Done status and cause. The receive FIFO threshold irq cause. The receive Dma Done irq cause.
Writing a '1' clear the receive Dma Done status and cause. The transmit FIFO overflow status.
Writing a '1' clear the transmit overflow status and cause. The receive FIFO underflow status.
Writing a '1' clear the receive underflow status and cause. The receive FIFO overflow status.
Writing a '1' clear the receive overflow status and cause. The transmit FIFO threshold status. The transmit Dma Done status.
Writing a '1' clear the transmit Dma Done status and cause. The receive FIFO threshold status. The receive Dma Done status.
Writing a '1' clear the receive Dma Done status and cause. Transmit FIFO Space
Number of empty spot in the FIFO Receive FIFO level
Number of DATA in the FIFO Writing '1' flush both FIFO, don't do it when SPI is active (transfer in progress) Spi1 fifo size (rxtx_buffer): 8bits.
Spi2 fifo size (rxtx_buffer): 8bits.
Spi3 fifo size (rxtx_buffer): 32bits.
Write to the transmit FIFO Read in the receive FIFO. Chip Select on which write the data written in the Fifo. Data in bit [30:29] Data out bit [30:29] Set this bit to one when the data received while sending this peculiar data are expected to be kept in the FIFO, otherwise no data is recorded in the FIFO. Data in bit [31] Data out bit [31] Chip select polarity chip select is active high chip select is active low Clock Divider
The state machine clock is generated by dividing the system clock by the value of this register + 1.
So the output clock is divided by (register + 1)*2 When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. MMC Pattern value for RX pattern match mode. Enable the pattern mode. Spi Behaviour. Pattern matching. Select the RX pattern matching mode when the pattern_mode is enabled( set 1). Used for SD/MMC SPI mode. No datas are written into the RX FIFO UNTIL the received data is equal to the pattern. No datas are written into the RX FIFO WHILE the received data is equal to the pattern. When TX stream mode is enabled, once the TX fifo is empty, all new bits send have the value of this bit. Enable the TX stream mode. Used for SD/MMC SPI mode.
When enabled, this mode provide infinite bit stream for sending, after fifo is empty the extra bits generated all have the same value. The value is in tx_stream_bit. Allow to automatically clear the tx_stream_mode when Rx_Dma_Done is set. The Spi_Clk pin is set OUTPUT(Basic SPI Behaviour). The Spi_Clk pin is set INPUT (High Impedance). The Spi_Clk pin is set OUTPUT and forced to 0. The Spi_Clk pin is set OUTPUT and forced to 1. The Spi_DO pin is set OUTPUT(Basic SPI Behaviour). The Spi_DO pin is set INPUT (High Impedance). The Spi_DO pin is set OUTPUT and forced to 0. The Spi_DO pin is set OUTPUT and forced to 1. The Spi_CSO pin is set OUTPUT(Basic SPI Behaviour). The Spi_CSO pin is set INPUT (High Impedance). The Spi_CSO pin is set OUTPUT and forced to 0. The Spi_CSO pin is set OUTPUT and forced to 1. The Spi_CS1 pin is set OUTPUT(Basic SPI Behaviour). The Spi_CS1 pin is set INPUT (High Impedance). The Spi_CS1 pin is set OUTPUT and forced to 0. The Spi_CS1 pin is set OUTPUT and forced to 1. The Spi_CS2 pin is set OUTPUT(Basic SPI Behaviour). The Spi_CS2 pin is set INPUT (High Impedance). The Spi_CS2 pin is set OUTPUT and forced to 0. The Spi_CS2 pin is set OUTPUT and forced to 1. Mask the receive FIFO overflow irq Mask the transmit FIFO threshold irq Mask the transmit Dma Done irq Mask the receive FIFO threshold irq Mask the receive DMA Done irq Transmit FIFO threshold this threshold is used to generate the irq. Receive FIFO threshold this threshold is used to generate the irq. CPU IDs Sys Axi Clks IDs reserved base number auto clock enable number Sys Ahb Clks IDs reserved base number auto clock enable number Sys Apb Clks IDs auto clock enable number Aif Apb Clks IDs reserved base number auto clock enable number Aon Ahb Clks IDs reserved base number auto clock enable number Aon Apb Clks IDs auto clock enable number auto clock enable number auto clock enable number Other Clks IDs System Spiflash Domain Clock ID Base Psram Ctrl Domain Clock ID Base Other Clks 1 IDs Psram Clks IDs Sys Spiflash Clks IDs Sys Spiflash1 Clks IDs Sys Axi Rst IDs Sys Ahb Rst IDs Sys Apb Rst IDs Aif Apb Rst IDs Aon Ahb Rst IDs Aon Apb Rst IDs Rf Ahb Rst IDs Rf Apb Rst IDs APCPU Rst IDs CPCPU Rst IDs BBlte Rst IDs Other Rsts IDs For REG_DBG protect lock/unlock value This register is used to Lock and Unlock the protected registers.
[7:0] Write 0x89 to the register to release automatically for related clock gate enable in sysctrl datapath
[15:8] Write 0x89 to the register to release automatically for related soft reset in sysctrl datapath Is set to 1 when a write attempt has been done on a protected register
Can be reset by writing 0xa50000 or 0xa50001 to the debug register (With the LSB at 1 to unlock the protected registers, with the LSB at 0 to lock them) When this bit is set to 1, the protected registers are accessible
When this bit is set to 0, the protected registers can not be written
Write 0xa50000 to the debug register to set this bit to 0
Write 0xa50001 to the debug register to set this bit to 1 This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset This register is protected. Writing a 1 to any of the reset bit will reset the corresponding module and leave it in reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset Writing a 1 to any of the reset bit will take the corresponding module out of reset state
Reading this register returns the reset state of all the corresponding modules
0 : in reset
1 : out of reset automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) automatic clock gating enabled manual clock gating only Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will enable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) This register is protected. Each bit controls the manual enable for one clock
Writing a 1 to bit x of this register will disable the corresponding clocks
Writing a 0 to bit x has no effect on clock x
Reading this register gives the current status for all the clocks (1 : enabled, 0: disabled) Register protected by Write_Unlocked_H. Mode of the Pll. This register is set to enable by the LPS_start_ExtPll_pulse_H. Used to reset the PLL Lock Detector. In this mode the output of the PLL is its input clock divided by the proper dividers In this mode the output of the PLL is its input clock Enables the Fast Clock from the ExtPll (Clock Gate Reg Resync). This register is protected. PreSelects between RF clock(26mhz) and Oscillator clock(32k) for Clock Slow Selects between the Slow clock and the Fast Clock (APll clock) and Selects between the Slow clock and the APcpu Clock When 0, select 26m div32k.
When 1, select osc 32k. Disable PLL when LPS power up. When 1, the clock from the XCver is detected. When 0, the clock from the XCver is not detected. If RF_Detect_Bypass = 0, RF clock is selected when she is detected.
If RF_Detect_Bypass = 1, RF clock is selected even she is not detected. When 1, The RF clock detection counter is force reseted.
When 0, The RF clock detection counter is enabled. 0 when RF clock is effectively selected for Slow Clock. RF clock selection is not done until the clock has been detected. 0 when Fast clock is effectively selected. Fast clock selection is not done until the PLL has locked. When 1, clk_spiflash is clk_slow.
When 0, switch from clk_slow to clk_spiflash When 1, clk_mem_bridge is clk_slow.
When 0, switch from clk_slow to clk_pll_mem_bridge When 1, clk_bblte is inverted.
When 0, clk_bblte is itself, pole select When 1, clk_pix is clk_slow.
When 0, switch from clk_slow to clk_pll_pix_div_out When 1, usb clock pll locked.
When 0, usb clock pll not locked. When 1, select i_osc_26m.
When 0, select i_bb_26m(default). When 1, clk_spiflash is clk_slow.
When 0, switch from clk_slow to clk_spiflash
When 1, apll locked
When 0, apll not locked
When 1, mempll locked
When 0, mempll not locked
When 1, audiopll locked
When 0, audiopll not locked
When 1, bbpll2 locked
When 0, bbpll2 not locked
When 1, bbpll1 locked
When 0, bbpll1 not locked
When 1, usbpll locked
When 0, usbpll not locked This register is protected. The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL. The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL. The generated clock frequency is equal to the pll_host_div4 divided by this value + 2. The clock comes from a PLL. The generated clock frequency is equal to the selected source frequency divided by this value.
The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details).
[9:0] numerator 'b0000000001
[23:10] denominator 'b000000000000110 The Pwm reference clock frequency is the system clock divided by this register value + 1. The generated clock frequency is equal to the 156MHz divided by this value + 2. The 156MHz clock comes from a PLL. Clk camera out enable. Selects from which clock the Clk camera is generated. Clk spi camera out enable. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A watchdog reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. A reset was initiated from Global soft reset register The reset was not from the soft reset register. A reset was initiated from the Host interface The reset was not from the debug interface. A watchdog cp reset has happened No watchdog reset happened since the last HW reset or power on. Writing a 1 to this bit will reset the bits watchdog_Reset cause, GlobalSoft_Reset cause and HostDebug_Reset cause to 0. An Alarm occur from the calendar No Alarm occur. This contains the state of boot mode pins latched during Reset.
bit 16: Force download.
bit 17: Mass production.
bit 18: Secure boot 1-> secure boot, 0-> nonsecure boot.
bit 19: Unused.
bit 20: Unused.
bit 21: Unused.
see BootSequence for details.
This register is not reseted by a software or host reset. Software boot mode (Reseted at zero by external reset pin)
This register is not reseted by a software or host reset. When 1 the chip has booted in fonctional test mode (for chip production tests). This register is protected. When 1, the wake up is set. When 0, the wake up is clear . This register is protected. When 1, the CHG_MASK line to PMU is set. When 0, it is cleared. The generated clock frequency is equal to the selected source frequency divided by this value .
The generated clock must be 4 or 16 times the expected baud rate depending on the Uart settings (see Uart section for details).
[17:8] numerator 'b0000000001
[30:18] denominator 'b0000000000101 This register is ahb master protect cfg. This register is cq memory cfg. This register is a5_top_wrap/axidma/cp_a5_top/f8/gea3_wrap/lzma/sys_imem mem cfg. This register is audio mem cfg. This register is lcd/gouda mem cfg. This register is camera mem cfg. This register is peri(sdmmc/uart/usbc etc.) mem cfg. This register is aon sys mem cfg. This register is rf sys mem cfg. This register is coresight mem cfg. This register is vad mem cfg. This register is for audio i2s mux ,aif load_position etc. config.
000 = aif1 out mux to aif1
001 = aif2 out mux to aif1
010 = i2s1 out mux to aif1
011 = i2s2 out mux to aif1
100 = i2s3 out mux to aif1
101 = zero out mux to aif1
000 = aif1 out mux to aif2
001 = aif2 out mux to aif2
010 = i2s1 out mux to aif2
011 = i2s2 out mux to aif2
100 = i2s3 out mux to aif2
101 = zero out mux to aif2
000 = aif1 out mux to i2s1
001 = aif2 out mux to i2s1
010 = i2s1 out mux to i2s1
011 = i2s2 out mux to i2s1
100 = i2s3 out mux to i2s1
101 = zero out mux to i2s1
000 = aif1 out mux to i2s2
001 = aif2 out mux to i2s2
010 = i2s1 out mux to i2s2
011 = i2s2 out mux to i2s2
100 = i2s3 out mux to i2s2
101 = zero out mux to i2s2
000 = aif1 out mux to i2s3
001 = aif2 out mux to i2s3
010 = i2s1 out mux to i2s3
011 = i2s2 out mux to i2s3
100 = i2s3 out mux to i2s3
101 = zero out mux to i2s3
0 = i2s1 bck,lrck output enable
1 = i2s1 bck,lrck output disable
0 = i2s2 bck,lrck output enable
1 = i2s2 bck,lrck output disable
0 = i2s3 bck,lrck output enable
1 = i2s3 bck,lrck output disable This register is limit_en_spi,,clk_freq cfg.
0 = wcn uart and ap uart(with wcn communication) connect
1 = wcn uart output by iomux
0 = ap uart(with wcn communication) and wcn uart connect
1 = ap uart(with wcn communication) output by iomux This register is misc cfg.
0 = disable pwr_ctrl for ap reset
1 = enable pwr_ctrl for ap reset
0 = disable pwr_ctrl for gge reset
1 = enable pwr_ctrl for gge reset
0 = disable pwr_ctrl for btfm reset
1 = enable pwr_ctrl for btfm reset
0 = disable pwr_ctrl for ap clock
1 = enable pwr_ctrl for ap clock
0 = disable pwr_ctrl for gge clock
1 = enable pwr_ctrl for gge clock
0 = disable pwr_ctrl for btfm clock
1 = enable pwr_ctrl for btfm clock
0 = disable bbpll1 output
1 = enable bbpll1 output
0 = disable bbpll2 output
1 = enable bbpll2 output
0 = disable mempll output
1 = enable mempll output
0 = disable usbpll output
1 = enable usbpll output
0 = disable audiopll output
1 = enable audiopll output
0 = select clk_494m clock
1 = select from apll clock
0 = select i_apll_in clock
1 = select clk_494m clock gic400 axi aruser sel gic400 axi aruser dbg gic400 axi awuser sel gic400 axi awuser dbg
0 = select rfdig lvds
1 = select wcn lvds
0 = select rfdig from rf lvds
1 = select rfdig from bb lvds
0 = disable wcn_hclk and wcn_clk_26m wcn_osc_en control
1 = enable wcn_hclk and wcn_clk_26m wcn_osc_en control
0 = force clock on disable
1 = force clock on enable
0 = select vad clock(default)
1 = select vad inv clock
0 = select aud_sclk(default)
1 = select aud_sclk inv clock
0 = disable pwr_ctrl for aon_lp reset
1 = enable pwr_ctrl for aon_lp reset
0 = disable pwr_ctrl for aon_lp clock
1 = enable pwr_ctrl for aon_lp clock
0 = disable aon rf async bridge dump data to fifo
1 = enable aon rf async bridge dump data to fifo for bus access efficiency This register set lp related config. This register is reserved. For WCN Ahb Bus peri prot. For WCN Ahb Bus mem prot. aes ahb bus prot. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is reserved. This register is for CHIP_ID(METAL_ID[11:0],BOND_ID[15:12]),PROD[31:16]
[11:0] metal ID
[15:12] bond ID, bit15: spi_flash_sel 0->1.8v pad sequence 1->3.3v pad sequence; bit14: boot
[31:16] production ID This register is for BUS QOS config.
[3:0] for wcn_mem_arqos
[4] for wcn_mem_arqos sync
[8:5] for wcn_mem_awqos
[9] for wcn_mem_awqos sync
[13:10] for gge_arqos
[14] for gge_arqos sync
[18:15] for gge_awqos
[19] for gge_awqos sync
[23:20] for a5_arqos
[24] for a5_arqos sync
[28:25] for a5_awqos
[29] for a5_awqos sync This register is for BUS QOS config.
[3:0] for axidma_arqos
[4] for axidma_arqos sync
[8:5] for axidma_awqos
[9] for axidma_awqos sync
[13:10] for cp_a5_arqos
[14] for cp_a5_arqos sync
[18:15] for cp_a5_awqos
[19] for cp_a5_awqos sync
[23:20] for f8_arqos
[24] for f8_arqos sync
[28:25] for f8_awqos
[29] for f8_awqos sync This register is for BUS QOS config.
[3:0] for lcdc_arqos
[4] for lcdc_arqos sync
[8:5] for lcdc_awqos
[9] for lcdc_awqos sync
[13:10] for lzma_arqos
[14] for lzma_arqos sync
[18:15] for lzma_awqos
[19] for lzma_awqos sync
[23:20] for gouda_arqos
[24] for gouda_arqos sync
[28:25] for gouda_awqos
[29] for gouda_awqos sync This register is for BUS QOS config.
[3:0] for lte_arqos
[4] for lte_arqos sync
[8:5] for lte_awqos
[9] for lte_awqos sync
[13:10] for usb_arqos
[14] for usb_arqos sync
[18:15] for usb_awqos
[19] for usb_awqos sync This register is for merge mem awqos/arqos QOS config.
[3:0] for merge_mem_awqos
[4] for merge_mem_awqos sync
[8:5] for merge_mem_arqos
[9] for merge_mem_arqos sync This register is for bcpu break point debug.
[27:0] for bcpu break point address.
[29:28] for bcpu break point mode.
[30] for bcpu break point enable.
[31] for bcpu stalled write 1 clear. spi_flash_clk force enable for outoen. spi_flash_clk force output value for output. spi_flash_clk pin output value. spi_flash_clk force outoen value. spi_flash_clk force enable for pu/pd spi_flash_clk PUll up spi_flash_clk PUll down spi_flash_clk select spi_flash_cs force enable for outoen. spi_flash_cs force output value for output. spi_flash_cs pin output value. spi_flash_cs force outoen value. spi_flash_cs force enable for pu/pd spi_flash_cs PUll up spi_flash_cs PUll down spi_flash_cs select spi_flash_sel force enable for outoen. spi_flash_sel force output value for output. spi_flash_sel pin output value. spi_flash_sel force outoen value. spi_flash_sel force enable for pu/pd spi_flash_sel PUll up spi_flash_sel PUll down spi_flash_sel select spi_flash_sio_0 force enable for outoen. spi_flash_sio_0 force output value for output. spi_flash_sio_0 pin output value. spi_flash_sio_0 force outoen value. spi_flash_sio_0 force enable for pu/pd spi_flash_sio_0 PUll up spi_flash_sio_0 PUll down spi_flash_sio_0 select spi_flash_sio_1 force enable for outoen. spi_flash_sio_1 force output value for output. spi_flash_sio_1 pin output value. spi_flash_sio_1 force outoen value. spi_flash_sio_1 force enable for pu/pd spi_flash_sio_1 PUll up spi_flash_sio_1 PUll down spi_flash_sio_1 select spi_flash_sio_2 force enable for outoen. spi_flash_sio_2 force output value for output. spi_flash_sio_2 pin output value. spi_flash_sio_2 force outoen value. spi_flash_sio_2 force enable for pu/pd spi_flash_sio_2 PUll up spi_flash_sio_2 PUll down spi_flash_sio_2 select spi_flash_sio_3 force enable for outoen. spi_flash_sio_3 force output value for output. spi_flash_sio_3 pin output value. spi_flash_sio_3 force outoen value. spi_flash_sio_3 force enable for pu/pd spi_flash_sio_3 PUll up spi_flash_sio_3 PUll down spi_flash_sio_3 select sdmmc1_clk force enable for outoen. sdmmc1_clk force output value for output. sdmmc1_clk pin output value. sdmmc1_clk force outoen value. sdmmc1_clk force enable for pu/pd sdmmc1_clk PUll up sdmmc1_clk PUll down sdmmc1_clk select sdmmc1_cmd force enable for outoen. sdmmc1_cmd force output value for output. sdmmc1_cmd pin output value. sdmmc1_cmd force outoen value. sdmmc1_cmd force enable for pu/pd sdmmc1_cmd PUll up sdmmc1_cmd PUll down sdmmc1_cmd select sdmmc1_data_0 force enable for outoen. sdmmc1_data_0 force output value for output. sdmmc1_data_0 pin output value. sdmmc1_data_0 force outoen value. sdmmc1_data_0 force enable for pu/pd sdmmc1_data_0 PUll up sdmmc1_data_0 PUll down sdmmc1_data_0 select sdmmc1_data_1 force enable for outoen. sdmmc1_data_1 force output value for output. sdmmc1_data_1 pin output value. sdmmc1_data_1 force outoen value. sdmmc1_data_1 force enable for pu/pd sdmmc1_data_1 PUll up sdmmc1_data_1 PUll down sdmmc1_data_1 select sdmmc1_data_2 force enable for outoen. sdmmc1_data_2 force output value for output. sdmmc1_data_2 pin output value. sdmmc1_data_2 force outoen value. sdmmc1_data_2 force enable for pu/pd sdmmc1_data_2 PUll up sdmmc1_data_2 PUll down sdmmc1_data_2 select sdmmc1_data_3 force enable for outoen. sdmmc1_data_3 force output value for output. sdmmc1_data_3 pin output value. sdmmc1_data_3 force outoen value. sdmmc1_data_3 force enable for pu/pd sdmmc1_data_3 PUll up sdmmc1_data_3 PUll down sdmmc1_data_3 select aud_da_sync force enable for outoen. aud_da_sync force output value for output. aud_da_sync pin output value. aud_da_sync force outoen value. aud_da_sync force enable for pu/pd aud_da_sync PUll up aud_da_sync PUll down aud_da_sync select aud_da_d1 force enable for outoen. aud_da_d1 force output value for output. aud_da_d1 pin output value. aud_da_d1 force outoen value. aud_da_d1 force enable for pu/pd aud_da_d1 PUll up aud_da_d1 PUll down aud_da_d1 select aud_da_d0 force enable for outoen. aud_da_d0 force output value for output. aud_da_d0 pin output value. aud_da_d0 force outoen value. aud_da_d0 force enable for pu/pd aud_da_d0 PUll up aud_da_d0 PUll down aud_da_d0 select aud_ad_sync force enable for outoen. aud_ad_sync force output value for output. aud_ad_sync pin output value. aud_ad_sync force outoen value. aud_ad_sync force enable for pu/pd aud_ad_sync PUll up aud_ad_sync PUll down aud_ad_sync select aud_ad_d0 force enable for outoen. aud_ad_d0 force output value for output. aud_ad_d0 pin output value. aud_ad_d0 force outoen value. aud_ad_d0 force enable for pu/pd aud_ad_d0 PUll up aud_ad_d0 PUll down aud_ad_d0 select aud_sclk force enable for outoen. aud_sclk force output value for output. aud_sclk pin output value. aud_sclk force outoen value. aud_sclk force enable for pu/pd aud_sclk PUll up aud_sclk PUll down aud_sclk select adi_sda force enable for outoen. adi_sda force output value for output. adi_sda pin output value. adi_sda force outoen value. adi_sda force enable for pu/pd adi_sda PUll up adi_sda PUll down adi_sda select adi_sync force enable for outoen. adi_sync force output value for output. adi_sync pin output value. adi_sync force outoen value. adi_sync force enable for pu/pd adi_sync PUll up adi_sync PUll down adi_sync select adi_scl force enable for outoen. adi_scl force output value for output. adi_scl pin output value. adi_scl force outoen value. adi_scl force enable for pu/pd adi_scl PUll up adi_scl PUll down adi_scl select spi_lcd_sio force enable for outoen. spi_lcd_sio force output value for output. spi_lcd_sio pin output value. spi_lcd_sio force outoen value. spi_lcd_sio force enable for pu/pd spi_lcd_sio PUll up spi_lcd_sio PUll down spi_lcd_sio select spi_lcd_sdc force enable for outoen. spi_lcd_sdc force output value for output. spi_lcd_sdc pin output value. spi_lcd_sdc force outoen value. spi_lcd_sdc force enable for pu/pd spi_lcd_sdc PUll up spi_lcd_sdc PUll down spi_lcd_sdc select spi_lcd_clk force enable for outoen. spi_lcd_clk force output value for output. spi_lcd_clk pin output value. spi_lcd_clk force outoen value. spi_lcd_clk force enable for pu/pd spi_lcd_clk PUll up spi_lcd_clk PUll down spi_lcd_clk select spi_lcd_cs force enable for outoen. spi_lcd_cs force output value for output. spi_lcd_cs pin output value. spi_lcd_cs force outoen value. spi_lcd_cs force enable for pu/pd spi_lcd_cs PUll up spi_lcd_cs PUll down spi_lcd_cs select spi_lcd_select force enable for outoen. spi_lcd_select force output value for output. spi_lcd_select pin output value. spi_lcd_select force outoen value. spi_lcd_select force enable for pu/pd spi_lcd_select PUll up spi_lcd_select PUll down spi_lcd_select select lcd_fmark force enable for outoen. lcd_fmark force output value for output. lcd_fmark pin output value. lcd_fmark force outoen value. lcd_fmark force enable for pu/pd lcd_fmark PUll up lcd_fmark PUll down lcd_fmark select lcd_rstb force enable for outoen. lcd_rstb force output value for output. lcd_rstb pin output value. lcd_rstb force outoen value. lcd_rstb force enable for pu/pd lcd_rstb PUll up lcd_rstb PUll down lcd_rstb select i2c_m1_scl force enable for outoen. i2c_m1_scl force output value for output. i2c_m1_scl pin output value. i2c_m1_scl force outoen value. i2c_m1_scl force enable for pu/pd i2c_m1_scl PUll up i2c_m1_scl PUll down i2c_m1_scl select i2c_m1_sda force enable for outoen. i2c_m1_sda force output value for output. i2c_m1_sda pin output value. i2c_m1_sda force outoen value. i2c_m1_sda force enable for pu/pd i2c_m1_sda PUll up i2c_m1_sda PUll down i2c_m1_sda select camera_rst_l force enable for outoen. camera_rst_l force output value for output. camera_rst_l pin output value. camera_rst_l force outoen value. camera_rst_l force enable for pu/pd camera_rst_l PUll up camera_rst_l PUll down camera_rst_l select camera_pwdn force enable for outoen. camera_pwdn force output value for output. camera_pwdn pin output value. camera_pwdn force outoen value. camera_pwdn force enable for pu/pd camera_pwdn PUll up camera_pwdn PUll down camera_pwdn select camera_ref_clk force enable for outoen. camera_ref_clk force output value for output. camera_ref_clk pin output value. camera_ref_clk force outoen value. camera_ref_clk force enable for pu/pd camera_ref_clk PUll up camera_ref_clk PUll down camera_ref_clk select spi_camera_si_0 force enable for outoen. spi_camera_si_0 force output value for output. spi_camera_si_0 pin output value. spi_camera_si_0 force outoen value. spi_camera_si_0 force enable for pu/pd spi_camera_si_0 PUll up spi_camera_si_0 PUll down spi_camera_si_0 select spi_camera_si_1 force enable for outoen. spi_camera_si_1 force output value for output. spi_camera_si_1 pin output value. spi_camera_si_1 force outoen value. spi_camera_si_1 force enable for pu/pd spi_camera_si_1 PUll up spi_camera_si_1 PUll down spi_camera_si_1 select spi_camera_sck force enable for outoen. spi_camera_sck force output value for output. spi_camera_sck pin output value. spi_camera_sck force outoen value. spi_camera_sck force enable for pu/pd spi_camera_sck PUll up spi_camera_sck PUll down spi_camera_sck select gpio_13 force enable for outoen. gpio_13 force output value for output. gpio_13 pin output value. gpio_13 force outoen value. gpio_13 force enable for pu/pd gpio_13 PUll up gpio_13 PUll down gpio_13 select gpio_0 force enable for outoen. gpio_0 force output value for output. gpio_0 pin output value. gpio_0 force outoen value. gpio_0 force enable for pu/pd gpio_0 PUll up gpio_0 PUll down gpio_0 select gpio_1 force enable for outoen. gpio_1 force output value for output. gpio_1 pin output value. gpio_1 force outoen value. gpio_1 force enable for pu/pd gpio_1 PUll up gpio_1 PUll down gpio_1 select gpio_2 force enable for outoen. gpio_2 force output value for output. gpio_2 pin output value. gpio_2 force outoen value. gpio_2 force enable for pu/pd gpio_2 PUll up gpio_2 PUll down gpio_2 select gpio_3 force enable for outoen. gpio_3 force output value for output. gpio_3 pin output value. gpio_3 force outoen value. gpio_3 force enable for pu/pd gpio_3 PUll up gpio_3 PUll down gpio_3 select gpio_4 force enable for outoen. gpio_4 force output value for output. gpio_4 pin output value. gpio_4 force outoen value. gpio_4 force enable for pu/pd gpio_4 PUll up gpio_4 PUll down gpio_4 select gpio_5 force enable for outoen. gpio_5 force output value for output. gpio_5 pin output value. gpio_5 force outoen value. gpio_5 force enable for pu/pd gpio_5 PUll up gpio_5 PUll down gpio_5 select gpio_7 force enable for outoen. gpio_7 force output value for output. gpio_7 pin output value. gpio_7 force outoen value. gpio_7 force enable for pu/pd gpio_7 PUll up gpio_7 PUll down gpio_7 select ap_jtag_tck force enable for outoen. ap_jtag_tck force output value for output. ap_jtag_tck pin output value. ap_jtag_tck force outoen value. ap_jtag_tck force enable for pu/pd ap_jtag_tck PUll up ap_jtag_tck PUll down ap_jtag_tck select ap_jtag_trst force enable for outoen. ap_jtag_trst force output value for output. ap_jtag_trst pin output value. ap_jtag_trst force outoen value. ap_jtag_trst force enable for pu/pd ap_jtag_trst PUll up ap_jtag_trst PUll down ap_jtag_trst select ap_jtag_tms force enable for outoen. ap_jtag_tms force output value for output. ap_jtag_tms pin output value. ap_jtag_tms force outoen value. ap_jtag_tms force enable for pu/pd ap_jtag_tms PUll up ap_jtag_tms PUll down ap_jtag_tms select ap_jtag_tdi force enable for outoen. ap_jtag_tdi force output value for output. ap_jtag_tdi pin output value. ap_jtag_tdi force outoen value. ap_jtag_tdi force enable for pu/pd ap_jtag_tdi PUll up ap_jtag_tdi PUll down ap_jtag_tdi select ap_jtag_tdo force enable for outoen. ap_jtag_tdo force output value for output. ap_jtag_tdo pin output value. ap_jtag_tdo force outoen value. ap_jtag_tdo force enable for pu/pd ap_jtag_tdo PUll up ap_jtag_tdo PUll down ap_jtag_tdo select gpio_14 force enable for outoen. gpio_14 force output value for output. gpio_14 pin output value. gpio_14 force outoen value. gpio_14 force enable for pu/pd gpio_14 PUll up gpio_14 PUll down gpio_14 select gpio_15 force enable for outoen. gpio_15 force output value for output. gpio_15 pin output value. gpio_15 force outoen value. gpio_15 force enable for pu/pd gpio_15 PUll up gpio_15 PUll down gpio_15 select gpio_18 force enable for outoen. gpio_18 force output value for output. gpio_18 pin output value. gpio_18 force outoen value. gpio_18 force enable for pu/pd gpio_18 PUll up gpio_18 PUll down gpio_18 select gpio_19 force enable for outoen. gpio_19 force output value for output. gpio_19 pin output value. gpio_19 force outoen value. gpio_19 force enable for pu/pd gpio_19 PUll up gpio_19 PUll down gpio_19 select gpio_20 force enable for outoen. gpio_20 force output value for output. gpio_20 pin output value. gpio_20 force outoen value. gpio_20 force enable for pu/pd gpio_20 PUll up gpio_20 PUll down gpio_20 select gpio_21 force enable for outoen. gpio_21 force output value for output. gpio_21 pin output value. gpio_21 force outoen value. gpio_21 force enable for pu/pd gpio_21 PUll up gpio_21 PUll down gpio_21 select gpio_22 force enable for outoen. gpio_22 force output value for output. gpio_22 pin output value. gpio_22 force outoen value. gpio_22 force enable for pu/pd gpio_22 PUll up gpio_22 PUll down gpio_22 select gpio_23 force enable for outoen. gpio_23 force output value for output. gpio_23 pin output value. gpio_23 force outoen value. gpio_23 force enable for pu/pd gpio_23 PUll up gpio_23 PUll down gpio_23 select gpio_8 force enable for outoen. gpio_8 force output value for output. gpio_8 pin output value. gpio_8 force outoen value. gpio_8 force enable for pu/pd gpio_8 PUll up gpio_8 PUll down gpio_8 select gpio_9 force enable for outoen. gpio_9 force output value for output. gpio_9 pin output value. gpio_9 force outoen value. gpio_9 force enable for pu/pd gpio_9 PUll up gpio_9 PUll down gpio_9 select gpio_10 force enable for outoen. gpio_10 force output value for output. gpio_10 pin output value. gpio_10 force outoen value. gpio_10 force enable for pu/pd gpio_10 PUll up gpio_10 PUll down gpio_10 select gpio_11 force enable for outoen. gpio_11 force output value for output. gpio_11 pin output value. gpio_11 force outoen value. gpio_11 force enable for pu/pd gpio_11 PUll up gpio_11 PUll down gpio_11 select gpio_12 force enable for outoen. gpio_12 force output value for output. gpio_12 pin output value. gpio_12 force outoen value. gpio_12 force enable for pu/pd gpio_12 PUll up gpio_12 PUll down gpio_12 select keyin_0 force enable for outoen. keyin_0 force output value for output. keyin_0 pin output value. keyin_0 force outoen value. keyin_0 force enable for pu/pd keyin_0 PUll up keyin_0 PUll down keyin_0 select keyin_1 force enable for outoen. keyin_1 force output value for output. keyin_1 pin output value. keyin_1 force outoen value. keyin_1 force enable for pu/pd keyin_1 PUll up keyin_1 PUll down keyin_1 select keyin_2 force enable for outoen. keyin_2 force output value for output. keyin_2 pin output value. keyin_2 force outoen value. keyin_2 force enable for pu/pd keyin_2 PUll up keyin_2 PUll down keyin_2 select keyin_3 force enable for outoen. keyin_3 force output value for output. keyin_3 pin output value. keyin_3 force outoen value. keyin_3 force enable for pu/pd keyin_3 PUll up keyin_3 PUll down keyin_3 select keyin_4 force enable for outoen. keyin_4 force output value for output. keyin_4 pin output value. keyin_4 force outoen value. keyin_4 force enable for pu/pd keyin_4 PUll up keyin_4 PUll down keyin_4 select keyin_5 force enable for outoen. keyin_5 force output value for output. keyin_5 pin output value. keyin_5 force outoen value. keyin_5 force enable for pu/pd keyin_5 PUll up keyin_5 PUll down keyin_5 select keyout_0 force enable for outoen. keyout_0 force output value for output. keyout_0 pin output value. keyout_0 force outoen value. keyout_0 force enable for pu/pd keyout_0 PUll up keyout_0 PUll down keyout_0 select keyout_1 force enable for outoen. keyout_1 force output value for output. keyout_1 pin output value. keyout_1 force outoen value. keyout_1 force enable for pu/pd keyout_1 PUll up keyout_1 PUll down keyout_1 select keyout_2 force enable for outoen. keyout_2 force output value for output. keyout_2 pin output value. keyout_2 force outoen value. keyout_2 force enable for pu/pd keyout_2 PUll up keyout_2 PUll down keyout_2 select keyout_3 force enable for outoen. keyout_3 force output value for output. keyout_3 pin output value. keyout_3 force outoen value. keyout_3 force enable for pu/pd keyout_3 PUll up keyout_3 PUll down keyout_3 select keyout_4 force enable for outoen. keyout_4 force output value for output. keyout_4 pin output value. keyout_4 force outoen value. keyout_4 force enable for pu/pd keyout_4 PUll up keyout_4 PUll down keyout_4 select keyout_5 force enable for outoen. keyout_5 force output value for output. keyout_5 pin output value. keyout_5 force outoen value. keyout_5 force enable for pu/pd keyout_5 PUll up keyout_5 PUll down keyout_5 select debug_host_rx force enable for outoen. debug_host_rx force output value for output. debug_host_rx pin output value. debug_host_rx force outoen value. debug_host_rx force enable for pu/pd debug_host_rx PUll up debug_host_rx PUll down debug_host_rx select debug_host_tx force enable for outoen. debug_host_tx force output value for output. debug_host_tx pin output value. debug_host_tx force outoen value. debug_host_tx force enable for pu/pd debug_host_tx PUll up debug_host_tx PUll down debug_host_tx select debug_host_clk force enable for outoen. debug_host_clk force output value for output. debug_host_clk pin output value. debug_host_clk force outoen value. debug_host_clk force enable for pu/pd debug_host_clk PUll up debug_host_clk PUll down debug_host_clk select sim_1_clk force enable for outoen. sim_1_clk force output value for output. sim_1_clk pin output value. sim_1_clk force outoen value. sim_1_clk force enable for pu/pd sim_1_clk PUll up sim_1_clk PUll down sim_1_clk select sim_1_dio force enable for outoen. sim_1_dio force output value for output. sim_1_dio pin output value. sim_1_dio force outoen value. sim_1_dio force enable for pu/pd sim_1_dio PUll up sim_1_dio PUll down sim_1_dio select sim_1_rst force enable for outoen. sim_1_rst force output value for output. sim_1_rst pin output value. sim_1_rst force outoen value. sim_1_rst force enable for pu/pd sim_1_rst PUll up sim_1_rst PUll down sim_1_rst select sim_2_clk force enable for outoen. sim_2_clk force output value for output. sim_2_clk pin output value. sim_2_clk force outoen value. sim_2_clk force enable for pu/pd sim_2_clk PUll up sim_2_clk PUll down sim_2_clk select sim_2_dio force enable for outoen. sim_2_dio force output value for output. sim_2_dio pin output value. sim_2_dio force outoen value. sim_2_dio force enable for pu/pd sim_2_dio PUll up sim_2_dio PUll down sim_2_dio select sim_2_rst force enable for outoen. sim_2_rst force output value for output. sim_2_rst pin output value. sim_2_rst force outoen value. sim_2_rst force enable for pu/pd sim_2_rst PUll up sim_2_rst PUll down sim_2_rst select rfdig_gpio_0 force enable for outoen. rfdig_gpio_0 force output value for output. rfdig_gpio_0 pin output value. rfdig_gpio_0 force outoen value. rfdig_gpio_0 force enable for pu/pd rfdig_gpio_0 PUll up rfdig_gpio_0 PUll down rfdig_gpio_0 select rfdig_gpio_1 force enable for outoen. rfdig_gpio_1 force output value for output. rfdig_gpio_1 pin output value. rfdig_gpio_1 force outoen value. rfdig_gpio_1 force enable for pu/pd rfdig_gpio_1 PUll up rfdig_gpio_1 PUll down rfdig_gpio_1 select rfdig_gpio_2 force enable for outoen. rfdig_gpio_2 force output value for output. rfdig_gpio_2 pin output value. rfdig_gpio_2 force outoen value. rfdig_gpio_2 force enable for pu/pd rfdig_gpio_2 PUll up rfdig_gpio_2 PUll down rfdig_gpio_2 select rfdig_gpio_3 force enable for outoen. rfdig_gpio_3 force output value for output. rfdig_gpio_3 pin output value. rfdig_gpio_3 force outoen value. rfdig_gpio_3 force enable for pu/pd rfdig_gpio_3 PUll up rfdig_gpio_3 PUll down rfdig_gpio_3 select rfdig_gpio_4 force enable for outoen. rfdig_gpio_4 force output value for output. rfdig_gpio_4 pin output value. rfdig_gpio_4 force outoen value. rfdig_gpio_4 force enable for pu/pd rfdig_gpio_4 PUll up rfdig_gpio_4 PUll down rfdig_gpio_4 select rfdig_gpio_5 force enable for outoen. rfdig_gpio_5 force output value for output. rfdig_gpio_5 pin output value. rfdig_gpio_5 force outoen value. rfdig_gpio_5 force enable for pu/pd rfdig_gpio_5 PUll up rfdig_gpio_5 PUll down rfdig_gpio_5 select rfdig_gpio_6 force enable for outoen. rfdig_gpio_6 force output value for output. rfdig_gpio_6 pin output value. rfdig_gpio_6 force outoen value. rfdig_gpio_6 force enable for pu/pd rfdig_gpio_6 PUll up rfdig_gpio_6 PUll down rfdig_gpio_6 select rfdig_gpio_7 force enable for outoen. rfdig_gpio_7 force output value for output. rfdig_gpio_7 pin output value. rfdig_gpio_7 force outoen value. rfdig_gpio_7 force enable for pu/pd rfdig_gpio_7 PUll up rfdig_gpio_7 PUll down rfdig_gpio_7 select secure_boot_mode force enable for outoen. secure_boot_mode force output value for output. secure_boot_mode pin output value. secure_boot_mode force outoen value. secure_boot_mode force enable for pu/pd secure_boot_mode PUll up secure_boot_mode PUll down secure_boot_mode select nand_flash_sel force enable for outoen. nand_flash_sel force output value for output. nand_flash_sel pin output value. nand_flash_sel force outoen value. nand_flash_sel force enable for pu/pd nand_flash_sel PUll up nand_flash_sel PUll down nand_flash_sel select configure whether to check the write id and read id is the same when release the token Record Select Control 0: Record ID 1: Record User bits the configuration of this register, can be ignored in APB bus matrix total status register, 32 lock status, indicate if each lock is taken Read LOCK[i]=0x0, lock i is in the Not Taken status Read LOCK[i]=1, lock i is in the taken status spinlock software flag register0 this register is used to record message by software spinlock software flag register1 this register is used to record message by software spinlock software flag register2 this register is used to record message by software spinlock software flag register3 this register is used to record message by software the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 the master id is stored in this register. The value of this reg in APB bus is 0x0 read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect read 0x0, request and get the lock read 0x1, reqeust but does not get the lock write unlock token (0x55aa10c5), to unlock the lock write any other, no effect hw version id All 0 check start index All 0 check end index write 1 to this bit will trigger all0 check to efuse, this bit is self-clear ,read this bit will always get 0.(use PREADY) Efuse type: 00 TSMC IP version, now is r1p0 Clk_efs divider, if this value is n, the frequency of controller will be divided by (n+1) from clk_efs. In most case, this field not need to change. This counter is used to control STROBE signal low level width in PGM mode, for TSMC efuse memory, no extra requirement for this signal, For 26Mhz efuse controller clock, by default, this width will be: 38.4*28=1075ns > 1us. If you want to speed up program speed, can configure the register to a smaller value. Program strobe high time. If set n, the Tpgm time will last for (n+1) clk_efuse cycle, only when PGM_EN=1 can write this field. If set the bit, lock bits will be written after PGM process. efuse margin read mode enable efuse double bit enable program read back auto-check enable efuse vdd enable the bit indicates all 0 check fail. the bit enk1 and enk2 is not switch correctly. the bit indicates write process without setting magic number. the bit indicates arbiter read block0 which may indicates unexpected access. the bit indicates read process without setting vdd_on to 1. the bit indicates write process without setting pg_en to 1. The bit indicates shadow block is protected and can not be programmed if double_bit_en is set. If SW send a PGM command to memory block[i], and the controller found this memory block is protected(which means the highest bit is 1), this bit will set to 1. The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. The bit indicates shadow block auto check failed after programming if double_bit_en is set. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. The bit indicates block auto check failed after programming. If PGM_AUTO_CHK_EN is set, and controller compared the value read after PGM from the same block, and found the two value not match, this bit will set as an error flag. But if this block is protected, the PGM command in-fact not really send, so this bit will not set. write 1 will clear SEC_ALL0_CHECK_FLAG write 1 will clear SEC_ENK_ERR_FLAG write 1 will clear SEC_MAGNUM_WR_FLAG write 1 will clear SEC_BLOCK0_RD_FLAG write 1 will clear SEC_VDD_ON_RD_FLAG write 1 will clear SEC_PG_EN_WR_FLAG write 1 will clear SEC_WORD1_PROT_FLAG. Write 0 will do nothing. write 1 will clear SEC_WORD0_PROT_FLAG. Write 0 will do nothing. write 1 will clear SEC_WORD1_ERR_FLAG. Write 0 will do nothing. write 1 will clear SEC_WORD0_ERR_FLAG. Write 0 will do nothing. Magic number, only when this field is 0x8910, the efuse programming command can be handle. Set the magic number right will lock the power switch and PGM enable. So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : (1) SEC_EFUSE_MAGIC_NUMBER =0x8910 (2) PG_EN=1; (3) Switch the power right; 0: SEC access; 1: NON SEC address enable switch SEC/NON-SEC address configure. 1: indicates SEC can access EFUSE_CFG0; 0: indicates NON-SEC can access EFUSE_CFG0; set this bit will open static power supply for efuse memory, before any operation towards to efuse memory this bit have to set to 1. once this bit is cleared, the efuse will go to power down mose. VDDQ power switch K2, to safely control this power switch. VDDQ power switch K2, to safely control this power switch. AP cortex-a5 dbgen, write once register,Invasive debug enable: 0 = not enabled 1 = enabled. AP cortex-a5 niden, write once register,Noninvasive debug enable: 0 = not enabled 1 = enabled. AP cortex-a5 spien, write once register,Secure privileged invasive debug enable: 0 = not enabled 1 = enabled. AP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable: 0 = not enabled 1 = enabled. AP cortex-a5 dap deviceen, write once register,device enable RISCV JTAG disable, write once register ZSP JTAG disable, write once register debug host rx disable, write once register uart1 rx disable, write once register uart2 rx disable, write once register uart3 rx disable, write once register uart cp rx disable, write once register mbist disable, write once register scan disable, write once register efuse bist enable, write once register CP cortex-a5 dbgen, write once register,Invasive debug enable: 0 = not enabled 1 = enabled. CP cortex-a5 niden, write once register,Noninvasive debug enable: 0 = not enabled 1 = enabled. CP cortex-a5 spien, write once register,Secure privileged invasive debug enable: 0 = not enabled 1 = enabled. CP cortex-a5 spnien, write once register,Secure privileged noninvasive debug enable: 0 = not enabled 1 = enabled. CP cortex-a5 dcp deviceen, write once register,device enable control efuse block0 read/write, write once register: 0 = not enable read/write efuse block0 1 = enable read/write efuse block0 control efuse block1 read/write, write once register: 0 = not enable read/write efuse block1 1 = enable read/write efuse block1 control efuse block2 read/write, write once register: 0 = not enable read/write efuse block2 1 = enable read/write efuse block2 control efuse block3 read/write, write once register: 0 = not enable read/write efuse block3 1 = enable read/write efuse block3 control efuse block4 read/write, write once register: 0 = not enable read/write efuse block4 1 = enable read/write efuse block4 control efuse block5 read/write, write once register: 0 = not enable read/write efuse block5 1 = enable read/write efuse block5 control efuse block6 read/write, write once register: 0 = not enable read/write efuse block6 1 = enable read/write efuse block6 control efuse block7 read/write, write once register: 0 = not enable read/write efuse block7 1 = enable read/write efuse block7 control efuse block8 read/write, write once register: 0 = not enable read/write efuse block8 1 = enable read/write efuse block8 control efuse block9 read/write, write once register: 0 = not enable read/write efuse block9 1 = enable read/write efuse block9 control efuse block10 read/write, write once register: 0 = not enable read/write efuse block10 1 = enable read/write efuse block10 control efuse block11 read/write, write once register: 0 = not enable read/write efuse block11 1 = enable read/write efuse block11 control efuse block12 read/write, write once register: 0 = not enable read/write efuse block12 1 = enable read/write efuse block12 control efuse block13 read/write, write once register: 0 = not enable read/write efuse block13 1 = enable read/write efuse block13 control efuse block14 read/write, write once register: 0 = not enable read/write efuse block14 1 = enable read/write efuse block14 control efuse block15 read/write, write once register: 0 = not enable read/write efuse block15 1 = enable read/write efuse block15 control efuse block16 read/write, write once register: 0 = not enable read/write efuse block16 1 = enable read/write efuse block16 control efuse block17 read/write, write once register: 0 = not enable read/write efuse block17 1 = enable read/write efuse block17 control efuse block18 read/write, write once register: 0 = not enable read/write efuse block18 1 = enable read/write efuse block18 control efuse block19 read/write, write once register: 0 = not enable read/write efuse block19 1 = enable read/write efuse block19 control efuse block20 read/write, write once register: 0 = not enable read/write efuse block20 1 = enable read/write efuse block20 control efuse block21 read/write, write once register: 0 = not enable read/write efuse block21 1 = enable read/write efuse block21 control efuse block22 read/write, write once register: 0 = not enable read/write efuse block22 1 = enable read/write efuse block22 control efuse block23 read/write, write once register: 0 = not enable read/write efuse block23 1 = enable read/write efuse block23 control efuse block24 read/write, write once register: 0 = not enable read/write efuse block24 1 = enable read/write efuse block24 control efuse block25 read/write, write once register: 0 = not enable read/write efuse block25 1 = enable read/write efuse block25 control efuse block26 read/write, write once register: 0 = not enable read/write efuse block26 1 = enable read/write efuse block26 control efuse block27 read/write, write once register: 0 = not enable read/write efuse block27 1 = enable read/write efuse block27 control efuse block28 read/write, write once register: 0 = not enable read/write efuse block28 1 = enable read/write efuse block28 control efuse block29 read/write, write once register: 0 = not enable read/write efuse block29 1 = enable read/write efuse block29 control efuse block30 read/write, write once register: 0 = not enable read/write efuse block30 1 = enable read/write efuse block30 control efuse block31 read/write, write once register: 0 = not enable read/write efuse block31 1 = enable read/write efuse block31 read config bits done status from efuse macro after por, then this bit is set to 1. ap_ca5_dbgen status ap_ca5_niden status ap_ca5_spiden status ap_ca5_spniden status ap_ca5_dap_deviceen status riscv_jtag_disable status zsp_jtag_disable status debug_host_rx_disable status uart_1_rx_disable status uart_2_rx_disable status uart_3_rx_disable status uart_cp_rx_disable status mbist_disable status scan_disable status efuse_bist_en status cp_ca5_dbgen status cp_ca5_niden status cp_ca5_spiden status cp_ca5_spniden status cp_ca5_dap_deviceen status every block(31~0) read/write enable status read block22_23 config bit wcn_jtag_disable, write once register wcn_uart_disable, write once register rf_uart_disable, write once register the registers are the mapping address to efuse macro. Write the 12'hxxx address means burn the data into block (12'hxxx<<2) of efuse. Read the 12'hxxx address will get the block (12'hxxx<<2) data of efuse. This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
0000 = use Channel0
0001 = use Channel1
0010 = use Channel2
...
0111 = use Channel7
1111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
1111_1111 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Read FIFO data exchange high 8-bit and low 8-bit.
0: Exchange; [31:0] = {b2,b3,b0,b1}
1: No exchange; [31:0] = {b3,b2,b1,b0} Write FIFO data exchange high 8-bit and low 8-bit.
0: Exchange; [31:0] = {b3,b2,b1,b0}
1: No exchange; [31:0] = {b2,b3,b0,b1} Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Channel Enable, write one in this bit enable the channel.
This channel works only in fifo mode. Channel Disable, write one in this bit to disable the channel. Enable bit, when '1' the channel is running The internal channel fifo is empty Internal fifo level AHB Start Address.
This field represent the start address of the fifo. The start address must 32-bit aligned. AHB End Address.
This field represent the last address of the fifo (it is the first address not used in the fifo).
The end address must 32-bit aligned. Transfer Count, transfer size in bytes.
This bit indicated the transfer size in bytes to perform. Up to 16kbytes per transfer.
During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. The Channel 0 conveys data from the AIF to the memory.
The Channel 1 conveys data from the memory to the AIF.
These Channels only exist with Voice Option. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. When 1 the channel is enabled When 1 the fifo is empty Cause interrupt End of FIFO. Cause interrupt Half of FIFO. Cause interrupt Quarter of FIFO. Cause interrupt Three Quarter of FIFO. Cause interrupt ahb error. End of FIFO interrupt status bit. Half of FIFO interrupt status bit. Quarter of FIFO interrupt status bit. Three Quarter of FIFO interrupt status bit. ahb error interrupt status bit. channel busy status bit. AHB Start Address. This field represent the start address of the FIFO located in RAM. Fifo size in bytes, max 1MBytes.
The size of the fifo must be a multiple of 16 (The four LSB are always zero). END FIFO Mask interrupt. When one this interrupt is enabled. HALF FIFO Mask interrupt. When one this interrupt is enabled. QUARTER FIFO Mask interrupt. When one this interrupt is enabled. THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. ahb_error Mask interrupt. When one this interrupt is enabled. Write one to clear end of fifo interrupt. Write one to clear half of fifo interrupt. Write one to clear Quarter fifo interrupt. Write one to clear Three Quarter fifo interrupt. Write one to clear ahb_error interrupt. Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
0000 = use Channel0
0001 = use Channel1
0010 = use Channel2
...
0111 = use Channel7
1111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
1111_1111 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Read FIFO data exchange high 8-bit and low 8-bit.
0: Exchange; [31:0] = {b2,b3,b0,b1}
1: No exchange; [31:0] = {b3,b2,b1,b0} Write FIFO data exchange high 8-bit and low 8-bit.
0: Exchange; [31:0] = {b3,b2,b1,b0}
1: No exchange; [31:0] = {b2,b3,b0,b1} Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Channel Enable, write one in this bit enable the channel.
This channel works only in fifo mode. Channel Disable, write one in this bit to disable the channel. Enable bit, when '1' the channel is running The internal channel fifo is empty Internal fifo level AHB Start Address.
This field represent the start address of the fifo. The start address must 32-bit aligned. AHB End Address.
This field represent the last address of the fifo (it is the first address not used in the fifo).
The end address must 32-bit aligned. Transfer Count, transfer size in bytes.
This bit indicated the transfer size in bytes to perform. Up to 16kbytes per transfer.
During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. Value loaded to OS timer. Write '1' to this bit will enable OS timer.
When read, the value is what we have written to this bit, it changes immediately after been written. Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.

'1' indicates OS timer enabled.
'0' indicates OS timer not enabled. Read this bit will get the information if OS timer interruption clear operation is finished or not.

'1' indicates OS timer interruption clear operation is on going.
'0' indicates no OS timer interruption clear operation is on going. Write '1' to this bit will set OS timer to repeat mode.
When read, get the information if OS timer is in repeat mode.

'1' indicates OS timer in repeat mode.
'0' indicates OS timer not in repeat mode. Write '1' to this bit will set OS timer to wrap mode.
When read, get the information if OS timer is in wrap mode.

'1' indicates OS timer in wrap mode.
'0' indicates OS timer not in wrap mode. Write '1' to this bit will load the initial value to OS timer. Current value of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. Write '1' to this bit will enable watchdog timer and Load it with WDTimer_LoadVal. Write '1' to this bit will stop watchdog timer. Write '1' to this bit will load WDTimer_LoadVal value to watchdog timer.
Use this bit to implement the watchog keep alive. Read this bit will get the information if watchdog timer is really enabled or not. This bit will change only after the next front of 32 KHz system clock.

'1' indicates watchdog timer is enabled, if current watchdog timer value reaches 0, the system will be reseted.
'0' indicates watchdog timer is not enabled. Load value of watchdog timer. Number of 32kHz Clock before Reset.
This bit enables interval IRQ mode.

'0': hw delay timer does not generate interval IRQ.
'1': hw delay timer generate an IRQ each interval. interval of generating an HwTimer IRQ.

"00": interval of 1/8 second.
"01": interval of 1/4 second.
"10": interval of 1/2 second.
"11": interval of 1 second. Current value of the hardware delay timer. The value is incremented every 61 us. This timer is running all the time and wrap at value 0xFFFFFFFF. Set mask for OS timer IRQ. Set mask for hardwre delay timer wrap IRQ. Set mask for hardwre delay timer interval IRQ. Clear mask for OS timer IRQ. Clear mask for hardwre delay timer wrap IRQ. Clear mask for hardwre delay timer interval IRQ. Clear OS timer IRQ. Clear hardware delay timer wrap IRQ. Clear hardware delay timer interval IRQ. OS timer IRQ cause. hardware delay timer wrap IRQ cause. hardware delay timer interval IRQ cause. OS timer IRQ status. hardware delay timer wrap IRQ status. hardware delay timer interval IRQ status. Value low 32bits loaded to OS timer. Value high 24bits loaded to OS timer. Write '1' to this bit will enable OS timer.
When read, the value is what we have written to this bit, it changes immediately after been written. Read this bit will get the information if OS timer is really enabled or not. This bit will change only after the next front of 16 KHz system clock.

'1' indicates OS timer enabled.
'0' indicates OS timer not enabled. Read this bit will get the information if OS timer interruption clear operation is finished or not.

'1' indicates OS timer interruption clear operation is on going.
'0' indicates no OS timer interruption clear operation is on going. Write '1' to this bit will set OS timer to repeat mode.
When read, get the information if OS timer is in repeat mode.

'1' indicates OS timer in repeat mode.
'0' indicates OS timer not in repeat mode. Write '1' to this bit will set OS timer to wrap mode.
When read, get the information if OS timer is in wrap mode.

'1' indicates OS timer in wrap mode.
'0' indicates OS timer not in wrap mode. Write '1' to this bit will load the initial value to OS timer. Current value low 32bits of OS timer. Current value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. Current locked value low 32bits of OS timer. Current locked value high bits of OS timer. The value is 24 bits and the first 8 bits are sign extension of the most important bit. A negative value indicates that the timer has wraped. This bit enables interval IRQ mode.

'0': hw delay timer does not generate interval IRQ.
'1': hw delay timer generate an IRQ each interval. interval of generating an HwTimer IRQ.

"00": interval of 1/8 second.
"01": interval of 1/4 second.
"10": interval of 1/2 second.
"11": interval of 1 second. Current low 32bits value of the hardware delay timer. Current high 32bits value of the hardware delay timer. Current locked low 32bits value of the hardware delay timer. Current locked high 32bits value of the hardware delay timer. Set mask for OS timer IRQ. Set mask for hardwre delay timer wrap IRQ. Set mask for hardwre delay timer interval IRQ. Clear mask for OS timer IRQ. Clear mask for hardwre delay timer wrap IRQ. Clear mask for hardwre delay timer interval IRQ. Clear OS timer IRQ. Clear hardware delay timer wrap IRQ. Clear hardware delay timer interval IRQ. OS timer IRQ cause. hardware delay timer wrap IRQ cause. hardware delay timer interval IRQ cause. OS timer IRQ status. hardware delay timer wrap IRQ status. hardware delay timer interval IRQ status. transmit data register receive data register baud rate divider constant N: (N>=4) 0011: N=4 ... 0111: N=8 ... 1111: N=16 baud rate divider coeffcient,baud rate formula is: BAUD RATE = Fclk/(Nx(BAUD_DIV+1)) default baud rate is 921.6K, N=4, Ffun=26MHz. Stick parity enble 1: enable 0: disable Automatic baud detection complete interrupt enable 1: enable 0: disable software flow control bit 1: enable 0: disable 1: enable software flow XON interrupt 0: disable software flow XON interrupt 1: enable software flow XOFF interrupt 0: disable software flow XOFF interrupt 1: enable automatically detect baud rate 0: disable automatically detect baud rate 1: autobaud BAUD_CONST=4'b1111 0: autobaud BAUD_CONST=4'b0011 1: the automatic baud rate detects 2 bytes 0: the automatic baud rate detects 1 byte 2'b00: automatic baud rate detection using odd check 2'b01: automatic baud rate detection using even check 1: automatic baud rate detection has test bit 0: automatic baud rate detection has no test bit RX FIFO reset control 1: RX FIFO reset 0: RX FIFO not reset; or set 1'b1, auto clear to 1'b0 TX FIFO reset control 1: TX FIFO reset 0: TX FIFO not reset;or set to 1'b1,auto clear to 1'b0 TRAIL byte manipulation: 1: DMA dispose the TRAIL byte of RXFIFO 0: ARM dispose the TRALL byte of RXFIFO frames stop control 1: enable 0: disable HDLC escape bytes enable control 1: enable add escape bytes(transit data),and remove escape byte(receive data) 0: disable after RX timeout, enable hardware flow control (on condition that HWFC is enable) 1: after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control 0: after RX timeout, disable hardware flow control RX trigger RTS enable control (on condition that HWFC is enable) 1: enable RX TRIG trigger RTS flow signal 0: disable RX TRIG trigger RTS flow signal hardware flow control bit 1: enable 0: disable RX timeout interrupt control bit 1: enable 0: disable TX data interrupt control bit 1: enable TX interrupt 0: disable TX interrupt RX data interrupt control bit 1: enable RX interrupt 0: disable RX interrupt stop bit detection control bit 1: enable stop bit detection 0: disable stop bit detection stop bit control bit 1: 2bit stop bit 0: 1bit stop bit check bit 1: odd check 0: even check check bit enable or not 1: enable 0: disable RX FIFO trigger settings 00000000: don't trigger 00000001: 1 byte trigger 00000010: 2 bytes trigger 00000011: 3 bytes trigger 00000100: 4 bytes trigger ...... 01111111: 127bytes trigger 10000000: 128bytes trigger TX FIFO trigger setting 00000000: 0 byte trigger 00000001: 1 byte trigger 00000010: 2 bytes trigger 00000011: 3 bytes trigger 00000100: 4 bytes trigger ...... 01111110: 126bytes trigger 01111111: 127bytes trigger 10000000: don't trigger configure the time interval between sending data twice 0000: interval 0 baud rate clock 0001: interval 1 baud rate clock 1111: interval 15 baud rate clock configure the threshold value of the UART timeout interrupt counter 00000000: configure the initial value of 0 baud rate clock 00000001: configure the initial value of 1 baud rate clock 00000010: configure the initial value of 2 baud rate clock ...... 11111111: configure the initial value of 255 baud rate clock bit type is changed from rw1c to rc. XON interrupt status bit 1: XON interrupt 0: not XON interrupt bit type is changed from rw1c to rc. XOFF interrupt status bit 1: XOFF interrupt 0: not XOFF interrupt SWFC status 1: prohbit home terminal to send 0: allow home terminal to send bit type is changed from rw1c to rc. request to send status bit 1: prohibit far-end to send 0: request far-end to send bit type is changed from rw1c to rc. clear the sending status bit 1: prohibit home terminal to send 0: allow home terminal to send bit type is changed from rw1c to rc. the received data stop bit state 1: stop bit error 0: stop bit right bit type is changed from rw1c to rc. RX data parity status 1: parity error 0: parity right bit type is changed from rw1c to rc. RX data frame stop bit interrupt status bit 1: received frame stop bit "7E" 0: not received frame stop bit "7E" bit type is changed from rw1c to rc. RX data timeout interrupt status bit 1: timeout 0: not timeout bit type is changed from rw1c to rc. RX data interrupt status bit 1: RX_FIFO_CNTRX_TRIG 0: RX_FIFO_CNT<RX_TRIG bit type is changed from rw1c to rc. TX data interrupt status bit 1: TX_FIFO_CNT TX_TRIG 0: TX_FIFO_CNT >TX_TRIG RX FIFO data number 00000000: RX FIFO has 0 data 00000001: RX FIFO has 1 data ...... 01111111: RX FIFO has 127 data 10000000: RX FIFO has 128 data TX FIFO data number 00000000: TX FIFO has 0 data 00000001: TX FIFO has 1 data ...... 01111111: TX FIFO has 127 data 10000000: TX FIFO has 128 data enable HDLC, the number of RX FIFO data when received at the end of frames(include the end of frames) 00000000: RX FIFO has 0 data 00000001: RX FIFO has 1 data ...... 01111111: RX FIFO has 127 data 10000000: RX FIFO has 128 data Note: UART_RXFIFO_HDLC only read.Uart automatically updates the register value, after receiving the end of frames "7e". After automatic detection, the detective byte is "AT" or "at" 1: "AT" 0: "at" 1: Automatic detection complete,lock baud rate 0: automatic detection is not completed 1: automatic detection failed, no matching bytes detected 0: automatic detection of matching bytes automatic detection of BAUD_DIV values XON characteristic parameter XOFF characteristic parameter Number of key in the keypad Number of key in the low data register Number of key in the high data register For keys in column Idx_KeyOut(from 0 to 3) and in line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_L(Idx_KeyOut*8+Idx_KeyIn) :
0 = Released
1 = Pressed For keys in column Idx_KeyOut(from 4 to 7) and line Idx_KeyIn(from 0 to 7), the pressing status are stored in KP_DATA_H(Idx_KeyIn*8-32+Idx_KeyIn):
0 = Released
1 = Pressed For keys in lines status
0 = Released
1 = Pressed Indicate Key ON pressing status :
0 = Release
1 = Pressed This bit enables key detection. If this bit is '0', the key detection function is disabled. Key ON is an exception, it can be still detected and generate key interrupt even if KP_En = '0', however in this case, the debouncing time configuration in key control register is ignored and the key ON state is considerred to be stable if it keeps same in consecutive 2 cycles of 16KHz clock.

0 = keypad disable
1 = keypad enable De-bounce time = (KP_DBN_TIME + 1) * SCAN_TIME, SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*0.3125*6=15 ms. The maximum debounce time is 480 ms. Configure interval of generating an IRQ if one key or several keys are pressed long time. Interval of IRQ generation = (KP_ITV_Time + 1) * (KP_DBN_TIME + 1) * SCAN_TIME. SCAN_TIME = 0.3125 ms * Number of Enabled KeyOut (determined by KP_OUT_MASK). For example, if KP_ITV_TIME = 7, KP_DBN_TIME = 7, KP_OUT_MASK = "111111", then De-bounce time = (7+1)*(7+1)*0.3125*6=120 ms. each bit masks one input lines.
'1' = enabled
'0' = disabled
The Key In pins 0 to 5 are muxed with the boot mode pins, latched during Reset.
Key_In 0: BOOT_MODE_NO_AUTO_PU.
Key_In 1: BOOT_MODE_FORCE_MONITOR.
Key_In 2: BOOT_MODE_UART_MONITOR_ENABLE.
Key_In 3: BOOT_MODE_USB_MONITOR_DISABLE.
Key_In 4: reserved each bit masks one output lines.
'1' = enabled
'0' = disabled This bit mask keypad irq generated by event0 (key press or key release event, not including all keys release event which is event1).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by event1 (all keys release event).
0 = keypad event irq disable
1 = keypad event irq enable This bit mask keypad irq generated by key pressed long time (generated each interval configured in KP_ITV_Time.
0 = keypad interval irq disable
1 = keypad interval irq enable keypad event0(key press or key release event, not including all keys release which is event1) IRQ cause. keypad event1(all keys release event) IRQ cause. keypad interval irq cause. keypad event0(key press or key release event, not including all keys release which is event1) irq status. keypad event1(all keys release event) irq status. keypad interval irq status. Write '1' to this bit clears key IRQ. Enables the Pulse Width Tone output
1 = Enable PWT output
0 = Disable PWT output The working status of PWT. The PWT_Duty value can be used to set the approximate volume of the tone.
The PWT_Duty value must be less than or equal to half the PWT_Period value and must be at least a value of 8, otherwise no tone will be generated. PWT_Period is the divider value to produce a tone of a given frequency.
To calculate the PWT_Period value, Use the following formula:
PWT_Period = FBASE/FNOTE
where FBASE is the frequency of the PWM module clock (it is based on the system frequency, 26, 39, 52, 78 or 104 MHz divided by 5). FNOTE is the frequency of the desired tone. Setting this bit to '0' will reset the Light Pulse Generator internal counters. Setting this bit to '0' will reset the Light Pulse Generator internal counters. Configures the duty cycle for the Light Pulse Generator by setting the ontime for the LPG output. The actual on-time is calculated as: Tick Period * LPG_OnTime * 256 where the Tick Period is nominally 1/16kHz. Configures the main period of the light pulse generator. The period is calculated based on the following configurations:
with the Tick Period ~ 1/16kHz
Tick Period * 2048 Tick Period * 4096 Tick Period * 8192 Tick Period * 12288 Tick Period * 16384 Tick Period * 20480 Tick Period * 24576 Tick Period * 28672 Sets the lower boundary for PWL pulse. When pulse mode is not used, this is the threshold value for the PWL0. Reading this value will return the current value used for the threshold. Sets the upper boundary for PWL pulse. When pulse mode is not used, this value is ignored. Reading this value will return the LFSR value used for generating the PWL outputs. When this bit is written with '1', the PWL 0 is enabled and the output is a PRBS whose average on-time is proportional to PWL_Min. This bit is cleared when either of the Force bits are written. Reading this bit will return the current state of the PWL0 enable. Writing a '1' to this bit will force the PWL0 to output a low value. If the PWL0 was previously enabled, this will clear the bit. Writing a '1' to this bit will force the PWL0 to output a high value. If the PWL0 was previously enabled, this will clear the bit. This will enable the PWL pulse mode. The threshold will dynamically sweep between PWL_Min and PWL_Max at a rate depending on PWL_Pulse_Per. Writing '1' to this bit will set the output enable. Reading this bit will return the current status. Writing '1' to this bit will clear the output enable. Writing a '1' to this bit will swap the PWL0 and PWL1 outputs. Reading this bit will return the current status. Writing a '1' to this bit will unswap the PWL0/PWL1 outputs. This value will adjust the pulse period when pulsing is enabled. Average duty cycle for the Pulse Width Light 1 output. The average duty cycle is calculated as PWL1_Threshold/256. LFSR value for PWL. When this bit is written with '1', the PWL 1 is enabled and the output is a PRBS whose average on-time is proportional to PWL1_Threshold. This bit is cleared when either of the Force bits are written. Reading this bit will return the current state of the PWL1 enable. Writing a '1' to this bit will force the PWL1 to output a low value. If the PWL1 was previously enabled, this will clear the bit. Writing a '1' to this bit will force the PWL1 to output a high value. If the PWL1 was previously enabled, this will clear the bit. Writing '1' to this bit will set the output enable. Reading this bit will return the current status. Writing '1' to this bit will clear the output enable. TSC X Value. TSC X Value valid. TSC Y Value. TSC Y Value valid. GPADC Value. GPADC Value valid. These 2 bits configure the interval of generating an IRQ status. When write, command to program calendar with a new value (sec, min, hour, day, month, year, day of week) previously written in registers Calendar_LoadVal_H and Calendar_LoadVal_L. This bit is auto cleared.
'1' = load calendar timer.

When read, Calendar timer load status.
'1' = Calendar load has not finished.
'0' = Calendar load has finished. When write, command to program alarm with a new value (sec, min, hour, day, month, year, day of week) prviously written in registers AlarmVal_H and AlarmVal_L. This bit is auto cleared.
'1' = load alarm.

When read, alarm load status.
'1' = alarm load has not finished.
'0' = alarm load has finished. command to enable alarm. When alarm is triggered, it will generate a wakup.
'1' = enable alarm.

When read, alarm enable status.
'1' = alarm enable operation is on going, not finished.
'0' = alarm is enabled. command to disable alarm.
'1' = disable alarm.

When read, alarm enable status.
'1' = alarm disable operation is on going, not finished.
'0' = alarm is disabled. writing '1', clear Alarm triggered signal (connect to wakeup) and alarm triggered IRQ.

When read, get alarm clear status.
'1' = alarm clear operation is on going, not finished.
'0' = alarm is cleared. writing '1', clear interval IRQ. When write '1', Set interval Irq Mask.
When read, get interval Irq mask. When write '1', Clear interval Irq Mask.
When read, get inteval Irq mask. When write '1', mark calendar value to be not valid.

When read, Indicate if the Calendar value is valid or not.
The calendar value is not valid in case of mismatch between the calendar counter and the APB register, which is the case of wakeup the phone after shut down. This mismatch disappear after one RTC cycle or after re-porgramming a new calendar value.
'1' = not valid. Interval Irq Cause. Alarm Irq Cause. Force Wakeup status. After set "Force_Wakeup" to '1' in sys_ctrl, the real force_wakeup is not set immediatly, this bit indicates when the force wakeup is really set. This bits also indicates if the interface between Calendar domain and Core domain is enabled.
'1': force wakeup set. Charger Mask status. After set "Chg_Mask" to '1' in sys_ctrl, the real Chg_Mask line is not set immediatly, this bit indicates when the Chg_Mask line is really set.
'1': Chg_Mask line set. Interval Irq Status. Alarm Enable Status.
Note: When calendar is not programmed, Alarm can be enabled or not.
It is suggested to clear Alarm Enable when program RTC. '1' = Calendar has not been programmed.
This bit keep value '0' after the calendar is programmed once. Second value loaded to calendar, ranged from 0 to 59. Minute value loaded to calendar, ranged from 0 to 59. Hour value loaded to calendar, ranged from 0 to 23. Day value loaded to calendar, ranged from 1 to 31. Month value loaded to calendar, ranged from 1 to 12. Year value loaded to calendar, ranged from 0 to 127.
Represent year 2000 to 2127. Day of the week value loaded to calendar, ranged from 1 to 7.
Represent Monday, Tuesday etc. Current Second value of calendar, ranged from 0 to 59. Current Minute value of calendar, ranged from 0 to 59. Current Hour value of calendar, ranged from 0 to 23. Current Day value of calendar, ranged from 1 to 31.
Maximum number of days in each month are stored in the module, and leap year is supported, so February can have 28 or 29 days. Current Month value of calendar, ranged from 1 to 12. Current Year value of calendar, ranged from 0 to 127.
Represent year 2000 to 2127. Current Day of the week value of calendar, ranged from 1 to 7.
Represent Monday, Tuesday etc. Second value loaded to alarm, ranged from 0 to 59. Minute value loaded to alarm, ranged from 0 to 59. Hour value loaded to alarm, ranged from 0 to 23. Day value loaded to alarm, ranged from 1 to 31. Month value loaded to alarm, ranged from 1 to 12. Year value loaded to alarm, ranged from 0 to 127.
Represent year 2000 to 2127. This reg contains data to be read or written by IFC. In mono mode, data0 is before data1. In stereo mode, data0 is in left channel. This reg contains data to be read or written by IFC. In mono mode, data1 is after data0. In stereo mode, data1 is in right channel. Audio Interface Enable.
0: if AIF_Tone[0] is also 0, AIF is disabled.
1 = AIF Enabled. If AIF_Tone[0] is also '1', Tx fifo continue to fetch and distribute data from IFC when tone is enable. However, these data are not used. Disable AIF Tx functions. Important: if you want to do record only, you must set this bit otherwise AIF state machine will not start.
0 = Both Tx Rx enabled.
1 = Rx enabled only, Tx disabled. Selects parallel audio interface connected to analog front-end.
0 = serial output.
1 = parallel output. Selects parallel audio interface connected to analog front-end.
0 = serial output.
1 = parallel output. Selects parallel audio interface connected to analog front-end.
0 = serial input.
1 = parallel input. Selects parallel audio interface connected to analog front-end.
0 = serial input.
1 = parallel input. In parallel mode, select AIF Tx Strobe mode. Reserved in serial mode.
0 = Tx STB edge is in middle of data.
1 = Tx STB edge is aligned to data edge. This bit indicates if the AIF had needed some data while the Out Fifo was empty. In case of data famine, the last available data will be sent again.
Write one to clear the out_underflow status bit. This bit is auto clear. This bit indicates if the AIF had received some data while the Input Fifo was full. If the Fifo In is full, the newly received data will be lost.
Write one to clear the in_overflow status bit. This bit is auto clear. Sets the loop back mode. The feature is for debug only and can not work in DAI mode. Configure serial AIF mode. "11" is reserved.

When mode is set DAI, the bit Master Mode should be set to '1', bit Endian_L set to '0'. Data should be sent out on falling edge, which requires either Bclk_Pol = '0' and Half_Cycle_DLY = '1' or Bclk_Pol = '1' and Half_Cycle_DLY = '0'. Bits Tx_DLY and BCKOut_Gate must be configured to '0' and '1'.
The DAI mode must NOT be modified after AIF is enabled.
Select AIF I2S input. configure AIF works in master mode (LRCLK and BCK timing signals are generated internally) or slave mode (LRCLK and BCK timing signals are generated externally). When high, the output data format is with the least significant bit first. configure LRCK polarity.
0 = high level on LRCK means left channel, low level on LRCK means right channel.
1 = high level on LRCK means right channel, low level on LRCK means left channel.

Note: this bit should be set to '0' (LEFT_H_RIGHT_L) in voice mode. . Indicates the delay between serial data in MSB and LRCK edge.
"00" = Digital audio in MSB is aligned with LRCLK edge.
"01" = Digital audio in MSB is 1 cycle delayed to LRCLK edge.
"10" = Digital audio in MSB is 2 cycle delayed to LRCLK edge.
"11" = Digital audio in MSB is 3 cycle delayed to LRCLK edge. configure the delay between serial data out MSB and LRCK edge.
"0" = Digital audio out MSB is aligned with LRCLK edge.
"1" = Digital audio out MSB is 1 cycle delayed to LRCLK edge. ONLY for slave mode: configure 1 cycle supplementary Tx delay.
"0" = No supplementary Tx delay.
"1" = One Cycle supplementary Tx delay. Configure mono or stereo format for Audio data out. This field is used both in serial mode or in parallel EXT mode.
"00" = stereo input from IFC, stereo output to pin.
"01" = mono input from IFC, stereo output in left channel to pin. This value is reserved in parallel EXT mode.
"10" = mono input from IFC, stereo output duplicate in both channels to pin.
"11" = stereo input from IFC, mono output to left and right channel. This mode is only used for parallel stereo interface.

if AIF works in DAI or Voice mode, always select "00" mode STEREO_STEREO. Configure mono or stereo format for Audio data in.
0 = stereo input from pin, stereo output to IFC.
1 = stereo input from pin, mono input to IFC selected from left channel.

Users can change LRCK polarity to choose mono input from right channel. configure the ratio of BCK and LRCK cycle from 16 to 31.
Voice_Mode: "XXXX": each sample takes 16 + "XXXX" BCLK cycle.
Audio_Mode: "XXXX": each sample takes 2*(16 + "XXXX) BCLK cycle. 2 times than Voice Mode because in audio mode each sample occupies two channels. if Master Mode, invert BCLK out. if slave Mode, invert BCLK in. delayed Audio output data or LRCK by half cycle. delayed Audio input data by half cycle. Sets the BckOut gating. This bit decide if AIF continue to output BCK clock after 16-bit data has been sent. When this bit is set, the audio interface is enabled and a comfort tone or DTMF tone is output on the audio interface instead of the regular data, even if the AIF_CTRL[0] enable bit is 0.
0 = AIF is disabled if the AIF_CTRL[0] is also 0.
1 = AIF is enabled and generates a tone. Select whether a DTMF of a comfort tone is generated. Frequency of the first DTMF sine wave. Frequency of the second DTMF sine wave. Frequency of comfort tone. Tone attenuation. The Comfort Tone or DTMF is attenuated according to this programmable gain. Side Tone attenuation. The side tone is attenuated according to this programmable gain.
0000 = mute.
0001 = -36 dB.
0010 = -33 dB.
0011 = -30 dB.
0100 = -27 dB.
0101 = -24 dB.
0110 = -21 dB.
0111 = -18 dB.
1000 = -15 dB.
1001 = -12 dB.
1010 = -9 dB.
1011 = -6 dB.
1100 = -3 dB.
1101 = 0 dB.
1110 = +3 dB.
1111 = +6 dB. set rx load position delay, the range is 0 to 15. "1" enable fm record. "1" swap fm left and right channel. [9:8]=='b00: select adc input data ; [9:8]=='b01: select dac output loop data ; [9:8]=='b1x: force to zero ; [6]==0: fm input to aif1; [6]=1: audio codec input to aif1; [7]==0: fm input to aif2; [7]=1: audio codec input to aif2; [5:4]=='bx1: aif1 output to audio codec ; [5:4]=='b10: aif2 output to audio codec ; [5:4]=='b00: zero output to audio codec ; ==1: enable adc left channel; ==1: enable dac right channel; ==1: enable adc left channel; ==1: enable adc right channel; ==1: enable mute; ==1: enable soft mute; dac mute counter1 threshold, step is countrolled by counter 0; dac mute counter0 threshold dac fs frequency 0:96K 1:48K 2:44.1K 3:32K 4:24K 5:22.05K 6:16K 7:12K 8:11.025K 9:9.6K 10:8K adc src upsample tap, sample rate=N*4K ==1: enable audio adc parallel data loop to dac parallel data path; ==0: force to 0 to select 26m audio clock; ==1: invert output mclk ; left adc channel dgain 4'hf: 16dB 4'he: 14dB 4'hd: 12dB 4'hc: 10dB 4'hb: 8dB 4'ha: 6dB 4'h9: 4dB 4'h8: 2dB 4'h7: 0dB 4'h6:-2dB 4'h5:-4dB 4'h4:-6dB 4'h3:-8dB 4'h2:-10dB 4'h1:-12dB 4'h0:mute right adc channel dgain 4'hf: 16dB 4'he: 14dB 4'hd: 12dB 4'hc: 10dB 4'hb: 8dB 4'ha: 6dB 4'h9: 4dB 4'h8: 2dB 4'h7: 0dB 4'h6:-2dB 4'h5:-4dB 4'h4:-6dB 4'h3:-8dB 4'h2:-10dB 4'h1:-12dB 4'h0:mute right adc channel dgain 1:sel tone dac tone dgain 0:sel normal dac dgain left dac channel dgain [5:1] = 5'h1f: 05dB 5'h1e: 04dB 5'h1d: 03dB 5'h1c: 02dB 5'h1b: 01dB 5'h1a: 00dB 5'h19: -01dB 5'h18: -02dB 5'h17: -03dB 5'h16: -04dB 5'h15: -05dB 5'h14: -06dB 5'h13: -07dB 5'h12: -08dB 5'h11: -09dB 5'h10: -10dB 5'h0f: -11dB 5'h0e: -12dB 5'h0d: -13dB 5'h0c: -14dB 5'h0b: -15dB 5'h0a: -16dB 5'h09: -17dB 5'h08: -18dB 5'h07: -19dB 5'h06: -20dB 5'h05: -21dB 5'h04: -22dB 5'h03: -23dB 5'h02: -24dB 5'h01: -25dB 5'h00: -26dB [0]:1'b1,+0.5dB [7]:1'b1,+12dB [6]:1'b1,+6dB right dac channel dgain detail see dac_l_nor_dgain[7:0] left dac channel dgain detail see dac_l_nor_dgain[7:0] right dac channel dgain detail see dac_l_nor_dgain[7:0] OTG Control and Status Register The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the controller.
Mode: Device only

Session Request Success (SesReqScs)

The core sets this bit when a session request initiation is successful.

- 1'b0: Session request failure

- 1'b1: Session request success

Mode: Device only

Session Request (SesReq)

The application sets this bit to initiate a session request on the USB. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The core clears this bit when the HstNegSucStsChng bit is cleared.

If you use the USB 1.1 Full-Speed Serial Transceiver interface to initiate the session request, the application must wait until the VBUS discharges to 0.2 V, after the B-Session Valid bit in this register (GOTGCTL.BSesVld) is cleared. This discharge time varies between different PHYs and can be obtained from the PHY vendor.

- 1'b0: No session request

- 1'b1: Session request

Mode: Host only

VBUS Valid Override Enable (VbvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.VbvalidOvVal.

- 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.VbvalidOvVal.

- 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the controller.

Mode: Host only

VBUS Valid OverrideValue (VbvalidOvVal)

This bit is used to set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn is set.

- 1'b0 : vbusvalid value is 1'b0 when GOTGCTL.VbvalidOvEn =1

- 1'b1 : vbusvalid value is 1'b1 when GOTGCTL.VbvalidOvEn =1

Mode: Host only

A-Peripheral Session Valid Override Enable (AvalidOvEn)

This bit is used to enable/disable the software to override the Avalid signal using the GOTGCTL.AvalidOvVal.

- 1'b1: Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal.

- 1'b0: Override is disabled and avalid signal from the respective PHY selected is used internally by the core

Mode: Host only

A-Peripheral Session Valid OverrideValue (AvalidOvVal)

This bit is used to set Override value for Avalid signal when GOTGCTL.AvalidOvEn is set.

- 1'b0 : Avalid value is 1'b0 when GOTGCTL.AvalidOvEn =1

- 1'b1 : Avalid value is 1'b1 when GOTGCTL.AvalidOvEn =1

Mode: Device only

B-Peripheral Session Valid Override Value (BvalidOvEn)

This bit is used to enable/disable the software to override the Bvalid signal using the GOTGCTL.BvalidOvVal.

- 1'b1 : Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal.

- 1'b0 : Override is disabled and bvalid signal from the respective PHY selected is used internally by the force

Mode: Device only

B-Peripheral Session Valid OverrideValue (BvalidOvVal)

This bit is used to set Override value for Bvalid signal when GOTGCTL.BvalidOvEn is set.

- 1'b0 : Bvalid value is 1'b0 when GOTGCTL.BvalidOvEn =1

- 1'b1 : Bvalid value is 1'b1 when GOTGCTL.BvalidOvEn =1

Mode: HNP-capable Device

Host Negotiation Success (HstNegScs)

The controller sets this bit when host negotiation is successful. The controller clears this bit when the HNP Request (HNPReq) bit in this register is set.

- 1'b0: Host negotiation failure

- 1'b1: Host negotiation success

Mode: HNP Capable OTG Device

HNP Request (HNPReq)

The application sets this bit to initiate an HNP request to the connected USB host. The application can clear this bit by writing a 0 when the Host Negotiation Success Status Change bit in the OTG Interrupt register (GOTGINT.HstNegSucStsChng) is SET. The controller clears this bit when the HstNegSucStsChng bit is cleared.

- 1'b0: No HNP request

- 1'b1: HNP request

Mode: HNP Capable OTG Host

Host Set HNP Enable (HstSetHNPEn)

The application sets this bit when it has successfully enabled HNP (using the SetFeature.SetHNPEnable command) on the connected device.

- 1'b0: Host Set HNP is not enabled

- 1'b1: Host Set HNP is enabled

Mode: HNP Capable OTG Device

Device HNP Enabled (DevHNPEn)

The application sets this bit when it successfully receives a SetFeature.SetHNPEnable command from the connected USB host.

- 1'b0: HNP is not enabled in the application

- 1'b1: HNP is enabled in the application

Mode: SRP Capable Host

Embedded Host Enable (EHEn)

It is used to select between OTG A Device state Machine and Embedded Host state machine.

- 1'b0: OTG A Device state machine is selected

- 1'b1: Embedded Host State Machine is selected

Note:

This field is valid only in SRP-Capable OTG Mode (OTG_MODE=0,1).

Mode: Host and Device

Debounce Filter Bypass

Bypass Debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled.

- 1'b0: Disabled

- 1'b1: Enabled




Note: This register bit is valid only when debounce filters are present in core.


Mode: Host and Device

Connector ID Status (ConIDSts)

Indicates the connector ID status on a connect event.

- 1'b0: The core is in A-Device mode.

- 1'b1: The core is in B-Device mode.


Note:

The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

Reset:

- 1'b0: in host only mode (OTG_MODE = 5 or 6)

- 1'b1: in all other configurations

Mode: Host only

Long/Short Debounce Time (DbncTime)

Indicates the debounce time of a detected connection.

- 1'b0: Long debounce time, used for physical connections (100 ms + 2.5 micro-sec)

- 1'b1: Short debounce time, used for soft connections (2.5 micro-sec)

Mode: Host only

A-Session Valid (ASesVld)

Indicates the Host mode transceiver status.

- 1'b0: A-session is not valid

- 1'b1: A-session is valid

Note: If you do not enabled OTG features (such as SRP and HNP), the read reset value will be 1. The vbus assigns the values internally for non-SRP or non-HNP configurations.

In case of OTG_MODE=0, the reset value of this bit is 1'b0.

Mode: Device only

B-Session Valid (BSesVld)

Indicates the Device mode transceiver status.

- 1'b0: B-session is not valid.

- 1'b1: B-session is valid.

In OTG mode, you can use this bit to determine if the device is connected or disconnected.


Note:

- If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations.

- In case of OTG_MODE=0, the reset value of this bit is 1'b0.

- The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.

OTG Version (OTGVer)

Indicates the OTG revision.

- 1'b0: OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP.

- 1'b1: OTG Version 2.0. In this version the core supports only Data line pulsing for SRP.

Current Mode of Operation (CurMod)

Mode: Host and Device

Indicates the current mode.

- 1'b0: Device mode

- 1'b1: Host mode

Reset:

- 1'b1 in Host-only mode (OTG_MODE=5 or 6)

- 1'b0 in all other configurations

Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.
OTG Interrupt Register The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.
Mode: Host and Device

Session End Detected (SesEndDet)

The controller sets this bit when the utmiotg_bvalid signal is deasserted. This bit can be set only by the core and the application should write 1 to clear it.

Mode: Host and Device

Session Request Success Status Change (SesReqSucStsChng)

The core sets this bit on the success or failure of a session request. The application must read the Session Request Success bit in the OTG Control and Status register (GOTGCTL.SesReqScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.

Mode: Host and Device

Host Negotiation Success Status Change (HstNegSucStsChng)

The core sets this bit on the success or failure of a USB host negotiation request. The application must read the Host Negotiation Success bit of the OTG Control and Status register (GOTGCTL.HstNegScs) to check for success or failure. This bit can be set only by the core and the application should write 1 to clear it.

Mode:Host and Device

Host Negotiation Detected (HstNegDet)

The core sets this bit when it detects a host negotiation request on the USB. This bit can be set only by the core and the application should write 1 to clear it.

Mode: Host and Device

A-Device Timeout Change (ADevTOUTChg)

The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect.This bit can be set only by the core and the application should write 1 to clear it.

Mode: Host only

Debounce Done (DbnceDone)

The core sets this bit when the debounce is completed after the device connect. The application can start driving USB reset after seeing this interrupt. This bit is only valid when the HNP Capable or SRP Capable bit is SET in the Core USB Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). This bit can be set only by the core and the application should write 1 to clear it.
AHB Configuration Register This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.
Mode: Host and device

Global Interrupt Mask (GlblIntrMsk)

The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bit's setting, the interrupt status registers are updated by the controller.

- 1'b0: Mask the interrupt assertion to the application.

- 1'b1: Unmask the interrupt assertion to the application.

Mode: Host and device

Burst Length/Type (HBstLen)

This field is used in both External and Internal DMA modes. In External DMA mode, these bits appear on dma_burst[3:0] ports, which can be used by an external wrapper to interface the External DMA Controller interface to Synopsys DW_ahb_dmac or ARM PrimeCell.

External DMA Mode defines the DMA burst length in terms of 32-bit words:

- 4'b0000: 1 word

- 4'b0001: 4 words

- 4'b0010: 8 words

- 4'b0011: 16 words

- 4'b0100: 32 words

- 4'b0101: 64 words

- 4'b0110: 128 words

- 4'b0111: 256 words

- Others: Reserved

Internal DMA Mode AHB Master burst type:

- 4'b0000 Single

- 4'b0001 INCR

- 4'b0011 INCR4

- 4'b0101 INCR8

- 4'b0111 INCR16

- Others: Reserved

Mode: Host and device

DMA Enable (DMAEn)


This bit is always 0 when Slave-Only mode has been selected.


Reset: 1'b0

Mode: Host and device

Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)

This bit is used only in Slave mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered.

With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered.

Host mode and with Shared FIFO with device mode:

- 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty

- 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty

Dedicated FIFO in device mode:

- 1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty

- 1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty

Mode: Host only

Periodic TxFIFO Empty Level (PTxFEmpLvl)

Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode.

- 1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty

- 1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty

Mode: Host and Device

Remote Memory Support (RemMemSupp)

This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers.

- GAHBCFG.RemMemSupp=1

The int_dma_req output signal is asserted when the DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from the controller. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint.

- GAHBCFG.RemMemSupp=0

The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as the DMA write transfer is done at the Core Boundary and it does not wait for the sys_dma_done signal to complete the DATA transfers.

Mode: Host and Device

Notify All DMA Write Transactions (NotiAllDmaWrit)

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1.

- GAHBCFG.NotiAllDmaWrit = 1

The core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint.

- GAHBCFG.NotiAllDmaWrit = 0

The core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint.

Mode: Host and Device

AHB Single Support (AHBSingle)

This bit when programmed supports Single transfers for the remaining data in a transfer when the core is operating in DMA mode.

- 1'b0: The remaining data in the transfer is sent using INCR burst size.

- 1'b1: The remaining data in the transfer is sent using Single burst size.

Note: If this feature is enabled, the AHB RETRY and SPLIT transfers still have INCR burst type. Enable this feature when the AHB Slave connected to the core does not support INCR burst (and when Split, and Retry transactions are not being used in the bus).

Mode: Host and Device

Invert Descriptor Endianess (InvDescEndianess)

- 1'b0: Descriptor Endianness is same as AHB Master Endianness.

- 1'b1:

-- If the AHB Master endianness is Big Endian, the Descriptor Endianness is Little Endian.

-- If the AHB Master endianness is Little Endian, the Descriptor Endianness is Big Endian.
USB Configuration Register This register can be used to configure the core after power-on or a changing to Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.
Mode: Host and Device

HS/FS Timeout Calibration (TOutCal)


The number of PHY clocks that the application programs in this field is added to the high-speed/full-speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY. This can be required, because the delay introduced by the PHY in generating the linestate condition can vary from one PHY to another.


The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows:


High-speed operation:

- One 30-MHz PHY clock = 16 bit times

- One 60-MHz PHY clock = 8 bit times

Full-speed operation:

- One 30-MHz PHY clock = 0.4 bit times

- One 60-MHz PHY clock = 0.2 bit times

- One 48-MHz PHY clock = 0.25 bit times


Mode: Host and Device

PHY Interface (PHYIf)

The application uses this bit to configure the core to support a UTMI+ PHY with an 8- or 16-bit interface. When a ULPI PHY is chosen, this must be Set to 8-bit mode.

- 1'b0: 8 bits

- 1'b1: 16 bits

This bit is writable only If UTMI+ and ULPI were selected. Otherwise, this bit returns the value for the power-on interface selected during configuration.

Mode: Host and Device

ULPI or UTMI+ Select (ULPI_UTMI_Sel)


The application uses this bit to select either a UTMI+ interface or ULPI Interface.

- 1'b0: UTMI+ Interface

- 1'b1: ULPI Interface

Mode: Host and Device

Full-Speed Serial Interface Select (FSIntf)


The application uses this bit to select either a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface.

- 1'b0: 6-pin unidirectional full-speed serial interface

- 1'b1: 3-pin bidirectional full-speed serial interface

If a USB 1.1 Full-Speed Serial Transceiver interface was not selected, this bit is always 0, with Write Only access. If a USB 1.1 FS interface was selected, Then the application can Set this bit to select between the 3- and 6-pin interfaces, and access is Read and Write.


Note: For supporting the new 4-pin bi-directional interface, you need to select 6-pin unidirectional FS serial mode, and add an external control to convert it to a 4-pin interface.

PHYSel


Mode: Host and Device


USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select (PHYSel)

The application uses this bit to select either a high-speed UTMI+ or ULPI PHY, or a full-speed transceiver.

- 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY

- 1'b1: USB 1.1 full-speed serial transceiver

If a USB 1.1 Full-Speed Serial Transceiver interface was not selected in, this bit is always 0, with Write Only access.

If a high-speed PHY interface was not selected in, this bit is always 1, with Write Only access.

If both interface types were selected (parameters have non-zero values), the application uses this bit to select which interface is active, and access is Read and Write.

Mode: Host and Device

SRP-Capable (SRPCap)

The application uses this bit to control the controller's SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to

activate VBUS and start a session.

- 1'b0: SRP capability is not enabled.

- 1'b1: SRP capability is enabled.

If SRP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.

Mode: Host and Device

HNP-Capable (HNPCap)

The application uses this bit to control the controller's HNP capabilities.

- 1'b0: HNP capability is not enabled.

- 1'b1: HNP capability is enabled.

If HNP functionality is disabled by the software, the OTG signals on the PHY domain must be tied to the appropriate values.

Mode: Device only

USB Turnaround Time (USBTrdTim)

Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). This must be programmed to

- 4'h5: When the MAC interface is 16-bit UTMI+ .

- 4'h9: When the MAC interface is 8-bit UTMI+ .

Note: The previous values are calculated for the minimum AHB frequency of 30 MHz. USB turnaround time is critical for certification where long cables and 5-Hubs are used. If you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, these bits can be programmed to a larger value.

PHY Low-Power Clock Select (PhyLPwrClkSel)

Mode: Host and Device

Selects either 480-MHz or 48-MHz (low-power) PHY mode. In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.

- 1'b0: 480-MHz Internal PLL clock

- 1'b1: 48-MHz External Clock

In 480 MHz mode, the UTMI interface operates at either 60 or 30-MHz, depending upon whether 8- or 16-bit data width is selected.

In 48-MHz mode, the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode (depending on the PHY vendor). This bit drives the utmi_fsls_low_power core output signal, and is valid only for UTMI+ PHYs.

Mode: Device only

TermSel DLine Pulsing Selection (TermSelDLPulse)

This bit selects utmi_termselect to drive data line pulse during SRP.

- 1'b0: Data line pulsing using utmi_txvalid (Default).

- 1'b1: Data line pulsing using utmi_termsel.

Mode: Host and Device

IC_USB-Capable (IC_USBCap)

The application uses this bit to control the core's IC_USB capabilities.

- 1'b0: IC_USB PHY Interface is not selected.

- 1'b1: IC_USB PHY Interface is selected.

This bit is writable only if OTG_ENABLE_IC_USB=1 and OTG_FSPHY_INTERFACE!=0.

The reset value depends on the configuration parameter OTG_SELECT_IC_USB when OTG_ENABLE_IC_USB = 1. In all other cases, this bit is set to 1'b0 and the bit is read only.

Mode: Device only

Tx End Delay (TxEndDelay)

Writing 1'b1 to this bit enables the controller to follow the TxEndDelay timings as per UTMI+ specification 1.05 section 4.1.5 for opmode signal during remote wakeup.

- 1'b0 : Normal Mode.

- 1'b1 : Tx End delay.

Mode: Host and device

Force Host Mode (ForceHstMode)

Writing a 1 to this bit forces the core to host mode irrespective of utmiotg_iddig input pin.

- 1'b0 : Normal Mode.

- 1'b1 : Force Host Mode.

After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

Mode:Host and device

Force Device Mode (ForceDevMode)

Writing a 1 to this bit forces the controller to device mode irrespective of utmiotg_iddig input pin.

- 1'b0 : Normal Mode.

- 1'b1 : Force Device Mode.

After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 micro sec is sufficient. This bit is valid only when OTG_MODE = 0, 1 or 2. In all other cases, this bit reads 0.

Mode: Host and device

Corrupt Tx packet (CorruptTxPkt)

This bit is for debug purposes only. Never Set this bit to 1. The application should always write 1'b0 to this bit.
Reset Register The application uses this register to reset various hardware features inside the controller.
Mode: Host and Device

Core Soft Reset (CSftRst)

Resets the hclk and phy_clock domains as follows:

- Clears the interrupts and all the CSR registers except the following register bits:

-- PCGCCTL.RstPdwnModule

-- PCGCCTL.GateHclk

-- PCGCCTL.PwrClmp

-- PCGCCTL.StopPPhyLPwrClkSelclk

-- GUSBCFG.ForceDevMode

-- GUSBCFG.ForceHstMode

-- GUSBCFG.PhyLPwrClkSel

-- GUSBCFG.DDRSel

-- GUSBCFG.PHYSel

-- GUSBCFG.FSIntf

-- GUSBCFG.ULPI_UTMI_Sel

-- GUSBCFG.PHYIf

-- GUSBCFG.TxEndDelay

-- GUSBCFG.TermSelDLPulse

-- GUSBCFG.ULPIClkSusM

-- GUSBCFG.ULPIAutoRes

-- GUSBCFG.ULPIFsLs

-- GGPIO

-- GPWRDN

-- GADPCTL

-- HCFG.FSLSPclkSel

-- DCFG.DevSpd

-- DCTL.SftDiscon

- All module state machines

- All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed.

- Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately.

- When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset.

The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after

all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay). Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.


Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.

Mode: Host and Device

PIU FS Dedicated Controller Soft Reset (PIUFSSftRst)


Resets the PIU FS Dedicated Controller

All module state machines in FS Dedicated Controller of PIU are reset to the IDLE state. Used to reset the FS Dedicated controller in PIU in case of any PHY Errors like Loss of activity or Babble Error resulting in the PHY remaining in RX state for more than one frame boundary.

This is a self clearing bit and core clears this bit after all the necessary logic is reset in the core.

Mode: Host only

Host Frame Counter Reset (FrmCntrRst)

The application writes this bit to reset the (micro)Frame number counter inside the core. When the (micro)Frame counter is reset, the subsequent SOF sent out by the core has a (micro)Frame number of 0.

When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.

Mode: Host and Device

RxFIFO Flush (RxFFlsh)

The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction.

The application must only write to this bit after checking that the controller is neither reading from the RxFIFO nor writing to the RxFIFO.


The application must wait until the bit is cleared before performing any other operations. This bit requires eight clocks (slowest of PHY or AHB clock) to clear.

Mode: Host and Device

TxFIFO Flush (TxFFlsh)

This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction.

The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO.

Verify using these registers:

- ReadNAK Effective Interrupt ensures the core is not reading from the FIFO

- WriteGRSTCTL.AHBIdle ensures the core is not writing anything to the FIFO.

Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.

Mode: Host and Device

TxFIFO Number (TxFNum)

This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.

- 5'h0:

-- Non-periodic TxFIFO flush in Host mode

-- Non-periodic TxFIFO flush in device mode when in shared FIFO operation

-- Tx FIFO 0 flush in device mode when in dedicated FIFO mode

- 5'h1:

-- Periodic TxFIFO flush in Host mode

-- Periodic TxFIFO 1 flush in Device mode when in shared FIFO operation

-- TXFIFO 1 flush in device mode when in dedicated FIFO mode

- 5'h2:

-- Periodic TxFIFO 2 flush in Device mode when in shared FIFO operation

-- TXFIFO 2 flush in device mode when in dedicated FIFO mode

...

- 5'hF

-- Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation

-- TXFIFO 15 flush in device mode when in dedicated FIFO mode

- 5'h10: Flush all the transmit FIFOs in device or host mode

Mode: Host and Device

DMA Request Signal (DMAReq)

Indicates that the DMA request is in progress. Used for debug.

Mode: Host and Device

AHB Master Idle (AHBIdle)

Indicates that the AHB Master State Machine is in the IDLE condition.
Interrupt Register This register interrupts the application for system-level events in the current mode (Device mode or Host mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device mode only. This register also indicates the current mode. To clear the interrupt status bits of type R_SS_WC, the application must write 1'b1 into the bit. The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. Note: Read the reset value of GINTSTS.CurMod only after the following conditions: - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.
Mode: Host and Device

Current Mode of Operation (CurMod)

Indicates the current mode.

- 1'b0: Device mode

- 1'b1: Host mode




Note: The reset value of this register field can be read only after the PHY clock is stable, or if IDDIG_FILTER is enabled, wait for the filter timer to expire to read the correct reset value which ever event is later.


Mode: Host and Device

Mode Mismatch Interrupt (ModeMis)

The core sets this bit when the application is trying to access:

- A Host mode register, when the controller is operating in Device mode

- A Device mode register, when the controller is operating in Host mode

The register access is completed on the AHB with an OKAY response, but is ignored by the controller internally and does not affect the operation of the controller.

This bit can be set only by the core and the application should write 1 to clear it.

Mode: Host and Device

OTG Interrupt (OTGInt)

The controller sets this bit to indicate an OTG protocol event. The application must read the OTG Interrupt Status (GOTGINT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the GOTGINT register to clear this bit.

Mode: Host and Device

Start of (micro)Frame (Sof)


In Host mode, the core sets this bit to indicate that an SOF (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.


In Device mode, the controller sets this bit to indicate that an SOF token has been received on the USB. The application can read the Device Status register to get the current (micro)Frame number. This interrupt is seen only when the core is operating at either HS or FS. This bit can be set only by the core and the application must write 1 to clear it.


Note: This register may return 1'b1 if read immediately after power-on reset.

If the register bit reads 1'b1 immediately after power-on reset, it does not indicate that an SOF has been sent (in case of host mode) or SOF has been received (in case of device mode).

The read value of this interrupt is valid only after a valid connection between host and device is established. If the bit is set after power on reset the application can clear the bit.

Mode: Host and Device

RxFIFO Non-Empty (RxFLvl)


Indicates that there is at least one packet pending to be read from the RxFIFO.

Mode: Host and Device

Non-periodic TxFIFO Empty (NPTxFEmp)

This interrupt is asserted when the Non-periodic TxFIFO is either half or completely empty, and there is space for at least one Entry to be written to the Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl).

In host mode, the application can use GINTSTS.NPTxFEmp with the OTG_EN_DED_TX_FIFO parameter set to either 1 or 0.

In device mode, the application uses GINTSTS.NPTxFEmp when OTG_EN_DED_TX_FIFO=0. When OTG_EN_DED_TX_FIFO=1, the application uses DIEPINTn.TxFEmp.

Mode: Device only

Global IN Non-periodic NAK Effective (GINNakEff)

Indicates that the Set Global Non-periodic IN NAK bit in the Device Control register (DCTL.SGNPInNak) set by the application, has taken effect in the core. That is, the core has sampled the Global IN NAK bit Set by the application. This bit can be cleared by clearing the Clear Global Non-periodic IN NAK bit in the Device Control register (DCTL.CGNPInNak). This interrupt does not necessarily mean that a NAK handshake

is sent out on the USB. The STALL bit takes precedence over the NAK bit.

Mode: Device only

Global OUT NAK Effective (GOUTNakEff)

Indicates that the Set Global OUT NAK bit in the Device Control register (DCTL.SGOUTNak), Set by the application, has taken effect in the core. This bit can be cleared by writing the Clear Global OUT NAK bit in the Device Control register (DCTL.CGOUTNak).

Mode: Device only

Early Suspend (ErlySusp)

The controller sets this bit to indicate that an Idle state has been detected on the USB for 3 ms.

Mode: Device only

USB Suspend (USBSusp)

The controller sets this bit to indicate that a suspend was detected on the USB. The controller enters the Suspended state when there is no activity on the linestate signal for an extended period of time.

Mode: Device only

USB Reset (USBRst)

The controller sets this bit to indicate that a reset is detected on the USB.

Mode: Device only

Enumeration Done (EnumDone)

The core sets this bit to indicate that speed enumeration is complete. The application must read the Device Status (DSTS) register to obtain the enumerated speed.

Mode: Device only

Isochronous OUT Packet Dropped Interrupt (ISOOutDrop)

The controller sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum packet size packet for the isochronous OUT endpoint.

Mode: Device only

End of Periodic Frame Interrupt (EOPF)

Indicates that the period specified in the Periodic Frame Interval field of the Device Configuration register (DCFG.PerFrInt) has been reached in the current microframe.

Mode: Device only

Endpoint Mismatch Interrupt (EPMis)

Note: This interrupt is valid only in shared FIFO operation.

Indicates that an IN token has been received for a non-periodic endpoint, but the data for another endpoint is present in the top of the Non-periodic Transmit FIFO and the IN endpoint mismatch count programmed by the application has expired.

Mode: Device only

IN Endpoints Interrupt (IEPInt)

The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the IN endpoint on Device IN Endpoint-n Interrupt (DIEPINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the corresponding DIEPINTn register to

clear this bit.

Mode: Device only

OUT Endpoints Interrupt (OEPInt)

The controller sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of the core (in Device mode). The application must read the Device All Endpoints Interrupt (DAINT) register to determine the exact number of the OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the interrupt. The application must

clear the appropriate status bit in the corresponding DOEPINTn register to clear this bit.

Mode: Device only

Incomplete Isochronous IN Transfer (incompISOIN)

The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.

Note: This interrupt is not asserted in Scatter/Gather DMA mode.

Incomplete Periodic Transfer (incomplP)

Mode: Host only

In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending which are scheduled for the current microframe.

Incomplete Isochronous OUT Transfer (incompISOOUT)

Mode: Device only

The Device mode, the core sets this interrupt to indicate that there is at least one isochronous OUT endpoint on which the transfer is not completed in the current microframe. This interrupt is asserted along with the End of Periodic Frame Interrupt (EOPF) bit in this register.

Mode: Device only

Data Fetch Suspended (FetSusp)

This interrupt is valid only in DMA mode. This interrupt indicates that the core has stopped fetching data. For IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.


For example, after detecting an endpoint mismatch, the application:

- Sets a Global non-periodic IN NAK handshake

- Disables IN endpoints

- Flushes the FIFO

- Determines the token sequence from the IN Token Sequence Learning Queue

- Re-enables the endpoints

- Clears the Global non-periodic IN NAK handshake

If the Global non-periodic IN NAK is cleared, the core has not yet fetched data for the IN endpoint, and the IN token is received. The core generates an 'IN token received when FIFO empty' interrupt. The DWC_otg then sends the host a NAK response. To avoid this scenario, the application can check the GINTSTS.FetSusp interrupt, which ensures that the FIFO is full before clearing a Global NAK handshake.


Alternatively, the application can mask the IN token received when FIFO empty interrupt when clearing a Global IN NAK handshake.

Mode: Device only

Reset detected Interrupt (ResetDet)

In Device mode, this interrupt is asserted when a reset is detected on the USB in partial power-down mode when the device is in Suspend.


In Host mode, this interrupt is not asserted.

Mode: Host only

Host Port Interrupt (PrtInt)

The core sets this bit to indicate a change in port status of one of the controller ports in Host mode. The application must read the Host Port Control and Status (HPRT) register to determine the exact event that caused this interrupt. The application must clear the appropriate status bit in the Host Port

Control and Status register to clear this bit.

Mode: Host only

Host Channels Interrupt (HChInt)

The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in Host mode). The application must read the Host All Channels Interrupt (HAINT) register to determine the exact number of the channel on which the interrupt occurred, and Then read the corresponding Host

Channel-n Interrupt (HCINTn) register to determine the exact cause of the interrupt. The application must clear the appropriate status bit in the HCINTn register to clear this bit.

Mode: Host only

Periodic TxFIFO Empty (PTxFEmp)

This interrupt is asserted when the Periodic Transmit FIFO is either half or completely empty and there is space for at least one entry to be written in the Periodic Request Queue. The half or completely empty status is determined by the Periodic TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.PTxFEmpLvl).

Mode: Host and Device

Connector ID Status Change (ConIDStsChng)

The core sets this bit when there is a change in connector ID status.

Mode: Host only

Disconnect Detected Interrupt (DisconnInt)

Asserted when a device disconnect is detected.

Mode: Host and Device

Session Request/New Session Detected Interrupt (SessReqInt)

In Host mode, this interrupt is asserted when a session request is detected from the device. In Host mode, this interrupt is asserted when a session request is detected from the device.

In Device mode, this interrupt is asserted when the utmisrp_bvalid signal goes high.

For more information on how to use this interrupt, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.

Mode: Host and Device

Resume/Remote Wakeup Detected Interrupt (WkUpInt)

Wakeup Interrupt during Suspend(L2) or LPM(L1) state.

- During Suspend(L2):

-- Device Mode: This interrupt is asserted only when Host Initiated Resume is detected on USB.

-- Host Mode: This interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB.

For more information, see 'Partial Power-Down and Clock Gating Programming Model' in the Programming Guide.

- During LPM(L1):

-- Device Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.

-- Host Mode: This interrupt is asserted for either Host Initiated Resume or Device Initiated Remote Wakeup on USB.

For more information, see 'LPM Entry and Exit Programming Model' in the Programming Guide.
Interrupt Mask Register This register works with the Interrupt Register (GINTSTS) to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the GINTSTS register bit corresponding to that interrupt is still set. Note: The fields of this register change depending on host or device mode.
Mode: Host and Device

Mode Mismatch Interrupt Mask (ModeMisMsk)

Mode: Host and Device

OTG Interrupt Mask (OTGIntMsk)

Mode: Host and Device

Start of (micro)Frame Mask (SofMsk)

Mode: Host and Device

Receive FIFO Non-Empty Mask (RxFLvlMsk)

Mode: Host and Device

Non-periodic TxFIFO Empty Mask (NPTxFEmpMsk)

Mode: Device only,

Global Non-periodic IN NAK Effective Mask (GINNakEffMsk)

Mode: Device only

Global OUT NAK Effective Mask (GOUTNakEffMsk)

Mode: Device only

Early Suspend Mask (ErlySuspMsk)

Mode: Device only

USB Suspend Mask (USBSuspMsk)

Mode: Device only

USB Reset Mask (USBRstMsk)

Mode: Device only

Enumeration Done Mask (EnumDoneMsk)

Mode: Device only

Isochronous OUT Packet Dropped Interrupt Mask (ISOOutDropMsk)

Mode: Device only

End of Periodic Frame Interrupt Mask (EOPFMsk)

Mode: Device only

Endpoint Mismatch Interrupt Mask (EPMisMsk)

Mode: Device only

IN Endpoints Interrupt Mask (IEPIntMsk)

Mode: Device only

OUT Endpoints Interrupt Mask (OEPIntMsk)

Incomplete Periodic Transfer Mask (incomplPMsk)

Mode: Host only

Incomplete Isochronous OUT Transfer Interrupt Mask (incompISOOUTMsk)

Mode: Device only

Mode: Device only

Data Fetch Suspended Mask (FetSuspMsk)

Mode: Device only

Reset detected Interrupt Mask (ResetDetMsk)

Mode: Host only

Host Port Interrupt Mask (PrtIntMsk)

Mode: Host only

Host Channels Interrupt Mask (HChIntMsk)

Mode: Host only

Periodic TxFIFO Empty Mask (PTxFEmpMsk)

Mode: Host and Device

Connector ID Status Change Mask (ConIDStsChngMsk)

Mode: Host and Device

Disconnect Detected Interrupt Mask (DisconnIntMsk)

Mode: Host and Device

Session Request/New Session Detected Interrupt Mask (SessReqIntMsk)

Mode: Host and Device

Resume/Remote Wakeup Detected Interrupt Mask (WkUpIntMsk)

The WakeUp bit is used for LPM state wake up in a way similar to that of wake up in suspend state.
Receive Status Debug Read Register A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status read when the receive FIFO is empty and returns a value of 32'h0000_0000. Note: - Use of these fields vary based on whether the core is functioning as a host or a device. - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.
Channel Number (ChNum)

Mode: Host only

Indicates the channel number to which the current received packet belongs.

Endpoint Number (EPNum)

Mode: Device only

Indicates the endpoint number to which the current received packet belongs.

Byte Count (BCnt)


In host mode, indicates the byte count of the received IN data packet.


In device mode, indicates the byte count of the received data packet.

Data PID (DPID)


In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.

- 2'b00: DATA0

- 2'b10: DATA1

- 2'b01: DATA2

- 2'b11: MDATA

Reset: 2'h0

Packet Status (PktSts) indicates the status of the received packet.

In host mode,

- 4'b0010: IN data packet received

- 4'b0011: IN transfer completed (triggers an interrupt)

- 4'b0101: Data toggle error (triggers an interrupt)

- 4'b0111: Channel halted (triggers an interrupt)

- Others: Reserved

Reset:4'b0


In device mode,

- 4'b0001: Global OUT NAK (triggers an interrupt)

- 4'b0010: OUT data packet received

- 4'b0011: OUT transfer completed (triggers an interrupt)

- 4'b0100: SETUP transaction completed (triggers an interrupt)

- 4'b0110: SETUP data packet received

- Others: Reserved

Reset:4'h0

Mode: Device only

Frame Number (FN)

This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.
Receive Status Read/Pop Register A read to the Receive Status Read and Pop register returns the contents of the top of the Receive FIFO and additionally pops the top data entry out of the RxFIFO. The receive status contents must be interpreted differently in Host and Device modes. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 32'h0000_0000. The application must only pop the Receive Status FIFO when the Receive FIFO Non-Empty bit of the Core Interrupt register (GINTSTS.RxFLvl) is asserted. Note: - Use of these fields vary based on whether the core is functioning as a host or a device. - Do not read this register's reset value before configuring the core because the read value is 'X' in the simulation.
Channel Number (ChNum)

Mode: Host only

Indicates the channel number to which the current received packet belongs.

Endpoint Number (EPNum)

Mode: Device only

Indicates the endpoint number to which the current received packet belongs.

Byte Count (BCnt)


In host mode, indicates the byte count of the received IN data packet.


In device mode, indicates the byte count of the received data packet.

Data PID (DPID)


In host mode, indicates the Data PID of the received packet. In device mode, indicates the Data PID of the received OUT data packet.

- 2'b00: DATA0

- 2'b10: DATA1

- 2'b01: DATA2

- 2'b11: MDATA

Reset: 2'h0

Packet Status (PktSts) indicates the status of the received packet.

In host mode,

- 4'b0010: IN data packet received

- 4'b0011: IN transfer completed (triggers an interrupt)

- 4'b0101: Data toggle error (triggers an interrupt)

- 4'b0111: Channel halted (triggers an interrupt)

- Others: Reserved

Reset:4'b0


In device mode,

- 4'b0001: Global OUT NAK (triggers an interrupt)

- 4'b0010: OUT data packet received

- 4'b0011: OUT transfer completed (triggers an interrupt)

- 4'b0100: SETUP transaction completed (triggers an interrupt)

- 4'b0110: SETUP data packet received

- Others: Reserved

Reset:4'h0

Mode: Device only

Frame Number (FN)

This is the least significant 4 bits of the (micro)Frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported.
Receive FIFO Size Register The application can program the RAM size that must be allocated to the RxFIFO.
Mode: Host and Device

RxFIFO Depth (RxFDep)

This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth during configuration.

If Enable Dynamic FIFO Sizing is selected in coreConsultant, these flops are optimized, and reads return the power-on value.

If Enable Dynamic FIFO Sizing is selected in coreConsultant, you can write a new value in this field. Programmed values must not exceed the power-on value.
Non-periodic Transmit FIFO Size Register The application can program the RAM size and the memory start address for the Non-periodic TxFIFO Note: The fields of this register change depending on host or device mode.
Non-periodic Transmit RAM Start Address (NPTxFStAddr)

For host mode, this field is always valid.

This field contains the memory start address for Non-periodic Transmit FIFO RAM.

- This field is determined during coreConsultant configuration by "Enable Dynamic FIFO Sizing?" (OTG_DFIFO_DYNAMIC):OTG_DFIFO_DYNAMIC = 0

These flops are optimized, and reads return the power-on value.

- OTG_DFIFO_DYNAMIC = 1 The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.

Programmed values must not exceed the power-on value set in coreConsultant.

The power-on reset value of this field is specified during coreConsultant configuration by Largest Rx Data FIFO Depth (parameter OTG_RX_DFIFO_DEPTH).

Mode: Host only

Non-periodic TxFIFO Depth (NPTxFDep)

For host mode, this field is always valid.

For device mode, this field is valid only when OTG_EN_DED_TX_FIFO=0.

This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

This attribute of field is determined during coreConsultant configuration by "Enable Dynamic FIFO Sizing?" (OTG_DFIFO_DYNAMIC):

- OTG_DFIFO_DYNAMIC = 0: These flops are optimized, and reads return the power-on value.

- OTG_DFIFO_DYNAMIC = 1: The application can write a new value in this field. Programmed values must not exceed the power-on value set in coreConsultant.

The power-on reset value of this field is specified during coreConsultant configuration as Largest IN Endpoint FIFO 0 Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_0).
Non-periodic Transmit FIFO/Queue Status Register In Device mode, this register is valid only in Shared FIFO operation. This read-only register contains the free space information for the Non-periodic TxFIFO and the Non-periodic Transmit Request Queue.
Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)

Indicates the amount of free space available in the Non-periodic TxFIFO.

Values are in terms of 32-bit words.

- 16'h0: Non-periodic TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 <= n <= 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved

Reset: Configurable

Non-periodic Transmit Request Queue Space Available (NPTxQSpcAvail)

Indicates the amount of free space available in the Non-periodic Transmit Request Queue. This queue holds both IN and OUT requests in Host mode. Device mode has only IN requests.

- 8'h0: Non-periodic Transmit Request Queue is full

- 8'h1: 1 location available

- 8'h2: 2 locations available

- n: n locations available (0 <= n <= 8)

- Others: Reserved

Reset: Configurable

Top of the Non-periodic Transmit Request Queue (NPTxQTop)

Entry in the Non-periodic Tx Request Queue that is currently being processed by the MAC.


- Bits [30:27]: Channel/endpoint number

- Bits [26:25]:

- 2'b00: IN/OUT token

-- 2'b01: Zero-length transmit packet (device IN/host OUT)

-- 2'b10: PING/CSPLIT token

-- 2'b11: Channel halt command

- Bit [24]: Terminate (last Entry for selected channel/endpoint)

Reset: 7'h0
General Purpose Input/Output Register The application can use this register for general purpose input/output ports or for debugging.

General Purpose Input (GPI)


This field's read value reflects the gp_i[15:0] core input value.


General Purpose Output (GPO)


This field is driven as an output from the core, gp_o[15:0]. The

application can program this field to determine the

corresponding value on the gp_o[15:0] output.
User ID Register This is a read/write register containing the User ID. It is implemented only if Remove Optional Features? was deselected during coreConsultant configuration (parameter OTG_RM_OPT_FEATURES = 0). The power-on value for this register is specified as the Power-on Value of User ID Register User Identification Register during coreConsultant configuration (parameter OTG_USERID). This register can be used in the following ways: - To store the version or revision of your system - To store hardware configurations that are outside the DWC_otg core - As a scratch register
User ID (UserID)

Application-programmable ID field.

Reset: Configurable
Synopsys ID Register This read-only register contains the release number of the core being used.
Release number of the controller being used currently.
User Hardware Configuration 1 Register This register contains the logical endpoint direction(s) selected using coreConsultant.
This 32-bit field uses two bits per

endpoint to determine the endpoint direction.


Endpoint

- Bits [31:30]: Endpoint 15 direction

- Bits [29:28]: Endpoint 14 direction

...

- Bits [3:2]: Endpoint 1 direction

- Bits[1:0]: Endpoint 0 direction (always BIDIR)

Direction

- 2'b00: BIDIR (IN and OUT) endpoint

- 2'b01: IN endpoint

- 2'b10: OUT endpoint

- 2'b11: Reserved

Note: This field is configured using the OTG_EP_DIR_1(n) parameter.
User Hardware Configuration 2 Register This register contains configuration options selected using coreConsultant.
Mode of Operation (OtgMode)

- 3'b000: HNP- and SRP-Capable OTG (Host & Device)

- 3'b001: SRP-Capable OTG (Host & Device)

- 3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device)

- 3'b011: SRP-Capable Device

- 3'b100: Non-OTG Device

- 3'b101: SRP-Capable Host

- 3'b110: Non-OTG Host

- Others: Reserved

Note: This field is configured using the OTG_MODE parameter.

Architecture (OtgArch)

- 2'b00: Slave-Only

- 2'b01: External DMA

- 2'b10: Internal DMA

- Others: Reserved

Note: This field is configured using the OTG_ARCHITECTURE parameter.

Point-to-Point (SingPnt)

- 1'b0: Multi-point application (hub and split support)

- 1'b1: Single-point application (no hub and split support)

Note: This field is configured using the OTG_SINGLE_POINT parameter.

High-Speed PHY Interface Type (HSPhyType)

- 2'b00: High-Speed interface not supported

- 2'b01: UTMI+

- 2'b10: ULPI

- 2'b11: UTMI+ and ULPI

Note: This field is configured using the OTG_HSPHY_INTERFACE parameter.

Full-Speed PHY Interface Type (FSPhyType)

- 2'b00: Full-speed interface not supported

- 2'b01: Dedicated full-speed interface

- 2'b10: FS pins shared with UTMI+ pins

- 2'b11: FS pins shared with ULPI pins

Note: This field is configured using the OTG_FSPHY_INTERFACE parameter.

Number of Device Endpoints (NumDevEps)


Indicates the number of device endpoints supported by the core in Device mode.


The range of this field is 0-15.


Note: This field is configured using the OTG_NUM_EPS parameter.

Number of Host Channels (NumHstChnl)

Indicates the number of host channels supported by the core in Host mode. The range of this field is 0-15: 0 specifies 1 channel, 15 specifies 16 channels.


Note: This field is configured using the OTG_NUM_HOST_CHAN parameter.

Periodic OUT Channels Supported in Host Mode (PerioSupport)

- 1'b0: No

- 1'b1: Yes

Note: This field is configured using the OTG_EN_PERIO_HOST parameter.

Dynamic FIFO Sizing Enabled (DynFifoSizing)

- 1'b0: No

- 1'b1: Yes

Note: This field is configured using the OTG_DFIFO_DYNAMIC parameter.

Multi Processor Interrupt Enabled (MultiProcIntrpt)

- 1'b0: No

- 1'b1: Yes

Note: This field is configured using the OTG_MULTI_PROC_INTRPT parameter.

Non-periodic Request Queue Depth (NPTxQDepth)

- 2'b00: 2

- 2'b01: 4

- 2'b10: 8

- Others: Reserved

Note: This field is configured using the OTG_NPERIO_TX_QUEUE_DEPTH parameter.

Host Mode Periodic Request Queue Depth (PTxQDepth)

- 2'b00: 2

- 2'b01: 4

- 2'b10: 8

- 2'b11:16

Note: This field is configured using the OTG_PERIO_TX_QUEUE_DEPTH parameter.

Device Mode IN Token Sequence Learning Queue Depth (TknQDepth)

Range: 0-30


Note: This field is configured using the OTG_TOKEN_QUEUE_DEPTH parameter.
User Hardware Configuration 3 Register
Width of Transfer Size Counters (XferSizeWidth)

- 4'b0000: 11 bits

- 4'b0001: 12 bits

...

- 4'b1000: 19 bits

- Others: Reserved

Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.

Width of Packet Size Counters (PktSizeWidth)

- 3'b000: 4 bits

- 3'b001: 5 bits

- 3'b010: 6 bits

- 3'b011: 7 bits

- 3'b100: 8 bits

- 3'b101: 9 bits

- 3'b110: 10 bits

- Others: Reserved

Note: This field is configured using the OTG_PACKET_COUNT_WIDTH parameter.

OTG Function Enabled (OtgEn)


The application uses this bit to indicate the OTG capabilities of the controller .

- 1'b0: Not OTG capable

- 1'b1: OTG Capable

Note: This field is configured using the OTG_MODE parameter.

I2C Selection (I2CIntSel)

- 1'b0: I2C Interface is not available on the controller.

- 1'b1: I2C Interface is available on the controller.

Note: This field is configured using the OTG_I2C_INTERFACE parameter.

Vendor Control Interface Support (VndctlSupt)


- 1'b0: Vendor Control Interface is not available on the core.

- 1'b1: Vendor Control Interface is available.

Note: This field is configured using the OTG_VENDOR_CTL_INTERFACE parameter.

Optional Features Removed (OptFeature)

Indicates whether the User ID register, GPIO interface ports, and SOF toggle and counter ports were removed for gate count optimization by enabling Remove Optional Features.

- 1'b0: No

- 1'b1: Yes

Note: This field is configured using the OTG_RM_OPT_FEATURES parameter.

Reset Style for Clocked always Blocks in RTL (RstType)

- 1'b0: Asynchronous reset is used in the controller

- 1'b1: Synchronous reset is used in the controller

Note: This field is configured using the OTG_SYNC_RESET_TYPE parameter.

This bit indicates whether ADP logic is present within or external to the controller

- 0: No ADP logic present with the controller

- 1: ADP logic is present along with the controller.

HSIC mode specified for Mode of Operation

Value Range: 0 - 1

- 1: HSIC-capable with shared UTMI PHY interface

- 0: Non-HSIC-capable

This bit indicates the controller support for Battery Charger.

- 0 - No Battery Charger Support

- 1 - Battery Charger support present


LPM mode specified for Mode of Operation.

DFIFO Depth (DfifoDepth - EP_LOC_CNT)


This value is in terms of 32-bit words.

- Minimum value is 32

- Maximum value is 32,768

Note: This field is configured using the OTG_DFIFO_DEPTH parameter. For more information on EP_LOC_CNT, see the "Endpoint Information Controller (EPINFO_CTL)" section.
User Hardware Configuration 4 Register Note Bit [31] is available only when Scatter/Gather DMA mode is enabled. When Scatter/Gather DMA mode is disabled, this field is reserved.
Number of Device Mode Periodic IN Endpoints (NumDevPerioEps)


Range: 0-15

Enable Partial Power Down (PartialPwrDn)

- 1'b0: Partial Power Down Not Enabled

- 1'b1: Partial Power Down Enabled

Minimum AHB Frequency Less Than 60 MHz (AhbFreq)

- 1'b0: No

- 1'b1: Yes

Enable Hibernation (Hibernation)

- 1'b0: Hibernation feature not enabled

- 1'b1: Hibernation feature enabled

Enable Hibernation

- 1'b0: Extended Hibernation feature not enabled

- 1'b1: Extended Hibernation feature enabled

Active Clock Gating Support


This bit indicates that the controller supports the Dynamic (Switching) Power Reduction during periods

when there is no USB and AHB Traffic.

- 1'b0: Active Clock Gating is not enabled.

- 1'b1: Active Clock Gating Enabled.


Enhanced LPM Support (EnhancedLPMSupt)


This bit indicates that the controller supports the following behavior:

L1 Entry Behavior based on FIFO Status

- TX FIFO

- Accept L1 Request even if ISOC OUT TX FIFO is not empty.

- Reject L1 Request if Non-Periodic TX FIFO is not empty.

- Ensure application can flush the TX FIFO while the Controller is in L1.

- RX FIFO

- Accept L1 Request even if RX FIFO (common to Periodic and Non-Periodic) is not empty.

- Accept L1 Request but delay SLEEPM assertion until RX SINK Buffer is empty.


Prevent L1 Entry if a Control Transfer is in progress on any Control Endpoint.

Ability to Flush TxFIFO even if PHY Clock is gated.




UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width

(PhyDataWidth)<vr>When a ULPI PHY is used, an internal wrapper converts ULPI to

UTMI+.

- 2'b00: 8 bits

- 2'b01: 16 bits

- 2'b10: 8/16 bits, software selectable

- Others: Reserved

Number of Device Mode Control Endpoints in Addition to

Endpoint 0 (NumCtlEps)

Range: 0-15

IDDIG Filter Enable (IddgFltr)

- 1'b0: No filter

- 1'b1: Filter

VBUS Valid Filter Enabled (VBusValidFltr)

- 1'b0: No filter

- 1'b1: Filter

a_valid Filter Enabled (AValidFltr)

- 1'b0: No filter

- 1'b1: Filter

b_valid Filter Enabled (BValidFltr)

- 1'b0: No filter

- 1'b1: Filter

session_end Filter Enabled (SessEndFltr)

- 1'b0: No filter

- 1'b1: Filter

Enable Dedicated Transmit FIFO for device IN Endpoints

(DedFifoMode)

- 1'b0 : Dedicated Transmit FIFO Operation not enabled.

- 1'b1 : Dedicated Transmit FIFO Operation enabled.

Number of Device Mode IN Endpoints Including Control Endpoints (INEps)

- 0: 1 IN Endpoint

- 1: 2 IN Endpoints

....

- 15: 16 IN Endpoints


Scatter/Gather DMA configuration

- 1'b0: Non-Scatter/Gather DMA configuration

- 1'b1: Scatter/Gather DMA configuration

Scatter/Gather DMA configuration

- 1'b0: Non Dynamic configuration

- 1'b1: Dynamic configuration

Note: This field is configured using the OTG_EN_DESC_DMA parameter.
Global Power Down register This is the external Hibernation control register. This register is active only during hibernation and ADP. The application can get the status of the wakeup_logic and control it through this register.
PMU Interrupt Select (PMUIntSel)


A write to this bit with 1'b1 enables the PMU to generate interrupts to the application. During this state all interrupts from the DWC_otg_core module are blocked to the application.


Note: This bit must be set to 1'b1 before the core is put into hibernation.

- 1'b0: Internal DWC_otg_core interrupt is selected

- 1'b1: External DWC_otg_pmu interrupt is selected

Note: This bit must not be written to during normal mode of operation.

PMU Active (PMUActv)


This is bit is to enable or disable the PMU logic.

- 1'b0: Disable PMU module

- 1'b1: Enable PMU module

Note: This bit must not be written to during normal mode of operation.


Power Down Clamp (PwrDnClmp)


The application must program this bit to enable or disable the clamps to all the outputs of the core module to prevent the corruption of other active logic.

- 1'b0: Disable PMU power clamp

- 1'b1: Enable PMU power clamp

Power Down ResetN (PwrDnRst_n)


The application must program this bit to reset the core during the Hibernation exit process or during ADP when powering up the core (in case the core was powered off during ADP process).

- 1'b1: The controller is in normal operation

- 1'b0: reset the controller

Note: This bit must not be written to during normal mode of operation.

Power Down Switch (PwrDnSwtch)


This bit indicates to the controller whether the VDD switch is in ON/OFF state.

- 1'b0: The controller is in ON state

- 1'b1: The controller is in OFF state

Note: This bit must not be written to during normal mode of operation.

DisableVBUS


Host Mode:


The application should program this bit if HPRT0.PrtPwr was programmed to 0 before entering Hibernation. This is to indicate PMU whether session was ended before entering Hibernation.

- 1'b0: HPRT0.PrtPwr was not programed to 0.

- 1'b1: HPRT0.PrtPwr was programmed to 0.

Device Mode:


The application must program this bit to inform the PMU whether the bvalid valid signal is high (session valid) or low (session end) whenever the core is switched off.

- 1'b0: bvalid signal is High (Session Valid)

- 1'b1: bvalid signal is Low (Session End)

This bit is valid only when GPWRDN.PMUActv is 1.


SRPDetect


This field indicates that SRP has been detected by the PMU. This field generates an interrupt. After detecting SRP during hibernation the application should not restore the core. The application should get into the initialization process.

- 1'b0: SRP not detected

- 1'b1: SRP detected

SRPDetectMsk


Mask for SRPDetect Interrupt

Status Change Interrupt (StsChngInt)


This field indicates a status change in either the IDDIG or BSessVld signal.

- 1'b0: No Status change

- 1'b1: Status change detected

After receiving this interrupt the application should read the GPWRDN register and interpret the change in IDDIG or BSesVld with respect to the previous value stored by the application.


Note: When Battery Charger is enabled and the ULPI interface is used, if StsChngInt is received and the application reads GPWRDN register and determines that it is because of a change in the value of IDDIG, then StsChngInt may be generated once again within the next few clock cycles.


This occurs because of an ambiguity in the implementation of Battery Charger Support over the ULPI interface. After receiving the StsChngInt for the second time the application can once again read the GPWRDN register. However, this time the valueIDDIG (or BSesVld) will not have changed. The application then processes the second interrupt but no further action will be required as a result.

StsChngIntMsk


Mask for StsChng Interrupt

LineState


This field indicates the current linestate on USB as seen by the PMU module.

- 2'b00: DM = 0, DP = 0.

- 2'b01: DM = 0, DP = 1.

- 2'b10: DM = 1, DP = 0.

- 2'b11: Not-defined.

This bit is valid only when GPWRDN.PMUActv is 1.

This bit indicates the status of the signal IDDIG. The application must read this bit after receiving GPWRDN.StsChngInt and decode based on the previous value stored by the application.


Indicates the current mode.

- 1'b0: Host mode

- 1'b1: Device mode

This bit is valid only when GPWRDN.PMUActv is 1.

B Session Valid (BSessVld)


This field reflects the B session valid status signal from the PHY.

- 1'b0: B-Valid is 0.

- 1'b1: B-Valid is 1.

This bit is valid only when GPWRDN.PMUActv is 1.

ADP Interrupt (ADPInt)


This bit is set whenever there is a ADP event.
Global DFIFO Configuration Register
GDFIFOCfg


This field is for dynamic programming of the DFIFO Size. This value takes effect only when the application programs a non zero value to this register. The value programmed must conform to the guidelines described in 'FIFO RAM Allocation'. The core does not have any corrective logic if the FIFO sizes are programmed incorrectly.

EPInfoBaseAddr


This field provides the start address of the EP info controller.

ADP Timer, Control and Status Register This register is maintained in the PMU module. These register values are used for deciding the timing values by the ADP controller. This register is available only if the ADP controller logic is present within the HS OTG Controller. If the ADP logic is external to the HS OTG Controller, this register is reserved and the register contents are zero. For more information about ADP controller options, see "ADP Programming Flow when ADP Controller Logic is Supplied with the Core " in the Programming Guide.
Probe Discharge (PrbDschg)


These bits set the times for TADP_DSCHG. These bits are defined as follows:

- 2'b00: 4 msec (Scaledown 2 32Khz clock cycles)

- 2'b01: 8 msec (Scaledown 4 32Khz clock cycles)

- 2'b10: 16 msec (Scaledown 8 32Khz clock cycles)

- 2'b11: 32 msec (Scaledown 16 32Khz clock cycles)

Probe Delta (PrbDelta)


These bits set the resolution for RTIM value. The bits are defined in units of 32 kHz clock cycles as follows:

- 2'b00: 1 cycles

- 2'b01: 2 cycles

- 2'b10: 3 cycles

- 2'b11: 4 cycles

For example, if this value is chosen to 2'b01, it means that RTIM increments for every three 32Khz clock cycles.

Probe Period (PrbPer)


These bits sets the TadpPrd as follows:

- 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec)

- 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)

- 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)

- 2'b11 - Reserved

(PrbPer is also scaledown

- prb_per== 2'b00 => 400 ADP clocks

- prb_per== 2'b01 => 600 ADP clocks

- prb_per== 2'b10 => 800 ADP clocks

- prb_per==2'b11 => 1000 ADP clocks)

RAMP TIME (RTIM)


These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. The bits are defined in units of 32 kHz clock cycles as follows:

- 0x000 - 1 cycles

- 0x001 - 2 cycles

- 0x002 - 3 cycles, and so on till

- 0x7FF - 2048 cycles

A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.

(Note for scaledown ramp_timeout =

- prb_delta == 2'b00 => 200 cycles.

- prb_delta == 2'b01 => 100 cycles.

- prb_delta == 2'b01 => 50 cycles.

- prb_delta == 2'b01 => 25 cycles.)

Enable Probe (EnaPrb)


When programmed to 1'b1, the core performs a probe operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).

Enable Sense (EnaSns)


When programmed to 1'b1, the core performs a sense operation. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).


ADP Reset (ADPRes)


When set, ADP controller is reset. This bit is auto-cleared after the reset procedure is complete in ADP controller. This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).

ADP Enable (ADPEn)


When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns.

This bit is valid only if OTG_Ver = 1'b1 (GOTGCTL[20]).

ADP Probe Interrupt (AdpPrbInt)


When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VadpPrb is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).


ADP Sense Interrupt (AdpSnsInt)


When this bit is set, it means that the VBUS voltage is greater than VadpSns value or VadpSns is reached.This bit is valid only if OTGVer = 1'b1 (GOTGCTL[20]).


ADP Timeout Interrupt (AdpToutInt)


This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.

ADP Probe Interrupt (AdpPrbInt)


This bit is relevant only for an ADP probe. When this bit is set, it means that the ramp time has completed (GADPCTL.RTIM has reached its terminal value of 0x7FF). This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTGVer = 1'b1.


ADP Sense Interrupt Mask (AdpSnsIntMsk)


When this bit is set, it unmasks the interrupt due to AdpSnsInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).


ADP Timeout Interrupt Mask (AdpToutMsk)


When this bit is set, it unmasks the interrupt because of AdpTmouInt. This bit is valid only if OTG_Ver = 1'b1(GOTGCTL[20]).

Access Request (AR)

- 2'b00 Read/Write Valid (updated by the core)

- 2'b01 Read

- 2'b10 Write

- 2'b11 - Reserved
Host Periodic Transmit FIFO Size Register This register holds the size and the memory start address of the Periodic TxFIFO. Note: Read the reset value of this register only after the following conditions: - If IDDIG_FILTER is disabled, read only after PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.
Host Periodic TxFIFO Start Address (PTxFStAddr)


The power-on reset value of this register is the sum of the Largest Rx Data FIFO Depth and Largest Non-periodic Tx Data FIFO Depth.These parameters are:


In shared FIFO operation:

- OTG_RX_DFIFO_DEPTH + OTG_TX_NPERIO_DFIFO_DEPTH


In dedicated FIFO mode:

- OTG_RX_DFIFO_DEPTH + OTG_TX_HNPERIO_DFIFO_DEPTH If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value. If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field.


Programmed values must not exceed the power-on value set in coreConsultant.

Host Periodic TxFIFO Depth (PTxFSize)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest Host Mode Periodic Tx Data FIFO Depth.

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field.

Programmed values must not exceed the power-on value set in coreConsultant.
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Device IN Endpoint Transmit FIFO Size Register $i This register is valid only in dedicated FIFO mode (OTG_EN_DED_TX_FIFO=1). It holds the size and memory start address of IN endpoint TxFIFOs implemented in Device mode. Each FIFO holds the data for one IN endpoint. This register is repeated for instantiated IN endpoint FIFOs 1 to 15. For IN endpoint FIFO 0, use GNPTXFSIZ register for programming the size and memory start address.
IN Endpoint FIFOn Transmit RAM Start Address (INEPnTxFStAddr)


This field contains the memory start address for IN endpoint Transmit FIFOn (0<n< = 15).

The power-on reset value of this register is specified as the Largest Rx Data FIFO Depth. The power-on reset value of this register is calculated according to the following formula: OTG_RX_DFIFO_DEPTH + SUM of OTG_TX_DINEP_DFIFO_DEPTH_'i' (where x = 0 to n 1) If at POR the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C 65536). Example: If start address of IN endpoint FIFO 1 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 and start address of IN endpoint FIFO 2 is OTG_RX_DFIFO_DEPTH + OTG_TX_DINEP_DFIFO_DEPTH_ 0 + OTG_TX_DINEP_DFIFO_DEPTH_ 1.

- If Enable Dynamic FIFO Sizing is deselected in coreConsultant (OTG_DFIFO_DYNAMIC = 0), this field is read-only and read value is the power-on reset value.

- If Enable Dynamic FIFO Sizing is selected in coreConsultant (OTG_DFIFO_DYNAMIC = 1), and you have calculated or programmed a new value for RxFIFO depth or TX FIFO depths, you can program their values according to the above formula. Programmed values must not exceed the power-on value set in coreConsultant.

IN Endpoint TxFIFO Depth (INEPnTxFDep)


This value is in terms of 32-bit words.

- Minimum value is 16

- Maximum value is 32,768

The power-on reset value of this register is specified as the Largest IN Endpoint FIFO number Depth (parameter OTG_TX_DINEP_DFIFO_DEPTH_n) during coreConsultant configuration (0 < i <= 15).

- If Enable Dynamic FIFO Sizing? was deselected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 0), these flops are optimized, and reads return the power-on value.

- If Enable Dynamic FIFO Sizing? was selected in coreConsultant (parameter OTG_DFIFO_DYNAMIC = 1), you can write a new value in this field. .

Programmed values must not exceed the power-on value
Host Configuration Register
FS/LS PHY Clock Select (FSLSPclkSel)


When the core is in FS Host mode

- 2'b00: PHY clock is running at 30/60 MHz

- 2'b01: PHY clock is running at 48 MHz

- Others: Reserved

When the core is in LS Host mode

- 2'b00: PHY clock is running at 30/60 MHz. When the UTMI+/ULPI PHY Low Power mode is not selected, use 30/60 MHz.

- 2'b01: PHY clock is running at 48 MHz. When the UTMI+ PHY Low Power mode is selected, use 48MHz If the PHY supplies a 48 MHz clock during LS mode.

- 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode, use 6 MHz when the UTMI+ PHY Low Power mode is selected and the PHY supplies a 6 MHz clock during LS mode. If you select a 6 MHz clock during LS mode, you must do a soft reset.

- 2'b11: Reserved

Notes:

- When Core in FS mode, the internal and external clocks have the same frequency.

- When Core in LS mode,

-- If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency

-- If FSLSPclkSel = 2'b10: Internal clock is the divided by eight version of external 48 MHz clock


FS- and LS-Only Support (FSLSSupp)


The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core

enumerate as a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial

programming.

- 1'b0: HS/FS/LS, based on the maximum speed supported by the connected device

- 1'b1: FS/LS-only, even If the connected device can support HS

Enable 32 KHz Suspend mode (Ena32KHzS)


This bit can be set only in FS PHY interface is selected.

Else, this bit needs to be set to zero.

When FS PHY interface is chosen and this bit is set,

the core expects that the PHY clock during Suspend is switched

from 48 MHz to 32 KHz.

Resume Validation Period (ResValid)


This field is effective only when HCFG.Ena32KHzS is set.

It will control the resume period when the core resumes from suspend.

The core counts for 'ResValid' number of clock cycles to detect a

valid resume when this is set.

Enable Scatter/gather DMA in Host mode (DescDMA)


When the Scatter/Gather DMA option selected during configuration of the RTL, the application can set this bit during initialization

to enable the Scatter/Gather DMA operation.


Note: This bit must be modified only once after a reset.


The following combinations are available for programming:

- GAHBCFG.DMAEn=0,HCFG.DescDMA=0 => Slave mode

- GAHBCFG.DMAEn=0,HCFG.DescDMA=1 => Invalid

- GAHBCFG.DMAEn=1,HCFG.DescDMA=0 => Buffered DMA mode

- GAHBCFG.DMAEn=1,HCFG.DescDMA=1 => Scatter/Gather DMA mode

Frame List Entries(FrListEn)


The value in the register specifies the number of entries in the Frame list.

This field is valid only in Scatter/Gather DMA mode.

- 2'b00: 8 Entries

- 2'b01: 16 Entries

- 2'b10: 32 Entries

- 2'b11: 64 Entries

Enable Periodic Scheduling (PerSchedEna):


Applicable in host DDMA mode only.

Enables periodic scheduling within the core. Initially, the bit is reset.

The core will not process any periodic channels.


As soon as this bit is set,

the core will get ready to start scheduling periodic channels and

sets HCFG.PerSchedStat. The setting of HCFG.PerSchedStat indicates the core

has enabled periodic scheduling. Once HCFG.PerSchedEna is set,

the application is not supposed to again reset the bit unless HCFG.PerSchedStat

is set.


As soon as this bit is reset, the core will get ready to

stop scheduling periodic channels and resets HCFG.PerSchedStat.

Mode Change Ready Timer Enable (ModeChTimEn)


This bit is used to enable/disable the Host core to wait 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00

after Suspend or LPM.

- 1'b0 : The Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to the change the opmode from 2'b10 to 2'b00

- 1'b1 : The Host core waits only for a linstate of SE0 at the end of resume to change the opmode from 2'b10 to 2'b00.
Host Frame Interval Register
Frame Interval (FrInt)


The value that the application programs to this field specifies

the interval between two consecutive SOFs (FS) or micro-

SOFs (HS) or Keep-Alive tokens (HS). This field contains the

number of PHY clocks that constitute the required frame

interval. The Default value set in this field is for FS operation

when the PHY clock frequency is 60 MHz. The application can

write a value to this register only after the Port Enable bit of the

Host Port Control and Status register (HPRT.PrtEnaPort) has

been Set. If no value is programmed, the core calculates the

value based on the PHY clock specified in the FS/LS PHY

Clock Select field of the Host Configuration register

(HCFG.FSLSPclkSel). Do not change the value of this field

after the initial configuration.

- 125 s * (PHY clock frequency for HS)

- 1 ms * (PHY clock frequency for FS/LS)

Reload Control (HFIRRldCtrl)


This bit allows dynamic reloading of the HFIR register during run time.

- 1'b0 : The HFIR cannot be reloaded dynamically

- 1'b1: the HFIR can be dynamically reloaded during runtime.

This bit needs to be programmed during initial configuration and its value should not be changed during runtime.

Host Frame Number/Frame Time Remaining Register This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current (micro)frame. Note: Read the reset value of this register only after the following conditions: - If IDDIG_FILTER is disabled, read only when the PHY clock is stable. - If IDDIG_FILTER is enabled, read only after the filter timer expires.
Frame Number (FrNum)


This field increments when a new SOF is transmitted on the

USB, and is reset to 0 when it reaches 16'h3FFF.


Frame Time Remaining (FrRem)


Indicates the amount of time remaining in the current

microframe (HS) or Frame (FS/LS), in terms of PHY clocks. This

field decrements on each PHY clock. When it reaches zero, this

field is reloaded with the value in the Frame Interval register and

a new SOF is transmitted on the USB.
Host Periodic Transmit FIFO/Queue Status Register
Periodic Transmit Data FIFO Space Available (PTxFSpcAvail)


Indicates the number of free locations available to be written to in the Periodic TxFIFO.


Values are in terms of 32-bit words

- 16'h0 : Periodic TxFIFO is full

- 16'h1 : 1 word available

- 16'h2 : 2 words available

- 16'hn : n words available (where 0 n 32,768)

- 16'h8000 : 32,768 words

- Others : Reserved

Periodic Transmit Request Queue Space Available (PTxQSpcAvail)


Indicates the number of free locations available to be written in the Periodic Transmit Request Queue. This queue holds both IN and OUT requests.

- 8'h0: Periodic Transmit Request Queue is full

- 8'h1: 1 location available

- 8'h2: 2 locations available

- n: n locations available (0 <= n <= 16)

- Others: Reserved

Top of the Periodic Transmit Request Queue (PTxQTop)


This indicates the Entry in the Periodic Tx Request Queue that is

currently being processes by the MAC.


This register is used for debugging.

- Bit [31]: Odd/Even (micro)Frame

-- 1'b0: send in even (micro)Frame

-- 1'b1: send in odd (micro)Frame

- Bits [30:27]: Channel/endpoint number

- Bits [26:25]: Type

-- 2'b00: IN/OUT

-- 2'b01: Zero-length packet

-- 2'b10: CSPLIT

-- 2'b11: Disable channel command

- Bit [24]: Terminate (last Entry for the selected channel/endpoint)
Host All Channels Interrupt Register When a significant event occurs on a channel, the Host All Channels Interrupt register interrupts the application using the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt). This is shown in the "Interrupt Hierarchy" figure in the databook. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Host Channel-n Interrupt register.

Channel Interrupt for channel no.
Host All Channels Interrupt Mask Register The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
Channel Interrupt Mask (HAINTMsk)

One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
Host Frame List Base Address Register This register is present only in case of Scatter/Gather DMA. It is implemented as flops. This register holds the starting address of the Frame list information.
The starting address of the Frame list.

This register is used only for Isochronous and Interrupt Channels.
Host Port Control and Status Register This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in the "Interrupt Hierarchy" figure in the databook. The R_SS_WC bits in this register can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt). On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt. For the R_SS_WC bits, the application must write a 1 to the bit to clear the interrupt.
Port Connect Status (PrtConnSts)

- 0: No device is attached to the port.

- 1: A device is attached to the port.

Port Connect Detected (PrtConnDet)


The core sets this bit when a device connection is detected

to trigger an interrupt to the application using the Host Port

Interrupt bit of the Core Interrupt register (GINTSTS.PrtInt).This bit can be set only by the core and the application should write 1 to clear it.The application must write a 1 to this bit to clear the

interrupt.

Port Enable (PrtEna)


A port is enabled only by the core after a reset sequence,

and is disabled by an overcurrent condition, a disconnect

condition, or by the application clearing this bit. The

application cannot Set this bit by a register write. It can only

clear it to disable the port by writing 1. This bit does not trigger any

interrupt to the application.

- 1'b0: Port disabled

- 1'b1: Port enabled

Port Enable/Disable Change (PrtEnChng)


The core sets this bit when the status of the Port Enable bit [2] of this register changes.This bit can be set only by the core and the application should write 1 to clear it.

Port Overcurrent Active (PrtOvrCurrAct)


Indicates the overcurrent condition of the port.

- 1'b0: No overcurrent condition

- 1'b1: Overcurrent condition

Port Overcurrent Change (PrtOvrCurrChng)


The core sets this bit when the status of the Port Overcurrent Active bit (bit 4) in this register changes.This bit can be set only by the core and the application should write 1 to clear it

Port Resume (PrtRes)


The application sets this bit to drive resume signaling on the

port. The core continues to drive the resume signal until the

application clears this bit.


If the core detects a USB remote wakeup sequence, as

indicated by the Port Resume/Remote Wakeup Detected

Interrupt bit of the Core Interrupt register

(GINTSTS.WkUpInt), the core starts driving resume

signaling without application intervention and clears this bit

when it detects a disconnect condition. The read value of

this bit indicates whether the core is currently driving

resume signaling.

- 1'b0: No resume driven

- 1'b1: Resume driven

When LPM is enabled, In L1 state the behavior of this bit is as follows:

The application sets this bit to drive resume signaling on the port.

The core continues to drive the resume signal until a pre-determined time

specified in GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote

wakeup sequence, as indicated by the Port L1Resume/Remote L1Wakeup Detected

Interrupt bit of the Core Interrupt register (GINTSTS.L1WkUpInt),

the core starts driving resume signaling without application intervention

and clears this bit at the end of resume.This bit can be set by both core or application

and also cleared by core or application. This bit is cleared by the core even if there is

no device connected to the Host.

Port Suspend (PrtSusp)


The application sets this bit to put this port in Suspend

mode. The core only stops sending SOFs when this is Set.

To stop the PHY clock, the application must Set the Port

Clock Stop bit, which asserts the suspend input pin of the

PHY.


The read value of this bit reflects the current suspend status

of the port. This bit is cleared by the core after a remote

wakeup signal is detected or the application sets the Port

Reset bit or Port Resume bit in this register or the

Resume/Remote Wakeup Detected Interrupt bit or

Disconnect Detected Interrupt bit in the Core Interrupt

register (GINTSTS.WkUpInt or GINTSTS.DisconnInt,

respectively).This bit is cleared by the core even if there is

no device connected to the Host.

- 1'b0: Port not in Suspend mode

- 1'b1: Port in Suspend mode

Port Reset (PrtRst)


When the application sets this bit, a reset sequence is

started on this port. The application must time the reset

period and clear this bit after the reset sequence is

complete.

- 1'b0: Port not in reset

- 1'b1: Port in reset

The application must leave this bit set for at least a

minimum duration mentioned below to start a reset on the

port. The application can leave it set for another 10 ms in

addition to the required minimum duration, before clearing

the bit, even though there is no maximum limit Set by the

USB standard.This bit is cleared by the core even if there is

no device connected to the Host.

- High speed: 50 ms

- Full speed/Low speed: 10 ms

Port Line Status (PrtLnSts)


Indicates the current logic level USB data lines

- Bit [10]: Logic level of D+

- Bit [11]: Logic level of D-

Port Power (PrtPwr)


The application uses this field to control power to this port (write 1'b1 to set to 1'b1

and write 1'b0 to set to 1'b0), and the core can clear this bit on an over current

condition.

- 1'b0: Power off

- 1'b1: Power on


Note: This bit is interface independent. The application needs to program this bit for all interfaces as described in the host programming flow in the Programming Guide.

Port Test Control (PrtTstCtl)


The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port.

- 4'b0000: Test mode disabled

- 4'b0001: Test_J mode

- 4'b0010: Test_K mode

- 4'b0011: Test_SE0_NAK mode

- 4'b0100: Test_Packet mode

- 4'b0101: Test_Force_Enable

- Others: Reserved


To move the DWC_otg controller to test mode, you must set this field. Complete the following steps to move the DWC_otg core to test mode:

- 1. Power on the core.

- 2. Load the DWC_otg driver.

- 3. Connect an HS device and enumerate to HS mode.

- 4. Access the HPRT register to send test packets.

- 5. Remove the device and connect to fixture (OPT) port. The DWC_otg host core continues sending out test packets.

- 6. Test the eye diagram.

Port Speed (PrtSpd)


Indicates the speed of the device attached to this port.

- 2'b00: High speed

- 2'b01: Full speed

- 2'b10: Low speed

- 2'b11: Reserved
Host Channel 0 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 0 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 0 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 1 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 1 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 1 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 2 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 2 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 2 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 3 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 3 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 3 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 4 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 4 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 4 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 5 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 5 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 5 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 6 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 6 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 6 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 7 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 7 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 7 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 8 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 8 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 8 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 9 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 9 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 9 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 10 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 10 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 10 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 11 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 11 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 11 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 12 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 12 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 12 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 13 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 13 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 13 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 14 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 14 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 14 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Host Channel 15 Characteristics Register
Maximum Packet Size (MPS)


Indicates the maximum packet size of the associated endpoint.

Endpoint Number (EPNum)


Indicates the endpoint number on the device serving as the data source or sink.

Endpoint Direction (EPDir)


Indicates whether the transaction is IN or OUT.

- 1'b0: OUT

- 1'b1: IN

Low-Speed Device (LSpdDev)


This field is Set by the application to indicate that this channel is communicating to a low-speed device.


The application must program this bit when a low speed device is connected to the host through an FS HUB. The DWC_otg Host core uses this field to drive the XCVR_SELECT signal to 2'b11 while communicating to the LS Device through the FS hub.


Note: In a peer to peer setup, the DWC_otg Host core ignores this bit even if it is set by the application software.

Endpoint Type (EPType)


Indicates the transfer type selected.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

Multi Count (MC) / Error Count (EC)


When the Split Enable bit of the Host Channel-n Split Control

register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to

the host the number of transactions that must be executed per

microframe for this periodic endpoint. For non periodic transfers,

this field is used only in DMA mode, and specifies the number

packets to be fetched for this channel before the internal DMA

engine changes arbitration.

- 2'b00: Reserved This field yields undefined results.

- 2'b01: 1 transaction

- 2'b10: 2 transactions to be issued for this endpoint per microframe

- 2'b11: 3 transactions to be issued for this endpoint per microframe

When HCSPLTn.SpltEna is Set (1'b1), this field indicates the

number of immediate retries to be performed for a periodic split

transactions on transaction errors. This field must be Set to at

least 2'b01.

Device Address (DevAddr)


This field selects the specific device serving as the data source

or sink.

Odd Frame (OddFrm)


This field is set (reset) by the application to indicate that the OTG host must perform

a transfer in an odd (micro)Frame. This field is applicable for only periodic

(isochronous and interrupt) transactions.

- 1'b0: Even (micro)Frame

- 1'b1: Odd (micro)Frame


Channel Disable (ChDis)


The application sets this bit to stop transmitting/receiving data

on a channel, even before the transfer for that channel is

complete. The application must wait for the Channel Disabled

interrupt before treating the channel as disabled.

Channel Enable (ChEna)


When Scatter/Gather mode is enabled

- 1'b0: Indicates that the descriptor structure is not yet ready.

- 1'b1: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor.

When Scatter/Gather mode is disabled


This field is set by the application and cleared by the OTG host.

- 1'b0: Channel disabled

- 1'b1: Channel enabled
Host Channel 15 Split Control Register
Port Address (PrtAddr)


This field is the port number of the recipient transaction translator.

Hub Address (HubAddr)


This field holds the device address of the transaction translator's hub.

Transaction Position (XactPos)


This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction.

- 2'b11: All. This is the entire data payload is of this transaction (which is less than or equal to 188 bytes).

- 2'b10: Begin. This is the first data payload of this transaction (which is larger than 188 bytes).

- 2'b00: Mid. This is the middle payload of this transaction (which is larger than 188 bytes).

- 2'b01: End. This is the last payload of this transaction (which is larger than 188 bytes).

Do Complete Split (CompSplt)


The application sets this field to request the OTG host to perform a complete split transaction.

Split Enable (SpltEna)


The application sets this field to indicate that this channel is enabled to perform split transactions.
"Host Channel $i Interrupt Register" This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All Channels Interrupt (HAINT) register to get the exact channel number for the Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers.
Transfer Completed (XferCompl)


Transfer completed normally without any errors.This bit can be set only by the core and the application should write 1 to clear it.

- For Scatter/Gather DMA mode, it indicates that current descriptor processing got completed with IOC bit set in its descriptor.

- In non Scatter/Gather DMA mode, it indicates that Transfer completed normally without any errors.


Channel Halted (ChHltd)


In non Scatter/Gather DMA mode, it indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application or because of a completed transfer.


In Scatter/gather DMA mode, this indicates that transfer completed due to any of the following

- EOL being set in descriptor

- AHB error

- Excessive transaction errors

- Babble

- Stall


AHB Error (AHBErr)


This is generated only in Internal DMA mode when there is an AHB error during AHB read/write. The application can read the corresponding channel's DMA address register to get the error address.

STALL Response Received Interrupt (STALL)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NAK Response Received Interrupt (NAK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

ACK Response Received/Transmitted Interrupt (ACK)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

NYET Response Received Interrupt (NYET)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Transaction Error (XactErr)


Indicates one of the following errors occurred on the USB.

- CRC check failure

- Timeout

- Bit stuff error

- False EOP

In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core.This bit can be set only by the core and the application should write 1 to clear it.

Babble Error (BblErr)


In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. This bit can be set only by the core and the application should write 1 to clear it.

Frame Overrun (FrmOvrun).


In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core. This bit can be set only by the core and the application should write 1 to clear

it.


Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear

it.In Scatter/Gather DMA mode, the interrupt due to this bit is masked

in the core.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the Core to process. BNA will not be generated

for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Excessive Transaction Error (XCS_XACT_ERR)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when 3 consecutive transaction errors occurred on the USB bus. XCS_XACT_ERR will

not be generated for Isochronous channels.

For non Scatter/Gather DMA mode, this bit is reserved.

Descriptor rollover interrupt (DESC_LST_ROLLIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core sets this bit

when the corresponding channel's descriptor list rolls over.

For non Scatter/Gather DMA mode, this bit is reserved.
"Host Channel $i Interrupt Mask Register" This register reflects the mask for each channel status described in the previous section.

Transfer Completed Mask (XferComplMsk)


Channel Halted Mask (ChHltdMsk)


AHB Error Mask (AHBErrMsk)

In scatter/gather DMA mode for host,

interrupts will not be generated due to the corresponding bits set in

HCINTn.


BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.


Descriptor List rollover interrupt Mask register(DESC_LST_ROLLIntrMsk)

This bit is valid only when Scatter/Gather DMA mode is enabled.
Host Channel 15 Transfer Size Register
Transfer Size (XferSize)


For an OUT, this field is the number of data bytes the host sends during the transfer.


For an IN, this field is the buffer size that the application has Reserved for the transfer. The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions (periodic and non-periodic).


The width of this counter is specified as Width of Transfer Size Counters during coreConsultant configuration (parameter OTG_TRANS_COUNT_WIDTH).

Packet Count (PktCnt)


This field is programmed by the application with the expected number of packets to be transmitted (OUT) or received (IN).


The host decrements this count on every successful transmission or reception of an OUT/IN packet. Once this count reaches zero, the application is interrupted to indicate normal completion.


The width of this counter is specified as Width of Packet Counters during coreConsultant configuration (parameter OTG_PACKET_COUNT_WIDTH).

PID (Pid)


The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA (non-control)/SETUP (control)

Do Ping (DoPng)


This bit is used only for OUT transfers.

Setting this field to 1 directs the host to do PING protocol.


Note: Do not set this bit for IN transfers. If this bit is set for for IN transfers it disables the channel.
"Host Channel $i DMA Address Register" This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer for IN/OUT transactions. The starting DMA address must be DWORD-aligned.
In Buffer DMA Mode:


[31:0]: DMA Address (DMAAddr)


This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction.


Reset: X if not programmed as the register is in SPRAM.


In Scatter-Gather DMA (DescDMA) Mode for Non-Isochronous:


[31:9]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the start address of the 512 bytes page. The first descriptor in the list should be located in this address. The first descriptor may be or may not be ready. The core starts processing the list from the CTD value.


[8:3]: Current Transfer Desc(CTD)


This value is in terms of number of descriptors. The values can be from 0 to 63.

- 0 - 1 descriptor.

- 63 - 64 descriptors.

This field indicates the current descriptor processed in the list. This field is updated both by application and the core. For example, if the application enables the channel after programming CTD=5, then the core will start processing the sixth descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr.


Reset: 6'h0


[2:0]: Reserved


In Scatter-Gather DMA (DescDMA) Mode for Isochronous:


[31:N]: DMA Address (DMAAddr)


The start address must be 512-bytes aligned.


This field holds the address of the 2*(nTD+1) bytes of locations in which the isochronous descriptors are present where N is based on nTD as follows:

- [31:N]: Base Address

- [N-1:3]: Offset

- [2:0]: 000

For HS ISOC, if nTD is,

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

- 127, N=10

- 255, N=11

For FS ISOC, if nTD is,

- 1, N=4

- 3, N=5

- 7, N=6

- 15, N=7

- 31, N=8

- 63, N=9

[N-1:3]: Current Transfer Desc(CTD)


CTD for isochronous is based on the current frame/(micro)frame value. Need to be set to zero by application.


Reset: (N+1:3)'h0


[2:0]: Reserved
"Host Channel $i DMA Buffer Address Register" This register is present only in case of Scatter/Gather DMA. It is implemented in RAM instead of flop-based implementation. This register holds the current buffer address.
Holds the current buffer address.

This register is updated as and when the data transfer for the corresponding end point

is in progress. This register is present only in Scatter/Gather DMA mode. Otherwise this

field is reserved.
Device Configuration Register This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.
Device Speed (DevSpd)


Indicates the speed at which the application requires the core to

enumerate, or the maximum speed the application can support.

However, the actual bus speed is determined only after the connect

sequence is completed, and is based on the speed of the USB

host to which the core is connected.

Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)


The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage.

- 1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.

- 1'b0: Send the received OUT packet to the application (zerolength or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.

Enable 32 KHz Suspend mode (Ena32KHzSusp)


This bit can be set only if FS PHY interface is selected. Otherwise, this bit needs to be set to zero. If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend must be switched from 48 MHz to 32 KHz.


Device Address (DevAddr)


The application must program this field after every SetAddress control command.

Periodic Frame Interval (PerFrInt)


Indicates the time within a (micro)Frame at which the application

must be notified using the End Of Periodic Frame Interrupt. This

can be used to determine If all the isochronous traffic for that

(micro)Frame is complete.

- 2'b00: 80% of the (micro)Frame interval

- 2'b01: 85% of the (micro)Frame interval

- 2'b10: 90% of the (micro)Frame interval

- 2'b11: 95% of the (micro)Frame interval

Enable Device OUT NAK (EnDevOutNak)


This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed for Device mode Descriptor DMA

- 1'b0 : The core does not set NAK after Bulk OUT transfer complete

- 1'b1 : The core sets NAK after Bulk OUT transfer complete

It bit is one time programmable after reset like any other DCFG register bits.

XCVRDLY


Enables or disables delay between xcvr_sel and txvalid during device chirp


Erratic Error Interrupt Mask


Enable Scatter/gather DMA in device mode (DescDMA).


When the Scatter/Gather DMA option selected during configuration of the RTL, the application can Set this bit during initialization to enable the Scatter/Gather DMA operation.


Note: This bit must be modified only once after a reset. The following combinations are available for programming:

- GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode

- GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid

- GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA mode

- GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode

Periodic Scheduling Interval (PerSchIntvl)


PerSchIntvl must be programmed for Scatter/Gather DMA mode.


This field specifies the amount of time the Internal

DMA engine must allocate for fetching periodic IN endpoint data.

Based on the number of periodic endpoints, this value must be

specified as 25,50 or 75% of (micro)Frame.

- When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data .

- When no periodic endpoints are active, Then the internal DMA engine services non-periodic endpoints, ignoring this field.

- After the specified time within a (micro)Frame, the DMA switches to fetching for non-periodic endpoints.

-- 2'b00: 25% of (micro)Frame.

-- 2'b01: 50% of (micro)Frame.

-- 2'b10: 75% of (micro)Frame.

-- 2'b11: Reserved.

Reset: 2'b00


Resume Validation Period (ResValid)


This field is effective only when DCFG.Ena32KHzSusp is set.

It controls the resume period when the core resumes from

suspend. The core counts for ResValid number of clock cycles

to detect a valid resume when this bit is set
Device Control Register
Remote Wakeup Signaling (RmtWkUpSig)


When the application sets this bit, the core initiates remote

signaling to wake up the USB host. The application must Set this

bit to instruct the core to exit the Suspend state. As specified in

the USB 2.0 specification, the application must clear this bit

1-15 ms after setting it.



If LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must set this bit to instruct the core to exit the Sleep state. As specified in the LPM specification, the hardware automatically clears this bit 50 microseconds (TL1DevDrvResume) after being set by the application. The application must not set this bit when GLPMCFG bRemoteWake from the previous LPM transaction is zero.

Soft Disconnect (SftDiscon)


The application uses this bit to signal the controller to do a soft disconnect. As long as this bit is Set, the host does not see that the device is connected, and the device does not receive

signals on the USB. The core stays in the disconnected state until the application clears this bit.

- 1'b0: Normal operation. When this bit is cleared after a soft disconnect, the core drives the phy_opmode_o signal on the

UTMI+ to 2'b00, which generates a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.

- 1'b1: The core drives the phy_opmode_o signal on the UTMI+ to 2'b01, which generates a device disconnect event to the USB host.

The following is the minimum duration under various conditions for which this bit must be set for the USB host to detect a device disconnect. To accommodate clock jitter, it is

recommended that the application adds some extra delay to the specified minimum duration.


For high speed, if the device state is,

- Suspended, the minimum duration is 1ms + 2.5us

- Idle, the minimum duration is 3ms + 2.5us

- Not Idle or Suspended (performing transactions), the minimum duration 125 us

For full speed/low speed, if the device state is,

- Suspended, the minimum duration is 1ms + 2.5us

- Idle, the minimum duration is 2.5us

- Not Idle or Suspended (performing transactions), the minimum duration 125 us

Note:

- This bit can be also used for ULPI/FS Serial interfaces.

- This bit is not impacted by a soft reset.

Global Non-periodic IN NAK Status (GNPINNakSts)

- 1'b0: A handshake is sent out based on the data availability in the transmit FIFO.

- 1'b1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.

Global OUT NAK Status (GOUTNakSts)

- 1'b0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.

- 1'b1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.

Test Control (TstCtl)

- 3'b000: Test mode disabled

- 3'b001: Test_J mode

- 3'b010: Test_K mode

- 3'b011: Test_SE0_NAK mode

- 3'b100: Test_Packet mode

- 3'b101: Test_Force_Enable

- Others: Reserved

Set Global Non-periodic IN NAK (SGNPInNak)


A write to this field sets the Global Non-periodic IN NAK.The application uses this bit to send a NAK handshake on all non-periodic IN endpoints.

The core can also Set this bit when a timeout condition is detected on a non-periodic endpoint in shared FIFO operation.

The application must Set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared

Clear Global Non-periodic IN NAK (CGNPInNak)


A write to this field clears the Global Non-periodic IN NAK.

Set Global OUT NAK (SGOUTNak)


A write to this field sets the Global OUT NAK. The application uses this bit to send a NAK handshake on all OUT endpoints.

The application must set the this bit only after making sure that the Global OUT NAK Effective bit in the Core Interrupt Register (GINTSTS.GOUTNakEff) is cleared.

Clear Global OUT NAK (CGOUTNak)


A write to this field clears the Global OUT NAK.

Power-On Programming Done (PWROnPrgDone)


The application uses this bit to indicate that register programming is completed after a wake-up from Power Down mode.

Global Multi Count (GMC)


GMC must be programmed only once after initialization.

Applicable only for Scatter/Gather DMA mode. This indicates the number of packets to be serviced for that end point before moving to the next end point. It is only for non-periodic endpoints.

- 2'b00: Invalid.

- 2'b01: 1 packet.

- 2'b10: 2 packets.

- 2'b11: 3 packets.

The value of this field automatically changes to 2'h1 when DCFG.DescDMA is set to 1. When Scatter/Gather DMA mode is disabled, this field is reserved. and reads 2'b00.

Ignore Frame Number Feature for Isochronous Endpoints (IgnrFrmNum)


This field is also used to control the Periodic Transfer Interrupt (PTI) feature.


Note: Do not program IgnrFrmNum bit to 1'b1 when the core is operating in threshold mode.


Slave Mode (GAHBCFG.DMAEn=0):


This bit is not valid in Slave mode and should not be programmed to 1.


Scatter/Gather DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=1):


Note: When Scatter/Gather DMA mode is enabled this feature is not applicable to High Speed, High bandwidth transfers.


When this bit is enabled, there must be only one packet per descriptor.

- 0: The core transmits the packets only in the frame number in which they are intended to be transmitted.

- 1: The core ignores the frame number, sending packets immediately as the packets are ready.

In Scatter/Gather DMA mode, if this bit is enabled, the packets are not flushed when a ISOC IN token is received for an elapsed frame.


Non-Scatter/Gather DMA Mode, that is, Buffer DMA Mode (GAHBCFG.DMAEn=1,DCFG.DescDMA=0):


When Scatter/Gather DMA mode is disabled, this field is used by the application to enable Periodic Transfer Interrupt (PTI) Mode.


The application can program Periodic Endpoint transfers for multiple (micro)Frames.

- 0: Periodic Transfer Interrupt feature is disabled, application needs to program transfers for periodic endpoints every (micro)Frame

- 1: Periodic Transfer Interrupt feature is enabled, application can program transfers for multiple (micro)Frames for periodic endpoints.

In the PTI mode, the application will receive Transfer Complete Interrupt after transfers for multiple (micro)Frames are completed.

NAK on Babble Error (NakOnBble)


Set NAK automatically on babble (NakOnBble). The core sets NAK automatically for the endpoint on which babble is received.

Enable Continue on BNA (EnContOnBNA)


This bit enables the core to continue on BNA for Bulk OUT endpoints.

With this feature enabled, when a Bulk OUT or INTR OUT endpoint receives a BNA interrupt

the core starts processing the descriptor that caused the BNA interrupt after

the endpoint re-enables the endpoint.

- 1'b0: After receiving BNA interrupt,the core disables the endpoint. When the endpoint is re-enabled by the application,the core starts processing from the DOEPDMA descriptor.

- 1'b1: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt.


This bit is valid only when OTG_EN_DESC_DMA == 1'b1. It is a one-time programmable after reset bit like any other DCTL register bits.
Device Status Register This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.
Suspend Status (SuspSts)


In Device mode, this bit is set as long as a Suspend condition is

detected on the USB. The core enters the Suspend state

when there is no activity on the phy_line_state_i signal for an

extended period of time. The core comes out of the suspend under the following conditions :

- If there is any activity on the phy_line_state_i signal, or

- If the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig).

When the core comes out of the suspend, this bit is set to 1'b0.

Enumerated Speed (EnumSpd)


Indicates the speed at which the controller has come up

after speed detection through a connect or reset sequence.

- 2'b00: High speed (PHY clock is running at 30 or 60 MHz)

- 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)

- 2'b10: Low speed (PHY clock is running at 6 MHz)

- 2'b11: Full speed (PHY clock is running at 48 MHz)

Low speed is not supported for devices using a UTMI+ PHY.

Erratic Error (ErrticErr)


The core sets this bit to report any erratic errors

(phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at

least 2 ms, due to PHY error) seen on the UTMI+.

Due to erratic errors, the DWC_otg core goes into Suspended

state and an interrupt is generated to the application with Early

Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).

If the early suspend is asserted due to an erratic error, the

application can only perform a soft disconnect recover.

Frame or Microframe Number of the Received SOF (SOFFN)


When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number.


Note: This register may return a non-zero value if read immediately after power-on reset.

In case the register bit reads non-zero immediately after power-on reset, it does not

indicate that SOF has been received from the host. The read value of this interrupt is

valid only after a valid connection between host and device is established.

Device Line Status (DevLnSts)


Indicates the current logic level USB data lines

- DevLnSts[1]: Logic level of D+

- DevLnSts[0]: Logic level of D-
Device IN Endpoint Common Interrupt Mask Register This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.
Transfer Completed Interrupt Mask (XferComplMsk)

Endpoint Disabled Interrupt Mask (EPDisbldMsk)

AHB Error Mask (AHBErrMsk)

Timeout Condition Mask (TimeOUTMsk) (Non-isochronous endpoints)

IN Token Received When TxFIFO Empty Mask (INTknTXFEmpMsk)

IN Token received with EP Mismatch Mask (INTknEPMisMsk)

IN Endpoint NAK Effective Mask (INEPNakEffMsk)

Fifo Underrun Mask (TxfifoUndrnMsk)

BNA interrupt Mask (BNAInIntrMsk)

NAK interrupt Mask (NAKMsk)
Device OUT Endpoint Common Interrupt Mask Register This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTn register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.
Transfer Completed Interrupt Mask (XferComplMsk)

Endpoint Disabled Interrupt Mask (EPDisbldMsk)

AHB Error (AHBErrMsk)

SETUP Phase Done Mask (SetUPMsk)


Applies to control endpoints only.

OUT Token Received when Endpoint Disabled Mask (OUTTknEPdisMsk)


Applies to control OUT endpoints only.

Status Phase Received Mask (StsPhseRcvdMsk)


Applies to control OUT endpoints only.

Back-to-Back SETUP Packets Received Mask (Back2BackSETup)


Applies to control OUT endpoints only.

OUT Packet Error Mask (OutPktErrMsk)

BNA interrupt Mask (BnaOutIntrMsk)

Babble Error interrupt Mask (BbleErrMsk)

NAK interrupt Mask (NAKMsk)

NYET interrupt Mask (NYETMsk)
Device All Endpoints Interrupt Register When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively). This is shown in Figure 5-2. There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
IN Endpoint 0 Interrupt Bit

IN Endpoint 1 Interrupt Bit

IN Endpoint 2 Interrupt Bit

IN Endpoint 3 Interrupt Bit

IN Endpoint 4 Interrupt Bit

IN Endpoint 5 Interrupt Bit

IN Endpoint 6 Interrupt Bit

IN Endpoint 7 Interrupt Bit

IN Endpoint 8 Interrupt Bit

IN Endpoint 9 Interrupt Bit

IN Endpoint 10 Interrupt Bit

IN Endpoint 11 Interrupt Bit

IN Endpoint 12 Interrupt Bit

OUT Endpoint 0 Interrupt Bit

OUT Endpoint 1 Interrupt Bit

OUT Endpoint 2 Interrupt Bit

OUT Endpoint 3 Interrupt Bit

OUT Endpoint 4 Interrupt Bit

OUT Endpoint 5 Interrupt Bit

OUT Endpoint 6 Interrupt Bit

OUT Endpoint 7 Interrupt Bit

OUT Endpoint 8 Interrupt Bit

OUT Endpoint 9 Interrupt Bit

OUT Endpoint 10 Interrupt Bit

OUT Endpoint 11 Interrupt Bit

OUT Endpoint 12 Interrupt Bit
Device All Endpoints Interrupt Mask Register The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the application when an event occurs on a device endpoint. However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set.
IN Endpoint 0 Interrupt mask Bit

IN Endpoint 1 Interrupt mask Bit

IN Endpoint 2 Interrupt mask Bit

IN Endpoint 3 Interrupt mask Bit

IN Endpoint 4 Interrupt mask Bit

IN Endpoint 5 Interrupt mask Bit

IN Endpoint 6 Interrupt mask Bit

IN Endpoint 7 Interrupt mask Bit

IN Endpoint 8 Interrupt mask Bit

IN Endpoint 9 Interrupt mask Bit

IN Endpoint 10 Interrupt mask Bit

IN Endpoint 11 Interrupt mask Bit

IN Endpoint 12 Interrupt mask Bit

OUT Endpoint 0 Interrupt mask Bit

OUT Endpoint 1 Interrupt mask Bit

OUT Endpoint 2 Interrupt mask Bit

OUT Endpoint 3 Interrupt mask Bit

OUT Endpoint 4 Interrupt mask Bit

OUT Endpoint 5 Interrupt mask Bit

OUT Endpoint 6 Interrupt mask Bit

OUT Endpoint 7 Interrupt mask Bit

OUT Endpoint 8 Interrupt mask Bit

OUT Endpoint 9 Interrupt mask Bit

OUT Endpoint 10 Interrupt mask Bit

OUT Endpoint 11 Interrupt mask Bit

OUT Endpoint 12 Interrupt mask Bit
Device VBUS Discharge Time Register This register specifies the VBUS discharge time after VBUS pulsing during SRP.
Device VBUS Discharge Time (DVBUSDis)


Specifies the VBUS discharge time after VBUS pulsing during SRP. This value equals (VBUS discharge time in PHY clocks) / 1, 024.


The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).


Depending on your VBUS load, this value can need adjustment.
Device VBUS Pulsing Time Register
Device VBUS Pulsing Time (DVBUSPulse)


Specifies the VBUS pulsing time during SRP. This value equals (VBUS pulsing time in PHY clocks) / 1, 024


The value you use depends whether the PHY is operating at 30MHz (16-bit data width) or 60 MHz (8-bit data width).
Device Threshold Control Register
Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)


When this bit is Set, the core enables thresholding for Non Isochronous IN endpoints.


ISO IN Endpoints Threshold Enable. (ISOThrEn)



When this bit is Set, the core enables thresholding for isochronous IN

endpoints.

Transmit Threshold Length (TxThrLen)


This field specifies Transmit thresholding size in DWORDS. This also forms

the MAC threshold and specifies the amount of data in bytes to be in the

corresponding endpoint transmit FIFO, before the core can start transmit

on the USB. The threshold length has to be at least eight DWORDS when the

value of AHBThrRatio is 2'h00. In case the AHBThrRatio is non zero the

application needs to ensure that the AHB Threshold value does not go below

the recommended eight DWORD. This field controls both isochronous and

non-isochronous IN endpoint thresholds. The recommended value for ThrLen

is to be the same as the programmed AHB Burst Length (GAHBCFG.HBstLen).


Note:

- When OTG_ARCHITECTURE=0, the reset value of this register field is 0.

- When OTG_ARCHITECTURE=2, the reset value of this register field is 8.


AHB Threshold Ratio (AHBThrRatio)


These bits define the ratio between the AHB threshold and the MAC threshold for the

transmit path only. The AHB threshold always remains less than or equal to the USB

threshold, because this does not increase overhead. Both the AHB and the MAC

threshold must be DWORD-aligned. The application needs to program TxThrLen and the

AHBThrRatio to make the AHB Threshold value DWORD aligned. If the AHB threshold

value is not DWORD aligned, the core might not behave correctly. When programming

the TxThrLen and AHBThrRatio, the application must ensure that the minimum AHB

threshold value does not go below 8 DWORDS to meet the USB turnaround time

requirements.

- 2'b00: AHB threshold = MAC threshold

- 2'b01: AHB threshold = MAC threshold / 2

- 2'b10: AHB threshold = MAC threshold / 4

- 2'b11: AHB threshold = MAC threshold / 8

Receive Threshold Enable (RxThrEn)


When this bit is set, the core enables thresholding in the receive direction.


Note: We recommends that you do not enable RxThrEn, because it may cause issues in the RxFIFO especially during error conditions such as RxError and Babble.

Receive Threshold Length (RxThrLen)


This field specifies Receive thresholding size in DWORDS.

This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB.

The threshold length has to be at least eight DWORDS.

The recommended value for ThrLen is to be the same as the programmed

AHB Burst Length (GAHBCFG.HBstLen).

Arbiter Parking Enable (ArbPrkEn)


This bit controls internal DMA arbiter parking for IN endpoints. If thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default, arbiter parking is enabled.
Device IN Endpoint FIFO Empty Interrupt Mask Register This register is valid only in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO = 1). This register is used to control the IN endpoint FIFO empty interrupt generation (DIEPINTn.TxfEmp).
IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)


These bits acts as mask bits for DIEPINTn.TxFEmp interrupt, one bit per IN Endpoint:


Bit 0 for IN EP 0, bit 15 for IN EP 15
Device Control IN Endpoint 0 Control Register
Maximum Packet Size (MPS)


Applies to IN and OUT endpoints.


The application must program this field with the maximum packet size for the current logical endpoint.

- 2'b00: 64 bytes

- 2'b01: 32 bytes

- 2'b10: 16 bytes

- 2'b11: 8 bytes

USB Active Endpoint (USBActEP)


This bit is always SET to 1, indicating that control endpoint 0 is always active in all configurations and interfaces.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When this bit is set, either by the application or core, the core stops

transmitting data, even If there is data available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data

packets with an ACK handshake.

Endpoint Type (EPType)


Hardcoded to 00 for control.

STALL Handshake (Stall)


The application can only set this bit, and the core clears it, when a

SETUP token is received for this endpoint. If a NAK bit, Global Nonperiodic

IN NAK, or Global OUT NAK is set along with this bit, the STALL

bit takes priority.

TxFIFO Number (TxFNum)

- For Shared FIFO operation, this value is always set to 0, indicating that control IN endpoint 0 data is always written in the Non-Periodic Transmit FIFO.

- For Dedicated FIFO operation, this value is set to the FIFO number that is assigned to IN Endpoint.


Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.


Set NAK (SNAK)

A write to this bit sets the NAK bit for the endpoint.

Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Endpoint Disable (EPDis)


The application sets this bit to stop transmitting data on an endpoint,

even before the transfer for that endpoint is complete. The application

must wait for the Endpoint Disabled interrupt before treating the endpoint

as disabled. The core clears this bit before setting the Endpoint Disabled

Interrupt. The application must Set this bit only if Endpoint Enable is

already set for this endpoint.

Endpoint Enable (EPEna)


When Scatter/Gather DMA mode is enabled for IN endpoints, this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.


When Scatter/Gather DMA mode is disabled (such as in buffer pointer based DMA mode) this bit indicates that data is ready to be transmitted on the endpoint.

The core clears this bit before setting the following interrupts on this endpoint:

- Endpoint Disabled

- Transfer Completed
Device IN Endpoint 0 Interrupt Register This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in the "Interrupt Hierarchy" figure in the databook. The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an AHB error during an AHB read/write. The application can read the corresponding endpoint DMA address register to get the error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core).


The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN Endpoints


This interrupt is asserted when the TxFIFO for this endpoint is either half or completely empty. The half or completely empty status is determined by the TxFIFO Empty Level bit in the Core AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints only.


The core generates this interrupt when it detects a transmit FIFO underrun condition in threshold mode for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled. The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

<brIn case of isochronous IN endpoints the interrupt gets generated when a zero length packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 0 Transfer Size Register The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using Endpoint Enable bit of the Device Control Endpoint 0 Control registers (DIEPCTL0.EPEna/DOEPCTL0.EPEna), the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit. Nonzero endpoints use the registers for endpoints 115. When Scatter/Gather DMA mode is enabled, this register must not be programmed by the application. If the application reads this register when Scatter/Gather DMA mode is enabled, the core returns all zeros.
Transfer Size (XferSize)


This field contains the transfer size in bytes for the current endpoint. The transfer size (XferSize) = Sum of buffer sizes across all descriptors in the list for the endpoint.

In Buffer DMA, the core only interrupts the application after it has exhausted the transfer size amount of data. The transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet.

- IN Endpoints: The core decrements this field every time a packet from the external memory is written to the TxFIFO.

- OUT Endpoints: The core decrements this field every time a packet is read from the RxFIFO and written to the external memory.


Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the


Transfer Size amount of data for endpoint 0.

- IN Endpoints : This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

- OUT Endpoints: This field is decremented every time a packet (maximum size or short packet) is written to the RxFIFO.
Device IN Endpoint 0 DMA Address Register
DMAAddr


This field holds the start address of the external memory for storing or fetching endpoint data.


Note: For control endpoints, this field stores control OUT data packets as well as SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give only a DWORD-aligned address.


When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.


When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 0
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 16 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control IN Endpoint 1 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 1 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 1 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 1 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 1 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 1 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 2 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 2 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 2 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 2 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 2 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 2 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 3 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 3 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 3 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 3 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 3 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 3 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 4 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 4 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 4 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 4 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 4 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 4 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 5 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 5 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 5 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 5 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 5 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 5 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 6 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 6 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 6 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 6 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 6 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 6 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 7 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 7 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 7 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 7 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 7 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 7 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 8 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 8 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 8 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 8 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 8 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 8 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 9 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 9 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 9 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 9 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 9 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 9 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 10 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 10 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 10 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 10 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 10 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 10 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 11 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 11 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 11 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 11 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 11 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 11 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control IN Endpoint 12 Control Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.


Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather

DMA mode.


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:


Applies to isochronous IN and OUT endpoints only.


Indicates the (micro)frame number in which the core transmits/receives isochronous

data for this endpoint. The application must program the even/odd (micro)frame

number in which it intends to transmit/receive isochronous data for this endpoint using

the SetEvnFr and SetOddFr fields in this register.

- 1'b0: Even (micro)frame

- 1'b1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number

in which to send data is provided in the transmit descriptor structure. The frame in

which data is received is updated in receive descriptor structure.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)

This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.


TxFIFO Number (TxFNum)


Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic

endpoints must map this to the corresponding Periodic TxFIFO number.

- 4'h0: Non-Periodic TxFIFO

- Others: Specified Periodic TxFIFO.number

Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for

applications such as mass storage. The core treats an IN endpoint as a non-periodic

endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be

allocated for an interrupt IN endpoint, and the number of this

FIFO must be programmed into the TxFNum field. Configuring an interrupt IN

endpoint as a non-periodic endpoint saves the extra periodic FIFO area.


Dedicated FIFO Operation: These bits specify the FIFO number associated with this

endpoint. Each active IN endpoint must be programmed to a separate FIFO number.

This field is valid only for IN endpoints.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

SetD0PID

- Set DATA0 PID (SetD0PID)

-- Applies to interrupt/bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

-- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

In non-Scatter/Gather DMA mode: Set Even (micro)Frame (SetEvenFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the Even/Odd (micro)Frame (EO_FrNum) field to even (micro)Frame.

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to

receive data is updated in receive descriptor structure.

SetD1PID

- Set DATA1 PID (SetD1PID)

-- Applies to interrupt and bulk IN and OUT endpoints only.

-- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

-- This field is applicable both for Scatter-Gather DMA mode and non Scatter-Gather DMA mode.

- Set odd (micro)Frame (SetOddFr)

-- Applies to isochronous IN and OUT endpoints only.

-- Writing to this field sets the even and odd (micro)Frame (EO_FrNum) field to odd (micro)Frame.

-- This field is not applicable for Scatter-Gather DMA mode.

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled,

-- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

-- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

-- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

-- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device IN Endpoint 12 Interrupt Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

Timeout Condition (TimeOUT)

- In shared TX FIFO mode, applies to non-isochronous IN endpoints only.

- In dedicated FIFO mode, applies only to Control IN endpoints.

- In Scatter/Gather DMA mode, the TimeOUT interrupt is not asserted.

Indicates that the core has detected a timeout condition on the USB for the last IN token on this endpoint.

IN Token Received When TxFIFO is Empty (INTknTXFEmp)


Applies to non-periodic IN endpoints only.


Indicates that an IN token was received when the associated TxFIFO (periodic/non-periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received.

IN Token Received with EP Mismatch (INTknEPMis)


Applies to non-periodic IN endpoints only.


Indicates that the data in the top of the non-periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received. This interrupt is asserted on the endpoint for which the IN token was received.

IN Endpoint NAK Effective (INEPNakEff)


Applies to periodic IN endpoints only.


This bit can be cleared when the application clears the IN endpoint NAK by writing to DIEPCTLn.CNAK.


This interrupt indicates that the core has sampled the NAK bit


Set (either by the application or by the core). The interrupt indicates that the IN endpoint NAK bit Set by the application has taken effect in the core.


This interrupt does not guarantee that a NAK handshake is sent on the USB. A STALL bit takes priority over a NAK bit.

Transmit FIFO Empty (TxFEmp)


This bit is valid only for IN endpoints


This interrupt is asserted when the TxFIFO for this endpoint is

either half or completely empty. The half or completely empty

status is determined by the TxFIFO Empty Level bit in the Core

AHB Configuration register (GAHBCFG.NPTxFEmpLvl)).

Fifo Underrun (TxfifoUndrn)


Applies to IN endpoints Only


This bit is valid only If thresholding is enabled. The core generates this interrupt when

it detects a transmit FIFO underrun condition for this endpoint.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed is not ready for the Core to process, such as Host busy or DMA done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.
Device IN Endpoint 12 Transfer Size Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet from the

external memory is written to the TxFIFO.

Packet Count (PktCnt)


Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0.


This field is decremented every time a packet (maximum size or short packet) is read from the TxFIFO.

MC


Applies to IN endpoints only.


For periodic IN endpoints, this field indicates the number of packets that must be transmitted per microframe on the USB. The core uses this field to calculate the data PID for isochronous IN endpoints.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets

For non-periodic IN endpoints, this field is valid only in Internal DMA mode. It specifies the number of packets the core must fetchfor an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device Endpoint-n Control register (DIEPCTLn.NextEp)
Device IN Endpoint 12 DMA Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.

Device IN Endpoint Transmit FIFO Status Register 12 Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)


Indicates the amount of free space available in the Endpoint TxFIFO.


Values are in terms of 32-bit words.

- 16'h0: Endpoint TxFIFO is full

- 16'h1: 1 word available

- 16'h2: 2 words available

- 16'hn: n words available (where 0 n 32,768)

- 16'h8000: 32,768 words available

- Others: Reserved
Device IN Endpoint 12 Buffer Address Register Note: This register exists for an endpoint i if the OTG_EP_DIR_i parameter is 0 or 1 for that endpoint.
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control OUT Endpoint 0 Control Register
Maximum Packet Size (MPS)


The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN Endpoint 0.

- 2'b00: 64 bytes

- 2'b01: 32 bytes

- 2'b10: 16 bytes

- 2'b11: 8 bytes

USB Active Endpoint (USBActEP)


This bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces.

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit, the core

stops receiving data, even If there is space in the RxFIFO to

accommodate the incoming packet. Irrespective of this bit's

setting, the core always responds to SETUP data packets with

an ACK handshake.

Endpoint Type (EPType)


Hardcoded to 2'b00 for control.

RESERVED

STALL Handshake (Stall)


The application can only set this bit, and the core clears it, when

a SETUP token is received for this endpoint. If a NAK bit or

Global OUT NAK is Set along with this bit, the STALL bit takes

priority. Irrespective of this bit's setting, the core always

responds to SETUP data packets with an ACK handshake.

Clear NAK (CNAK)


A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.

Using this bit, the application can control the transmission of NAK handshakes on an endpoint.

The core can also set bit on a Transfer Completed interrupt, or after a SETUP is received on the endpoint.

Endpoint Disable (EPDis)


The application cannot disable control OUT endpoint 0.

Endpoint Enable (EPEna)

- When Scatter/Gather DMA mode is enabled, for OUT endpoints this bit indicates that the descriptor structure and data buffer to receive data is setup.

- When Scatter/Gather DMA mode is disabled (such as for buffer-pointer based DMA mode)this bit indicates that the application has allocated the memory to start receiving data from the USB.

- The core clears this bit before setting any of the following interrupts on this endpoint:

-- SETUP Phase Done

-- Endpoint Disabled

-- Transfer Completed

Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory.

Device OUT Endpoint 0 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled

- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

Note: In DMA mode, this bit must be set for the core to transfer SETUP data packets into memory. When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint

was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled.


This interrupt is asserted when the core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.

The core generates this interrupt when the descriptor accessed

is not ready for the core to process, such as Host busy or DMA

done.

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.

In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 0 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)


This field is decremented to zero after a packet is written into the RxFIFO.

SETUP Packet Count (SUPCnt)


This field specifies the number of back-to-back SETUP data packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 0 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 16 Buffer Address Register

Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.

This register is present only in Scatter/Gather DMA mode. Otherwise this field is

reserved.
Device Control OUT Endpoint 1 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 1 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 1 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 1 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 1 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 2 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 2 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 2 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 2 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 2 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 3 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 3 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 3 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 3 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 3 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 4 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 4 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 4 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 4 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 4 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 5 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 5 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 5 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 5 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 5 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 6 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 6 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 6 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 6 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 6 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 7 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 7 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 7 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 7 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 7 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 8 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 8 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 8 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 8 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 8 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 9 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 9 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 9 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 9 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 9 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 10 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 10 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 10 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 10 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 10 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 11 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 11 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 11 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 11 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 11 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Device Control OUT Endpoint 12 Control Register
Maximum Packet Size (MPS)


The application must program this field with the maximum packet size for the current

logical endpoint. This value is in bytes.

USB Active Endpoint (USBActEP)


Indicates whether this endpoint is active in the current configuration and interface. The

core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After

receiving the SetConfiguration and SetInterface commands, the application must

program endpoint registers accordingly and set this bit.

Endpoint Data PID (DPID)


Applies to interrupt/bulk IN and OUT endpoints only.


Contains the PID of the packet to be received or transmitted on this endpoint. The

application must program the PID of the first packet to be received or transmitted on

this endpoint, after the endpoint is activated. The applications use the SetD1PID and

SetD0PID fields of this register to program either DATA0 or DATA1 PID.

- 1'b0: DATA0

- 1'b1: DATA1

This field is applicable for both Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.


Reset: 1'b0


Even/Odd (Micro)Frame (EO_FrNum)


In non-Scatter/Gather DMA mode:

- Applies to isochronous IN and OUT endpoints only.

- Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro)frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

-- 1'b0: Even (micro)frame

-- 1'b1: Odd (micro)frame

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Reset: 1'b0

NAK Status (NAKSts)


Indicates the following:

- 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status.

- 1'b1: The core is transmitting NAK handshakes on this endpoint.

When either the application or the core sets this bit:

- The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.

- For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.

- For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Endpoint Type (EPType)


This is the transfer type supported by this logical endpoint.

- 2'b00: Control

- 2'b01: Isochronous

- 2'b10: Bulk

- 2'b11: Interrupt

RESERVED

STALL Handshake (Stall)


Applies to non-control, non-isochronous IN and OUT endpoints only.


The application sets this bit to stall all tokens from the USB host to this endpoint. If a

NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the

STALL bit takes priority. Only the application can clear this bit, never the core.


Applies to control endpoints only.


The application can only set this bit, and the core clears it, when a SETUP token is

received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT

NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's

setting, the core always responds to SETUP data packets with an ACK handshake.



Clear NAK (CNAK)

A write to this bit clears the NAK bit for the endpoint.

Set NAK (SNAK)


A write to this bit sets the NAK bit for the endpoint.


Using this bit, the application can control the transmission of NAK

handshakes on an endpoint. The core can also set this bit for an

endpoint after a SETUP packet is received on that endpoint.

Set DATA0 PID (SetD0PID)

- Applies to interrupt/bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0.

- This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Reset: 1'b0


In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro)frame.

- When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Reset: 1'b0

Set DATA1 PID (SetD1PID)

- Applies to interrupt and bulk IN and OUT endpoints only.

- Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1.

- This field is applicable both for scatter-gather DMA mode and non scatter-gather DMA mode.

Reset: 1'b0


Set Odd (micro)frame (SetOddFr)

- Applies to isochronous IN and OUT endpoints only.

- Writing to this field sets the even and odd (micro)frame (EO_FrNum) field to odd (micro)frame.

Reset: 1'b0

Endpoint Disable (EPDis)


Applies to IN and OUT endpoints.


The application sets this bit to stop transmitting/receiving data on an endpoint, even

before the transfer for that endpoint is complete. The application must wait for the

Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears

this bit before setting the Endpoint Disabled interrupt. The application must set this bit

only if Endpoint Enable is already set for this endpoint.

Endpoint Enable (EPEna)


Applies to IN and OUT endpoints.


When Scatter/Gather DMA mode is enabled,

- For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.

- For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.

When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:

- For IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.

- For OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.

The core clears this bit before setting any of the following interrupts on this endpoint:

- SETUP Phase Done

- Endpoint Disabled

- Transfer Completed

Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
Device OUT Endpoint 12 Interrupt Register
Transfer Completed Interrupt (XferCompl)


Applies to IN and OUT endpoints.

- When Scatter/Gather DMA mode is enabled

-- For IN endpoint this field indicates that the requested data from the descriptor is moved from external system memory to internal FIFO.

-- For OUT endpoint this field indicates that the requested data from the internal FIFO is moved to external system memory. This interrupt is generated only when the corresponding endpoint descriptor is closed, and the IOC bit for the corresponding descriptor is Set.

- When Scatter/Gather DMA mode is disabled, this field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint.

Endpoint Disabled Interrupt (EPDisbld)


Applies to IN and OUT endpoints.


This bit indicates that the endpoint is disabled per the application's request.

AHB Error (AHBErr)


Applies to IN and OUT endpoints.


This is generated only in Internal DMA mode when there is an

AHB error during an AHB read/write. The application can read

the corresponding endpoint DMA address register to get the

error address.

SETUP Phase Done (SetUp)


Applies to control OUT endpoints only.


Indicates that the SETUP phase for the control endpoint is

complete and no more back-to-back SETUP packets were

received for the current control transfer. On this interrupt, the

application can decode the received SETUP data packet.

OUT Token Received When Endpoint Disabled (OUTTknEPdis)


Applies only to control OUT endpoints.


Indicates that an OUT token was received when the endpoint was not yet enabled. This interrupt is asserted on the endpoint for which the OUT token was received.

Status Phase Received for Control Write (StsPhseRcvd)


This interrupt is valid only for Control OUT endpoints and only in

Scatter Gather DMA mode.


This interrupt is generated only after the core has transferred all

the data that the host has sent during the data phase of a control

write transfer, to the system memory buffer.


The interrupt indicates to the application that the host has

switched from data phase to the status phase of a Control Write

transfer. The application can use this interrupt to ACK or STALL

the Status phase, after it has decoded the data phase. This is

applicable only in Case of Scatter Gather DMA mode.

Back-to-Back SETUP Packets Received (Back2BackSETup)


Applies to Control OUT endpoints only.


This bit indicates that the core has received more than three

back-to-back SETUP packets for this particular endpoint. For

information about handling this interrupt,

OUT Packet Error (OutPktErr)


Applies to OUT endpoints Only


This interrupt is valid only when thresholding is enabled. This interrupt is asserted when the

core detects an overflow or a CRC error for non-Isochronous OUT packet.

BNA (Buffer Not Available) Interrupt (BNAIntr)


This bit is valid only when Scatter/Gather DMA mode is enabled.


The core generates this interrupt when the descriptor accessed

is not ready for the Core to process, such as Host busy or DMA

done

Packet Drop Status (PktDrpSts)


This bit indicates to the application that an ISOC OUT packet has been dropped. This

bit does not have an associated mask bit and does not generate an interrupt.


Dependency: This bit is valid in non Scatter/Gather DMA mode when periodic transfer

interrupt feature is selected.

NAK Interrupt (BbleErr)


The core generates this interrupt when babble is received for the endpoint.

NAK Interrupt (NAKInterrupt)


The core generates this interrupt when a NAK is transmitted or received by the device.


In case of isochronous IN endpoints the interrupt gets generated when a zero length

packet is transmitted due to un-availability of data in the TXFifo.

NYET Interrupt (NYETIntrpt)


The core generates this interrupt when a NYET response is transmitted for a non isochronous OUT endpoint.

Setup Packet Received


Applicable for Control OUT Endpoints in only in the Buffer DMA Mode


Set by the controller, this bit indicates that this buffer holds 8 bytes of

setup data. There is only one Setup packet per buffer. On receiving a

Setup packet, the controller closes the buffer and disables the

corresponding endpoint. The application has to re-enable the endpoint to

receive any OUT data for the Control Transfer and reprogram the buffer

start address.


Note: Because of the above behavior, the controller can receive any

number of back to back setup packets and one buffer for every setup

packet is used.

- 1'b0: No Setup packet received

- 1'b1: Setup packet received

Reset: 1'b0
Device OUT Endpoint 12 Transfer Size Register
Transfer Size (XferSize)


Indicates the transfer size in bytes for endpoint 0. The core

interrupts the application only after it has exhausted the transfer

size amount of data. The transfer size can be Set to the

maximum packet size of the endpoint, to be interrupted at the

end of each packet.


The core decrements this field every time a packet is read from

the RxFIFO and written to the external memory.

Packet Count (PktCnt)

This field is decremented to zero after a packet is written into the RxFIFO.

RxDPID


Applies to isochronous OUT endpoints only.


This is the data PID received in the last packet for this endpoint.

- 2'b00: DATA0

- 2'b01: DATA2

- 2'b10: DATA1

- 2'b11: MDATA

SETUP Packet Count (SUPCnt)


Applies to control OUT Endpoints only.


This field specifies the number of back-to-back SETUP data

packets the endpoint can receive.

- 2'b01: 1 packet

- 2'b10: 2 packets

- 2'b11: 3 packets
Device OUT Endpoint 12 DMA Address Register
Holds the start address of the external memory for storing or fetching endpoint

data.


Note: For control endpoints, this field stores control OUT data packets as well as

SETUP transaction data packets. When more than three SETUP packets are

received back-to-back, the SETUP data packet in the memory is overwritten.


This register is incremented on every AHB transaction. The application can give

only a DWORD-aligned address.

- When Scatter/Gather DMA mode is not enabled, the application programs the start address value in this field.

- When Scatter/Gather DMA mode is enabled, this field indicates the base pointer for the descriptor list.
Device OUT Endpoint 12 Buffer Address Register
Holds the current buffer address.This register is updated as and when the data

transfer for the corresponding end point is in progress.


This register is present only in Scatter/Gather DMA mode. Otherwise this field is reserved.
Power and Clock Gating Control Register
Stop Pclk (StopPclk)

- The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected.

- The application clears this bit when the USB is resumed or a new session starts.

Reset Power-Down Modules (RstPdwnModule)


This bit is valid only in Partial Power-Down mode.

- The application sets this bit when the power is turned off.

- The application clears this bit after the power is turned on and the PHY clock is up.


Note: The R/W of all core registers are possible only when this bit is set to 1b0.

PHY In Sleep


Indicates that the PHY is in Sleep State.

L1 Deep Sleep


Indicates that the PHY is in deep sleep when in L1 state.
bit type is changed from ru to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from ru to rw. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from ru to rw. bit type is changed from ru to rw. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. bit type is changed from othr to rw. bit type is changed from othr to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from w1 to rw. bit type is changed from othr to rw. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from w1c to rc. bit type is changed from ru to rw. Controls the big endian or little endian of the FIFO data.
Take 32 bit data 0X0A0B0C0D for Example,bit[31:24]=Byte3,bit[23:16]=Byte2,bit[15:8]=Byte1,bit[7:0]=Byte0.
"000": the order is not changed.
Byte3="0A",Byte2="0B",Byte1="0C",Byte0="0D".
"001": reversed on byte.
Byte3="0D",Byte2="0C,Byte1="0B",Byte0="0A".
"010": reversed on half word.
Byte3="0C",Byte2="0D,Byte1="0A",Byte0="0B".
"010": reversed on bit.
Byte3="B0",Byte2="30,Byte1="D0",Byte0="50".
"100": reversed on bit.
Byte3="0A",Byte2="0X,Byte1="0D",Byte0="0C". For the software to clear FIFO in case there is an error in communication with SD controller and some data are left behind.
Active Low. Write to the transmit FIFO Read in the receive FIFO SD/MMC operation begin register, active high.
When '1', the controller finishes the last command and goes into suspend status. At suspend status, the controller will not execute the next command until the bit is set '0'. SD/MMC operation suspend register, active high. '1'indicates having a response,'0'indicates no response. Response select register,"10" means R2 response, "01" means R3 response, "00" means others response, "11" is reserved. '1' indicates data operation, which includes read and write. '1' means write operation,'0' means read operation. '1'means multiple block data operation. '1' means the SD/MMC operation is not over. '1' means SD/MMC is busy. '1' means the data line is busy. '1' means the controller will not perform the new command when SDMMC_SENDCMD= '1'. Response CRC checks error register '1' means response CRC check error. '1' means the card has no response to command. CRC check for SD/MMC write operation
"101" transmission error
"010" transmission right
"111" flash programming error 8 bits data CRC check, "00000000" means no data error, "00000001" means DATA0 CRC check error, "10000000" means DATA7 CRC check error, each bit match one data line. SDMMC DATA 3 value. SD/MMC command register. SD/MMC command argument register, write data to the SD/MMC card. SD/MMC response index register. Response argument of R1, R3 and R6, or 127 to 96 bit response argument of R2. 95 to 64 bit response argument of R2. 63 to 32 bit response argument of R2. 31 to 0 bit response argument of R2. SD/MMC data width:
0x1: 1 data line
0x2: 2 reserved
0x4: 4 data lines
0x8: 8 data lines SD/MMC size of one block:
0-1:reserved
2: 1 word
3: 2 words
4: 4 words
5: 8 words
6: 16 words

11: 512 words
12-15 reserved Block number that wants to transfer. '1' means no response. '1' means CRC error of response. '1' means CRC error of reading data. '1' means CRC error of writing data. '1' means data transmission is over. '1' means tx dma done. '1' means rx dma done. '1' means no response is the source of interrupt. '1' means CRC error of response is the source of interrupt. '1' means CRC error of reading data is the source of interrupt. '1' means CRC error of writing data is the source of interrupt. '1' means the end of data transmission is the source of interrupt. '1' means tx dma done is the source of interrupt. '1' means rx dma done is the source of interrupt. When no response, '1' means INT is disable. When CRC error of response, '1' means INT is disable. When CRC error of reading data, '1' means INT is disable. When CRC error of writing data, '1' means INT is disable. When data transmission is over, '1' means INT is disable. when tx dma done, '1' means INT is disabled. '1' means rx dma done, '1' means INT is disabled. Write a '1' to this bit to clear the source of interrupt in NO_RSP_SC. Write a '1' to this bit to clear the source of interrupt in RSP_ERR_SC. Write a '1' to this bit to clear the source of interrupt in RD_ERR_SC. Write a '1' to this bit to clear the source of interrupt in WR_ERR_SC. Write a '1' to this bit to clear the source of interrupt in DAT_OVER_SC. Write a '1' to this bit to clear the source of interrupt in TXDMA_DONE_SC. Write a '1' to this bit to clear the source of interrupt in RXDMA_DONE_SC. Mclk = Pclk/(2*(SDMMC_TRANS_SPEED +1)). This register may delay the mclk output. When MCLK_ADJUSTER = n, Mclk is outputted with n Pclk. Invert Mclk. Enable camera controller,high active. Enable camera controller,high active. "0" = RGB565.
"1" = YUV422.
"2" = Compressed Data.
"3" = Reserved. '0' = keep output camera reset polarity.
'1' = invert output camera reset polarity. '0' = keep output camera power down polarity.
'1' = invert output camera power down polarity. '0' = keep input VSYNC polarity.
'1' = invert input VSYNC polarity. '0' = keep input HREF polarity so data is sampled when HREF high.
'1' = invert input HREF polarity so data is sampled when HREF low. '0' = keep pix clk polarity.
'1' = invert pix clk polarity. '0' = VSYNC irq always exists when Frame decimation is enabled.
'1' = VSYNC irq will drop when Frame data are dropped in decipation. "0"= All frame data will be sent.
"1"= only one frame out of two (1/2) will be sent.
"2"= only one frame out of three (1/3) will be sent.
"3"= only one frame out of four (1/4) will be sent. "0"= Pixel Decimation Disabled.
"1"= Pixel Decimation 1/2.
"2"= Pixel Decimation 1/3.
"3"= Pixel Decimation 1/4. "0"= line Decimation Disabled.
"1"= line Decimation 1/2.
"2"= line Decimation 1/3.
"3"= line Decimation 1/4. Controls the Re-ordering of the FIFO data.
In following table, for input data, right comes before left. So YUYV means V comes first.
for output data, right data is the LSB. So YUYV means V is stored in low 8-bit (byte0) of 32-bit word.

If Bit 26 is '1', byte2 and byte0 is Y.
If Bit 25 is '1', both byte2/byte3 and byte1/byte0 interchange.
If Bit 24 is '1', byte U and V should interchange. (UV bytes can be decided using bit 26).

input YUYV, output YUYV: "000"
input YVYU, output YUYV: "001"
input UYVY, output YUYV: "110"
input VYUY, output YUYV: "111"

input YUYV, output UYVY: "010"
input YVYU, output UYVY: "011"
input UYVY, output UYVY: "100"
input VYUY, output UYVY: "101"

input YUYV, output YVYU: "001"
input YVYU, output YVYU: "000"
input UYVY, output YVYU: "111"
input VYUY, output YVYU: "110"

input YUYV, output VYUY: "011"
input YVYU, output VYUY: "010"
input UYVY, output VYUY: "101"
input VYUY, output VYUY: "100"

Decimation will reorder data flow also. Input UYVY becomes YUVY after decimation. This reorder is corrected using Bit 26 infomation. "0"= Cropping Disabled.
"1"= Cropping Enabled.
Note: this bit should set to '0' when bit field "DataFormat" is "10" (compressed data) In Bist Mode, FIFO RAM are read and write by its address, FIFO mode is disabled. Debug only. A RGB565 test card is sent to system bus instead of real data from sensor. '1' = FIFO over-write IRQ status.
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = VSYNC rising edge IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = VSYNC falling edge IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = DMA Done IRQ status
Write to corresponding bit in IRQ CLEAR register will clear this bit. '1' = FIFO Empty status, not clear-able. Read in the receive FIFO '1' = FIFO over-write enable '1' = VSYNC rising edge enable '1' = VSYNC falling edge enable '1' = DMA Done enable Write '1' to clear FIFO over-write interrupt Write '1' to clear VSYNC rising edge interrupt Write '1' to clear VSYNC falling edge interrupt Write '1' to clear DMA Done interrupt '1' = FIFO over-write cause '1' = VSYNC rising edge cause '1' = VSYNC falling edge cause '1' = DMA Done cause Power down pin of CMOS sensor . Reset pin of CMOS sensor.
Active Low. For the software to clear FIFO. This bit is auto-reset to 0. Power down pin of CMOS sensor . Reset pin of CMOS sensor. start pixel of cropped window. end pixel of cropped window. start line of cropped window. end line of cropped window. swap camera data output [15:0],[31:16]. spi slave enable. spi master enable. yuv out format. 3'b000: data_serial_mux = {Y0,U0,Y1,V0}; 3'b001: data_serial_mux = {Y0,V0,Y1,U0}; 3'b010: data_serial_mux = {U0,Y0,V0,Y1}; 3'b011: data_serial_mux = {U0,Y1,V0,Y0}; 3'b100: data_serial_mux = {V0,Y1,U0,Y0}; 3'b101: data_serial_mux = {V0,Y0,U0,Y1}; 3'b110: data_serial_mux = {Y1,V0,Y0,U0}; 3'b111: data_serial_mux = {Y1,U0,Y0,V0}; overflow rstn only vsync low. overflow_observe_only_vsync_low. overflow_rstn enable big_end_dis overflow inv control href inv control vsync inv control block_num_per_line[9:0] pixels num of a line line_num_per_frame[9:0] lines num of a frame camera_clk_div_num cts_spi_master_reg ssn_cm inv control sck_cm inv control ssn_spi_oen select, 1:from reg 0: from logic ssn_spi_oenb reg sck_spi_oenb select, 1:from reg 0:from logic sck_spi_oenb reg sdo_spi_swap reg,swap camera_spi_0 and camera_spi_1 clk inv control sck double edge enable ssn_wait_length[7:0] init_wait_length[7:0] word_num_per_block[7:0] ssn_cs_delay[1:0] data_receive_choose_bit[1:0] ready_cs_inv ssn_cs_inv eco_bypass_isp line_wait_length[15:0] line_wait_length block_wait_length[7:0] ssn_high_length[7:0] camera_spi_master no ssn mode enable sdo_line_choose_bit[1:0] 0:1 line 1: 2lines 2:4lines data_size_choose_bit 1: from reg 0:from logic image_height_choose_bit 1: from reg 0:from logic image_width_choose_bit 1: from reg 0:from logic block_num_per_packet[9:0] 0: spi data0 delay 0 1: spi data0 delay 2 cycles spi_cam_clk 2: spi data0 delay 3 cycles spi_cam_clk 3: spi data0 delay 4 cycles spi_cam_clk 0: spi data1 delay 0 1: spi data1 delay 2 cycles spi_cam_clk 2: spi data1 delay 3 cycles spi_cam_clk 3: spi data1 delay 4 cycles spi_cam_clk sync code packet_id_data_start packet_id_line_start packet_id_frame_end packet_id_frame_start line_id[15:0] data_id[7:0] observe_data_size_wrong observe_image_height_wrong observe_image_width_wrong observe_line_num_wrong observe_data_id_wrong image_height[15:0] image_width[15:0] num_d_term_en[7:0] term time reg cur_frame_line_num[12:0] data_lp_in_choose_bit[1:0] clk_lp inv trail_data_wrong_choose_bit 1:secelt trail1 0:select trail0 sync_bypass rdata_bit_inv en hs_sync_find en line_packet_enable ecc_bypass data_lane_choose_bit 1:select lane2 0:select lane1 csi_module_enable num_hs_settle[7:0] set hs settle time lp_data_length_choose_bit[2:0] set data length data_clk_lp_posedge_choose[2:0] select delay cycles clk_lp_ck_inv rclr_mask_en rinc_mask_en hs_enable_mask_en den_csi_inv_bit hsync_csi_inv_bit vsync_csi_inv_bit hs_data2_enable_reg hs_data1_enable_reg hs_data1_enable_choose_bit hs_data1_enable_dr 1:select reg 0:select logic data2_terminal_enable_reg data1_terminal_enable_reg data1_terminal_enable_dr 1:select reg 0:select logic lp_data_interrupt_clr, clear flag lp_cmd_interrupt_clr, clear flag lp_data_clr, clear data out lp_cmd_clr, clear cmd out num_hs_settle_clk[15:0], set hs settle counter num_c_term_en[15:0],set clk term counter clk_lp_in_choose_bit pu_lprx_reg pu_hsrx_reg pu_dr, 1:select reg 0:select logic data_pnsw_reg hs_clk_enable_reg hs_clk_enable_choose_bit hs_clk_enable_dr 1:select reg 0:select logic clk_terminal_enable_reg clk_terminal_enable_dr 1:select reg 0:select logic observe_reg_5_low8_choose ecc_error_flag_reg ecc_error_dr csi_channel_sel two_lane_bit_reverse, reverse high and low 8bit data2_lane_bit_reverse 1:select revert data data1_lane_bit_reverse 1:select revert data data2_hs_no_mask 1:data only valid when sync assert data1_hs_no_mask 1:data only valid when sync assert pu_lprx_d2_reg pu_lprx_d1_reg clk_edge_sel clk_x2_sel single_data_lane_en 1:1lane 0:2lanes num_hs_clk_useful[30:0] hs clk useful counter num_hs_clk_useful_en vc_id_set[1:0] data_lp_inv fifo_rclr_8809p_reg fifo_wclr_8809p_reg hs_sync_16bit_8809p_mode d_term_small_8809p_en data_line_inv_8809p_en hs_enable_8809p_mode sp_to_trail_8809p_en trail_wrong_8809p_bypass rinc_trail_8809p_bypass hs_data_enable_8809p_mode hs_clk_enable_8809p_mode data_type_re_check_en sync_id_reg sync_id_dr csi_observe_choose_bit crc_error_flag_reg crc_error_flag_dr 1:select reg 0:select logic csi_rinc_new_mode_dis data_type_dp_reg[5:0], set data type data_type_le_reg line end type data_type_ls_reg line start type data_type_fe_reg frame end type data_type_fs_reg frame start type 1: only support raw8 0:support more type 1:select reg value data_lane_16bits_mode terminal_2_hs_exchage_8809p terminal_1_hs_exchage_8809p data2_terminal_enable_8809p_dr hs_data2_enable_8809p_dr csi_dout_test_8809p_en csi_dout_test_8809p[7:0] num_d_term_en[15:8] num_hs_settle[15:8] hs_data_state[13:0] phy_data_state[14:0] fifo_wfull_almost fifo_wfull fifo_wempty if observe_reg_5_low8_choose=1, out is data_id[7:0], else out is lp_cmd_out[7:0] lp_data_interrupt_flag lp_data_interrupt_flag phy_clk_state[8:0] fifo_rcount[8:0] crc_error err_ecc_corrected_flag err_data_corrected_flag err_data_zero_flag if observe_reg_5_low8_choose=1, out is csi_observe_mon, else out is lp_data_out[63:32] csi_observe_reg_7[31:0] csi_enable dly_sel_clkn_reg,set clkn delay,to csi analog phy dly_sel_clkp_reg,set clkp delay,to csi analog phy dly_sel_data2_reg,set data2 delay,to csi analog phy dly_sel_data1_reg,set data1 delay,to csi analog phy vth_sel,to csi analog phy Direct FIFO Ram Access. They are enabled only in Bist Mode. rstn of dsp for A ctd block, u2.7 format awb_x1_min[8:0]=[awb_ctd_msb[0],awb_x1_min[7:0]] for A ctd block, u2.7 format awb_x1_max[8:0]=[awb_ctd_msb[1],awb_x1_max[7:0]] for A ctd block, u1.7 format for A ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for TL84 ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for CWF ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for Indoor ctd block, u1.7 format for D65 ctd block, u1.7 format for D65 ctd block, u1.7 format for D65 ctd block, u2.7 format awb_y5_min[8:0]=[awb_ctd_msb[2],awb_y5_min[7:0]] for D65 ctd block, u2.7 format awb_y5_max[8:0]=[awb_ctd_msb[3],awb_y5_max[7:0]] for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for TL84 skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format for CWF skin ctd block, u1.7 format awb_x1_min[8:0]=[awb_x1_min_msb,awb_x1_min[7:0]] awb_x1_max[8:0]=[awb_x1_max_msb,awb_x1_max[7:0]] awb_y5_min[8:0]=[awb_y5_min_msb,awb_y5_min[7:0]] awb_y5_max[8:0]=[awb_y5_max_msb,awb_y5_max[7:0]] 2d0: awb_adj_sig=1 2d1: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 or cbsum_abs>vld_cnt_cb_thr x2 2d2: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x3 or cbsum_abs>vld_cnt_cb_thr x3 2d3: awb_adj_sig= crsum_abs>vld_cnt_cr_thr x2 and cbsum_abs>vld_cnt_cb_thr x2 2d3: awb_ratio_lmax=4 2d2: awb_ratio_lmax=2 2d1: awb_ratio_lmax=0 2d0: awb_ratio_lmax= according to the proportion of cnt_max and cnt_lmax vsync_end_reg=[vsync_end_high,vsync_end_low] vsync_end_reg=[vsync_end_high,vsync_end_low] line_num = [line_numH,line_numL] pix_num = [pix_numH,pix_numL] not used here not used here 00:YUV/RAW8(para) 01:RAW8(mipi) 10:RAW10(mipi) line_cnt=[line_cnt_H[1:0], [7:0]] line_cnt=[line_cnt_H[1:0], line_cnt_L] 1: kl 0: kldci () 1: kl 0: kldci 1: ku 0: kudci () 1: ku 0: kudci hist 2 00: 0x98regae_dark_hist_reg 01: 0x98regyave_target_RO_reg other: 0x98regyave_contr_reg kl_ofstx1[4:0] = [kl_ofstx1, 1b0] (kl0x80) ku_ofstx1[4:0] = [ku_ofstx1, 1b0] (kl0x80) dk_histx1[4:0] = [dk_histx1, 1b0] (dhist) br_histx1[4:0] = [br_histx1, 1b0] (bhist) swaeswexp/gainnexphw// sw/hwae,SWae, THR_dark[4:0] = [THR_dark, 1'b0] (ytarget-yave THR_darkae) THR_bright[4:0] = [THR_bright,1'b0](yave-ytargetTHR_brightae) ytarget_dec 2d3:4indexytargetregd[3:0]8index08 2d2:2indexytargetregd[3:0]8index016 2d1:1indexytargetregd[3:0]8index032 2d0:1indexytargetregd[3:0]8index064 ytarget_dec 2d3:4indexytargetregc[7:4]8index_max8 2d2:2indexytargetregc[7:4]8index_max16 2d1:1indexytargetregd[7:4]8index_max32 2d0:1indexytargetregd[7:4]8index_max64 1yave_diff_2frame 1THR_big 1bhist>0@is_dark 1index_ofst @nexp @nexp low_th = [[0], lsc_blc_gain_th[7:6]](nexp=low_th) nexp>(8+high_th) Fixed Ythr of contr = [[7:4], 4d0] 1: dynamic yave (Yave) 0: fixed ythr contr_ythr_reg YaveYthrofst (01) upper@Low gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@Low gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 upper@Mid gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@Mid gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 upper@High gain Yout = Yin +/- min(ku*(Yin-Ythr), ku*(255-Yin)) 1: 0 lower@High gain Yout = Yin -/+ min(kl*(Ythr-Yin), kl*Yin) 1: 0 @Low gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 @Mid gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 @High gain 1: Yout = (256-offset)*Yin/256 + offset 0: Yout = Yin + offset 0 1 Cb@Low gain0x80 just x1.0 Cr@Low gain0x80 just x1.0 Cb@Mid gain0x80 just x1.0 Cr@Mid gain0x80 just x1.0 Cb@High gain0x80 just x1.0 Cr@High gain0x80 just x1.0 @luma/contr/satur(nexp=low_th) not used here @luma/contr/satur(nexp>(8+high_th)) 4'd0: cc_type = 0; //D65 4'd1: cc_type = 1; //U30 4'd2:if(is_outdoor) cc_type = 0; else cc_type = 1; 4'd3:if(ana_gain>=cc_gain_th) cc_type = 0; else cc_type = 1; 4'd4:if(rgain_bigger) cc_type = 0; //D65 else if(bgain_bigger) cc_type = 1; //U30 4'd5: if(is_outdoor) cc_type = 0; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd6: if(is_outdoor) cc_type = 0; else if(ana_gain=cc_gain_th) cc_type = 0; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd7: if(is_outdoor) cc_type = 0; else if(ana_gain=cc_gain_th) cc_type = 1; else if(rgain_bigger) cc_type = 0; else if(bgain_bigger) cc_type = 1; 4'd8: if(r_awb_gain_outr_low_non_A)cc_type = 1; else if(r_awb_gain_out(r_low_non_A+8)) cc_type = 0; 4d9: if(awb_idx_max2) cc_type = 1; else if(awb_idx_max2) cc_type = 0; other: SW driven ( reg1c2) nexp>(8+high_th) 1: 0: r_big_th=[awb_cc_type_th_reg[3:0], 2d0] b_big_th=[awb_cc_type_th_reg[7:4], 2d0] 00: YUV422 01: RGB565 10: raw bayer 11: clip out 00:YUYV 01:YVYU 10:UYVY 11:VYUY (Note:[2] uv_sel 0:UV 1:VU) Case(rgb_mode_reg) @clip out 3'd0: to_n_clp_data 3'd1: y_data 3'd2: cnr_1d_cb 3'd3: cnr_1d_cr 3'd4: c_data 3'd5: yc2r_data 3'd6: yc2g_data 3'd7: yc2b_data Note:rgb_mode_reg[0] is also used to 1, select the line of sub_YUV output not used, sca_reg=1:sub mode bypass vsync_in and hsync_in Line_num=[lin_num_l_reg[5:0], 3d0] Pix_num=[pix_num_l_reg[6:0], 3d0] HsyncNvsync Mvsync top_dummy>16, vtop_dummy=top_dummy-[7:4] 1blc[ku, kl] 1:nexp[3:0] 0:mono_color 1: dpc_out 0: bayer_data 1: enable 0: disable y_gamma_en = is_outdoor ? scg_reg[5] : scg_reg[4] 1: SDI 0: BT.601 1: [ae_ok, nexp_sel[1:0], awb_ok, exp[11:8]] 0: [ae_ok, 1b0, nexp_sel[1:0], awb_ok, exp[10:8]] labview (0x00)0 (0x00)0 (0x00)0 (0x13)19 (0x10)16 (0x08)8 (0x20)32 (0x1c)28 (0x10)16 (0x36)54 (0x30)48 (0x20)32 (0x49)73 (0x43)67 (0x30)48 (0x5a)90 (0x54)84 (0x40)64 (0x6b)107 (0x65)101 (0x50)80 (0x7b)123 (0x75)117 (0x60)96 RW(0x98)152 (0x93)147 (0x80)128 (0xb4)180 (0xb0)176 (0xa0)160 (0xce)206 (0xcb)203 (0xc0)192 (0xe7)231 (0xe6)230 (0xe0)224 0.75 0.8 1.0 r_gain_manual 2.6 format g_gain_manual 2.6 format b_gain_manual 2.6 format 2.6 format 2.6 format 2.6 format 2.6 format also update cc_type,gamma_type,is_outdoor 00: AWB 01: AWB 10: yaveAWB 11: nexpAWB 1: mon ae index 0:mon awb_debug 0yave 1yave 2yave 3yave 07/0f/17/1f Yave 00: y2ave x1.0 01: y2ave x1.5 10: y3ave x1.0 11: y3ave x1.5 1:plus bh 0: only yave 1:plus bh 0: only ywave pcnt_left =[ae_win_start_reg[3:0] ,1'd0] lcnt_top =[ae_win_start_reg[7:4] ,1'd0] ae(yave) win_width = [ae_win_width[7:0], 2'd0] ae(yave) ae_win_height = [ae_win_height[7:0], 1'd0] exp[7:0](ae_enMCUexp_init[6:0]indexae) exp[11:8] 10msexp (ytarget) THR_dark(reg41) THR22index1 THR24index2 THR26index4+ofst0 THR28index8+ofst1 index16 (ytarget) THR_bright(reg41) THR22index1 THR24index2 THR26index4+ofst0 THR28index8+ofst1 index16 Bh = Bh_mean * bh_factor /8 bh_factor = is_outdoor? bh_factor_outdoor : bh_factor_indoor 00: curr frame 01: 2 frame ave 10: 3 frame ave 11: 4 frame ave awb_mon_out[7:0][cbsum_abs_eq, crsum_abs_eq]SWAWB 2.0xr/b 4.0xr/b 0: 1frame or 2frame [ 2] 0:readback blc 1: readback awb [1:0] 0: crsum_abs 1:cbsum_abs 2: vld_cnt 3:awb_idx_lmax and max AWB 3'd0:awb_vld=vld_max||(vld_lmax and awb_ratio_lmax); 3'd1: awb_vld = awb_vld1; 3'd2: awb_vld = awb_vld2; 3'd3: awb_vld = awb_vld3; 3'd4: awb_vld = awb_vld4; 3'd5: awb_vld = awb_vld5; 3'd6: awb_vld =!skin_vld; 3'd7: awb_vld = awb_vld1|awb_vld2|awb_vld3| awb_vld4 | awb_vld5; Y Y_maxAWB Levelawb_stop Levelawb_stop Levelawb_stop Levelawb_stop [7:0]awb_algo_thr Y > cr_abs+cb_abs+awb_algo_reg // 0: (vld_cntawb_vld_thr) 1: (vld_cntawb_vld_thr)and(crsum_absawb_vld_thr)and(cbsum_absawb_vld_thr) 0: awb_stopcb/cr 1: 0: use CTD block to detect skin 1: use cb,cr to detect skin 0: cb+cr 1: cb/cr awb_vld_thr = [awb_ctrl4[7:0], 4'hf] 1: 0 y_low_thr = [1h0, y_thr_reg[7:3], 2'h0] y_high_thr = ~y_low_thr Only for awb_adj, yaveAWB y_low_limit = y_ave_target - [y_lmt_offset_reg[2:0],4'd0] not used here Only for awb_adj, yaveAWB y_high_limit = y_ave_target+ [y_lmt_offset_reg[6:4],4'd0] nexp=low_th not used here nexp>(8+high_th) yave_target (yave_target0) yave_target (yave_target0) not used here 1reg93vbright_hist 1reg94vdark_hist display edge pixel for sharpness Ywave+bhist histYwave bright hist Yave+bhisthistYave exp_out[10:8] nexp_selbnr/dpc/int_dif 00: cr_lt_1x 01: cr_gt_1x 10: cr_gt_2x 11: cr_gt_4x 00: cb_lt_1x 01: cb_gt_1x 10: cb_gt_2x 11: cb_gt_4x 0:crsum (5R B+4G) 1:crsum (5R B+4G) 0:cbsum (3B R+2G) 1:cbsum (3B R+2G) 0: crsum_abs cbsum_abs (crsum) 1: crsum_abs cbsum_abs (cbsum) ae_index Note: regd[5]? ae_vbright_hist : reg75[7]? ae_index[6:0] : awb_debug; YUVnexp vdark_hist Note: regd[6]? ae_vdark_hist : reg5F[1]? nexp[3:0] : mono_color yavehist Vbh_sel[1]? Yave_contr_reg : Vbh_sel[0]? Yave_target_RO_reg : ae_dark_hist NoteVbh_sel[1:0] = reg3d[7:6] 3d0: gamma_type=0 3d1: gamma_type=1 3d2: gamma_type=is_outdoor 3d3: gamma_type=ana_gain>=gamma_gain_th default:gamma_type=gamma_type_sw nexp>(8+high_th) 00:QVGA 240x320 01:QVGA 320x240 10:CIF 352x288 11:VGA 640x480 line_sel = [line_init_H, blc_line_reg[7:0]] lsc gain@ lsc gain@ nexp=low_th nexp>(8+high_th) low_th = [csup_gain_low_th_H, [7:6]](nexp=low_th) 2'd0: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_01] 2'd1: [blc_out0_reg,blc_out1_reg] = [blc_10, blc_11] 2'd2: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_10] 2'd3: [blc_out0_reg,blc_out1_reg] = [blc_00, blc_11] 0: plus 1: minus 00: 1frame 01: 2frame ave 10: 3frame ave 11: 4frame ave blc00_ofst =[blc_init_reg[3:0] , 1'b0] blc01_ofst =[blc_init_reg[7:4] , 1'b0] blc10_ofst =[blc_offset_reg[3:0] , 1'b0] blc11_ofst =[blc_offset_reg[7:4] , 1'b0] High limit of black level pixel blcofst y_cent=[3:0]+240 x_cent=[7:4]+320 CNR CNR 1: 0: edge monitor 3d0: never skip 3d1: skip 2/8 skin point 3d2: skip 3/8 skin point 3d3: skip 4/8 skin point 3d4: skip 5/8 skin point 3d5: skip 6/8 skin point 3d6: skip 7/8 skin point 3d7: skip 8/8 skin point cnr_thr_v = [cnr_thr[2:0], 2'd3] enable cnr_thr_h = [cnr_thr[6:4], 2'd3] enable ~awb_mon_sel? blc_out0_reg : kukl_sel ? kl : awb_mon_out[7:0] ~awb_mon_sel? blc_out1_reg : kukl_sel ? ku : awb_mon_out[15:8] Note: awb_mon_sel = reg1[2] Kukl_sel = reg5F[0] dpc on 1: median 0:adp_median sel=(nexp[3:0]>dpc_ctrl0[3:2])? 1 : dpc_ctrl0[1] This adp_med is used in int_dif_data and nrf_data_out not used here 1:gausian filter 0:median filter bayer nr on cc on 00: always not meet 01: all round point must meet 10: can be one except point 11: can be two except point 00: can be three sign diff with other 01: can be two sign diff with other 10: can be one sign diff with other 11: 8 same sign 1: gausian filter 0:median filter Y_thr @ Y_thr @mid Y_thr @ cfa_v_thr[2:0] not used here cfa_h_thr[2:0] not used here 0: inc 1:dec nexp=low_th @bnr/dpc/int_dif/sharp/cnr not used here nexp>(8+high_th) @bnr/dpc/int_dif/sharp/cnr bnr low frequency str @Low gain @ (ff) bnr high frequency str @Low gain (ff) 4.4 format, 16x ~ 1/16x @Low gain HF bnr low frequency str @Mid gain (ff) bnr high frequency str @Mid gain (ff) 4.4 format, 16x ~ 1/16x @Mid gain HF bnr low frequency str @high gain @ (ff) bnr high frequency str @high gain (ff) 4.4 format, 16x ~ 1/16x @high gain HF 0: 9 1:7 2: 5 3:3 4: median 5: adp_median cfa_h_thr=[intp_cfa_h_thr[7:0], intp_cfa_hv[6:4]] cfa_v_thr=[intp_cfa_v_thr[7:0], intp_cfa_hv[2:0]] gf_lmt_thr=[3d0, intp_gf_lmt_thr_reg] S7 format, before cc S7 format, before cc S7 format, before cc S1.6 format, x1=64, cc00+cc01+cc02=1 S1.6 format, x1=64, cc10+cc11+cc12=1 S1.6 format, x1=64, cc20+cc21+cc22=1 S7 format, after cc S7 format, after cc S7 format, after cc S7 format, before cc S7 format, before cc S7 format, before cc S1.6 format, x1=64, cc00+cc01+cc02=1 S1.6 format, x1=64, cc10+cc11+cc12=1 S1.6 format, x1=64, cc20+cc21+cc22=1 sharp data db/da/d9 sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) 0: delay_df 1: delay_de 2: delay_dd 3: delay_dc 1:ppdif_sum 0:pp_dif (8) plus @Low gain (2.6 format)@ Sharp@Low gain (edge) plus @Mid gain (2.6 format) Sharp@Mid gain (edge) plus @high gain (2.6 format)@ Sharp@high gain (edge) (Ey) 2d0:Ey_H/V/D1/D2 2d1: 2d2: 2d3: (sharpness) 00: if(i_y_data8'ha0) sharp_data = sharp_out[6:2]; else if(i_y_data8'h80) sharp_data = sharp_out[6:1]; else sharp_data = sharp_out[6:0]; 01: 0x80pixelsharpness 10: 0x90pixelsharpness 11: No change AEYin 00:y=yuv_y 01:y=y_gamma // after ygamma 10:y=luma_y_out // after y_luma 11:y=contr_y_out // after y_contr GMYc @low gain GMYc128Ey @low gain GMYc128Ey 4.4 format, 16x ~ 1/16x @low gain HF @Mid gain GMYc128Ey @Mid gain GMYc128Ey 4.4 format, 16x ~ 1/16x @Mid gain HF @high gain GMYc128Ey @high gain GMYc128Ey 4.4 format, 16x ~ 1/16x @high gain HF sinx[7:0]=256*sin(x*pi/180) cosx[7:0]=256*cos(x*pi/180) cosx[7] fixed as 1, As abs(x) = pi/4 1: sinx is negative 0: sinx is positive CNR@Mid gain CNR@Low gain CNR@High gain Center point smaller than around, black point Center point bigger than around, white point E00 E00 E00 max is 3Line E01 E01 E01 max is 7Line E02max is 7F E02 E02 max is 15Line E1 (64) E1 (1E) E2 (64) E2 (2E) E3 (64) E3 (3E) E4 (64) E4 (4E) E5 (64) E5 (5E) E6 (64) E6 (6E) E7 (64) E7 (7E) E8 (64) E8 (8E) E9 (64) E9 (9E) Ea (64) Ea (aE) Eb (64) Eb (bE) Ec (64) Ec (cE) Ed (64) Ed (dE) Y_thr7 (for 2 dead point) @ Y_thr7 (for 2 dead point) @ mid Y_thr7 (for 2 dead point) @ 0: check one black dead point 1: don't check one black dead point 0: check 2 black dead point 1: don't check 2 black dead point 0: don't check 2 dead point 1: check 2 dead point (Note) 0: check one black dead point 1: don't check one black dead point (Note) 0: check 2 black dead point 1: don't check 2 black dead point (Note) 0: don't check 2 dead point 1: check 2 dead point not used here 2E 12 3E 12 4E 12 5E 12 6E 12 7E 12 8E 12 9E 12 awb_win_height = [[7:0],1'd0] //4:3 and keep height as even number blue: 0x72 red: 0xD4 brown:0xAB blue: 0xD4 red: 0x64 brown:0x60 0x20~ff (x1~8) () 0x20~ff (x1~8) () If bhist>bhist_too_big_thr, then bhist_too_big If bhist>bhist_big_thr, then bhist_big Y level of bhist and 4pbhist outdoor_th=[outdoor_th_reg[3:0], 4'd0] non_outdoor_th=[outdoor_th_reg[7:4], 4'd0] Low limit of rgain = [[7:2], 2d0] High limit of rgain = [[7:2], 2d0] Low limit of bgain = [[7:2], 2d0] High limit of bgain = [[7:2], 2d0] awb_win_y_start = [[3:0], 2'd0]; awb_win_x_start = [[7:4], 2'd0]; awb_win_width =[[7:0],2'd0]; //4:3 and keep height as even number Y level of dark_hist for skin for skin for skin for skin for skin for skin for mono color for mono color for mono color for mono color for mono color for mono color 0yave 1yave 2yave 3yave 0yave 1yave 2yave 3yave 0: win yave 1: ywave ae ywave ae ywave QVGA 240x320 :8d60 QVGA 320x240: 8d80 CIF 352x288: 8d88 VGA 640x480: 8d160 QVGA 240x320 :8d80 QVGA 320x240: 8d60 CIF 352x288: 8d72 VGA 640x480: 8d120 0: x1(CIFx1) 1:x1.5 yave pcnt_sta=[[3:0], 1b0] yave lcnt_sta=[[7:4], 1b0] yave Width=[[7:0], 2d0] QVGA 240x320 :10d216 QVGA 320x240: 10d304 CIF 352x288: 10d304 VGA 640x480: 10d596 yave Height=[[7:0], 1d0] QVGA 240x320 :10d304 QVGA 320x240: 10d216 CIF 352x288: 10d216 VGA 640x480: 10d440 not used here 3'd0: is_outdoor = 0; 3'd1: is_outdoor = 1; 3'd2: if(ana_gain==0) begin if(expoutdoor_th) is_outdoor = 1; else if(expnon_outdoor_th) is_outdoor = 0; end else is_outdoor = 0; 3'd3: if(ana_gain==0 and rgain_bigger) begin if(expoutdoor_th) is_outdoor = 1; else if(expnon_outdoor_th) is_outdoor = 0; end else is_outdoor = 0; default: if(vsync_rp_d and sw_update_en) is_outdoor = is_outdoor_sw; 1: when is_outdoor=1, only detect white point at D65 and Indoor CTD block 0: dont care is_outdoor, detect white point at all ctd block awb_stop_cr_pos_level =[[3],awb_stop_reg[7:6]]; awb_stop_cr_neg_level =[[2],awb_stop_reg[5:4]]; awb_stop_cb_pos_level =[[1],awb_stop_reg[3:2]]; awb_stop_cb_neg_level =[[0],awb_stop_reg[1:0]]; awb_adj_again = [2'b11, [5:4]] 1: add awb_algo_thr condition to detect white point@A 0: detect white point according to A ctd block 0: normal(no scale) 1: sub(yuv sub mode) 2: sca_320x240(1/2) 3: sca_176x144(1/3) 4: sca_160x120(1/4) 5: sca352x288(2/3) 6: sca352x288(3/5) 7: 3/4 Ee (64) Ee (eE) Ef (64) Ef (fE) ae_thr_big = [reg1CA[3:0],2d0]@dark ae_thr_big = [reg1CA[7:4],2d0]@bright sharp gain @low gain(2.6 format) sharp gain @medium gain(2.6 format) sharp gain @high gain(2.6 format) sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) sharp_cmp> (sharp_nr_area_thr[6:0]+sharp_cmp_gap) Y = Y_min ( AWB) Y level of vbright_hist Y level of vdark_hist adi low bits version. adi high bits version,read only. addr mode for access. "00" word mode,means addr[x:2],"01" half word,means addr[x:1], "1x" byte mode, means addr[x:0]. configure write bit flag. addr bit number configure, "00" address is 12 bits, "01" address is 10 bits, "10" address is 15 bits. "1" write uses command mode, in this mode, must first configure channel addr, then data. write channel 0 priority. 0 has lowest priority, 4 has highest priority. read channel 1 priority. 0 has lowest priority, 4 has highest priority. read channel 2 priority. 0 has lowest priority, 4 has highest priority. read channel 3 priority. 0 has lowest priority, 4 has highest priority. read channel 4 priority. 0 has lowest priority, 4 has highest priority. read channel 5 priority. 0 has lowest priority, 4 has highest priority. "1" write command fifo enable. fifo overfolow interrupt mask. fifo overfolow interrupt without mask status. fifo overfolow interrupt with mask status. fifo overfolow interrupt clear. total adi frame length = rf_gssi_cmd_len + rf_gssi_data_len. total adi cmd length = rf_gssi_addr_len + read/write flag. total adi data length . write bit position in frame stream . "1" write means 1, "0" write means 0. "1" hardware auto generate sync, "0" software generates sync. "1" sync is pulse, "0" sync is level. "1" software generates sync. "1" invert output sck. output oen : "1" oen add dummy cycle, "0" oen not add dummy cycle. reserved. "1" output dummy_clock, "0" gate dummy clock. "1" rx sample delay 1 adi clk cycle, "0" delay 0 adi clk cycle. "1" sck always on, "0" audo gate clock. "1" write bit disable, "0" write bit enable. "1" tx data at negedge of sck."0" tx data at posedge of sck. "1" rx data at negedge of sck."0" rx data at posedge of sck. F_sck = F_clk/(2*(rf_gssi_clk_div+1)) sync before data transfer sync end data transfer extral dummy sck extral dummy sck start sequence condition, only used in RFFE master turn around to salve length , only used in RFFE slave turn around to master length , only used in RFFE "1" 2 wires enable configure read address and start a read operation. read data from analog die. read address map to arm_red_cmd[16:2]. 1 means has not been read back. "1" write channel is busy "1" read channel is busy "1" adi operation is busy wfifo full status wfifo empty status wfifo fill data number adi fsm status event 0 wr status event 1 wr status event 2 wr status event 3 wr status the address map to the PMIC chip space, just for write operation the dat to the PMIC chip space, just for write operation freq/26*2^25 768Mhz 800Mhz 1: clk_datarx 0: inv of clk_datarx 1: enable rst intepolator by squelch 0: disable rst by squelch default: 1'h0 tx clk samle data phase set cdr gain internal bias current internal bias voltage squelch threshold voltage disconnect threshold voltage hi-speed differential signal voltage if charged(1: squelch threshold voltage is reduced;0 hold) 1: differential signal 0: single-end signal 1: differential signal 0: single-end signal 1: internal reference voltage 0: bandgap voltage 1: enable otg 0: disable otg 1: set vbusvld to 1'h1; 0: not set if pwr_on=01:pullup and pulldown circuit power on;0 off) 1:pullup and pulldown circuit power always on 0:power is controled by pu_usb_dev 1:enable disconnect dectector circuit 0:dsiable 1:enable 1.8V voltage 0:dsiable 1:enable 1.2V voltage 0:dsiable 1:enable current generator circuit 0:disable 1:enable hi-speed rx 0 disable 1:enable hi-speed tx 0 disable 1:enable full/low-speed tx 0 disable enable charger ac detect 1: loopback data to tx 0: hi-speed data to tx enable loopback; loopback data RW 1:enable lptx bias 0: disable lptx bias(should lead power up of avdd3v3) hi-speed term res full/low-speed tx driver strength; internal regulator's voltage bit,default:4'h1000 internal regulator rout bit loop filter R2 bit loop filter c2 bit loop filter r2 bit pll_presc mode selectdefault:1'h0 reference frequency select PLL TEST mode enable output clk select: 0 VCO 1 sdm_clk force VCO run at highest frequency force VCO run at lowest frequency enable 960MHz clk output loopback test output pll lock signal pll lock signal to UTMI reserved for USB 960Mhz freq/26*2^25 1000Mhz reserved 2 dedicated enable for 2 DL HSSBs, bit0-lane0, bit1-lane1 2 dedicated enable for 2 UL HSSBs, bit0-lane0, bit1-lane1 DL FIFO reset and clear UL FIFO reset and clear SYNC WORD for lvds dest SYNC WORD for lvds src bit reverse enable bit offset index used in byte training stage for lane0 bit offset index used in byte training stage for lane1 Byte Training Done from SW Bit Training Done from SW data ready from DFE for ulfifo to lvds Payload max length for timeout check, 0-disabled Sync max length for timeout check, 0-disabled LVDS tx fixed pattern instead of data from ulfifo LVDS tx fixed pattern0[31:0] LVDS tx fixed pattern1[31:0] [1]: 0-2 cycles per word , 1-1cycle per word for LVDS_TX [0]: 0-2 cycles per word , 1-1cycle per word for LVDS_RX 0-mode0, 1-mode1, 2-mode2, 3-mode3 for tx 0-mode0, 1-mode1, 2-mode2, 3-mode3 for rx number of cycles to read from Fifo under MT mode for both tx number of cycles to read from Fifo under MT mode for both rx [3]: 0- Non-MT mode, 1-MT enable for rx [2]: 0- Non-MT mode, 1-MT enable for tx [1]: 0-1x clock, 1-2x clock for rx [0]: 0-1x clock, 1-2x clock for tx bit training Done for lvds tx byte training Done for lvds tx report bit or byte training results word0 for lane0 report bit or byte training results word1 for lane0 report bit or byte training results word0 for lane1 report bit or byte training results word1 for lane1 dest_lane1_fstate dest_lane0_fstate dest_lane1_state dest_lane1_mstate dest_lane0_state dest_lane0_mstate src_lane1_state src_lane1_mstate src_lane0_state src_lane0_mstate reserved register for lvds bb [15]: for RX, 1-use SW configure Sync index enable, 0-use HW anto sync detection [14]: for TX, 1-use SW configure Sync index enable, 0-use HW anto sync detection [13]: for RX, 1-use LFSR for BIST , 0-use normal data for RX [12]: for TX, 1-use LFSR for BIST , 0-use normal data for TX configure register for lvds used by IQMUX: [15:12]: reserved [11]: software reset for LVDS digital TX [10]: software reset for LVDS digital RX [9]: software reset for LVDS analog TX [8]: software reset for LVDS analog RX [7:3]: reserved [2]: clock gating enable for MT clock divided from mt2lvds@61.44MHz clock. [1]: clock gating enable to LVDS digital rx related clocks [0]: clock gating enable to LVDS digital tx related clocks Latch trigger for capturing 8 lvds received Bytes header to be received or transmitted for LVDS number of header to be received or transmitted for LVDS mstate and fstate machine rerport for lvds_rx debug purpose mstate and state machine rerport for lvds_tx debug purpose 16 bit counter for LVDS_RX PLL stable time wait 16 bit counter for LVDS_TX PLL stable time wait raw interrupt status, write 1 to clear interrupt status after masked raw interrupt status write 1 to clear interrupt raw interrupt source select raw interrupt mask for latch done number of errors for lvds lane0 bist enabled period 1: bist fail for lane0, 0: bist pass for lane0 number of errors for lvds lane1 bist enabled period 1: bist fail for lane1, 0: bist pass for lane0 reset for LVDS RX path, active low soft reset for LVDS TX path, active low reg for PLL divisor lvds_clk_band=3'b0001 with pll_din=7'h08 lvds_clk_band=3'b0010 with pll_din=7'h10 lvds_clk_band=3'b0100 with pll_din=7'h20 lvds_clk_band=3'b1000 with pll_din=7'h40 1st phase coarse tuning between TX_DATA and TX_CLOCK input P and N switch phase fine tuning between RX_DATA and RX_CLOCK phase coarse tuning between RX_DATA and RX_CLOCK RX BUFFER enable RX BUFFER select phase fine tuning between TX_DATA and TX_CLOCK 2nd phase coarse tuning between TX_DATA and TX_CLOCK LVDS DRIVER tri-state enable LVDS DRIVER strength adjust LVDS DRIVER output common mode voltage adjust LVDS DRIVER output difference mode voltage adjust LVDS reserved register [2:0]:pll_rx_clk_ref_dig [4]:pll_rx_clk_ref_dig_enable [20:18]:pll_rx_clk_ref_xtal [17]:pll_rx_clk_ref_xtal_enable enable for PLL reference clock being input clock divided by 2 PLL output clock enable set with lvds_clk_band PLL divisor decimal part,fixed to 0 PLL refmulit2 enable PLL Regulator voltage adjust PLL power up PLL lock status 0:unlock 1:lock PLL 1st reserved register PLL 2nd reserved register LVDS tx fixed pattern0[31:0] LVDS tx fixed pattern1[31:0] LVDS2DFE latch reg0 LVDS2DFE latch reg1 top bist en Internal Bootrom Space Internal SRam Space Number of Watchpoint Register Pairs: For the Cortex-A5 processor, this field reads as b0001 to indicate two WRPs are implemented. Number of Breakpoint Register Pairs: For the Cortex-A5 processor, this field reads as b0010 to indicate three BRPs are implemented. Number of Breakpoint Register Pairs with context ID comparison capability: For the Cortex-A5 processor, this field reads as b0000 to indicate one BRP has context ID capability. Debug architecture version: b0011 = ARMv7 Debug with Extended CP14 interface implemented. For the Cortex-A5 processor, this field reads as b1 to indicate that the Debug Device ID Register, DBGDEVID is implemented For the Cortex-A5 processor, this field reads as b1 to indicate that Secure User halting debug is not supported Program Counter Sample Register, DBGPCSR. For the Cortex-A5 processor, this field reads as b1 to indicate that DBGPCSR is implemented as debug register 33. Security extensions bit: For the Cortex-A5 processor, this field reads as b1 to indicate that the debug security extensions are implemented. Implementation-defined variant number. This number is incremented on functional changes. The value matches bits [23:20] of the ID Code Register in CP15 c0. Implementation-defined revision number. This number is incremented on bug fixes. The value matches bits [3:0] of the ID Code Register in CP15 c0. The DBGDTRRX Register full flag: 0 = DBGDTRRX empty, reset value 1 = DBGDTRRX full. When set, this flag indicates that there is data available in the Receive Data Transfer Register, DBGDTRRX. It is automatically set on writes to the DBGDTRRXext by the debugger, and is cleared when the processor reads the CP14 DBGDTRRXint. If the flag is not set, reads of the DBGDTRRX return an Unpredictable value. The DBGDTRTX Register full flag: 0 = DBGDTRTX empty, reset value 1 = DBGDTRTX full. When clear, this flag indicates that the Transmit Data Transfer Register, DBGDTRTX is ready for data write. It is automatically cleared on reads of the DBGDTRTXext by the debugger, and is set when the processor writes to the CP14 DBGDTRTXint. If this bit is set and the processor attempts to write to the DBGDTRTXint, results are Unpredictable. The latched DBGDTRRX Register full flag. This flag is read in one of the following ways: ? in DBGDSCRint using a CP14 instruction ? in DBGDSCRext using the APB interface or CP14 instruction. Reads of DBGDSCRint return an Unpredictable value for this bit. Reads of DBGDSCRext return the same value as RXfull. If a write to the DBGDTRRXext address succeeds, RXfull_l is set to 1. The latched DBGDTRTX Register full flag. This flag is read in one of the following ways: ? in DBGDSCRint using a CP14 instruction ? in DBGDSCRext using the APB interface or CP14 instruction. Reads of DBGDSCRint return an Unpredictable value for this bit. Reads of DBGDSCRext return the same value as TXfull. If a read to the DBGDTRTXext address succeeds, TXfull_l is cleared. Sticky pipeline advance bit. This bit enables the debugger to detect whether the processor is idle. In some situations, this might mean that the system bus port is deadlocked. This bit is set to 1 every time the processor pipeline retires one instruction. A write to DBGDRCR[3] clears this bit. See Debug Run Control Register on page 9-19. 0 = no instruction has completed execution since the last time this bit was cleared, reset value 1 = an instruction has completed execution since the last time this bit was cleared. The latched InstrCompl flag. This flag is read in one of the following ways: ? in DBGDSCRint using CP14 instructions ? in DBGDSCRext using the APB interface. When in Non-debug state, all reads of DBGDSCR return an Unpredictable value for this bit. Otherwise, reads through the CP14 interface return an Unpredictable value for this bit. Reads of the DBGDSCRext APB address return the same value as InstrCompl. If a write to the DBGITR APB address succeeds while in Stall or Nonblocking mode, InstrCompl_l and InstrCompl are cleared. If a write to the DBGDTRRXext APB address or a read to the DBGDTRTXext APB address succeeds while in Fast mode, InstrCompl_l and InstrCompl are cleared. InstrCompl is the instruction complete bit. This internal flag determines whether the processor has completed execution of an instruction issued through the APB interface. 0 = the processor is currently executing an instruction fetched from the DBGITR Register, reset value 1 = the processor is not currently executing an instruction fetched from the DBGITR Register. External DCC access mode. This is a read and write field. You can use this field to optimize DTR and DBGITR traffic between a debugger and the processor: b00 = Nonblocking mode, reset value b01 = Stall mode b10 = Fast mode b11 = reserved. Note ? This field only affects the behavior of DBGDSCR, DTR, and DBGITR accesses through the APB port, and not through CP14 debug instructions. ? Nonblocking mode is the default setting. Improper use of the other modes might result in the debug access bus becoming jammed. See External DCC and DBGITR access mode on page 9-17 for more information. Discard asynchronous abort. This read-only bit is set while the processor is in debug state and is cleared on exit from debug state. While this bit is set, the processor does not record asynchronous Data Aborts. However, the sticky asynchronous Data Abort bit is set to 1. 0 = asynchronous Data Aborts not discarded, reset value 1 = asynchronous Data Aborts discarded. Non-secure state status bit: 0 = the processor is in Secure state or the processor is in Monitor mode 1 = the processor is in Non-secure state and is not in Monitor mode. Secure privileged noninvasive debug disabled: 0 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is HIGH 1 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is LOW. This value is the inverse of bit [6] of the Authentication Status Register. See Authentication Status Register on page 9-33. Secure privileged invasive debug disabled: 0 = (DBGEN && SPIDEN) is HIGH 1 = (DBGEN && SPIDEN) is LOW. This value is the inverse of bit [4] of the Authentication Status Register. See Authentication Status Register on page 9-33. The Monitor debug-mode enable bit. This is a read and write bit. 0 = Monitor debug-mode disabled, reset value 1 = Monitor debug-mode enabled. If Halting debug-mode is enabled, bit [14] is set, then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGEN is LOW, DBGDSCR[15] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value. The Halting debug-mode enable bit. This is a read and write bit. 0 = Halting debug-mode disabled, reset value 1 = Halting debug-mode enabled. If the external interface input DBGEN is LOW, DBGDSCR[14] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value. Execute ARM instruction enable bit. This is a read and write bit. 0 = disabled, reset value 1 = enabled. If this bit is set and a DBGITR write succeeds, the processor fetches an instruction from the DBGITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable. CP14 debug user access disable control bit. This is a read and write bit. 0 = CP14 debug user access enable, reset value 1 = CP14 debug user access disable. If this bit is set and a User mode process tries to access any CP14 debug registers, the Undefined instruction exception is taken. Interrupts disable bit. This is a read and write bit. 0 = interrupts enabled, reset value 1 = interrupts disabled. If this bit is set, the IRQ and FIQ input signals are disabled. The external debugger can set this bit before it executes code in normal state as part of the debugging process. If this bit is set to 1, an interrupt does not take control of the program flow. For example, the debugger might use this bit to execute an OS service routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the routine execution. This bit is ignored when either: ? DBGDSCR[15:14] == 0b00 ? DBGEN is LOW. Debug Acknowledge bit. This is a read and write bit. If this bit is set to 1, both the DBGACK and DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The external debugger can use this bit if it wants the system to behave as if the processor is in debug state. Some systems rely on DBGACK to determine whether the application or debugger generates the data accesses. The reset value is 0. Sticky Undefined bit: 0 = No Undefined instruction exception occurred in debug state since the last time this bit was cleared. This is the reset value. 1 = An Undefined instruction exception has occurred while in debug state since the last time this bit was cleared. This flag detects Undefined instruction exceptions generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when an Undefined instruction exception occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19. Sticky asynchronous Data Abort bit: 0 = no asynchronous Aborts occurred since the last time this bit was cleared, reset value 1 = an asynchronous Abort occurred since the last time this bit was cleared. This flag detects asynchronous Aborts triggered by instructions issued to the processor through the DBGITR. This bit is set to 1 when an asynchronous Abort occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19. Sticky synchronous Data Abort bit: 0 = no synchronous Data Abort occurred since the last time this bit was cleared, reset value 1 = a synchronous Data Abort occurred since the last time this bit was cleared. This flag detects synchronous Data Aborts generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register on page 9-19. When this is set, no instructions are issued through the DBGITR. Writes to DBGITR are ignored and, if ExtDCCmode is configured for Fast mode, reads of DBGDTRTXext and writes of DBGDTRRXext are ignored. MOE, Method of entry bits. This is a read and write field. b0000 = a DRCR[0] halting debug event occurred, reset value b0001 = a breakpoint occurred b0010 = not supported b0011 = a BKPT instruction occurred b0100 = an EDBGRQ halting debug event occurred b0101 = a vector catch debug event occurred b1010 = a synchronous watchpoint debug event occurred other = reserved. These bits are set to indicate any of: ? the cause of a debug exception ? the cause for entering debug state. A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event. Core restarted bit: 0 = The processor is exiting debug state. 1 = The processor has exited debug state. This is the reset value. The debugger can poll this bit to determine when the processor responds to a request to leave debug state Core halted bit: 0 = The processor is in normal state. This is the reset value. 1 = The processor is in debug state. The debugger can poll this bit to determine when the processor has entered debug state. DBGVCR dtrrx old location of PCSR dtrrx Cancel BIU request Clear sticky pipeline advance. Writing a 1 to this bit clears DBGDSCR[25]. Clear sticky exceptions. Writing a 1 to this bit clears DBGDSCR[8:6]. Restart request. Writing a 1 to this bit requests that the processor leaves debug state. This request is held until the processor exits debug state. When the debugger makes this request, it polls DBGDSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is not in debug state. Halt request. Writing a 1 to this bit triggers a halting debug event, that is, a request that the processor enters debug state. This request is held until the debug state entry occurs. When the debugger makes this request, it polls DBGDSCR[0] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is already in debug state. The sampled value of bits [31:2] of the Program Counter Meaning of Program Counter Sample value: b00 = References an ARM state instruction. bx1 = References a Thumb or ThumbEE state instruction. b10 = Jazelle-DBX. context ID Breakpoint value. The reset value is Unpredictable Contains the breakpoint value that corresponds to either an instruction address or a context ID. Breakpoints can be set on: ? an instruction address ? a context ID value ? an instruction address and context ID pair. For an instruction address and context ID pair, two BRPs must be linked. A debug event is generated when both the instruction address and the context ID pair match at the same time. Note ? Only BRP2 supports context ID comparison. ? DBGBVR0[1:0] and DBGBVR1[1:0] are SBZP on writes and RAZ on reads because these registers do not support context ID comparisons. ? The context ID value for DBGBVR2 to match with is given by the contents of the CP15 Context ID Register. See Chapter 4 System Control for information on the Context ID Register. Breakpoint value. The reset value is Unpredictable Breakpoint value. The reset value is Unpredictable Breakpoint address mask. RAZ/WI b00000 = no mask Meaning of DBGBVR: b000 = instruction virtual address match b001 = linked instruction virtual address match b010 = unlinked context ID b011 = linked context ID b100 = instruction virtual address mismatch b101 = linked instruction virtual address mismatch b11x = reserved. Note DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID comparison capability. Linked BRP number. The binary number encoded here indicates another BRP to link this one with. Note ? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated ? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated. Secure state access control. This field enables the breakpoint to be conditional on the security state of the processor. b00 = breakpoint matches in both Secure and Non-secure state b01 = breakpoint only matches in Non-secure state b10 = breakpoint only matches in Secure state b11 = reserved. Byte address select. For breakpoints programmed to match an instruction address, you must write a word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits only if you access certain byte addresses. If you program the BRP for instruction address match: b0000 = the breakpoint never hits b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is accessed b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed. If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected. Supervisor access control. The breakpoint can be conditioned on the mode of the processor. b00 = User, System, or Supervisor b01 = privileged b10 = User b11 = any. Breakpoint enable: 0 = breakpoint disabled, reset value 1 = breakpoint enabled. Breakpoint address mask. RAZ/WI b00000 = no mask Meaning of DBGBVR: b000 = instruction virtual address match b001 = linked instruction virtual address match b010 = unlinked context ID b011 = linked context ID b100 = instruction virtual address mismatch b101 = linked instruction virtual address mismatch b11x = reserved. Note DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID comparison capability. Linked BRP number. The binary number encoded here indicates another BRP to link this one with. Note ? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated ? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated. Secure state access control. This field enables the breakpoint to be conditional on the security state of the processor. b00 = breakpoint matches in both Secure and Non-secure state b01 = breakpoint only matches in Non-secure state b10 = breakpoint only matches in Secure state b11 = reserved. Byte address select. For breakpoints programmed to match an instruction address, you must write a word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits only if you access certain byte addresses. If you program the BRP for instruction address match: b0000 = the breakpoint never hits b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is accessed b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed. If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected. Supervisor access control. The breakpoint can be conditioned on the mode of the processor. b00 = User, System, or Supervisor b01 = privileged b10 = User b11 = any. Breakpoint enable: 0 = breakpoint disabled, reset value 1 = breakpoint enabled. Breakpoint address mask. RAZ/WI b00000 = no mask Meaning of DBGBVR: b000 = instruction virtual address match b001 = linked instruction virtual address match b010 = unlinked context ID b011 = linked context ID b100 = instruction virtual address mismatch b101 = linked instruction virtual address mismatch b11x = reserved. Note DBGBCR0[21] and DBGBCR1[21] are RAZ on reads because these registers do not have context ID comparison capability. Linked BRP number. The binary number encoded here indicates another BRP to link this one with. Note ? If a BRP is linked with itself, it is Unpredictable whether a breakpoint debug event is generated ? If this BRP is linked to another BRP that is not configured for linked context ID matching, it is Unpredictable whether a breakpoint debug event is generated. Secure state access control. This field enables the breakpoint to be conditional on the security state of the processor. b00 = breakpoint matches in both Secure and Non-secure state b01 = breakpoint only matches in Non-secure state b10 = breakpoint only matches in Secure state b11 = reserved. Byte address select. For breakpoints programmed to match an instruction address, you must write a word-aligned address to the DBGBVR. You can then use this field to program the breakpoint so it hits only if you access certain byte addresses. If you program the BRP for instruction address match: b0000 = the breakpoint never hits b0011 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed b1100 = the breakpoint hits if any of the two bytes starting at address DBGBVR & 0xFFFFFFFC +2 is accessed b1111 = the breakpoint hits if any of the four bytes starting at address DBGBVR & 0xFFFFFFFC +0 is accessed. If you program the BRP for instruction address mismatch, the breakpoint hits where the corresponding instruction address breakpoint does not hit, that is, the range of addresses covered by an instruction address mismatch breakpoint is the negative image of the corresponding instruction address breakpoint. If you program the BRP for context ID comparison, this field must be set to b1111. Otherwise, breakpoint and watchpoint debug events might not be generated as expected. Supervisor access control. The breakpoint can be conditioned on the mode of the processor. b00 = User, System, or Supervisor b01 = privileged b10 = User b11 = any. Breakpoint enable: 0 = breakpoint disabled, reset value 1 = breakpoint enabled. Watchpoint address Watchpoint address Watchpoint address This field watches a range of addresses by masking lower order address bits out of the watchpoint comparison: b00000 = no mask b00001 = reserved b00010 = reserved b00011 = 0x00000007 mask for data address b00100 = 0x0000000F mask for data address b00101 = 0x0000001F mask for data address . . . b11111 = 0x7FFFFFFF mask for data address. Note ? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is Unpredictable. ? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the comparison SBZ. Otherwise the behavior is Unpredictable. To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those that have a 4-bit byte address select field (bits [8:5]). Enable linking bit: 0 = linking disabled 1 = linking enabled. When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP field. Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is Unpredictable whether a watchpoint debug event is generated. Secure state access control. This field enables the watchpoint to be conditioned on the security state of the processor. b00 = watchpoint matches in both Secure and Non-secure state b01 = watchpoint only matches in Non-secure state b10 = watchpoint only matches in Secure state b11 = reserved Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to program the watchpoint so it only hits if certain byte addresses are accessed. Load/store access. The watchpoint can be conditioned to the type of access being done. b00 = reserved b01 = load, load exclusive, or swap b10 = store, store exclusive or swap b11 = either. SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local monitor within the processor. Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: b00 = reserved b01 = privileged, match if the processor does a privileged access to memory b10 = User, match only on nonprivileged accesses b11 = either, match all accesses Watchpoint enable: 0 = watchpoint disabled, reset value 1 = watchpoint enabled. This field watches a range of addresses by masking lower order address bits out of the watchpoint comparison: b00000 = no mask b00001 = reserved b00010 = reserved b00011 = 0x00000007 mask for data address b00100 = 0x0000000F mask for data address b00101 = 0x0000001F mask for data address . . . b11111 = 0x7FFFFFFF mask for data address. Note ? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is Unpredictable. ? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the comparison SBZ. Otherwise the behavior is Unpredictable. To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those that have a 4-bit byte address select field (bits [8:5]). Enable linking bit: 0 = linking disabled 1 = linking enabled. When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP field. Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is Unpredictable whether a watchpoint debug event is generated. Secure state access control. This field enables the watchpoint to be conditioned on the security state of the processor. b00 = watchpoint matches in both Secure and Non-secure state b01 = watchpoint only matches in Non-secure state b10 = watchpoint only matches in Secure state b11 = reserved Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to program the watchpoint so it only hits if certain byte addresses are accessed. Load/store access. The watchpoint can be conditioned to the type of access being done. b00 = reserved b01 = load, load exclusive, or swap b10 = store, store exclusive or swap b11 = either. SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local monitor within the processor. Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: b00 = reserved b01 = privileged, match if the processor does a privileged access to memory b10 = User, match only on nonprivileged accesses b11 = either, match all accesses Watchpoint enable: 0 = watchpoint disabled, reset value 1 = watchpoint enabled. This field watches a range of addresses by masking lower order address bits out of the watchpoint comparison: b00000 = no mask b00001 = reserved b00010 = reserved b00011 = 0x00000007 mask for data address b00100 = 0x0000000F mask for data address b00101 = 0x0000001F mask for data address . . . b11111 = 0x7FFFFFFF mask for data address. Note ? If bits [28:24] are not set to b00000, bits [12:5] must be set to b11111111. Otherwise the behavior is Unpredictable. ? If [28:24] are not set to b00000, the corresponding DBGWVR bits that are not being included in the comparison SBZ. Otherwise the behavior is Unpredictable. To watch for a write to any byte in an 8-byte aligned object of size 8 bytes, ARM recommends that a debugger sets bits [28:24] to b00111, and bits [12:5] to b11111111. This is compatible with both ARMv7 debug compliant implementations that have an 8-bit byte address select field (bits [12:5]) and with those that have a 4-bit byte address select field (bits [8:5]). Enable linking bit: 0 = linking disabled 1 = linking enabled. When this bit is set, this watchpoint is linked with the context ID holding BRP selected by the linked BRP field. Linked BRP number. The binary number encoded here indicates a context ID holding BRP to link this WRP with. If this WRP is linked to a BRP that is not configured for linked context ID matching, it is Unpredictable whether a watchpoint debug event is generated. Secure state access control. This field enables the watchpoint to be conditioned on the security state of the processor. b00 = watchpoint matches in both Secure and Non-secure state b01 = watchpoint only matches in Non-secure state b10 = watchpoint only matches in Secure state b11 = reserved Byte address select. The DBGWVR is programmed with word-aligned address. You can use this field to program the watchpoint so it only hits if certain byte addresses are accessed. Load/store access. The watchpoint can be conditioned to the type of access being done. b00 = reserved b01 = load, load exclusive, or swap b10 = store, store exclusive or swap b11 = either. SWP and SWPB trigger a watchpoint on b01, b10, or b11. A load exclusive instruction triggers a watchpoint on b01 or b11. A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local monitor within the processor. Privileged access controlb. The watchpoint can be conditioned to the privilege of the access being done: b00 = reserved b01 = privileged, match if the processor does a privileged access to memory b10 = User, match only on nonprivileged accesses b11 = either, match all accesses Watchpoint enable: 0 = watchpoint disabled, reset value 1 = watchpoint enabled. Write 0xC5ACCE55 to this field to unlock the DBG. Write any other value to this field to lock the DBG OSLM[0] OSLM[1] OS Lock Model implemented field. This field identifies the form of OS Save and Restore mechanism implemented. The possible values are: 0b00 No OS Save and Restore mechanism implemented. OS Lock not implemented. v7 Debug only. 0b01 OS Lock and DBGOSSRR implemented. v7 Debug only. 0b10 OS Lock implemented. DBGOSSRR not implemented. v7.1 Debug only. 0b11 Reserved. Note This field is split across two non-contiguous bits in the register. Not 32-bit access. This bit is always RAZ. It indicates that a 32-bit access is needed to write the key to the OS Lock Access Register. OS Lock Status. The possible values are: 0 OS Lock not set. 1 OS Lock set. If the OS Save and Restore mechanism is not implemented this bit is UNK. The OS Lock is set or cleared by writing to the DBGOSLAR. Hold non-debug logic reset: 0 = Do not hold the non-debug logic reset on power-up or warm reset. 1 = Hold the non-debug logic of the processor in reset on power-up or warm reset. The processor is held in this state until this flag is cleared to 0. Warm reset request, RAZ When set to 1, the DBGNOPWRDWN output signal is HIGH. This output is connected to the system power controller and is interpreted as a request to operate in emulate mode. In this mode, the Cortex-A5 processor and ETM are not actually powered down when requested by software or hardware handshakes. 0 = DBGNOPWRDWN is LOW. This is the reset value. 1 = DBGNOPWRDWN is HIGH. Sticky reset status Reset status Sticky power-down status. RAZ Power up status. RAO Set value of the DBGRESTARTED output pin Set value of PMUIRQ output pin. Set value of the DBGACK output pin. Read value of the DBGRESTART input pin Read value of nFIQ input pin. Read value of nIRQ input pin. Read value of EDBGRQ input pin. Controls whether the processor is in normal operating mode or integration mode: b0 = normal operation b1 = integration mode enabled. Indicates the claim tags. Writing 1 to a bit in this register sets that particular claim. You can read the claim status at the Claim Tag Clear Register. For example, if you write 1 to bit [3] of this register, bit [3] of the Claim Tag Clear Register is read as 1. Writing 0 to a specific claim tag bit has no effect. This register always reads 0xFF, indicating that up to eight claims can be set. Indicates the claim tag status. Writing 1 to a specific claim tag clear bit clears that claim tag. Reading this register returns the current claim tag value. For example, if you write 1 to bit [3] of this register, it is read as 0. The reset value is 0. Lock access control. To unlock the debug registers, write a 0xC5ACCE55 key to this register. To lock the debug registers, write any other value. Accesses to locked debug registers are ignored. The reset value is 0 Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register This bit indicates the status of the debug registers lock. 0 = Lock clear. Debug register writes are permitted. 1 = Lock set. Debug register writes are ignored. The Debug reset value of this bit is 1. Read-as-One Secure noninvasive debug enable field DBGEN || NIDEN) && (SPIDEN || SPNIDEN Secure invasive debug enable field DBGEN && SPIDEN Non-secure noninvasive debug field DBGEN || NIDEN Non-secure invasive debug enable DBGEN Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1. Indicates that the main class of the Cortex-A5 processor is debug logic. This value is 0x5. Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0. Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4. Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0x05. Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB. Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0xC Indicates the revision number for the Cortex-A5 processor. This value changes based on the product major and minor revision. This value is set to 1 indicating revision r0p1. Always 1. Indicates that a JEDEC assigned value is used. Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3. Indicates the manufacturer revision number. This value changes based on the manufacturer metal fixes. This value is set to 0. For the Cortex-A5 processor, this value is set to 0. Component identifier, bits [7:0]. Component class (component identifier, bits [15:12]). Component identifier, bits [11:8]. Component identifier, bits [23:16]. Component identifier, bits [31:24]. PMU Event counter 0 PMU Event counter 1 Counts processor clock cycles Specifies the event selected as described in the ARM Architecture Reference Manual. Event EVNTBUS bit position Description 0x00 - Software increment. The register is incremented only on writes to the Software Increment Register. See Software Increment Register on page 10-7. 0x01 [0] Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache. Includes the speculative linefills in the count. 0x02 [1] Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB. Includes the speculative requests in the count. 0x03 [2] Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache. Counts the number of allocations performed in the Data Cache because of a read or a write 0x04 [3] Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache. This includes speculative reads. 0x05 [4] Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB. This does not include micro TLB misses because of PLD, PLI, CP15 Cache operation by MVA and CP15 VA to PA operations. 0x06 [5] Data read architecturally executed. Counts the number of data read instructions accepted by the Load Store Unit. This includes counting the speculative and aborted LDR/LDM, and the reads because of the SWP instructions. 0x07 [6] Data write architecturally executed. Counts the number of data write instructions accepted by the Load Store Unit. This includes counting the speculative and aborted STR/STM, and the writes because of the SWP instructions. 0x08 [7] Instruction architecturally executed. 0x09 [8] Exception taken. Counts the number of exceptions architecturally taken. 0x0A [9] Exception return architecturally executed. The following instructions are reported on this event: 0x0B [10] Change to ContextID retired. Counts the number of instructions architecturally executed writing into the ContextID Register. 0x0C [11] Software change of PC. 0x0D [12] Immediate branch architecturally executed (taken or not taken). This includes the branches which are flushed due to a previous load/store which aborts late. 0x0E [13] Procedure return (other than exception returns) architecturally executed. 0x0F [14] Unaligned load-store. 0x10 [15] Branch mispredicted/not predicted. Counts the number of mispredicted or not-predicted branches executed. This includes the branches which are flushed because of a previous load/store which aborts late. 0x11 - Cycle counter. 0x12 [16] Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor. This includes the branches which are flushed because of a previous load/store which aborts late. 0x13 [17] Data memory access. 0x14 [18] Instruction Cache access. 0x15 [19] Data cache eviction. 0x86 [20] IRQ exception taken. 0x87 [21] FIQ exception taken. 0xC0 [22] External memory request. 0xC1 [23] Non-cacheable external memory request. 0xC2 [24] Linefill because of prefetch. 0xC3 [25] Prefetch linefill dropped. 0xC4 [26] Entering read allocate mode. 0xC5 [27] Read allocate mode. 0xC6 [28] Reserved. 0xC7 - ETM Ext Out[0]. 0xC8 - ETM Ext Out[1]. 0xC9 [29] Data Write operation that stalls the pipeline because the store buffer is full. Cycle counter enable set: 0 = disable 1 = enable. Counter 1 enable Counter 0 enable Cycle counter enable clear: 0 = disable 1 = enable. Counter 1 enable Counter 0 enable PMCCNTR overflow interrupt request enable. When reading this register: 0 = interrupt request disabled 1 = interrupt request enabled. When writing to this register: 0 = no action 1 = interrupt request enabled. PMC1 overflow interrupt request enable PMC0 overflow interrupt request enable. PMCCNTR overflow interrupt clear bit. When reading this register: 0 = interrupt request disabled 1 = interrupt request enabled. When writing to this register: 0 = no action 1 = interrupt request cleared. Clear interrupt request on PMC1 overflow. Clear interrupt request on PMC0 overflow Cycle counter overflow flag: 0 = disable 1 = enable. Counter 1 overflow flag Counter 0 overflow flag Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing. Increment Counter 1. When writing this register, a value of 1 increments the counter, and value of 0 does nothing. User mode enable supported (using PMUSERENR) Event export supported Cycle counter pre-scale supported Cycle counter implemented 32-bit counters implemented 2 event counters implemented Specifies the implementor code: 0x41 = ARM. This field is read-only and write ignored. Specifies the identification code: 0x5 This field is read-only and write ignored. Specifies the number of counters implemented: 0x2 = two counters implemented. This field is read-only and write ignored. Disables cycle counter, PMCCNTR, when prohibited: 0 = count is enabled in prohibited regions. This is the reset value. 1 = count is disabled in prohibited regions. Enables export of the events from the event bus to an external monitoring block, such as an ETM: 0 = export disabled. This is the reset value. 1 = export enabled. Cycle count divider: 0 = count every clock cycle when enabled. This is the reset value. 1 = count every 64th clock cycle when enabled. Cycle counter reset, write only bit, RAZ: 0 = no action 1 = reset cycle counter, PMCCNTR, to zero. Performance counter reset, write only bit, RAZ: 0 = no action 1 = reset all performance counters to zero, not including PMCCNTR. Enable bit: 0 = disable all counters, including PMCCNTR. This is the reset value. 1 = enable all counters including PMCCNTR. User mode enable. 0 is the reset value Bus cycle Write to translation table base Instruction speculatively executed Local memory error Bus access Level 2 data cache write-back Level 2 data cache refill Level 2 data cache access Level 1 data cache write-back Level 1 instruction cache access Data memory access Predictable branch speculatively executed Cycle Mispredicted or not predicted branch speculatively executed Unaligned load or store Procedure return Immediate branch Software change of the PC Write to CONTEXTIDR Exception return Exception taken Instruction architecturally executed Store Load Level 1 data TLB refill Level 1 data cache access Level 1 data cache refill Level 1 instruction TLB refill Level 1 instruction cache refill Software increment Lock access control. To unlock the performance monitor registers, write a 0xC5ACCE55 key to this register. To lock the performance monitor registers, write any other value. Accesses to locked performance monitor registers are ignored. The reset value is 0. Read as zero. It indicates that a 32-bit access is required to write the key to the Lock Access Register This bit indicates the status of the debug registers lock. 0 = Lock clear. Debug register writes are permitted. 1 = Lock set. Debug register writes are ignored. The Debug reset value of this bit is 1. Read-as-One Secure noninvasive debug enable field DBGEN || NIDEN) && (SPIDEN || SPNIDEN Secure invasive debug enable field DBGEN && SPIDEN Non-secure noninvasive debug field DBGEN || NIDEN Non-secure invasive debug enable Indicates that the sub-type of the Cortex-A5 processor is core. This value is 0x1. Indicates that the main class of the Cortex-A5 processor is performance monitor. This value is 0x6. Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0. Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is 0x4. Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is 0xA5. Indicates bits of the JEDEC JEP106 Identity Code. This value is 0xB. Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is 0x9. Indicates the revision number for the Cortex-A5 processor. This value changes based on the product major and minor revision. This value is set to 1 indicating revision r0p1. Always 1. Indicates that a JEDEC assigned value is used. Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to 0x3. Indicates the manufacturer revision number. This value changes based on the manufacturer metal fixes. This value is set to 0. For the Cortex-A5 processor, this value is set to 0. Component identifier, bits [7:0]. Component class (component identifier, bits [15:12]). Component identifier, bits [11:8]. Component identifier, bits [23:16]. Component identifier, bits [31:24]. Set to 1 to enable timestamping. On an ETM reset this bit is 0. If an ETM is shared between multiple cores, selects which core to trace. For the maximum value permitted, see bits [14:12] of the System Configuration Register. See the Embedded Trace Macrocell Architecture Specification for more information. To guarantee that the ETM is correctly synchronized to the new core, you must update these bits as follows: 1:Set bit [10], ETM programming, and bit [0], ETM power down, to 1. 2:Change the core select bits. 3:Clear bit [0], ETM power down, to 0. 4:Perform other programming required as normal. On an ETM reset this field is zero. Instrumentation resources access control, ETM-A5 does not implement any instrumentation resources and therefore this bit is RAZ. Disable software writes. ETM-A5 does not support this feature and therefore this bit is RAZ. Disable register writes from the debugger. ETM-A5 does not support this feature and therefore this bit is RAZ. Port size[3].Use this bit in conjunction with bits [6:4].On an ETM reset this bit is 0, corresponding to the 32-bit port size. 0:Instruction trace enabled. 1:Instruction trace disabled. Data-only tracing is possible in this mode. On an ETM reset this bit is 0. Use this bit in conjunction with bit [1], the MonitorCPRT bit. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. Use this bit with bit [7] to suppress data. For details see Data suppression in the Embedded Trace Macrocell Architecture Specification.On an ETM reset this bit is 0. These bits are used, in conjunction with bit [13], to set the trace port clocking mode. ETM-A5 supports only dynamic mode, corresponding to the value b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit [11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode.On an ETM reset these bits are zero. b00 No Context ID tracing. b01 Context ID bits [7:0] traced. b10 Context ID bits [15:0] b11 Context ID bits [31:0] traced. Note Only the number of bytes specified is traced even if the new value is larger than this.On an ETM reset this field is zero. See the description of bits [17:16].On an ETM reset this bit is 0. Set this bit to 1 if you want the trace to include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive.On an ETM reset this bit is 0. This bit controls an external output, ETMEN. The possible values are: 0 ETMEN is LOW. 1 ETMEN is HIGH. You can use the ETMEN signal to control the routing of trace port signals to shared GPIO pins on your SoC, under the control of logic external to the ETM.Trace software tools must set this bit to 1 to ensure that trace output is enabled from this ETM. When set to 1, the ETM is being programmed. For more information, see ETM Programming bit and associated state in the Embedded Trace Macrocell Architecture Specification. If you set this bit to 1, when the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the Cortex-A5 processor to be forced into Debug state. On an ETM reset this bit is 0. Set this bit to 1 if you want the ETM to output all branch addresses, even if the branch isbecause of a direct branch instruction. Setting this bit to 1 enables reconstruction of the program flow without having access to the memory image of the code being executed.On an ETM reset this bit is 0. ETM-A5 does not implement FIFOFULL stalling of the processor, and therefore this bit is RAZ. Use this field with bit [21] to specify the port size.The port size determines how many external pins are available to output the trace information on ATDATA[31:0]. ETM-A5 supports only the 32-bit port size, corresponding to a Port size[3:0] value of b0100, but you can write other values to these bits, and a read of the register returns the value written. Writing other values to these bits has no effect on the ETM.Bit [10] of the System Configuration Register indicates if these bits are set to select an unsupported port size.For more information see the Embedded Trace Macrocell Architecture Specification. On an ETM reset this field is b100, corresponding to the 32-bit port size. This field configures the data tracing mode. The possible values are: b00 No data tracing. b01 Trace only the data portion of the access. b10 Trace only the address portion of the access. b11 Trace both the address and the data of the access. On an ETM reset this field is zero. This field controls whether CPRTs are traced. The possible values are: 0 CPRTs not traced. 1 CPRTs traced. This bit is used with bit [19]. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. A pin controlled by this bit enables the ETM power to be controlled externally, see Control of ETM power down. The sense of this bit is inverted, and drives the ETMPWRUP signal. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, ETM tracing is disabled and accesses to any registers other than this register and the Lock Access Register are ignored.On an ETM reset this bit is set to 1. ETMIDR present. Software access is supported. Trace start/stop block is present. Number of Context ID comparators. FIFOFULL logic absent. Number of external outputs. Determined by the MAXEXTOUT[1:0] inputs.The value of these bits is the minimum of MAXEXTOUT[1:0] and 2, because ETM-A5 supports a maximum of 2 external outputs. Number of external inputs. Determined by the MAXEXTIN[2:0] inputs. The value of these bits is the minimum of MAXEXTIN[2:0] and 4, because ETM-A5 supports a maximum of 4 external inputs. The sequencer is present. Number of counters. Number of memory map decoders. Number of data comparators. Number of pairs of address comparators. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A ASICCTL[7:0]: when a bit in this field is set to 0 the corresponding bit of ASICCTL[7:0] is LOW when a bit in this field is set to 1 the corresponding bit of ASICCTL[7:0] is HIGH. v3.1 Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is programmed again. This bit exists in all architecture versions, but can only be accessed in ETMv3.1 and later as described in ETM Programming bit and associated state on page 3-97. Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match The current effective value of the ETM Programming bit, bit [10] of the ETMCR. You must wait for this bit to go to 1 before you start to program the ETM as described in ETM Programming bit and associated state on page 3-97. If you read other bits in the ETMSR while this bit is 0, some instructions might not have taken effect. ARM recommends that you set the ETM Programming bit and wait for this bit to go to 1 before reading the overflow bit. In ETMv3.2 and later this bit remains 0 if there is any data in the FIFO. This ensures that the FIFO is empty before the ETM programming is changed. In ETMv3.5 this bit is set when the OS Lock is set. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later on page 3-166. In ETMv3.5 this bit must be polled before saving or restoring state. See Access permissions for ETMv3.5, multiple power domains on page 3-224 If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either: ? trace is restarted. ? the ETM Power Down bit, bit [0] of ETMCR, is set to 1. Setting or clearing the ETM Programming bit does not cause this bit to be cleared to 0. No Fetch comparisons. If this bit is set to 1, address comparators cannot perform fetch-stage comparisons. Setting bits [2:0] of an ETMACTR to b000, instruction fetch causes the comparator to have UNPREDICTABLE behavior. Number of supported processors minus 1. The value given here is the maximum value that can be written to bits [27:25] of the ETMCR, register 0x000. This field must be b000 if the ETM supports Direct JTAG access Port mode supported. Set to 1 if the currently selected port mode is supported internally or externally. Port size supported. Set to 1 if the currently selected port size is supported internally or externally for the currently selected port mode. Enables more complex port sizes to be supported Maximum port size[3]. This bit is used in conjunction with bits [2:0]. If set to 1, FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR, register 0x001. Maximum port size[2:0]. This bit is used in conjunction with bit [9]. The value given here is the maximum size supported by both the ETM and the ASIC. Smaller sizes might or might not be supported. Check bit [10] for precise information on supported modes. See bits [6:4] in ETMCR bit assignments on page 3-101. When a bit is set to 1, it selects a single address comparator 16-1 as stop addresses. For example, bit [16] set to 1 selects single address comparator 1 as a stop address. When a bit is set to 1, it selects a single address comparator 16-1 as start addresses. For example, bit [0] set to 1 selects single address comparator 1 as a start address. When a bit is set to 1, it selects a single address comparator 16-1 for include/exclude control. For example, bit [0] set to 1 selects single address comparator 1. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A Trace start/stop enable. The possible values of this bit are: 0 Tracing is unaffected by the trace start/stop logic. 1 Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. See The trace start/stop block on page 2-40. The trace start/stop resource (resource 0x5F) is unaffected by the value of this bit. Include/exclude control. The possible values of this bit are: 0 Include. The specified resources indicate the regions where tracing can occur. When outside this region tracing is prevented. 1 Exclude. The resources, specified in bits [23:0] and in the ETMTECR2, indicate regions to be excluded from the trace. When outside an exclude region, tracing can occur. When a bit is set to 1, it selects memory map decode 16-1 for include/exclude control. For example, bit [8] set to 1 selects MMD 1. When a bit is set to 1, it selects address range comparator 8-1 for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1. The number of bytes left in the FIFO, below which the FIFOFULL or SuppressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A When a bit is set to 1, it selects single address comparator 16 to 1 for exclude control. For example, bit [16] set to 1 selects single address comparator 1. When a bit is set to 1, it selects single address comparator 16 to 1 for include control. For example, bit [0] set to 1 selects single address comparator 1. Exclude-only control. The possible values of this bit are: 0 Mixed mode. ViewData operates in a mixed mode, and both include and exclude resources can be programmed. 1 Exclude-only mode. ViewData is programmed only in an excluding mode. If none of the excluding resources match, tracing can occur. When a bit is set to 1, it selects address range comparator 8-1 for exclude control. For example, bit [8] set to 1 selects address range comparator 1. When a bit is set to 1, it selects address range comparator 8-1 for include control. For example, bit [0] set to 1 selects address range comparator 1. Address value Address value Address value Address value Address value Address value Address value Address value Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Virtual Machine ID (VMID) comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator matches only if the current VMID matches the value stored in the ETMVMIDCVR. See VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5 on page 3-164. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions Hyp mode comparison enable, if the processor implements the Virtualization Extensions.b A value of 1 means that the address comparator also matches if the processor is operating in Hyp mode. See Virtualization Extensions, ETMv3.5 on page 7-345. This bit is reserved, RAZ if the processor does not implement the Virtualization extensions. State and mode comparison control. The assignment of these bits is: Bit [13, 11] Non-secure state comparison control. Bit [12, 10] Secure state comparison control. For each pair of bits, the encoding is: b00 Match in all modes in this state. b01 Do not match in any modes in this state. b10 Match in all modes except User mode in this state. b11 Match only in User mode in this state. If the processor does not implement the Security Extensions, bits [13, 11] are reserved, RAZ/WI. See Filtering by state and mode, in ETMv3.5 on page 3-131 Context ID comparator control. The permitted values of this field are: b00 Ignore Context ID comparator. b01 Address comparator matches only if Context ID comparator value 1 matches. b10 Address comparator matches only if Context ID comparator value 2 matches. b11 Address comparator matches only if Context ID comparator value 3 matches. Exact match bit. Specifies comparator behavior when exceptions, aborts, and load misses occur. See Exact matching, in ETMv2.0 and later on page 2-54. Data value comparison control. The permitted values of this field are: b00 No data value comparison is made. b01 Comparator can match only if data value matches. b11 Comparator can match only if data value does not match. The value of b10 is reserved and must not be used. Note: The b11 encoding was introduced in ETM architecture version 1.2. Previously this value was reserved. For details of the effect of this field on data value comparison, see Exact matching for data address comparisons on page 2-56. Comparison access size. The permitted values of this field are: b00 Java instruction (from ETM architecture version 1.3 only) or byte data. b01 Thumb instruction or halfword data. b11 ARM instruction or word data. The value of b10 is reserved and must not be used. For more information, see Comparator access size on page 2-49. Access type. The permitted values of this field are: b000c Instruction fetch. b001 Instruction execute. b010 Instruction executed and passed condition code test. b011 Instruction executed and failed condition code test. b100 Data load or store. b101 Data load. b110 Data store. The value of b111 is reserved and must not be used. Note: ? The b010 and b011 encodings were introduced in ETM architecture version 1.2. Previously these values were reserved. ? From ETMv3.3, if data address comparisons are not supported, writing b100, b101 or b110 to this field causes UNPREDICTABLE behavior. See No data address comparator option, ETMv3.3 and later on page 2-25 for more information. Data value for comparison Data value for comparison Data mask Data mask Initial count Initial count Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and decrements every cycle regardless of the count enable event. When set to 1, the count enable event is used to enable the counter. ARM recommends that bit [17] is always set to 1 and that the count enable event is used to control counter operation, using 0x6F (TRUE) if a free running counter is required. Note This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM architecture versions. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A Count enable source in ETMv1.x. When set to 0, the counter is continuously enabled and decrements every cycle regardless of the count enable event. When set to 1, the count enable event is used to enable the counter. ARM recommends that bit [17] is always set to 1 and that the count enable event is used to control counter operation, using 0x6F (TRUE) if a free running counter is required. Note This bit is not supported in ETMv2.0 and later, and is always set to 1 in these ETM architecture versions. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A Current counter value. From ETM v3.1, when the Programming bit is set to 1 you can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information. Current counter value. From ETM v3.1, when the Programming bit is set to 1 you can write to an ETMCNTVR to set the current value of the counter. See ETM Programming bit and associated state on page 3-97 for more information. Sequencer state transition event Sequencer state transition event Sequencer state transition event Sequencer state transition event Sequencer state transition event Sequencer state transition event Current sequencer state.The permitted values of this field are: b00 Sequencer currently in state 1. b01 Sequencer currently in state 2. b10 Sequencer currently in state 3. The value of b11 is reserved. From ETMv3.1, when the Programming bit is set to 1, software can write to this field to force the sequencer to a particular state. The effect of writing b11 to this field is UNPREDICTABLE, and software must not write this value. function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A function: 0: A 1: NOT(A) 2: A AND B 3: NOT(A) AND B 4: NOT(A) AND NOT(B) 5: A OR B 6: NOT(A) OR B 7: NOT(A) OR NOT(B) Resource B [13:11]: resource type [10:7]: resource index Resource A Context ID value Context ID mask value Synchronization frequency. Default value is 1024. Branch packet encoding implemented. The possible values of this bit are: 0 The ETM implements the original branch packet encoding. See Branch packet formats with the original address encoding scheme on page 7-310. 1 The ETM implements the alternative branch packet encoding. See Branch packet formats with the alternative address encoding scheme on page 7-313. Support for Security Extensions. The possible values of this bit are: 0 The ETM behaves as if the processor is in Secure state at all times. 1 The ARM architecture Security Extensions are implemented by the processor Support for 32-bit Thumb instructions. The possible values of this bit are: 0: A 32-bit Thumb instruction is traced as two instructions, and exceptions might occur between these two instructions. 1: A 32-bit Thumb instruction is traced as a single instruction. See 32-bit Thumb instructions on page 4-240 for more information. Load PC first. If this bit is set to 1, LSMs with the PC in the list load the PC first, followed by the other registers in the normal order. This can be decompressed by using the following procedure: 1. Calculate the number of items transferred by the LSM by looking at the code image. 2. As each item is read, assign an address equal to 4 greater than the previous one as normal. 3. When the number of items read equals the total number of items transferred, subtract (4 * number of items) from each address other than the first. Note This means that a branch address can be traced before the remaining data values of an instruction. While this has never been prohibited in the protocol, care must be taken to ensure that this case is correctly handled. Processor family. The meaning of this field depends on the value of the Implementer code.The following apply if Implementer code = 0x41, for ARM Limited: b0000 ARM7 processor. b0001 ARM9 processor. b0010 ARM10 processor. b0011 ARM11 processor b1111 Processor family is defined elsewhere. See The Processor family field on page 3-157 for more information. When the Implementer code = 0x41, all other values are reserved by ARM Limited. For any other Implementer code the permitted values of this field are defined by the implementer. Major ETM architecture version number. See The ETM architecture version. Possible values of this field are: b0000 ETMv1. b0001 ETMv2. b0010 ETMv3. All other values are reserved. Minor ETM architecture version number. See The ETM architecture version. Implementation revision. See Implementation revision on page 3-157 Timestamp packet size. This bit is 0 if the size of the packet is 48 bits. This bit is 1 if the size of the packet is 64 bits. Timestamp packet encoding. This bit is 1 if the timestamp packet is encoded as a natural binary number. This bit is 0 if the packet is gray coded. For more information see Encoding of the timestamp value on page 7-343. Reduced function counter. This bit is 1 if counter 1 is implemented as a reduced function counter. This bit is 0 if all counters are implemented as full-function counters. The Virtualization Extensions are implemented. This bit is 1 if the Virtualization Extensions are implemented, and 0 if not implemented. Timestamping implemented. This bit is 1 if timestamping is implemented, and 0 if it is not implemented ETMEIBCR implemented. This bit is 1 if the register is implemented, and 0 if it is not implemented. Trace Start/Stop block can use EmbeddedICE watchpoint inputs. This bit is 1 if the Trace Start/Stop block can use these inputs, and is 0 otherwise. Number of EmbeddedICE watchpoint inputs implemented. This field can take any value from b0000 (0 inputs) to b1000 (8 inputs). Number of Instrumentation resources supported. The maximum value of this field is b100, for four Instrumentation resources. For more information see Instrumentation resources, from ETMv3.3 on page 2-69. Set to 1 if data address comparisons are not supported. For more information see No data address comparator option, ETMv3.3 and later on page 2-25. Set to 1 if all registers are readable Size of extended external input bus. This field must be 0 if bits [2:0] are 0. Number of extended external input selectors. Extended external input selector 4 Extended external input selector 3 Extended external input selector 2 Extended external input selector 1 Stop resource selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] to input 2, and this pattern continues up to bit [23] corresponding to input 8. Start resource selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8. Trace ID to output onto the trace bus. On an ETM reset this field is cleared to 0x00. Identifies the order of transfers for a SWP or SWPB instruction: 0 = the Load transfer is traced before the Store transfer 1 = the Store transfer is traced before the Load transfer Identifies the order of transfers for the RFE instruction: 0 = the PC transfer is traced before the CPSR transfer 1 = the CPSR transfer is traced before the PC transfer OS lock status. The value of this bit is the same as the value of bit [1] of the ETMOSLSR, which indicates whether the ETM trace registers are locked. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later on page 3-166. This bit is UNKNOWN when the ETM is powered down Sticky Register state bit. The possible values of this bit are: 0 ETM Trace Registers have not been powered down since this register was last read. 1 ETM Trace Registers have been powered down since this register was last read, and have lost their state. When the core power domain of the ETM is powered down or reset, this bit is set to 1. Reads of this register when the core power domain is powered down or held in reset return 1 for this bit, and do not change the value of this bit. Reads of this register when the core power domain is powered up and not held in reset return the current value of this bit, and then clear this bit to 0. If the Software Lock mechanism is locked and the ETMPDSR read is made through the memory mapped interface, this bit is not cleared. In ETMv3.3 and ETMv3.4,when this bit is set, accesses to any ETM Trace Registers return an error response. In ETMv3.5, the value of this bit has no effect on accesses to the ETM Trace Registers. ETM powered up bit. The value of this bit indicates whether you can access the ETM Trace Registers. The possible values are: 0 ETM Trace Registers cannot be accessed. 1 ETM Trace Registers can be accessed. When this bit is set to 0, accesses to any ETM Trace Registers return an error response. Drives the EXTOUT[1:0] output pins Drives the nETMWFXREADY output pin Drives the ETMDBGRQ output pina Returns the value of the ETMWFXPENDING input pin Returns the value of the DBGACK input pin Returns the value of the EXTIN[3:0] input pins Drives the TRIGGER output pin Drives the ATDATA[31, 23, 15, 7, 0] output pins Returns the value of the SYNCREQ input pin Returns the value of the AFVALID input pin Returns the value of the ATREADY input pin Drives the ATID[6:0] output pins Drives the ATBYTES[1:0] output pins Drives the AFREADY output pin Drives the ATVALID output pin When this bit is set to 1, the device enters an integration mode to enable Topology Detection or Integration Testing to be checked. On an ETM reset this bit is cleared to 0. On reads, returns 0xFF. On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be set. On reads, returns the current claim tag value. On writes, a 1 in a bit position causes the corresponding bit in the claim tag value to be cleared to 0. On an ETM reset this field is cleared to 0x00. Write 0xC5ACCE55 to this field to unlock the ETM. Write any other value to this field to lock the ETM Reads as b0. Indicates that the ETMLAR is 32 bits Indicates whether the ETM is locked. The possible values of this bit are: 0 Writes are permitted. 1 ETM locked. Writes are ignored. If this register is accessed from an interface where the lock registers are ignored, this field reads as 0 regardless of whether the ETM is locked. Indicates whether the lock registers are implemented for this interface. The possible values of this bit are: 0 This access is from an interface that ignores the lock registers. 1 This access is from an interface that requires the ETM to be unlocked. Permission for Secure non-invasive debug. Reads as b00, Secure invasive debug not supported by the ETM Permission for Non-secure non-invasive debug. This field is only implemented if the processor implemented with the ETM implements the Security Extensions. When this field is implemented the possible values of the field are: b10 Non-secure non-invasive debug disabled. b11 Non-secure non-invasive debug enabled. This field is a logical OR of the NIDEN and DBGEN signals. It takes the value b11 when the OR is TRUE, and b10 when the OR is FALSE. If the processor does not support the Security Extensions, bits [3:2] are reserved, RAZ. Reads as b00, Non-secure invasive debug not supported by the ETM. 0x1 Sub type, processor trace 0x3 Main type, trace source n, where 2n is number of 4KB blocks used. JEP 106 continuation code Part Number[7:0]. Middle and Lower BCD value of Device Number. JEP 106 identity code[3:0] Part Number[11:8]. Upper Binary Coded Decimal (BCD) value of Device Number. Revision Number of Peripheral. This value is the same as the Implementation revision field of the ETMIDR, see ETM ID Register on page 3-19. Always 1. Indicates that a JEDEC assigned value is used. JEP 106 identity code[6:4]. RevAnd (at top level). Manufacturer revision number. Customer Modified. 0x0 indicates from ARM Component identifier, bits [7:0]. Component class (component identifier, bits [15:12]). Component identifier, bits [11:8]. Component identifier, bits [23:16]. Component identifier, bits [31:24]. Enables or disables the CTI. 0 When this bit is 0, all cross-triggering mapping logic functionality is disabled. 1 When this bit is 1, cross-triggering mapping logic functionality is enabled. Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel. Reads as follows: 0 Application trigger is inactive. 1 Application trigger is active. Writes as follows: 0 No effect. 1 Generate channel event. Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. On writes, for each bit: 0 Has no effect. 1 Clears the corresponding channel event. Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. On writes, for each bit: 0 Has no effect. 1 Generate an event pulse on the corresponding channel. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[0], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[1], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[2], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[3], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[4], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 0, ctitrigin[5], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 6, ctitrigin[6], generate an event on the channel corresponding to this bit. Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels. On writes, for each bit: 0 Input trigger 0 events are ignored by the corresponding channel. 1 When an event is received on input trigger 7, ctitrigin[7], generate an event on the channel corresponding to this bit. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 0, ctitrigout[0]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 1, ctitrigout[1]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 2, ctitrigout[2]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 3, ctitrigout[3]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 4, ctitrigout[4]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 5, ctitrigout[5]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 6, ctitrigout[6]. Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. On writes, for each bit 0 The corresponding channel is ignored by the output trigger 0. 1 When an event occurs on the channel corresponding to this bit, generate an event on output event 7, ctitrigout[7]. Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input. 1 ctitrigin is active. 0 ctitrigin is inactive. Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. 1 ctitrigout is active. 0 ctitrigout is inactive. Shows the status of the ctichin inputs. There is one bit of the field for each channel input. 0 ctichin is inactive. 1 ctichin is active. Because the register provides a view of the raw ctichin inputs, the reset value is UNKNOWN. Shows the status of the ctichout outputs. There is one bit of the field for each channel output. 0 ctichout is inactive. 1 ctichout is active. Enable ctichout3. Set to 0 to disable channel propagation. Enable ctichout2. Set to 0 to disable channel propagation. Enable ctichout1. Set to 0 to disable channel propagation. Enable ctichout0. Set to 0 to disable channel propagation. When external multiplexing is implemented for trigger signals, then the number of multiplexed signals on each trigger must be shown in the Device ID Register. This is done using a Verilog define EXTMUXNUM. Sets the value of the ctichinack outputs Sets the value of the ctitriginack outputs. Sets the value of the ctichout outputs Sets the value of the ctitrigout outputs. Reads the values of the ctichoutack inputs Reads the value of the ctitrigoutack inputs Reads the value of the ctichin inputs Reads the values of the ctitrigin inputs. Integration Mode Enable. 0 Disable integration mode. 1 Enable integration mode. Note The CTI must also be enabled using the CTICONTROL register for integration mode operation. On reads, for each bit: 1 Claim tag bit is implemented On writes, for each bit: 0 Has no effect. 1 Sets the relevant bit of the claim tag. On reads, for each bit: 0 Claim tag bit is not set. 1 Claim tag bit is set. On writes, for each bit: 0 Has no effect. 1 Clears the relevant bit of the claim tag. Software lock key value. 0xC5ACCE55 Clear the software lock. All other write values set the software lock. Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. 0 Indicates that write operations are permitted from this interface. 1 Indicates that write operations are not permitted from this interface. Read operations are permitted. Software Lock Implemented. Indicates that a lock control mechanism is present from this interface. 0 Indicates that a lock control mechanism is not present from this interface. Write operations to the LAR are ignored. 1 Indicates that a lock control mechanism is present from this interface Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled elsewhere. Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. Indicates the security level for Non-secure non-invasive debug: 0b10 Disabled. 0b11 Enabled. Indicates the security level for Non-secure invasive debug: 0b10 Disabled. 0b11 Enabled. Number of ECT channels available. Number of ECT triggers available. Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. Sub-classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification within the major classification as specified in the MAJOR field. 0b0001 Indicates that this component is a cross-triggering component. Major classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification for this debug and trace component. 0b0100 Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. Always 0b0000. Indicates that the device only occupies 4KB of memory. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b0100 JEDEC continuation code. Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0x06 Indicates bits[7:0] of the part number of the component Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0b1001 Indicates bits[11:8] of the part number of the component. 0b0101 This device is at r1p0. Always 1. Indicates that a JEDEC assigned value is used. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 0b0000 Indicates that there are no errata fixes to this component. Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0b0000 Indicates that the customer has not modified this component. Preamble[0]. Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. Class of the component, for example, whether the component is a ROM table or a generic CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight SoC-400 component. Preamble[1]. Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. Preamble[2]. Contains bits[23:16] of the component identification code. 0x05 Bits[23:16] of the identification code. Preamble[3]. Contains bits[31:24] of the component identification code. 0xB1 Bits[31:24] of the identification code. Defines the depth, in words, of the trace RAM. Formatter pipeline is empty. All data is stored to RAM. 0 Formatter pipeline is not empty. 1 Formatter pipeline is empty. The acquisition complete flag indicates that the capture is completed when the formatter stops because of any of the methods defined in the FFCR, or CTL.TraceCaptEn is 0. This sets FFSR.FtStopped to 1. 0 Acquisition is not complete. 1 Acquisition is complete. The Triggered bit is set when the component observes a trigger during programming the FFCR. Note This field does not indicate that the formatter embedded a trigger in the trace data. 0 A trigger is not observed. 1 A trigger is observed. The flag indicates whether the RAM is full or not. 0 The RAM write pointer is not wrapped around. The RAM is not full. 1 The RAM write pointer is wrapped around. The RAM is full. Data read from the ETB Trace RAM. Sets the read pointer to the required value. The read pointer reads entries from the Trace RAM through the APB interface. The RAM Write Pointer Register sets the write pointer to the required value. The write pointer writes entries from the CoreSight bus to the Trace RAM. The counter is used as follows: Trace after The counter is set to a large value, slightly less than the number of entries in the RAM. Trace before The counter is set to a small value. Trace about The counter is set to half the depth of the trace RAM. You must not write to this register when trace capture is enabled, FFSR.FtStopped is 0, and CTL.TraceCaptEn is 1. When a write is attempted, then the register is not updated. A read operation is permitted when trace capture is enabled. ETB Trace Capture Enable. This is the master enable bit that sets FtStopped to HIGH when TraceCaptEn is LOW. When capture is disabled, any remaining data in the ATB formatter is stored to RAM. When all of the data is stored, the formatter outputs FtStopped. Capture is fully disabled, or complete, when FtStopped goes HIGH. See ETB Formatter and Flush Status Register. 0 Disable trace capture. 1 Enable trace capture. When CTL.TraceCaptEn is 0: ? Writes to this register write the data to the ETB trace RAM. The RAM Write Pointer Register value is incremented. ? Reads of this register return an UNKNOWN value. When CTL.TraceCaptEn is 1: ? Writes to this register are ignored. The data is not written to the ETB trace RAM and the RAM Write Pointer is not affected. ? Reads of this register return an UNKNOWN value. Formatter stopped. The formatter has received a stop request signal and all trace data and post-amble is sent. Any additional trace data on the ATB interface is ignored and atreadys goes HIGH. 0 Formatter is not stopped. 1 Formatter is stopped. Flush In Progress. This is an indication of the current state of afvalids. 0 afvalids is LOW. 1 afvalids is HIGH. Stops trace capture after a trigger event is observed. The reset value is 0. 0 Disable stopping of the formatter after a trigger event is observed. 1 Enable stopping of the formatter after a trigger event is observed. Stops trace capture after the next flush completes. The reset value is 0. 0 Disable stopping the formatter when a flush completes. 1 Enable stopping the formatter when a flush completes. Indicates a Trigger-on-Flush completion. 0 Disable trigger indication on flush completion. 1 Enable trigger indication on flush completion. Indicates a trigger on a trigger event. 0 Disable trigger indication on a trigger event. 1 Enable trigger indication on a trigger event. Indicates a trigger when trigin is asserted. 0 Disable trigger indication when trigin is asserted. 1 Enable trigger indication when trigin is asserted. Initiates a manual flush. This bit is set to 0 after the flush has been serviced. The reset value is 0. 0 Manual flush is not initiated. 1 Manual flush is initiated. Flushes the data in the system when a trigger event occurs. The reset value is 0. 0 Disable flush generation when a trigger event occurs. 1 Enable flush generation when a trigger event occurs. Enables use of the flushin input. The reset value is 0. 0 Disable flush generation using the flushin interface. 1 Enable flush generation using the flushin interface. When EnFTC is 1, this bit controls whether triggers are recorded in the trace stream. Most usage models require Continuous mode, where this bit is set to 1. The reset value is 0. See Modes of operation on page 10-5 for more information. Note This bit can only be changed when FtStopped is HIGH. 0 Triggers are not embedded in the trace stream. 1 Triggers are embedded in the trace stream. Enable formatting. Most usage models require Continuous mode, where this bit is set to 1. The reset value is 0. See Modes of operation on page 10-5 for more information. Note This bit can only be changed when FtStopped is HIGH. 0 Formatting is disabled. 1 Formatting is enabled. Sets the value of full output. 0 Sets the value to 0. 1 Sets the value to 1. Sets the value of acqcomp output. 0 Sets the value to 0. 1 Sets the value to 1. Sets the value of flushinack. 0 Sets the value of FLUSHINACK to 0. 1 Sets the value of FLUSHINACK to 1. Sets the value of triginack. 0 Sets the value of TRIGINACK to 0. 1 Sets the value of TRIGINACK to 1. Reads the value of flushin. 0 flushin is LOW. 1 flushin is HIGH. TRIGIN Reads the value of trigin. 0 trigin is LOW. 1 trigin is HIGH. Reads the value of atdatas[31]. 0 atdatas[31] is 0. 1 atdatas[31] is 1. Reads the value of atdatas[23]. 0 atdatas[23] is 0. 1 atdatas[23] is 1. Reads the value of atdatas[15]. 0 atdatas[15] is 0. 1 atdatas[15] is 1. Reads the value of atdatas[7]. 0 atdatas[7] is 0. 1 atdatas[7] is 1. Reads the value of atdatas[0]. 0 atdatas[0] is 0. 1 atdatas[0] is 1. Sets the value of afvalids. 0 Sets the value of afvalids to 0. 1 Sets the value of afvalids to 1. Sets the value of atreadys. 0 Sets the value of atreadys to 0. 1 Sets the value of atreadys to 1. Reads the value of atids Reads the value of atbytess Reads the value of afreadys. 0 afreadys is 0. 1 afreadys is 1. Reads the value of atvalids. 0 atvalids is 0. 1 atvalids is 1. Integration Mode Enable. 0 Disable integration mode. 1 Enable integration mode. On reads, for each bit: 1 Claim tag bit is implemented On writes, for each bit: 0 Has no effect. 1 Sets the relevant bit of the claim tag. On reads, for each bit: 0 Claim tag bit is not set. 1 Claim tag bit is set. On writes, for each bit: 0 Has no effect. 1 Clears the relevant bit of the claim tag. Software lock key value. 0xC5ACCE55 Clear the software lock. All other write values set the software lock. Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. 0 Indicates that write operations are permitted from this interface. 1 Indicates that write operations are not permitted from this interface. Read operations are permitted. Software Lock Implemented. Indicates that a lock control mechanism is present from this interface. 0 Indicates that a lock control mechanism is not present from this interface. Write operations to the LAR are ignored. 1 Indicates that a lock control mechanism is present from this interface Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled elsewhere. Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. Indicates the security level for Non-secure non-invasive debug: 0b10 Disabled. 0b11 Enabled. Indicates the security level for Non-secure invasive debug: 0b10 Disabled. 0b11 Enabled. This bit returns 0 on reads to indicate that the ETB RAM operates synchronously to atclk. 0 The ETB RAM operates synchronously to atclk. Number of external multiplexing available. Non-zero values indicate the type of ATB multiplexing on the input to the ATB. 0b0000 Only 0x00 is supported, that is, no multiplexing is present. This value helps detect the ATB structure. Sub-classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification within the major classification as specified in the MAJOR field. 0b0010 This component is a trace buffer, ETB. Major classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification for this debug and trace component. 0b0001 This component is a trace sink component. Always 0b0000. Indicates that the device only occupies 4KB of memory. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b0100 JEDEC continuation code. Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0x07 Indicates bits[7:0] of the part number of the component. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0b1001 Indicates bits[11:8] of the part number of the component. 0b0100 This device is at r0p5. Always 1. Indicates that a JEDEC assigned value is used. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 0b0000 Indicates that there are no errata fixes to this component. Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0b0000 Indicates that the customer has not modified this component. Preamble[0]. Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. Class of the component, for example, whether the component is a ROM table or a generic CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight SoC-400 component. Preamble[1]. Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. Preamble[2]. Contains bits[23:16] of the component identification code. 0x05 Bits[23:16] of the identification code. Preamble[3]. Contains bits[31:24] of the component identification code. 0xB1 Bits[31:24] of the identification code. Hold Time. The formatting scheme can become inefficient when fast switching occurs, and you can use this setting to minimize switching. When a source has nothing to transmit, then another source is selected irrespective of the minimum number of transactions. The ATB funnel holds for the minimum hold time and one additional transaction. The actual hold time is the register value plus 1. The maximum value that can be entered is 0b1110 and this equates to 15 transactions. 0b1111 is reserved. 0b0000 1 transaction hold time. 0b0001 2 transactions hold time. 0b0010 3 transactions hold time. 0b0011 4 transactions hold time. 0b0100 5 transactions hold time. 0b0101 6 transactions hold time. 0b0110 7 transactions hold time. 0b0111 8 transactions hold time. 0b1000 9 transactions hold time. 0b1001 10 transactions hold time. 0b1010 11 transactions hold time. 0b1011 12 transactions hold time. 0b1100 13 transactions hold time. 0b1101 14 transactions hold time. 0b1110 15 transactions hold time. Enable slave port 7. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 6. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 5. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 4. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 3. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 2. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 1. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Enable slave port 0. The reset value is 0. 0 Slave port disabled. This excludes the port from the priority selection scheme. 1 Slave port enabled. Priority value of the eighth slave port. Priority value of the seventh slave port. Priority value of the sixth slave port. Priority value of the fifth slave port. Priority value of the fourth slave port. Priority value of the third slave port. Priority value of the second slave port. Priority value of the first slave port. A read access returns the value of atdatas<x>[127] of the enabled port. A write access writes to atdatam[127] of the enabled port. 0 atdata[127] of the enabled port is LOW. 1 atdata[127] of the enabled port is HIGH. A read access returns the value of atdatas<x>[119] of the enabled port. A write access writes to atdatam[119] of the enabled port. 0 atdata[119] of the enabled port is LOW. 1 atdata[119] of the enabled port is HIGH. A read access returns the value of atdatas<x>[111] of the enabled port. A write access writes to atdatam[111] of the enabled port. 0 atdata[111] of the enabled port is LOW. 1 atdata[111] of the enabled port is HIGH. A read access returns the value of atdatas<x>[103] of the enabled port. A write access writes to atdatam[103] of the enabled port. 0 atdata[103] of the enabled port is LOW. 1 atdata[103] of the enabled port is HIGH. A read access returns the value of atdatas<x>[95] of the enabled port. A write access writes to atdatam[95] of the enabled port. 0 atdata[95] of the enabled port is LOW. 1 atdata[95] of the enabled port is HIGH. A read access returns the value of atdatas<x>[87] of the enabled port. A write access writes to atdatam[87] of the enabled port. 0 atdata[87] of the enabled port is LOW. 1 atdata[87] of the enabled port is HIGH. A read access returns the value of atdatas<x>[79] of the enabled port. A write access writes to atdatam[79] of the enabled port. 0 atdata[79] of the enabled port is LOW. 1 atdata[79] of the enabled port is HIGH. A read access returns the value of atdatas<x>[71] of the enabled port. A write access writes to atdatam[71] of the enabled port. 0 atdata[71] of the enabled port is LOW. 1 atdata[71] of the enabled port is HIGH. A read access returns the value of atdatas<x>[63] of the enabled port. A write access writes to atdatam[63] of the enabled port. 0 atdata[63] of the enabled port is LOW. 1 atdata[63] of the enabled port is HIGH. A read access returns the value of atdatas<x>[55] of the enabled port. A write access writes to atdatam[55] of the enabled port. 0 atdata[55] of the enabled port is LOW. 1 atdata[55] of the enabled port is HIGH. A read access returns the value of atdatas<x>[47] of the enabled port. A write access writes to atdatam[47] of the enabled port. 0 atdata[47] of the enabled port is LOW. 1 atdata[47] of the enabled port is HIGH. A read access returns the value of atdatas<x>[39] of the enabled port. A write access writes to atdatam[39] of the enabled port. 0 atdata[39] of the enabled port is LOW. 1 atdata[39] of the enabled port is HIGH. Reads the value of atdatas[31]. 0 atdatas[31] is 0. 1 atdatas[31] is 1. Reads the value of atdatas[23]. 0 atdatas[23] is 0. 1 atdatas[23] is 1. Reads the value of atdatas[15]. 0 atdatas[15] is 0. 1 atdatas[15] is 1. Reads the value of atdatas[7]. 0 atdatas[7] is 0. 1 atdatas[7] is 1. Reads the value of atdatas[0]. 0 atdatas[0] is 0. 1 atdatas[0] is 1. A read access returns the value of afvalidm. A write access outputs the data to afvalidsn, where the value of the Ctrl_Reg at 0x000 defines n. 0 Pin is at logic 0. 1 Pin is at logic 1. A read access returns the value of atreadym. A write access outputs the data to atreadysn, where the value of the Ctrl_Reg at 0x000 defines n. 0 Pin is at logic 0. 1 Pin is at logic 1. A read returns the value of the atidsn signals, where the value of the Control Register at 0x000 defines n. A write outputs the value to the atidm port. A read returns the value of the atbytessn signal, where the value of the Ctrl_Reg at 0x000 defines n. A write outputs the value to atbytesm. A read returns the value of the afreadysn signal, where the value of the Ctrl_Reg at 0x000 defines n. A write outputs the value to afreadym. A read returns the value of the atvalidsn signal, where the value of the Ctrl_Reg at 0x000 defines n. A write outputs the value to atvalidm. Integration Mode Enable. 0 Disable integration mode. 1 Enable integration mode. On reads, for each bit: 1 Claim tag bit is implemented On writes, for each bit: 0 Has no effect. 1 Sets the relevant bit of the claim tag. On reads, for each bit: 0 Claim tag bit is not set. 1 Claim tag bit is set. On writes, for each bit: 0 Has no effect. 1 Clears the relevant bit of the claim tag. Software lock key value. 0xC5ACCE55 Clear the software lock. All other write values set the software lock. Register size indicator. Always 0. Indicates that the LAR is implemented as 32-bit. 0 Indicates that write operations are permitted from this interface. 1 Indicates that write operations are not permitted from this interface. Read operations are permitted. Software Lock Implemented. Indicates that a lock control mechanism is present from this interface. 0 Indicates that a lock control mechanism is not present from this interface. Write operations to the LAR are ignored. 1 Indicates that a lock control mechanism is present from this interface Always 0b00. The security level for Secure non-invasive debug is not implemented or is controlled elsewhere. Always 0b00 Secure invasive debug is not implemented or is controlled elsewhere. Indicates the security level for Non-secure non-invasive debug: 0b10 Disabled. 0b11 Enabled. Indicates the security level for Non-secure invasive debug: 0b10 Disabled. 0b11 Enabled. Indicates the priority scheme implemented in this component. 0b0011 Program the slave ports to have higher or lower priority with respect to each other. Indicates the number of input ports connected. 0x0 and 0x1 are illegal values. 0b0010 Two ATB slave ports. 0b0011 Three ATB slave ports. 0b0100 Four ATB slave ports. 0b0101 Five ATB slave ports. 0b0110 Six ATB slave ports. 0b0111 Seven ATB slave ports. 0b1000 Eight ATB slave ports. Sub-classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification within the major classification as specified in the MAJOR field: 0b0001 This component arbitrates ATB inputs mapping to ATB outputs. Major classification of the type of the debug component as specified in the ARM? CoreSight? Architecture Specification for this debug and trace component: 0b0010 This component has both ATB inputs and ATB outputs. Always 0b0000. Indicates that the device only occupies 4KB of memory. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b0100 JEDEC continuation code. Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0x08 Indicates bits[7:0] of the part number of the component. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0b1001 Indicates bits[11:8] of the part number of the component. 0b0011, This device is at r1p1. Always 1. Indicates that a JEDEC assigned value is used. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 0b0000 Indicates that there are no errata fixes to this component. Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0b0000 Indicates that the customer has not modified this component. Preamble[0]. Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. Class of the component, for example, whether the component is a ROM table or a generic CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight SoC-400 component. Preamble[1]. Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. Preamble[2]. Contains bits[23:16] of the component identification code. 0x05 Bits[23:16] of the identification code. Preamble[3]. Contains bits[31:24] of the component identification code. 0xB1 Bits[31:24] of the identification code. Halt on Debug. 0 Do not halt on debug, HLTDBG signal into the counter has no effect. 1 Halt on debug, when HLTDBG is driven HIGH, the count value is held static. Enable. 0 The counter is disabled and not incrementing. 1 The counter is enabled and is incrementing. Debug Halted. Current value of the timestamp counter, lower 32 bits. To change the current timestamp value, write the lower 32 bits of the new value to this register before writing the upper 32 bits to CNTCVU. The timestamp value is not changed until the CNTCVU register is written to. Current value of the timestamp counter, upper 32 bits. To change the current timestamp value, write the lower 32 bits of the new value to CNTCVL before writing the upper 32 bits to this register. The 64-bit timestamp value is updated with the value from both writes when this register is written to. Frequency in number of ticks per second. You can specify up to 4GHz. Always 0b0000. Indicates that the device only occupies 4KB of memory. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b0100 JEDEC continuation code. Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0x01 Indicates bits[7:0] of the part number of the component. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b1011 ARM. Bits[3:0] of the JEDEC JEP106 Identity Code. Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0b0001 Indicates bits[11:8] of the part number of the component. 0b0001 This device is at r0p1. Always 1. Indicates that a JEDEC assigned value is used. Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0b011 ARM. Bits[6:4] of the JEDEC JEP106 Identity Code. Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 0b0000 Indicates that there are no errata fixes to this component. Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. 0b0000 Indicates that the customer has not modified this component. Preamble[0]. Contains bits[7:0] of the component identification code. 0x0D Bits[7:0] of the identification code. Class of the component, for example, whether the component is a ROM table or a generic CoreSight SoC-400 component. Contains bits[15:12] of the component identification code. 0b1001 Indicates that the component is a CoreSight SoC-400 component. Preamble[1]. Contains bits[11:8] of the component identification code. 0b0000 Bits[11:8] of the identification code. Preamble[2]. Contains bits[23:16] of the component identification code. 0x05 Bits[23:16] of the identification code. Preamble[3]. Contains bits[31:24] of the component identification code. 0xB1 Bits[31:24] of the identification code. transmit data register receive data register baud rate divider constant N: (N>=4) 0011: N=4 ... 0111: N=8 ... 1111: N=16 baud rate divider coeffcientbaud rate formula is: BAUD RATE = Fclk/(Nx(BAUD_DIV+1)) default baud rate is 115.2K, N=16, Ffun=26MHz. choose big or little endian 0: little endian 1: big endian RX FIFO reset control 1: RX FIFO reset 0: RX FIFO not reset; or set 1'b1, auto clear to 1'b0 TX FIFO reset control 1: TX FIFO reset 0: TX FIFO not reset;or set to 1'b1,auto clear to 1'b0 after RX timeout, enable hardware flow control (on condition that HWFC is enable) 1: after RX timeout,enable hardware flow control. Do not accept data until the timeout bit has been cleared, so that disable the hardware flow control 0: after RX timeout, disable hardware flow control RX trigger RTS enable control (on condition that HWFC is enable) 1: enable RX TRIG trigger RTS flow signal 0: disable RX TRIG trigger RTS flow signal hardware flow control bit 1: enable 0: disable RX timeout interrupt control bit 1: enable 0: disable TX data interrupt control bit 1: enable TX interrupt 0: disable TX interrupt RX data interrupt control bit 1: enable RX interrupt 0: disable RX interrupt stop bit detection control bit 1: enable stop bit detection 0: disable stop bit detection stop bit control bit 1: 2bit stop bit 0: 1bit stop bit check bit 1: odd check 0: even check check bit enable or not 1: enable 0: disable TX FIFO trigger setting 00000000: 0 byte trigger 00000001: 1 byte trigger 00000010: 2 bytes trigger 00000011: 3 bytes trigger 00000100: 4 bytes trigger 01111110: 126bytes trigger 01111111: 127bytes trigger 10000000: don't trigger RX FIFO trigger settings 00000000: don't trigger 00000001: 1 byte trigger 00000010: 2 bytes trigger 00000011: 3 bytes trigger 00000100: 4 bytes trigger 01111111: 127bytes trigger 10000000: 128bytes trigger configure the time interval between sending data twice 0000: interval 0 baud rate clock 0001: interval 1 baud rate clock 1111: interval 15 baud rate clock configure the threshold value of the UART timeout interrupt counter 00000000: configure the initial value of 0 baud rate clock 00000001: configure the initial value of 1 baud rate clock 00000010: configure the initial value of 2 baud rate clock 11111111: configure the initial value of 255 baud rate clock bit type is changed from w1c to rc. request to send status bit 1: prohibit far-end to send 0: request far-end to send bit type is changed from w1c to rc. clear the sending status bit 1: prohibit home terminal to send 0: allow home terminal to send bit type is changed from w1c to rc. the received data stop bit state 1: stop bit error 0: stop bit right bit type is changed from w1c to rc. RX data parity status 1: parity error 0: parity right bit type is changed from w1c to rc. RX data timeout interrupt status bit 1: timeout 0: not timeout bit type is changed from w1c to rc. RX data interrupt status bit 1: RX_FIFO_CNTRX_TRIG 0: RX_FIFO_CNT<RX_TRIG bit type is changed from w1c to rc. TX data interrupt status bit 1: TX_FIFO_CNT TX_TRIG 0: TX_FIFO_CNT >TX_TRIG TX FIFO data number 00000000: TX FIFO has 0 data 00000001: TX FIFO has 1 data 01111111: TX FIFO has 127 data 10000000: TX FIFO has 128 data RX FIFO data number 00000000: RX FIFO has 0 data 00000001: RX FIFO has 1 data 01111111: RX FIFO has 127 data 10000000: RX FIFO has 128 data IP version r6p0 Auxadc offset function enable 0: disable offset calibration function 1: enable offset calibration function When set 1, the adc inner offset is calibrated and not include in output data auxadc convert data out average control: 000: disable adc average, output 12bit data and valid after once conversion; 001: adc convert twice and output the average data; 010: adc convert 4 times and output the average data; 011: adc convert 8 times and output the average data; 100: adc convert 16 times and output the average data; 101: adc convert 32 times and output the average data; 110: adc convert 64 times and output the average data; 111: adc convert 128 times and output the average data; the number of SW channel accessing, N+1. No use, reserved SW channel run, Write 1 to run a SW channel accessing, it is cleared by HW. ADC global enable, 0: ADC module disable; 1: ADC module enable. ADC scale setting for current ADC channel, more detail see 7.6.6.3 Application note ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC software config channel ID. ADC software config channel ID. 4h0:for BAT_DET 4h1:for general ADCI1 4h2:for general ADCI2 4h3:for general ADCI3 5h4: for general ADCI4 5h5: for VBAT_SENSE 5h6: no use 5h7 TYPEC_CC1 5h8 for THM sensor 5h9: for TYPEC_CC2 5hA-5hC: no use 5hD: for DCDC_CALOUT 5hE, for VCHGSEN 5hF, for VCHG_BG 5h10, for PROG2ADC 5h11, 5h12: no use 5h13: for SD_AVDD 5h14: for AUDIO_HEADMIC 5h15: for LDO_CALOUT0 5h16: for LDO_CALOUT1 5h17: for LDO_CALOUT2 5h18-5h1C: no use 5h1D: for DAC self offset calibretion 5h1E: for DP 5h1F: for DM ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC scale setting for current ADC channel, more detail see 7.7.6 Application note current channel delay enable, 0-diable; 1-enable. ADC conversion speed control: 0: quick mode, conversion initial includes 50 ADC clocks; 1: slow mode, conversion initial includes 70 ADC clocks. ADC channel ID Same as ADC_SW_CH_CFG adc_cs ADC HW channel accessing delay, its unit is ADC clock. It can be use for signal without enough setup time ADC conversion result. When with one more result, each read gets one result. ADC interrupt enable, 0: interrupt disable; 1: interrupt enable. ADC interrupt clear. Write "1" to clear. ADC masked interrupt. ADC raw interrupt. Current accessing channel, 0~7: fast HW channel 0~7; 8: SW channel; 9~16: slow HW channel 0~7; 31: NO request; ADC state machine status, 0: idle; 1: fast HW req; 2: SW req; 3: slow HW req; 4: fast HW wait; 5: slow HW wait; Others: reserved ADC internal counter status, 0: idle; 1~n: work or wait counter; ADC fast HW channel7 timer enable, 0: disable; 1: enable; ADC fast HW channel6 timer enable, 0: disable; 1: enable; ADC fast HW channel5 timer enable, 0: disable; 1: enable; ADC fast HW channel4 timer enable, 0: disable; 1: enable; ADC fast HW channel3 timer enable, 0: disable; 1: enable; ADC fast HW channel2 timer enable, 0: disable; 1: enable; ADC fast HW channel1 timer enable, 0: disable; 1: enable; ADC fast HW channel0 timer enable, 0: disable; 1: enable; ADC fast HW channel timer working clock divider ADC fast HW channel0 timer threshold ADC fast HW channel1 timer threshold ADC fast HW channel2 timer threshold ADC fast HW channel3 timer threshold ADC fast HW channel4 timer threshold ADC fast HW channel5 timer threshold ADC fast HW channel6 timer threshold ADC fast HW channel7 timer threshold ADC fast HW channel0 data ADC fast HW channel1 data ADC fast HW channel2 data ADC fast HW channel3 data ADC fast HW channel4 data ADC fast HW channel5 data ADC fast HW channel6 data ADC fast HW channel7 data output to analog 0: adc reference voltage is generated by local resister devider 1: adc reference voltage is direct from bandgap 1.25v voltage. output to analog THM calibration enable signal, 0: disable THM calibration(default) 1: enable THM calibration, must set high 100us before AUXADC measure THM voltage and start the calibration output to analog Aux ADC current sense enable signal, active high, default 0. ADC fast HW channel7 data valid. ADC fast HW channel6 data valid. ADC fast HW channel5 data valid. ADC fast HW channel4 data valid. ADC fast HW channel3 data valid. ADC fast HW channel2 data valid. ADC fast HW channel1 data valid. ADC fast HW channel0 data valid. bit type is changed from wc to rc. ear shut down clear bit type is changed from wc to rc. hp shut down clear bit type is changed from wc to rc. pa shut down clear bit type is changed from wc to rc. [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} [0]: audio HEAD_INSERT debounce enable [1]: audio HEAD_BUTTON_OUT debounce enable low debounce threshold(clock 1k), for HEAD_INSERT signal high debounce threshold(clock 1k), for HEAD_INSERT signal head insert detect T1/T2 timer step (clock 1k) head insert detect T0 timer , (clock 1k) head insert detect T1 timer ,step: HID_TMR_T1T2_STEP head insert detect T2 timer ,step: HID_TMR_T1T2_STEP low debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal high debounce threshold(clock 1k), for HEAD_BUTTON_OUT signal ear_shutdown hp_shutdown pa_shutdown head insert detect out: AUDIO_HEAD_INSERT_OUT state head button detect out : AUDIO_HEAD_BUTTON_OUT state u1 debounce state machine status u0 debounce state machine status ear_shutdown_enable hp_shutdown_enable pa_shutdown_enable2 pa_shutdown_enable1 pa_shutdown_enable0 1:32k_clk 0:1k_clk protect enable over-temperature protection threshold over-temperature protection precis overvoltage protection threshold overvoltage protection precis overcurrent protection threshold overcurrent protection precis int status: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} int mask = aud_irq_raw & aud_int_en int enable: [7:0]={audio_rcv_depop,audio_pacal_irq,audio_hp_dpop_irq,ovp_irq,otp_irq,pa_ocp_irq,ear_ocp_irq,hp_ocp_irq} adc right enable dac right enable adc left enable adc right enable bypass DEM Audio DACL & DACR output mixer select 00 = R/L 01 = R/0 10 = 0/L 11 = 0/0 Audio DACL & DACR output mixer select 00 = L + R 01 = 2 x L 10 = 2 x R 11 = 0 bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. bit type is changed from wc to rc. Audio LDO VB enable signal 0 = disable 1 = enable Audio LDO VB prevent reverse flow back power down signal 0 = power up 1 = power down Audio LDO VB SLEEP MODE PD signal 0 = EN 1 = PD Audio BG EN 0 = disable 1 = enable Audio BIAS EN 0 = disable 1 = enable Audio Microphone bias enable signal 0 = disable 1 = enable Audio Headset Micbias enable signal 0 = disable 1 = enable Audio HeadMic SLEEP MODE EN signal 0 = disable 1 = enable Audio MIC SLEEP MODE EN signal 0 = disable 1 = enable Audio BG Voltage 0 :BG=1.55V 1: BG=1.5V Audio BG Bias option 0 = normal 1 = debug mode Audio BG tune TC option 00: normal 01: TC reduce 10: TC reduce more 11: TC enhance Audio MICBIAS power down signal (do not control discharge circuit) 0 = power up 1 = power down Audio Headmic VREF 0 = main-BG 1 = AUD_BG HMIC_COMP_MODE_EN: 0 = disable 1 = headmicbias filter RC integrated in chip Audio LDO_VB output voltage calibration signal 00000 = -13.3% 00001 = -12.5% 00010 = -11.7% 00011 = -10.8% 00100 = -10% 00101 = -9.2% 00110 = -8.4% 00111 = -7.5% 01000 = -6.7% 01001 = -5.8% 01010 =-5% 01011 = -4.2% 01100 = -3.3% 01101 = -2.5% 01110 = -1.67% 01111 = -0.83% 10000 = 0 10001 = 0.83% 10010 = 1.67% 10011 = 2.5% 10100 = 3.3% 10101 = 4.2% 10110 = 5% 10111 =5.8% 11000 = 6.7% 11001 = 7.5% 11010 = 8.4% 11011 = 9.2% 11100 = 10% 11101 = 10.8% 11110 = 11.7% 11111 = 12.5% Audio ADC/DAC/DRV VCM & LDO VB output voltage control bit (VB should be set larger than 3.0V) 00000 -00011 = forbidden 00100 = 3.0V 00101 = 3.025V 00110 = 3.05V 00111 = 3.075V 01000 = 3.1V 01001 = 3.125V 01010 =3.15V 01011 = 3.175V 01100 = 3.2V 01101 = 3.225V 01110 = 3.25V 01111 = 3.275V 10000 = 3.3V 10001 = 3.325V 10010 = 3.35V 10011 = 3.375V 10100 = 3.4V 10101 = 3.425V 10110 = 3.45V 10111 =3.475V 11000 = 3.5V 11001 = 3.525V 11010 = 3.55V 11011 = 3.575V 11100 = 3.6V 11101 - 11111 = forbidden Audio headmicbias output voltage control bit 000 = 2.2V 001 = 2.4V 010 = 2.5V 011 = 2.6V 100 = 2.7V 101 = 2.8V 110 = 2.9V 111 = 3.0V Audio MICBIAS output voltage select signal 000 = 2.2V 001 = 2.4V 010 = 2.5V 011 = 2.6V 100 = 2.7V 101 = 2.8V 110 = 2.9V 111 = 3.0V AUD HP-PGA BIAS current: 00:X1 11:X2 AUD HP-PGA 3rd stage BIAS current: 000: 5uA 001:7.5uA 010:10uA 011: 12.5uA 100: 15uA 101: 17.5uA 110:20uA 111: 22.5uA Audio PA class-AB mode Quiescent current decreasing level 00=3.5mA, 01=2.5mA, 10=1.9mA, 11=1.6mA Audio ADC & PGA ibias current control bit <3:2> control the ibias of the PGA 00 = 10uA 01 = 7.5uA 10 = 5uA 11 = 5uA <1:0> control the ibias of the modulator 00 = 5uA 01 = 3.75uA 10 = 2.5uA 11 = 2.5uA Audio DACL & DACR output gain control bit 00 = 0dB 01 = -0.75dB 1x=-1.5dB HP&RCV DRV SEL 00: input gm/2, miller cap cut 01: input gm/2, miller cap normal 10: input gm normal, miller cap cut 11: input gm normal, miller cap normal Audio PA over temperature protection circuit power down signal 0 = power up 1 = power down Audio PA over temperature protection circuit temperature select 000: 4C -> -14C 001: 25C -> 8C 010: 47C -> 31C 011: 68C -> 52C 100: 89C -> 74C 101: 110C -> 95C 110: 130C -> 115C 111: 150C -> 135C Audio VBAT_PA over voltage protection circuit power down signal 0 = power up 1 = power down Audio VBAT_PA over voltage protection circuit threshold select 0 = 0.3V 1 = 0.6V Audio VBAT_PA over voltage protection circuit voltage select RG_AUD_PA_OVP_THD = 0/1 000 = 5.8 -> 5.5/5.2 001 = 6.0 -> 5.7/5.4 010 = 6.2 -> 5.9/5.6 011 = 6.4 -> 6.1/5.8 100 = 6.6 -> 6.3/6.0 101 = 6.8 -> 6.5/6.2 110 = 7.0 -> 6.7/6.4 111 = 7.2 -> 6.9/6.6 Audio PA over current protection circuit power down signal 0 = power up,1 = power down Audio PA class-AB mode over current protection circuit current select 0=800mA 1=1000mA Audio PA over current protection circuit power down signal 0 = power up,1 = power down Audio Driver over current protection current select HP mode: 00--108mA 01--150mA 10--156mA 11--195mA RCV mode: 00--209mA 01300mA 10310mA 11-- 400mA Audio PA VCOM voltage control bit 00 = 0.55xVDD 01 = 0.5xVDD 10 = 0.45xVDD 11 = 0.4xVDD Audio PA class-D mode PWM Gain select 00 = 1 01 = 1.5 10 = 1.67 11 = 2 Audio PA class-D mode PWM logic delay time select 00 = 7ns 01 = 14ns 10 =24ns 11 = 29ns Audio PA class-D output edge slew rate control 000 = 2ns 001 = 4ns 010 = 6ns 011 = 8ns 100 = 10ns 101=12ns 110 = 14ns 111 = 16ns Audio PA class-D mode spread spectrum enable signal 0 = disable 1 = enable Audio PA class-D mode spread spectrum reset enable signal 0 = disable 1 = enable Audio PA class-D mode spread spectrum dither level select signal when PA_DTRI_F<1:0> = 00/01/10/11 00 = 3.2%/1.6%/0.8%/0.4% 01 = 9%/4.7%/2.3%/1.2% 10 = 22%/ 11%/5.5%/2.7% 11 = 47%/ 23%/ 12%/ 6% Audio PA class-D mode spread spectrum 32k dither clock select signal 0 = disable 1 = enable Audio PA class-D mode spread spectrum dither clock divider select signal 000 = 1 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 1/32 110 = 1/64 111 = 1/128 Audio Speaker PA class-D mode enable signal 0 = disable (CLASS-AB mode) 1 = enable(CLASS-D mode) Audio Speaker PA class-D mode switching frequency locking enable signal 0 = disable 1 = enable Audio Speaker PA class-D mode switching frequency locking resolution select 0 = 1X 1 = 2X Audio Speaker PA class-D mode switching frequency select 000 = 330kHz 001 = 490kHz 010 = 650KHz 011 = 810KHz 100 = 970kHz 101 = 1.12MHz 110 = 1.27MHz 111 = 1.42MHz Audio PA class-D mode Switching frequency hopping level 000000=0Hz 000001=1*2.5KHz 000010=2*2.5KHz 000011=3*2.5KHz 000100=4*2.5KHz 000101=5*2.5KHz 000110=6*2.5KHz 000111=7*2.5KHz 001000=8*2.5KHz 001001=9*2.5KHz 001010=10*2.5KHz 001011=11*2.5KHz 001100=12*2.5KHz 001101=13*2.5KHz 001110=14*2.5KHz 001111=15*2.5KHz 010000=16*2.5KHz 010001=17*2.5KHz 010010=18*2.5KHz 010011=19*2.5KHz 010100=20*2.5KHz 010101=21*2.5KHz 010110=22*2.5KHz 010111=23*2.5KHz 011000=24*2.5KHz 011001=25*2.5KHz 011010=26*2.5KHz 011011=27*2.5KHz 011100=28*2.5KHz 011101=29*2.5KHz 011110=30*2.5KHz 011111=31*2.5KHz 100000=32*2.5KHz 100001=33*2.5KHz 100010=34*2.5KHz 100011=35*2.5KHz 100100=36*2.5KHz 100101=37*2.5KHz 100110=38*2.5KHz 100111=39*2.5KHz 101000=40*2.5KHz 101001=41*2.5KHz 101010=42*2.5KHz 101011=43*2.5KHz 101100=44*2.5KHz 101101=45*2.5KHz 101110=46*2.5KHz 101111=47*2.5KHz 110000=48*2.5KHz 110001=49*2.5KHz 110010=50*2.5KHz 110011=51*2.5KHz 110100=52*2.5KHz 110101=53*2.5KHz 110110=54*2.5KHz 110111=55*2.5KHz 111000=56*2.5KHz 111001=57*2.5KHz 111010=58*2.5KHz 111011=59*2.5KHz 111100=60*2.5KHz 111101=61*2.5KHz 111110=62*2.5KHz 111111=63*2.5KHz Audio PA Driver stop output enable signal 0 = disable, 1 = enable Audio PA output short to VBAT detect enable signal 0 = disable 1 = enable Audio PA output short to GND detect enable signal 0 = disable 1 = enable Audio digital core clcok input enable signal 0 = disable 1 = enable Audio digital loop clcok input enable signal 0 = disable 1 = enable Audio analog core clcok input enable signal 0 = disable 1 = enable Audio analog ADC clock input enable signal 0 = disable 1 = enable Audio analog ADC clock reset enable signal 0 = EN 1 = RESET Audio DAC clock input enable signal 0 = disable 1 = enable Audio DRV clock input enable signal 0 = disable 1 = enable Audio DCDC GEN clock input enable signal 0 = disable 1 = enable Audio DCDC MEM clock input enable signal 0 = disable 1 = enable Audio DCDC CORE clock input enable signal 0 = disable 1 = enable Audio VAD enable signal 0 = disable 1 = enable Audio ADC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk 01 = Fclk / 2 Audio DAC clock frequency select (based on Fclk=6.5MHz) 00 = Fclk 01/11 = Fclk x 2 10 = Fclk / 2 Audio PGA&ADC BIAS en signal 0 = disable 1 = enable Audio PGA & ADC VCM buffer enable signal 0 = disable 1 = enable Audio ADC PGAL enable signal 0 = disable 1 = enable Audio ADC PGAR enable signal 0 = disable 1 = enable Audio ADC PGAL bypass select signal 00 = normal input 01 = HEADMIC to ADCL 10/11 = All disconnected Audio ADC PGAR bypass select signal 00 = normal input 01 = HEADMIC to ADCR 10/11 = All disconnected Audio ADCL enable signal 0 = disable 1 = enable Audio ADCL reset enable signal 0 = disable 1 = enable Audio ADCR enable signal 0 = disable 1 = enable Audio ADCR reset enable signal 0 = disable 1 = enable Audio ADC VREF current drv increasing by 1.3 times enable signal 0 = disable 1 = enable Headmic button release depop signal 0 = disable 1 = depop Headmic button release depop signal to VCM enable 0 = disable 1 = depop Reserved ADPGA_Internal common voltage select 00: 0.5*VB 01: 0.45*VB 10: 0.425*VB 11:0.4*VB Audio ADC PGAL Gain control 000 = 0dB 001 = 3dB 010 = 6dB 011 = 12dB 100 = 18dB 101 = 24dB 110 = 30dB 111 = 36dB Audio ADC PGAR Gain control 000 = 0dB 001 = 3dB 010 = 6dB 011 = 12dB 100 = 18dB 101 = 24dB 110 = 30dB 111 = 36dB Audio DACL/R dc offset trim bit 000 = 0 001 = +1/20*VFS 010 = +2/20*VFS 011 = +1/20*VFS 100 = 0 101 = -1/20*VFS 110 = -2/20*VFS 111 = -1/20*VFS Audio DACS dc offset trim bit 000 = 0 001 = +1/20*VFS 010 = +2/20*VFS 011 = +1/20*VFS 100 = 0 101 = -1/20*VFS 110 = -2/20*VFS 111 = -1/20*VFS Audio DACS enable signal 0 = disable 1 = enable Audio DACL enable signal 0 = disable 1 = enable Audio DACR enable signal 0 = disable 1 = enable Audio Driver HPL dummy loop enable signal 0 = disable 1 = enable Audio Driver HPL dummy loop end enable signal 0 = disable 1 = enable: true loop fade in Audio Driver HPR dummy loop enable signal 0 = disable 1 = enable Audio Driver HPR dummy loop end enable signal 0 = disable 1 = enable: true loop fade in Audio Driver RCV dummy loop enable signal 0 = disable 1 = enable Audio Driver RCV dummy loop end enable signal 0 = disable 1 = enable: true loop fade in Audio Driver HPL output enable signal 0 = disable 1 = enable Audio Driver HPR output enable signal 0 = disable 1 = enable Audio Driver vcm buffer enable signal 0 = disable 1 = enable Audio Driver RCV output enable signal 0 = disable 1 = enable Audio Speaker PA (Driver SPKL) enable signal 0 = disable 1 = enable Audio DACL/R dc offset enable signal 0 = disable 1 = enable Audio DACS dc offset enable signal 0 = disable 1 = enable NG_PA enable control 0 = mute disable 1 = mute enable Audio DACL to HPL enable signal 0 = disable 1 = enable Audio DACR to HPR enable signal 0 = disable 1 = enable Audio DACL to Receiver/Earpiece enable signal 0 = disable 1 = enable Audio DACS to PA enable signal 0 = disable 1 = enable Audio HMIC to PA enable signal 0 = disable 1 = enable when debug=1, HMIC to PA path on, no matter "RG_AUD_SDAPA" when debug=0, HMIC to PA path off, "RG_AUD_SDAPA" is enable Audio MIC to HPL enable signal 0 = disable 1 = enable when debug=1, MIC to HPL path on , "RG_AUD_SDALHPL"/"RG_AUD_SDALRCV" is dis-enable when debug=0, MIC to HPL path off , "RG_AUD_SDALHPL"/"RG_AUD_SDALRCV" is enable MIC1 to Audio ADC PGAL enable signal 0 = disable 1 = enable MIC2 to Audio ADC PGAR enable signal 0 = disable 1 = enable HEADMIC to Audio ADC PGAL enable signal 0 = disable 1 = enable HEADMIC to Audio ADC PGAR enable signal 0 = disable 1 = enable Audio Speaker Driver PGA Gain control <3:2>For Class-D PGA, dft=00 00 = 0dB 01 = 1.5dB 10 = 3dB 11 = 3dB <1:0>For Class-AB PGA 00 = -3dB(20K) 01 = 0dB(28K) 10 = 1.16dB(32K) 11 = 1.16dB(32K) Audio Receiver/Earpiece Driver RCV_P/RCV_N PGA Gain control 0010 = 6dB 0011 = 3dB 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute Audio Headphone left channel Gain control 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute Audio Headphone right channel Gain control 0100 = 0dB 0101 = -3dB 0110 = -6dB 0111 = -9dB 1000 = -12dB 1001 = -15dB 1010 = -18dB 1111 = mute MUX2ADC SEL PD 0 = power up 1 = power down Audio signal input to AuxADC enable signal 0 = disable 1 = enable Audio headset button detect circuit enable signal 0 =disable 1 = enable Audio headset detect signal RG_HP_DRIVER_EN software control enable signal 0 = DG_HP_DRIVER_EN work 1 = RG_HP_DRIVER_EN work Audio headset detect reference voltage circuit enable signal 0 =disable 1 = enable Audio headset mic detect circuit power enable signal 0 =disable 1 = enable Audio signal input to AuxADC scale select signal 0 =little scale 1 =large scale(4:1) Audio headset_LINT low detect filter enable signal 0 = no filter 1 = filter Audio signal input to AuxADC buffer chop signal (1kHz) Audio signal input to AuxADC select 000 = HEADMIC_IN_DET 001 = HEADSET_L_INT 010 = HP_L 011 = HP_R 100 = AVDD_VB 101 = VDDPA 110 = MICBIAS 111 = HEADMIC_BIAS Audio headset detect circuit current select signal 0000 =0 0001 = 0.5u 0010 =1u 0011 = 1.5u 0100 =2u 0101 = 2.5u 0110 =3u 0111 = 3.5u 1000 =4u 1001 = 4.5u 1010 =5u 1011 = 5.5u Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 2V 001 =2.1V 010 = 2.2V 011 =2.3V 100 = 2.4V 100 =2.5V 110 = 2.6V 111 = 2.7V Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 000 = 25mV 001 =50mV 010 = 100mV 011 = 150mV 100 = 200mV 100 =250mV 110 = 300mV 111 = 350mV Audio headset_L_INT insert detect voltage select signal (VDDIO=2.8V) 00 = 1.7V 01 = 1.8V 10 = 1.9V 11 = 2V Audio L_DET pull up power down signal 00 = power up 01 = power down 10/11 = high-z Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden BYPASS CHG_STS signal 1 = bypass CHG_EN 0 = dis-bypass CHG_EN Audio Headphone jack type select (Head_L_INT) 00 = Tie High 01 = Tie Low 10 = No Spring 11 = forbidden Audio head microphone button pressed detect voltage select signal (VDDIO=2.8V) 0000 = 1.0V 0001 = 0.95V 0010 = 0.9V 0011 = 0.85V 0100 = 0.8V 0101 = 0.75V 0110 = 0.7V 0111 = 0.65V 1000 = 0.6V 1001 = 0.55V 1010 =0.5V 1011 = 0.45V 1100 = 0.4V 1101/1110/1111 = forbidden Audio headset button detect circuit hysteresis sel signal 00 = 10mV 01 = 20mV 10 = 40mV 11 =forbidden Audio headset plug out detect enable signal 0 = disable 1 = enable Audio headset detect signal LDRV_ENB software control signal, it should be set from 0->1 several ms (ex. 5ms) after audio driver HPL output enable signal (RG_AUD_HPL_EN) set from 1-> 0 Audio Driver HPL output enable signal to headset detect delay function enable signal 0 = disable delay-reg(RG_AUD_HPL_EN_D2HDT_T) 1 = enable delay-reg(RG_AUD_HPL_EN_D2HDT_T) Audio Driver HPL output enable signal (RG_AUD_HPL_EN) to headset detect delay time 00 = 8*Tclk 01 = 16*Tclk 10 = 32*Tclk 11 = 64*Tclk Audio digital control logic enable signal 0 = disable 1 = enable Audio digital control logic reset enable signal 0 = disable 1 = enable Audio DRV delay timer control signal 000 = 0us 001 = 30us 010 = 60us 011 = 90us 100 = 120us 101 = 150us 110 = 180us 111 = 210us Audio DRV soft start enable signal 0 = disable 1 = enable Soft reset dpop module . 0:disable , 1:enable Audio PA calibration clock input enable signal 0 = disable 1 = enable Audio PA PWM clock divider select signal 00 = 1/128 01 = 1/64 10 = 1/256 11 = 1/1 Audio VBAT_PA over voltage protection circuit mode change signal 0 = enable Class-AB mode 1 = keep the previous mode Audio PA over current protection circuit mute timer control signal 000 = 0ms 001 = 1ms 010 = 4ms 011 = 16ms 100 = 64ms 101 = 256ms 110 = 1s 111 = 4s Audio VBAT_PA over voltage protection circuit alert deglitch enable signal 0 = disable 1 = enable Audio VBAT_PA over voltage protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable 1 = enable Audio PA over temperature protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms Audio PA over temperature protection circuit mute enable signal 0 = disable 1 = enable Audio PA over temperature protection circuit alert deglitch enable signal 0 = disable 1 = enable Audio PA over temperature protection circuit alert deglitch timer control signal 000 = 0ms 001 = 0.06ms 010 = 0.24ms 011 = 1ms 100 = 4ms 101 = 16ms 110 = 64ms 111 = 256ms Audio PA over current protection circuit mute power down signal 1 = enable mute 0 = disable mute Audio PA over current protection circuit mute timer control signal 000 = 0ms 001 = 1ms 010 = 4ms 011 = 16ms 100 = 64ms 101 = 256ms 110 = 1s 111 = 4s HPL depop DAC current setting HPR depop DAC current setting Reserved, always=1 Reserved, always=1 Audio HP de-pop fade in function enable signal 0 = disable 1 = enable Audio HP de-pop fade out function enable signal 0 = disable 1 = enable Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 Audio HP de-pop gain step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 1 001 = 2 010 = 3 011 = 4 100 = 5 101 = 6 110 = 7 111 = 8 Audio HP de-pop gain time step (RG_AUD_HP_DPOP_RES_PD=0) 000 = 30us 001 = 60us 010 = 120us 011 = 250us 100 = 500us 101 = 1ms 110 = 2ms 111 = 4ms Audio HPL_RDAC status signal 0 = unfinish/have never done 1 = finish Audio HPR_RDAC status signal 0 = unfinish/have never done 1 = finish Audio dc-calibration waiting time, every data change 000 = 2Tclk 001 = 3Tclk 010 = 4Tclk 011 = 5Tclk 100 = 6Tclk 101 = 7Tclk 110 = 8Tclk 111 = 9Tclk Audio DePOP HPL DAC clock(start-up) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk Audio DePOP HPL DAC data increase step(start-up) 00 = +1 01 = +2 10 = +4 11 = +8 Audio DePOP HPL DAC data final value(start-up) 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 =256 Audio DePOP HPL DAC clock(rising/falling) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk Audio DePOP HPL DAC data increase step(rising/falling) 00 = +1 01 = +2 10 = +4 11 = +8 depop_hpl_current_sel 00: X2 01:X1 10:X2/3 11:X1/2 depop_hpr_current_sel 00: X2 01:X1 10:X2/3 11:X1/2 Audio DePOP HPR DAC clock(start-up) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk Audio DePOP HPR DAC data increase step(start-up) 00 = +1 01 = +2 10 = +4 11 = +8 Audio DePOP HPR DAC data final value(start-up) 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 =256 Audio DePOP HPR DAC clock(rising/falling) 00 = 1Tclk 01 = 2Tclk 10 = 4Tclk 11 = 8Tclk Audio DePOP HPR DAC data increase step(rising/falling) 00 = +1 01 = +2 10 = +4 11 = +8 depop_runing time 000: 10ms 001: 20ms 010: 40ms 011: 80ms 100:160ms 101: 320ms 110: 640ms 111: 1280ms depop_finish waiting time 000: 10ms 001: 20ms 010: 40ms 011: 80ms 100:160ms 101: 320ms 110: 640ms 111: 1280ms CHG_EN_Delay time 00: 1Tclk 01: 2Tclk 10: 4Tclk 11: 8Tclk depop path on delay time 00: 1Tclk 01: 2Tclk 10: 4Tclk 11: 8Tclk DCCALI_IDAC_repeat_goal 000: 8 001: 9 010: 10 011:11 100:12 101:13 110:14 111:7 IDAC LSB SETTING: 00: 10nA 01:15nA 10:5nA 11:10nA RDAC current enhancement 0 = X1 1 = X2 DC-calibraion start signal 0 ---> 1 start calibration DC-calibraion enable signal (digital) 0: disable 1: enable DC-calibraion enable signal (analog) 0: disable 1: enable Audio DC-calibration status signal 0 = unfinish/have never done 1 = finish DCCALI_STS_BYPASS=0, not bypass DCCALI_process DCCALI_STS_BYPASS=1, bypass DCCALI_process Audio DC-calibration finish insert signal 0 = unfinish 1 = finish depop start signal 0 ---> 1 start calibration depop charge en 0: disable 1:enable plug_in=1, headphone has been inserted depop_ana_en 0: disable 1:enable Audio plug-in depop status signal 0 = depop not finish 1 = depop finish Audio plug-in depop charge finish insert signal 0 = unfinish 1 = finish HPL_pull_up enable 0: pull up enable 1: pull up disable HPR_pull_up enable 0: pull up enable 1: pull up disable INSBUF_EN 0: disable 1:enable Reserved AUD_DRV_DEPOP_BIAS_CURRENT SEL 00: 1.25uA 01:2.5uA 10:3.75uA 11:5uA AUD_DRV_DEPOP_OPA_CURRENT SEL 00: LS_I=5uA, LS_R=100K 01: LS_I=10uA, LS_R=100K 10: LS_I=5uA, LS_R=50K 11: LS_I=10uA,LS_R=50K Hardware control/software control sel <3>: 0: depend on analog comp value 1: bypass analog comp value <2>: 0: RG_AUD_VCMI_SEL change, repeat dccali 1: change RG_AUD_VCMI_SEL, get two dccali value, choose any according RG_AUD_VCMI_SEL =0/=1 <1>: 0: hw control DC_CALI_IDAC_CURSEL, 1: sw control DC_CALI_IDAC_CURSEL <0>: 0: hw control RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN 1: sw control RG_HPL_PU_ENB, RG_HPR_PU_ENB, RG_INSBUF_EN HPL_DCCALI_RDAC_VALUE HPR_DCCALI_RDAC_VALUE HPL_DCCALI_IDAC_path HPR_DCCALI_IDAC_path HPL_DCCALI_IDAC_VALUE HPR_DCCALI_IDAC_VALUE HPL_DCCALI_IDAC_VALUE HPR_DCCALI_IDAC_VALUE Audio PA clock calibration data delta output Audio PA clock calibration data valid signal 0 = not valid 1 = data valid Audio headset insert alert signal (need software anti-dither) 0 = normal 1 = plug in Audio headset-H insert alert signal (need software anti-dither) 0 = normal 1 = plug in Audio headset-L insert alert signal (need software anti-dither) 0 = normal 1 = plug in Audio headset microphone insert alert signal (need software anti-dither) 0 = normal 1 = plug in Audio headset microphone button press alert signal (need software anti-dither) 0 = normal 1 = button press Audio PA output short to VBAT detect ALERT signal 0 = normal 1 = short Audio PA output short to GND detect ALERT signal 0 = normal 1 = short Audio PA over voltage protection circuit alert signal 0 = normal 1 = over temperature Audio PA over temperature protection circuit alert signal 0 = normal 1 = over temperature Audio Driver over current protection circuit alert signal <3:2> for SPK <1:0> for Headphone/Earpiece DCDC GEN/MEM clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 DCDC CORE clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 DCDC CHG clock frequency select (based on Fclk=6.5MHz) 00 = Fclk/4 01 = Fclk / 3 10/11 = Fclk / 2 Audio PA clock frequency select (based on ADC Clock) 00 = 1/2 01 = 1/4 10 = 1/8 11 = 1/16 Audio clock PN select (If RG_AUD_AD_CLK_F[1:0]=00 or 10 & RG_AUD_DA_CLK_F[1:0]=00, RG_AUD_CLK_PN_SEL) <0> CLK_AUD_DIG_LOOP <1> CLK_AUD_DIG_6P5M <2> CLK_AUD_DAC <3> CLK_AUD_ADC <4> CLK_AUD_DCDCGEN <5> CLK_AUD_VAD_CLK_SEL <6> CLK_AUD_DCDCCORE <7> RG_AUD_VB_V<5> ADC FIFO almost full signal ADC FIFO real empty. There is no data in ADC FIFO ADC FIFO real full. ADC FIFO read address ADC FIFO write address DAC FIFO real empty. There is no data in ADC FIFO DAC FIFO real full. DAC FIFO read address DAC FIFO write address Internal fsm state Internal counter Internal counter If 1, begin to receive data from A-die BLTC WLED output value when by SW. BLTC WLED output selection 1: output by SW; 0: output by HW. BLTC WLED output type 1: Normal PWM; 0: Breath light. BLTC WLED run 1: start BLTC WLED; 0: stop BLTC WLED. BLTC B output value when by SW. BLTC B output selection 1: output by SW; 0: output by HW. BLTC B output type 1: Normal PWM; 0: Breath light. BLTC B run 1: start BLTC B; 0: stop BLTC B. BLTC G output value when by SW. BLTC G output selection 1: output by SW; 0: output by HW. BLTC G output type 1: Normal PWM; 0: Breath light. BLTC G run 1: start BLTC G; 0: stop BLTC G. BLTC R output value when by SW. BLTC R output selection 1: output by SW; 0: output by HW. BLTC R output type 1: Normal PWM; 0: Breath light. BLTC R run 1: start BLTC R; 0: stop BLTC R. BLTC prescale coefficient. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC prescale coefficient. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC prescale coefficient. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. BLTC WLED busy, active high. BLTC B busy, active high. BLTC G busy, active high. BLTC R busy, active high. Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) Current control bit. 64 steps. Min current: 1.68mA (000000) One step is 0.84mA (default 6b0) BLTC prescale coefficient. PWM duty counter,duty cycle = duty /(mod+1) PWM mod counter. Output falling time, its unit is 0.125s, it should be >0. Output rising time, its unit is 0.125s, it should be >0. Output low time, its unit is 0.125s, it should be >0. Output high time, its unit is 0.125s, it should be >0. Power down signal 0:bltc_pd depend on SW_PD 1:bltc_pd depend on bltc output Power down signal : 0: Power on the reference current source 1: Power down the reference current source BLTC_VERSION information Default value is 16h0100 (r1p0) Write this bit 1 will start calibration process, write 0 has no effect Read this this will get the current calibration status. If 1, means the calibration is on progress. If 0, means calibration is finished, current is idle. Calibration cycle control, this is the low part of calibration cycle. Coupled with CAL_CYCLE_P1[7:0], the whole calibration cycles is : Calibration cycle = {CAL_CYCLE_P1[7:0],CAL_CYCLE_P0[15:0]}; The calibration cycle means using how many self-oscillator clocks to do calibration, the more cycles used, the more accuracy will be achieved. To make calculation simple, calibration cycle should be multiple of 2, that means, Calibration cycle = 2^n Calibration cycle control, this is the high part of calibration cycle. Calibration result, part 0. Coupled with CAL_RESULT_P1, the total calibration result is : Cal result = {CAL_RESULT_P1[15:0],CAL_RESULT_P0[15:0]} Calibration result, part 1. Write this bit 1 will start 32k sigma-delta divider factor update process. write 0 has no effect Read this this will get the current update process status. If 1, means the update process is not finished. If 0, means this process is finished,current is idle. 32k sigma-delta divider factor fraction part. This field is part of the fraction bits. 32k sigma-delta divider integer. Factor update done interrupt enable Calibration done interrupt enable.. Write 1 to this bit will clear OSC_FAC_UPD_DONE_INT_RAWWrite 0 has no effect Write 1 to this bit will clear OSC_CAL_DONE_INT_RAWWrite 0 has no effect Interrupt raw bits, 1 means factor update process has finished. Interrupt raw bits, 1 means self-oscillator calibration process has finished. 0: Function test mode 1: Analog test mode 0: IOMODE 1-255: Analog Test Mode EIC bits data input. Note: EICDATA synchronizes the original data inputs with 2 cycles of Rtcdiv5_clk, so SW need delay 2ms to get the exact value of original data inputs when Rtcdiv5_clk is enabled. bit type is changed from r/w to rw. EICDATA register can be read if EICDMSK set 1 EIC bits interrupt status register:1 high levels trigger interrupts, 0 low levels trigger interrupts. EIC bits interrupt enable register:1 corresponding bit interrupt is enabled. 0 corresponding bit interrupt isnt enabled EIC bits raw interrupt status register:1 interrupt condition met0 condition not met EIC bits masked interrupt status register:1 Interrupt active 0 interrupt not active EIC bits interrupt clear register:1 clears detected interrupt. 0 has no effect. EIC bits trig control register:1: generate the trig_start pulse0: no effect It must set EICTRIG for using de-bounce function and getting active interrupt. 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond 1: clock of dbnc forced open; 0: no effect de-bounce mechanism enable or disable: 1 enable,0 disable(bypass) de-bounce counter period value setting, the unit is millisecond Reserved Reserved 0: Normal read mode, 1:Margin read1 mode Efuse read data, If SW use efuse controller to send a read command to efuse memory, the return value will store here. Efuse data to be write. If SW want to program the efuse memory, the data to be programmed will write to this register before SW issue a PGM command. The efuse memory block index to be read or write. Write 1 to this bit will clear normal read flag. This bit is self-clear, read this bit will always get 0 Write 1 to this bit start READ mode(read mode). This bit is self-clear, read this bit will always get 0 Write 1 to this bit start PGM mode(PGM mode). This bit is self-clear, read this bit will always get 0 1 indicate EFUSE normal read has been done If SW send a PGM command to memory and memory controller find the memory need to be protected (LSB of 64 bit is 1), this flag will be set to 1. 1 indicate efuse memory in standby mode 1 indicate efuse memory in read mode 1 indicate efuse memory in programming mode Magic number, only when this field is 0x2720, the Efuse programming command can be handle. So if SW want to program efuse memory, except open clocks and power, 2 other conditions must be met : a) PGM_EN =1; b) EFUSE_MAGIC_NUMBER = 0x2720 Magic number, only when this field is 0x6868, the margin read is usable. Config this register to control the timing of writing operation related signals. 300us voltage rise,20usx16 program,300us voltage fall Config this register to control the timing of writing operation related signals 2.348us Read Time Qmax Update enables. Write 1 to this bit will do a Qmax update processing. It is auto cleared to 0, after write 1. To check the updating status, please read QMAX_UPD_STS. FGU Reset signal. Write this bit to reset the module, it is auto cleared to 0 after reset. When write CLBCNT_SETH & CLBCNT_SETL, software should write this bit after write all of the two register to sync. It to CLK32KHz domain. bit type is changed from r/w to rw. Software force qmax low voltage area to be locked, (Need to check WRITE_ACTIVE_STS) bit type is changed from r/w to rw. Software force qmax high voltage area to be locked bit type is changed from r/w to rw. When set to 1, qmax counter will be forced to intergrate current, regardless of qmax lock conditions. bit type is changed from r/w to rw. Voltage high bit valid 0: voltage is 12 bits valid (high bit is omitted) 1: voltage is 13 bits valid bit type is changed from r/w to rw. FGU Disable signal. It indicates if the FGU is worked or not. 0: FGU is not disable and worked 1: FGU is disable and not worked bit type is changed from r/w to rw. Coulomb Counter Delta Threshold Mode. This bit indicates if the coulomb counter is working when the battery is in low power condition. 0: work when in low power condition 1: no work when in low power condition It is working in default. bit type is changed from r/w to rw. Voltage duty ratio. 2h0: 1-7 2h1: 1-3 2h2: 1-1 2h3: 1-0 When ADC_SEL = 0, these bits are invalid. Refer to Timing Diagram for detail bit type is changed from r/w to rw. When just use voltage of this module, this bit can disable all the current calculation logic, which will save power. 0: not disable current 1: disable current logic bit type is changed from r/w to rw. When update the Qmax, if the battery is not in relax mode, then the voltage wont lock, write this bit will force the voltage lock to OCV either the battery is in relax mode or in active mode. 0: not force lock 1: force lock bit type is changed from r/w to rw. There are 2 methods to judge whether the battery is in low power mode. 0: use relax counter to judge 1: use deep_sleep signal to judge bit type is changed from r/w to rw. When the battery is in relax mode, the current can be set to sample at each 1 second instead of each 500ms, which will save power. If this bit is set 1, then the module will auto switch to low power mode. 0: not auto low, SW should control manually 1: auto low when the battery is in relax mode. Note: when AD1_ENABLE = 0, the voltage and current is measured in ADC0 Note: when AD1_ENABLE = 1, the current is measured in ADC0, and voltage is measured in ADC1. bit type is changed from r/w to rw. RG_SD_RSV[14] bit type is changed from r/w to rw. Enable Common voltage tied to ground bit type is changed from r/w to rw. Enable high current mode bit type is changed from r/w to rw. Enable reference band gap bit type is changed from r/w to rw. When ADC_EN_SEL is 0, ADC enable is always high When ADC_EN_SEL is 1, FGU takes the control of ADC enable Ad0_in_data Ad1_in_data bit type is changed from r/w to rw. Force ADC1_VIN_EN interface to set value. bit type is changed from r/w to rw. Force ADC0_VIN_EN interface to set value. bit type is changed from r/w to rw. Force ADC0_IIN_EN interface to set value. bit type is changed from r/w to rw. Force ADC0/ADC1 interface enable. bit type is changed from r/w to rw. ADC1 Voltage Reference. 0: 0.1V 1: 0.2V bit type is changed from r/w to rw. ADC0 Voltage Reference. 0: 0.1V 1: 0.2V bit type is changed from r/w to rw. ADC0 / ADC1 Reset bit type is changed from r/w to rw. ADC0 / ADC1 Power Down This flag indicates whether the battery is plugged in during power on sequence. This flag indicates the power on open circuit voltage measurement is invalid. Select current and voltage enable signal between fgu_top and fgu_ana 0: select fgu_ana current and voltage enable signal 1: select fgu_top current and voltage enable signal Indicate the power is lower 0: not lower 1: lower Note: Case LOW_POWER_MODE = 0 when CURT_LOW is 1 and the relax counter is bigger than threshold, then the power is low. Case LOW_POWER_MODE = 1; The power mode select the deepsleep, then it is equal to deepsleep signal. Indicate the current is lower then threshold 0: not lower 1: lower Note: when CURT_LOW is occur, the POWER_LOW may not occur other than the relax count is bigger than threshold. To update the Qmax, there should be two OCV lock. 2b00: OCV0 not locked OCV1 not locked. 2b01: OCV0 locked first OCV1 locked second. 2b10: OCV0 locked first OCV1 locked second 2b11: Invalid When both of them are locked, the Qmax is locked. Qmax updating status 0: not in updating process. 1: in updating process. When write following register, software should check this register to know whether it has been sync. to clk32KHz domain. FGU_CONFIG, ADC_CONFIG, FGU_INT_EN, FGU_HIGH_OVER, FGU_LOW_OVER, FGU_CLBCNT_SETH, FGU_CLBCNT_SETL bit type is changed from r/w to rw. When the CLBCNT is lower than wet clbcnt low threshold , then interrupt bit type is changed from r/w to rw. When the OCV is lower than set ocv low threshold, then interrupt bit type is changed from r/w to rw. When Current data is ready, an interrupt is generated. It is used when calibration. bit type is changed from r/w to rw. When Voltage data is ready, an interrupt is generated. bit type is changed from r/w to rw. Qmax update timeout interrupt Enable bit type is changed from r/w to rw. Qmax update done interrupt Enable bit type is changed from r/w to rw. Relax Counter interrupt Enable. When the relax counter reached its set threshold, an interrupt is generated. bit type is changed from r/w to rw. Coulomb counter threshold interrupt Enable When the Coulomb counter reached the multiply of the threshold, then an interrupt is generated. E.g. If set CLBCNT_DELTA = 5mAh, then when the Coulomb counter is 5mAh, 10mAh, 15mAh will generate interrupt. bit type is changed from r/w to rw. Voltage High overload interrupts Enable. When the voltage is higher than the threshold, then an interrupt is generated. bit type is changed from r/w to rw. Voltage Low overload interrupt Enable. When the voltage is lower than the threshold, then an interrupt is generated. CLBCNT lower interrupt clear OCV lower interrupt clear Current ready interrupt clear Voltage ready interrupt clear Qmax update timeout interrupt clear Qmax update done interrupt clear Relax counter interrupt clear Coulomb counter delta interrupt clear Voltage High overload interrupts clear. Voltage Low overload interrupts clear. CLBCNT lower interrupt raw status OCV lower interrupt raw status Current ready interrupt raw status Voltage ready interrupt raw status Qmax update timeout interrupt raw status Qmax update done interrupt raw status Relax counter interrupt raw status Coulomb counter delta interrupt raw status Voltage High overload interrupts raw status. Voltage Low overload interrupts raw status. CLBCNT lower interrupt status OCV lower interrupt status Current ready interrupt status Voltage ready interrupt status Qmax update timeout interrupt status Qmax update done interrupt status Relax counter interrupt status Coulomb counter delta interrupt status Voltage High overload interrupts status. Voltage Low overload interrupts status. Voltage now It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. Open Circuit Voltage. It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. Open Circuit Value read at the very beginning of 250ms Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value bit type is changed from r/w to rw. Voltage High overload threshold. It is forbidden that the battery voltage is higher than the voltage max threshold. If it violates that, the battery may be destroyed. Once it reaches this value, an interrupt is generated to notify the software to do something to deal with it. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Voltage low overload threshold. Once the battery voltage is lower than the set threshold, the device will not Work at any moment. To avoid the lost of data, the software should save the data and shut down the device when a lower threshold interrupt is generated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Voltage High-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshod of the locked high OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Voltage High-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked high OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Voltage Low-High threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the high threshold of the locked low OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Voltage Low-Low threshold. When update the Qmax, there should be two OCV and its relative coulomb counter value to calculate the Qmax. This register is used to set the low threshold of the locked low OCV. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid Qmax OCV record Low point The Low OCV record of Qmax updated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13] is omitted, and just 12 bit is valid Qmax OCV record High Point The High OCV record of Qmax updated. It is unsigned value, the unit is equal the A/D value, and the really voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0,then the bit [13] is omitted, and just 12 bit is valid bit type is changed from r/w to rw. Set Coulomb Counter Value register, bit[29:16] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_SET_IND = 2h0, then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point Note: the Coulomb Counter is 28 bits, and it is distributed in two register, after both of them are set, then it can be valid. When first write CLBCNT_SETH, then CLBCNT_SET_IND[1] is high to indicate it; second write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable.When first write CLBCNT_SETL, then CLBCNT_SET_IND[0] is high to indicate it; second write CLBCNT_SETH then CLBCNT_SET_IND[1] is high to indicate it, and after one clock, the CLBCNT_SET_IND[1] and CLBCNT_SET_IND[0] is auto clear to 0 to indicate both the register is write and stable. bit type is changed from r/w to rw. Set Coulomb Counter Set Value register. bit[15:0]] In Work mode 2 of Current-Integration-based algorithm. The software can initial the coulomb counter by writing the value to this register, it Once the value is write to this register (with CLBCNT_H_IND =0 & CLBCNT_L_IND = 0), then the FGU_CLBCNT_VAL will be set to the same value, and the coulomb counter will count from this value. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point bit type is changed from r/w to rw. Coulomb Counter Delta register, bit[29:16] Once the coulomb is changed multiply of the Coulomb counter threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point bit type is changed from r/w to rw. Coulomb Counter Delta register, bit[:15:0] Once the coulomb is changed multiply of the Coulomb counter delta threshold, then an interrupt is generated to notify software to deal with the resolution. It is 2s Complement Code value 30h1FFF_FFFF: represent the max positive point30h0: represent the zero point30h2000_0000: represent the min negative point Coulomb Counter Last OCV register, bit[31:16] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point 32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value point Coulomb Counter Last OCV register, bit[15:0] This register indicated the coulomb counter value changed after the OCV is locked. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Coulomb Counter Value register, bit[31:16] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: maxpositive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Coulomb Counter Value register, bit[15:0] This register is accumulate once every charge is coming, and it is can be set by CLBCNT_SET register at any moment. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Coulomb Counter Qmax Value, bit[31:16] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Coulomb Counter Qmax Value, bit[15:0] It is used to record the Qmax value when the Qmax process is used. It is read only. It is 2s Complement Code value 32h7FFF_FFFF ~ 32h2000_0000: reserved 32h1FFF_FFFF: max positive point32h0: zero point32hE000_0000: min negative point 32hDFFF_FFFF~32h8000_0000: reserved Note: There are really 30 bits valid, the upper 2 bits is used to complement for the positive or negative sign of signed value Note: after Power On, it saved the first sampled Curt data, unsigned, and just 250ms data.14bits. or said POCI. bit type is changed from r/w to rw. FGU Qmax timeout set counter. When the Qmax update exceed the timeout set counter, then the Qmax quit and it is failed to update. The unit of the counter is 4 seconds, so the max value is 72.8 hours. Note: when the QMAX_TIMEOUT_CNT is 0, it means it is never timeout. FGU Qmax timer counter. Once the Qmax is updating, the timer is counted from 0. After the Qmax is updated, the timer is stay on the last value until the next update process start. The unit of the counter is 4 seconds, so the max value is 72.8 hours. bit type is changed from r/w to rw. Relax Current threshold. It is unsigned value, It is a tiny value which will add or subtract the zero value (14h1FFF) of the CURT_VALUE, to indicate a low current threshold. And it will define the conception of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state. And then the relax counter will work to count, else it clear to 0. bit type is changed from r/w to rw. Relax counter threshold. When the counter reaches to this value, it stops at this value. The unit is 1 second. 13h1 means 1 second Relax counter value. The relax counter register is 13 bit read-only register clocked every 1s and can go up to about 2hs. The counter is auto clearer to 0 when the current is out of the relax state. Definition of Relax State: When current value of CURT_VALUE bigger than (14h1FFF-CURT_THRE) and smaller than (14h1FFF + CURT_THRE), the battery will work in Relax state. OCV Last count. After the OCV is locked, this counter will count how many times it keeps The unit is 1 second, and the max count is about 9 hours, if the count is bigger than 18hrs, than the count is keep its max value 16hFFFF. Current offset value, It is signed value, and 2s complement value. Used to adjust the calibration current value. bit type is changed from r/w to rw. For software to set this area, where the data will be kept in USER_AREA_STS0 if the RTC clock is working. bit type is changed from r/w to rw. For software to clear this area, Set 1, the data kept in USER_AREA_STS0 will be cleared. Set 0, after clearing the status, the register value will be set back to 0 The data will be kept in if RTC clock is working Open Circuit Current. Refer to the Current Value. bit type is changed from r/w to rw. The OCV low threshold. When the real OCV lower than this register, then an interrupt is occurred. bit type is changed from r/w to rw. The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred. Its higer part. bit type is changed from r/w to rw. The CLBCNT low threshold. When the real CLBCNT lower than this register, then an interrupt is occurred. bit type is changed from r/w to rw. For software to set this area, where the data will be kept in USER_AREA_STS1 if the RTC clock is working. bit type is changed from r/w to rw. For software to clear this area, Set 1, the data kept in USER_AREA_STS1 will be cleared. Set 0, after clearing the status, the register value will be set back to 0 The data will be kept in if RTC clock is working Power On Open Circuit Voltage. If is just valid when the very time of power on . It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous voltage values. Once voltage value is updated, buffer0 will save the value in voltage value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest voltage value.It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, it voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value This set of registers save previous current values. Once curt value is updated, buffer0 will save the value in curt value register. Buffer1 saves previous value in buffer0. Same manner as buffer2~7. Buffer0 is always same as lattest current value. Current now value, It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, it voltage is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value Qmax Lock Low Point current value It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value Qmax Lock High Point current value It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000:represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value Legacy Open Circuit Voltage Value for Debug It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. When VOLT_H_VALID is 0, then the bit [13] is omitted, and just 12 bit is valid It has another function, when in ADC software calibration mode; it is act as the ADC1 voltage value. bit type is changed from r/w to rw. Select which type of data being shit out to pad 0: current value 1: voltage value bit type is changed from r/w to rw. ATE test voltage time mode 3b000: 15.6ms 3b001: 31.25ms 3b010: 62.5ms 3b011: 125ms 3b100: 250ms 3b101: 500ms bit type is changed from r/w to rw. ATE test current time mode 3b000: 15.6ms 3b001: 31.25ms 3b010: 62.5ms 3b011: 125ms 3b100: 250ms 3b101: 500ms ATE test current value saved register It is unsigned value, but represents signed value. The unit is equal the A/D value, and the really current value should multiply the LSB value (refer to the Analogy Spec.) 14h3FFF: represent the max point14h2000: represent the zero point14h0: : represent the min point That means when the value is 14h2000, its current is 0 A. Data bigger than 14h2000 is positive value, and data small than 14h2000 is negative value ATE test voltage value saved register It is unsigned value, the unit is equal the A/D value, and the relative voltage value should multiply the LSB value (refer to the Analogy Spec.) 13h1FFF: represent the max point13h1000: represent the zero point <13h1000: invalid That means when the value is 13h1000, its voltage is 0 V. Because the voltage is all positive value, the value of below 13h1000 should not be valid as see it as some offset of 0v. CHIP ID low 16 bits CHIP ID high 16 bits TMR module enable 0: Disable the PCLK of timer 1: Enable the PCLK of timer PSM module enable 0: Disable the PCLK of PSM 1: Enable the PCLK of PSM BLTC module enable 0: Disable the PCLK of BLTC 1: Enable the PCLK of BLTC PINREG module enable 0: Disable the PCLK of pin registers 1: Enable the PCLK of pin registers FGU module enable 0: Disable the PCLK of FGU 1: Enable the PCLK of FGU Efuse module enable 0: Disable the PCLK of efuse ctrl 1: Enable the PCLK of efuse ctrl AUXADC module enable 0: Disable the PCLK of AUXADC 1: Enable the PCLK of AUXADC Audio module enable 0: Disable the PCLK of Audio 1: Enable the PCLK of Audio EIC module enable 0: Disable the PCLK of EIC 1: Enable the PCLK of EIC WDG module enable 0: Disable the PCLK of watchdog 1: Enable the PCLK of watchdog RTC module enable 0: Disable the PCLK of RTC 1: Enable the PCLK of RTC CAL module enable 0: Disable the PCLK of CAL 1: Enable the PCLK of CAL AUXAD clock enable, the clock is connected to AUXADC converter 0: disable AUXAD_CLK 1: enable AUXAD_CLK AUXADC module work clock enable 0: disable clk_adc 1: enable clk_adc Calibration module clock source select 2'b00: 32K-less 1MHZ clock 2'b01: DCDC_CLK2M_OUT 2'b10: DCDC_CLK3M_OUT 2'b11: N/A CLK_CAL eanble 0: disable clk_cal 1: enable clk_cal Audio 6.5M clock enable 0: disable clk_aud_6p5m_rx and clk_aud_6p5m_tx 1: enable clk_aud_6p5m_rx and clk_aud_6p5m_tx Audio IF clock enable 0: disable CLK_AUDIF 1: enable CLK_AUDIF TIMER RTC clock soft enable 0: Disable the RTC clock of timer 1: Enable RTC clock of timer FLASH controller RTC clock enable 0: Disable the RTC clock of FLASH controller 1: Enable RTC clock of FLASH controller EFS RTC clock soft enable 0: Disable the RTC clock of EFS 1: Enable RTC clock of EFS BLTC RTC clock soft enable 0: Disable the RTC clock of BLTC 1: Enable RTC clock of BLTC FGU RTC clock soft enable 0: Disable the RTC clock of FGU 1: Enable RTC clock of FGU EIC RTC clock soft enable 0: Disable the RTC clock of EIC 1: Enable RTC clock of EIC Watchdog RTC clock soft enable 0: Disable the RTC clock of Watchdog 1: Enable RTC clock of Watchdo RTC RTC clock soft enable 0: Disable the RTC clock of RTC 1: Enable RTC clock of RTC ARCH RTC clock soft enable 0: Disable the RTC clock of ARCH 1: Enable RTC clock of ARCH AUD RX soft reset AUD TX soft reset BLTC soft reset Audio IF soft reset Efuse soft reset Auxadc soft reset PSM apb soft reset FGU soft reset EIC soft reset Watchdog soft reset RTC soft reset CAL soft reset TMR soft reset LDO_DCXO power down 1: power down 0: power on EMM domain power down 1: power down 0: power on LDO of charge pump power down 1: power down 0: power on DCDC_GEN power down 1: power down 0: power on DCDC_CORE power down 1: power down 0: power on internal oscillator enable 1'b0: oscillator off 1'b1: oscillator on LDO_MEM power down 1: power down 0: power on LDO_ANA power down 1: power down 0: power on LDO_VDD28 power down 1: power down 0: power on Bandgap power down 1: power down 0: power on Power off_sequence enable register soft reset,write 1 can: 1 reset total system 2 power down and up clock output enable phase shift option 1'b0: default, w/i 1/5 phase shift at internal mode 1'b1: uni-phase mode, all ouputs = channel 0 clock selection for each channel RG_CLKOUT_SEL<0>: VCORE clk selection RG_CLKOUT_SEL<1>: VGEN clk selection RG_CLKOUT_SEL<2>: VPA clk selection 0: internal mode, default 1: external mode soft reset of all dcdc generated clk oscillator frequency tuing, (1/16)/step 4'b0000: default 3MHz 4'b0001: -1 step 4'b0111: -7 step 4'b1000: +8 step 4'b1111: +1 step current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset reference voltage trimming (base on 1.2V) 3'b000: default 3'b001: +12.5mV 3'b010: +25mV 3'b011: +37.5mV 3'b100: -50mV 3'b101: -37.5mV 3'b110: -25mV 3'b111: -12.5mV force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCCORE, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 output voltage selection, 3.125mV/step 9'b111100000: 1.5V 9'b111000000: 1.4V 9'b110100000: 1.3V 9'b110000000: 1.2V 9'b101100000: 1.1V 9'b101000000: 1.0V 9'b100100000: 0.9V 9'b100000000: 0.8V 9'b011100000: 0.7V 9'b011000000: 0.6V current limit threshold tuning 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% current sense R ratio tuning current sense multiplier tuning 2'b00: default, x1 2'b01: -20% 2'b10: +40% 2'b11: +20% PFM mode threshold for upper limit 2'b00: default, 0.6V 2'b01: 0.55V 2'b10: 0.65V 2'b11: 0.7V compensation R select 2'b00: default, 360k 2'b01: 320k 2'b10: 400k 2'b11: 440k slope compensation tuning 2'b00: default 2'b01: 0.5x 2'b10: 1.5x 2'b11: 2x high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off reserved force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCGEN, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 output voltage selection, 12.5mV/step. 8'b00000000= 1.3V 8'b00001000= 1.4V 8'b00010000= 1.5V 8'b00011000= 1.6V 8'b00100000= 1.7V 8'b00101000= 1.8V 8'b00110000= 1.9V 8'b00111000= 2.0V 8'b01000000= 2.1V 8'b01001000= 2.2V 8'b01010000= 2.3V 8'b01011000= 2.4V 8'b01100000= 2.5V 8'b01101000= 2.6V 8'b01110000= 2.7V 8'b01111000= 2.8V current limit threshold tuning 2'b00: default 2'b01: -0.5pF 2'b10: +1pF 2'b11: +0.5pF current sense multiplier tuning 2'b00: default, x1 2'b01: x0.5 2'b10: x2 2'b11: x1.5 compensation C3 2'b00: default 2'b01: -20% 2'b10: +40% 2'b11: +20% PFM mode threshold for upper limit 2'b00: default 2'b01: -50mV 2'b10: +50mV 2'b11: +100mV compensation R2 select 2'b00: default, 960k 2'b01: 880k 2'b10: 1040k 2'b11: 1120k compensation R3 select 2'b00: default, 5k 2'b01: 2.5k 2'b10: 10k 2'b11: 7.5k sawtooth tuning manully 2'b00: default 2'b01: +15% 2'b10: -30% 2'b11: -15% high side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x low side slew rate control 2'b00: default 2'b01: 0.75x 2'b10: 0.5x 2'b11: 0.25x zero-cross offset tuning 2'b00: default 2'b01: +5mV offset 2'b10: -5mV offset 2'b11: -10mV offset anti-ring enable 1'b0: default, anti-ring off 1'b1: anti-ring on APC mode enable 1'b0: default, RG control mode 1'b1: APC mode APC ramp selection 1'b0: default, 2.0x ramp 1'b1: 2.5x ramp bypass mode disable 1'b0: default, auto bypass 1'b1: bypass off bypass force on 1'b0: default, auto bypass 1'b1: force bypass mode on bypass mode threshold 2'b00: default, ~200mV DVS control 1'b0: default, off 1'b0: on, for DCM down discharge 100% duty selection 1'b0: default, max duty=100% 1'b1: max duty ~95% clock gating enable the phase difference, 26M per step the division factor from 26M for DCDCWPA, in default the clock is from RC in analog 6'h0: no divide 6'h1: divide by 26'h3F: divide by 64 force zero-cross off 1'b0: default, zero_cross detect on 1'b1: zero-cross detect off sawtooth calibration 1'b0: default, auto calibration before power-on 1'b1: calibration manully DCDC power down 1'b0: DCDC on 1'b1: DCDC power down output voltage selection, 25mV/step. 7'b1111100= 3.5V 7'b1110000= 3.2V 7'b1100000= 2.8V 7'b1010000= 2.4V 7'b1000000= 2.0V 7'b0110000= 1.6V 7'b0100000= 1.2V 7'b0010000= 0.8V 7'b0000000= 0.4V force PWM mode 1'b0: default, PFM/PWM auto mode 1'b1: force PWM mode DCDC to AUXADC trim channel selection 3'b001: select VCORE 3'b010: select VGEN (VGEN*18/37) 3'b011: select VPA (VPA*18/68) RG_DCDC_AUXTRIM_SEL<2>, internal test mode select: 0: default, internal test mode disable 1: internal test mode enable. Monitor internal signals by reuse CLK3M_OUT path 3'b100: enpwm_vgen 3'b101: zx_vgen 3'b110: enpwm_vcore 3'b111: zx_vcore LDO short protection power down ANA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 ANA LDO bypass application: default 1'b0, no bypass default 1'b1, bypass ANA LDO stability compensation: default 2'b00 ANA LDO foldback current threshold adjust: default 1'b0 ANA LDO current limit threshold adjust: default 1'b0 ANA LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.8V, 6'b100000 RF15 LDO short protection RF15 LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 RF15 LDO bypass application: default 1'b0, no bypass default 1'b1, bypass RF15 LDO stability compensation: default 2'b00 RF15 LDO foldback current threshold adjust: default 1'b0 RF15 LDO current limit threshold adjust: default 1'b0 LDO_RF15 power down 1: power down 0: power on RF15 LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.5V, 6'b1000 CAMD LDO short protection CAMD LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 CAMD LDO bypass application: default 1'b0, no bypass default 1'b1, bypass CAMD LDO stability compensation: default 2'b00 CAMD LDO foldback current threshold adjust: default 1'b0 CAMD LDO current limit threshold adjust: default 1'b0 LDO_CAMD power down 1: power down 0: power on CAMD LDO program bits:12.5mV/step, 1.4V~2.1875V; default 1.8V, 6'b100000 CON LDO short protection CON LDO bypass application: default 1'b0, no bypass default 1'b1, bypass CON LDO stability compensation: default 2'b00 CON LDO foldback current threshold adjust: default 1'b0 CON LDO current limit threshold adjust: default 1'b0 LDO_CON power down 1: power down 0: power on CON LDO program bits: 12.5mV/step, 1.1V~1.8875V; default 1.5V, 6'b100000 MEM LDO short protection MEM LDO remote cap application:default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 MEM LDO bypass application: default 1'b0, no bypass default 1'b1, bypass MEM LDO stability compensation: default 2'b00 MEM LDO foldback current threshold adjust: default 1'b0 MEM LDO current limit threshold adjust: default 1'b0 MEM LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 6'h100000, 1.8V SIM0 LDO short protection SIM0 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 SIM0 LDO stability compensation: default 2'b10 SIM0 LDO foldback current threshold adjust: default 1'b1 SIM0 LDO current limit threshold adjust: default 1'b1 LDO_SIM0 power down 1: power down 0: power on SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 SIM1 LDO short protection SIM1 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 SIM1 LDO stability compensation: default 2'b10 SIM1 LDO foldback current threshold adjust: default 1'b1 SIM1 LDO current limit threshold adjust: default 1'b1 LDO_SIM1 power down 1: power down 0: power on SIM0 LDO program bits:12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 CAMA LDO short protection CAMA LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 CAMA LDO stability compensation: default 2'b10 CAMA LDO foldback current threshold adjust: default 1'b1 CAMA LDO current limit threshold adjust: default 1'b1 LDO_CAMA power down 1: power down 0: power on CAMA LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111 LCD LDO short protection LCD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 LCD LDO stability compensation: default 2'b10 LCD LDO foldback current threshold adjust: default 1'b1 LCD LDO current limit threshold adjust: default 1'b1 LDO_LCD power down 1: power down 0: power on LCD LDO program bits: 12.5mV/step, 1.6125V~3.2V; default 1.8V, 7'b0001111 MMC LDO short protection MMC LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 MMC LDO stability compensation: default 2'b10 MMC LDO foldback current threshold adjust: default 1'b1 MMC LDO current limit threshold adjust: default 1'b1 LDO_MMC power down 1: power down 0: power on MMC LDO program bits: 12.5mV/step, 2V~3.5875V; default 3.0V, 7'b1010000 SD LDO short protection SD LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 SD LDO stability compensation: default 2'b10 SD LDO foldback current threshold adjust: default 1'b1 SD LDO current limit threshold adjust: default 1'b1 LDO_SD power down 1: power down 0: power on SD LDO program bits: 12.5mV/step, 1.4V~2.1875V; default 1.8V, 7'b100000 DDR12 LDO short protection DDR12 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 DDR12 LDO stability compensation: default 2'b10 DDR12 LDO foldback current threshold adjust: default 1'b1 DDR12 LDO current limit threshold adjust: default 1'b1 LDO_DDR12 power down 1: power down 0: power on DDR12 LDO program bits: 12.5mV/step, 0.8V~1.5875V ; default 1.25V, 7'b100100 VDD28 LDO short protection VDD28 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 VDD28 LDO stability compensation: default 2'b10 VDD28 LDO foldback current threshold adjust: default 1'b1 VDD28 LDO current limit threshold adjust: default 1'b1 VDD28 LDO program bits: 12.5mV/step, 1.6125V~3.2V ; default 2.8V, 7'b1011111 SPIMEM LDO short protection SPIMEM LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 SPIMEM LDO stability compensation: default 2'b10 SPIMEM LDO foldback current threshold adjust: default 1'b1 SPIMEM LDO current limit threshold adjust: default 1'b1 LDO_SPIMEM power down 1: power down 0: power on SPIMEM LDO program bits:12.5mV/step, 1.75V~3.3375V; default is select by V_SPIMEM pad, when V_SPIMEM ==0, spimem voltage is 1.8V, register default is 7'b100 when V_SPIMEM ==1, spimem voltage is 3.3V, register default is 7b1111100 LDO DCXO trim bits: 5mV/step, 0.72V~0.875V; default 1.2V, 5'b10000 DCXO LDO short protection DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 DCXO LDO stability compensation: default 2'b10 DCXO LDO foldback current threshold adjust: default 1'b1 DCXO LDO current limit threshold adjust: default 1'b1 DCXO LDO program bits: 12.5mV/step, 1.5V~3.0875V ; default 1.8V, 7'b0011000 USB33 LDO short protection USB33 LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 USB33 LDO stability compensation: default 2'b10 USB33 LDO foldback current threshold adjust: default 1'b1 USB33 LDO current limit threshold adjust: default 1'b1 LDO_USB33 power down 1: power down 0: power on USB33 LDO program bits: 12.5mV/step, 2.1V~3.6875V; default 3.3V, 7'b1100000 LDO trim bits: 5mV/step, 0.72V~0.875V; default 0.8V, 5'b10000 LDO trim bits: 5mV/step, 0.72V~0.875V; default 0.8V, 5'b10000 LDO VDDRTC output calibretion bit cover +/-10% step 0.625% acc +/- 0.3125% LDO RTC output program bits, 00:1.8, 01:1.8, 10:1.85(default),11:1.9 Backup battery output program bits;00:2.6, 01:2.8, 10:3.0(default),11:3.2 VBAT2 LDO TRIM CONTROL BITS: 000: cal disable (default) 001: LDO VDDSIM0 cal enable; 010: LDO VDDSIM1 cal enable; 011: LDO VDDDCXOcal enable; 100: LDO VDDUSB cal enable; 101: LDO VDDCAMA cal enable; 110: LDO VDDVIB cal enable; VBAT1 LDO TRIM CONTROL BITS: 000: cal disable (default) 001: LDO VDDMMC cal enable; 010: LDO VDD28 cal enable; 011: LDO VDDSPIMEM cal enable; 100: LDO VDDLCD cal enable; 101: LDO VDDPLLED cal enable; DCDC supplied LDO TRIM CONTROL BITS: 000: cal disable (default) 001: LDO VDDCAMD cal enable; 010: LDO VDDCON cal enable; 011: LDO VDDANA cal enable; 100: LDO VDDVIO18 cal enable; 101: LDO VDDDDR12 cal enable; 110: LDO VDDMEM cal enable; 111: LDO VDDRF15 cal enable; LDO and DCDC can be controlled by external device if this bit is set IO PAD sleep enable in deep sleep mode ALL LDO and DCDC power down enable in deep sleep mode DCDC CORE power down reset valid threshold @32K clock DCDC CORE power down reset release threshold @32K clock DCDC CORE power down enable in deep sleep mode DCDC CORE power drop enable in deep sleep mode DCDC WPA power down enable in deep sleep mode VIO1V8 power down enable in deep sleep mode LDO RFA power down enable in deep sleep mode LDO MMC power down enable in deep sleep mode LDO DCXO power down enable in deep sleep mode LDO SPIMEM power down enable in deep sleep mode LDO VDD28 power down enable in deep sleep mode LDO VIO18 power down enable in deep sleep mode LDO DDR12 power down enable in deep sleep mode LDO USB33 power down enable in deep sleep mode LDO LCD power down enable in deep sleep mode LDO CAMIO power down enable in deep sleep mode LDO CAMD power down enable in deep sleep mode LDO CAMA power down enable in deep sleep mode LDO SIM1 power down enable in deep sleep mode LDO CP power down enable in deep sleep mode LDO CON power down enable in deep sleep mode LDO SIM0 power down enable in deep sleep mode LDO ANA power down enable in deep sleep mode LDO MEM power down enable in deep sleep mode DCDC CORE low power mode enable in deep sleep mode DCDC GEN low power mode enable in deep sleep mode DCDC WPA low power mode enable in deep sleep mode LDO RFA low power mode enable in deep sleep mode LDO MMC low power mode enable in deep sleep mode LDO DCXO low power mode enable in deep sleep mode LDO SPIMEM low power mode enable in deep sleep mode LDO VDD28 low power mode enable in deep sleep mode LDO VIO18 low power mode enable in deep sleep mode 0: Disable 1: Enable LDO DDR12 low power mode enable in deep sleep mode 0: Disable 1: Enable LDO USB low power mode enable in deep sleep mode 0: Disable 1: Enable LDO LCD low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CAMIO low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CAMD low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CAMA low power mode enable in deep sleep mode 0: Disable 1: Enable LDO SIM1 low power mode enable in deep sleep mode 0: Disable 1: Enable LDO CON low power mode enable in deep sleep mode 0: Disable 1: Enable LDO SIM0 low power mode enable in deep sleep mode 0: Disable 1: Enable LDO ANA low power mode enable in deep sleep mode LDO MEM low power mode enable in deep sleep mode 0: Disable 1: Enable delay between two steps 00:1*32k clock 01:2*32k clock 10:3*32k clock 11:4*32k clock step number voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv DCDCCORE step tune enable in deep sleep 0: disable 1: enable DCDC CORE control bits in deep sleep mode DCDC CORE can be controlled by EXT_XTL0_EN(from PAD) if this bit is set DCDC CORE can be controlled by EXT_XTL1_EN(from PAD) if this bit is set DCDC CORE can be controlled by EXT_XTL2_EN(from PAD) if this bit is set DCDC CORE can be controlled by EXT_XTL3_EN(from PAD) if this bit is set DCDC GEN can be controlled by EXT_XTL0_EN(from PAD) if this bit is set DCDC GEN can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set DCDC GEN can be controlled by EXT_XTL2_EN(from PAD) if this bit is set DCDC GEN can be controlled by EXT_XTL3_EN(from PAD) if this bit is set DCDC WPA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set DCDC WPA can be controlled by EXT_XTL1_EN1(from PAD) if this bit is set DCDC WPA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set DCDC WPA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO DCXO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO DCXO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO DCXO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO DCXO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO VDD28 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO VDD28 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO VDD28 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO VDD28 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO RFA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO RFA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO RFA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO RFA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO SIM0 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO SIM0 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO SIM0 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO SIM0 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO SIM1 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO SIM1 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO SIM1 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO SIM1 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO MEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO MEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO MEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO MEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO LCD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO LCD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO LCD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO LCD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO CAMIO can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO CAMIO can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO CAMIO can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO CAMIO can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO CAMA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO CAMA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO CAMA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO CAMA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO CAMD can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO CAMD can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO CAMD can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO CAMD can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO DDR12 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO DDR12 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO DDR12 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO DDR12 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO VIO18 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO VIO18 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO VIO18 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO VIO18 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO MMC can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO MMC can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO MMC can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO MMC can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO USB33 can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO USB33 can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO USB33 can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO USB33 can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO KPLED can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO KPLED can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO KPLED can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO KPLED can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO VIBR can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO VIBR can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO VIBR can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO VIBR can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO CON can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO CON can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO CON can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO ANA can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO ANA can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO ANA can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO ANA can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO CP can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO CON can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO CP can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO CP can be controlled by EXT_XTL3_EN(from PAD) if this bit is set LDO SPIMEM can be controlled by EXT_XTL0_EN(from PAD) if this bit is set LDO SPIMEM can be controlled by EXT_XTL1_EN(from PAD) if this bit is set LDO SPIMEM can be controlled by EXT_XTL2_EN(from PAD) if this bit is set LDO SPIMEM can be controlled by EXT_XTL3_EN(from PAD) if this bit is set Band-gap chopping enable: "0":chopping disable (default) "1": chopping enable DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended DCDC Voltage calibration disable 0: enable calibration 1: disable calibration DCDC Voltage calibration disable 0: enable calibration 1: disable calibration DCDC reference Bits selection 0: From efuse 1: From Software Register change is not recommended DCDC sleep voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1 DCDC normal voltage turnning 0: From efuse,cannot voltage turnning 1: From Software Register,can be turnned if software want to control this voltage, must set this bit to 1 LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended LDO Voltage calibration disable 0: enable calibration 1: disable calibration change is not recommended RC_MODE write ack flag bit type is changed from wc to rc. RC_MODE write ack flag clear, high effective Low power LDO_DCXO power down set in RTC Low power LDO_DCXO power down clear in RTC 0: there isnt 32k crystal in PMIC 32K clock select in 32K crystal removal option 0: From XO 1: From RC RC 32K oscillator enable RC 32K mode in battery drop case: 26M wake up enable by ext_xtl3_en 26M wake up enable by ext_xtl2_en 26M wake up enable by ext_xtl1_en 26M wake up enable by ext_xtl0_en 26MHz crystal oscillator power down enable in deep sleep mode 26MHz crystal oscillator output enable 26MHz crystal oscillator wait cycles RGB driver power down enable in chip deep sleep mode RGB driver hardware power down enable RGB driver soft power down current mode enable "0" disable (default) "1" enable (default) set current level in current mode 000:1.25uA;001:2.5uA;010:5uA;011:10uA;100:20uA;101:40uA;110:80uA;111:160uA; 8step Internal resistor for sink current calibration bit. Internal resistor for sink current calibration bit selection 0: From Software Register 1: From Ememory External resisitor for sink current adjustment for test Flash power on 1: power on 0: power down FLASH_V hardware control enable FLASH_V hardware control step 00: 1 cycle of clock 32k 01: 2 cycle of clock 32k 10: 3 cycle of clock 32k 11: 4 cycle of clock 32k Current control bit. 16 steps. Min current: 15mA ("0000") One step is 15mA (default 4'b0) Current control bit. 16 steps (default 4'b0) (0000:0.9mA 0001:1.8mA 0010:2.7mA 0011:3.6mA 0100:4.5mA 0101:5.4mA 0110:6.3mA 0111:7.2mA 1000:16.2mA 1001:22.5mA 1010:29.7mA 1011:37.8mA 1100:46.8mA 1101:56.7mA 1110:67.5mA 1111:79.2mA) Key PAD LED driver power down "1" power down (default) "0" enable Keypad LED pull down enable signale, high effective KPLED LDO sleep power down enable KPLED LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 KPLED LDO stability compensation: default 2'b10 KPLED LDO foldback current threshold adjust: default 1'b1 VIBR LDO current limit threshold adjust: default 1'b1 KPLED LDO power down signal KPLED LDO program bits: 100mV/step, 2.8V~3.5V; default 3.3V, 3'b101 KPLED LDO TRIM program bits: 8mV/step 1.2V default LDO short protection power down VIBR LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 KPLED LDO stability compensation: default 2'b10 VIBR LDO foldback current threshold adjust: default 1'b1 VIBR LDO current limit threshold adjust: default 1'b1 LDO short protection power down Vibrator LDO sleep power down enable VIBR LDO power down signal VIBR LDO program bits: 100mV/step, 2.8V~3.5V; default 3.0V, 3'b010 VIBR LDO TRIM program bits: 8mV/step 1.2V default LDO EA load compensation EN ,effective(1'b1) Whether Adie use inverse of clk_audif to sample Ddie tx data 0: No 1: Yes Whether Adie use inverse of clk_aud6m5 to send rx data to Ddie 0: No 1: Yes Whether Adie audio controller use inverse of clk_aud6m5 in tx path 0: No 1: Yes Whether Adie audio controller use inverse of clk_aud6m5 in rx path 0: No 1: Yes VCHG tracking voltage level for automatic input control loop(AICL) 00: 3.8V 01: 3.95V 10: 4.3V 11: 4.5V Default value is 11 Charger CC mode enable, high effective Charger battery sense DAC (CC-CV trans-point control) Charger battery charging end voltage 00: Vend=4.2V 01: Vend=4.3V 10: Vend=4.4V 11: Vend=4.5V Termination charger current programmable bits 00:cc*0.9 01:cc*0.4 10:cc*0.2 11:cc*0.1 Charger power down Choice of charger external power device 0:PNP+NMOS 1:PMOS+DIODE Default value is 0 CC mode charging current 0000:300mA 0001 : 350 0010: 400mA 0011 : 450 0100: 500mA 0101 :550 0110: 600mA 0111: 650 1000: 700mA 1001: 750 1010: 800mA 1011: 900 1100: 1000mA 1101: 1100 1110: 1200mA 1111: 1300 Default4'b0 control bits of over voltage protection for VCHG. When VCHG is above some level set by these 2 bits, charger power down and CHGR_OVI becomes high. 00: 6.0V 01: 6.5V 10: 7.0V 11: 9.7V Default 2'b01 Chgr_int enable after CHG_DET_DONE Charging port of NON-DCP status "1" Charging port is NON-DCP "0" Charging port is not NON-DCP Charging detect done after charger insert once The output of the comparator of DCD detection or SDP/NON-DCP detection "1" means DCD pass when doing DCD, or SDP if CHG_DET=0 "0" means DCD fail when doing DCD, or NON-DCP if CHG_DET=0 The output of the comparator of DCP_DET loop "1" means DCP if CHG_DET is "1" "0" means CDP if CHG_DET is "1" The output of the comparator of CHG_DET loop "1" DCP or CDP "0" SDP or NON-DCP Charging port of SDP status "1" Charging port is SDP "0" Charging port is not SDP Charging port of DCP status "1" Charging port is DCP "0" Charging port is not DCP Charging port of CDP status "1" Charging port is CDP "0" Charging port is not CDP Flag when charging current below some level(0.5*full current) in CV mode High effective Charger voltage ready indicator, high effective When VCHG<4.1V: "0" When VCHG>4.3V: "1" Charger present indicator, high effective When VCHG<3.1V: "0" When VCHG>3.3V: "1" 0: switch DPDM to USB phy when DCP 1: keep to connect charger detector when DCP VCHG over voltage(programmable) flag When VCHG higher than some voltage set by VCHG_OVP_V<5:0> and lasts 2mS, CHGR_OVI="1" The hysteresis voltage is 600mV. FGU ANA soft reset LDO FGU power down control 0: Normal Mode 1: Power Down Mode charger int delay time: 000:0ms 001:64ms 010:264ms.. 111:764ms ADC chop enable ADC clock programming bits input RC for ADC0 input filtering select signal: 0: ADC0 input with RC filtering 1: ADC0 input without RC filtering 0: ADC0 input with RC filtering 1: ADC0 input without RC filtering SD ADC_A will be dc offset calibration Code mode 0(default) off 1 on DP DM to auxADC select signal: "0": switch off, no DP/DM to auxADC "1": switch on, DP/DM to auxADC The DP DM path switch enable "1" switch on, BC1P2 disable "0" invalid Battery crash voltage setting: 00: 2.1V (default) 01: 2.2V 10: 2.3V 11: 2.5V Over voltage locked-out enable (high effective) Default "1" Over voltage locked-out detecting time 00 : 5.0V (default) 01 : 5.2V 10 : 4.8V 11 : 4.2V Over voltage locked-out detecting time 00 : 1ms (default) 01 : 0.5ms 10 : 0.25ms 11 : 2ms Schmitt Trigger 0: no Schmitt trigger 1: Schmitt trigger(default) Control bit of de-glitch time for battery remove "00" 32us "01" 64us "10" 128us "11" no de-glitch default"00" when VPP tie to 5V should shet VPP_5V_SEL=1 Battery presence flag to SW and POCV, so need RTC domain "0" no battery "1" battery presence VBAT detect. Active "0" is reset, no need 32K osc. ALL GPI source debug GPI debug enable ALL_INT debug, if 1, interrupt will be sent Interupt debug enable When POR reset active, this register is reset to 0 When WDG reset active, this register is reset to 0 When POR_EXT_RST active, this register is reset to 0 Setting this bit could disable the 1S debouncing time of power key after boot. bit type is changed from wc to rc. register reset flag clear Power on source flag: [0]: Debounced PBINT signal, set when PBINT=0 >50ms, clear when PBINT=1>50ms. [1]: PBINT initiating power-up hardware flag, set when PBINT=0>1s, clear after power down. [2]: Debounced PBINT2 signal, set when PBINT2=0 >50ms, clear when PBINT2=1>50ms. [3]: PBINT2 initiating power-up hardware flag, set when PBINT2=0>1s, clear after power down. [4]: Debounced CHGR_INT signal, set when VCHG=1 >50ms, clear when VCHG=0>50ms. [5]: Charger plug-in initiating power-up hardware flag, set when VCHG=1>1s, clear after power down. [6]: RTC alarm initiating power-up hardware flag [7]: Long pressing power key reboot hardware flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear after power down. [8]: PBINT initiating power-up software flag, set when PBINT=0>1s, clear by pbint_flag_clr. [9]: PBINT2 initiating power-up software flag, set when PBINT2=0>1s, clear by pbint2_flag_clr. [10]: Charger plug-in initiating power-up software flag, set when VCHG=1>1s, clear by chgr_int_flag_clr. [11: External pin reset reboot software flag, set when EXTRSTN=0>30ms, clear by ext_rstn_flag_clr. [12]: Long pressing power key reboot software flag, set when PBINT=0>PBINT_7S_THRESHOLD, clear by pbint_7s_flag. [13]: flag when register reset happened uvlo + ovlo chip power down flag bit type is changed from wc to rc. uvlo + ovlo chip power down flag clear uvlo chip power down flag bit type is changed from wc to rc. uvlo chip power down flag clear 7s hard chip power down flag bit type is changed from wc to rc. 7s hard chip power down flag clear OTP chip power down flag bit type is changed from wc to rc. OTP chip power down flag clear HW chip power down flag bit type is changed from wc to rc. HW chip power down flag clear OTP chip power down flag bit type is changed from wc to rc. OTP chip power down flag clear Write 1'b1 to this bit will clear pbint_7s_flag. Write 1'b1 to this bit will clear ext_rstn_flag. Write 1'b1 to this bit will clear chgr_int_flag. Write 1'b1 to this bit will clear pbint2_flag. Write 1'b1 to this bit will clear pbint_flag. 1: One-key Reset Mode; 0: long reset; The power key long pressing time threshold: 0~1: 2S 2: 3S 3: 4S 4: 5S 5: 6S 6: 7S 7: 8S 8: 9S 9: 10S 10:11S 11:12S 12: 13S 13:14S 14:15S 15:16S EXT_RSTN PIN function mode when 1key 7S reset 0: EXT_INT 1: RESET RTC register PBINT_7S_AUTO_ON_EN 0: enable 7s reset function; 1: disable 7s reset function; 0: software reset; 1: hardware reset; RTC status register, set by HWRST_RTC_SET. Software set this register to test VBAT and RTC power status. PCLK_arch enable Arch_en write protect bit status. When mcu_wr_prot_value==16'h3c4d, the bit is "1",else "0" Arch_en write protect value All power which default on write protect bit status. When mcu_wr_prot_value==16'h6e7f, the bit is "1",else "0" Arch_en write protect value SMPL mode: [15:13]: SMPL timer threshold 0: 0.25s 1: 0.5s 2: 0.75s.. 7: 2s [12:0]: SMPL enable 13'h1935: enable Others: disable Set once SMPL timer not expired. Set once SMPL mode write finish bit type is changed from wc to rc. Clear SMPL_PWR_ON_FLAG bit type is changed from wc to rc. Clear SMPL_MODE_WR_ACK Set once SMPL timer not expired, SMPL enable indication RTC register flag RTC register flag RTC register flag, reset by RTC_RST, default is 16'hA596 rtc time over thresthold value set reset rtc cnt time,default 16s VBAT Drop Time Count Software reset certain power enable when ext_rstn valid Software reset certain power enable when pb_7s_rst valid Software reset certain power enable when reg_rst valid Software reset certain power enable when wdg_rst valid register reset enable: reset LDO to normal mode threshold time Software reset DCDC_GEN_PD enable when global reset valid Software reset DCDC_CORE_PD enable when global reset valid Software reset LDO_MEM_PD enable when global reset valid Software reset LDO_DCXO_PD enable when global reset valid Software reset LDO_VDD28_PD enable when global reset valid Software reset LDO_ANA_PD enable when global reset valid Software reset LDO_RF18_PD enable when global reset valid Software reset LDO_USB33_PD enable when global reset valid Software reset LDO_MMC_PD enable when global reset valid Software reset LDO_DDR12_PD enable when global reset valid Software reset LDO_VIO18_PD enable when global reset valid OTP threshold option, 00 135, 01 140, 10 145, 11 150; OTP function enable control bit low 16 bit value of free timer high 16 bit value of free timer clock source for CORE DVFS 0: clock 26M 1: clock 32K delay between two steps 00:1*32k clock or 2us in 26M 01:2*32k clock or 4us in 26M 10:3*32k clock or 8us in 26M 11:4*32k clock or 16us in 26M step number DVFS voltage per step 00000:0mv 00001:1*3.125mv 00010:2*3.125mv.. 11111:31*3.125mv bit type is changed from wc to rc. voltage tune start bit voltage tune flag 0:done 1:on going voltage tune enable 0: disable 1: enable This interrupt is masked from TYPEC_INT_RAW_STATUS by TYPEC_INT_EN This interrupt is masked from CAL_INT_RAW_STATUS by CAL_INT_EN This interrupt is masked from TMR_INT_RAW_STATUS by TMR_INT_EN This interrupt is masked from AUD_PROTECT_INT_RAW_STATUS by AUD_PROTECT_INT_EN This interrupt is masked from EIC_INT_RAW_STATUS by EIC_INT_EN This interrupt is masked from FGU_INT_RAW_STATUS by FGU_INT_EN This interrupt is masked from WDG_INT_RAW_STATUS by WDG_INT_EN This interrupt is masked from RTC_INT_RAW_STATUS by RTC_INT_EN This interrupt is masked from ADC_INT_RAW_STATUS by ADC_INT_EN typeC raw interrupt flag calibration raw interrupt flag timer raw interrupt flag Audio protect raw interrupt flag EIC raw interrupt flag FGU raw interrupt flag WDG raw interrupt flag RTC raw interrupt flag auxADC raw interrupt flag bit type is changed from r/w to rw. Enable TYPEC_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable CAL_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable TMR_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable AUD_PROTECT_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable EIC_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable FGU_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable WDG_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable RTC_INT_RAW_STATUS to system bit type is changed from r/w to rw. Enable ADC_INT_RAW_STATUS to system Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: default normal function selection 2b01: GPO 0 function selection 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: default normal function selection 2b01: GPO 1 function selection 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: default normal function selection 2b01: GPO 2 function selection 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: default normal function selection 2b01: GPO 3 function selection 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: default normal functon sel 2b01: VAD ADCL data function sel 2b10: VAD ADCR data function sel 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode Driver Strength select(VDDIO=1.8V, tt corner) 00: 0.8mA 01: 1.6mA 10: 3.2mA 11: 6.4mA Weakly pull up for function mode Weakly pull down for function mode Function select: 2b00: Mode0 2b01: Mode1 2b10: Mode2 2b11: Mode3 Weak pull up for chip deep sleep mode Weak pull down for chip deep sleep mode Input enable for chip deep sleep mode Output enable for chip deep sleep mode if write 0x454e to enable write psm reg, readback only [15] is high psm calibration pre time. The time is from pull DCXO high to OSC 26M stable. unit is (clk_cal_64k_div_th +1)ms psm calibration time 1s/(2^(16-rc_32k_cal_cnt_n))/( rc_32k_cal_cnt_p+1) psm 26m calibration value update down threshold. Value = (1/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) psm 26m calibration value update up threshold Value = (3/2)*26*10^6/(2^(16-rc_32k_cal_cnt_n)) /(2^9) 1'b1: rtc use psm cal 32K clock in 32K less mode,1'b0:rtc use RC 32K clock in 32K less mode enable psm cal clear psm int status enble psm timer cnt posedge to update psm cnt value software reset psm module, auto clear enable psm timer to wake up sys enable psm alarm function enable charger to power on sys enable pbint2 to power on sys enable pbint1 to power on sys enable ext int to power on sys enable rtc power on time out detect enable psm fsm The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms The time to disable rtc clk in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to hold rtc ISO in power off rtc state, (clk_cal_64k_div_th +1)ms The time to reset rtc in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to power off rtc done in power off rtc state, unit is (clk_cal_64k_div_th +1)ms The time to release reset in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to power on rtc , unit is 4*(clk_cal_64k_div_th +1)ms The time to clock enable in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to release hold ISO in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to mark power on timeout in power on rtc state, unit is 4*(clk_cal_64k_div_th +1)ms The time to power on rtc done , unit is 4*(clk_cal_64k_div_th +1)ms The low 16 bits threshold of psm time , unit is 10*(clk_cal_64k_div_th +1)ms The high 16 bits threshold of psm time , unit is 10ms The low 16 bits threshold of psm alarm time , unit is 10*(clk_cal_64k_div_th +1)ms The high 16 bits threshold of psm alarm time The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms The threshold of psm calibration interval , unit is (clk_cal_64k_div_th +1)ms DCXO LDO short protection DCXO LDO remote cap application: default 1'b0; when parasitic resistance is larger than 200m ohm, select 1'b1 DCXO LDO stability compensation: default 2'b10 DCXO LDO foldback current threshold adjust: default 1'b1 DCXO LDO current limit threshold adjust: default 1'b1 DCXO voltage setting, 1.5~3.0875V,12.5mv step Psm calibration divider,it is calculated with rc_32k_cal_cnt_n C log2(clk_cal_64k_div_th+1) Psm rc 64K divider, the input RC clock is divider to CLK_64K/( clk_cal_64k_div_th+1) Enable watchdog power on chip by internal RC clock Psm cnt updated low 16 bits value, the step of read this value is : (1)enable psm_cnt_update, (2)wait till psm_cnt_update_vld ==1.(psm_fsm_status[6]) Psm cnt updated high 16 bits value psm cnt updated valid when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when psm_cnt_en==1, then if psm cnt get psm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when psm_cnt_alarm_en==1, then if alarm cnt get psm_alarm_cnt_th, this bit is high, When psm_status_clr is high, this bit is low when pbint2_pwr_en==1, then if pbint2 is low, this bit is high, When psm_status_clr is high, this bit is low when pbint1_pwr_en==1, then if pbint1 is low, this bit is high, When psm_status_clr is high, this bit is low when ext_int_en==1, then if ext_int is high, this bit is high, When psm_status_clr is high, this bit is low Only debug use We can use this value to calculate the RC 64K clock real frequency. Rc_64k=( clk_cal_64k_div_th+1)*(2^ rc_32k_cal_cnt_p)*26*10^6/ (psm_cal_cnt*2^9) RTC second counter value RTC minute counter value RTC hour counter value RTC day counter value bit type is changed from r/w to rw. RTC second counter update Write new counter value to this register to start a second counter updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC minute counter update Write new counter value to this register to start a minute counter updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC hour counter update Write new counter value to this register to start an hour counter updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC day counter update Write new counter value to this register to start a day counter updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC second alarm update Write new counter value to this register to start a second alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC minute alarm update Write new counter value to this register to start a minute alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC hour alarm update Write new counter value to this register to start an hour alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC day alarm update Write new counter value to this register to start a day alarm updating operation in VDDRTC domain. Reading this register can get recent updating value. Day alarm updating complete interrupt enable Hour alarm updating complete interrupt enable Minute alarm updating complete interrupt enable Second alarm updating complete interrupt enable Day counter updating complete interrupt enable Hour counter updating complete interrupt enable Minute counter updating complete interrupt enable Second counter updating complete interrupt enable Spare register updating complete interrupt enable auxiliary alarm interrupt enable Hour format select alarm interrupt enable day interrupt enable hour interrupt enable minute interrupt enable Second interrupt enable Day alarm updating complete interrupt raw status Hour alarm updating complete interrupt raw status Minute alarm updating complete interrupt raw status Second alarm updating complete interrupt raw status Day counter updating complete interrupt raw status Hour counter updating complete interrupt raw status Minute counter updating complete interrupt raw status Second counter updating complete interrupt raw status Spare register updating complete interrupt raw status auxiliary alarm interrupt raw status Reserved for debug alarm interrupt raw status day interrupt raw status hour interrupt raw status minute interrupt raw status Second interrupt raw status Day alarm updating complete interrupt clear Hour alarm updating complete interrupt clear Minute alarm updating complete interrupt clear Second alarm updating complete interrupt clear Day counter updating complete interrupt clear Hour counter updating complete interrupt clear Minute counter updating complete interrupt clear Second counter updating complete interrupt clear Spare register updating complete interrupt clear Auxiliary alarm interrupt clear alarm interrupt clear day interrupt clear hour interrupt clear minute interrupt clear Second interrupt clear Day alarm updating complete interrupt masked status Hour alarm updating complete interrupt masked status Minute alarm updating complete interrupt masked status Second alarm updating complete interrupt masked status Day counter updating complete interrupt masked status Hour counter updating complete interrupt masked status Minute counter updating complete interrupt masked status Second counter updating complete interrupt masked status Spare register updating complete interrupt masked status auxiliary alarm interrupt masked status alarm interrupt masked status day interrupt masked status hour interrupt masked status minute interrupt masked status Second interrupt masked status RTC second alarm value RTC minute alarm value RTC hour alarm value RTC day alarm value RTC spare register value RTC alarm lock register value bit type is changed from r/w to rw. RTC spare register update Write new counter value to this register to start a spare register updating operation in VDDRTC domain. Reading this register can get recent updating value. bit type is changed from r/w to rw. RTC alarm lock register update Write new counter value to this register to start a register updating operation in VDDRTC domain. Reading this register can get recent updating value. Write 8hA5 to this register to unlock alarm function, and write other data to lock alarm function. That means, software must 8hA5 to this register to enable alarm function before using this function. bit type is changed from r/w to rw. RTC power flag register set bit type is changed from r/w to rw. RTC power flag register clear RTC power flag status register bit type is changed from r/w to rw. RTC second auxiliary alarm register bit type is changed from r/w to rw. RTC minute auxiliary alarm register bit type is changed from r/w to rw. RTC hour auxiliary alarm register bit type is changed from r/w to rw. RTC day auxiliary alarm register RTC second counter raw value Only for debug RTC minute counter raw value RTC hour counter raw value Only for debug RTC day counter raw value Only for debug the IP version of this timer the IP patch version of this timer timer load value of lower 16 bit. Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. timer load value of higher 16 bit Write to this register will reload the timer with the new value. In one-time mode, this value is the first counting start number. In periodic mode, this value is each counting start number. timer open bit 0: timer stops 1: timer runs timer mode select 0: one-time mode 1: period mode timer Interrupt clear timer interrupt masked status timer interrupt raw status timer interrupt enable timer counter of lower 16bit shadow value for read. When the timer in 16 bit mode, it represent the shadow value of the timer This read-only register indicates current counter value. The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. timer counter of 16bit higher shadow value for read. It will be valid only in 64 bit mode. This read-only register indicates current counter value.The software can read the counter value immediately after load, without waiting for the load done. Also, software just needs to read once instead of double read. wdg_load_low: low 16 bit of watchdog timer load value. Wdg_load_high: high 16 bit of watchdog timer load value. wdg_load_low and wdg_load_high are used together. Software should write wdg_load_high firstly, and then write wdg_load_low, because writing wdg_load_low can trig loading both wdg_load_low and wdg_load_high to watchdog counter, and writing wdg_load_high cannot trig this event. So software must guarantee w In reset mode, software should load new value before timer decrease to 0. In interrupt mode, this value is counting start number. The default value is about 8 seconds. See wdg_load_low description Watchdog reset enable bit 0: reset is disabled 1: reset is enabled In reset mode and combined mode, this bit should be 1 Watchdog version 0: watchdog use old behavior, this is for backward compatibility. 1: watchdog uses new behavior, such as multiple loads without checking busy bit, only need to read once to get timer counter value. Watchdog counter open: 0: counter stops. 1: counter runs. Watchdog interrupt enable bit 0: interrupt is disabled 1: interrupt is enabled In interrupt mode and combined mode, this bit should be 1 Watchdog reset clear Write 1 to this bit to clear reset Read this bit always get 0. Watchdog interrupt clear Write 1 to this bit to clear interrupt Read this bit always get 0. Watchdog load busy status 0: Watchdog is ready for new loading 1: Last loading is not completed Software must not load new value when this bit is busy, that is, this bit should be checked before any new loading. This bit is set after a new loading, and lasts two or three RTC clock cycles, about 60us - 92us. Watchdog reset raw status. Watch dog reset cannot clear this raw status, so it can be used to judge if or not system rebooting comes from watchdog reset. Write wdg_rst_clr can clear this raw status. Watchdog interrupt raw status. Watch dog reset cannot clear this raw status. Write wdg_int_clr can clear this raw status. Watchdog interrupt masked status wdg_cnt_low: Low 16 bit of watchdog timer counter value. wdg_cnt_high: High 16 bit of watchdog timer counter value. wdg_cnt_low and wdg_cnt_high are used together. This read-only register indicates current counter value. Its not recommended to read this register in normal usage. Because the counter is in different clock domain with APB, software needs use double-reading method to read this value, like system timer. See wdg_cnt_low description. Watchdog lock control Write 16hE551 to this register to unlock watchdog. Write other value to this register to lock watchdog If reading this register, bit-0 is lock status, and other bits are reserved. If watchdog is locked, all control registers cannot be written by software. wdg_cnt_rd_low: Low 16 bit of watchdog timer counter value for read. wdg_cnt_rd_high: High 16 bit of watchdog timer counter value for read. wdg_cnt_rd_low and wdg_cnt_rd_high are used together. This read-only register indicates current counter value. Read once can get watchdog counter value. No need to double read this reg. Refer to timers TIMER0_CNT_RD or TIMER1_CNT_RD Refer to wdg_cnt_rd_low wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high are used together. Its useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds, which means reset will occur after irq is 1 for 6 seconds. wdg_ irqvalue_low: Low 16 bit of watchdog irqvalue. wdg_ irqvalue_high: High 16 bit of watchdog irqvalue. wdg_ irqvalue_low and wdg_ irqvalue_high are used together, which means reset will occur after irq is 1 for 6 seconds. Its useful in interrupt mode and combined mode. When wdg_cnt equal watchdog irqvalue, an interrupt is generated. Default value of watchdog irqvalue is 32h0003_0000, corresponds to 6 seconds. Enable CP sleep 0: disable 1: enable Enable AP sleep(Auto cleared to be 0 when the system is awaked) 0: disable 1: enable Enable AP sleep 0: disable 1: enable Enable CP sleep 0: disable 1: enable System begin to wakeup when the current ref_32k counter reach this value, the difference between warp value and current ref_32k value larger than one gsm frame is best. Default value when the enable bit was disabled. Enable bit of wcn idle_cg 0: disable 1: enable Enable bit of wcn pd_pll 0: disable 1: enable Enable bit of wcn pd_xtal 0: disable 1: enable Enable bit of wcn chip_pd 0: disable 1: enable Enable Timer sleep(Auto clear to be 0 when timer is awaked) 0: disable 1: enable Threshold register M1: when the signal pow_on_ack is low, both gsm and lte timer are sleeped, and the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP state. Threshold register M2: when idct_sys1 and idct_sys2 are set to be1, the difference between current ref_32k counter and sleep wrap value is larger than this register, system sleep state machine can shift to SLP_PRE state. Enable mode(TCU suspend and this bits are clear to be 0 when take over is started) 00: disbale or already release TCU. 01: take over TCU immediately 10: take over at gsm frame interrupt. 11: no effect. restart TCU when gsm counter reach this register restart mode(this bits clear to be 0 when TCU restarts) 00: disable 01: restart TCU immediately 10: restart TCU when gsm frame interrupt occurred. 11: restart TCU when gsm framc equal to TC_END_FRAMC. Timer wakeup enable(software accessed only) 0: disable 1: enable TCU restart enable(software accessed only) Output to the port gsm_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. gsm_frame_irq enable 1: enable 0: disable cleared by writing 1 to correspond bit ltem1_frame3_irq enable 1: enable 0: disable ltem1_frame2_irq enable 1: enable 0: disable ltem1_frame1_irq enable 1: enable 0: disable bit type is changed from rw1c to rc. cleared by writing 1 to correspond bit ltem2_frame3_irq enable 1: enable 0: disable ltem2_frame2_irq enable 1: enable 0: disable ltem2_frame1_irq enable 1: enable 0: disable bit type is changed from rw1c to rc. cleared by writing 1 to correspond bit NB timer state 0: running at 61.44M 1: running at 32K H circuit state 0: not work 1: at wok ltem2 timer state 0: running at 122.88M 1: running at 32K ltem1 timer state 0: running at 122.88M 1: running at 32K GSM timer state 0: running at 26M 1: running at 32K SYS state 0: normal working 1: low power mode Runtime of H circuit, the length is 2^h_run_time(number of 32k clocks) Automatic computing mode enable(loop computing until disabled) 0: disable 1: enable Invocation pattern(compute only one time, automatic clear to be 0 when finished.) 0: disable 1: enable The length of sys clock in 2^h_run_time 32k cycles The cycles number of 26M in 2^h_run_time 32k cycles The cycles number of 122.88M in of 2^h_run_time 32k cycles signal nb_lp_pu_reach wakeup enable 0: disable 1: enable signal gsm_lp_pu_reach wakeup enable 0: disable 1: enable sofware wakeup enable 0: disable 1: enable OSW2 wakeup enable 0: disable 1: enable OSW1 wakeup enable 0: disable 1: enable wcn_osc_en wakeup enable 0: disable 1: enable wcn2sys wakeup enable 0: disable 1: enable pad_uart1_rxd wakeup enable 0: disable 1: enable Uart1_irq wakeup enable 0: disable 1: enable Gpio1_irq wakeup enable 0: disable 1: enable Keyboard wakeup enable 0: disable 1: enable Vad_int wakeup enable 0: disable 1: enable Pad_gpio6 wakeup enable 0: disable 1: enable pow_dfe_ack state 0: pow_dfe_ack is 0 when system exit IDLE 1: pow_dfe_ack is 1 when system exit IDLE bit type is changed from rw1c to rc. Threshold M1 state 1: pow_ack not meet threshold M1 or pow_ack not feedback in sleep period 0: meet threshold M1 bit type is changed from rw1c to rc. pow_ack state 0: pow_ack is 0 when system exit IDLE 1: pow_ack is 1 when system exit IDLE bit type is changed from rw1c to rc. system exit idle state 0: sys not enter idle 1: sys enter idle state bit type is changed from rw1c to rc. IDLE sleep wakeup state 0: awaked before the sleep warp time 1: awaked at the sleep warp time bit type is changed from rw1c to rc. Signal nb_lp_pu_reach wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. Signal gsm_lp_pu_reach wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. software wakeup state 0: software wakeupup signal not generated 1: software wakeupup system. bit type is changed from rw1c to rc. OSW2 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. OSW1 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK7 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK6 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK5 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK4 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWk3 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWk2 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK1 wakeup state 0: this signal not generated 1: this signal generated bit type is changed from rw1c to rc. AWK0 wakeup state 0: this signal not generated 1: this signal generated 0: not effect 1: wakeup system (accessed by software only, this bit shold clear bu software when system is awaked.) 1: enable 0: disable osw1 wrap value OSW1 Timer is based on a slow counter, which start counting from the wrap value and decreasing 1 at each 2 cycles(counter frequency is 16K), the counter suspend when disabled. Number of frames gsm sleeped. Number of frames ltem1 sleeped. Number of sub-frames ltem1 sleeped. Number of frames ltem2 sleeped Number of sub-frames ltem2 sleeped. LTE sleep frame length, suggest keep the default value. LTE sleep sub-frame length, suggest keep the default value. Idle_cg_en enable 1: enable. 0: disable. Pd_pll_en enable 1: enable 0: disable pd_xtal_en enable 1: enable. 0: disable. chip_pd_en enable 1: enable. 0: disable. The time from enable clock to obtain clock The time of PLL from power saving state to output normal clock. The time of OSC circuit from power saving state to normal state. The time of PMIC boost stabilization. Current 32K counter value target_irq enable 1: enable 0: disable nb_pu_reach_irq enable 1: enable 0: disable nb_tc_end_irq enable 1: enable 0: disable nb_tc_start_irq enable 1: enable 0: disable sys_awk _irq enable 1: enable 0: disable Timer_awk_irq_enable 1: enable 0: disable gsm_pu_reach_irq enable 1: enable 0: disable gsm_tc_end_irq enable 1: enable 0: disable gsm_tc_start_irq enable 1: enable 0: disable osw1_irq enable 1: enable 0: disable tstamp_irq enable 1: enable 0: disable idle_frame_irq enable 1: enable 0: disable idle_h_irq enable 1: enable 0: disable layout_irq enable 1: enable 0: disable bit type is changed from w1s to rs. set cp interrupt enable register when writing 1 to correspond bits. bit type is changed from rw1c to rc. clear cp interrupt enable register when writing 1 to correspond bits. bit type is changed from rw1c to rc. clear interrupt state register when writing 1 to correspond bits. target_irq enable 1: enable 0: disable nb_pu_reach_irq enable 1: enable 0: disable sys_awk _irq enable 1: enable 0: disable Timer_awk_irq_enable 1: enable 0: disable gsm_pu_reach_irq enable 1: enable 0: disable osw2_irq enable 1: enable 0: disable bit type is changed from w1s to rs. set ap interrupt enable register when writing 1 to correspond bits. bit type is changed from rw1c to rc. clear ap interrupt enable register when writing 1 to correspond bits. bit type is changed from rw1c to rc. clear ap interrupt state register when writing 1 to correspond bits. Ltem1 high-level frame number value LTE-M1 frame number LTE-M1 sub-frame number frame adjust time 0: adjust at next frame interrupt 1: adjust frame immetiately frame adjust direction 0: postive 1: negative LTE-M1 frame offest value (Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) LTE-M1 high-level frame value LTE-M1 radio frame value LTE-M1 sub-frame value LTE-M1 counter value LTE-M1 frame length adjust time 0: adjust immetiately 1: adjust at next ltem frame interrupt LTE-M1 adjuste frame length. current Ltem frame length load the register when write happens,then return the LFRAML at the time of lte frame interrupt arrivals. LTE-M1 high-level frame value time stamp register LTE-M1 frame stamp value LTE-M1 stamp counter LTE-M2 high-level frame value LTE-M2 radio frame value LTE-M2 sub-frame value adjust time. 0: adjust at next frame interrupt 1: adjust frame immetiately adjust direction 0: postive 1: negative Frame offest value(Adjust frame offset B, there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value at the time of frame interrupt genereted. otherwise write b-1 into this register then current frame minus this value at the time of frame interrupt generated.) LTE-M2 super read frame value LTE-M2 radio frame read value LTE-M2 sub-frame read value LTE-M counter LTE-M2 frame length value adjust time 0: adjust immetiately 1: adjust at next ltem frame interrupt LTE-M2 adjuste frame length. current Ltem frame length load the register when write happens,then backed the LFRAML at the time of lte frame interrupt occurred. LTE-M2 high-level frame time stamp register LTE-M2 frame stamp value LTE-M2 stamp counter GSM frame value adjust direction 0: postive 1: negative frame offest value (Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 into this register then current frame plus this value when frame interrupt occurred. otherwise write b-1 into this register then current frame minus this value when frame interrupt occurred.) GSM frame overflow value LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. LTE-M frame locked value, lock the register LTEM_CFSR_FN LTE-M couner locked value LTE-M high-level frame locked value, lock the register LTEM_CFSR_HFN. LTE-M frame locked value, lock the register LTEM_CFSR_FN LTE-M counter locked value GSM frame locked value GSM counter locked value lock signal 000: ltem1 frame interrupt. 001: ltem2 frame interrupt. 010: gsm frame interrupt. 011: negative of 32k clock. 100: nb frame interrput. others: gsm frame interrupt. lock way 00: disable lock 01: bit 0 control the time stamp, bit 0 auto clear to be 0 after time stamp finsihed. 10: time stamp when lock signal comes after that bit 5 and 4 clear to be 0. 11: time stamp loop 1: time stamp immediately. 0: not effect The initial value of task planning, the register value decrement after a certain number of TS when started task planning, you can get the remaining time by reading this register. Layoutt register descending unit. 15h0000: 1 15h0001: 2 15h0002: 3 15h7fff: 32768 Layout count time selection 0: ltem1 timer 1: ltem2 timer task planning 1: start task planing 0: end timing (The control bit is clear automatically after the timer is finished, and the software can be clear to bestop counting.) LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTE-M2 frame interrupt delay, take ltem2_framc as a reference. LTE-M2 frame interrupt delay, take ltem2_framc as a reference. Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. Each bit corresponds to 10 sub-frame, sub-frame interrupt will be sent to CPU when correspond bit is enabled. NB timer enable 0: disable 1: enable LTE-M timer enable 0: disable 1: enable (note: this timer is the reference lte timer.) GSM timer enable 0: disable 1: enable LTE-M2 timer enable 0: disable 1: enable LTE-M1 timer enable 0: disable 1: enable bit type is changed from rw1c to rc. NB frame interrupt state 0: No interrupt occurred 1: interrupt occurred bit type is changed from rw1c to rc. reference lte frame interrupt state 0: No interrupt occurred 1: interrupt occurred bit type is changed from rw1c to rc. GSM frame interrupt state 0: No interrupt occurred 1: interrupt occurred bit type is changed from rw1c to rc. LTE-M2 frame interrupt state 0: No interrupt occurred 1: interrupt occurred bit type is changed from rw1c to rc. LTE-M1 frame interrupt state 0: No interrupt occurred 1: interrupt occurred enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt frame number interrupt occurred when current frame reach this register. enable(this bit is cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register. enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_GSM interrupt occurred when current frame reach this register. enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable reference lte frame reference lte frame locked value reference lte counter locked value reference 32k counter locked value reference lte counter GSM frame length value 1: enable OSW2 timer 0: disable OSW2 Timing start value OSW2 Timer is based on a slow counter, which start counting from the start value and decreasing 1 at each 2 cycles(counter frequency is 16K) IDLE GSM frame interrupt generated when GSM frame counter reach GSM_FRAME_GSM and GSM counter equal to this register. LTE-M1 frame interrupt delay, take ltem1_framc as a reference. LTE-M2 frame interrupt delay, take ltem2_framc as a reference. 1: select pd_xtal, 0: select chip_pd the length of pd_xtal(or chip_pd) set to be 1. The cycles number of 26M in 2^h_run_time 32k cycles The cycles number of 122.88M in of 2^h_run_time 32k cycles Enable mode(NB TCU suspend and this bits are cleared by hardware when take over started) 00: disbale or already release TCU. 01: take over TCU immediately 10: take over at gsm frame interrupt. 11: no effect. restart TCU when gsm counter reach this register restart mode(this bits cleared when TCU restarts) 00: disable 01: restart TCU immediately 10: restart TCU when gsm frame interrupt occurred. 11: restart TCU when gsm framc equal to TC_END_FRAMC. TCU restart enable(accessed by software only.) Output to the port nb_lp_pu_done directly, wakeup TCU in low power mode when writing 1 to this bit. The cycles number of 61.44M in the length of 2^h_run_time 32k cycles The cycles number of 61.44M in the length of 2^h_run_time 32k cycles Number of frames nb timer sleeped. nb_frame_irq enable 1: enable 0: disable cleared by writing 1 to correspond bit NB frame value NB frame length value adjust direction 0: postive 1: negative frame offest value (Adjust frame offset B. there are two case: if adjust direction is 0, write b+1 to this register then current frame plus this value when frame interrupt occurred. otherwise write b- 1 to this register then current frame minus this value when frame interrupt occurred.) NB frame overflow value NB frame locked value NB counter locked value enable(this bit cleared automatically after the frame interrupt generated) 0: disable 1: enable interrupt occurred when current frame reach this register and counter equal to IDLE_FRAMC_NB IDLE NB frame interrupt generated when NB frame counter reach IDLE_FRAME_NB and NB counter equal to this register. bit type is changed from w1s to rs. set wakeup enable register by writing 1 to correspond bits. bit type is changed from rw1c to rc. clear wakeup enable register by writing 1 to correspond bits. Read enable register. This bit should be set first when read the value of GSM counter, then rd_enable bit cleared by hardware after locked the GSM counter. GSM framc Read enable register. This bit should be set first when read the value of NB counter, then rd_enable bit cleared by hardware after locked the NB counter. NB framc Eliminate jitter delay register Emilinate the jitter from awake signal when writing 1 to correspond bits. GGE low power Scheme selection signal 0: use RDA8909 LP Scheme 1: use IDLE module of LP Scheme NB low power Scheme selection signal 0: use RDA8909 LP Scheme 1: use IDLE module of LP Scheme 1:disbale PLL 0:enable PLL 1:disable PLL 0:enbale PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL 1:disable PLL 0:enable PLL bit type is changed from w1s to rs. set corresponding bits of PD_PLL_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of PD_PLL_SW 0:Invariance of corresponding bits 1:clean corresponding bits select hardware signal or software register to control the PLL output clk switch 1:software register(bit6 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit5 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit4 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit3 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit2 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit1 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) select hardware signal or software register to control the PLL switch 1:software register(bit0 of PD_PLL_SW) 0:hardware signal(IDLE module of pd_pll signal invert) bit type is changed from w1s to rs. set corresponding bits of PD_PLL_SEL 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of PD_PLL_SEL 0:Invariance of corresponding bits 1:clean corresponding bits 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk 1:disable PLL output clk 0:enable PLL output clk bit type is changed from w1s to rs. set corresponding bits of IDLE_CG_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of IDLE_CG_SW 0:Invariance of corresponding bits 1:clean corresponding bits select hardware signal or software register to control the PLL output clk switch 1:software register(bit6 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit5 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit4 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit3 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit2 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit1 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) select hardware signal or software register to control the PLL output clk switch 1:software register(bit0 of IDLE_CG_SW) 0:hardware signal(IDLE module of idle_cg signal invert) bit type is changed from w1s to rs. set corresponding bits of IDLE_CG_SEL 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of IDLE_CG_SEL 0:Invariance of corresponding bits 1:clean corresponding bits 1:control the RF_DIG enter in IDLE 0:control the RF_DIG exit to the IDLE select the hardware signal or software register to control the RF_DIG enter in or extit to IDLE model. 1:software register(RF_IDLE_ENABLE_SW) 0:hardware signal( pow_on signal invert of IDLE module) RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal UART module reset control: 0: reset 1: reset release UART module clock control: 0: disable 1: enable PSRAM IO LATCH: 0: release PSRAM PAD 1: no release PSRAM PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after PSRAM initialization when AP wake-up from deep sleep. LPDDR IO LATCH: 0: release LPDDR PAD 1: no release LPDDR PAD.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after LPDDR initialization when AP wake-up from deep sleep. mon15_sel: 00: select nb_en. 01: select awk_sys_valid. 10: select awake[7]. 11: select target_timer_stat[1]. mon14_sel: 00: select gsm_en. 01: select wcn_chip_pd. 10: select awake[6]. 11: select target_timer_stat[0]. mon13_sel: 00: select wake_timer. 01: select wcn_pd_xtal. 10: select awake[5]. 11: select target_timer_enable. mon12_sel: 00: select timer_en_nb. 01: select wcn_pd_pll. 10: select awake[4]. 11: select nb_frame_int. mon11_sel: 00: select timer_en_gsm. 01: select wcn_idle_cg. 10: select awake[3]. 11: nb_lp_pu_done. mon10_sel: 00: select timer_en_ltem2. 01: select nb_en_sel. 10: select awake[2]. 11: select nb_lp_sf_slowrunning. mon9_sel: 00: select timer_en_ltem1. 01: select gsm_en_sel. 10: select awake[1]. 11: select nb_fint. mon8_sel: 00: select idst_nb_timer. 01: select idle_chip_pd. 10: select awake[0]. 11: select gsm_frame_int. mon7_sel: 00: select idst_gsm_timer 01: select idle_pd_xtal. 10: select awk_self. 11: gsm_lp_pu_done. mon6_sel: 00: select idst_ltem2_timer. 01: select idle_pd_pll. 10: select idst_gsm_ltem_timer. 11: select gsm_lp_sf_slowrunning. mon5_sel: 00: select idst_ltem1_timer. 01: select idle_idle_cg. 10: select awk_gsm_ltem_timner. 11: select gsm_fint. mon4_sel: 00: select idct_nb_timer. 01: select pow_on. 10: select idst_sys. 11: select rstctrl_uart. mon3_sel: 00: select idct_gsm_timer. 01: select idct_sys_valid. 10: select nb_lp_pu_reach. 11: select clken_uart. mon2_sel: 00: select idct_ltem2_timer. 01: select idct_ap. 10: select gsm_lp_pu_reach. 11: select psram_latch_reg. mon1_sel: 00: select idct_ltem1_timer 01: select idct_cp. 10: select osw2_awk 11: select lpddr_latch_reg mon0_sel: 00: select idct_timer. 01: select ltem1_fint. 10: select osw1_awk. 11: select ltem2_fint set corresponding bits of MON_SEL 0:Invariance of corresponding bits 1:set corresponding bits clear corresponding bits of MON_SEL 0:Invariance of corresponding bits 1:clear corresponding bits Interrupt generated when the reference 32K counter reach to this register value. 1: disable target timer. 0: enable The locked value of reference 32K when interrupt generated. Indicat the state of target timer in 32K clock domain Indicate the state of target timer in 122.88M clock domain 0:SLOW_CLK and system clk selected by software bit conrtol 1:SLOW_CLK and system clk select by hareware signal control 0:SLOW_CLK selected(between 26M and 32k) by software bit control 1:SLOW_CLK selected(between 26M and 32k) by hareware signal control The minimum threshold of deep sleep, to ensure PMIC have complete deep sleep in and deep sleep out. sysmail0 Interrupt generate register bit type is changed from ws to rs. sysmail0 interrupt bit set register bit type is changed from w1c to rc. sysmail0 interrupt clean register sysmail0 interrupt mask register sysmail0 interrupt status register sysmail0 interrupt mask status register sysmail1 Interrupt generate register bit type is changed from ws to rs. sysmail1 interrupt bit set register bit type is changed from w1c to rc. sysmail1 interrupt clean register sysmail1 interrupt mask register sysmail1 interrupt status register sysmail1 interrupt mask status register sysmail2 Interrupt generate register bit type is changed from ws to rs. sysmail2 interrupt bit set register bit type is changed from w1c to rc. sysmail2 interrupt clean register sysmail2 interrupt mask register sysmail2 interrupt status register sysmail2 interrupt mask status register sysmail3 Interrupt generate register bit type is changed from ws to rs. sysmail3 interrupt bit set register bit type is changed from w1c to rc. sysmail3 interrupt clean register sysmail3 interrupt mask register sysmail3 interrupt status register sysmail3 interrupt mask status register sysmail4 Interrupt generate register bit type is changed from ws to rs. sysmail4 interrupt bit set register bit type is changed from w1c to rc. sysmail4 interrupt clean register sysmail4 interrupt mask register sysmail4 interrupt status register sysmail4 interrupt mask status register sysmail5 Interrupt generate register bit type is changed from ws to rs. sysmail5 interrupt bit set register bit type is changed from w1c to rc. sysmail5 interrupt clean register sysmail5 interrupt mask register sysmail5 interrupt status register sysmail5 interrupt mask status register clock select for module of IDLE_H: 00: 122.88M clock 01: 26M clock 10: 61.44M clock 11: 122.88M clock clock select for module of ZSP_WD: 0: 32K clock 1: 26M clock clock select for module of BB_SYSCTRL_WD: 0: 32K clock 1: 26M clock clock select of 480M and SLOW: 0: SLOW clock 1: 480M clock clock select of 122M and SLOW: 0: SLOW clock 1: 122.88M clock bit type is changed from w1s to rs. set corresponding bits of CLKSEL register: 0: Invariance of corresponding bits 1: set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of CLKSEL register: 0: Invariance of corresponding bits 1: clean of corresponding bits ZSP and bus clock division: 0: no clock division 1: 1/16 clock division 2: 2/16 clock division F: 15/16 clock division LTE accelerator function clock division: 0: no clock division 1: 1/16 clock division 2: 2/16 clock division F: 15/16 clock division 0: close 1: open 0: close 1: open 0: close 1: open 0: close 1: open 0: close 1: open bit type is changed from w1s to rs. set corresponding bits of CLKEN_BB_SYSCTRL regsiter: 0: Invariance of corresponding bits 1: set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of CLKSEL register 0: Invariance of corresponding bits 1: clean of corresponding bits 0: close 1: open 0: close 1: open 0: close 1: open 0: close 1: open 0: close 1: open 0: close 1: open bit type is changed from w1s to rs. set corresponding bits of CLKEN_ZSP regsiter: 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of CLKEN_ZSP register: 0: Invariance of corresponding bits 1: clean of corresponding bits 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable bit type is changed from w1s to rs. set corresponding bits of CLKEN_LTE register 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of CLKEN_LTE: 0: Invariance of corresponding bits 1: clean of corresponding bits 0: ZSPCORE clock switch controlled by hardware 1: ZSPCORE clock switch controlled by register 0: ZSP_AXIDMA clock switch controlled by hardware 1: ZSP_AXIDMA clock switch controlled by register 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset bit type is changed from w1s to rs. set corresponding bits of RSTCTRL_BB_SYSCTRL register: 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of RSTCTRL_BB_SYSCTRL: 0: Invariance of corresponding bits 1: set 1 of corresponding bits 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset bit type is changed from w1s to rs. set corresponding bits of RSTCTRL_ZSP register: 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of RSTCTRL_ZSP: 0: Invariance of corresponding bits 1: set "1" of corresponding bits 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset) 1: no reset 0: reset 1: no reset 0: reset 1: no reset 0: reset 1: no reset bit type is changed from w1s to rs. set corresponding bits of RSTCTRL_LTE register: 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of RSTCTRL_LTE: 0: Invariance of corresponding bits 1: clean corresponding bits 0: reset 1: no reset 0: reset 1: no reset waiting time of bus entered low power model,calculated by bus clock Control bit of ZSP_CORE DOMAIN low power model 0: enable 1: disable Control bit of PHY DOMAIN low power model 0: enable 1: disable control bit of SWITCH2 DOMAIN low power model 0: enable 1: disable control bit of SWITCH1 DOMAIN low power model: 0: enable 1: disable bit type is changed from w1s to rs. set corresponding bits of ZSP_BUSLPMC register 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of ZSP_BUSLPMC 0: Invariance of corresponding bits 1: clean corresponding bits control bit of ZSPCORE force entering in low power model: 0: disable 1: enable control bit of PHY DOMAIN force entering in low power model: 0: disable 1: enable control bit of SWITCH2 DOMAIN force entering in low power model: 0: disable 1: enable control bit of SWITCH1 DOMAIN force entering in low power model: 0: disable 1: enable bit type is changed from w1s to rs. set corresponding bits of ZSP_BUSFORCELPMC: 0: Invariance of corresponding bits 1: clean corresponding bits bit type is changed from w1c to rc. clean corresponding bits of ZSP_BUSFORCELPMC: 0: Invariance of corresponding bits 1: clean corresponding bits 0: MAILBOX clock switch controlled by hardware 1: MAILBOX clock switch controlled by register 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable bit type is changed from w1s to rs. set corresponding bits of CLKEN_LTE_INTF register 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of CLKEN_LTE_INTF register 0: Invariance of corresponding bits 1: clean of corresponding bits 0: LTE module clock auto gating individual 1: LTE modules invide into two parties : "uplink" and "downlink", and auto gating individual 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable bit type is changed from w1s to rs. set corresponding bits of LTE_AUTOGATE_EN register 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of LTE_AUTOGATE_EN register 0: Invariance of corresponding bits 1: clean of corresponding bits When LTE autogating function enable, After module "running" signal was pull down, a counter begin to count from zero.LTE modules clock will be gated when the counter counts to this number value. AON_LP hardware power domain switch: 1:AON_LP power domain switch controlled by hardware signal. 0:AON_LP power domain switch controlled by regiser. BTFM hardware power domain switch: 1:BTFM power domain switch controlled by hardware signal. 0:BTFM power domain switch controlled by regiser. RF hardware power domain switch: 1:RF power domain switch controlled by hardware signal. 0:RF power domain switch controlled by register. GGE hardware power domian switch: 1:GGE power domain switch controlled by hardware signal. 0:GGEpower domain switch controlled by register. LTE hardware power domain switch: 1:LTE power domain switch controlled by hardware signal. 0:LTE power domain switch controlled by register. ZSP hardware power domain switch: 1:ZSP power domain switch controlled by hardware signal . 0:ZSP power domain switch controlled by register. AP hardware power domain switch: 1:AP power domain switch controlled by hardware signal. 0:AP power domain switch controlled by register. AP power domain on: 1:AP power domain on. 0:after AP power domain on,hardware cleared. AP power domain off: 1:AP power domian off. 0:after AP power domain off,hareware cleared. ZSP power domain on: 1:ZSP power domain on. 0:after ZSP power domain on,hardware cleared. ZSP power domain off: 1:ZSP power domain off. 0:after ZSP power domain off,hardware cleared. LTE power domain on: 1:LTE power domain on. 0:after LTE power domain on,hardware cleared. LTE power domain off: 1:LTE power domain off. 0:after LTE power domain off,hardware cleared. GGE power domain on: 1:GGE power domain on. 0:after GGE power domain on,hardware cleared. GGE power domain off: 1:GGE power domain off. 0:after GGE power domain off,hardware cleared. RF power domain on: 1:RF power domain on. 0:after RF power domain on,hardware cleared. RF power domain off: 1:RF power domain off. 0:after RF power domain off,hardware cleared. BTFM power domain on: 1:BTFM power domain on. 0:after BTFM power domain on,hardware cleared. BTFM power domain off: 1:BTFM power domain off. 0:after BTFM power domain off,hardware cleared. AON_LP power domain on: 1:AON_LP power domain on. 0:after AON_LP power domain on,hardware cleared. AON_LP power domain off: 1:AON_LP power domain off. 0:after AON_LP power domain off,hardware cleared. AP power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off of the middle state. AP power domain current state: 1:on 0:off ZSP power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off of the middle state. ZSP power domain current state: 1:on 0:off LTE power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off of the middle state. LTE power domain current state: 1:on 0:off GGE power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off the middle state. GGE power domain current state: 1:on 0:off RF power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off the middle state. RF power domain current state: 1:on 0:off BTFM power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off the middle state. BTFM power domain current state: 1:on 0:off AON_LP power domain stable state: 1:power domain stable. 0:power domain unstable,in the power on/off the middle state. AON_LP power domain current state: 1:on 0:off power control state machine for Intermediate state delay value,use function clk count power gating cell domain power-on of waiting time value,use function clk count. All of power gating cell power-on of waiting time value,use function clk count. 0:release DDR port signals 1:no release DDR port signals.This bit will be set "1" by hardware when AP power domain was shut-down.Software should write this bit to "0" after ddr initialization when AP wake-up from deep sleep. 1:vote for off ZSP power domain 0:vote for on ZSP power domain 1:vote for off ZSP power domain 0:vote for on ZSP power domain 1:vote for off ZSP power domain 0:vote for on ZSP power domain bit type is changed from w1s to rs. set corresponding bits of ZSP_PD_POLL 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of ZSP_PD_POLL 0:Invariance of corresponding bits 1:clean corresponding bits wcn2sys_sleep signal state wcn2sys_osc_en signal state wcn2sys_wakeup signal state control WCN sub_system of awake siganl:sys2wcn_awake when this bit set "1",the hardware signal arm_slp_req will enter in ARM sub_system ,force ARM's AXI bus enter LP model. 0:normal work 1:SLEEP request the work status of AXI bus in ARM sub_system . 0:normal work 1:low_power state 0:the hardware signal arm_slp_req controlled by ARM_SLP_REQ_SW register,and pwrctrl status is bypass. 1:pwrctrl status controlled by the hardware signal of arm_slp_req. when this bit set "1",zsp_slp_req signal will enter in ZSP sub_system ,force ZSP's AXI bus enter in LP model. Before ZSP sub_system software reset,need this bit set "1",and wait ZSP_SLP_ACK register to be "1".after ZSP sub_system reset,should set this bit "0",so that ZSP bus can normal work. 0:normal work 1:SLEEP request the status of AXI bus in ZSP sub_system. 0:normal work 1:low_power state 0:zsp_slp_req signal controlled by ZSP_SLP_REQ_SW register,and pwrctrl status is bypass. 1: pwrctrl status controlled by the hareware signal of zsp_slp_req when this bit set "1",ddr_slp_req hardware signal will enter in ARM sub_system,force DDR enter in self refresh. 0:normal work 1:SLEEP request DDR work status 0:normal work status 1:low_power(self_refresh)state 0:ddr_slp_req is the hardware signal controlled by DDR_SLP_REQ_SW register,and pwrctrl corresponding status is bypass. 1:pwrctrl status controlled by the hareware signal of ddr_slp_req 0:normal work 1:DDR sleep request time out 0:normal work 1:ZSP bus sleep request time out 0:normal work 1:ARM bus sleep request time out power domain auto control state machine status AON_LP power domain state of machine status BTFM power domain state of machine status RF power domain state of machine status GGE power domain state of machine status LTE power domain state of machine status ZSP power domain state of machine status ARM power domain state of machine status 0:power domain control siganl conrtolled by related bit of PWRCTRL_SW register 1:power domain conrtol signal conrtolled by hardware signal of PWRCTRL btfm_pwr_ctrl btfm_pwr_ctrl_pre btfm_hold btfm_rst_ctrl btfm_clk_ctrl rf_pwr_ctrl rf_pwr_ctrl_pre rf_hold rf_rst_ctrl rf_clk_ctrl gge_pwr_ctrl gge_pwr_ctrl_pre gge_hold gge_rst_ctrl gge_clk_ctrl lte_pwr_ctrl lte_pwr_ctrl_pre lte_hold lte_rst_ctrl lte_clk_ctrl zsp_pwr_ctrl zsp_pwr_ctrl_pre zsp_hold zsp_rst_ctrl zsp_clk_ctrl ap_pwr_ctrl ap_pwr_ctrl_pre ap_hold ap_rst_ctrl ap_clk_ctrl bit type is changed from w1s to rs. set corresponding bits of PWRCTRL_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of PWRCTRL_SW 0:Invariance of corresponding bits 1:clean corresponding bits aon_lp_pwr_ctrl aon_lp_pwr_ctrl_pre aon_lp_hold aon_lp_rst_ctrl aon_lp_clk_ctrl bit type is changed from w1s to rs. set corresponding bits of PWRCTRL_SW 0:Invariance of corresponding bits 1:set 1 of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of PWRCTRL_SW1 0:Invariance of corresponding bits 1:clean corresponding bits Interrupt vector entry address RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RASPD type EMA signal RASPD type EMA signal RASPU type EMA signal RASPU type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RASPD type EMA signal RASPD type EMA signal RASPU type EMA signal RASPU type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal ROM type EMA signal ROM type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RFTPD type EMA signal RASPD type EMA signal RASPD type EMA signal RASPU type EMA signal RASPU type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal RADPD type EMA signal awqos_zsp_axidma arqos_zsp_axidma awqos_zsp_ibus arqos_zsp_ibus awqos_zsp_dbus arqos_zsp_dbus Used to store and determine whether the pow on and Other relevant information is in a calibrated version RF scheme selection signal 0: use SOC RF scheme signal 1: use chip RF scheme AD/DA data path select signal 1: LTE 0: NBIOT AD/DA data path select signal 0: NBIOT 1: GGE WCN 26M clock control: 0: disable 1: enable ADI module 26M clock control: 0: disable 1: enable VAD module 26M clock control: 0: disable 1: enable AUD2AD module of 26M clock select: 0: AP_26M 1: after 17/16 clock operation AUD2AD module of 26M clock switch: 0: disable 1: enable audio pll input Reference clock select: 0: AP_26M 1: after 17/16 clock operation 0: disable 1: enable 0: disable 1: enable 0: disable 1: enable bit type is changed from w1s to rs. set corresponding bits of RF_ANA_26M_CTRL register: 0: Invariance of corresponding bits 1: set "1" of corresponding bits bit type is changed from w1c to rc. clean corresponding bits of RF_ANA_26M_CTRL register: 0: Invariance of corresponding bits 1: clean corresponding bits 0: DISABLE 1: ENABLE When AP power domain shut-down, this bit will be clear to "0". Need software re-enable. 0: do not force ddr_slp_ctrl wakeup 1: force ddr_slp_ctrl wakeup force ddr_slp_ctrl wakeup done when "1" after count N cycles,ddr_slp_ctrl begin sleep sequence when sleep condition meet. LVDS_SPI_SEL 0: select idle_test[16] (LTE frame irq signal.) 1: select lte_rbdp_tx[11]; bit type is changed from rw1c to rc. Indicate RFSPI_CONFILICT_IRQ happened when "1". Can be cleared by software writing "1". bit type is changed from rw1c to rc. Indicate TXFIFO_FULL_IRQ happened when "1". Can be cleared by software writing "1". 0: select lte_up_rfctrl; 1: select rf_gpio_o[9]; 0: 3-wire mode; 1: 4-wire mode; General ctrl signal for GGENB. 1:enable 0:disable 1:enable 0:disable 0 1 2 3 4 5 6 7 monitor_o[0] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[1] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[2] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[3] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[4] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[5] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[6] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 monitor_o[7] 3'h0: 0 3'h1: 1 3'h2: 2 3'h3: 3 3'h4: 4 3'h5: 5 3'h6: 6 3'h7: 7 1 0 monitor output signal value. WD_PROT function enable 0: WD_PROT register function invalid 1: WD_PROT register function valid 0: timer mode 1: watchdog mode 0000: no pre-div 0001: 1/2 pre-div 0010: 1/4 pre-div 0011: 1/8 pre-div 0100: 1/16 pre-div 0101: 1/32 pre-div 0110: 1/64 pre-div 0111: 1/128 pre-div 1000: 1/256 pre-div others: no pre-div 0: no influence to current timer value 1: clear current timer value to zero 0: interrupt disable 1: interrupt enable 0: keep the timer value when it reach the loaded value 1: clear the timer value to zero when it reach the loaded value 0: stop 1: run Note: WD_LOAD1/2 register can not be writen when this bit is '1'. This bit will be clear by hardware when reset signal generated in watchdog mode; and in timer mode, this bit will be clear by hardware when timer value reach the loaded value and 'AR' is set to '0'. WD_CONF and WD_LOAD1/2 register can be writen when this register value is 0xCCCC. The low 32-bits of the load value. The high 32-bits of the load value. The low 32-bits of the timer value. The high 32-bits of the timer value. Write orderly 0xAAAA and 0x5555 to convert to timer mode from watchdog mode. Write orderly 0xAAAA and 0x4444 to convert to watchdog mode from timer mode. Write 0xBBBB to "feed dog" in watchdog mode. 0: disable timer divider 1: enable timer divider f= FuncClk/(DIV+1) bit type is changed from w1c to rc. The counter value of timer divider. bit type is changed from w1c to rc. Interrupt source flag(0-31) 0: no interrupt 1: capture interrupt bit type is changed from w1c to rc. Interrupt source flag(32-63) 0: no interrupt 1: capture interrupt Interrupt mask bit (0-30) 0: open interrupt 1: mask interrupt Interrupt mask bit (32-63) 0: open interrupt 1: mask interrupt bit type is changed from w1s to rs. sets the corresponding bit in the mask register (0-31) 0: the corresponding bit in the mask register do not change. 1: sets the corresponding bit in the mask register to '1'. bit type is changed from w1s to rs. sets the corresponding bit in the mask register(32-64) 0: the corresponding bit in the mask register do not change. 1: sets the corresponding bit in the mask register to '1'. bit type is changed from w1c to rc. clears the corresponding bit in the mask register(0-31) 0: the corresponding bit in the mask register do not change 1: Writing '1' clears the corresponding bit in the mask register to '0'. bit type is changed from w1c to rc. clears the corresponding bit in the mask register(32-64) 0: the corresponding bit in the mask register do not change 1: Writing '1' clears the corresponding bit in the mask register to '0'. Global interrupt enable BIT 0: Interrupt is decided by corresponding mask bit 1: Maks all Interrupt FIQ OR IRQ Select (0-31) 0: corresponding interrupt send to arm through IRQ 1: corresponding interrupt send to arm through FIR FIQ OR IRQ Select (32-63) 0: corresponding interrupt send to arm through IRQ 1: corresponding interrupt send to arm through FIR IRQ status bit(0-31) 0: corresponding interrupt source no interrupt 1: corresponding interrupt source no interrupt send interrupt to arm through IRQ IRQ status bit(32-63) 0: corresponding interrupt source no interrupt 1: corresponding interrupt source no interrupt send interrupt to arm through IRQ IRQ interrupt source code 0000000: IRQ0 0000001: IRQ1 0000010: IRQ2 ...... 0111111: IRQ63 Clear interrupt status bit 0: no operation 1: clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low FIQ status bit(0-31) 0: corresponding interrupt source no interrupt 1: corresponding interrupt source no interrupt send interrupt to arm through Fiq FIQ status bit(32-63) 0: corresponding interrupt source no interrupt 1: corresponding interrupt source no interrupt send interrupt to arm through Fiq fiq interrupt source code 0000000: FIQ0 0000001: FIQ1 0000010: FIQ2 ...... 0111111: FIQ63 Clear interrupt status bit 0: no operation 1: clear corresponding bit of IRQ_STA and ITR,at the same time change irq from high to low Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio Interrupt prio 0: Interrupt prio 0 1: Interrupt prio 1 ...... 7: Interrupt prio 7 Prio 0 is corrosponed to the highist prio general used register security visit enable 0security 1unsecurity response error stop function enable 0enable 1disable the number of outstanding that can be send out 0: 2 1: 3 2: 4 multe-channel transport priority mode control 0: there is no priority in the channels, using polling to DMA data 1: smaller channel number has high-priority.high-priority move data before low-priority channels interrupt control bit 0: no interruption occurs when all logical channels finish 1: interruption occurs when all logical channels finish the control bit of logical channel transport finish 0: don't stop all the channel,or automatically clear after setting 1: stop all channel.the current transmission is stopped.the start bits of all channels are cleared in the non-priority mode, the time interval between two COUNTP transmission. Take the system clock as the criterion to avoid AXIDMA long-term use of the bus. stop status 0: not finish 1: finish the channel number of the final transmission 0000: channel 0 just finished the transmission 0001: channel 1 just finished the transmission 0010: channel 2 just finished the transmission 1011: channel 11 just finished the transmission others: nonentity 0 1 channel 11 interrupts state 0: the channel 11 has not been interrupted, or the interrupt bit has been cleared 1: channel 11 is interrupted channel 10 interrupts state 0: the channel 10 has not been interrupted, or the interrupt bit has been cleared 1: channel 10 is interrupted channel 9 interrupts state 0: the channel 9 has not been interrupted, or the interrupt bit has been cleared 1: channel 9 is interrupted channel 8 interrupts state 0: the channel 8 has not been interrupted, or the interrupt bit has been cleared 1: channel 8 is interrupted channel 7 interrupts state 0: the channel 7 has not been interrupted, or the interrupt bit has been cleared 1: channel 7 is interrupted channel 6 interrupts state 0: the channel 6 has not been interrupted, or the interrupt bit has been cleared 1: channel 6 is interrupted channel 5 interrupts state 0: the channel 5 has not been interrupted, or the interrupt bit has been cleared 1: channel 5 is interrupted channel 4 interrupts state 0: the channel 4 has not been interrupted, or the interrupt bit has been cleared 1: channel 4 is interrupted channel 3 interrupts state 0: the channel 3 has not been interrupted, or the interrupt bit has been cleared 1: channel 3 is interrupted channel 2 interrupts state 0: the channel 2 has not been interrupted, or the interrupt bit has been cleared 1: channel 2 is interrupted channel 1 interrupts state 0: the channel 1 has not been interrupted, or the interrupt bit has been cleared 1: channel 1 is interrupted channel 0 interrupts state 0: the channel 0 has not been interrupted, or the interrupt bit has been cleared 1: channel 0 is interrupted state of IRQ 23 generate requests of moving data 0: IRQ 23 does not generate requests of moving data 1: IRQ 23 generate requests of moving data state of IRQ 22 generate requests of moving data 0: IRQ 22 does not generate requests of moving data 1: IRQ 22 generate requests of moving data state of IRQ 21 generate requests of moving data 0: IRQ 21 does not generate requests of moving data 1: IRQ 21 generate requests of moving data state of IRQ 20 generate requests of moving data 0: IRQ 20 does not generate requests of moving data 1: IRQ 20 generate requests of moving data state of IRQ 19 generate requests of moving data 0: IRQ 19 does not generate requests of moving data 1: IRQ 19 generate requests of moving data state of IRQ 18 generate requests of moving data 0: IRQ 18 does not generate requests of moving data 1: IRQ 18 generate requests of moving data state of IRQ 17 generate requests of moving data 0: IRQ 17 does not generate requests of moving data 1: IRQ 17 generate requests of moving data state of IRQ 16 generate requests of moving data 0: IRQ 16 does not generate requests of moving data 1: IRQ 16 generate requests of moving data state of IRQ 15 generate requests of moving data 0: IRQ 15 does not generate requests of moving data 1: IRQ 15 generate requests of moving data state of IRQ 14 generate requests of moving data 0: IRQ 14 does not generate requests of moving data 1: IRQ 14 generate requests of moving data state of IRQ 13 generate requests of moving data 0: IRQ 13 does not generate requests of moving data 1: IRQ 13 generate requests of moving data state of IRQ 12 generate requests of moving data 0: IRQ 12 does not generate requests of moving data 1: IRQ 12 generate requests of moving data state of IRQ 11 generate requests of moving data 0: IRQ 11 does not generate requests of moving data 1: IRQ 11 generate requests of moving data state of IRQ 10 generate requests of moving data 0: IRQ 10 does not generate requests of moving data 1: IRQ 10 generate requests of moving data state of IRQ 9 generate requests of moving data 0: IRQ 9 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 8 generate requests of moving data 0: IRQ 8 does not generate requests of moving data 1: IRQ 8 generate requests of moving data state of IRQ 7 generate requests of moving data 0: IRQ 7 does not generate requests of moving data 1: IRQ 7 generate requests of moving data state of IRQ 6 generate requests of moving data 0: IRQ 6 does not generate requests of moving data 1: IRQ 6 generate requests of moving data state of IRQ 5 generate requests of moving data 0: IRQ 5 does not generate requests of moving data 1: IRQ 5 generate requests of moving data state of IRQ 4 generate requests of moving data 0: IRQ 4 does not generate requests of moving data 1: IRQ 4 generate requests of moving data state of IRQ 3 generate requests of moving data 0: IRQ 3 does not generate requests of moving data 1: IRQ 3 generate requests of moving data state of IRQ 2 generate requests of moving data 0: IRQ 2 does not generate requests of moving data 1: IRQ 2 generate requests of moving data state of IRQ 1 generate requests of moving data 0: IRQ 1 does not generate requests of moving data 1: IRQ 1 generate requests of moving data state of IRQ 0 generate requests of moving data 0: IRQ 0 does not generate requests of moving data 1: IRQ 0 generate requests of moving data state of ACK 23 generate requests of moving data 0: ACK 23 does not generate requests of moving data 1: ACK 23 generate requests of moving data state of ACK 22 generate requests of moving data 0: ACK 22 does not generate requests of moving data 1: ACK 22 generate requests of moving data state of ACK 21 generate requests of moving data 0: ACK 21 does not generate requests of moving data 1: ACK 21 generate requests of moving data state of ACK 20 generate requests of moving data 0: ACK 20 does not generate requests of moving data 1: ACK 20 generate requests of moving data state of ACK 19 generate requests of moving data 0: ACK 19 does not generate requests of moving data 1: ACK 19 generate requests of moving data state of ACK 18 generate requests of moving data 0: ACK 18 does not generate requests of moving data 1: ACK 18 generate requests of moving data state of ACK 17 generate requests of moving data 0: ACK 17 does not generate requests of moving data 1: ACK 17 generate requests of moving data state of ACK 16 generate requests of moving data 0: ACK 16 does not generate requests of moving data 1: ACK 16 generate requests of moving data state of ACK 15 generate requests of moving data 0: ACK 15 does not generate requests of moving data 1: ACK 15 generate requests of moving data state of ACK 14 generate requests of moving data 0: ACK 14 does not generate requests of moving data 1: ACK 14 generate requests of moving data state of ACK 13 generate requests of moving data 0: ACK 13 does not generate requests of moving data 1: ACK 13 generate requests of moving data state of ACK 12 generate requests of moving data 0: ACK 12 does not generate requests of moving data 1: ACK 12 generate requests of moving data state of ACK 11 generate requests of moving data 0: ACK 11 does not generate requests of moving data 1: ACK 11 generate requests of moving data state of ACK 10 generate requests of moving data 0: ACK 10 does not generate requests of moving data 1: ACK 10 generate requests of moving data state of ACK 9 generate requests of moving data 0: ACK 9 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 8 generate requests of moving data 0: ACK 8 does not generate requests of moving data 1: ACK 8 generate requests of moving data state of ACK 7 generate requests of moving data 0: ACK 7 does not generate requests of moving data 1: ACK 7 generate requests of moving data state of ACK 6 generate requests of moving data 0: ACK 6 does not generate requests of moving data 1: ACK 6 generate requests of moving data state of ACK 5 generate requests of moving data 0: ACK 5 does not generate requests of moving data 1: ACK 5 generate requests of moving data state of ACK 4 generate requests of moving data 0: ACK 4 does not generate requests of moving data 1: ACK 4 generate requests of moving data state of ACK 3 generate requests of moving data 0: ACK 3 does not generate requests of moving data 1: ACK 3 generate requests of moving data state of ACK 2 generate requests of moving data 0: ACK 2 does not generate requests of moving data 1: ACK 2 generate requests of moving data state of ACK 1 generate requests of moving data 0: ACK 1 does not generate requests of moving data 1: ACK 1 generate requests of moving data state of ACK 0 generate requests of moving data 0: ACK 0 does not generate requests of moving data 1: ACK 0 generate requests of moving data channel 11 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 10 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 9 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 8 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 7 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 6 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 5 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 4 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 3 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 2 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 1 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption channel 0 interrupt allocation bit 0: the interrupt of the channel is output to the dma_irq interruption 1: the interrupt of the channel is output to the dma_irq1 interruption response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel response error interrupt enable 0disable 1enable security visit 0security 1unsecurity after moving a COUNTP,the DADDR is automatically returned to the original destination addr 0: the destination addr does not automatically ring back 1: the destination addr automatically ring back after moving a COUNTP,the SADDR is automatically returned to initial source addr 0: the source addr does not automatically ring back 1: the source addr automatically ring back the length of moving data in one interrupt in interrupted mode 0: move a countp 1: move all count mandatory transmission control bit 0: a transmission is not mandatory in interrupted mode. Or after seting, automatically cleared. 1: force a transmission without interruption in interrupted mode. fixed destination addr control bit 0: destination addr can be incremented by different data types during transmission 1: the destination addr is fixed during transmission fixed source addr control bit 0: source addr can be incremented by different data types during transmission 1: the source add is fixed during transmission control bit of each transmission interruption 0: each transmission does not produce an interrupt signal 1: each transmission prodece an interrupt signal control bit of whole transmission interruption 0: whole transmission does not produce an interrupt signal 1: whole transmission prodece an interrupt signal control bit of synchronous interrupt trigger mode 0: this channel is in normal transmission mode 1: this channel is in sync interrupt trigger mode data types 00: Byte (8 bits) 01: Half Word (16 bits) 10: Word (32 bits) 11: DWord (64 bits) start control bit 0: stop the transmission of this channel 1: start the transmission of this channel this channel corresponds to the ACK signal that is triggered 00000: ACK0 00001: ACK1 00010: ACK2 10111: ACK23 the source of interrupt trigger for this channel 00000: IRQ0 trigger transmission 00001: IRQ1 trigger transmission 00010: IRQ2 trigger transmission 01111: IRQ15 trigger transmission 10111: IRQ23trigger transmission the source addr of this channel the destination addr of this channel The total length of the transmitted data is measured in byte the data length per transmission is measured in byte bit type is changed from w1c to rc. response error interrupt flag 0unset 1set bit type is changed from w1c to rc. response error status 0unset 1set bit type is changed from w1c to rc. data linked list is paused 0: not paused 1: paused bit type is changed from w1c to rc. the linked list is completed 0: not completed 1: completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. COUNT transmission completion indication 0: COUNT is not completed 1: COUNT is completed bit type is changed from w1c to rc. scatter-gather pause bit type is changed from w1c to rc. the number of scatter-gather transfers completed 0x0000: 0 0xFFFF: 65535 times bit type is changed from w1c to rc. scatter-gather transmission completion 0: scatter-gather is not completed 1: scatter-gather is completed bit type is changed from w1c to rc. COUNTP transmission completion indication 0: COUNTP is not completed 1: COUNTP is completed bit type is changed from w1c to rc. the whole transmission completion indication 0: the whole transmission is not completed 1: the whole transmission is completed bit type is changed from w1c to rc. the channel runs state 0: IDLE 1: TRANS first addr of the structural body scatter-gather transmission frequency 0x0: unlimited limit 0xFFFF: 65535 times linked table read control 0: after the data is moved,the linked list isread and no descriptor_req are required 1: descriptor_req is needed to read the linked list scatter-gather pause interrupt enable 0: disable 1: enable scatter-gather complete interrupt enable 0: disable 1: enable bit type is changed from w1c to rc. scatter-gather function enable 0: disable 1: enable channel runs position 0: the running bit of the channel does not change 1: set the running bit of the channel clear the running bit of channel 0: the running bit of the channel does not change 1: clear the running bit of the channel reserved fields of DFT 1: HW insert zeros for imag part, 0: SW provide zeros 1: mask DMA out intr; 0:not mask DMA out intr 1: mask Calc intr; 0:not mask Calc intr 1: mask DMA in intr; 0:not mask DMA in intr 1:iq swap; 0:iq not swap 1:fft; 0:ifft force clock gating enable base address of ram in dft index of DFT N length bit type is changed from w1s to rs. write clear pulse for DFT error status, read in err status bit type is changed from w1s to rs. write clear pulse for DFT dma out interrupts, read in dma out interrupt source before mask bit type is changed from w1s to rs. write clear pulse for DFT calc interrupts, read in calc interrupt source before mask bit type is changed from w1s to rs. write clear pulse for DFT dma in interrupts, read in dma in interrupt source before mask bit type is changed from w1s to rs. write start trigger pulse of DFT, which will do dma rx, and read in dma rx request status 1: interrupt source in dma out; 0 : no interrupt, read interrupt after mask 1: interrupt source in calc; 0 : no interrupt, read interrupt after mask 1: interrupt source in dma in; 0 : no interrupt, read interrupt after mask DFT error status report upon interrupt gen, cleared via DFT_err_stat_clr set DFT state machine status report Monitor 0 1 :BUS Monitor 0 1 BUSY 1 0 RBUSY 1 0 WBUSY 1 0 1 0 1 0 1 0 1 0 1 0 0 1 MON_M0_ADDR_WIDIDDDR0x0-0x1fff_ffffDDR , PCLK MON_NUM_EN,MASTER MASTER0 0 1 0 1 0 1 LOCK 0 1 bit type is changed from w1c to rc. 0 1 bit type is changed from w1c to rc. MASTER0 0 1 bit type is changed from w1c to rc. MASTER4 0 1 bit type is changed from w1c to rc. MASTER4 0 1 bit type is changed from w1c to rc. MASTER3 0 1 bit type is changed from w1c to rc. MASTER3 0 1 bit type is changed from w1c to rc. MASTER2 0 1 bit type is changed from w1c to rc. MASTER2 0 1 bit type is changed from w1c to rc. MASTER1 0 1 bit type is changed from w1c to rc. MASTER1 0 1 bit type is changed from w1c to rc. MASTER0 0 1 bit type is changed from w1c to rc. MASTER0 0 1 bit type is changed from w1c to rc. 0 1 bit type is changed from w1c to rc. MASTER4 0 1 bit type is changed from w1c to rc. MASTER3 0 1 bit type is changed from w1c to rc. MASTER2 0 1 bit type is changed from w1c to rc. MASTER1 0 1 bit type is changed from w1c to rc. MASTER0 0 1 ID : MON_START_ADDR, MON_END_ADDRMASTER0;MASTER0,ADDR_INT, 0 -10xFF0x100 0 -10xFF0x100 0 0 -10xFF0x100 1 -10xFF0x100 1 -10xFF0x100 1 1 -10xFF0x100 2 -10xFF0x100 2 -10xFF0x100 2 2 -10xFF0x100 3 -10xFF0x100 3 -10xFF0x100 3 3 -10xFF0x100 4 -10xFF0x100 4 -10xFF0x100 4 4 -10xFF0x100 0 1 0 1 0000 00011/2 00101/4 00111/8 01001/16 01011/32 01101/64 01111/128 10001/256 0 00 10 0 1Load 0Load 1Load0 0 1 1STARTTR0 20xCCCCSTARTPROT_EN 3STARTARSTART 0xCCCCWD_CONFWD_LOAD12 WD_CONF[9]1 32bit 1 32bit 1 32bit 32bit 0xAAAA0x5555 0xAAAA0x4444 0xBBBB 0 1 f= FuncClk/(DIV+1) WATCHDOG26MhzDIVWD_DIV_COUNT bit type is changed from w1c to rc. ACK RIMCS CQIMCS PUSCHPUSCHCRCbit PUSCHPUSCHCRCbit 00BPSK 01QPSK 1016QAM 1164QAM PUSCH PUSCH RU PUSCHCAT1/CATM 1PUSCH DATA CAT-NB1RU PUSCHCAT1/CATM1 PUSCH DATACAT-NB 1RU CQI31~0 CQI31~0 CQI CQI65 CQI64 RI RI ACK4 ACK 0FDDTDDHARQ-ACK 1TDDHARQ-ACK TDD HARQ-ACK PUCCH 000~010RESERVED 0112 1002a 1012b 110~111RESERVED U U CV GOLD 1PUSCHULDFT 0PUSCHULDFT 00PUSCH 01PUCCH UCI 10PRACH 11NPUSCH1NPUSCH2PUSCH IP FUNC_SELPUSCH UCIPUCCH UCIFUNC_SEL00PUSCH UCIFUNC_SEL01PUCCH UCI 0UCI 1UCI PUSCH_BUFFERMEM 00PUSCH_BUF1 01PUSCH_BUF2 10PUSCH_BUF3 11PRACH_BUF 0PUSCH_BUFFER 1PUSCH_BUFFER PRACHZC 0ZC139 1ZC839 0PUSCHCRCByte 1PUSCHCRCByte 0LTE 1LTE 0PUSCH 1PUSCH 0PUSCH 1PUSCH 0PUSCHTurbo 1PUSCHTurbo 0PUSCHCRC 1PUSCHCRC 0LTE 1LTE bit type is changed from rw1c to rc. 0 1 PUCCH format2/2a/2b UCI Schedule SIB1 BR R13PBML PHICH resourcePBML PHICH durationPBML 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 Ng 01/6 11/2 21 32 1~:9tm1,tm2,,tm9 TDD0~9 9 0~66 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 01 12 24 32 CP 0CP 1CP FDDTDD 0TDD 1FDD ID0~503 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 Ng 01/6 11/2 21 32 1~:9tm1,tm2,,tm9 TDD0~99 0~66 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 01 12 24 32 CP 0CP 1CP FDDTDD 0TDD 1FDD MBSFN ID0~255 ID0~503 Temp-C-RNTI RA_RNTI SPS_RNTI C_RNTI TPC-PUCSH-RNTI TPC-PUCCH-RNTI G_RNTI 2PRBCSI-RS CSIRS_GROUP1 1PRBCSI-RS 011PRBRE#0 RE#1101RE#0 CSI-RS CSI-RSOFDM1PDSCHNorm-CP2430OFDM#5689101213Ext-CP2429OFDM#45781011Norm-CP241OFDM#510OFDM#51CSI-RS 4PRBCSI-RSCSIRS_GROUP1 3PRBCSI-RSCSIRS_GROUP1 PMI (codebookSubsetRestriction) 0PMIbit 1PMIbit BIT Bit0:1OFDMCFI Bit1:2OFDMCFI Bit2:3OFDMCFI Bit3:4OFDMCFI 0 1 HIOFDM0~3 PHICH1 0 1 PHICH10~7 PHICH10~99 PHICH0 0 1 PHICH00~7 PHICH00~99 UEDCImax57 UEDCImax57 COMMDCImax57 COMMDCImax57 DCILEN 0 1 PUSCH 0DCI0 1DCI0C CSI 01 12 0 1 SRS 0DCISRS_REQ 1DCISRS_REQ PDCCH 0:1 1:2 2:3 3:4 78 PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 0 1 0~3 max2216 0 1 0~3 max2216 0~65535 :0~1023 :0~9 0~65535 :0~1023 :0~9 SC-N-RNTI 0 1 SC-RNTI 0 1 G-RNTI 0 1 TPC-PUCCH-RNTI 0 1 TPC-PUSCH-RNTI 0 1 Temp-C-RNTI 0 1 SPS-C-RNTI 0 1 C-RNTI 0 1 RA-RNTI 0 1 P-RNTI 0 1 SI-RNTI 0 1 SC-RNTI 0 1 G-RNTI 0 1 Temp-C-RNTI 0 1 SPS-C-RNTI 0 1 C-RNTI 0 1 RA-RNTI 0 1 P-RNTI 0 1 SI-RNTI 0 1 SINR DMA 0 1 PMI DMA 0 1 SINR 0 1 PMI 0 1 PDCCH 0 1 PBCH 0 1 MBMS 0MBMS 1MBMS CTRL QFQT 01 12 23 PBCH 0 1 SINR 0 1 PMI 0 1 HI 0 1 PDCCH 0 1 PBCH 0 1 PDSCH DMA 0 1 PDSCH 0 1 DATA QFQT 01 12 23 CSIRS 0 1 SIHQBUF 0HQBUF0 1HQBUF1 PDSCH 0 1 PDS 0 1 PDSCH 0 1 LDTC 0 1 LDTC 0 1 bit type is changed from rw1c to rc. DCI 0DCI 1DCI bit type is changed from rw1c to rc. MIB 0MIB 1MIB bit type is changed from rw1c to rc. SINR 0 1 bit type is changed from rw1c to rc. PMI 0 1 bit type is changed from rw1c to rc. PDCCH 0 1 bit type is changed from rw1c to rc. PBCH 0 1 bit type is changed from rw1c to rc. PAGINGCRC 0 1 bit type is changed from rw1c to rc. PAGINGCRC 0CRC 1CRC bit type is changed from rw1c to rc. SICRC 0 1 bit type is changed from rw1c to rc. SICRC 0CRC 1CRC bit type is changed from rw1c to rc. PDSCH CRC 0 1 bit type is changed from rw1c to rc. PDSCH CRC 0CRC 1CRC bit type is changed from rw1c to rc. PDSCH 0 1 FHdata 0FH0 1FH1 FHctrl 0FH0 1FH1 DSCHOUT 0DSCHOUT0 1DSCHOUT1 FFTBUF 0FFTBUF0 1FFTBUF1 PDCCH GQ 0Q15 1Q16 7Q22 HQ 0CC 1IR HQ BUF 04bit 16bit SDGnoise 0noise 1GM PMI/PWR 0 1 CTCG 0OFDM4(OFDM4)CRS 1OFDM8(OFDM8)CRS CRS G 01PRB 12PRB CRS36 PRB 03PRB 16PRB UE RSPRB1,3 0 1 16bit10bit 0 1 16bit10bit 0x015~6 0x114~5 0x213~4 0x312~3 0x411~2 0x510~1 0x69~0 reserved 16bit 0x028~13 0x127~12 0x226~11 0x325~10 0x424~9 0x523~8 0x622~7 0x721~6 0x820~5 0x919~4 0xa18~3 0xb17~2 0xc16~1 0xd15~0 Reserved 0x025~10 0x124~9 0x223~8 0x322~7 0x421~6 0x520~5 0x619~4 0x718~3 0x817~2 0x916~1 0xa15~0 0.5msbitmapbitprbbit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbit[99:96]prbbit 0prb 1prb 0.5msbitmapbit[31:0]prbbit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbit[99:96]prbbit 0prb 1prb 0.5msbitmapbit[31:0]prbbit 0prb 1prb 0.5msbitmapbit[64:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbitprbbit 0prb 1prb 0.5msbitmapbit[31:0]prbbit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbit[99:96]prbbit 0prb 1prb 0.5msbitmapbit[31:0]prbbit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbit[99:96]prbbit 0prb 1prb 0.5msbitmapbit[31:0]prbbit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbit[95:64]prbbit 0prb 1prb 0.5msbitmapbit[99:96]prbbit 0prb 1prb 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 25 1CRS 1CRS 1CRSAGC 1CRSAGC PDCCH 0 1 PBCH 0 1 1 0 PDSCH 0 1 0 2 1 4 3 OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata 32Q300~7fff_ffff AGC PDCCHPBCH 32Q300~7fff_ffff AGC PDCCHINDX PBCHINDX3 PBCHINDX2 PBCHINDX1 PBCHINDX0 INDX7 INDX6 INDX5 INDX4 INDX3 INDX2 INDX1 INDX0 INDX15 INDX14 INDX13 INDX12 INDX11 INDX10 INDX9 INDX8 INDX23 INDX22 INDX21 INDX20 INDX19 INDX18 INDX17 INDX16 INDX31 INDX30 INDX29 INDX28 INDX27 INDX26 INDX25 INDX24 INDX34 INDX33 INDX32 bit type is changed from rw1c to rc. 15HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 14HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 13HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 12HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 11HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 10HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 9HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 8HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 7HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 6HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 5HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 4HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 3HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 2HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 1HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 0HARQBUFFER 0: 1: 7HARQBUFFER:0~15 6HARQBUFFER:0~15 5HARQBUFFER:0~15 4HARQBUFFER:0~15 3HARQBUFFER:0~15 2HARQBUFFER:0~15 1HARQBUFFER:0~15 0HARQBUFFER:0~15 15HARQBUFFER:0~15 14HARQBUFFER:0~15 13HARQBUFFER:0~15 12HARQBUFFER:0~15 11HARQBUFFER:0~15 10HARQBUFFER:0~15 9HARQBUFFER:0~15 8HARQBUFFER:0~15 64QAM 02 1 16QAM 02 1 QPSK 02 1 64QAM 0 1 16QAM 0 1 QPSK 0 1 2 1 1 90~8 PAG-1 SI-1 PDS-1 PDS-1 0 1 CRC 0CRC16 1CRC24A DMA 0 1 0 1 VIT 0:1 1:2 2:3 3:4 PDCCHfalse alarm PDCCHfalse alarm(U8Q7) VIT VIT 0 1 bit type is changed from rw1c to rc. VIT CRCCRC 0 1 bit type is changed from rw1c to rc. VIT CRC 0 1 bit type is changed from rw1c to rc. PBCH 0 1 DCI false alarm0 DCI false alarm CFI 1~41.4M1 HI1 HI0 PDSCH 15 PDSCH 14 PDSCH 13 PDSCH 12 PDSCH 11 PDSCH 10 PDSCH 9 PDSCH 8 PDSCH 7 PDSCH 6 PDSCH 5 PDSCH 4 PDSCH 3 PDSCH 2 PDSCH 1 PDSCH 0 SI1 SI0 PBCH 2 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 1 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 MultiCell 0SingalCell 1MultiCell ABIS 0 1DLFFT ABIS 0 1 ABISSD PDSCH 0 1 ABISSD MPDCCH 0 1 ABISSD PBCH 0 1 000 011 102 0 2 001port 012port 104port 1port 1 001port 012port 104port 1port 2 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 1 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 2 CELL ID 1 CELL ID 1TS 2TS ABIS31+2 ABIS22 ABIS11 2 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 1 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 ABIS 0 1DLFFT ABIS 0 1 ABISSD PDSCH 0 1 ABISSD MPDCCH 0 1 ABISSD PBCH 0 1 000 011 102 0 2 001port 012port 104port 1port 2 001port 012port 104port 1port 2 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 1 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 2 CELL ID 1 CELL ID 1TS 2TS ABIS31+2 ABIS22 ABIS11 REIS 0 1 REISNUM REIS1 REIS1RE20M1200RE REIS0 REIS0RE20M1200RE REIS3 REIS3RE20M1200RE REIS2 REIS2RE20M1200RE REIS5 REIS5RE20M1200RE REIS4 REIS4RE20M1200RE REIS7 REIS7RE20M1200RE REIS6 REIS6RE20M1200RE 2ABISPORT 0port0 1port1 RBIS 0 1 RBISSD PDSCH 0 1 RBISSD MPDCCH 0 1 RBISSD PBCH 0 1 RBIS 0 1 RBIS 01 12 23 34 45 RBIS RBIS RBIS0~99 RBIS0~99 RBIS0~99 RBIS0~99 RBIS0~99 RBIS RBIS PBML 0 1 LLR LLR LLR 0~255 0~65535 0~1023 0~9 0~65535 0~1023 0~9 CB0HARQIN MEM0 CB0HARQIN MEM0 CB0 CB0HARQIN MEM1 CB1HARQIN MEM0 CB1HARQIN MEM0 CB1 CB1HARQIN MEM1 SICB1HARQIN MEM0 SICB1HARQIN MEM0 SICB1 SICB1HARQIN MEM1 PAGINGCB1HARQIN MEM0 PAGINGCB1HARQIN MEM0 PAGINGCB1 PAGINGCB1HARQIN MEM1 ABIS31+2 ABIS22 ABIS11 ABIS31+2 ABIS22 ABIS11 1TS 2TS TS DCI032 DCI032 DCI DCI false alarm0 DCI false alarm 00 11 DCI1A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI0 1:DCI1 2:DCI1A 3:DCI1B 4:DCI1C 5:DCI1D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI0C DCI2/DCI2A/DCI2B/DCI2C2 01 12 DCI0 DCI0CQI DCI2/DCI2ATBCW 0 1 SRS SRQDCI0DCI1ADCI2B TDDDCI2C TDD DCI1D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI132 DCI132 DCI DCI false alarm0 DCI false alarm 00 11 DCI1A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI1 1:DCI1 2:DCI1A 3:DCI1B 4:DCI1C 5:DCI1D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI1C DCI2/DCI2A/DCI2B/DCI2C2 01 12 DCI1 DCI1CQI DCI2/DCI2ATBCW 0 1 SRS SRQDCI1DCI1ADCI2B TDDDCI2C TDD DCI1D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI232 DCI232 DCI DCI false alarm0 DCI false alarm 00 11 DCI2A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI2 1:DCI2 2:DCI2A 3:DCI2B 4:DCI2C 5:DCI2D 6:DCI2 7:DCI2A 8:DCI2B 9:DCI2C 10:DCI3/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI2C DCI2/DCI2A/DCI2B/DCI2C2 01 12 DCI2 DCI2CQI DCI2/DCI2ATBCW 0 1 SRS SRQDCI2DCI2ADCI2B TDDDCI2C TDD DCI2D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI332 DCI332 DCI DCI false alarm0 DCI false alarm 00 11 DCI3A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI3 1:DCI3 2:DCI3A 3:DCI3B 4:DCI3C 5:DCI3D 6:DCI3 7:DCI3A 8:DCI3B 9:DCI3C 10:DCI3/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI3C DCI3/DCI3A/DCI3B/DCI3C2 01 12 DCI3 DCI3CQI DCI3/DCI3ATBCW 0 1 SRS SRQDCI3DCI3ADCI3B TDDDCI3C TDD DCI3D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI432 DCI432 DCI DCI false alarm0 DCI false alarm 00 11 DCI4A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI4 1:DCI4 2:DCI4A 3:DCI4B 4:DCI4C 5:DCI4D 6:DCI4 7:DCI4A 8:DCI4B 9:DCI4C 10:DCI4/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI4C DCI4/DCI4A/DCI4B/DCI4C2 01 12 DCI4 DCI4CQI DCI4/DCI4ATBCW 0 1 SRS SRQDCI4DCI4ADCI4B TDDDCI4C TDD DCI4D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI532 DCI532 DCI DCI false alarm0 DCI false alarm 00 11 DCI5A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI5 1:DCI5 2:DCI5A 3:DCI5B 4:DCI5C 5:DCI5D 6:DCI5 7:DCI5A 8:DCI5B 9:DCI5C 10:DCI5/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI5C DCI5/DCI5A/DCI5B/DCI5C2 01 12 DCI5 DCI5CQI DCI5/DCI5ATBCW 0 1 SRS SRQDCI5DCI5ADCI5B TDDDCI5C TDD DCI5D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI632 DCI632 DCI DCI false alarm0 DCI false alarm 00 11 DCI6A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI6 1:DCI6 2:DCI6A 3:DCI6B 4:DCI6C 5:DCI6D 6:DCI6 7:DCI6A 8:DCI6B 9:DCI6C 10:DCI6/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI6C DCI6/DCI6A/DCI6B/DCI6C2 01 12 DCI6 DCI6CQI DCI6/DCI6ATBCW 0 1 SRS SRQDCI6DCI6ADCI6B TDDDCI6C TDD DCI6D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb DCI732 DCI732 DCI DCI false alarm0 DCI false alarm 00 11 DCI7A 0ORDER 1ORDER SPS-C-RNTI 0 1 2 3 DCI 0:DCI7 1:DCI7 2:DCI7A 3:DCI7B 4:DCI7C 5:DCI7D 6:DCI7 7:DCI7A 8:DCI7B 9:DCI7C 10:DCI7/3A DCI RNTI 0RNTI0SI-RNTI 1RNTI1P-RNTI 2RNTI2RA-RNTI 3RNTI3C-RNTI 4RNTI4SPS-RNTI 5RNTI5T-RNTI 6RNTI6TPCS-RNTI 7RNTI7TPCC-RNTI 8RNTI8G-RNTI 9RNTI9SC-RNTI 10RNTI10SC-N-RNTI DCICOMMUE 0 1UE DCI(index:0~23) DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) PMIDCIPMI 0DCIPMI 1PMI HARQ:0~15 tx2:0~3tx4:0~15 0 1 2 3PORT7 4PORT8 5PORT5 0 1 Nscid(UE)0~1 0~3 0:QPSK 1:16QAM 2:64QAM max10296 DCI7C DCI7/DCI7A/DCI7B/DCI7C2 01 12 DCI7 DCI7CQI DCI7/DCI7ATBCW 0 1 SRS SRQDCI7DCI7ADCI7B TDDDCI7C TDD DCI7D POWER OFFSET DAI 0TYPE0 1TYPE1 Type0 Type0/Type1RBA 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb 0.5msbitmapbit[63:32]prbbit 0prb 1prb 0.5msbitmapbitprb[63:32]bit 0prb 1prb 0.5msbitmapbitprb[95:64]bit 0prb 1prb 0.5msbitmapbitprb[99:96]bit 0prb 1prb MIB0 MIB MIB1 MIB MIB2 MIB MIB3 MIB Schedule SIB1 BR R13PBML PHICH resourcePBML PHICH durationPBML PBCH 0PBCH 1PBCH CATM1,2,6,9 TDD 099 066 0: 1.4MHZ 1: 3MHZ 2: 5MHZ 310MHZ 4: 15MHZ 5: 20MHZ 6~75 0 1 1 2 2 4 3 2 CP 0 CP 1 CP FDDTDD 0 TDD 1 FDD ID0503 G_RNTI Temp-C-RNTI RA-RNTI SPS-C-RNTI C-RNTI TPC-PUCSH-RNTI TPC-PUCCH-RNTI MPDCCH1PRB 0 2 1 4 2 6 MPDCCH1RBA MPDCCH1ID 0503 MPDCCH1 0(LOC) 1(DIS) 2PRBCSI-RSCSIRS_GROUP1 1PRBCSI-RS011PRBRE#0RE#1101RE#0CSI-RS 4PRBCSI-RSCSIRS_GROUP1 3PRBCSI-RSCSIRS_GROUP1 PMIcsi-NumrepetitionCE-R13: 0: 1 1: 2 2: 4 3: 8 4: 16 5: 32 PMI 0 PMIbit 1 PMIbit PBCH 0 1 PBCH 0FDD90TDD05 10PBCH PBCH 0 1 1 2 PBCH2TDD03 0 1 2 3 PBCH1(TDD,FDD)03 0 1 2 3 PBCH(TDD/FDD)03 0 1 2 3 MPDCCHFHBUNDbit3PRB3PRB Bit2013PRBBUND03PRBBUND Bit2113PRBBUND03PRBBUND 0 1 UL TBSIZE 0max1000 1max2984 PDSCH_PUSCH 0 1 FDD HARQ 08 110 HARQ ACK 0 1 0harq 1harq MPDCCH DCI 0 1 MPDCCH SRSRREQ 0SRSRREQ 1SRSRREQ MPDCCH COMM 0:1 1:2 2:3 3:4 MPDCCH SET 0:1 1:2 2:3 3:4 MPDCCH COMM(1256) 0:1 1:2 2:4 3:8 4:16 8:256 MPDCCH SET1(1~256) 0:1 1:2 2:4 3:8 4:16 8:256 MPDCCH COMM DCImax38 MPDCCH SET1 COMM DCImax38 MPDCCH SET1 UESPEC DCImax38 MPDCCH SET10255 tx2:03 tx4:015 0 1 2 3PORT7 4PORT8 HARQ015 NscidUE01 03 0:QPSK 1:16QAM max1000 RB16 RB05 AGC 065535 01023 09 C-RNTI 0 1 SI-RNTISIB1SIB 0SIB1SIB 1SIB1 PDSCHC-RNTSPS-C-RNTI 0C-RNTI 1SPS-RNTI SI-RNTI 0 1 G-RNTI 0 1 SC-RNTI 0 1 Temp-C-RNTI 0 1 RA-RNTI 0 1 P-RNTI 0 1 TPC-PUSCH-RNTI 0 1 TPC-PUCCH-RNTI 0 1 SPS-C-RNTI 0 1 C-RNTI 0 1 PDSCH/PBCH 0 1PDSCH /PBCH MPDCCH 0 1MPDCCH PDSCH/PBCHPMI 0 1 MPDCCH(PMI) 0 1 CFI 0:1 1:2 2:3 3:4 MPDCCH/PDSCHSIB 0 1 PDSCH0 000 100 CSI RS 0 1 0 1PDSCH/MPDCCH/PBCH 0 1 QFQT 0Qtable0 1Qtable1 2Qtable2 0CEA 1CEB :015 MPDCCH SET1 0 1 PDSCH URS 0 1 PDSCH CRS/PMI 0 1 0 1 MPDCCH SET1 0 1 PMI 0 1 PDSCH 0 1 MPDCCH SET1 0 1 PBCH 0 1 PMI 0 1 PDSCH 0 1 MPDCCH 0 1 PBCH 0 1 LDTC 0 1 bit type is changed from rw1c to rc. 0LDTC 1LDTC bit type is changed from rw1c to rc. PMI 0PMI 1PMI bit type is changed from rw1c to rc. PDSCH 0PDSCH 1PDSCH bit type is changed from rw1c to rc. MPDCCH 0MPDCCH 1PBCH bit type is changed from rw1c to rc. PBCH 0PBCH 1PBCH bit type is changed from rw1c to rc. 0 1 COEFF DATMEM RSMEM0~4 DCI 0 1 DCI Ri 0DCI 1DCIRi DCI2 0DCI 1DCI2 DCI 0DCI 1DCI MIB 0MIB 1MIB PDSCH CRC 0 1 PDSCH CRC 0CRC 1CRC 065535 01023 09 MPDCCH CNT HARQ:0~15 RNTI 0RNTI0C-RNTI 1RNTI1SPS-C-RNTI 2RNTI2TPC-PDCCH-RNTI 3RNTI3TPC-PDSCH-RNTI 4RNTI4P-RNTI 5RNTI5RA-RNTI 6RNTI6Temp-C-RNTI 7RNTI7SC-RNTI 8RNTI7G-RNTI 9RNTI7SI-RNTI C-RNTI 0 1 SI-RNTISIB1SIB 0SIB1SIB 1SIB1 MIB 0 12 24 MPDCCH SET10255 PDSCH UE 0 1 MPDCCH 0MPDCCHextendCPMPDCCH 1MPDCCHnormalCP FIR/IIR 0FIR 1IIR FIR 0:1 1:2 2:3 3:4 IIRHLS FIRHLS FIR1HLS IIR/FIR0HLS FIR2HLS FIR1HLS FIR0HLS FIR3HLS FIR2HLS FIR1HLS FIR0HLS UE RSPRB1,3 0:1 1:3 16bit10bit 0 1 16bit10bit 0x015~6 0x114~5 0x213~4 0x312~3 0x411~2 0x510~1 0x69~0 RESERVED 16bit 0x028~13 0x127~12 0x226~11 0x325~10 0x424~9 0x523~8 0x622~7 0x721~6 0x820~5 0x919~4 0xa18~3 0xb17~2 0xc16~1 0xd15~0 RESERVED 0x02510 0x1249 0x2238 0x3227 0x4216 0x5205 0x6194 0x7183 0x8172 0x9161 0xa150 PBCH 0 1 2 1 0 MPDCCH 0 1 2 1 0 PDSCH 0 1 0 2 1 4 3 OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata OFDMCELL RSdata 32Q3007fff_ffff AGC PDSCH(16~31bit) MPDCCH/PBCH(16~31bit) INDX3 INDX2 INDX1 INDX0 INDX11 INDX10 INDX9 INDX8 INDX7 INDX6 INDX5 INDX4 INDX19 INDX18 INDX17 INDX16 INDX15 INDX14 INDX13 INDX12 INDX9 INDX8 INDX7 INDX6 INDX5 INDX4 INDX3 INDX2 INDX1 INDX0 INDX19 INDX18 INDX17 INDX16 INDX15 INDX14 INDX13 INDX12 INDX11 INDX10 INDX32 INDX31 INDX30 INDX29 INDX28 INDX27 INDX26 INDX25 INDX24 INDX23 INDX22 INDX21 INDX20 INDX7 INDX6 INDX5 INDX4 INDX3 INDX2 INDX1 INDX0 INDX15 INDX14 INDX13 INDX12 INDX11 INDX10 INDX9 INDX8 INDX16 HARQ1280255 HARQ320255 HARQ6408191 HARQ1608191 MPDCCH m ECCEYpk4 MPDCCH m ECCEYpk3 MPDCCH m ECCEYpk2 MPDCCH m ECCEYpk1 MPDCCH m ECCEYpk0 MPDCCH m ECCEYpk9 MPDCCH m ECCEYpk8 MPDCCH m ECCEYpk7 MPDCCH m ECCEYpk6 MPDCCH m ECCEYpk5 bit type is changed from rw1c to rc. 7HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 6HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 5HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 4HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 3HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 2HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 1HARQBUFFER 0: 1: bit type is changed from rw1c to rc. 0HARQBUFFER 0: 1: 7HARQBUFFER:0~15 6HARQBUFFER:0~15 5HARQBUFFER:0~15 4HARQBUFFER:0~15 3HARQBUFFER:0~15 2HARQBUFFER:0~15 1HARQBUFFER:0~15 0HARQBUFFER:0~15 max1000 PDSCH PDSCH PDSCHmax4*2048-1 N 01 11.5 22 3 2.5 2 1 1 908 -1 VIT 0:1 1:2 2:3 3:4 DCI032 DCI032 0 1 2 3PORT7 4PORT8 00 11 PRB2+4DCIPRB 0:2PRB 1:4PRB 2:6PRB DCI 01 12 DCICOMMUE 0 1UE DCIRi 0R0 1R1 2R2 3R3 DCIPORTn0 Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 0PORT107 1PORT108 2PORT109 3PORT110 Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 0:107 1:109 Extended cyclic prefix 0:107 1:108 DCI(index:023) DCI RNTI 0RNTI0C-RNTI 1RNTI1SPS-C-RNTI 2RNTI2TPC-PDCCH-RNTI 3RNTI3TPC-PDSCH-RNTI 4RNTI4P-RNTI 5RNTI5RA-RNTI 6RNTI6Temp-C-RNTI 7RNTI7SC-RNTI 8RNTI8G-RNTI DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) tx2:03tx4:015 HARQ:015 Nscid(UE)01 03 0:QPSK 1:16QAM max2984 RB16 RB05 HARQ-ACK delay HARQ-ACK bundling flag SPS-C-RNTI 0 1 2 DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification DCI6-0A /DCI6-1ASRS DCI6-0ACSI DCI6-1A/DCI6-0A(TDD,uldl:16)DAI DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX DCI6-0A /DCI6-1A PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) MPDCCH DCI (03),Transport blocks in a bundle DCI2DI(direct indication) 0PAGING 1DI DCI6-1ADCI1-BPDCCH ORDER 0ORDER 1ORDER 0DCI 1 0 1 DCI 0:DCI6-1A 1:DCI6-1B 2:DCI6-0A 3:DCI6-0B 4:DCI3/3A 5:DCI2 015 DCI6-1APDSCH1tbsize DCIfalse alarm(vit) DCIfalse alarm0 DCI DCI132 DCI132 0 1 2 3PORT7 4PORT8 00 11 PRB2+4DCIPRB 0:2PRB 1:4PRB 2:6PRB DCI 01 12 DCICOMMUE 0 1UE DCIRi 0R0 1R1 2R2 3R3 DCIPORTn0 Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 0PORT107 1PORT108 2PORT109 3PORT110 Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 0:107 1:109 Extended cyclic prefix 0:107 1:108 DCI(index:023) DCI RNTI 0RNTI0C-RNTI 1RNTI1SPS-C-RNTI 2RNTI2TPC-PDCCH-RNTI 3RNTI3TPC-PDSCH-RNTI 4RNTI4P-RNTI 5RNTI5RA-RNTI 6RNTI6Temp-C-RNTI 7RNTI7SC-RNTI 8RNTI8G-RNTI DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) tx2:03tx4:015 HARQ:015 Nscid(UE)01 03 0:QPSK 1:16QAM max2984 RB16 RB05 HARQ-ACK delay HARQ-ACK bundling flag SPS-C-RNTI 0 1 2 DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification DCI6-0A /DCI6-1ASRS DCI6-0ACSI DCI6-1A/DCI6-0A(TDD,uldl:16)DAI DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX DCI6-0A /DCI6-1A PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) MPDCCH DCI (03),Transport blocks in a bundle DCI2DI(direct indication) 0PAGING 1DI DCI6-1ADCI1-BPDCCH ORDER 0ORDER 1ORDER 0DCI 1 0 1 DCI 0:DCI6-1A 1:DCI6-1B 2:DCI6-0A 3:DCI6-0B 4:DCI3/3A 5:DCI2 015 DCI6-1APDSCH1tbsize DCIfalse alarm(vit) DCIfalse alarm0 DCI DCI232 DCI232 0 1 2 3PORT7 4PORT8 00 11 PRB2+4DCIPRB 0:2PRB 1:4PRB 2:6PRB DCI 01 12 DCICOMMUE 0 1UE DCIRi 0R0 1R1 2R2 3R3 DCIPORTn0 Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 0PORT107 1PORT108 2PORT109 3PORT110 Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 0:107 1:109 Extended cyclic prefix 0:107 1:108 DCI(index:023) DCI RNTI 0RNTI0C-RNTI 1RNTI1SPS-C-RNTI 2RNTI2TPC-PDCCH-RNTI 3RNTI3TPC-PDSCH-RNTI 4RNTI4P-RNTI 5RNTI5RA-RNTI 6RNTI6Temp-C-RNTI 7RNTI7SC-RNTI 8RNTI8G-RNTI DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) tx2:03tx4:015 HARQ:015 Nscid(UE)01 03 0:QPSK 1:16QAM max2984 RB16 RB05 HARQ-ACK delay HARQ-ACK bundling flag SPS-C-RNTI 0 1 2 DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification DCI6-0A /DCI6-1ASRS DCI6-0ACSI DCI6-1A/DCI6-0A(TDD,uldl:16)DAI DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX DCI6-0A /DCI6-1A PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) MPDCCH DCI (03),Transport blocks in a bundle DCI2DI(direct indication) 0PAGING 1DI DCI6-1ADCI1-BPDCCH ORDER 0ORDER 1ORDER 0DCI 1 0 1 DCI 0:DCI6-1A 1:DCI6-1B 2:DCI6-0A 3:DCI6-0B 4:DCI3/3A 5:DCI2 015 DCI6-1APDSCH1tbsize DCIfalse alarm(vit) DCIfalse alarm0 DCI DCI332 DCI332 0 1 2 3PORT7 4PORT8 00 11 PRB2+4DCIPRB 0:2PRB 1:4PRB 2:6PRB DCI 01 12 DCICOMMUE 0 1UE DCIRi 0R0 1R1 2R2 3R3 DCIPORTn0 Normal cyclic prefix; Normal subframes, Special subframes, configurations 3, 4, 8 0PORT107 1PORT108 2PORT109 3PORT110 Normal cyclic prefix; Special subframes, configurations 1, 2, 6, 7, 9 0:107 1:109 Extended cyclic prefix 0:107 1:108 DCI(index:023) DCI RNTI 0RNTI0C-RNTI 1RNTI1SPS-C-RNTI 2RNTI2TPC-PDCCH-RNTI 3RNTI3TPC-PDSCH-RNTI 4RNTI4P-RNTI 5RNTI5RA-RNTI 6RNTI6Temp-C-RNTI 7RNTI7SC-RNTI 8RNTI8G-RNTI DCIL 000L=1; 001L=2; 010L=4; 011L=8; 100L=12; 101L=16; 110L=24; DCI (max38) tx2:03tx4:015 HARQ:015 Nscid(UE)01 03 0:QPSK 1:16QAM max2984 RB16 RB05 HARQ-ACK delay HARQ-ACK bundling flag SPS-C-RNTI 0 1 2 DCI6-1A/DCI6-1BACKInformation for SC-MCCH change notification DCI6-0A /DCI6-1ASRS DCI6-0ACSI DCI6-1A/DCI6-0A(TDD,uldl:16)DAI DCI6-1A/DCI6-0A(TDD,uldl:0)ULINDEX DCI6-0A /DCI6-1A PDSCH/PUSCH(DCI6-207DCI6-1x/ DCI6-0x03) MPDCCH DCI (03),Transport blocks in a bundle DCI2DI(direct indication) 0PAGING 1DI DCI6-1ADCI1-BPDCCH ORDER 0ORDER 1ORDER 0DCI 1 0 1 DCI 0:DCI6-1A 1:DCI6-1B 2:DCI6-0A 3:DCI6-0B 4:DCI3/3A 5:DCI2 015 DCI6-1APDSCH1tbsize DCIfalse alarm(vit) DCIfalse alarm0 DCI MIB SIB1schedule0~31 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 MIB 00 11 22 33 MIB bit0 bit11 alllegacyTDD0FDD90 bit221 onlylegacyTDD0FDD90 bit32 alllegacyTDD05FDD bit42 onlylegacyTDD05FDD MIB SIB1schedule0~31 01.4Mhz 13Mhz 25Mhz 310Mhz 415Mhz 520Mhz 6~75 MIB 00 11 22 33 MIB bit0 bit11 alllegacyTDD0FDD90 bit221 onlylegacyTDD0FDD90 bit32 alllegacyTDD05FDD bit42 onlylegacyTDD05FDD 5 4 3 2 1 0 11 10 9 8 7 6 13 12 LDTC CYCLE LDTCCYCLE REIS 0 1 REIS 0 1REIS REIS0 REISNUM REIS1 REIS1RE20M1200RE REIS0 REIS0 RE20M1200RE REIS3 REIS3RE20M1200RE REIS2 REIS2 RE20M1200RE REIS3 REIS3RE20M1200RE REIS2 REIS2 RE20M1200RE REIS3 REIS3RE20M1200RE REIS2 REIS2 RE20M1200RE 2ABISPORT 0port0 1port1 RBIS 0 1 RBISSD PDSCH 0 1 RBISSD MPDCCH 0 1 RBISSD PBCH 0 1 RBIS 0 1 RBIS 01 12 23 34 45 RBIS RBIS RBIS0~5 RBIS0~5 RBIS0~5 RBIS0~5 RBIS0~5 RBIS RBIS 2 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 1 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 02port0port14port0port1port2port3 12port04port0port2port3 22port14port1port2port3 MultiCell 0SingalCell 1:MultiCell ABIS SD PDSCH 0 1 ABIS SD MPDCCH 0 1 ABIS SD PBCH 0 1 ABIS 0 1 000 011 102 0 2 001port 012port 104port 1port 1 001port 012port 104port 1port 2 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 1 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 2 CELL ID 1 CELL ID 1TS 2TS ABIS31+2 ABIS22 ABIS11 PBML 0 1 LLR LLR LLR 0~255 PDCCHfalse alarm PDCCHfalse alarm(U8Q7) bit type is changed from rw1c to rc. PMI 0 1 bit type is changed from rw1c to rc. PBCH 0 1 bit type is changed from rw1c to rc. PDSCH 0 1 bit type is changed from rw1c to rc. MPDCCH 0 1 DCI 0 1 DCI Ri 0DCI 1DCIRi DCI2 0DCI 1DCI2 DCI 0DCI 1DCI MIB 0MIB 1MIB PDSCH CRC 0 1 PDSCH CRC 0CRC 1CRC LDTC LDTC 1TS 2TS TS CATMCELL RSOFDM0 0OFDM0 1OFDM0 FFT 0 1 0FFTFFT 1FFTFFT 0DLFFTLDTC1LDTC 1DLFFTLDTC1LDTC 1DLFFTTXRXOFDM 0DLFFT 0: 1: 0~1023 0~9 CELL RS&AGC 000 001 010 011 100 CAT1CELL RSOFDM0 0OFDM0 1OFDM0 MBMS 2b00MBMSCELLRS 2b01MBMS1CELLRS 2b10MBMS2CELLRS 2b1100 0MBMS 1MBMS CELLID CP 0NORM CP 1EX CP CELLRS PORT 2b00port0 2b01port0/1 2b10port0/1/2/3 2b11CELLPORT_SEL2b112b00prot0 UERS PORT 0port5 1port7/8 0CELLRS 1CELLRS 0UERS 1UERS RSCSIRSCSIRS BITMAP CSIRSCSIRSOFDM CSIRSCSIRSOFDM MBMSCELLRSOFDMAGC MBMSAGCMBMSCELLRSOFDMAGC 0PBCH 1PBCH 0CSIRS 1CSIRS PRB 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 1116prb 0~6 0TDD MODE 1FDD MODE 0~9 FFT0~4096 NBIOTNBPRB0~5 CP 0CP 1CP 0~6 0TDD MODE 1FDD MODE 0~9 CELL RS&AGC 000 001 010 011 100 0NBNRS 1NBCRS CELLRSNRSID CELLRSNRS PORT 2b00port0 2b01port0/1 2b10port0/1/2/3 2b112b10 0 1 CATMAGC 0LDTC1LLR0 1LDTC1LLR CTCG 0OFDM4(OFDM4)CRS 1OFDM8(OFDM8)CRS 000 011 102 0 2 001port 012port 104port 1port 1 001port 012port 104port 1port 2 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 1 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 2 CELL ID 1 CELL ID 1TS 2TS ABISOFDM0~13 CRSCRS AGC 0DLFFT_INFO_OUT1 1DLFFT_INFO_OUT2 DLFFT INFO 0CRS_POW_MAXPOWAGC 1CRS_POW_MAXPOWAGC 0SOFT_IRT 1SOFT_IRT 00CAT1 01CATM 10NB-IOT 11CAT1 FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~18bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~19bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~20bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~21bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~22bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~23bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~24bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~25bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~26bit ATMCELL RSOFDM0 0OFDM0 1OFDM0 FFT 0 1 0FFTFFT 1FFTFFT 0DLFFTLDTC1LDTC 1DLFFTLDTC1LDTC 1DLFFTTXRXOFDM 0DLFFT 0: 1: 0~1023 0~9 CELL RS&AGC 000 001 010 011 100 CELL RSOFDM0 0OFDM0 1OFDM0 MBMS 2b00MBMSCELLRS 2b01MBMS1CELLRS 2b10MBMS2CELLRS 2b1100 0MBMS 1MBMS CELLID CP 0NORM CP 1EX CP CELLRS PORT 2b00port0 2b01port0/1 2b10port0/1/2/3 2b11CELLPORT_SEL2b112b00prot0 UERS PORT 0port5 1port7/8 0CELLRS 1CELLRS 0UERS 1UERS RSCSIRSCSIRS BITMAP CSIRSCSIRSOFDM CSIRSCSIRSOFDM MBMSCELLRSOFDMAGC MBMSAGCMBMSCELLRSOFDMAGC 0PBCH 1PBCH 0CSIRS 1CSIRS PRB 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 1116prb 0~6 0TDD MODE 1FDD MODE 0~9 FFT0~4096 NBIOTNBPRB0~5 CP 0CP 1CP 0~6 0TDD MODE 1FDD MODE 0~9 CELL RS&AGC 000 001 010 011 100 0NBNRS 1NBCRS CELLRSNRSID CELLRSNRS PORT 2b00port0 2b01port0/1 2b10port0/1/2/3 2b112b10 0 1 CATMAGC 0LDTC1LLR0 1LDTC1LLR CTCG 0OFDM4(OFDM4)CRS 1OFDM8(OFDM8)CRS 000 011 102 0 2 001port 012port 104port 1port 1 001port 012port 104port 1port 2 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 1 0006prb 00115prb 01025prb 01150prb 10075prb 101100prb 6prb 2 CELL ID 1 CELL ID 1TS 2TS ABIS LLR-8~8 ABISOFDM0~13 CRSCRS AGC 0DLFFT_INFO_OUT1 1DLFFT_INFO_OUT2 DLFFT INFO 0CRS_POW_MAXPOWAGC 1CRS_POW_MAXPOWAGC 0SOFT_IRT 1SOFT_IRT 00CAT1 01CATM 10NB-IOT 11CAT1 FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~18bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~19bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~20bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~21bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~22bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~23bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~24bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~25bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~26bit 1RF 0RF 1RF 0RF 1RF 0RF 1RF 0RF 1RF 0RF 1AXIDMA AXIDMADLFFT OFDM 0AXIDMA 1DLFFTTXRX or LDTC or LDTC1ERROR 0DLFFTTXRX or LDTCor LDTC1ERROR 1DLFFTOFDM 0DLFFT 1DLFFTTXRXOFDM 0DLFFT FFT0~4096 0: CATM/NB 1: CATM/NB 0: CAT1 1: CAT1 bit type is changed from rw1c to rc. 1MEASPWR 0 MEASPWR bit type is changed from rw1c to rc. 1RF 0RF bit type is changed from rw1c to rc. 1SDDLFFT 0SDDLFFT bit type is changed from rw1c to rc. 1COEFFLDTC 0COEFFLDTC bit type is changed from rw1c to rc. 1COEFFLDTC1 0COEFFLDTC1 bit type is changed from rw1c to rc. 1RF 0RF bit type is changed from rw1c to rc. 1RF 0RF bit type is changed from rw1c to rc. 1RF 0RF bit type is changed from rw1c to rc. 1RF 0RF bit type is changed from rw1c to rc. 1AXIDMAAXIDMADLFFTOFDM 0AXIDMA bit type is changed from rw1c to rc. 1CSI 0CSI bit type is changed from rw1c to rc. 1MMSE 0MMSE bit type is changed from rw1c to rc. 1LDTC 0LDTC bit type is changed from rw1c to rc. 1TXRX 0TXRX bit type is changed from rw1c to rc. 1DLFFTOFDM 0DLFFT bit type is changed from rw1c to rc. 1DLFFTTXRXOFDM 0DLFFT OFDM0~13 DLFFT INFO 2 DLFFT INFO 1 0 1 ABIS11 ABIS22 ABIS31+2 CELLRS CELLRSAGC CELLRS CELLRSAGC CELLRS CELLRSAGC CELLRS CELLRSAGC CELLRS CELLRSAGC OFDM 7TXRX OFDM 6TXRX OFDM 5TXRX OFDM 4TXRX OFDM 3TXRX OFDM 2TXRX OFDM 1TXRX OFDM 0TXRX OFDM 13TXRX OFDM 12TXRX OFDM 11TXRX OFDM 10TXRX OFDM 9TXRX OFDM 8TXRX TXRXSOFT IRT1 TXRXSOFT IRT0 ASSERTTXRX_ENABLE ASSERTOFDM0~13 ASSERT 0ABISLLR_OUT3 1ABISLLR_OUT3 0ABISLLR_OUT2 1ABISLLR_OUT2 0ABISLLR_OUT1 1ABISLLR_OUT1 Coeffmeas 1 0 Coeffldtc\ldtc1 1 0 Coeffldtc\ldtc1 buf 00ldtc buf1 01ldtc buf2 10ldtc buf3 11 CAT1CATM 0CATM 1CAT1 0 1 Port 0Port78 1Port5 0QFQT 1QFQT 0: NCP 1: ECP 0: QFQT 1: QFQT bit type is changed from rw1c to rc. buf 00ldtc buf1 01ldtc buf2 10ldtc buf3 11meas buf bit type is changed from rw1c to rc. bit type is changed from rw1c to rc. 0: 1: 000: 6PRB 001: 15PRB 010: 25PRB 011: 50PRB 100: 75PRB 101: 100PRB Others: RESERVED 6PRB 00: EPA 01: EVA 10: ETU 11: RESERVED EPA 005 0170 10300 11: 850 TDDFDD 0TDD 1FDD 0000SS0 0001SS1 0010SS2 0011SS3 0100SS4 0101SS5 0110SS6 0111SS7 1000SS8 1001SS9 1 0 1 0 RAM3RAM RAM3256+ RAM2SPI RAM RAM3RAM RAM3256+ RAM2SPI RAM 1 0 SPI 1SPI 0GPO SPI 1SPI 0SPI SPI SPISENSCLK SPI 0004 0016default 0108 01110 10012 10114 11016 11118 SPI 0004 0016default 0108 01110 10012 10114 11016 11118 4-W3-W 0 1 17bit4 0 1 SPI 03 14 SPISPI 00:0 01:1 10:2 11:3 00 1 0Normal SPI 1DigRF SPI SPI 0: 1; 1: ; SPI 0: SPIIDLE 1: SPIIDLE SPI 0: SPI 1: SPI SPI 00000: 1-bits 00001: 2-bits ........... 11111: 32-bits SPI 00000: 1-bits 00001: 2-bits ........... 11111: 32-bits RFSPI 1 0 1 0 0RAM 1RAM 0 1 0xf0xA RAM 1 0 1 0 0RAM 1RAM 0 1 0xf0xA RAM RF GPO control register 1 0 RFAD 1 0 FRAMC 1 0 FRAMC FRAML FRAML FRAMC FRAMC bit type is changed from r/w to rw. DFT/IDFTindex0~4344index bit type is changed from r/w to rw. 00: BPSK 01: QPSK 10: 16QAM 11: 64QAM bit type is changed from r/w to rw. 0DFT/IDFT 1DFT/IDFT bit type is changed from r/w to rw. 0PUSCH 1PUSCH bit type is changed from r/w to rw. 0: DFT 1: IDFT bit type is changed from r/w to rw. PUCCHd(n) SRS 021 143 bit type is changed from r/w to rw. 000 011 102 113 bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS 0SRS1 1SRS2 SRSOFDM SRSOFDM SRSOFDM bit type is changed from r/w to rw. SRSZC 0TX 1TX 2 1 PUCCH PUCCH PUSCH 00.5ms 11ms PUSCH PUSCH PUSCH PUSCH PUSCH DMRS 1 0 PUSCH/PUCCH 0000normal 0001type0_shortend 0010type1_shortend 0011type2_shortend 0100type3_shortend 0101type4_shortend 0110type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1u 0u 1v 0v TA0~32 dmrsValue0~7 SRSAPC PUSCH/PUCCH/PRACHAPC PUCCH1/1a/1b0~4095 SRS CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 0~1023 OFDMoffset OFDMoffset 0ULDFTTXRXPUSCHERROR 1ULDFTTXRXPUSCHERROR 1AXIDMA 0AXIDMA 1OFDM13 0OFDM13 1OFDM12 0OFDM12 1OFDM11 0OFDM11 1OFDM10 0OFDM10 1OFDM9 0OFDM9 1OFDM8 0OFDM8 1OFDM7 0OFDM7 1OFDM6 0OFDM6 1OFDM5 0OFDM5 1OFDM4 0OFDM4 1OFDM3 0OFDM3 1OFDM2 0OFDM2 1OFDM1 0OFDM1 1OFDM0 0OFDM0 bit type is changed from rw1c to rc. 1OFDM13 0OFDM13 bit type is changed from rw1c to rc. 1OFDM12 0OFDM12 bit type is changed from rw1c to rc. 1OFDM11 0OFDM11 bit type is changed from rw1c to rc. 1OFDM10 0OFDM10 bit type is changed from rw1c to rc. 1OFDM9 0OFDM9 bit type is changed from rw1c to rc. 1OFDM8 0OFDM8 bit type is changed from rw1c to rc. 1OFDM7 0OFDM7 bit type is changed from rw1c to rc. 1OFDM6 0OFDM6 bit type is changed from rw1c to rc. 1OFDM5 0OFDM5 bit type is changed from rw1c to rc. 1OFDM4 0OFDM4 bit type is changed from rw1c to rc. 1OFDM3 0OFDM3 bit type is changed from rw1c to rc. 1OFDM2 0OFDM2 bit type is changed from rw1c to rc. 1OFDM1 0OFDM1 bit type is changed from rw1c to rc. 1OFDM0 0OFDM0 bit type is changed from rw1c to rc. 1pusch 0pusch bit type is changed from rw1c to rc. 1txrx 0txrx OFDM 14b0 14b10 14b1101 14b111012 0ULDFT 1ULDFT 0ULDFT 1ULDFTPUSCH 0 1 0SRS 1SRS 0FFTMEM 1FFTMEM 1IFFT 0FFT 1FFT/IFFT 0FFT/IFFT 0 1 PRACH 000PRACH0 001PRACH1 010PRACH2 011PRACH3 100PRACH4 PUCCH 000PUCCH1 001PUCCH1a 010PUCCH1b 011PUCCH2 100PUCCH2a 101PUCCH2b 0NPUSCH format 1 1NPUSCH format2 OFDM 0DATADRIVE 1DATADRIVE UL_DFTPUSCH BUFFER 00PUSCH BUFFER1 01PUSCH BUFFER2 10PUSCH BUFFER3 11PUSCH PRA_BUF 000PUSCH 001PUCCH 010PRACH 011SRS 100NPUSCH 101NPRACH FFT/IFFT 111 110 101 1002048 0111024 010512 001256 000128 0: 1: FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit NPUSCH0~127 001 013 106 1112 NPUSCH 0~47 Nslots1~160 0: 3.75KHz 1: 15KHz RU0~19 1DMRS0~20480 BASE_SEQ_NEXT0~30 CYCLIC_SHIFT0~3 t0~128 frequency location of the first sub-carrier allocated to NPRACH 000frequency location0 001frequency location2 010frequency location12 011frequency location18 100frequency location24 101frequency location34 110frequency location36 1110 being the subcarrier selected by the MAC layer from 0-47 0~29 PUCCH2/2a/2b0~1184 0~7 CP 0CP 1CP 0TDD mode 1FDD mode 1: 0: NCSUGOLDC_INI 1if no value for or is configured by higher layers or the PUSCH transmission corresponds to a Random Access Response Grant or a retransmission of the same transport block as part of the contention based random access procedure 0otherwise NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509 NCS_U_GOLD_MODE1 + 0~532NCS_U_GOLD_MODE0 0~509 ID0~503 RSID nCsAn1/1a/1b0~7 CE_mode 0CE_modeA 1CE_modeB 00 1 01 2 10 3 1100 1 cqiNrb PUCCH2/2a/2b0~98 ULDFT 00CAT1 01CATM 10NB-IOT 11CAT1 CAT1 0006PRB 00115PRB 01025PRB 01150PRB 10075PRB 101100PRB 6PRB 0DMA 1DMA 0: 1: SW_PAUSE_EN=1OFDM 14`b0 14`b1OFDM0 14`b11OFDM01 14`b111OFDM012 SW_PAUSE_EN=1 0SW_PAUSE_OFDMOFDM 1SW_PAUSE_OFDMOFDM 0 1 0 1 0 1OFDM bit type is changed from rw1c to rc. 0 1 bit type is changed from rw1c to rc. 0 1 bit type is changed from r/w to rw. DFT/IDFTindex0~4344index bit type is changed from r/w to rw. 00: BPSK 01: QPSK 10: 16QAM 11: 64QAM bit type is changed from r/w to rw. 0DFT/IDFT 1DFT/IDFT bit type is changed from r/w to rw. 0PUSCH 1PUSCH bit type is changed from r/w to rw. 0: DFT 1: IDFT bit type is changed from r/w to rw. PUCCHd(n) SRS 021 143 bit type is changed from r/w to rw. 000 011 102 113 bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS 0SRS1 1SRS2 SRSOFDM SRSOFDM SRSOFDM bit type is changed from r/w to rw. SRSZC 0TX 1TX 2 1 PUCCH PUCCH PUSCH 00.5ms 11ms PUSCH PUSCH PUSCH PUSCH PUSCH/PUCCH 0000normal 0001type0_shortend 0010type1_shortend 0011type2_shortend 0100type3_shortend 0101type4_shortend 0110type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1u 0u 1v 0v TA0~32 dmrsValue0~7 SRSAPC PUSCH/PUCCH/PRACHAPC PUCCH1/1a/1b0~4095 SRS CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 0~1023 OFDMoffset OFDMoffset 0ULDFTTXRXPUSCHERROR 1ULDFTTXRXPUSCHERROR 1AXIDMA 0AXIDMA 1OFDM13 0OFDM13 1OFDM12 0OFDM12 1OFDM11 0OFDM11 1OFDM10 0OFDM10 1OFDM9 0OFDM9 1OFDM8 0OFDM8 1OFDM7 0OFDM7 1OFDM6 0OFDM6 1OFDM5 0OFDM5 1OFDM4 0OFDM4 1OFDM3 0OFDM3 1OFDM2 0OFDM2 1OFDM1 0OFDM1 1OFDM0 0OFDM0 OFDM 14b0 14b10 14b1101 14b111012 0ULDFT 1ULDFT 0ULDFT 1ULDFTPUSCH 0 1 0SRS 1SRS 0FFTMEM 1FFTMEM 1IFFT 0FFT 1FFT/IFFT 0FFT/IFFT 0 1 PRACH 000PRACH0 001PRACH1 010PRACH2 011PRACH3 100PRACH4 PUCCH 000PUCCH1 001PUCCH1a 010PUCCH1b 011PUCCH2 100PUCCH2a 101PUCCH2b 0NPUSCH format 1 1NPUSCH format2 OFDM 0DATADRIVE 1DATADRIVE UL_DFTPUSCH BUFFER 00PUSCH BUFFER1 01PUSCH BUFFER2 10PUSCH BUFFER3 11PUSCH PRA_BUF 000PUSCH 001PUCCH 010PRACH 011SRS 100NPUSCH 101NPRACH FFT/IFFT 111 110 101 1002048 0111024 010512 001256 000128 0: 1: FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit NPUSCH0~127 001 013 106 1112 NPUSCH 0~47 Nslots1~160 0: 3.75KHz 1: 15KHz RU0~19 1DMRS0~20480 BASE_SEQ_CURR0~30 CYCLIC_SHIFT0~3 t0~128 frequency location of the first sub-carrier allocated to NPRACH 000frequency location0 001frequency location2 010frequency location12 011frequency location18 100frequency location24 101frequency location34 110frequency location36 1110 being the subcarrier selected by the MAC layer from 0-47 bit type is changed from r/w to rw. DFT/IDFTindex0~4344index bit type is changed from r/w to rw. 00: BPSK 01: QPSK 10: 16QAM 11: 64QAM bit type is changed from r/w to rw. 0DFT/IDFT 1DFT/IDFT bit type is changed from r/w to rw. 0PUSCH 1PUSCH bit type is changed from r/w to rw. 0: DFT 1: IDFT bit type is changed from r/w to rw. PUCCHd(n) SRS 021 143 bit type is changed from r/w to rw. 000 011 102 113 bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS bit type is changed from r/w to rw. SRS 0SRS1 1SRS2 SRSOFDM SRSOFDM SRSOFDM bit type is changed from r/w to rw. SRSZC 0TX 1TX 2 1 PUCCH PUCCH PUSCH 00.5ms 11ms PUSCH PUSCH PUSCH PUSCH PUSCH/PUCCH 0000normal 0001type0_shortend 0010type1_shortend 0011type2_shortend 0100type3_shortend 0101type4_shortend 0110type5_shortend 0111: type6_shortend 1000: type7_shortend 1001: other 1u 0u 1v 0v TA0~32 dmrsValue0~7 SRSAPC PUSCH/PUCCH/PRACHAPC PUCCH1/1a/1b0~4095 SRS CAT1/CATM/CAT-NB15kHz1ms2CAT-NB3.75kHz2ms1 0~1023 OFDMoffset OFDMoffset 0ULDFTTXRXPUSCHERROR 1ULDFTTXRXPUSCHERROR 1AXIDMA 0AXIDMA 1OFDM13 0OFDM13 1OFDM12 0OFDM12 1OFDM11 0OFDM11 1OFDM10 0OFDM10 1OFDM9 0OFDM9 1OFDM8 0OFDM8 1OFDM7 0OFDM7 1OFDM6 0OFDM6 1OFDM5 0OFDM5 1OFDM4 0OFDM4 1OFDM3 0OFDM3 1OFDM2 0OFDM2 1OFDM1 0OFDM1 1OFDM0 0OFDM0 OFDM 14b0 14b10 14b1101 14b111012 0ULDFT 1ULDFT 0ULDFT 1ULDFTPUSCH 0 1 0SRS 1SRS 0FFTMEM 1FFTMEM 1IFFT 0FFT 1FFT/IFFT 0FFT/IFFT 0 1 PRACH 000PRACH0 001PRACH1 010PRACH2 011PRACH3 100PRACH4 PUCCH 000PUCCH1 001PUCCH1a 010PUCCH1b 011PUCCH2 100PUCCH2a 101PUCCH2b 0NPUSCH format 1 1NPUSCH format2 OFDM 0DATADRIVE 1DATADRIVE UL_DFTPUSCH BUFFER 00PUSCH BUFFER1 01PUSCH BUFFER2 10PUSCH BUFFER3 11PUSCH PRA_BUF 000PUSCH 001PUCCH 010PRACH 011SRS 100NPUSCH 101NPRACH FFT/IFFT 111 110 101 1002048 0111024 010512 001256 000128 0: 1: FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit FFT 2b0025~14bit 2b0126~15bit 2b1027~16bit 2b1128~17bit NPUSCH0~127 001 013 106 1112 NPUSCH 0~47 Nslots1~160 0: 3.75KHz 1: 15KHz RU0~19 1DMRS0~20480 BASE_SEQ_CURR0~30 CYCLIC_SHIFT0~3 t0~128 frequency location of the first sub-carrier allocated to NPRACH 000frequency location0 001frequency location2 010frequency location12 011frequency location18 100frequency location24 101frequency location34 110frequency location36 1110 being the subcarrier selected by the MAC layer from 0-47 TXRX PING 1 0 TXRX PANG 1 0 OFDM0~13 ASSERT TXRX PING 1 0 ASSERT TXRX PANG 1 0 ASSERT ASSERT ASSERT OFDM0~13 bit type is changed from rw1c to rc. TRACE 0 1 bit type is changed from rw1c to rc. TRACE 0 1 bit type is changed from rw1c to rc. 0 1 bit type is changed from rw1c to rc. 0 1 bit type is changed from rw1c to rc. 0 1 bit type is changed from rw1c to rc. 0 1 TRACE 0 1 TRACE 0 1 0 1 0 1 0 1 0 1 bit type is changed from rw1c to rc. 0OFDM14 1OFDM14 bit type is changed from rw1c to rc. 0OFDM13 1OFDM13 bit type is changed from rw1c to rc. 0OFDM12 1OFDM12 bit type is changed from rw1c to rc. 0OFDM11 1OFDM11 bit type is changed from rw1c to rc. 0OFDM10 1OFDM10 bit type is changed from rw1c to rc. 0OFDM9 1OFDM9 bit type is changed from rw1c to rc. 0OFDM8 1OFDM8 bit type is changed from rw1c to rc. 0OFDM7 1OFDM7 bit type is changed from rw1c to rc. 0OFDM6 1OFDM6 bit type is changed from rw1c to rc. 0OFDM5 1OFDM5 bit type is changed from rw1c to rc. 0OFDM4 1OFDM4 bit type is changed from rw1c to rc. 0OFDM3 1OFDM3 bit type is changed from rw1c to rc. 0OFDM2 1OFDM2 bit type is changed from rw1c to rc. 0OFDM1 1OFDM1 bit type is changed from rw1c to rc. 0OFDM0 1OFDM0 1 0 1 0OFDM 1OFDM 0OFDM14 1OFDM14 0OFDM13 1OFDM13 0OFDM12 1OFDM12 0OFDM11 1OFDM11 0OFDM10 1OFDM10 0OFDM9 1OFDM9 0OFDM8 1OFDM8 0OFDM7 1OFDM7 0OFDM6 1OFDM6 0OFDM5 1OFDM5 0OFDM4 1OFDM4 0OFDM3 1OFDM3 0OFDM2 1OFDM2 0OFDM1 1OFDM1 0OFDM0 1OFDM0 DCOC 1 0 0 1 0 1 DFE 0DFE 1DFE 0 1 CAT1 0CAT1 1CAT1 0 1 0 1 SOFT AFC 0 1 RSSI 1data 0data RSSI 0: RSSI_MAX1 1: RSSI_MAX2 2: RSSI_MAX3 3: RSSI_MAX4 4: RSSI_MAX5 Other: 1 0 OTDOA 1 0 offset 1RXoffsetcp 0offset 1IDDET 0IDDET DLFFT DATA_DRIVE 0 1 00CP 01CP 10CPIDDET FIR 4h033-22 4h132-21 4h231-20 4h330-19 4h429-18 4h528-17 4h627-16 4h726-15 4h825-14 4h924-13 4ha23-12 4hb22-11 4hc21-10 4hd20-9 4he19-8 4hf18-7 TRACE 1 0 0measpwr/dlfft offset 10 0offsetoffset_ctrl_flag 0 1 0 1 0 1 0 1 RSSI 1 0 0 1 OFDM AFC 1 0 AFC 10hz 1 0 AD_ON0 RSSI0 1 0 RSSI 1~5 3h5: 20M (1/16) 3h4: 15M (1/16) 3h3: 10M (1/8) 3h2: 5M (1/4) 3h1: 3M (1/2) 3h0: 1.4M Other: 1 0 FIR 1 0 FIR 5b0000034-23 5b0000133-22 5b0001032-21 5b0001131-20 5b0010030-19 5b0010129-18 5b0011028-17 5b0011127-16 5b0100026-15 5b0100125-14 5b0101024-13 5b0101123-12 5b0110022-11 5b0110121-10 5b0111020-9 5b0111119-8 5b1000018-7 5b1000117-6 5b1001016-5 Other DCOC 0 1 I Q GAIN1 0 1 GAIN1 GAIN2 0 1 GAIN2 IDDET 2h0:bit7 2'h1:bit8 2h2:bit9 2'h3:bit10 IDDET 3h0:bit0 3'h1:bit1 3h2:bit2 3'h3:bit3 3h4:bit4 other:reserved OTDOA 2h0:bit7 2'h1:bit8 2h2:bit9 2'h3:bit10 OTDOA 3h0:bit0 3'h1:bit1 3h2:bit2 3'h3:bit3 3h4:bit4 other:reserved MEASPWR 2h0:bit7 2'h1:bit8 2h2:bit9 2'h3:bit10 MEASPWR 3h0:bit0 3'h1:bit1 3h2:bit2 3'h3:bit3 3h4:bit4 other:reserved 0 1 DATA_DRIVE 0 1 1CP 0CP 0 1 OFDM(-32~31) PINGCP0 PANGCP0 PRACH 1 0 DFT PRACH 3hxxx0~4 DFT NB DFT 1 0 DFT 3h5: 20M (16) 3h4: 15M (16) 3h3: 10M (8) 3h2: 5M (4) 3h1: 3M (2) 3h0: 1.4M Other: 1 0 FIR 5b0000034-23 5b0000133-22 5b0001032-21 5b0001131-20 5b0010030-19 5b0010129-18 5b0011028-17 5b0011127-16 5b0100026-15 5b0100125-14 5b0101024-13 5b0101123-12 5b0110022-11 5b0110121-10 5b0111020-9 5b0111119-8 5b1000018-7 5b1000117-6 5b1001016-5 Other 0 8hff : 255 8hfe: 254 8h01: 1 8h00: 0 32h0:0 32h1:1 ????????? RSSI RSSI RSSI RSSI RSSI I Q RX_MEM AD_ON 0 1 DLFFT OTDOA IDDET MEAS CP 0 1 0 1 PING_PANG OFDM TX_MEM DA_ON 0 1 FIFO 0ping 1pang OFDM TS AD_ON 01 mem CP TS DA_ON 0 1 PING RAM DFTPING DFTPANG PING PANG ADONFRAMC FRAMC FRAMC AD_ON AD_ON AD_ON AD_ON DA_ON DA_ON DA_ON DA_ON 4FFTBUF1 3FFTBUF1 2FFTBUF1 1FFTBUF1 4FFTBUF2 3FFTBUF2 2FFTBUF2 1FFTBUF2 4FFT2LDTC 3FFT2LDTC 2FFT2LDTC 1FFT2LDTC FDD_TDD 0FDD 1TDD TXRXAD_ON 0~30720*10-110ms(AD ON) MEASPWR1~30720*6(6ms) Offset2 0offset2 1offset2 MEASPWR 0~30720*6-1 ID1 (0~30720*10-1) ID2 (0~30720*10-1) s ID4 (0~30720*10-1) ID5 (0~30720*10-1) ID6 (0~30720*10-1) ID7 (0~30720*10-1) ID8 (0~30720*10-1) Nboffset4 ID3~ID8 01 12 23 511:512 ID1ID2 01 12 23 511:512 IFFT IFFT IFFT IFFT IFFT IFFT IFFT 2b00:bit[25:14] 2b01:bit[26:15] 2b10:bit[27:16] 2b11:bit[28:17] IFFT ID8 10 bit[28] bit[29] bit[30]AFC bit[31]:agc_compare ID7 10 bit[24] bit[25] bit[26]AFC bit[27]:agc_compare ID6 10 bit[20] bit[21] bit[22]AFC bit[23]:agc_compare ID5 10 bit[16] bit[17] bit[18]AFC bit[19]:agc_compare ID4 10 bit[12] bit[13] bit[14]AFC bit[15]:agc_compare ID3 10 bit[8] bit[9] bit[10]AFC bit[11]:agc_compare ID2 10 bit[4] bit[5] bit[6]AFC bit[7]:agc_compare ID1 10 bit[0] bit[1] bit[2]AFC bit[3]:agc_compare bit type is changed from r1c to rc. ID8 10 bit[28] bit[29] bit[30]AFC bit[31]:agc_compare bit type is changed from r1c to rc. ID7 10 bit[24] bit[25] bit[26]AFC bit[27]:agc_compare bit type is changed from r1c to rc. ID6 10 bit[20] bit[21] bit[22]AFC bit[23]:agc_compare bit type is changed from r1c to rc. ID5 10 bit[16] bit[17] bit[18]AFC bit[19]:agc_compare bit type is changed from r1c to rc. ID4 10 bit[12] bit[13] bit[14]AFC bit[15]:agc_compare bit type is changed from r1c to rc. ID3 10 bit[8] bit[9] bit[10]AFC bit[11]:agc_compare bit type is changed from r1c to rc. ID2 10 bit[4] bit[5] bit[6]AFC bit[7]:agc_compare bit type is changed from r1c to rc. ID1 10 bit[0] bit[1] bit[2]AFC bit[3]:agc_compare TRMS SIGMA DOPPLER SINR AFC AFC TRMS RSRP IRT TRMS SIGMA DOPPLER SINR AFC AFC TRMS RSRP IRT agcagcagc ID3-80-15CATM ID20-15CATM ID10-15CATM ID3-8 01.4m 13m 25m 310m 415m 520m ID3-8 01.4m 13m 25m 310m 415m 520m ID1-2 01.4m 13m 25m 310m 415m 520m ID1-2 01.4m 13m 25m 310m 415m 520m Afc_factor AFC 0 1 4 AFC 0001 0012 0103 0114 1006 10112 Other:1 ID1 AFC SIGPWR alpha SIGPWR 001 012 114 Other1 ID1-2 SIGPWR( SIGMA alpha SIGMA1~80 Id1-2 Doppler alpha Doppler_scaleQ12 DOPPLER1~80 Trms8q0 0TRMSDis_Limit 1RSRPDis_Limit ID3-8: 0:1L_U16ExtractStepTab_true1 11L_U16ExtractStepTab_true ID1-2: 0:1L_U16ExtractStepTab_true1 11L_U16ExtractStepTab_true (N2N+1) ID1-216q15 ID1-216q10 ID3-8 ID1-2 ID1-2beta16Q10 ID3-8RSRP ID1-2RSRP L_S32RsrpdB_Temp = L_S32RsrpdB - AGC_Base*16 - RSRPAgcAdjust*16 + L_U16DownSamplingCompensate*16 ID1-2 RSSI Q() FFTIFFTQ FFTIFFT IRT 08910 1 pow Scale IRT 001 012 114 ID1-2 ID1-216q10 1ScaleTh 2ScaleTh 4ScaleTh 8ScaleTh 16ScaleTh 32ScaleTh 64ScaleTh 128ScaleTh 256ScaleTh 512ScaleTh ID3-8 Rssi ID1-2 Rssi IDRSSI 0MEASPWROFDMRSSI 1MEASPWR AGC FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 AFC Crs_rssi 00 01 10 11reserved 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 AFC 0IRT 1bit[8:1] 01 12 CP 0CP 1CP Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls Crs_rssi bit[25:16]9-0 OFFLINE0 SINR 000NASINR 0011 0102 0113 1004 OtherNA AFC 0 1 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 AFC Crs_rssi 00 01 10 11reserved 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 AFC 0IRT 1bit[8:1] 01 12 CP 0CP 1CP Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls Crs_rssi bit[25:16]9-0 OFFLINE0 AFC 0 1 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 FFT 4`b0000 4`b0001 4`b0010 . OFFLINE0 0 1 NID 0~503 2port 0port 0 and port 1 1only port 1 01 12 CP 0CP 1CP Crs_rssi 0 1 0 1 1 Offline 00 11 offline 0 1 NID1-2 IRT 0 1 AFC 0 1 0CATM 1CAT1 2NB NB_LTEFFT bit type is changed from r1s to rs. NID_MAP 0 1 bit type is changed from r1s to rs. NID3-8 bit type is changed from r1s to rs. Offlineonline 0online 1offline bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from r1s to rs. ID1 0 bit type is changed from rw1s to rs. NID8 bit type is changed from rw1s to rs. NID7 bit type is changed from rw1s to rs. NID6 bit type is changed from rw1s to rs. NID5 bit type is changed from rw1s to rs. NID4 bit type is changed from rw1s to rs. NID3 bit type is changed from rw1s to rs. NID2 bit type is changed from rw1s to rs. NID1 AFC AFC AFC AFC AFC AFCRSRP db AFCRSRP db AFCRSRP db AFCRSRP db AFCRSRP db 1SIGPWR 2SIGPWR 3SIGPWR 4SIGPWR 5SIGPWR 6SIGPWR ID2SIGPWR ID3SIGPWR ID4SIGPWR ID5SIGPWR 1SIGMA 1SINR LOG 1SIGMAAGC 2SIGMA 2SINR LOG 2SIGMAAGC 3SIGMA 3SINR LOG 3SIGMAAGC 4SIGMA 4SINR LOG 4SIGMAAGC SIGMA 5SINR LOG SIGMAAGC ID1SIGMA 6SINR LOG ID1SIGMAAGC ID2SIGMA ID2SINR LOG ID2SIGMAAGC ID3SIGMA ID3SINR LOG ID3SIGMAAGC ID4SIGMA ID4SINR LOG ID4SIGMAAGC ID5SIGMA ID5SINR LOG ID5SIGMAAGC 1SINR 2SINR 3SINR 4SINR SINR ID1SINR ID2SINR ID3SINR ID4SINR ID5SINR hls_agc_base DOPPLER hls_agc_base DOPPLER RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM RSRP RSRPdB Scale ScaledB RSRQdBOFDM RSSIRSSI AGC RSSIdBOFDM Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale Irt_scale 1 0 IRTscale IRT scale ID2 ID1 ID1-2 RBIS CORRECT 0 1 ID1-2 RBIS JUDGE 0 1 ID1-2 RBIS 0 1 ID1-2 RBIS 0 1 ID1-2 RBIS 01 12 23 34 45 ID1-2 RBIS ID1-2 RBIS ID14RBIPRB ID13RBIPRB ID12RBIPRB ID11RBIPRB ID1 RBIS JUDGE ID15RBIPRB ID1 RBIS ID1 RBIS ID2 offset4 ID2 RX IRT ID1 offset4 ID1 RX IRT debug_rev_flag debug_update_flag id_update offset2_update din_id_sel datagen_state datain_state inmem_in_act invalid_data_cont inmem_cont datain_state_cur func_id_sel pow_state func_state ID6SIGPWR ID7SIGPWR ID8SIGPWR ID6SIGMA ID6SINR LOG ID6SIGMAAGC ID7SIGMA ID7SINR LOG ID7SIGMAAGC ID8SIGMA ID8SINR LOG ID8SIGMAAGC ID6SINR ID7SINR ID8SINR ID2 AFC ID3 AFC ID4 AFC ID5 AFC ID6 AFC ID7 AFC ID8 AFC Id3-8 Doppler alpha trmsf_scale(Q12 TRMS TRMS alpha OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 OFFLINE0 Hmmse QF mem 0QF mem 1QF mem IRT scale 0 1 AFC\POW 00hls 01hmmse 10freqfirst 11hls bit[9:0]9-0 AFC HST AFC HST AFC HST AFC HST AFC HST AFC HST AFC HST AFC HST ID1SIGPWR ID2SIGPWR ID3SIGPWR ID4SIGPWR ID5SIGPWR ID6SIGPWR ID7SIGPWR ID8SIGPWR ID1SIGMA ID2SIGMA ID3SIGMA ID4SIGMA ID5SIGMA ID6SIGMA ID7SIGMA ID8SIGMA hls_agc_base DOPPLER hls_agc_base DOPPLER hls_agc_base DOPPLER hls_agc_base DOPPLER hls_agc_base DOPPLER hls_agc_base DOPPLER DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 TRMS TRMS TRMS TRMS TRMS TRMS TRMS TRMS TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 TRMSPART1 TRMSPART2 POWbit[23:0] POWbit[23:0] POWbit[23:0] POWbit[23:0] POWbit[23:0] POWbit[23:0] POWbit[23:0] POWbit[23:0] REIS_DC REIS 0 1 REISNUM REIS1RE20M1200RE REIS0RE20M1200RE REIS3RE20M1200RE REIS2RE20M1200RE REIS5RE20M1200RE REIS4RE20M1200RE REIS7RE20M1200RE REIS6RE20M1200RE Pos\delay 0pos 1:delay 00IRT_Scale 01RSRP_Scale 10SINR 11POWMAX_Scale 00IRT_Scale 01Sigpwr 10SINR 11IRT_Scale Offline MEASPWR_OFFLINE_SEL[5:4] Id8TBin Id7TBin Id6TBin Id5TBin Id4TBin Id3TBin Id2TBin Id1TBin TbinID1~ID8 0 1 Offline 0xF 00 143 Offline1 000 0105 1050 1190 Offline1 01 12 Offline1 3 AGC 2 AGC 1 AGC 6 AGC 5 AGC 4 AGC 9 AGC 8 AGC 7 AGC 12 AGC 11 AGC 10 AGC 15 AGC 14 AGC 13 AGC 18 AGC 17 AGC 16 AGC Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssi Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc Crs rssiagc 03PRB 16PRB 13bit 0x029~17 0x128~16 0x227~15 0x326~14 0x425~13 0x524~12 0x623~11 0x722~10 0x821~9 0x920~8 0xa19~7 0xb18~6 0xc17~5 0xd16~4 0xe15~3 0xf14~2 USED_WL_IND QF MEM 00mem 01mem Othermem ID38 INMEM 00 measpwr 01OTDOA 10 11 AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db AFC HSTRSRP db Pow_max_scale Pow_max_scale Pow_max_scale Pow_max_scale Pow_max_scale Pow_max_scale Pow_max_scale Pow_max_scale AFC AFC AFC AFCRSRP db AFCRSRP db AFCRSRP db DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 DOPPLER1 DOPPLER2 20AGC 19AGC bit[7:0]id8-id1 0: 1 ID1 ID1 ID1 ID1 ID1 ID1 ID1 ID110 bit[0]\offine bit[1] bit[2]AFC bit[3]Agc_compare bit[7:0]id8-id1 0 1 ID13 ID12 ID11 ID23 ID22 ID21 ID33 ID32 ID31 ID43 ID42 ID41 ID53 ID52 ID51 ID63 ID62 ID61 ID73 ID72 ID71 ID83 ID82 ID81 ID3-8 RBIS CORRECT 0 1 ID3-8 RBIS JUDGE 0 1 ID3-8 RBIS 0 1 ID3-8 RBIS 0 1 ID3-8 RBIS 01 12 23 34 45 ID3-8 RBIS ID3-8 RBIS ID24RBIPRB ID23RBIPRB ID22RBIPRB ID21RBIPRB ID2 RBIS JUDGE ID25RBIPRB ID2 RBIS ID2 RBIS ID3-84RBIPRB ID3-83RBIPRB ID3-82RBIPRB ID3-81RBIPRB ID3-8 RBIS JUDGE ID3-85RBIPRB ID3-8 RBIS ID3-8 RBIS 1ScaleTh 2ScaleTh 4ScaleTh 8ScaleTh 16ScaleTh 32ScaleTh 64ScaleTh 128ScaleTh 256ScaleTh 512ScaleTh ID3-8 SIGPWR ID3-8 id3-816q10 ID3-816q15 ID3-816q10 id3-8beta16Q10 ID3-8 ID14RBIPRB ID13RBIPRB ID12RBIPRB ID11RBIPRB ID1 RBIS JUDGE ID15RBIPRB ID24RBIPRB ID23RBIPRB ID22RBIPRB ID21RBIPRB ID2 RBIS JUDGE ID25RBIPRB ID3-84RBIPRB ID3-83RBIPRB ID3-82RBIPRB ID3-81RBIPRB ID3-8 RBIS JUDGE ID3-85RBIPRB DMAIDDET 0: 1: DMAMEM 0: 1: 5ms+2OFDM 1~9856 4b000: 5ms+2OFDM 4b0001: 1 4b1111: 15 0: 1: 3b001: PSS 3b010: PSS 3b011: SSS 3b100: 3b101: 3b110: bit type is changed from r/w to rw. TXRXOFFSET 1:OFFSET 0:OFFSET 1: TXRXDMA; 0: TXRXDMA 1: IDDET 0: IDDET 1: IDDET 0: IDDET bit type is changed from r/w to rw. RSSI PSS.1~12512 ,1~5 0: ICS;1: IDDET 0: 0: 0: ID2 1: ID20 2: ID21 3: ID22 0: 1: 1 2: 3 3: 5 0: AGC 1: AGC 0: 1: bit type is changed from r/w to rw. RSSI 1~12 1: 0: 1: 0: 1: AGC 0: AGC 1: 0: bit type is changed from r/w to rw. RSSI bit type is changed from r/w to rw. 0: 1:1 2:2 3:4 bit type is changed from r/w to rw. 0: 1: 1~10 NID1ID 0~168 ICSIDDET1~12 1: 0: 0:ICS 1: ID DETECT 1: ID 0: ID 1: FDD 0: TDD 1: 0: 1: 0: 1: AGC 0: AGC 1: 0: RSSI 0: 1:1 2:2 3:4 1~12 PSSSSSM0~4 1: FDD 0: TDD 1: 0: 1: 0: 1: 0: 1: AGC 0: AGC 1: 0: RSSI 0:1ms 1:2ms 2:3ms 3:4ms 4:5ms 00: 01: 0 10: 5 1~5 ID1 0~167 ID2 0~2 0: AGC 1: AGC 0: 1: RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 RSSI -8~7 1: 0: 1: 1 0: 1 1:RSSI 0: RSSI 1: 0: 1: AXIDMA 0: AXIDMA 1:TXRX 0: TXRX 1: 0: 1: 0: 1:SSS 0: SSS 1:PSS 0: PSS 1:PSS 0: PSS RSSI PSSTXRX0PSSSSSTXRX 00~19200 0~200 0~200 0~200 0~200 0~200 0~200 0~200 0~200 0~200 0~200 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 PSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS PSSID-32768~32767 PSSID-32~31 IDCP 1EXTEND CP 0NORMAL CP ID(SSS)15 00 SSS NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 NID1 0-167 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 ID 0~9599 SSSMAX 10 0:31 1:61 2:127 IDDET PSSASSIST_WINMAX_NUMPOS_NUMPOS_NUM 2b00:2 2b01:4 2b10:8 others:2 0-127 Q3 PSS2 -1024~1023 PSS1 -1024~1023 PSS0 -1024~1023 PSS4 -1024~1023 PSS3 -1024~1023 PSS -4096~4095 PSS -4096~4095 PSS -4096~4095 PSS -4096~4095 RSSI PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 PSS -32~31 -8~7 -8~7 -8~7 -8~7 FFT/IFFT () 4`b0000 4`b0001 4`b0010 FFT/IFFT PSS/SSS 4`b0000 4`b0001 4`b0010 1 0 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 SSS SSS SSS 9600 0 11 22 -11 -22 0 SSS 00 11 1212 PSSPSSSSS 00 11 1212 PSSPSSSSS 0~200 PSSRSSIPSSSSS RSSI PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 SSS IDDET 0~11 0-8 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSS PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID PSSPSSSSSID NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 NID1 0-167 IDCP 1EXTEND CP 0NORMAL CP ID(SSS) 15 00 NID2 0-2 bit type is changed from rw1c to rc. 1: 0: bit type is changed from rw1c to rc. 1: 0: bit type is changed from rw1c to rc. 1:1 0: bit type is changed from rw1c to rc. 1:RSSI 0: RSSI bit type is changed from rw1c to rc. 1: 0: bit type is changed from rw1c to rc. 1:AXIDMA 0: bit type is changed from rw1c to rc. 1:TXRX 0: bit type is changed from rw1c to rc. 1: 0: bit type is changed from rw1c to rc. 1: 0: bit type is changed from rw1c to rc. 1:SSS 0: bit type is changed from rw1c to rc. 1:PSS 0: bit type is changed from rw1c to rc. 1:PSS 0: 1 0 1 0 1 0 1 0 PSS 1 0 PSS 1 0 0~1023 0: 1: FFT 0: FFT 1: FFT(1024),FFT : 0: 1: , 1~999 0~999 0: 5M 1: 10M 2: 20M : 5M 0: 5ms 1: 5ms 0: 5ms 1: 5ms ; 0:[19:0],20bit 1:[20:1],20bit 12:[31:12],20bit :12; ,;I^2+Q^2=PWR(32bit) 0:[31:15],16bit 1:[31:14],16bit 15:[31:0],16bit 0~49 0~50 20MHz 0: 1: 15MHz 0: 1: 10MHz 0: 1: 5MHz 0: 1: 3MHz 0: 1: 1.4MHz 0: 1: 200KHz 0: 1: ,1~11 Selectbinnum0~511 selectbinnum0~511 0~99 0~99 0~99 0~99 0~99 0~99 0~99 0~15 0~15 0~15 0~15 0~15 0~15 0~15 0~127 AGC 2 1 bit type is changed from r/w to rw. PSSRSSI0~47990~9599 bit type is changed from r/w to rw. PSSRSSI0~47990~9599 PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI PSSRSSI 1PWR1 1PWR0 1 1AGC data_drive 0data_drive 1data_drive DMACSI 0 1 CSI 0 1 cp 0 1 FH 5d0fh[11:0] 5d1fh[12:1] 5d2fh[13:2] 5d16fh[27:16] othersfh[28:17] CSI-RSCRS 0CSI-RS 1CRS LS/FH/ 0LS/FH/ 1 RIri_sel=1PMI 0RI=1 1RI=2 PMIRI 0RI 1RI PMI 0PMI 1PMI RI 0RI 1RI RIRI 0RI=1 1RI 6/15/25/50/75/100PRB total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB CSI-RS1248CRS24 01RIPMI 12 24 38 ((1-th2)/(1+th2))^2RI01Q15th240 ((1-th1)/(1+th1))^2RI01Q15th160 RI=2248i1bitmapbit0~bit150~151 RI=1248i1bitmapbit0~bit150~151 RI=28i2bitmapbit0~bit150~151 RI=18i2bitmapbit0~bit150~151 0 1 OFDM0CCSI-RS OFDM1CCSI-RS bit type is changed from rw1c to rc. bit type is changed from rw1c to rc. 0 1 sw_pause_en=1 0 1 0 10 0 1 bit type is changed from rw1c to rc. 0 1 bit type is changed from rw1c to rc. 0 1 RIPRBRI 0RI=1 1RI=2 PMIPRBPMI 1 2 1 2 cp 0 1 FH 5d0fh[11:0] 5d1fh[12:1] 5d2fh[13:2] 5d16fh[27:16] othersfh[28:17] CSI-RSCRS 0CSI-RS 1CRS LS/FH/ 0LS/FH/ 1 RIri_sel=1PMI 0RI=1 1RI=2 PMIRI 0RI 1RI PMI 0PMI 1PMI RI 0RI 1RI RIRI 0RI=1 1RI 6/15/25/50/75/100PRB total_nrb=6/15/25/50/75/100sub_nrb=6/2/2/3/4/4 PRB CSI-RS1248CRS24 01RIPMI 12 24 38 ((1-th2)/(1+th2))^2RI01Q15th240 ((1-th1)/(1+th1))^2RI01Q15th160 RI=2248i1bitmapbit0~bit150~151 RI=1248i1bitmapbit0~bit150~151 RI=28i2bitmapbit0~bit150~151 RI=18i2bitmapbit0~bit150~151 0 1 OFDM0CCSI-RS OFDM1CCSI-RS 0PUSCH 1PUSCH 0 1 0PUSCH 1PUSCH 0 1 bit type is changed from rw1c to rc. DCI 0 1 bit type is changed from rw1c to rc. ULPC 0 1 ID DCI Format 0 6PRB5bit 15PRB7bit 25PRB9bit 50PRB11bit 75PRB12bit 100PRB13bit DCI Format 4 6PRB6bit 15PRB7bit 25PRB10bit 50PRB12bit 75PRB13bit 100PRB14bit PUSCH 0 1 0 1 00 11 0TDD 1FDD type0PRBtype1PRB type0type0Type20type1PRB type0PRBLen1type1PRB type0type0Type21type1PRB PUSCHPRB type0PRBLen = Len1 = Len2 type1PRBLen = Len1+Len2 -6363 UE-3033dBm 0000 0010.4 0100.5 0110.6 1000.7 1010.8 1100.9 1111 UE 0Ks0 1Ks1.25 000PRACH 001PUSCH 010PUCCH 011PUSCHPUCCH 100SRS 101PUSCHSRS 110PUCCHSRS 111PUSCHPUCCHSRS 0 1 -140dBm-44dBm -60dBm50dBm PUSCH-134dBm31dBm PUSCHPRB PUSCH121200 PUSCH9101112 CQI050 CRCCQI PUCCH-135-89 0SR 1SR -6363 0CP 1CP -22 -26 0 1 PUCCH 000PUCCH1 001PUCCH1a 010PUCCH1b 011PUCCH2 100PUCCH2a 101PUCCH2b 110PUCCH3 111RESERVED HARQ SRS SRSPUSCH 0140 000 012 104 116 000 01-3 108 11RESERVED PRACH 0000-120 0001-118 0010-116 0011-114 0100-112 0101-110 0110-108 0111-106 1000-104 1001-102 1010-100 1011-98 1100-96 1101-94 1110-92 1111-90 SRS PUSCH PRACH PUCCH PUSCH SRS PUCCH UE PHR Type2 PHR Type1 TF_CI max384 max2800 IDmax10 1 0 0 1 max2800 IDmax10 CORR_MAX CORR_SUM 0 1 bit type is changed from rw1c to rc. 0 1 0~30720TS -30720x13.8 ~30720x13.8TS 0:catm 1:cat1 0:1.4M 1:3M 2:5M :5M PRSPRB100PRB200PRB0~199 0 1 0512 1256 0occasion 1occasion [0]ID1 [23]ID24 ID 0ID 1ID [0]ID1 [23]ID24 ID 0ID 1ID [0]ID1 [23]ID24 eg1IQ occasionAGC occasionID10~120ID1SF_ID1 occasionID210~9 PRSID2ID 0~4095 ID1 012 14 ID1CP 0CP 1CP ID1certain-8192x3x2 TS ~8192x3x2TS1 ID1uncertain0 TS ~1024x3x2TS2 occasionID20~120ID2SF_ID2 occasionID210~9 PRSID2ID 0~4095 ID2 012 14 ID2CP 0CP 1CP ID2certain-8192x3x2 TS ~8192x3x2TS1 ID2uncertain0 TS ~1024x3x2TS2 occasionID30~120ID3SF_ID3 occasionID310~9 PRSID3ID 0~4095 ID3 012 14 ID3CP 0CP 1CP ID3certain-8192x3x2 TS ~8192x3x2TS1 ID3uncertain0 TS ~1024x3x2TS2 occasionID40~120ID4SF_ID4 occasionID410~9 PRSID4ID 0~4095 ID4 012 14 ID4CP 0CP 1CP ID4certain-8192x3x2 TS ~8192x3x2TS1 ID4uncertain0 TS ~1024x3x2TS2 occasionID50~120ID5SF_ID5 occasionID510~9 PRSID5ID 0~4095 ID5 012 14 ID5CP 0CP 1CP ID5certain-8192x3x2 TS ~8192x3x2TS1 ID5uncertain0 TS ~1024x3x2TS2 occasionID60~120ID6SF_ID6 occasionID610~9 PRSID6ID 0~4095 ID6 012 14 ID6CP 0CP 1CP ID6certain-8192x3x2 TS ~8192x3x2TS1 ID6uncertain0 TS ~1024x3x2TS2 occasionID70~120ID7SF_ID7 occasionID710~9 PRSID7ID 0~4095 ID7 012 14 ID7CP 0CP 1CP ID7certain-8192x3x2 TS ~8192x3x2TS1 ID7uncertain0 TS ~1024x3x2TS2 occasionID80~120ID8SF_ID8 occasionID810~9 PRSID8ID 0~4095 ID8 012 14 ID8CP 0CP 1CP ID8certain-8192x3x2 TS ~8192x3x2TS1 ID8uncertain0 TS ~1024x3x2TS2 occasionID90~120ID9SF_ID9 occasionID910~9 PRSID9ID 0~4095 ID9 012 14 ID9CP 0CP 1CP ID9certain-8192x3x2 TS ~8192x3x2TS1 ID9uncertain0 TS ~1024x3x2TS2 occasionID100~120ID10SF_ID10 occasionID1010~9 PRSID10ID 0~4095 ID10 012 14 ID10CP 0CP 1CP ID10certain-8192x3x2 TS ~8192x3x2TS1 ID10uncertain0 TS ~1024x3x2TS2 occasionID110~120ID11SF_ID11 occasionID1110~9 PRSID11ID 0~4095 ID11 012 14 ID11CP 0CP 1CP ID11certain-8192x3x2 TS ~8192x3x2TS1 ID11uncertain0 TS ~1024x3x2TS2 occasionID120~120ID12SF_ID12 occasionID1210~9 PRSID12ID 0~4095 ID12 012 14 ID12CP 0CP 1CP ID12certain-8192x3x2 TS ~8192x3x2TS1 ID12uncertain0 TS ~1024x3x2TS2 occasionID130~120ID13SF_ID13 occasionID1310~9 PRSID13ID 0~4095 ID13 012 14 ID13CP 0CP 1CP ID13certain-8192x3x2 TS ~8192x3x2TS1 ID13uncertain0 TS ~1024x3x2TS2 occasionID140~120ID14SF_ID14 occasionID1410~9 PRSID14ID 0~4095 ID14 012 14 ID14CP 0CP 1CP ID14certain-8192x3x2 TS ~8192x3x2TS1 ID14uncertain0 TS ~1024x3x2TS2 occasionID150~120ID15SF_ID15 occasionID1510~9 PRSID15ID 0~4095 ID15 012 14 ID15CP 0CP 1CP ID15certain-8192x3x2 TS ~8192x3x2TS1 ID15uncertain0 TS ~1024x3x2TS2 occasionID160~120ID16SF_ID16 occasionID1610~9 PRSID16ID 0~4095 ID16 012 14 ID16CP 0CP 1CP ID16certain-8192x3x2 TS ~8192x3x2TS1 ID16uncertain0 TS ~1024x3x2TS2 occasionID170~120ID17SF_ID17 occasionID1710~9 PRSID17ID 0~4095 ID17 012 14 ID17CP 0CP 1CP ID17certain-8192x3x2 TS ~8192x3x2TS1 ID17uncertain0 TS ~1024x3x2TS2 occasionID180~120ID18SF_ID18 occasionID1810~9 PRSID18ID 0~4095 ID18 012 14 ID18CP 0CP 1CP ID18certain-8192x3x2 TS ~8192x3x2TS1 ID18uncertain0 TS ~1024x3x2TS2 occasionID190~120ID19SF_ID19 occasionID1910~9 PRSID19ID 0~4095 ID19 012 14 ID19CP 0CP 1CP ID19certain-8192x3x2 TS ~8192x3x2TS1 ID19uncertain0 TS ~1024x3x2TS2 occasionID200~120ID20SF_ID20 occasionID2010~9 PRSID20ID 0~4095 ID20 012 14 ID20CP 0CP 1CP ID20certain-8192x3x2 TS ~8192x3x2TS1 ID20uncertain0 TS ~1024x3x2TS2 occasionID210~120ID21SF_ID21 occasionID2110~9 PRSID21ID 0~4095 ID21 012 14 ID21CP 0CP 1CP ID21certain-8192x3x2 TS ~8192x3x2TS1 ID21uncertain0 TS ~1024x3x2TS2 occasionID220~120ID22SF_ID22 occasionID2210~9 PRSID22ID 0~4095 ID22 012 14 ID22CP 0CP 1CP ID22certain-8192x3x2 TS ~8192x3x2TS1 ID22uncertain0 TS ~1024x3x2TS2 occasionID230~120ID23SF_ID23 occasionID2310~9 PRSID23ID 0~4095 ID23 012 14 ID23CP 0CP 1CP ID23certain-8192x3x2 TS ~8192x3x2TS1 ID23uncertain0 TS ~1024x3x2TS2 occasionID240~120ID24SF_ID24 occasionID2410~9 PRSID24ID 0~4095 ID24 012 14 ID24CP 0CP 1CP ID24certain-8192x3x2 TS ~8192x3x2TS1 ID24uncertain0 TS ~1024x3x2TS2 FFT9 FFT8 FFT7 FFT6 FFT5 FFT4 FFT3 FFT2 FFT1 2b00:bit[29:14] 2b01:bit[30:15] 2b10:bit[31:16] 2b11:bit[32:17] IFFT8 IFFT7 IFFT6 IFFT5 IFFT4 IFFT3 IFFT2 FFT 2b00:bit[29:14] 2b01:bit[30:15] 2b10:bit[31:16] 2b11:bit[32:17] 0phasemax,2 1phasephasemax,2 0~31,3 IFFT7 IFFT6 IFFT5 IFFT4 IFFT3 IFFT2 FFT 2b00:bit[29:14] 2b01:bit[30:15] 2b10:bit[31:16] 2b11:bit[32:17] 0~32x2,2/3 0~32x2,2/3 0~32x2,1 0~32x2,1 0: 1: 0: OTDOA/ 1: OTDOA bit type is changed from rw1c to rc. 1: 0: Bit[n]: 0: 1: Bit01 Bit78 axidma OTDOA Ts AD_ON16Ts 16Ts IRT/AFCPDPPWR/RSSI MAX:20 IRT/AFC 20bitbit 0 1 IRTPHASE IRTPHASE16Ts IRT(-256~25516TsOFFSET) AFC-4096~2095TsOFFSET xAGC 2AGC 1AGC 0AGC 5AGC 4AGC 3AGC 8AGC 7AGC 6AGC 11AGC 10AGC 9AGC 14AGC 13AGC 12AGC 17AGC 16AGC 15AGC 19AGC 18AGC 0: 0 1FDD90TDD05 5 05 15 40MS schedulingInfoSIB1-BR-r13 phich-Config: PHICH resource phich-Config: PHICH duration dl-Bandwidth PORT 0: 2PORT0PORT14PORT0PORT1PORT2PORT3 1: PORT0 2: PORT1 0:1 1:2 2:4 ID0~504 PBCH 0: 1: CP 0: NORMAL CP 1: EXTEND CP FDD/TDD 0: TDD 1: FDD AFC 0: 1 1: 2 2: 4 IRT 0: 1 1: 2 2: 4 IRT 0 1SCALE IRT0~31 IRTSCALE 0 1 IRT0~63 AFCOFDM 0:1 1:2 2:3 3:4 AFC 0: 1RE 1: 1PRB 2: 2PRB 3: 3PRB 4: 6PRB 0 1 AFC 0FIRST 1FIRST IRT 0FIRST 1FIRST AFC 0 1 IRT 0 1 0 1 PBMEAS 0 1 IRT_OUTTs SINR SINRDB POWER POWER AFC_OUTHz SIGMA POWER SINR SINRDB RSSI(DBQ4) RSSI(DBQ4) RSSI(DBQ4) AGC_OUT(DBQ0) AFCAFC AFCAFC AFCAFC AFCAFC bit type is changed from rw1c to rc. MEM bit type is changed from rw1c to rc. MEM bit type is changed from rw1c to rc. 1: AFC 0: bit type is changed from rw1c to rc. 1: IRT 0: bit type is changed from rw1c to rc. 1:REC 0: AFC RSRP 16Q4 IRT RSRP 16Q4 AFC RSRQ 16Q4RSRPRSSI AFC RSSI 16Q4 PBMEAS MEM ADDR IRT IRT IRTPHASE 0 1 Dump 1 0 Tx Trace 1 0 IDDET offline 1 0 ODTOA 1 0 RX 1 0 DL offline 1 0 3h0:420M/15M 3h1:810M 3h2:165M 3h3:323M 3h4:641.4M Others: 4 IDDET offline 1 0 3h0:420M/15M 3h1:810M 3h2:165M 3h3:323M 3h4:641.4M Others: 4 DMA_req7 1 0 DMA_req6 1 0 DMA_req5 1 0 DMA_req4 1 0 DMA_req3 1 0 DMA_req2 1 0 DMA_req1 1 0 DMA_req0 1 0 Capt_err34 1 0 Capt_err12 1 0 Mem56 finish 1 0 Mem56 pang 1 0 Mem56 ping 1 0 Mem34 finish 1 0 Mem34 pang 1 0 Mem34 ping 1 0 Mem12 finish 1 0 Mem12 pang 1 0 Mem12 ping 1 0 bit type is changed from rw1s to rs. Capt_err34 1 0 bit type is changed from rw1s to rs. Capt_err12 1 0 bit type is changed from rw1s to rs. Mem56 finish 1 0 bit type is changed from rw1s to rs. Mem56 pang 1 0 bit type is changed from rw1s to rs. Mem56 ping 1 0 bit type is changed from rw1s to rs. Mem34 finish 1 0 bit type is changed from rw1s to rs. Mem34 pang 1 0 bit type is changed from rw1s to rs. Mem34 ping 1 0 bit type is changed from rw1s to rs. Mem12 finish 1 0 bit type is changed from rw1s to rs. Mem12 pang 1 0 bit type is changed from rw1s to rs. Mem12 ping 1 0 bit type is changed from rw1c to rc. Capt_err34 1 0 bit type is changed from rw1c to rc. Capt_err12 1 0 bit type is changed from rw1c to rc. Mem56 finish 1 0 bit type is changed from rw1c to rc. Mem56 pang 1 0 bit type is changed from rw1c to rc. Mem56 ping 1 0 bit type is changed from rw1c to rc. Mem34 finish 1 0 bit type is changed from rw1c to rc. Mem34 pang 1 0 bit type is changed from rw1c to rc. Mem34 ping 1 0 bit type is changed from rw1c to rc. Mem12 finish 1 0 bit type is changed from rw1c to rc. Mem12 pang 1 0 bit type is changed from rw1c to rc. Mem12 ping 1 0 bit type is changed from rw1c to rc. Capt_err34 bit type is changed from rw1c to rc. Capt_err12 bit type is changed from rw1c to rc. Mem56 finish bit type is changed from rw1c to rc. Mem56 pang bit type is changed from rw1c to rc. Mem56 ping bit type is changed from rw1c to rc. Mem34 finish bit type is changed from rw1c to rc. Mem34 pang bit type is changed from rw1c to rc. Mem34 ping bit type is changed from rw1c to rc. Mem12 finish bit type is changed from rw1c to rc. Mem12 pang bit type is changed from rw1c to rc. Mem12 ping Mem12 Mem34 Mem12 Mem56 Mem12 pang 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem12 pang Mem12 ping 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem12 ping Mem34 pang 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem34 pang Mem34 ping 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem34 ping Mem56 pang 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem56 pang Mem56 ping 000IDLE 001MEM 010MEM 011DMA 100MEM Others: IDLE Mem56 ping Err 0MEM12 Ping 1MEM12 Pang Error(ERR Err 0MEM34 Ping 1MEM34 Pang Error(ERR BB2G Ram Space
This RAM is used in 2G mode as ACC buffer and code space.
In NB mode, it can also be used as TCM memory space. This field is used for setting the first polynomial to encode or the CRC computation
First polynomial to encode :
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output)
Cyclic code :
000 = D8 + D4 + D3 + D2 + 1
001 = D3 + D + 1
010 = D14 + D13 + D5 + D3 + D2 +1
011 = D6 + D5 + D3 + D2 + D1 + 1
100 = D10 + D8 + D6 + D5 + D4 + D2 + 1
101 = D16 + D12 + D5 + 1
110 = (D23 + 1)*(D17 + D3 + 1)
111 = reserved Second polynomial to encode :
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output) Third polynomial to encode:
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output) Fourth polynomial to encode:
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output) Fith polynomial to encode:
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output) Sixth polynomial to encode:
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No polynomial code used (input connected to output) RSC (Recursive Systematic Convolutional) polynomial code:
000 = G0
001 = G1
010 = G2
011 = G3
100 = G4
101 = G5
110 = G6
111 = No RSC Number of polynomial code to process:
0x0 = 0
0x1 = 1 (First Poly)
0x2 = 2 (First poly and second Poly)
0x3 = 3 (First poly, second poly, third Poly)
0x6 = 6 (first Poly to sixth Poly)
0x7 = reserved Enable Puncturing
0 = No puncturing (puncturing disabled)
1 = Enable puncturing Number of inputs bits to process
0x01 = 1
0x02 = 2
0x03 = 3
...
0xFD = 253
0xFE = 254
0xFF = 255
0x100 = 256
...
0x1BF = 447
0x1C0 = 448 When 1 the bb_cp2 is running LRAM address for the next access
Automatically incremented after each access Select LRAM for the next access
0 = Puncturing LRAM
1 = Data LRAM CRC code LSB bits CRC code MSB bits CP2 register access selection bit
0= All registers are only accessible through the APB bus
1= All registers are only accessible by the BCPU through the CP2 bus LRAM Data. This register is used for access to the puncturing LRAM or to the Data LRAM.
All access into this register, increment the LRAM_ADDR register. // changing xml generated defines #undef BB_CP2_ENABLE_PUNCTURING #undef BB_CP2_LRAM_DATA #undef BB_CP2_BIT_NUMBER #define BB_CP2_ENABLE_PUNCTURING(n) (((n)&1)<<24) /// BB_CP2 address mapping #define BB_CP2_CTRL 0 #define BB_CP2_BIT_NUMBER 1 #define BB_CP2_STATUS 2 #define BB_CP2_LRAM_ADDR 3 #define BB_CP2_CRC_CODE_LSB 4 #define BB_CP2_CRC_CODE_MSB 5 #define BB_CP2_LRAM_DATA 0 #define BB_CP2_LRAM_PUNC (0<<5) #define BB_CP2_DATA_LRAM (1<<5) /* BB_CP2 ACCESSES */ // macro for converting a constant to a string #define CT_CONVERT_TO_STRING(x) #x // control register -> GPR #define CT_BB_CP2_RD_CTRL_REG(regaddr, n) asm volatile("cfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n))) // GPR -> control register #define CT_BB_CP2_WR_CTRL_REG(regaddr, n) asm volatile("ctc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n))) // general register -> GPR #define CT_BB_CP2_RD_GNRL_REG_GPR(regaddr, n) asm volatile("mfc2 %0, $" CT_CONVERT_TO_STRING(regaddr) :"=r"((n))) // GPR -> general register #define CT_BB_CP2_WR_GNRL_REG_GPR(regaddr, n) asm volatile("mtc2 %0, $" CT_CONVERT_TO_STRING(regaddr) ::"r"((n))) // general register -> memory #define CT_BB_CP2_RD_GNRL_REG_MEM(regaddr, out) asm volatile("swc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((out))) // memory -> general register #define CT_BB_CP2_WR_GNRL_REG_MEM(regaddr, in) asm volatile("lwc2 $" CT_CONVERT_TO_STRING(regaddr) ", 0(%0)"::"r"((in))) BCPU Irq Lines If cause is not null and interrupt are enabled then the interrupt line 0 is driven on the system CPU.
The cause for the Irq sources, one bit for each module's irq source.
The cause is the actual Irq source masked by the mask register. The status for the level Irq sources, one bit for each module's irq source.
The status reflect the actual Irq source. Writing '1' sets the corresponding bit in the mask register to '1'.
Reading gives the value of the mask register. Writing '1' clears the corresponding bit in the mask register to '0'.
Reading gives the value of the mask register. This is the Main Irq source it drive the system CPU interrupt line 0.
This bit comes from the modules irq and is masked by the Mask and SC registers. This is the WDT Irq source it drive the system CPU interrupt line 1.
This bit comes from watchdog module. This is the debug Irq source, the value written here drives the system CPU interrupt line 4. This is the Host Irq source it drive the system CPU interrupt line 5.
This bit is controlled by the host internal register. Status of the Interrupt enable semaphore bit. Interrupt enable semaphore, used for critical section.
Read returns its value and then clears it to '0' disabling interrupts.
Write the read value to restore the previous state, this will exit the critical section. Each bit to '1' in that registers allows the correcponding interrupt to wake up the System CPU (i.e.: Reenable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section) Writing '1' to this bit will put the BCPU to sleep (i.e.: Disable it's clock, see CLOCK_BB_ENABLE and CLOCK_BB_DISABLE registers in general registers section) Writing '1' sets the corresponding bit in the mask register to '1'.
Reading gives the value of the mask register. Writing '1' clears the corresponding bit in the mask register to '0'.
Reading gives the value of the mask register. Writing '1' clears the corresponding Pulse IRQ.
Pulse IRQ are set by the modules and cleared here. The status for the Pulse Irq sources, one bit for each module's irq source.
The status reflect the actual Irq source. BB Rom Space
This rom is used for BCPU. Base address of block in int_Rom patched (corresponding data are read from int_SRam) BB Rom patch Ram Space
Used for store the patch instead of rom, when patch is valid write 1 will enable CHOLK module 1:level INT will be masked, 0:level INT will not be masked 1: Complex mode ; 0: Real mode RESI GAIN RESI2 GAIN OGRS_GAIN OLES1_GAIN OLES2_GAIN COEF_GAIN GRAD_GAIN GOPS_GAIN OLES3_GAIN ITER_THRE1 Matrix COVA base addr in BBSRAM CE base addr in BBSRAM COEF base addr in BBSRAM Matrix Row Number, maximal is 24 for Real, and 16 for Complex Matrix COVA effective element number - 1 to read MAXIMAL iteration number - 1 for CHOLK CHOLK Done status, ACC enable and SW write this bit will clear this Done status, hardware will set this bit when done. write 0 to this bit will clear CHOLK level RAW interrupt source bit, write 1 will not. read this bit will get raw cholk INT source bit read this bit will get cholk INT status after masking. INT_out = INT_RAW and ~MASK Writing a '1' in this register triggers an A5 process. Ignored if the module is already processing. Auto-reset bit Selects the appropriate algorithm 1 when running, 0 in other case. 1 when data block ready (Ciphering processed), reseted when the data register is read. Cipher key Kc, LSB bit [31:0]. Cipher key Kc, MSB bit [31:0]. Count register, this field represent the TDMA frame number. Data block2 bit[31:0] Data block2 bit[63:32] Data block2 bit[95:64] Data block2 bit[113:96] Select Between A5/1-A5/2 and A5/3 Ciphering Block Initialize A5/3 Ciphering Select Ciphering Blcok Size Switch Between A5/1 and A5/2 Algorithm if A5/1-A5/2 Block is Selected Status and Activation of Ciphering Block Cipher Key0 Cipher Key1 Cipher Key2 Cipher Key3 Cipher Key4 Cipher Key5 Cipher Key6 Cipher Key7 GSM mode:00001111 EDGE mode:11110000 CB=0000 CD=0 CE=0000000000000000 cipher_a53 internal Spram space Control setting. y, i.e. numerator of atan computation. Control setting. x, i.e. denominator of atan computation. The start signal. Use the posedge of this signal. Status is set to 1 when an operation is finished. . angle. The actual value is angle*pi/4 amplitude. amplitude only. Control setting. comand type. Control setting. Number of internal loop iteration. Control setting. Number of nb_symbol. Control setting. Number of shift bits. address register 0. address register 1. address register 2. address register 3. address register 4. address register 5. data register 0. data register 1. data register 2. data register 3. for ircombine idx0 for ircombine idx1 for ircombine idx2 data register 5. Status is set to 1 when an operation is finished. Control setting. Number of A row. Control setting. Number of B column. Control setting. Number of A column and B row. Control setting. Number of shift bit after multiply. Number of bits to be (De)Interleaved. This value gives the write offset (in number of bursts) to be added to a Burst Base address (ignored for Type 1b). For normal operation, this offset should be even (lsb will be ignored). Selects (de-)interleaving type. TCH/FS, TCH/EFS, FACCH/F, TCH/F2.4, TCH/AFS (speech, ratscch, sid_first) SACCH, TCH/AFS(sid_update), PDTCH(CS-1 to CS-4), BCCH, PCH, AGCH, PACCH, PBCCH, PAGCH, PPCH, PNCH, PTCCH/D FACCH/H TCH/HS and TCH/AHS TCH/HS and TCH/AHS TCH/F14.4, TCH/F9.6, TCH/F4.8, TCH/H4.8, and TCH/H2.4 Sets the interrupt mask ('1': interruption enabled) Starts the de-interleaving process. Starts the interleaving process. This bit is high when a (de-)interleaving process is ongoing. It stays high if the module is stalled during operation. This is the start address of the burst buffer in SRAM This is the start address of the frame buffer in SRAM. This bit is the unmasked version of the IT_CAUSE bit. This bit is set when the ITLV module finishes an ongoing operation. It can be masked by setting ITLV_CMD(IT_MASK) to '1'. Resetting this bit is done by writing in IT_CLEAR register. IT_CAUSE is the image of the ITLV_DONE_H interrupt line to the CPU. Setting this bit to '1' resets the Interleaver's interrupt. In read mode this register contains the sample received on the Rx chain. I component is located on bit[15:0] and Q component is located on bit[31:16].
This register accesses to the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data sample arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overflow error will also occur.
The data written[29:0] into this register is the data transmitted. Any attempt to write data when the FIFO is full results in the write data being lost. Turn on/off the rf_if interface Analog more selected DigRF mode selected Turn on/off the DigRF mode Disable (mask) Rx fifo overflow interrupt Enable Rx fifo overflow interrupt Rx Fifo Overflow interrupt Enable Calibration bypass No Swap Swap I/Q Rx swap I/Q No forced, Rx_On output controlled by TCO_RX_ON signal from the TCU Forced ADC on;Rx_On output always high Force Rx On. This bit is used only with the analog option. No forced, decimator controlled by Rx_dec_on signal from the TCU Forced; decimator always on Force Decimator On Force start of calibation in receive mode
Writing a 1 to this bit launch the calibration phase. Write only bit, this bit doesn't need to be cleared. Writing a 1 to this bit resets and flush the receive Fifo.
Write only bit, this bit doesn't need to be cleared. Disable (mask) Tx fifo overflow interrupt Enable Tx fifo overflow interrupt Tx Fifo Overflow interrupt Enable Disable (mask) Tx fifo undeflow interrupt Enable Tx fifo underflow interrupt Tx Fifo Underflow interrupt Enable: No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU Forced DAC on; Tx_On output always high Force DAC On. This bit is used only with the analog option. No forced, Tx_On output controlled by TCO_TX_ON signal from the TCU Forced DAC Off; Tx_On output always low Force DAC Off. This bit is used only with the analog option. No forced, Tx_Oen controlled by TCO_TX_OEN signal from the TCU Forced; Tx_Oen always high, Low pass output in HZ Force Tx Oen. This bit is used only with the analog option. No forced, transmit serial interface controlled by TCO_GMSK_ON signal from the TCU Forced; serializer always enabled Force GMSK On. No Swap Swap I/Q Tx swap I/Q. This bit is used only with the analog option. Writing a 1 to this bit resets and flush the transmit Fifo.
Write only bit, this bit doesn.t need to be cleared. One sample per symbol Two samples per symbol Rx rate for DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
0 = No inversion
1 = Invert clock polarity Tx mode for the DigRF interface. This bit is used only when DigRF is enabled (DigRF Enabled) Change the polarity of the DigRF Rx clock. This bit is used only when DigRF is enabled (DigRF Enabled)
0 = No inversion
1 = Invert clock polarity Shift input sample in DigRF mode only.
The Rx sample are on 16-bit, this field select a variable of bit among 16.
000 = 16-bit selected
001 = 15-bit selected
010 = 14-bit selected
011 = 13-bit selected
100 = 12-bit selected Select the sample alignement in DigRF mode only..
0 = MSB aligned sample
1 = LSB aligned sample Those bits indicate the number of data available in the Rx Fifo. Those bits indicate the number of data available in the Tx Fifo. Those data will be sent. Rx overflow cause register
This bit indicates that an interruption was generated when the Rx fifo is overflow.
This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. Tx overflow cause register
This bit indicates that an interruption was generated when the Tx fifo is overflow.
This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. Tx underflow cause register
This bit indicates that an interruption was generated when the Tx fifo is underflow.
This bit is cleared when the Tx_underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written. This bit indicates that the receiver received a new sample when the FIFO was already full.
The new sample is discarded. This bit is cleared when the Rx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written This bit indicates that the user tried to write on the FIFO while it was already full.
This bit is cleared when the Tx_Overflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written This bit indicates that the modulator tried to read on the FIFO while it was empty.
This bit is cleared when the Tx_Underflow_Int field in the RF_IF_INTERRUPT_CLEAR register is written Clear Rx Interrupt Overflow interrupt. Clear Tx Interrupt Overflow interrupt. Clear Tx Interrupt Underflow interrupt. Number of symbol to transmit 0 for GMSK, 1 for 8PSK Indicate an end of the transmit for this current burst Rx offset measured after calibration for I channel Rx offset measured after calibratio for Q channel Rx Gain digital Rx Gain analog Rx Gain enable Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Burst size on AHB bus
0 = Single access
1 = burst Access (4 words). Set FIFO mode .
0 = no fifo mode, transfer stop when the current transfer counter reaches zero. Channel must be re-enabled for future transfer.
1 = Fifo mode, when the current AHB address counter reaches the end address of the FIFO. AHB address counter is reloaded with the initial value. In FIFO mode channel is not disabled at the end of the transfer. In no fifo mode the channel is automatically disabled at the end of the transfer. In fifo mode the channel is disabled only when disabled write is performed in the control register. When 1 the fifo is empty Cause interrupt half tc when fifo mode is enable. Half of TC interrupt when fifo mode is enable status bit. Cause interrupt End of TC. Cause interrupt End of FIFO. Cause interrupt Half Transfer Count (This interruption is generated when the IFC has transferred 96 word). End of TC interrupt status bit. End of FIFO interrupt status bit. Half TC interrupt status bit. Current value of transfer counter. AHB Start Address. The last page address of the FIFO, it is the first address not used for the FIFO. The start address of the FIFO is specified by the register AHB_ADDR and the last page address of the FIFO is specified by this field. The size of the fifo (END_ADDR - START_ADDR) must be a multiple of burst of 4x32-bits. Transfer Count
In no FIFO mode, this bit indicated the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per transfer.
In FIFO mode this field define, after how many transfer an interrupt in generated. End TC Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. Half TC Mask interrupt. When one this interrupt is enabled NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is enabled Write one to clear end of TC interrupt. Write one to clear end of FIFO interrupt. Write one to clear end of Half TC interrupt. Write one to clear end of Half TC (the real one) interrupt. Current AHB address value. Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Burst size on AHB bus
0 = Single access
1 = burst Access (4 words). Set FIFO mode .
0 = no fifo mode, transfer stop when the current transfer counter reaches zero. Channel must be re-enabled for future transfer.
1 = Fifo mode, when the current AHB address counter reaches the end address of the FIFO. AHB address counter is reloaded with the initial value. In FIFO mode channel is not disabled at the end of the transfer. In no fifo mode the channel is automatically disabled at the end of the transfer. In fifo mode the channel is disabled only when disabled write is performed in the control register. When 1 the fifo is empty Cause interrupt half tc when fifo mode is enable. Half of TC interrupt when fifo mode is enable status bit. Cause interrupt End of TC. Cause interrupt End of FIFO. Cause interrupt Half Transfer Count (This interruption is generated when the IFC has transferred 96 word). End of TC interrupt status bit. End of FIFO interrupt status bit. Half TC interrupt status bit. Current value of transfer counter. AHB Start Address. The last page address of the FIFO, it is the first address not used for the FIFO. The start address of the FIFO is specified by the register AHB_ADDR and the last page address of the FIFO is specified by this field. The size of the fifo (END_ADDR - START_ADDR) must be a multiple of burst of 4x32-bits. Transfer Count
In no FIFO mode, this bit indicated the transfer size in 32-bits word to perform. Up to 2^18 32-bits word per transfer.
In FIFO mode this field define, after how many transfer an interrupt in generated. End TC Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. Half TC Mask interrupt. When one this interrupt is enabled NB Half TC Mask interrupt. only fifo mode is enabled, When one this interrupt is enabled Write one to clear end of TC interrupt. Write one to clear end of FIFO interrupt. Write one to clear end of Half TC interrupt. Write one to clear end of Half TC (the real one) interrupt. Current AHB address value. dump the 'data from dfe to nb core' to mem when the bit is 1, dump only when nb-core comes an pulse ,capture the set data numbers ,then stop when the bit is 0, dump all bit normal dump mode when the bit is 1, downsample enable when the bit is 0, disable get data from mem, simu the data format from dfe to nb core get data from mem, simu the data format from nbcore to dfe feed data rate 1.92MHz=0x20 192KHz=0x140, 96KHz=0x280, 38.4KHz=0x640, 32KHz=0x780 fifo empty siganl fifo empty signal clr feed fifo point clr dump fifo point when the bit is 1, nb use the rf_dma when the bit is 0, 2g use the rf_dma the bandwidth select signal bypass the filter function to the data combine a unused data with I0 used as I0Q0, combine Q0I1 , used as I1Q1. next goes on. the last Qn will be discarded. set the delay of fclk_fordata to delay the rbdp_tx data set the delay of fclk external, only for the clk_phy gen fclk 1'b0 the source is fclk gen by clk_phy, 1'b1 the source is mclk dump_ovfl irq dump_udfl irq feed_ovfl irq feed_udfl irq dump_ovfl when ifc is still working irq dump_udfl when ifc is still working irq dump_ovfl mask dump_udfl mask feed_ovfl mask feed_udfl mask dump_ovfl when ifc is still working mask dump_udfl when ifc is still working mask dump_ovfl before mask irq source dump_udfl before mask irq source feed_ovfl before mask irq source feed_udfl before mask irq source dump_ovfl when ifc is still working irq source dump_udfl when ifc is still working irq source dump_ovfl clr irq dump_udfl clr irq feed_ovfl clr irq feed_udfl clr irq dump_ovfl when ifc is still working clr irq dump_udfl when ifc is still working clr irq Enable the rf spi
1 = Enable
0 = Disable (will finish current command anyway) Chip select polarity
1 = the chip select is active low
0 = the chip select is active high DigRF Read style mode
1 = DigRF Read style mode (read after CS disabled)
0 = SPI Read mode (read during write) DigRF style clocked back to back mode
1 = clocked back to back transfers using turnarround timing only when more data are present in the FIFO.
0 = stop the clock between each access according to CS_End_Hold and CS_Pulse_Min timings Input mode
1 = Record input data to input FIFO
0 = No input data SPI Clock polarity
1 = the clock disabled level is high, and the first edge is a falling edge.
0 = the clock disabled level is low, and the first edge is a rising edge. Transfer start to first edge delay
value from 0 to 2 is the number of spi clock half period between the Transfer start and the first clock edge. Transfer start to first data out delay
value from 0 to 2 is the number of spi clock half period between the Transfer start and the first data out. Transfer start to first data in sampled delay
value from 0 to 3 is the number of spi clock half period between the Transfer start and the first data sampled in.
The DI_Delay only specify the sampling time, for frame size, the counter is based on the DO_Delay even in DigRF read mode. Transfer start to CS activation delay
value from 0 to 3 is the number of spi clock half period between the Transfer start and the CS activation edge. Transfer end to chip select deactivation delay
value from 0 to 3 is the number of spi clock half period between the end of transfer (DO) and the CS deactivation edge.
Not used for Clocked_Back2Back mode Number of data in the frame, or number of out data in DigRF read mode.
The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits)
The frame size is given for the number of data, the actual number of clock pulses might be greater. First if Clock_Delay < DO_Delay an extra clock pulse is generated, second in case of DigRF read or back2back, some more clock pulses will be generated. Chip select deactivation to new start of transfer minimum delay
value from 0 to 3 is the number of spi clock half period between the CS deactivation and a new transfer start (transfer will start only if more data are available in the transmit FIFO)
Not used for Clocked_Back2Back mode Frame Size For Input in DigRF input mode
The actual frame size is the value of this register + 1; valid value are 3 to 31 (frame size 4 to 32bits) TurnAround time: end of write frame to start of read frame delay (in cycles)
value from 0 to 3 is the number of spi clock period between the end of the output frame (without the DO_Delay) and the Input Frame start.
Also used for Clocked_Back2Back mode, when Clocked_Back2Back=1 and there is more data available in the transmit FIFO:
value from 0 to 3 is the number of spi clock period between the end of the frame (without the DO_Delay) and the start of the new frame. (It can also be seen as the number of spi clock period between the end of the last data bit and the start of the new data bit.) The SPI activity status
1 = A transfer is in progress
0 = The transfer is done Error status
1 = a new command (or gain) has been requested while a command was in progress.
0 = No error
Write 1 to clear. The Gain Table overflow status.
1 = Too many data has been written in the table
Writing a 1 clear the overflow status. The Gain Table underflow status.
1 = a next gain request has been received while the read pointer was already at the top of the table.
Writing a '1' clear the underflow status. Command FIFO level, number of command in the FIFO The command FIFO overflow status.
1 = Too many data has been written in the FIFO
Writing a 1 clear the overflow status. The command FIFO underflow status.
1 = Data has been requested to read while the FIFO was empty
Writing a 1 clear the underflow status. Command FIFO level, number of bytes in the FIFO The command data FIFO overflow status.
1 = Too many data has been written in the FIFO
Writing a 1 clear the overflow status. The command data FIFO underflow status.
1 = Data has been requested to read while the FIFO was empty
Writing a 1 clear the underflow status. Receive FIFO level, number of bytes in the FIFO The receive FIFO overflow status.
1 = Too many data has been written in the FIFO
Writing a 1 clear the overflow status. The receive FIFO underflow status.
1 = Data has been requested to read while the FIFO was empty
Writing a 1 clear the underflow status. Read in the receive FIFO
Writing this register will write to Cmd_Data fifo (same as Cmd_Data register). This is because this address is used by the IFC channels to access the fifos. Writing 1 send the next command in the Cmd FIFO (This replace the TCU next cmd signal) Writing 1 flush both Cmd, and cmd_data FIFO, don't do it when SPI is active (transfer in progress) Writing 1 flush the receive data FIFO, don't do it when SPI is active (transfer in progress) Writing 1 place the read pointer at the beginning of the gain table. don't do it when SPI is active (transfer in progress) Writing 1 place the write pointer at the beginning of the gain table allowing to fill the table. Writing 1 change all the ouputs of the SPI interface to drive a logical '0'. This mode stops when a new command is requested to be send (by TCU) or when writting 0 to this register. This mode is useful when powering off the tranciever chip connected to the RF_SPI. Write the size in bytes of the next command in the FIFO Write 1 to mark the command.
Marked commands are discarded if Enable_Rf_Spi_Marked_Cmd is low in the tcu register. Write in the Command data FIFO Size of a Gain command in bytes. Write in the Gain Table (the pointer auto increments) Cmd_Data_DMA_Done IRQ Cause bit
1 = the IRQ was triggered by the end of the DMA transfer to the cmd FIFO.
To clear it write 1 in this bit or Cmd_Data_DMA_Done_Status bit. Cmd_FIFO_empty IRQ Cause bit
1 = the IRQ was triggered because the Cmd_FIFO is empty.
To clear it, fill the FIFO. Cmd_Threshold IRQ Cause bit
1 = the IRQ was triggered because the Cmd_FIFO level is below the Cmd_Threshold.
To clear it, fill the FIFO. Rx_FIFO_full IRQ Cause bit
1 = the IRQ was triggered because the Rx_Data_FIFO is full.
To clear it, read from the FIFO. Rx_Threshold IRQ Cause bit
1 = the IRQ was triggered because the Rx_Data_FIFO level is over the Rx_Threshold.
To clear it, read from the FIFO. Error IRQ Cause bit
1 = the IRQ was triggered because an error occured. Read the Status register to check the kind of error.
To clear it, clear it in the Status register. Cmd_Data_DMA_Done IRQ Status bit
1 = the end of the DMA transfer to the cmd FIFO occured.
To clear it write 1 in this bit or Cmd_Data_DMA_Done_Cause bit. Cmd_FIFO_empty IRQ Status bit
1 = the Cmd_FIFO is empty. Cmd_Threshold IRQ Status bit
1 = the Cmd_FIFO level is bellow the Cmd_Threshold. Rx_FIFO_full IRQ Status bit
1 = the Rx_Data_FIFO is full. Rx_Threshold IRQ Status bit
1 = the Rx_Data_FIFO level is over the Rx_Threshold. Error IRQ Status bit
1 = an error occured. Read the Status register to check the kind of error. Cmd_Data_DMA_Done IRQ Mask bit
1 = the Cmd_Data_DMA_Done IRQ is enabled
0 = the Cmd_Data_DMA_Done IRQ is disabled Cmd_FIFO_empty IRQ Mask bit
1 = the Cmd_FIFO_empty IRQ is enabled
0 = the Cmd_FIFO_empty IRQ is disabled Cmd_Threshold IRQ Mask bit
1 = the Cmd_Threshold IRQ is enabled
0 = the Cmd_Threshold IRQ is disabled Rx_FIFO_full IRQ Mask bit
1 = the Rx_FIFO_full IRQ is enabled
0 = the Rx_FIFO_full IRQ is disabled Rx_Threshold IRQ Mask bit
1 = the Rx_Threshold IRQ is enabled
0 = the Rx_Threshold IRQ is disabled Error IRQ Mask bit
1 = the Error IRQ is enabled
0 = the Error IRQ is disabled Command FIFO Threshold, number of command in the FIFO bellow which the Cmd_Threshold_IRQ is triggered. Receive FIFO Threshold, number of bytes in the FIFO above which the Rx_Threshold_IRQ is triggered. Clock Divider
The state machine clock is generated by dividing the system clock by the value of this register + 1. So the output clock is divided by (register + 1)*2 When enabled the clock input to the divider is not the system clock, but a limited version of it: It cannot be above 52MHz, so the output clock will never be above 26MHz.
for system clock of 104Mhz the clock input to the divider is 52Mhz, for system clock of 78Mhz the clock input to the divider is 39Mhz, for lower system clock value, the input to the divider is the system clock. This field indicates which standard channel to use.
Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy.
After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable in the control register of the channel to release the channel.
0000 = use Channel0
0001 = use Channel1
0010 = use Channel2
...
0111 = use Channel7
1111 = all channels are busy This register indicates which channel is enabled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:
0000_0000 = All channels disabled
0000_0001 = Ch0 enabled
0000_0010 = Ch1 enabled
0000_0100 = Ch2 enabled
0000_0101 = Ch0 and Ch2 enabled
0000_0111 = Ch0, Ch1 and Ch2 enabled
1111_1111 = all channels enabled This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is enabled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel Debug Channel Status .
0= The debug channel is running (not idle)
1= The debug channel is in idle mode Channel Enable, write one in this bit enable the channel.
When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Channel Disable, write one in this bit disable the channel.
When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Exchange the read data from fifo halfword MSB or LSB
Exchange the write data to fifo halfword MSB or LSB
Set Auto-disable mode
0 = when TC reach zero the channel is not automatically released.
1 = At the end of the transfer when TC reach zero the channel is automatically disabled. the current channel is released. Peripheral Size
0= 8-bit peripheral
1= 32-bit peripheral Select DMA Request source When one, flush the internal FIFO channel.
This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel.
Before writting back this bit to zero the internal fifo must empty. Set the MAX burst length for channel 0,1. This bit field is only used in channel 0~1, for channel 2~6, it is reserved.
The 2'b10 mean burst max 16 2'b01 mean burst max 8, 00 mean burst max 4.
. Enable bit, when '1' the channel is running The internal channel fifo is empty AHB Address. This field represent the start address of the transfer.
For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size in bytes to perform.
During a transfer a write in this register add the new value to the current TC.
A read of this register return the current current transfer count. Channel Enable, write one in this bit enable the channel.
This channel works only in fifo mode. Channel Disable, write one in this bit to disable the channel. Enable bit, when '1' the channel is running The internal channel fifo is empty Internal fifo level AHB Start Address.
This field represent the start address of the fifo. The start address must 32-bit aligned. AHB End Address.
This field represent the last address of the fifo (it is the first address not used in the fifo).
The end address must 32-bit aligned. Transfer Count, transfer size in bytes.
This bit indicated the transfer size in bytes to perform. Up to 16kbytes per transfer.
During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. 0: sel 26MHz clock.
1: sel 32KHz clock. 0: sel 61.44MHz clock.
1: sel 32KHz clock. Number of snapshot. Number of snapshot. Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg. 0: low active, assert reset.
1: high inactive, deassert reset. 0: not disable ip_* clock.
1: disable ip_* clock. 0: enable hclk_* auto clock gating.
1: disable hclk_* auto clock gating. 0: enable pclk_* auto clock gating.
1: disable pclk_* auto clock gating. 0: enable pclk_* and clk_* auto clock gating.
1: disable pclk_* and clk_* auto clock gating. cfg ram. select debug signal.
0: nbiot_dbgout
1: irq_dbg0 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53, gsm_fint_h_bb, gsm_tcu_bcpu_irq_h};
2: irq_dbg1 = {5'h0, irq_aif_apb_h, nb_acc_int_dsp, nb_tx_int_dsp, nb_rx_int_dsp, nb_tcu_sync_irq_h, irq_mailbox_gge_h, nb_rf_spi_irq, gsm_rf_spi_irq};
3: irq_dbg2 = {int_cholk, int_xcor, int_vitac, int_itlv, int_excor, int_evitac, rf_if_tx_irq, rf_if_rx_irq, rf_if_dbg_nb_irq,rf_if_dbg_2g_irq, 2'b0, int_a53, nb_fint_h_bb, nb_tcu_bcpu_irq_h};
4: tcu_dbg0 = {gsm_tcu_lps_fint, gsm_lps_tcu_fint_masked, gsm_lps_tcu_stop_counters, gsm_lp_pu_ready, gsm_lp_pu_done, tcu_nb_fint, gsm_fint_h_sys, gsm_fint_h_bb, gsm_toggle_fint_x, gsm_toggle_fint_b,
gsm_snap_config, gsm_send_spi_cmd_h, nb_o_tcu_trig, gsm_enable_rf_spi_marked_cmd_h};
5: tcu_dbg1 = {5'h0, gsm_send_spi_cmd_h, gsm_next_gain_h, gsm_first_gain_h, rx_soc_h, digrf_strobe_h, gsm_tcu_bcpu_irq_h, gsm_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h};
6: tcu_dbg2 = {4'h0, gsm_tco};
7: tcu_dbg3 = {nb_tcu_lps_fint, nb_lps_tcu_fint_masked, nb_lps_tcu_stop_counters, nb_lp_pu_ready, nb_lp_pu_done, tcu_nb_fint, nb_fint_h_sys, nb_fint_h_bb, nb_toggle_fint_x, nb_toggle_fint_b,
nb_snap_config, nb_send_spi_cmd_h, nb_o_tcu_trig, nb_enable_rf_spi_marked_cmd_h};
8: tcu_dbg4 = {5'h0, nb_send_spi_cmd_h, nb_next_gain_h, nb_first_gain_h, rx_soc_h, digrf_strobe_h, nb_tcu_bcpu_irq_h, nb_tcu_xcpu_irq_h, 1'b0, nb_tcu_sync_irq_h};
9: tcu_dbg5 = {4'h0, nb_tco};
deault: 16'hDABC; select rfif dump signal.
0: dfe_dump_data
1: dfe_rx_data
2: dfe_tx_data
deault: dfe_dump_data when bcpu is sleep, can disable bcpu cache mem. when bcpu not use cache, can disable bcpu cache mem. Internal TCO mapping Clear TCO 0 : set the TCO 0 to the inactive state
To clear TCO n, use event 2*n Set TCO 0 : set the TCO 0 to the active state
To set TCO n, use event 2*n+1 ... stop modulation starts modulation and output on IQ DAC disable IQ ADC enable IQ ADC stop recording IQ samples start recording IQ samples Clear RF_PDN Set RF_PDN Send RF spi command Start Ramp 0 Start Ramp 1 Start Ramp 2 Start Ramp 3 Start Ramp 4 Trigger BCPU TCU irq 0 Trigger BCPU TCU irq 1 Trigger XCPU TCU irq 0 Trigger XCPU TCU irq 1 End of the WakeUp Mode Start of Rf_spi Transfer End of Rf_spi Transfer Value loaded into the TCU counter when the Load bit is set to 1 Writing a 1 to this bit will load the TCU with the TCU loadval value
Writing a 0 has no effect Normal Behavior, The programmation area is copied to the active area when the tcu wraps The programmation area is copied into the active area only when force latch is used Writing a 1 to enable run tcu wakeup function in lowpower skip frame
Writing a 0 to disable TCU counter wrap value.
The TCU counter returns to 0 when this value is reached TCU counter current value Writing 1 transfer the programmed events to the active area. Writing 1 to this bit with one of the ForceLatch bit will force the corresponding Active Area to receive no events (i.e. clear it) instead of transfering the programmed area. Writing 1 clears the Program Area Configure the TCO polarity Error Status: become 1 when writing to Program Area while the TCU is coping the Program Area to the Active Area. In this case the write is ignored.
Write 1 to clear it. This bit allows to access directly the active area for debug purposes the active area is directly mapped instead of the program area. Writing 1 disable the events that affect corresponding TCO.
Reading return the actual enable state. Writing 1 disable the events that affect corresponding TCO.
Reading return the actual enable state. Writing 1 disable the events SEND_SPI_CMD.
Reading return the actual enable state. Writing 1 disable the events NEXT_GAIN.
Reading return the actual enable state. Writing 1 disable the events FIRST_GAIN.
Reading return the actual enable state. Writing 1 disable the events NEXT_FC.
Reading return the actual enable state. Writing 1 disable the corresponding Ramp event.
Reading return the actual enable state. Writing 1 disable the events RX_SOC.
Reading return the actual enable state. Writing 1 disable the events DIGRF_STB.
Reading return the actual enable state. Writing 1 disable the corresponding BCPU TCU irq event.
Reading return the actual enable state. Writing 1 disable the corresponding XCPU TCU irq event.
Reading return the actual enable state. Writing 1 disable the events RFSPI_START.
Reading return the actual enable state. Writing 1 disable the events RFSPI_END.
Reading return the actual enable state. Writing 1 disable the marked rf spi commands (cf RF SPI).
Reading return the actual enable state. Writing 1 enable the events that affect corresponding TCO.
Reading return the actual enable state. Writing 1 enable the events that affect corresponding TCO.
Reading return the actual enable state. Writing 1 enable the events SEND_SPI_CMD.
Reading return the actual enable state. Writing 1 enable the events NEXT_GAIN.
Reading return the actual enable state. Writing 1 enable the events FIRST_GAIN.
Reading return the actual enable state. Writing 1 enable the events NEXT_FC.
Reading return the actual enable state. Writing 1 enable the corresponding Ramp event.
Reading return the actual enable state. Writing 1 enable the events RX_SOC.
Reading return the actual enable state. Writing 1 enable the events DIGRF_STB.
Reading return the actual enable state. Writing 1 enable the corresponding BCPU TCU irq event.
Reading return the actual enable state. Writing 1 enable the corresponding XCPU TCU irq event.
Reading return the actual enable state. Writing 1 enable the events RFSPI_START.
Reading return the actual enable state. Writing 1 enable the events RFSPI_END.
Reading return the actual enable state. Writing 1 enable the marked rf spi commands (cf RF SPI).
Reading return the actual enable state. Writing 1 set corresponding TCO to the active state (The actual line state also depends on TCO_Polarity).
Reading returns the actual state of all TCOs. Writing 1 set corresponding TCO to the inactive state (The actual line state also depends on TCO_Polarity).
Reading returns the actual state of all TCOs. Enable Clk_TCU same with Clk_Sys. Enable the 208kHz pulse generation for DAI Simple. (!) When enabling the clock field Enable_Qbit should also be enabled. Enable the Quarter bit generation (required for normal TCU operation) 1 when the IRQ was triggered because the tcu counter synchronization is done.
Write 1 in cause or status bit to clear. 1 when the tcu counter synchronization is done.
Write 1 in cause or status bit to clear. when 1 the LPS_IRQ_TCU_Sync_Done is enabled. enable sync tcu counter to global counter function. tcu counter load value when synchronized. TCU counter value when rfspi conflict happen The event Id will be executed when the TCU counter reaches the value programmed in Event time field of this register. Event to be executed when the TCU counter reaches the programmed event time.
Writing a '1' in this register triggers a Viterbi Equalization process. Ignored if any Viterbi process is already ongoing. Auto-reset. Writing a '1' in this register triggers a Viterbi Decoding process. Ignored if any Viterbi process is already ongoing. Auto-reset. Writing a '1' in this register triggers the TraceBack process. Ignored if any Viterbi process is already ongoing. Auto-reset. When this bit is set, it enables the generation of the VITAC_DONE_H interrupt. Indicates whether a puncturing scheme has to be used during decoding. If this bit is set to '0', the code is assumed unpunctured and no puncturing matrix is needed. This field sets the number of states of the Trellis:
"00": 16 states
"01": 32 states
"10": 64 states
"11": reserved When this bit is set, the channel symbols are treated in the reverse order, i.e. CH_SYMB_ADDR represents the end of the buffer and the symbols are read out backward. This field sets the convolutional code rate for decoding:
"010": 1/2 rate
"011": 1/3 rate
"100": 1/4 rate
"101": 1/5 rate
"110": 1/6 rate
others: reserved This field sets the amount of shift right applied at the output of the equalizer BM calculation:
"0000": BM = OUT[30:19]
"0001": BM = OUT[29:18]
...
"1111": BM = OUT[15:4] This field sets the amount of shift right applied to the difference of the two metrics arriving at a node to create a Softvalue:
"0000": SoftVal = DELTA[15:9]
"0001": SoftVal = DELTA[14:8]
...
"1101": SoftVal = DELTA[2:0]&"0000"
others: reserved Number of symbols to be Equalized / Decoded. Auto decrement. This bit is high when an equalization process is ongoing. It stays high when the module is stalled during operation. This bit is high when an decoding process is ongoing. It stays high when the module is stalled during operation. This bit is high when an traceback process is ongoing. It stays high when the module is stalled during operation. After a Viterbi process, this field reports the number of rescaling operations that have been performed along the trellis.
This field is reset at every new Viterbi process. This is the start address of the channel symbols buffer in SRAM. For Equalization channel symbols are the sampled RF samples (2x12-bits packed complex values), and for Decoding channel symbols are a frame of softvalues (4x8-bits packed).
This address must be 4-bytes aligned, bits[1:0] will be ignored. For Equalization, this is the base address of the partial sum terms buffer in SRAM. (2x12-bits packed complex values)
For Decoding, this is the base address of the puncturing matrix.
This address must be 4-bytes aligned, bits[1:0] will be ignored. This is the base address in SRAM of the Path Metrics buffer. The VITAC will read and update PMs according to the scheme given in 1.2.1.2. (2x16-bits packed values).
This address must be 4-bytes aligned, bits[1:0] will be ignored. This is the start address of the output buffer in SRAM. When in Equalizer mode, the VITAC will output the calculated Softvalues according to the scheme given in 1.2.1.7. When in Decoder mode, the VITAC will output the trace words according to the scheme given in 1.2.2.4.
This address must be 4-bytes aligned, bits[1:0] will be ignored. Real part of the h0 parameter of the estimated channel response. Imaginary part of the h0 parameter of the estimated channel response. Real part of the hL parameter of the estimated channel response. Imaginary part of the hL parameter of the estimated channel response. This field indicates the threshold value to be reach by every PMs for triggering a rescale operation. The rescale operation consist in subtracting the threshold value to every PMs to avoid overflow during PM update. This register bank stores the less significant bit of the output from the coder for a particular code (see 1.2.2.1). The kth butterfly uses the bit k of this register. This register stores the less significant bit of the output from the coder for a particular code (see 1.2.2.1). The kth butterfly uses the bit k of this register. This bit is set when the VITAC module finishes an ongoing operation. It can be masked by setting VITAC_CMD(IT_MASK) to '1'.
Resetting this bit is done by writing in IT_CLEAR register.
IT_CAUSE is the image of the VITAC_DONE_H interrupt line to the CPU. This bit is the unmasked version of the IT_CAUSE bit. Setting this bit to '1' resets the VITAC interrupt. Count Value for 1st TimeOut Count Value for 2nd TimeOut Watchdog response mode.
0 = Generate a system reset.
1 = First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset. Reset pulse length in number of wdt clock cycles. The range of values available is 1 to 8 clk cycles.
3'b000 - 1 clk cycle
3'b001 - 2 clk cycles
3'b010 - 3 clk cycles
...
3'b111 - 8 clk cycles This register is used to restart/stop the WDT counter. As a safety feature to prevent accidental restarts/stops, write 8'h76 to restart and 8'h34 to stop.
When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. A pulse to clear interrupt.
When written is done, this register is self-cleared on the next clock cycle. Reading this register always returns zero. This register shows the word status of the WDT.
0 = The watchdog counter is idle/stopped.
1 = The watchdog counter runs. This register shows the interrupt status of the WDT.
0 = Interrupt is inactive.
1 = Interrupt asserts. Enables the Biterror calculation mode. Auto-reset. Enables the DC Offset Correction (1st pass) mode. Auto-reset. Enables the DC Offset Correction (2nd pass) mode. Auto-reset. Enables the DC Offset Correction (3rd pass) mode. Auto-reset. Enables the Training Sequence Cross-Correlation mode. Auto-reset. Enables the Symbol Re-Construction mode. Auto-reset. Enables the Bit Extraction mode. Auto-reset. Enables the Sum Of PROduCt mode. Auto-reset. Enables the Channel Estimation mode. Auto-reset. Enables the FCH Xcorrelation mode. Auto-reset. Enables the Sliding window mode. Auto-reset. Mask of the end of processing interrupt. Data path setting. Pack I and Q on a single 32-bits word. Data path setting. Enables derotation for DCOC 3pass. Control setting. Number of internal loop iteration. Control setting. Number of symbols to process. This bit is high when an operation is ongoing. Masked version of it_status that goes to Interrupt controller. This bit is set high when an operation is finished. It must be reset before lauching a new operation if Xcor interrupt is enabled. Multipurpose Data Register.
Store Training Sequence in TSXC mode.
Store SUM in DCOC 3rd pass mode.
Store bit sequence in SREC mode.
Store SUM in SPROC mode.
Store I SUM in CHEST mode.
Store R(k-1) in FCHXC mode. Multipurpose. Multipurpose Data Register.
Store Training Sequence in TSXC mode.
Store bit sequence in SREC mode.
Store Q SUM in CHEST mode. Multipurpose. Multipurpose Data Registers.
D0 stores symbols/softvalues/channel taps depending on mode. Not readable.
D1 stores decoded bits/IQ threshols/IQ Offsets/A terms depending on mode. Not readable.
D2 (aka A1) serves as Rd address (decoded bits, A or B terms) / Wr address register (I or packed IQ results, Symbols) / event counter depending on mode.
D3 (aka A2) serves as Wr address (Q results) / event counter depending on mode.
D4 stores results from VITAC / extracted HardValues depending on mode. Not readable.
D5 (aka A3) serves as Wr address (CQ results) Not readable. Multipurpose. I part accumulator register. I part accumulator register. Address 0 Register.
Stores Rd address for symbols / SoftValues / A terms depending on mode.
Auto increment/decrement/reset. 32-bit word address (bits 0 and 1 disregarded). Multipurpose Data Edge Registers. Multipurpose. program counter for the RF stage. Interrupt TLB modification exception TLB exception (load or instruction fetch) TLB exception (store) Address error exception (load or instruction fetch) Address error exception (store) Bus error exception (instruction fetch) Bus error exception (data reference: load or store) Syscall exception Breakpoint exception Reserved instruction exception Coprocessor Unusable exception Arithmetic Overflow exception Theses interrupt lines are software interrupts (the cpu can write in the CP0 bits to trigger and clear them). Theses interrupt lines maps to the hardware interrupt lines from the corresponding irq module. The Coprocessor Error (CE) field indicate the coprocessor unit number referenced when a Coprocessor Unusable exception is taken. The Branch Delay (BD) bit indicate whether the last exception was taken while executing in a branch delay slot. Current Interrupt Enable Current Kernel/User mode Previous Interrupt Enable Previous Kernel/User mode Old Interrupt Enable Old Kernel/User mode Interrupt Mask control the enabling of each of the external and software interrupts. (See Cause for more information on interruptions). This bit control handling of non-cached instruction fetch requests. By default, the system block reads multiple words of data from the AMBA bus in burst transactions and saves them in the Streaming Buffer. Non cached instruction fetch requests get their data directly from the Streaming Buffer. When "1" the cpu does not use the streaming buffer and does not ask for burst requests on the AMBA bus for non-cache instruction fetch requests. Cache Miss
Signals that the most recent access to the cachable space resulted in cache miss. Signals that 2 entries in the TLB matched the virtual address. This is an error condition but the processor takes no action other than signalling it via this bit in the Status Register. Select the location of the exception vectors in ROM or in DRAM. Reverse Endian in User mode. (probably unused in xcpu) Control the Usability of the corresponding Coprocessor Unit. (CP0 is always usable when in Kernel mode, regardless of the setting of the CU_0 bit. Control the Usability of the corresponding Coprocessor Unit. Exception Program Counter. Saves the value of the program counter for the instruction that caused the exception. Bad virtual address. Saves the address that caused the address exception. Exception Program Counter. Saves the value of the program counter for the instruction that caused the exception by break point instruction. assembler temporary register; their values are not preserved across procedure calls. Used for expression evaluations and for hold integer function results.
Also used to pass the statuc link when calling nested procedure. Used for expression evaluations and for hold integer function results.
Also used to pass the statuc link when calling nested procedure. register A0 to A3 is used to pass the first 4 words of integer type actual arguments; their values are not preserved across procedure calls. register A0 to A3 is used to pass the first 4 words of integer type actual arguments; their values are not preserved across procedure calls. register A0 to A3 is used to pass the first 4 words of integer type actual arguments; their values are not preserved across procedure calls. register A0 to A3 is used to pass the first 4 words of integer type actual arguments; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. saved register; their values must preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. temporary register, used for expression evaluations; their values are not preserved across procedure calls. reserved for the operating system kernal. reserved for the operating system kernal. contains the global pointer. contains the stack pointer. a saved register (like s0-s7). contains the return address; used for expression evaluation. Debug Page Address Register Is a 4 bit register used for extending the address of the debug to enable full access to the cache RAMs.
bit 3 is used when accessing the TAGs to select between Instruction TAG (0) or Data TAG (1). when "ON" all accesses for data are treated as non cache. Data is fetched directly from main memory. The content of the Data Cache is not altered. when "ON" all accesses for instructions are treated as non cache. Data is fetched directly from main memory. The content of the cache is not altered. when "ON" all accesses to either Instruction or data caches result in a cache miss and a cache refill. This is a quick way to initialize the caches. logic analyzer control register run control.
0 ela-500 disabled. register programming permitted.
1 ela-500 enabled. timestamp control register timestamp enable. timestamp interval.
when timestamps are enabled, tsint specifies the bit number of the 16-bit trace counter that causes a timestamp packet to be requested. the trace counter runs from elaclk. when the specified bit changes, a timestamp packet is requested to be inserted into the trace sram when there is an elaclk cycle during which trace data is not being captured. the ela-500 does not insert back-to-back timestamps in the sram, even when tsint causes multiple requests to be made.
when tsint = 0, a timestamp is written when action.trace disables trace. looping trigger states enable and then disable trace, causing timestamp writes. a timestamp is always written when ctrl.run is cleared and the previous trace write contained a data payload. trace counter 1 select.
selects the bit number of the 16-bit trace counter that is presented as trace counter[1] in the sram header byte. trace counter 0 select.
selects the bit number of the 16-bit trace counter that is presented as trace counter[0] in the sram header byte. trigger state select register each bit identifies the trigger state that enables independent trace. only trigger state 4 supports independent trace.
altts[4]=0 trigger state 4 independent trace disabled.
altts[4]=1 trigger state 4 independent trace enabled.
all other bits read zero. pre-trigger action register sets the value to drive on elaoutput[3:0]. enables trace. sets the level to drive on stopclock. sets the value to drive on cttrigout[1:0]. current trigger state register 0 ela-500 is still tracing.
1 indicates that the ela-500 has stopped advancing trigger states and stopped trace.
finalstate can be set by trigctrl.countbrk reaching the final loop count, or by programming nextstate or altnextstate to zero. reads current trigger state. this is a one-hot encoded field.
when ctrl.run:
0 raz
1 returns current trigger state.
if finalstate is 1, then the ctsr field gives the trigger state when finalstate became 1. current counter value register returns the counter value when the ctsr was last read. if the ctsr has never been read, then the value in the ccvr is undefined. current action value register value driven on elaoutput[3:0]. trace active.
0b0 trace is not active.
0b1 trace is active. level driven on stopclock.
0b0 0 driven on stopclock.
0b1 1 driven on stopclock. value driven on cttrigout[1:0]. read captured transaction id register returns the captured transaction id. ram read address register ram read address.
writes to the rra cause the trace sram data at that address to be transferred into the holding register.
after the sram read data is transferred to the holding register, rra increments by one. this prepares the rra address for sequential rrdr reads.
the rra automatically increments after apb reads from the rrdr have read the contents of the holding register. an rrdr read of the last data in the holding register initiates a read to sram at the address pointed to by the rra. the holding register is filled with the data at this address, then the rra increments. ram read data register reads sram data from the holding register.
reads from the rrd return the sram data from the holding register. the first read of the rrd after an rrar update returns the trace data header byte value, zero-extended to 32 bits. subsequent reads of the rrd return 32-bit chunks of the trace data payload, starting with the least significant word, until all the payload data has been read, that is, two words if grp_width = 64, four words if grp_width = 128, and eight words if grp_width = 256.
when the final 32 bits of the payload have been read, the rra is incremented automatically, and the next word of sram data is copied into the holding register. this enables the sram data content to be read out efficiently.
the rra wraps to address zero if it is incremented beyond the maximum depth of the sram. ram write address register the wrap bit is set when the ram write address is incremented beyond 2ram_addr_size while
the ela-500 is capturing trace data. the wrap bit is not set by writes to the rwdr that cause the
ram write address to roll over. software must clear the wrap bit when writing to the rwar. ram write address.
writes to the rwa set the sram address for data that is then written through the rwdr.
reads from the rwa return the address of the sram location that is to be written next, either by writes to the rwdr, or by the trace unit.
when trace is stopped, the rwa contains the address of the last sram location that was written plus one. if the ram write address was incremented beyond the depth of the ram while the ela-500 was capturing trace data, the wrap bit is set.
the rwar is automatically incremented by apb writes to the sram through the rwdr. ram write data register writes data to the write holding register and initiates an sram write when the write holding register is full. writes to the rwd update the internal write holding register.
the first write to the rwd sets the header byte value from the least significant byte written. subsequent writes to the rwd set 32-bit chunks of the payload, starting with the least significant chunk. when the final 32 bits of the payload have been written, the content of the holding register is copied into the sram and the rwa is incremented automatically. signal select registers selects signal group.
0x1 selects signal group 0.
0x2 selects signal group 1.
0x4 selects signal group 2.
0x8 selects signal group 3.
0x10 selects signal group 4.
0x20 selects signal group 5.
0x40 selects signal group 6.
0x80 selects signal group 7.
0x100 selects signal group 8.
0x200 selects signal group 9.
0x400 selects signal group 10.
0x800 selects signal group 11. trigger control registers selects the alternative comparison mode:
0b0 trigger signal alternative comparisons selected.
0b1 trigger counter alternative comparisons selected. trigger signal alternative comparison type select:
0b000 trigger signal alternative comparisons disabled.
0b001 alternative compare type is equal (==).
0b010 alternative compare type is greater than (>).
0b011 alternative compare type is greater than or equal (>=).
0b101 alternative compare type is not equal (!=).
0b110 alternative compare type is less than (<).
0b111 alternative compare type is less than or equal (<=).
0b00 disable use of the captured id for signal comparisons.
0b01 capture id when trigger signal condition matches. the id is captured, from signalgrp[id_capture_size-1:0].
0b10 use the captured id instead of the target value in sigcomp[id_capture_size-1:0] for comparison of signalgrp[id_capture_size-1:0].
0b11 use the captured id instead of the signalgrp[id_capture_size-1:0] for a comparison against sigcomp[id_capture_size-1:0]. loop counter break.
the loop counter break uses the trigger state counter to break loops between trigger states after a trigger counter comparison. when the counter comparison matches, the trigger state goes to a final state, which stops trace writes and leaves the output actions at the previous trigger state action value.
0b0 normal operation.
0b1 break trigger state loop: a counter comparison match causes a transition to the final state, otherwise go to the nextstate trigger state as the counter increments. counter clear.
0b0 do not clear the counter value when moving to a different nextstate.
0b1 clear the counter value when moving to a different nextstate.
note: trigctrl.watchrst must be 0b0 when using this feature. trace capture control.
0b00 trace is captured when trigger signal comparison succeeds.
0b01 trace is captured when trigger counter comparison succeeds.
0b10 trace is captured every elaclk cycle.
0b11 reserved. counter source select.
0b0 counter is incremented every elaclk cycle.
0b1 counter is incremented when trigger signal comparison matches. counter reset.
0b0 do not reset the counter after a trigger signal comparison match.
0b1 reset the counter after a trigger signal comparison match.
the counter acts like an activity watchdog timer, only allowing advancement to the next trigger state when the trigger counter comparison is reached. the counter is reset by a signal comparison. comparison mode. acts as both a counter enable and a select for the comparison mode.
0b0 disable counters and select trigger signal comparison mode.
0b1 enable counters and select trigger counter comparison mode. trigger signal comparison type select.
0b000 trigger signal comparisons disabled. the enabled counters count clocks immediately after the trigger state has been entered and generate a programmable output action and transition to the next trigger state when the counter compare register count is reached, that is when a trigger counter comparison match occurs.
0b001 compare type is equal (==).
0b010 compare type is greater than (>).
0b011 compare type is greater than or equal (>=).
0b101 compare type is not equal (!=).
0b110 compare type is less than (<).
0b111 compare type is less than or equal (<=). next state registers selects the next state to move to after the trigger condition has been met in the current state.
0x0 do not change state. this is the final trigger state.
0x1 selects trigger state 0.
0x2 selects trigger state 1.
0x4 selects trigger state 2.
0x8 selects trigger state 3.
0x10 selects trigger state 4, when num_trig_states=5. action registers value to drive on elaoutput[3:0]. trace active.
0b0 trace is not active.
0b1 trace is active. level to drive on stopclock.
0b0 drive 0 on stopclock.
0b1 drive 1 on stopclock. value to drive on cttrigout[1:0]. alt next state registers selects the next state to move to after the conditional trigger condition has been met in the current state.
0x0 do not change state. this is the final trigger state.
0x1 selects trigger state 0.
0x2 selects trigger state 1.
0x4 selects trigger state 2.
0x8 selects trigger state 3.
0x10 selects trigger state 4, when num_trig_states=5. alt action registers value to drive on elaoutput[3:0]. trace active.
0b0 trace is not active.
0b1 trace is active. level to drive on stopclock.
0b0 drive 0 on stopclock.
0b1 drive 1 on stopclock. value to drive on cttrigout[1:0]. counter compare registers value that, when reached in the associated up-counter for this trigger state, causes a trigger counter comparison match to occur. external mask registers mask exttrig[5:0] signals. each signal is masked by clearing the appropriate bit.
0b0 external trigger input signal is masked and is not used in comparisons.
0b1 external trigger input signal is not masked. mask cttrigin[1:0] signals. each signal is masked by clearing the appropriate bit.
0b0 external trigger input signal is masked and is not used in comparisons.
0b1 external trigger input signal is not masked. external compare registers compare value for exttrig[5:0] signals. compare value for cttrigin[1:0] signals. signal mask registers mask bits from sigcomp[31:0].
mask bits from sigcomp[63:32].
mask bits from sigcomp[95:64]. these bits are only used if grp_width = 128 or 256.
mask bits from sigcomp[127:96]. these bits are only used if grp_width = 128 or 256. signal compare registers compare value for signal group signals[31:0].
compare value for signal group signals[63:32].
compare value for signal group signals[95:64]. these bits are only used if grp_width = 128 or 256.
compare value for signal group signals[127:96]. these bits are only used if grp_width = 128 or 256. integration mode action trigger output register value to drive on elaoutput[3:0] when itctlr.ime = 1. level to drive on stopclock when itctlr.ime = 1.
0b0 drive 0 on stopclock.
0b1 drive 1 on stopclock. value to drive on cttrigout[1:0] when itctlr.ime = 1. integration mode external trigger input register captures the value on exttrig[5:0] when itctlr.ime = 1. captures the value on cttrigin[1:0] when itctlr.ime = 1. integration mode control register integration mode enable.
0b0 integration mode disabled. the ela-500 operates normally.
0b1 integration mode enabled when ctrl.run = 0. lock access register permits writes to the other ela-500 registers when the access code 0xc5acce55 is written. writing any other value prevents access to the other ela-500 registers. lock status register returns the status of the lock access control.
0b001 write access permitted.
0b011 write access not permitted. authentication status register secure, non-invasive debug.
0b10 debug disabled.
0b11 debug enabled. secure, invasive debug.
0b10 debug disabled.
0b11 debug enabled. non-secure, non-invasive debug.
0b10 debug disabled.
0b11 debug enabled. non-secure, invasive debug.
0b10 debug disabled.
0b11 debug enabled. device architecture register the architect of the device.
0x23b arm. indicates that the register is present.
1 register present. architecture revision.
0 first revision. the architecture of the device.
0x0a75 coresight ela. device configuration register 2 0: level detect of cttrigin and exttrig.
1: single edge detect of cttrigin and exttrig. indicates the comparator width. 0: comparator width = grp_width.
>0: comparator width = (comp_width + 1) x 8.
for example, if comp_width = 15, then comparator width = 256. 0x00 num_trig_states=4. trigger state 4 is not implemented.
0x10 num_trig_states=5. trigger state 4 is implemented and can be used for independent trace.
all other encodings are reserved and read as 0x00. device configuration register 1 counter width in bits. fixed at 32. number of trigger states. four or five. signal group width. the field value is (signal group width/8) - 1.
for example, 7 if grp_width = 64, 15 if grp_width = 128, and 31 if grp_width = 256. number of signal groups. fixed at 12. device configuration register 0: trace read data scrambler not present.
1: trace read data scrambler present. 2-30 bits when cond_trig = 1, or 0 otherwise. shows the value of the cond_trig parameter.
1, when cond_trig = 1, or 0 otherwise. sram address width in bits. trace implementation:
1 fixed at 1. indicates trace header format revision 1. atb trace:
0 atb trace not implemented.
1 atb trace is implemented. device type identifier register 0x75.
sub type = 0x7.
major type = 0x5. peripheral id4 register 0x0. one 4kb count. 0x4. jep continuation code for arm. peripheral id5 register 0x00. reserved. peripheral id6 register 0x00. reserved. peripheral id7 register 0x00. reserved. peripheral id0 register 0xb8. bits[7:0] of part number 0x9b8. peripheral id1 register 0xb. bits[3:0] of jep106 identification code for arm 0x3b. 0x9. bits[11:8] of part number 0x9b8. peripheral id2 register 0x2. revision number. indicates revision r2p0. 0b1. fixed at 0b1. 0b011. bits[6:4] of jep106 identification code for arm 0x3b. peripheral id3 register 0x0. revand. 0x0. indicates whether the customer has modified the behavior of the component. in most cases, this field is 0b0000. you can change this value when you make authorized modifications to this component. component id0 register 0x0d. preamble. component id1 register 0x9. indicates a coresight component. 0x0. preamble. component id2 register 0x05. preamble. component id3 register 0xb1. preamble. Control setting. psample increment. Control setting. Number of symbols. Control setting. node metric history. Control setting. Command. pbmml address. pzfm address. psample address. softbits output address. Status is set to 1 when an operation is finished,It must be reset before lauching a new operation sv shift bits. bm shift bits. zfhist history. Returns 1 and locks the DMA channel for a transaction if it is available. Else returns 0.
Clear the transfer done interrupt status. Status of the DMA: 1 if enabled, 0 if disabled. Cause of the interrupt. This bit is set when the transfer is done and the interrupt mask bit is set.
Write one in the Int Clear or write 0 in Enable control bits to clear Int Done Cause bit. Status of the interrupt. Status of the transfer: 1 if the transfer is finished, 0 if it is not finished.
Write one in the Int Clear or write 0 in Enable control bits to clear Int Done Status bit. Actual status of channel lock. Channel is unlocked at the end of transaction or when the DMA is disabled. Controls the DMA. Write 1 to enable the DMA, write 0 to disable it. When 0 is written in this register, the Int Done Status and Cause bits are reset. End of transfer interrupt generation. When 1, the DMA will send an interrupt at transaction completion. Clear the transfer done interruption (this will clear Int Done Status and Int Done Cause).
This bit is auto-clear. You will always read 0 here. If this bit is set, the source address will be ignored and the memory will be fill with the value of the pattern register. Set the MAX burst length.
The 2'b10 mean burst max 16, 2'b01 mean burst max 8, 00 mean burst max 4. The DMA stop the current transfer and flush his FIFO (write only bit). When the FIFO is empty and last write performed, the DMA is disabled and available for a next transfer. The number of bytes copied is readable on DMA_XFER_SIZE register. Enable Gea process when 1. This field sets the type of GEA algorithm to process. This field selects the Direction in the GEA algorithm. Enable FCS process when 1. Destination address management.
00 : Normal DMA operation, DMA_DST_ADDR register define the destination address.
01 : DMA write address is constant (no incremented) and defined by the DMA_DST_ADDR register. All data write are in 16-bit.
10 : DMA write address is alternatively defined by DMA_DST_ADDR and DMA_SD_DST_ADDR registers. All data write are in 16-bit.
In this configuration, DMA write operation is alternatively:
DMA_DST_ADDR <= DMA_PATTERN register
DMA_SD_DST_ADDR <= Data[DMA_SRC_ADDR]
11 : reserved Source start read byte address. When a transfer is stalled by the Stop_Transfer bit, this register give the next current source address, which is directly the value to re-program to complete the transfer stopped. Destination start read byte address. When a transfer is stalled by the Stop_Transfer bit, this register give the next current destination address, which is directly the value to re-program to complete the transfer stopped. Second destination address. This register is only used when Dst_Address_Mgt=10. Transfer size in bytes. Maximum: 262144 bytes. When a transfer is stopped by the Stop_Transfer bit, this register give the number of remainder bytes to transfer. Value taken to fill the memory when the configuration bit Use Pattern is set. When the pattern mode is used the destination address must be 32-bit aligned and the transfer size multiple of 4. when Dst_Address_Mgt=10 Pattern is the data written at the address given by the Dst_Address register. GEA key Kc, LSB bit [31:0]. GEA key Kc, MSB bit [31:0]. MessKey (Input) register. Frame Check Sequence. The FCS is correct in reception when the final remainder is equal to C(x)= x^22 + x^21 + x^19 + x^18 + x^16 + x^15 + x^11 + x^8 + x^5 + x^4 PSS Enable 1b0: Stop PSS calculation 1b1: Start PSS calculation PSS hypothesis number PSS output ping-pong buffer selection 1b1:Select the pong buffer as the first output buffer 1b0: Select the ping buffer as the first output buffer PSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. PSS start offset of subframe. Range is from 0 to 9. PSS internal sub frame counter(from 0 to 9) Indicate the buffer selection on current interrupt 1b0: buffer0 is selection 1b1: buffer1 is selection PSS output buffer 0 status. Clear by DSP or MCU 1b1: buffer 0 is ready. 1b0:buffer0 is idle PSS output buffer 0 status. 1b1: buffer 0 is over written. 1b0: buffer 0 is normal PSS output buffer 1 status. Clear by DSP or MCU 1b1: buffer 1 is ready. 1b0:buffer 1 is idle PSS output buffer 1 status. 1b1: buffer 1 is over written. 1b0: buffer 1 is normal PSS calculation done status. Update very 1ms and clear by DSP or MCU. 1b1: PSS calculation done 1b0: PSS is idle or under calculating PSS write memory arbitration error status. 1b1: the memory has conflict 1b0: the memory is normal bit8: pss final output data non-zero status bit7: pss 148x40 memory out data non-zero status bit6: pss 148x40 memory in data non-zero status bit5: pss power non-zero status bit4: pss 1312x24 memory out data non-zero status bit3: pss 1312x24 memory in data non-zero status bit2: pss in local sequence non-zero status bit1: pss_corr_calc in data non-zero status bit0: pss_deci in data non-zero status PSS sample position for Pu of hypothesis 0 PSS sample position for Pu of hypothesis 1 PSS sample position for Pu of hypothesis 2 PSS sample position for Pu of hypothesis 3 PSS sample position for Pu of hypothesis 0 PSS sample position for Pu of hypothesis 1 PSS sample position for Pu of hypothesis 2 PSS sample position for Pl of hypothesis 0 PSS sample position for Pl of hypothesis 1 PSS sample position for Pl of hypothesis 2 PSS sample position for Pl of hypothesis 3 PSS sample position for Pl of hypothesis 4 PSS sample position for Pl of hypothesis 5 PSS sample position for Pl of hypothesis 6 PSS set 0 coefficient for hypothesis 0 PSS set 0 coefficient for hypothesis 1 PSS set 0 coefficient for hypothesis 2 PSS set 0 coefficient for hypothesis 3 PSS set 0 coefficient for hypothesis 4 PSS set 0 coefficient for hypothesis 5 PSS set 0 coefficient for hypothesis 7 PSS set 1 coefficient for hypothesis 0 PSS set 1 coefficient for hypothesis 1 PSS set 0 coefficient for hypothesis 2 PSS set 0 coefficient for hypothesis 3 PSS set 1 coefficient for hypothesis 4 PSS set 1 coefficient for hypothesis 5 PSS set 0 coefficient for hypothesis 6 Real part of the local sequence 0 Imag part of the local sequence 0 Real part of the local sequence 1 Imag part of the local sequence 1 Real part of the local sequence 2 Imag part of the local sequence 2 Real part of the local sequence 3 Imag part of the local sequence 3 Real part of the local sequence 4 Imag part of the local sequence 4 Real part of the local sequence 5 Imag part of the local sequence 5 Real part of the local sequence 6 Imag part of the local sequence 6 Start trigger of one CFO calculation process by writing 1 to this register CFO data capture start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. CFO data capture start offset of sub-frame. Range is from 0 to 13. CFO calculation start offset of samples within a sub-frame. Based on 1.92MHz. Range is from 0 to 1920. CFO calculation start offset of sub-frame. Range is from 0 to 13. Rotated frequency bin number when rCFO_MODE=0. 1: Normal mode. CFO module only deal with 1 frequency bin(f0) and 9 sampling positions(Tau). 147 correlation results are reported to corresponding ram at most. 0: Searching mode. CFO module deal with 1~7 frequency bins(f0~6) and 21 sampling positions(Tau). 9 correlation results are reported to corresponding registers. Start write address of CFO correlation results reporting ram Correlation results truncation (32bits to 16bits). 0:>>8 1:>>7 2:>>6 3:>>5 4:>>4 5:>>3 6:>>2 7:>>1 Tau number of CFO correlation when rCFO_MODE=0. Sampling position start offset for bin f0 Sampling position start offset for bin f1 Sampling position start offset for bin f2 Sampling position start offset for bin f3 Sampling position start offset for bin f4 Sampling position start offset for bin f5 Sampling position start offset for bin f6 The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part The complex value of e^(-j2xpixf0xTsa). Tsa means decimation with 8. [31:16]:Imag part [15:0]: Real part CFO calculation done status. Clear by DSP or MCU. 1b1: CFO calculation done 1b0: CFO is idle or under calculating Memory request error for writing of CFO reporting ram when rCFO_MOED=0 0: Normal 1: Error Bit 2: DSP control bus error Bit 1: accelerator memory access collusion When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -4 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -3 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -2 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = -1 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = 0 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +1 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +2 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +3 is reported [31:16]: imag part [15:0]: real part When rCFO_MODE=1, correlation value of PSS sequence for frequency bin rCFO_A/B_F0 and sampling position Tau = +4 is reported [31:16]: imag part [15:0]: real part SSS Enable 1b0:Stop SSS calculation 1b1: Start SSS calculation SSS start offset of sample within a sbuframe. Based on 1.92MHz. Range is from 0 to 1920. SSS start offset of subframe. Range is from 0 to 9. SSS start calculation offset of sample within a subframe. Based on 1.92MHz. Range is from 0 to 1920. SSS start calculation offset of subframe. Range is from 0 to 9. Real part of SSS phase shift Imag part of SSS phase shift Real part of SSS phase shift 1 Imag part of SSS phase shift 1 Real part of SSS phase shift 2 Imag part of SSS phase shift 2 Real part of SSS phase shift 3 Imag part of SSS phase shift 3 Real part of SSS phase shift 4 Imag part of SSS phase shift 4 Real part of SSS phase shift 5 Imag part of SSS phase shift 5 Real part of SSS phase shift 6 Imag part of SSS phase shift 6 Real part of SSS phase shift 7 Imag part of SSS phase shift 7 Real part of SSS phase shift 8 Imag part of SSS phase shift 8 Real part of SSS phase shift 9 Imag part of SSS phase shift 9 Real part of SSS phase shift 10 Imag part of SSS phase shift 10 SSS internal sub frame counter(from 0 to 9) global sample count value at SSS subframe start global subframe count value at SSS subframe start Global radio frame count value at SSS subframe start Indicate the buffer selection on current interrupt 1b0: MEM0 is selection 1b1: MEM1 is selection SSS output buffer 0 status. Clear by DSP or MCU bit 2: 1b1: MEM2 or MEM0 is ready.1b0:buffer0 is idle SSS output buffer 0 status. bit 3: 1b1: MEM2 or MEM0 is over written. 1b0: buffer 0 is normal SSS output buffer 1 status. Clear by DSP or MCU bit 4: 1b1: MEM3 or MEM1 is ready.1b0:buffer1 is idle SSS output buffer 1 status. bit 5: 1b1: MEM3 or MEM1 is over written. 1b0: buffer 1 is normal SSS calculation done status. Update very 1ms and clear by DSP or MCU. 1b1: SSS calculation done 1b0: SSS is idle or under calculating SSS write memory arbitration error status. 0: Normal 1: Error Bit 7: DSP control bus error Bit 8: accelerator memory access collusion OFDM symbol CP offset which use to locate the FFT windows start position for serving cell. Value:[0:9] FFT result scaling 3d0: 2^-3 3d1: 2^-2 3d2: 2^-1 3d3: 2^0 3d4: 2^1 3d5: 2^2 Correlation result sScaling for both power and correlation 3d0: 20 3d1: 2-1 3d2: 2-2 3d3: 2-3 3d4: 2-4 3d5: 2-5(Default) 3d6: 2-6 3d7: 2-7 Cyclic shift value It is used when rSSS_CYCLIC_SHIFT_FIX_EN = 1'b1.Rang is from 0 to 2. Fix cyclic shift enable PCI ID It is used when rSSS_PCI_ID_FIX_RN = 1'b1 or rSSS_SIC_EN = 1'b1. Range is from 0 to 503. Fix PCI ID Enable. SIC Enable Used for succesive interference cancellation. SSS output ping-pong buffer selection 1b1:Select the pong buffer as the first output buffer 1b0: Select the ping buffer as the first output buffer Scaling for correlation only 3d0: 2-4 3d1: 2-3 3d2: 2-2 3d3: 2-1 3d4: 20(Default) 3d5: 21 3d6: 22 3d7: 23 SSS total power RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. RX interrupt DSP bitmap mask from 0 to 13. LSB is symbol 0. RX interrupt output OS 0 127 RX adjustment subframe count from 0 9 (auto clear in next subframe) RX adjustment symbol count from 0 13 (auto clear in next subframe) RX adjustment symbol direction (auto clear in next subframe) 0: advance 1: postpone RX coarse adjustment sample count from 0 138 in (chip unit) - (auto clear in next subframe) RX coarse adjustment sample direction (auto clear in next subframe) 0: advance 1: postpone RX fine adjustment sample count from 0 9 in (chip unit) - (auto clear in next subframe) RX fine adjustment sample direction (auto clear in next subframe) 0: advance 1: postpone RX interrupt symbol number 0-13 RX interrupt symbol number 0-13 RX interrupt buffer index Mirror rRX_INT_BUF_IDX_MCU register RX interrupt symbol number 0-13 RX interrupt symbol number 0-13 RX interrupt buffer index RX SFN number 0-1023 global sample count value at RX subframe start global subframe count value at RX subframe start global sample count value at RX subframe start global sample count value at RX radio frame start global subframe count value at RX radio frame start global sample count value at RX radio frame start global sample count value at TCU subframe start global subframe count value at TCU subframe start global sample count value at TCU subframe start TX coarse adjustment sample count from 0 1919 in (chip unit) - (auto clear in next subframe) TX coarse adjustment sample direction - (auto clear in next subframe) 0: advance 1: postpone 15KHz: TX fine adjustment sample count from 0 9 in (chip unit) 3.75Hz: TX fine adjustment sample count from (0 9) x 4 in (chip unit) Remark: SW should configure the sample boundary which is aligned to 3.75Hz sample if the timing adjustment between TX transmission. (auto clear in next subframe) TX fine adjustment sample direction - (auto clear in next subframe) 0: advance 1: postpone TX fine adjustment mode control: 0: adjust the boundary at the end of the current subframe 1: adjust the CP at the first symbol of the next TX global sample count value at TX subframe start global subframe count value at TX subframe start global radio frame count value at TX subframe start TX subsample control 0: sync with global subsample counter 1: only sync with RX subsample counter when TX is not on transmission Control RX coarse adjustment status Control RX fine adjustment status Control TX coarse adjustment status Control TX fine adjustment status Control adjustment enable 1: enable 0: disable Trigger to sample global counter position for DSP debegging global counter sample position when CAPTURE1_GLB_CNT is accessed global counter subframe position when CAPTURE1_GLB_CNT is accessed global counter radio frame position when CAPTURE1_GLB_CNT is accessed Trigger to sample global counter position for MCU debegging global counter sample position when CAPTURE2_GLB_CNT is accessed global counter subframe position when CAPTURE2_GLB_CNT is accessed global counter radio frame position when CAPTURE2_GLB_CNT is accessed For sleep operation When SLEEP_W is accessed, the start values needed for wake-up are loaded. Then values have to be written before the SLEEP_W is accessed Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for alignment of the DFE input valid. 0-31 global counter sample position in sleep mode (in chip unit) global counter subframe position global counter radio frame position Sample clock/32 (TX/RX sub-sample is always aligned with Global sub-sample) : this would use for align the DFE input valid. 0-31 RX sample count value RX OFDM symbol count value RX subframe count value Sleep Elapsed Subsample counter Range: 0-31 Sleep Elapsed Subsample counter Range: 0-1919 Sleep Elapsed SF counter Range: 0-2^32-1 TCU event subsample time TCU event subframe time RX synchronization method mode 0: normal mode 1: sync counter with input i_rx_sync_start pulse in DUMP mode only (For testing only) RX subframe count sync initialization value - 1 Global subframe count sync initialization value - 1 Global radio frame count sync initialization value - 1 RX Capture event sample time RX Capture event subframe time DSP memory 0 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 1 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 2 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 3 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 4 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 5 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock DSP memory 7 control 00: HW control with NB core clock 10: HW control with AHB clock 11: DSP control with AHB clock RX FFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Cell Search PSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Cell Search SSS sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX CFO sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX Viterbi sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX AGC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. RX DS_BSEL sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. TX frontend sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. PUSCH encoder sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. TX CHSC sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. FFT 512 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. NPRS acc1 sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. FINE_IFFT sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. rNBIOT general part reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. NC_RSRP sub-module reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. Enable/disable the clock for RX FFT/RSRP module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Cell Search module PSS 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Cell Search module SSS 0: clock disabled 1: clock enabled. Enable/disable the clock for RX CFO module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX Viterbi module 0: clock disabled 1: clock enabled. Enable/disable the clock for RX AGC module 0: clock disabled 1: clock enabled. Enable/disable the clock for DS_BSEL module 0: clock disabled 1: clock enabled. Enable/disable the clock for TX Frontend module. 0: clock disabled 1: clock enabled. Enable/disable the clock for PUSCH encoder module. 0: clock disabled 1: clock enabled. Enable/disable the clock for TX TX channel-interleaver and scrambling module. 0: clock disabled 1: clock enabled. Enable/disable the clock for FFT 512 module. 0: clock disabled 1: clock enabled. Enable/disable the clock for NPRS ACC1 module. 0: clock disabled 1: clock enabled. Enable/disable the clock for FINE ifft module 0: clock disabled 1: clock enabled. Enable/disable the clock for NBIOT module 0: clock disabled 1: clock enabled. Debug signal selection Debug signal output enable RFIN reset by DSP, it is used to re-timing the global timer to balance the timing of IQ data input from DFE in sample boundary. Write 1 and auto-clear by HW. 0: default value 1: reset to re-timing the sample boundary in global timer. Sample the glb_subsample_cnt with input rx_data_vld to check the phase change of the input Keep track the RFIN data strobe in valid window. 0: Normal 1: Error PSS Correlator coarse clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. SSS Correlator coarse clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. FFT_RSRP fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FFT_RSRP. PSS Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PSS Correlator. SSS Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module SSS Correlator. CFO Correlator fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module CFO Correlator. Viterbi fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module Viterbi. AGC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module AGC. DS_BSEL fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module DS_BSEL. TX_FRONTEND fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module TX_FRONTEND. PUSCH_ENC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module PUSCH_ENC. TX_CHSC fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module TX_CHSC. FFT 512 fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FFT 512. NPRS ACC1 fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module NPRS ACC1. FIne IFFT fine clock gating, 0: free running 1: clock gated by the clock enabled signal which generated from sub-module FINE_IFFT. NBIOT CORE APB domain reset by software, auto-clear to zero when write 1 to this register by DSP 0: default value; 1: Reset whole sub-module. Debug General Purpose Output Remark: need to set rNBIOT_MONITOR to 0x1a3 Minor Revision MAJOR Revision DS_BSEL accelerator start Maximum time out value for TX bit level processing in 61.44Mhz unit Number of Candidate 0: 1 candidate 1: 2 candidate 2: 3 candidate 3: 4 candidate Bit de-selection and combining 0: Disable 1: enable Remark: When this bit is disabled, the output data number is equal to rDESCR_SIZE0 and it only support 1 candidate. Descramble enable 0: Disable 1: enable NCB minus: NCB 3ND Descramble X1 value for candidate 0 Descramble X1 value for candidate 1 Descramble X1 value for candidate 2 Descramble X1 value for candidate 3 Descramble X2 value for candidate 0 Descramble X2 value for candidate 1 Descramble X2 value for candidate 2 Descramble X2 value for candidate 3 Descramble size 0 Descramble size 1 Descramble size 3 Descramble size 2 Descramble input buffer start address 0 Descramble input buffer start address 1 Descramble input buffer start address 3 Descramble input buffer start address 4 DS_BSEL output memory start address The last candidate Descramble X2 state value The last candidate Descramble X2 state value (This bit is write 1 clear) 0: No Done 1: Done If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion 0: Normal 1: Error FFT calculation enable the period of FFT done interrupt, 0: one time per-subframe; 1: twice per-subframe. FFT/RSRP enable FFT result scaling 0: FFT disabled, 5 RSRP CELLs calculation mode; 1: FFT + 2 RSRP Cell calculation mode. FFT OFDM symbol CP offset RSRP Cell0 Enabled. RSRP Cell1 Enabled. RSRP Cell2 Enabled. RSRP Cell3 Enabled. RSRP Cell4 Enabled. Frame start position of RSRP Cell0 based on global timer. Frame start position of RSRP Cell1 based on global timer. Frame start position of RSRP Cell2 based on global timer. Frame start position of RSRP Cell3 based on global timer. Frame start position of RSRP Cell4 based on global timer. OFDM symbol CP offset for NCELL0. OFDM symbol CP offset for NCELL1. OFDM symbol CP offset for NCELL2. OFDM symbol CP offset for NCELL3. OFDM symbol CP offset for NCELL4. vshift of NCELL0. vshift of NCELL1. vshift of NCELL2. vshift of NCELL3. vshift of NCELL4. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. confiugred subframe idx when RSRX cell enabled. Offset address for RSRP write memory buffer. Indicated whether the data in ping-pong buffer is updated. FFT buffer ping-pong flag Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. Indicated which triple buffer is UPDATED Indicated which buffer is just updated when interrupt asserted. subframe index of serving cell subframe idx of NCELL0 subframe idx of NCELL1 subframe idx of NCELL2 subframe idx of NCELL3 subframe idx of NCELL4 FFT pingpong buffer overwritten status RSRP Cell0 triple buffer over-written status. RSRP Cell1 triple buffer over-written status. RSRP Cell2 triple buffer over-written status. RSRP Cell3 triple buffer over-written status. RSRP Cell4 triple buffer over-written status. FFT write buffer bus error RSRP CELL0 write buffer bus error RSRP CELL1 write buffer bus error RSRP CELL2 write buffer bus error RSRP CELL3 write buffer bus error RSRP CELL4 write buffer bus error FFT pingpong buf idx RSRP0 Triple buffer idx RSRP1 Triple buffer idx RSRP2 Triple buffer idx RSRP3 Triple buffer idx RSRP4 Triple buffer idx FFT subframe idx RSRP Cell0 subframe idx RSRP Cell1 subframe idx RSRP Cell2 subframe idx RSRP Cell3 subframe idx RSRP Cell4 subframe idx Interrupt Masking bit for RX_INT_DSP Interrupt Masking bit for RX_INT_MCU Interrupt Masking bit for TX_INT_DSP Interrupt masking bit from the interrupt of fft_done_int Interrupt masking bit of NCELL0 decode done intterupt Interrupt masking bit of NCELL1 decode done interrupt Interrupt masking bit of NCELL2 decode done interrpt Interrupt masking bit of NCELL3 decode done interrupt Interrupt masking bit of NCELL4 decode done interrupt Interrupt masking bit of PSS SF done interrupt Interrupt masking bit of SSS SF done interrupt Interrupt masking bit of CFO SF done interrupt Interrupt masking bit of Viterbi decode done interrupt Interrupt masking bit of AGC interrupt masking Interrupt masking bit of DS_BSEL interrupt Interrupt masking bit of PUSCH encoder interrupt Interrupt masking bit of TX_CHSC interrupt Interrupt masking bit of FFT_512 done interrupt Interrupt masking bit of NPRS_ACC1 done interrupt Interrupt masking bit of FINE_IFFT done interrupt interrupt status of RX_INT_DSP, write 1 clear. Interrupt status of RX_INT_MCU, write 1 clear. Interrupt status of TX_INT_DSP, write 1 clear. Interrupt status of fft_sf_done_int Interrupt status of RSRP Cell0 decode done interrupt Interrupt status of RSRP Cell1 decode done interrupt Interrupt status of RSRP Cell20 decode done interrupt Interrupt status of RSRP Cell3 decode done interrupt Interrupt status of RSRP Cell4 decode done interrupt Interrupt status of PSS SF done interrupt Interrupt status of SSS SF done interrupt Interrupt status of CFO SF done interrupt Interrupt status of Viterbi decode done Interrupt status of AGC interrupt Interrupt status of DS_BSEL interrupt Interrupt status of PUSCH Encoder interrupt Interrupt status of TX_CHSC interrupt Interrupt status of FFT_512 done interrupt Interrupt status of NPRS_ACC1 done interrupt Interrupt status of FINE IFFT done interrupt Symbol power accumulation enable/disable signal and effective at subframe boundary. 1 : enable 0 : disable Gain used in shift and saturation of accumulation power value. Bit[3:0] Gain 0000 2^-24 (default) 0001 2^-23 0010 2^-22 0011 2^-21 Accumulation length of samples in every symbol. 0: 128 1: 64 2: 32 3: 16 Offset of samples from symbols boundaries which is the start boundary of agc symbol power calculation. Reading address for DSP to read asp response ram, and this register would auto-increment whenever access the rASP_RD_DATA register PING buffer address: 0~20 PONG buffer address: 21~41 Bit[27:16]: Q DC offset configuration Bit[11:0]: I DC offset configuration Report agc symbol power and DCC done status, write 1 to clear this status Index bit to indicate which buffer is updated of PING-PONG 1: PONG buffer data is updated 0: PING buffer data is updated Data = mem[rASP_RD_ADDR] which is the ASP response memory data content. The ASP_RD_ADDR would auto increase whenever access this register. ASP response Memory address range is 0-41 Address(0~6,21~27): symbol power, bit[15:0] for symbol 0,2,4,6,8,10,12 and bit[31:16] for symbol 1,3,5,7,9,11,13 Address(7~20,28~41):dc_offset value, bit[15:0] for I and bit[31:16] for Q Forward/Inverse FFT transform computing selection PING-PONG memory selection 1b0: Memory0; 1b1: Memory1. FFT scaling, it can be implemented by bit shift, 3d0: 2^-3 3d1: 2^-2 3d2: 2^-1 3d3: 2^0 (default) 3d4: 2^1 3d5: 2^2 3d6: 2^3 3d7: 2^4 FFT_amp_out scaling for amplitude square output, it can be implemented by bit shift, 3d0: 2^-3 3d1: 2^-2 3d2: 2^-1 3d3: 2^0 (default) 3d4: 2^1 3d5: 2^2 3d6: 2^3 3d7: 2^4 IFFT Output amptitude data 1b0: IFFT output normal data(I+j*Q); 1b1: IFFT output amptitude data(I^2+Q^2). FFT start indication, when write 1 to this register, a high active pulse will be generated and input to FFT engine to start FFT calculation. FFT done status, write 1 clear. An error grant is received when FFT request memory write bus to store FFT result. Bit1: DSP control error; Bit0: Accelerator memory access error. This register is used to check the range of FFT/IFFT input, 1b1: absolute maximum FFT/IFFT input less than 32, in this case, the resolution of FFT/IFFT output will loss 1bit; 1b0: normally. NPRS accelerator 1 Start Maximum time out value in 61.44Mhz unit Mode selection: 2b00: copy + dot product 2b01: dot product 2b10: copy Copy Source memory before sequence dot product 0: Memory 0 1: Memory 1 Copy memory with bit-reversed address write location enable 0: Disable 1: Enable Destination memory after sequence dot product 0: Memory 0 1: Memory 1 Dot Product from memory 5 to memory 0/1 with bit-reversed address write location enable 0: Disable 1: Enable Conjugate Sequence data Enable 0: Disable 1: Enable Operation length -1 Default : (511) Sequence Memory Start Offset Address (This bit is read write 1 clear) 0: No Done 1: Done If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error Read/Write process in Memory 0/1 (FFT/IFFT input/output memory) 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion Read/Write process in Memory 5 (Copied FFT memory) Read process in Memory 4 (Sequence memory) 0: Normal 1: Error Fine IFFT START A pulse to grigger the Fine IFFT NPRS Coarse Timing Result Range is from 0 to 272 Fine IFFT calculation offset. Range is from 0 to 95. Fine IFFT calculation length. Range is from 1 to 96. Fine IFFT output a+bj scaling 3d0:x2^0(default) 3d1:x2^-1 3d2:x2^-2 3d3:x2^-3 3d4:x2^-4 3d5:x2^-5 3d6:x2^-6 3d7:x2^-7 Fine IFFT output power scaling 3d0:x2^-3 3d1:x2^-2 3d2:x2^-1 3d3:x2^0 (default) 3d4:x2^1 3d5:x2^2 3d6:x2^3 3d7:x2^4 Fine IFFT output selection 1b0: Output IFFT result: a+bj 1b1: Output power result: a^2+b^2 Fine IFFT input data control 1b0: Input data in inverse order 1b1: Input data in inverse order and swap bit0~bit255 with bit256~bit511 Fine IFFT input data start address Fine IFFT output data start address Fine IFFT calculation done status. 1b1: Fine IFFT calculation done 1b0: Fine IFFT is idle or under calculating Fine IFFT output buffer status 1b1: Fine IFFT output buffer is over written 1b0: Fine IFFT output buffer is normal Fine IFFT calculation done status. 1b1: Fine IFFT calculation done 1b0: Fine IFFT is idle or under calculating Maximum time out value for TX channel-interleaver and scrambling in 61.44Mhz unit. Start control: 0: Trigger by SW start 1: Trigger by HW start. Channel interleaver enable 0: Disable 1: Enable. Scramble enable 0: Disable 1: Enable. TX channel-interleaver and scrambling accelerator 2 start. Bit selection memory start address. Scramble memory start output address. Ncb minus NCB - 3ND. K0 minus: K0 position without dummy bit.. Row size for ch-interleaver. Modulation type 0: BPSK 1: QPSK. Column size in each resource unit: (NUL_sym-1)* Nul_slot. scrambling size in current subframe. scrambling X1. scrambling X2. Last scrambling state in X1. Last scrambling state in X2. (This bit is read write 1 clear) 0: No Done 1: Done. If Done bit would not clear before this engine re-engine would indicate overwritten output buffer 0: Normal 1: Error 0: Normal 1: Error Bit 0: DSP control bus error Bit 1: accelerator memory access collusion 0: Normal 1: Error PUSCH offset1 for 3.75K process delay PUSCH offset0 for 15K process delay PRACH offset for process delay TA Value the advance time of PRACH start adjustment RF delay from NBIOT_CORE to chip output PUSCH Enable PRACH Enable Delta CP adjustment TX frame mode for PUSCH Module type TX Buffer idx CP length of PRACH0/1 PUSCH Tone mode Shorten PUSCH Enable PUSCH Subcarrier POsition TX Gain thetal symbol incremental step value symbol number modulo 2 memory bus access error TX Status, 2'b00: IDLE; 2'b01: PRACH; 2'b10: PUSCH 3.75K; 2'b11: PUSCH 15K Subframe index of NPRACH or NPUSCH transmitted PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH sub-carrier index 0~47 Reserved PRACH CFG Status Next PRACH symbol group enabled PRACH Nxt Command Read Pointer Reserved LPF1 coefficient0 LPF1 coefficient1 LPF1 coefficient2 LPF1 coefficient3 LPF2 coefficient0 LPF2 coefficient1 LPF2 coefficient2 TX dout checksum TX dout Checksum Enable Configurable Number of zero data padded at the end of TX transmission Maximum time out value for pusch encoder in 61.44Mhz unit. Endian SWAP control for bit, byte and word. Write this register will trigger pusch encoder start TB Size for PUSCH. Alpha init value for QPP interleaver. Alpha Step value for QPP interleaver. Rd address to DSP memory for pusch encoder. WR address to DSP memory for pusch encoder. (This bit is read write 1 clear) 0: No Done 1: Done. Indicate overwritten happen for pusch encoder 0: Normal 1: Error Bit 0: DSP control bus error, 0-Normal, 1-Error Bit 1: accelerator memory access collusion, 0-Normal, 1-Error 0: Normal 1: Error Start trigger of one sequential decoding of viterbi decoder which is generated by writing 1 to this register Payload size of CBs to be decoded in one sequential decoding Indicate the number(1~4) of coded blocks to be decoded in one sequential decoding process Function of de-interleaving in hardware enable/disable 1: Enable 0: Disable CRC mask checking enable/disable(for RNTI and antenna port number) 1: Enable 0: Disable Indicate the CRC type of sequential decoding 1:24 0:16 List viterbi mode enable/disable 1: Enable 0: Disable This register indicates the start address of viterbi output odd buffer for payload. This register indicates the start address of viterbi output even buffer for payload. This register indicates the start address of data in viterbi input ram. Indicate CRC mask1(for RNTI and antenna port number) Indicate CRC mask0(for RNTI and antenna port number) Indicate CRC mask1(for RNTI and antenna port number) Indicate CRC mask0(for RNTI and antenna port number) Reorder the 32bit data written to viterbi output buffer 2:Reverse the word sequence in the Dword(1Dword) 1: Reverse the byte sequence in every word(2words). 0: Reverse the bit sequence in every byte(4bytes). In a sequential decoding process, if the corresponding time counter exceeds this set value of rVD_TIMECNT_LIMIT, bit4 of rVD_DEC_SATUS will be set to 1 and sent to high layer. Indicate even/odd viterbi output buffer to be written by decoder: 1: odd output buffer 0: even output buffer Bit width of output scaling data's fractional part(S8.y) Bit width of input scaling data's fractional part(S16.x) This register(U8.7) is multiplied by scaling input data(S16.x) Bitmap of CRC masks(0~3) used in blind decoding for the CB3 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB2 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB1 to be decoded Bitmap of CRC masks(0~3) used in blind decoding for the CB0 to be decoded Subframe index of current subframe on which DSP configure the decoding start siganl 'rVD_DEC_START' 15: Antenna number for candidate CB3(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB3 15: Antenna number for candidate CB2(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB2 15: Antenna number for candidate CB1(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB1 15: Antenna number for candidate CB0(0: 1 antenna 1: 2 antennas) 14:12: 80ms SFN for candidate CB0 CRC checking result of the corresponding code block for output buffer odd, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 1: good 0: fail If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB [31:28] for CB3(28:MASK0, 29:MASK1, 30:MASK2, 31:MASK3) [27:24] for CB2(24:MASK0, 25: MASK1, 26: MASK2, 27: MASK3) [23:20] for CB1(20: MASK0, 21: MASK1, 22: MASK2, 23: MASK3) [19:16] for CB0(16: MASK0, 17: MASK1, 18: MASK2, 19: MASK3) And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB [28] for CB3 [24] for CB2 [20] for CB1 [16] for CB0 CRC check result of the corresponding code block for output buffer even, and CRC results from CB0 to CB3 have to be written sequentially to bit[0]~bit[15] of this register. 1: good 0: fail If rVD_CRCMASK_EN =1, 4 bits mask checking result is reported for every candidate CB [15:12] for CB3(12: MASK0, 13: MASK1, 14: MASK2, 15: MASK3) [11:8] for CB2(8: MASK0, 9: MASK1, 10: MASK2, 11: MASK3) [7:4] for CB1(4: MASK0, 5: MASK1, 6: MASK2, 7: MASK3) [3:0] for CB0(0: MASK0, 1: MASK1, 2: MASK2, 3: MASK3) And if rVD_CRCMASK_EN =0, 1 bit crc checking result is reported for every candidate CB [12] for CB3 [8] for CB2 [4] for CB1 [0] for CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Symbol error number of the candidate CB1 Symbol error number of the candidate CB0 Report some configurations to MCU for output buffer even [31:20] Report payload size [19:0] Report configuration of register rVD_CANDI_CFG Report some configurations to MCU for output buffer even [31:20] Report payload size [19:0] Report configuration of register rVD_CANDI_CFG Viterbi-in ram reading error Viterbi output buffer writing error This bit indicate that the time counter is exceed the limit of set value 3: This bit is to indicate that the odd memory is overwritten or not before UPDATED is cleared. 2: This bit is to indicate that the even memory is overwritten or not before UPDATED is cleared. 1: This bit is to indicate that the odd memory is updated or not. 0: This bit is to indicate that the even memory is updated or not. int clear int[15:0] int clear int[31:16] read only irq[15:0] read only irq[31:16] AFC PLL rxpll freq offset[15:0] AFC PLL rxpll freq offset[23:16] AFC PLL txpll freq offset[23:16] AFC PLL txpll freq offset[15:0] AFC PLL txpll1 freq offset[15:0] AFC PLL bbpll1 freq offset[23:16] AFC PLL bbpll2 freq offset[23:16] AFC PLL bbpll2 freq offset[15:0] AFC freq offset mode AFC freq offset mode AFC freq offset mode AFC freq offset mode sdm rxpll sdm rxpll sdm rxpll sdm rxpll freq_rxsdm[15:0] frequency dividing ratio for rxpll_div_bb[5:0] sdm rxpll freq_rxsdm[31:16] frequency dividing ratio for rxpll_div_bb[5:0] sdm rxpll sdm rxpll sdm rxpll 00: int divide; 01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm sdm rxpll sdm rxpll sdm rxpll reserved_sdm_rxsdm sdm rxpll sdm txpll sdm rxpll indication of dll_mode_txsdm being updated. write it to 1'b0 before assert it to 1'b1 sdm txpll sdm txpll indication feedback clock frequency: 2'b00: 182MHz, div 7 2'b01: 208MHz, div 8 2'b10: 234MHz, div 9 2'b11: 260MHz, div 10 sdm txpll sdm txpll sdm txpll 00: int divide; 01: 1 bit decimal divide;10: 2 bits decimal divide;11 :bypass sdm sdm txpll sdm txpll sdm txpll reserved_sdm_txsdm sdm txpll bbpll1 bbpll2 bbpll1 bbpll2 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 pll_reserved_rx bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 pll_reserved_dig_1_rx regplls1_0_bit bbpll1 pll_sdm_freq_rx[31:16] bbpll1 pll_sdm_freq_rx[15:0] bbpll1 reserved_sdm_rx bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 pll_reserved_dig_2_rx bbpll1 bbpll1 bbpll1 plls1_clk_cp26m_en,plls1_clk_cp624m_en,plls1_clk_sdio156m_en,plls1_clk_sdio416m_en bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll1 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 pll_reserved_tx bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 pll_reserved_dig_1_tx regplls2_0_bit bbpll2 pll_sdm_freq_tx[31:16] bbpll2 pll_sdm_freq_tx[15:0] bbpll2 reserved_sdm_tx bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 pll_reserved_dig_2_tx bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 [1] plls2_clk_cp307m_en bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 bbpll2 rxpll_cal target freq][15:8] rxpll_cal target freq[7:0] rxpll_cal [2:0]:rxpll_vco_bits[10:8] [6]:rxpll_cnt_enable [7]:rxpll_cal_enable rxpll_cal reset rxpll_cal [1]:rxpll_cal_opt [3:2]:rxpll_cnt_delay_sel [6:4]:rxpll_init_delay rxpll_cal rxpll_cal [7:0]:rxpll_vco_bits[7:0] rxpll_cal rxpll_cal rxpll_cal rxpll_cal rxvco_band_bit_bb txpll_cal target freq][15:8] txpll_cal target freq[7:0] txpll_cal [2:0]:txpll_vco_bits[10:8] [6]:txpll_cnt_enable [7]:txpll_cal_enable txpll_cal reset txpll_cal [1]:txpll_cal_opt [3:2]:txpll_cnt_delay_sel [6:4]:txpll_init_delay txpll_cal txpll_cal [7:0]:txpll_vco_bits[7:0] txpll_cal txpll_cal txpll_cal txpll_cal txvco_band_bit_bb gpio pa strobe pa strobe pa strobe pa strobe pa strobe pa strobe pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl pa ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ????? ana ctrl ????? ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl ana ctrl controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf controller rf clk gen clk gen clk gen clk gen clk gen clk gen clk gen clk gen clk gen clk gen chip id chip id revision_id mean_dccal_i0 mean_dccal_i1 mean_dccal_q bbpll2 bbpll1 analogy analogy analogy analogy pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa ramp pa_on_h direct value pa_on_h direct control, assert high threashold sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl sys ctrl DLPF vco band bit enable 0: TXPLL vco band bit is from pll_cal 1: TXPLL vco band bit is from DLPF reset DLPF IIR3, active low reset DLPF, active low cmd_mipi_sr[15:0] cmd_mipi_sr[31:16] data_mipi_sr[15:0] data_mipi_sr[31:16] data_out[15:0] data_out[31:16] REVERSED data_valid_byte[3:0] interrupt enable interrupt pending bit type is changed from w1s to rs. set interrupt pending bit type is changed from w1c to rc. clear interrupt pending Enable sleep sleep stauts 0: not_sleep 1: sleep when 1 written,core enters debug mode, when 0 written, core exits debug mode when read, 1 means core is in debug mode single step enable set when the core is a sleeping state and wait for an event single-step hit, sticky bit that must be cleared by external debugger environment call for M-mode store access fault (together with laf) store address Misaligned (never traps) load access fault (together with saf) load access Misaligned (never traps) ebreak instruction causes trap illegal instruction instruction access fault (not implemented) instruction address misaligned (never traps) interrupt caused us to enter debug mode exception/interrupt number general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register Next PC to be executed previous PC, already executed Statically 2'b11 and cannot be altered Interrupt enable: When an exception is encountered, Interrupt Enable will be set to 1'b0. When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS. If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code. When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. When an eret instruction is executed, the value from MEPC replaces the current program counter. this bit is set when the exception was triggerd by an interrupt exception code hardware loop 0 start hardware loop 0 end hardware loop 0 counter hardware loop 1 start hardware loop 1 end hardware loop 1 counter Statically 2'b11 and cannot be altered Interrupt enable: When an exception is encountered, the current value of MSTATUS is saved in MESTATUS. When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register. read as 0, which means RV32I RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0. ID of the cluster ID of the within the cluster [8]enable_clk_dac_afc; [9]dac_afc_bit select dig_rtc reg; [10]dig_afc_bit_dr; [13]step_offset_update; [0]vcore_vrtc_pwr_sel source select 0:vcore_vrtc_pwr_sel reg; 1:pu_xtal from IDLE_UART [1]pu_xtal_ana source select 0: pu_xtal_rtc from IDLE_UART; 1:pu_xtal reg [6]pu_xtal reg 0:pull down XTAL enter LP mode; 1:pull up XTAL enter normal mode [7]vcore_vrtc_pwr_sel reg 0: Vrtc power 1: Vcore power RTC [2]enable_clk26m_lp [6]idle_uart sw resetn 0:reset 1:release reset RTC RTC [9:8]lp_mode delay pu_xtal cycle select 2'b00: 4us; 2'b01:8us; 2'b10:12us; 2'b11:20us RTC 32k gen div step_offset LP mode 32k gen div step_offset Normal mode [5]lp_mode_en_dr; [4]lp_mode_en_reg; [7]change_reg_flag_dr; [6]change_reg_flag_reg; [3]lp_mode_h_dr; [2]lp_mode_h_reg; to XTAL for input clk_26m enable CAFC BBPLL2 ref clk 26m enable BBPLL1 ref clk 26m enable tsxadc clk 26m enable XTAL parameter pwdadc clk 26m enable xtal_osc_ibit lp mode xtal_osc_ibit normal mode RFPLL refcal clk 26m oscadc clk 26m enable xtal_fixi_bit lp mode xtal_fixi_bit normal mode pmic clk 26m enable clk_26m_interface enable xdrv pmic parameter xdrv aux2 parameter xdrv aux1 parameter xdrv parameter xtal_hsel lp mode CADC bit lp mode xtal_hsel normal mode CADC bit normal mode RTC RTC for TXDP modules after RC 0: use unmasked 61.44MHz clk when polarIQ disabled 1: use 26m_fbc clk when polarIQ enabled 1: use external resetn, 0-use sw/enable generated internal resetn for rxdp 0: clk_dac 1: clk_dac invert 0: clk_adc 1: clk_adc invert 0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT, 9:eMTC 0:GGE, 1:NB, 2:LTE-1.4M, 3:LTE-3M, 4:LTE-5M, 5:LTE-10M, 6:LTE-15M, 7:LTE-20M, 8:WT 0: SDM mode 1: SAR mode 0:26M/30.72MHz 1:52M/61.44MHz 2:104M/122.88MHz 0: ZF mode 1: IF mode 0: registers module clk gating enabled; 1: registers module clk always on 0: RX CIC1 doesn't work in loft mode; 1: RX CIC1 works in loft mode reset for ET, active low clock enable for ET sw controlled resetn for rxdp 0: assert reset 1: not reset DFE clock shift control. 0: clock shift disabled 1: clock shift enabled. When it is enabled, all DFE clocks except GSM TX clock are working in 17/16 normal frequency clock enable for BB GGE @26MHz clock enable for BB LTE @122.88MHz clock enable for BB NB/WT @61.44MHz clock enable for DFE NB/WT/LTE TX clock enable for DFE GSM TX clock enable for DFE RX clock enable for DAC clock eanble for ADC Start to load DC value, active high. Before next load, set it low firstly IQ swap in DC module 0: no swap 1. swap Hold DC accumulator calculation in DC calibration mode This register is not used. But DC module bypass is actrually controlled by register rxdp_bypass_dcc and rxdp_bypass_mode_dcc Store initial value to DC accumulator at positive edge in DC cancel mode or DC calibration mode. Load DC value in calibration mode to debug port, only used for debug purpose DC module work mode. 0: DC calibration mode 1: DC cancel mode DC real part value used in cancel mode DC image part value used in cancel mode Accumulator initial real part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Accumulator initial image part value, which is strored at positive edge of dcc_dc_delta_ld_st_rg register Slow convergence control, work with conv_mode_ct_rg register Fast convergence control, work with conv_mode_ct_rg register Duration time of DC calibration, which is based on sample unit DC convergence loop mode selection. 0: fast 1: slow 2: fast->slow 3: fast->hold load rxdp_gain_ct to DFE. Write it to 1b'0 before assert it bypass rxdp_gain_ct_load Gain BB control. [-24db, 47.9375db], step=1/16db Bit [15:0] of RX group delay coefficient 0 Bit [19:16] of RX group delay coefficient 0 Bit [15:0] of RX group delay coefficient 1 Bit [19:16] of RX group delay coefficient 1 Bit [15:0] of RX group delay coefficient 2 Bit [19:16] of RX group delay coefficient 2 Bit [15:0] of RX group delay coefficient 3 1: LP 0: BP Bit [19:16] of RX group delay coefficient 3 Read rate of DFE ADC FIFO, which depends on RX mode. 5'h00: GGE 5'h01: NB/WT Write enable of DFE ADC FIFO, active high Valid indication of DC value after assert rxdp_dcc_load to avoid metastability. rxdp_dcc_re_o and rxdp_dcc_im_o are stable when this register is high Real part of DC value, it is stable when rxdp_dcc_val_reg is high Image part of DC value, it is stable when rxdp_dcc_val_reg is high Data enable of Notch DC 0: disable 1: enable Coefficient a for real part of Notch DC Coefficient a for image part of Notch DC Coefficient k of Notch DC mrrm bandwidth selection Data enable of Notch H 1st core 0: disable 1: enable Data enable of Notch H 2nd core 0: disable 1: enable Coefficient a for real part of Notch H 1st core Coefficient a for image part of Notch H 1st core Coefficient a for real part of Notch H 2nd core Coefficient a for image part of Notch H 2nd core Coefficient k of Notch H 1st core Coefficient k of Notch H 2nd core Coefficient COEF0 of ACI filter Coefficient COEF1 of ACI filter Coefficient COEF2 of ACI filter Coefficient COEF3 of ACI filter Coefficient COEF4 of ACI filter Coefficient COEF5 of ACI filter Coefficient COEF6 of ACI filter Coefficient COEF7 of ACI filter Coefficient COEF8 of ACI filter Coefficient COEF9 of ACI filter Coefficient COEF10 of ACI filter Coefficient COEF11 of ACI filter Coefficient COEF12 of ACI filter Coefficient COEF13 of ACI filter Coefficient COEF14 of ACI filter Coefficient COEF15 of ACI filter Coefficient COEF16 of ACI filter Coefficient COEF17 of ACI filter Coefficient COEF18 of ACI filter Coefficient COEF19 of ACI filter Coefficient COEF20 of ACI filter Coefficient COEF21 of ACI filter Coefficient COEF22 of ACI filter Coefficient COEF23 of ACI filter Bit [15:0] of frequency offset for Mixer Bit [23:16] of frequency offset for Mixer Outband RSSI enable Inband RSSI enable Outband RSSI ushift value Inband RSSI ushift value delay count to discard some initial samples sample select in 12x data rate sample number per symbol 0: 541K, 2x 1: 1.08M, 4x sample select in 192K data rate 0: 192K 1: 96K=192K/2 2: 64K=192K/3 .... 15: 12K=192K/16 sel CIC2 mode 00: mode0, divided by 40, 96K 01: mode1, divided by 20, 192K 10/11: mode2, divided by 10, 384K load rxdp_gain_ct_rf to DFE. Write it to 1b'0 before assert it bypass rxdp_gain_ct_rf_load Gain RF control. [-24db, 47.9375db], step=1/16db start inband RSSI max and min measurement timer count[15:0] for max and min measurement report after start timer count[31:16] for max and min measurement report after start start to load max and min measurement report. Before next load, set it low firstly valid of max and min measurement report inband RSSI min value inband RSSI max value, it is stable when rssi_max_min_val_reg_ib_rssi is high interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear indication to read instant measurement report valid of instant measurement report inband RSSI instant value start outband RSSI max and min measurement timer count[15:0] for max and min measurement report after start timer count[31:16] for max and min measurement report after start indication to read max and min measurement report valid of max and min measurement report outband RSSI min value outband RSSI max value interrupt status to be able to start to load max and min measurement report interrupt mask interrupt clear indication to read instant measurement report valid of instant measurement report outband RSSI instant value for WD outband RSSI instant value for UP outband RSSI instant value for DN delay counter for rx_en RX IQ swap RX clock invert or not enable digrf RX delay counter for tx_data TX clock invert or not TX mode. 0: block mode 1: stream mode Interp. HBF1 0: SW bypass disable 1: SW bypass enable Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter No use Gain_RF Group Delay Equ No use Notch(DC) Mixer RC Deci.CIC2 DC Calib.&Cancel Deci.CIC1 dnhb2 imbc mrrm No use deci_digrf Interp. HBF3 Interp. HBF2 Interp. HBF1 0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement 1: bypass controlled by SW. When it is set, rxdp_bypass_uphb1 will be used Gain_BB Notrch(H) 2nd core Notrch(H) 1st core Deci. HBF1 ACI Filter No use Gain_RF Group Delay Equ No use Notch(DC) Mixer RC Deci.CIC2 DC Calib.&Cancel Deci.CIC1 dnhb2 imbc mrrm No use deci_digrf Interp. HBF3 Interp. HBF2 instant value of rxdp_dcc_re instant value of rxdp_dcc_im instant value of rssi_reg_ib_rssi instant value of rssi_reg_wd_ob_rssi instant value of rssi_reg_up_ob_rssi instant value of rssi_reg_dn_ob_rssi instant value of rxdp_imbc_wa_out instant value of rxdp_imbc_wq_out Coefficient a1 for PLL Equ. Coefficient a2 for PLL Equ. Coefficient b1 for PLL Equ. Coefficient b2 for PLL Equ. Bit [27:12] of gain for PLL Equ. It is valid when AFC adjustment is being enabled Bypass load_g: 0: disable bypass 1: enable bypass Bypass PLL Equ: 0: disable bypass 1: enable bypass No use 4 LSB control Former output shift control No use no use Bit [34:32] for GSM TX frequency use former output or not 0: RX don't use 1: TX use Bit [15:0] for GSM TX frequency Bit [31:16] for GSM TX frequency Offset add to GSM TX frequency Output control for TX SDM frequency 0: freqency from register 1: freqency from psdm, used by GSM or polarIQ No use No use No use No use GSM TX frequency control. 0: modulation signal act on GSM TX freqency 1: GSM TX freqency is fixed GSM TX frequency load is at the same time of AFC adjustment or not 0: at the same time 1: not at the same time Clear bit for read point of GSM TX FIFO Clear bit for write point of GSM TX FIFO PN test enable The mode of pseudo random polynomial The initial phase selection of differential encoding The differential encoding enable for GSM TX data Bit [11:0] of gain for PLL Equ. It works with register txdp_gsm_g_rg txdp polar1 delay txdp polar0 delay gsm_grp_dly_coff1_rg[15:0] gsm_grp_dly_coff1_rg[19:16] gsm_grp_dly_coff2_rg[15:0] gsm_grp_dly_coff2_rg[19:16] gsm_grp_dly_coff3_rg[15:0] gsm_grp_dly_coff3_rg[19:16] gsm_grp_dly_coff4_rg[15:0] gsm_grp_dly_coff4_rg[19:16] register value from GSM upper and low branch position of txdp_gdequ(2) in txdp_gsm 0: upper branch 1: low branch MDLL mode: 0: 26MHz*7 1: 26MHz*8 2: 26MHz*9 3: 26MHz*10 upper branch enable in txdp_gsm for 2P modulation bypass txdp_uplpf(2) in txdp_gsm load gsm_grp_dly_in_rg to DFE, assert it to load. Before load, write it to low firstly input mode for upper and low branch: 0: from DFE register, gsm_grp_dly_in_rg 1: from DFE function bypass txdp_gdequ(2) in txdp_gsm vco_gain for upper branch register value for data_pm_dac[15:0] bypass for data_pm_dac: 0: data_pm_dac from DFE function 1: data_pm_dac from DFE regsiter register value for data_pm_dac[30:16] load txdp_wedge_gain_ct to DFE. Write it to 1b'0 before assert it bypass txdp_wedge_gain_ct_load Gain control of NB/WT TX. [-24db, 47.9375db], step=1/16db Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Amplitude compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Phase compensation curve of DPD Coefficient 4 of ACLR filter Coefficient 5 of ACLR filter Coefficient 6 of ACLR filter Coefficient 7 of ACLR filter divide resource of clk_dac when test mode. 0: divide by 1 1: divide by 2 2: divide by 4 3: divide by 8 4: divide by 16 5: divide by 32 6: divide by 64 7: divide by 128 8: divide by 256 default: divide by 1 resource of clk_dac when test mode. 00: clk_26m 01: clk_245p76m 10: clk_fbc 11: clk_adc_gge_nb enable clk_dac when test mode 0: clk_dac is from function mode 1: clk_dac is from test mode txdp iq delay Coefficient 0 of ACLR filter Coefficient 1 of ACLR filter Coefficient 2 of ACLR filter Coefficient 3 of ACLR filter Bit [15:0] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 0 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 1 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 2 of group delay equ. for NB/LTE/eMTC TX Bit [15:0] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX Bit [19:16] of coefficient 3 of group delay equ. for NB/LTE/eMTC TX value to be delayed for phase part Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX Coefficient of PolarIQ LPF in DPD for NB/LTE/eMTC TX no use no use no use no use no use BB TX data loopback to BB RX BB RX IQ swap. 1: swap; 0: normal BB TX IQ swap. 1: swap; 0: normal ADC IQ swap. 1: swap; 0: normal DAC IQ swap. 1: swap; 0: normal BB RX. 0: two's complement 1: offset binary BB TX. 0: two's complement 1: offset binary RF ADC. 0: two's complement 1: offset binary RF DAC. 0: two's complement 1: offset binary instant value of txdp_loft_rssi_err valid indication of temper_dout after assert temper_pout_load to avoid metastability. Thetemper_dout is stable when this register is high start to load the result of temper_dout. Before next load, set it low firstly bandwidth select no use temper_dout value clock enable for temper divide mode of clock from analog for Temcomp 0: not divide 1: 1/2 divide 2: 1/4 divide 3: 1/8 divide clock invert for Temcomp 0: clock invert disable 1: clock invert enable clock enable for temcomp divide mode of clock from analog for Temcomp 0: not divide 1: 1/2 divide 2: 1/4 divide 3: 1/8 divide clock invert for Temcomp 0: clock invert disable 1: clock invert enable force bypass, high valid bypass, high valid no use set sdm frequency value, high valid sdm frequency value, high 8 bits sdm frequency value, low 16 bits Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter Coefficient of filter valid indication of temcom_pwd_dout after assert temcom_pout_load to avoid metastability. The temcom_pwd_dout is stable when this register is high start to load the result of thermometer. Before next load, set it low firstly temperature calibration LPF bypass, high valid temperature calibration LPF shift value 0 : left shift by 7 bit 1 : left shift by 6 bit 2 : left shift by 5 bit 3 : left shift by 4 bit 4 : left shift by 3 bit 5 : left shift by 2 bit 6 : left shift by 1 bit 7 : left shift by 0 bit select badwidth no use no use temcom result instant value of temper_dout instant value of temcom_pwd_dout swap of dfe_monitor[15:8] and dfe_monitor[7:0] dfe_monitor select The offset on DAC real part The offset on DAC image part The DAC real part on test mode The DAC image part on test mode Interp.CIC2 config mode for WT: 000: 60, 16K to 960K 001: 30, 32K to 960K 010: 25, 38.4K to 960K 011: 10, 96K to 960K others: 5, 192K to 960K select of function DAC data or test DAC data 00/01: select function DAC data including sine waveform 10: select test DAC data in txdp 11: select test DAC data in txdp enable sine generation module enable of test DAC data in rxdp select of test DAC data in rxdp enable of test DAC data in txdp select of test DAC data in txdp sine amp sine frequency[15:0] LOFT LOFT sine frequence[22:16] UPLPF(1) Interp. CIC1 0: SW bypass disable 1: SW bypass enable UPHBF(3) UPHBF(2) Group Delay Equ. LPF of DPD only when PolarIQ AMPM of DPD Split of DPD Whole DPD RC Gain UPHBF(5) when PolarIQ UPHBF(4) when PolarIQ UPHBF(1) ACLR LPF ampequ UPLPF(1) Interp. CIC1 0: bypass controlled by HW. HW bypass module automaticlly based on algorithm requirement 1: bypass controlled by SW. When it is set, txdp_bypass_cic1 will be used UPHBF(3) UPHBF(2) Group Delay Equ. LPF of DPD only when PolarIQ AMPM of DPD Split of DPD Whole DPD RC Gain UPHBF(5) when PolarIQ UPHBF(4) when PolarIQ UPHBF(1) ACLR LPF ampequ no use clock enable for BB side when adc-dfe-lvds-bb, enable when lvds_rx_mode is 3 no use clock enable for ADC RX when adc-lvds-dfe-bb, enable when lvds_rx_mode is 1 clock enable for DAC TX when bb-dfe-lvds-dac, enable when lvds_rx_mode is 0 clock enable for lvds_tx, enable when lvds_tx_mode is 0/1/2/3 no use no use no use no use 3: lvds_rx in adc-dfe-lvds-bb 2: lvds_rx in bb-lvds-dfe-dac 1: lvds_rx in adc-lvds-dfe-bb 0: lvds_rx in bb-dfe-lvds-dac 3: lvds_tx in adc-dfe-lvds-bb 2: lvds_tx in bb-lvds-dfe-dac 1: lvds_tx in adc-lvds-dfe-bb 0: lvds_tx in bb-dfe-lvds-dac LVDS enabled in DFE frequency select of dfe2lvds_clk when bb-lvds-dfe-dac. 0: 7.68MHz 1: 15.36MHz 2: 30.72MHz 3: 61.44MHz frequency select of dfe2lvds_clk when adc-dfe-lvds-bb. 0: 7.68MHz 1: 15.36MHz 2: 30.72MHz 3: 61.44MHz clock select in BB side when adc-dfe-lvds-bb and bb-lvds-dfe-dac 0: use LVDS clock 1: use BBPLL clock frequency indication of lvds2dfe_clk_dig_ref from LVDS 0: 122.88MHz 1: 61.44MHz iq swap on lvds2dfe_data iq swap on dfe2lvds_data all zero bits, reserved for ECO all one bits, reserved for ECO 1: clk always on, 0: clk gating by hardware 1: clk always on, 0: clk gating by hardware 1: clk always on, 0: clk gating by hardware determine dac bits position when test mode. 0:[11:0], 1:[12:1], 2:[13:2], 3:[14:3], 4: [15:4] Bit [11:0] of coefficient 0 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 1 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 2 of ampequ. for NB/LTE/eMTC TX Bit [11:0] of coefficient 3 of ampequ. for NB/LTE/eMTC TX Bit [27:12] of gain for ampequ. for NB/LTE/eMTC TX Bit [11:0] of gain for ampequ. It works with register txdp_ampequ_g_rg read interval for FIFO A read interval for FIFO B read interval for FIFO C read interval for FIFO D FIFO dump full FIFO dump empty FIFO txdp_rc full FIFO txdp_rc empty FIFO rxdp_rc full FIFO rxdp_rc empty FIFO ADC full FIFO ADC empty, this FIFO used between ADC and DFE FIFO D full FIFO D empty, this FIFO used when LVDS RX for bb-lvds-dfe-dac FIFO C full FIFO C empty, this FIFO used when normal TX or LVDS TX for bb-lvds-dfe-dac FIFO B full FIFO B empty, this FIFO used when LVDS RX for adc-dfe-lvds-bb FIFO A full FIFO A empty, this FIFO used when normal RX or LVDS TX for adc-dfe-lvds-bb clock frequency select when dump FIFO write 00000000: clk_122p88m_m 00000001: clk_61p44m_m 0000001x: clk_rxdp 000001xx: clk_rxdp_m 00001xxx: clk_txdp 0001xxxx: clk_245p76m_m(i.e., clk_txdp_m) 001xxxxx: lvds2dfe_clk 01xxxxxx: lvds2dfe_clk_dig_ref 1xxxxxxx: clk_pwd clock frequency select when dump FIFO read 0: 122.88Mhz 1: 61.44MHz enable dump dump node selection. It works with register sel_clk_dump_w for correct clock. 0: dump RX data from DFE, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref 1: dump TX data from BB, sel_clk_dump_w can be clk_122p88m_m/clk_61p44m_m/lvds2dfe_clk_dig_ref 2: dump RXDP data, sel_clk_dump_w can be clk_rxdp/clk_rxdp_m 3: dump TXDP data, sel_clk_dump_w can be clk_txdp/clk_245p76m_m(clk_txdp_m)/clk_pwd others: dump data from LVDS, sel_clk_dump_w can be can be lvds2dfe_clk DLPF output clk_rdac enable. 0: disable 1: enable DLPF sdm bypass 1'b0: digital DLPF 1'b1: analog DLPF vco data add enable read vco data from fifo enable vco data write into fifo enable no use register to analog DLPF MDLL mode 0: 26x7MHz 1: 26x8MHz 2: 26x9MHz 3: 26x10MHz DLPF notch bypass DLPF output clock inverse DLPF input clock inverse DLPF lock mode enable DLPF no use DLPF output direct control DLPF output direct value DLPF afc phase offset DLPF kdco phase offset DLPF gain kp afc DLPF gain ki afc DLPF gain kp 2m DLPF gain ki 2m DLPF gain kp 200k DLPF gain ki 200k DLPF IIR0 gain0[15:0] DLPF IIR0 gain1[15:0] DLPF IIR1 gain0[15:0] DLPF IIR1 gain1[15:0] DLPF IIR1 gain1[16] DLPF IIR1 gain0[16] DLPF IIR0 gain1[16] DLPF IIR0 gain0[16] diff_sel[2:0] afc_diff_thr[15:0] afc_diff_thr[31:16] afc_cnt_thr lock_2m_diff_thr[15:0] lock_2m_diff_thr[31:16] lock_2m_cnt_thr lock_200k_diff_thr[15:0] lock_200k_diff_thr[31:16] lock_200k_cnt_thr timer0_cnt[15:0] timer0_cnt[31:16] timer1_cnt[15:0] timer1_cnt[31:16] timer2_cnt[15:0] timer2_cnt[31:16] DLPF capture enable to dump internal values real time afc_code DLPF detect status read time kdco_code captured afc_code captured kdco_code tdc_code dlpf_add dlpf_gain0[15:0] dlpf_gain0[22:16] dlpf_gain1[15:0] dlpf_gain1[30:16] dlpf_sum0[15:0] dlpf_sum0[31:16] dlpf_sum0[38:32] iir0_sum0[15:0] iir0_sum0[31:16] iir0_sum0[43:32] iir0_sum0_reg[15:0] iir0_sum0_reg[31:16] iir0_sum0_reg[43:32] iir0_data[15:0] iir0_data[31:0] iir1_sum0[15:0] iir1_sum0[31:16] iir1_sum0[43:32] iir1_sum0_reg[15:0] iir1_sum0_reg[31:16] iir1_sum0_reg[43:32] iir1_data[15:0] iir1_data[31:16] lpf2_data[15:0] lpf2_data[31:16] DLPF reserved control bit. [15:3] reserved [1] IIR2 bypass [0] IIR1 bypass DLPF IIR3 output valid input data select: 1'b0: gro output 1'b1: dlpf notch output load DLPF IIR3 output decimator start point in dnsc bypass 256 dnsc DLPF IIR3 input clock inverse enable DLPF IIR3 reset DLPF IIR3, active low a11[15:0] a12[15:0] a21[15:0] a21[19:16] a12[19:16] a11[19:16] g1[15:0] g2[15:0] g2[19:16] g1[19:16] IIR3 output input iq_in and clk_in rate ratio 0: 1:1 1: 1:2 2: 1:3 .... input ET_CLK signal: 0: wide half clk 1: wide 1 clk 2: wide 2 clk ... 127: wide 127 clk 0: IQ sel IQ_IN[13:2] 1: IQ sel IQ_IN[12:1] 2: IQ sel IQ_IN[11:0] data to ETAPC frac delay: 1/16 datarate step, 015 data to ETAPC int delay: 2us, 063 Q0 Q15 cic fir enable cic fir enable hb fir enable 0 : {iq_re , iq_im[11:0] } 1 : {hb_re , hb_im[11:0] } 2 : {env_dato , 16'h0 } 3 : {dlyint_dato , 16'h0 } 4 : {dlyfrac_dato, 16'h0 } 5 : {dtr_dato , 16'h0 } 6 : {iir_dato , 16'h0 } 7 : {log_dato , 16'h0 } 8 : {modif_dato , 16'h0 } 9 : {tpc_dato , 16'h0 } 10 : {p2v_dato , 16'h0 } 11 : {volt_dato , 16'h0 } 12 : {cic1_dato , 16'h0 } 13 : {notch_dato , 16'h0 } 14 : {cic2_dato , 16'h0 } 15 : {clip_dato , 16'h0 } 0: hardware auto open clock 1: software force open clock Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Three Quarter of FIFO interrupt status bit. Quarter of FIFO interrupt status bit. Half of FIFO interrupt status bit. End of FIFO interrupt status bit. Cause interrupt Three Quarter of FIFO. Cause interrupt Quarter of FIFO. Cause interrupt Half of FIFO. Cause interrupt End of FIFO. When 1 the fifo is empty When 1 the channel is enabled AHB Start Address. This field represent the start address of the FIFO located in RAM. Fifo size in bytes, max 32kBytes. The size of the fifo must be a multiple of 16 (The four LSB are always zero). THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. QUARTER FIFO Mask interrupt. When one this interrupt is enabled. HALF FIFO Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. bit type is changed from w1c to rc. Write one to clear Three Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear half of fifo interrupt. bit type is changed from w1c to rc. Write one to clear end of fifo interrupt. Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Three Quarter of FIFO interrupt status bit. Quarter of FIFO interrupt status bit. Half of FIFO interrupt status bit. End of FIFO interrupt status bit. Cause interrupt Three Quarter of FIFO. Cause interrupt Quarter of FIFO. Cause interrupt Half of FIFO. Cause interrupt End of FIFO. When 1 the fifo is empty When 1 the channel is enabled AHB Start Address. This field represent the start address of the FIFO located in RAM. Fifo size in bytes, max 32kBytes. The size of the fifo must be a multiple of 16 (The four LSB are always zero). THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. QUARTER FIFO Mask interrupt. When one this interrupt is enabled. HALF FIFO Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. bit type is changed from w1c to rc. Write one to clear Three Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear half of fifo interrupt. bit type is changed from w1c to rc. Write one to clear end of fifo interrupt. Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. Automatic channel Disable. When this bit is set, the channel is automatically disabled at the next interrupt. Channel Disable, write one in this bit disable the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disabled. Channel Enable, write one in this bit enable the channel. When the channel is enabled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. Three Quarter of FIFO interrupt status bit. Quarter of FIFO interrupt status bit. Half of FIFO interrupt status bit. End of FIFO interrupt status bit. Cause interrupt Three Quarter of FIFO. Cause interrupt Quarter of FIFO. Cause interrupt Half of FIFO. Cause interrupt End of FIFO. When 1 the fifo is empty When 1 the channel is enabled AHB Start Address. This field represent the start address of the FIFO located in RAM. Fifo size in bytes, max 32kBytes. The size of the fifo must be a multiple of 16 (The four LSB are always zero). THREE QUARTER FIFO Mask interrupt. When one this interrupt is enabled. QUARTER FIFO Mask interrupt. When one this interrupt is enabled. HALF FIFO Mask interrupt. When one this interrupt is enabled. END FIFO Mask interrupt. When one this interrupt is enabled. bit type is changed from w1c to rc. Write one to clear Three Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear Quarter fifo interrupt. bit type is changed from w1c to rc. Write one to clear half of fifo interrupt. bit type is changed from w1c to rc. Write one to clear end of fifo interrupt. Current AHB address value. The nine MSB bit is constant and equal to the PAGE_ADDR field in the IFC_CH_AHB_START_ADDR register. Reset the complete BLE Core except registers and timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. In case of Dual Mode implementation, reset also common blocks. Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Forces the generation of ble_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. Abort the current RF Testing defined as per CS-FORMAT when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested 1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. Abort the current Advertising event when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Abort the current scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0: Normal operation of MD bits management 1: Allow a single Tx/Rx exchange whatever the MD bits are. - value forced by SW from Tx Descriptor - value just saved in Rx Descriptor during reception 0: Normal operation of Sequence number 1: Sequence Number Management disabled: - value forced by SW from Tx Descriptor - value ignored in Rx -> No SN error reported. 0: Normal operation of Acknowledge 1: Acknowledge scheme disabled: - value forced by SW from Tx Descriptor - value ignored in Rx -> No NESN error reported. 0: Normal operation. Encryption / Decryption enabled. 1: Encryption / Decryption disabled. Note that if CS-CRYPT_EN is set, then MIC is generated, and only data encryption is disabled, meaning data sent are plain data. 0: Normal operation. Whitening enabled. 1: Whitening disabled. 0: Normal operation. CRC removed from data stream. 1: CRC stripping disabled on Rx packets, CRC replaced by 0x000 in Tx. 0: Normal operation. Frequency Hopping Remapping algorithm enabled. 1: Frequency Hopping Remapping algorithm disabled Advertising Channels Error Filtering Enable control 0: RW-BLE Core reports all errors to RW-BLE Software 1: RW-BLE Core reports only correctly received packet, without error to RW-BLE Software 0: Disable RW-BLE Core Exchange Table pre-fetch mechanism. 1: Enable RW-BLE Core Exchange table pre-fetch mechanism. Default Rx Window size in 2s. Used when device - is master connected - performs its second receipt. 0 is not a valid value. Recommended value is 10 (in decimal). Indicates the maximum number of errors allowed to recognize the synchronization word. RW-BLE Core Type C 0x8 means BLE v4.2 (i.e. correspond LL version assigned number). Correspond to FS v8.0.10) RW-BLE Core version C Major release number. Correspond to FS v8.0.10 RW-BLE Core upgrade C Upgrade number. Correspond to FS v8.0.10 RW-BLE Core Build C Build number 0: RW-BLE Core is used as a standalone BLE device 1: RW-BLE Core is used in a Dual Mode device Number of supported Isochronous Channel (0 to 3) 00: No ISO/Audio Channel available 01: One ISO/Audio Channel available 10: Two ISO/Audio Channels available 11: Three ISO/Audio Channels available 0: AES deciphering not present 1: AES deciphering present 0: WLAN Coexistence mechanism not present 1: WLAN Coexistence mechanism present (Default Value) RFIF[k]= 0: Control logic supporting radio k not present RFIF[k]= 1: Control logic supporting radio k present Index k values are: 00001: Ripple RF. 00010: External Radio Controller Support 00100: IcyTRx Radio xxx000: Reserved Default value is 0000001 0: Diagnostic port not instantiated 1: Diagnostic port instantiated (Default Value) 0: AES-CCM Encryption block not present 1: AES-CCM Encryption block present (Default Value) Operating Frequency (in MHz) Default value is 13MHz 0: Interrupts are edge level generated, i.e. pulse. 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement (Default Value) Processor Bus Type 0: AHB Bus 1: X-Bar Bus Processor bus width: 0: 16 bits (Default Value) 1: 32 bits Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary. Default value is 13 (in decimal) CSCNT interrupt mask during event. This bit allows to enable CSCNT interrupt generation during events (i.e. advertising, scanning, initiating, and connection) 0: CSCNT Interrupt not generated during events. 1: CSCNT Interrupt generated during events. Audio channel 2 interrupt Mask 0: Interrupt not generated 1: Interrupt generated Audio channel 1 interrupt Mask 0: Interrupt not generated 1: Interrupt generated Audio channel 0 interrupt Mask 0: Interrupt not generated 1: Interrupt generated SW triggered interrupt Mask 0: Interrupt not generated 1: Interrupt generated End of event / anticipated pre-fetch abort interrupt Mask 0: Interrupt not generated 1: Interrupt generated Fine Target Timer Mask 0: Interrupt not generated 1: Interrupt generated Gross Target Timer Mask 0: Interrupt not generated 1: Interrupt generated Error Interrupt Mask 0: Interrupt not generated 1: Interrupt generated Encryption engine Interrupt Mask 0: Interrupt not generated 1: Interrupt generated End of event Interrupt Mask 0: Interrupt not generated 1: Interrupt generated Sleep Mode Interrupt Mask 0: Interrupt not generated 1: Interrupt generated Rx Interrupt Mask 0: Interrupt not generated 1: Interrupt generated 625s Base Time Interrupt Mask 0: Interrupt not generated 1: Interrupt generated Audio channel 2 interrupt status 0: No Audio interrupt. 1: An Audio interrupt is pending. Audio channel 1 interrupt status 0: No Audio interrupt. 1: An Audio interrupt is pending. Audio channel 0 interrupt status 0: No Audio interrupt. 1: An Audio interrupt is pending. SW triggered interrupt status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending. End of event / Anticipated Pre-Fetch Abort interrupt status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. Masked Fine Target Timer Error interrupt status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. Masked Gross Target Timer interrupt status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. Masked Error interrupt status 0: No Error interrupt. 1: An Error interrupt is pending. Masked Encryption engine interrupt status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. Masked End of Event interrupt status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. Masked Sleep interrupt status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. Masked Packet Reception interrupt status 0: No Rx interrupt. 1: An Rx interrupt is pending. Masked 625s base time reference interrupt status Audio channel 2 interrupt raw status 0: No Audio interrupt. 1: An Audio interrupt is pending. Audio channel 1 interrupt raw status 0: No Audio interrupt. 1: An Audio interrupt is pending. Audio channel 0 interrupt raw status 0: No Audio interrupt. 1: An Audio interrupt is pending. SW triggered interrupt raw status 0: No SW triggered interrupt. 1: A SW triggered interrupt is pending. End of event / Anticipated Pre-Fetch Abort interrupt raw status 0: No End of Event interrupt. 1: An End of Event interrupt is pending. Fine Target Timer Error interrupt raw status 0: No Fine Target Timer interrupt. 1: A Fine Target Timer interrupt is pending. Gross Target Timer interrupt raw status 0: No Gross Target Timer interrupt. 1: A Gross Target Timer interrupt is pending. Error interrupt raw status 0: No Error interrupt. 1: An Error interrupt is pending. Encryption engine interrupt raw status 0: No Encryption / Decryption interrupt. 1: An Encryption / Decryption interrupt is pending. End of Event interrupt raw status 0: No End of Advertising / Scanning / Connection interrupt. 1: An End of Advertising / Scanning / Connection interrupt is pending. Sleep interrupt raw status 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. Packet Reception interrupt raw status 0: No Rx interrupt. 1: An Rx interrupt is pending. 625s base time reference interrupt raw status 0: No 625s Base Time interrupt. 1: A 625s Base Time interrupt is pending. bit type is changed from wos to s. Audio channel 2 interrupt acknowledgement bit Software writing 1 acknowledges the Audio channel 2 interrupt. This bit resets AUDIOINT2STAT and AUDIOINT2RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Audio channel 1 interrupt acknowledgement bit Software writing 1 acknowledges the Audio channel 1 interrupt. This bit resets AUDIOINT1STAT and AUDIOINT1RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Audio channel 0 interrupt acknowledgement bit Software writing 1 acknowledges the Audio channel 0 interrupt. This bit resets AUDIOINT0STAT and AUDIOINT0RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. SW triggered interrupt acknowledgement bit Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of event / Anticipated Pre-Fetch Abort interrupt acknowledgement bit Software writing 1 acknowledges the End of event / Anticipated Pre-Fetch Abort interrupt. This bit resets EVENTAPFAINTSTAT and EVENTAPFAINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Fine Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTIMINTSTAT and FINETGTIMINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Gross Target Timer interrupt acknowledgement bit Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTIMINTSTAT and GROSSTGTIMINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Error interrupt acknowledgement bit Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Encryption engine interrupt acknowledgement bit Software writing 1 acknowledges the Encryption engine interrupt. This bit resets CRYPTINTSTAT and CRYPTINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of Event interrupt acknowledgment bit Software writing 1 acknowledges the End of Advertising / Scanning / Connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of Deep Sleep interrupt acknowledgment bit Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Packet Reception interrupt acknowledgment bit Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. 625s base time reference interrupt acknowledgment bit Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed Writing a 1 samples the Base Time Counter value in BASETIMECNT register field. Resets at 0 when action is performed Value of the 625s base time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW Value of the current s fine time reference counter. Updated each time SAMP field is written. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration Bluetooth Low Energy Device Address. LSB part. Bluetooth Low Energy Device Address privacy indicator 0: Public Bluetooth Device Address 1: Private Bluetooth Device Address Bluetooth Low Energy Device Address. MSB part. Exchange Table Pointer that determines the starting point of the Exchange Table Rx Descriptor Pointer that determines the starting point of the Receive Buffer Chained List 0: Disable diagnostic port 3 output. All outputs are set to 0x0. 1: Enable diagnostic port 3 output. Only relevant when DIAGEN3 = 1. Selection of the outputs that must be driven to the diagnostic port 3. See section 2.16 for a detailed description. 0: Disable diagnostic port 2 output. All outputs are set to 0x0. 1: Enable diagnostic port 2 output. Only relevant when DIAGEN2 = 1. Selection of the outputs that must be driven to the diagnostic port 2. See section 2.16 for a detailed description. 0: Disable diagnostic port 1 output. All outputs are set to 0x0. 1: Enable diagnostic port 1 output. Only relevant when DIAGEN1 = 1. Selection of the outputs that must be driven to the diagnostic port 1. See section 2.16 for a detailed description. 0: Disable diagnostic port 0 output. All outputs are set to 0x0. 1: Enable diagnostic port 0 output. Only relevant when DIAGEN0 = 1. Selection of the outputs that must be driven to the diagnostic port 0. See section 2.16 for a detailed description. Directly connected to ble_dbg3[7:0] output. Debug use only. Directly connected to ble_dbg2[7:0] output. Debug use only. Directly connected to ble_dbg1[7:0] output. Debug use only. Directly connected to ble_dbg0[7:0] output. Debug use only. Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.16) Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.16) Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.16) Indicates Resolving Address List engine Under run issue, happens when RAL List parsing not finished on time 0: No error 1: Error occurred Indicates Resolving Address List engine faced a bad setting (e.g CS-RAL_EN = 1 and null RALPTR, or RALPTR > CS-PEER_RALPTR). 0: No error 1: Error occurred Indicates whether two consecutive and concurrent ble_event_irq have been generated, and not acknowledged in time by the RW-BLE Software. 0: No error 1: Error occurred Indicates whether Rx data buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred Indicates whether Tx data buffer pointer value programmed is null during Advertising / Scanning / Initiating events, or during Master / Slave connections with non-null packet length: this is a major programming failure. 0: No error 1: Error occurred Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure. 0: No error 1: Error occurred Indicates whether Tx Descriptor pointer value programmed in Control Structure is null during Advertising / Scanning / Initiating events: this is a major programming failure. 0: No error 1: Error occurred Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred Indicates Link Layer Channel Map error, happens when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of Frequency Hopping process 0: No error 1: Error occurred Indicates Advertising Interval Under run, occurs if time between two consecutive Advertising packet (in Advertising mode) is lower than described in Table 3-11. 0: No error 1: Error occurred Indicates Inter Frame Space Under run, occurs if IFS time is not enough to update and read Control Structure/Descriptors, and/or White List parsing is not finished and/or Decryption time is too long to be finished on time 0: No error 1: Error occurred Indicates White List Timeout error, occurs if White List parsing is not finished on time 0: No error 1: Error occurred Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured Indicates Event Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred Indicates Event Scheduler Exchange Memory access error, happens when Exchange Memory accesses are not served in time, and blocks the Exchange Table entry read 0: No error 1: Error occurred Indicates Radio Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and data are corrupted. 0: No error 1: Error occurred Indicates Packet Controller Exchange Memory access error, happens when Exchange Memory accesses are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred Software Profiling register: used by RW-BLE Software for profiling purpose: this value is copied on Diagnostic port (Please refer to section 2.16 for details) Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet. 0: Access Code detection indicator provided as pulse 1: Access Code detection indicator provided as level Enables the use of the delayed DC offset compensated data path in Radio Correlator block. 1: Enable 0: Disable Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value 1: Enable 0: Disable Control Ripple modulation mode in between FM and I&Q 1: I&Q modulation mode 0: FM modulation mode Selects Jitter Elimination FIFO Frequency of the SPI clock 00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz) 01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz) 10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz) 11: Do not use This bit is READ ONLY. 0: Indicates that the SPI transfer is in progress. 1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer. Software writing 1 triggers the SPI access. This bit is always read as 0. Has no effect on Radio Controller Extended radio selection field 5'b00000: No radio selected 5'b00001: RivieraWaves Ripple RF (BT4.0) 5'b00010: External Radio controller support 5'b00011-5'b11111: reserved Pointer to the buffer containing data to be transferred to or received from the SPI port. RF Rx Test Mode Delay Adjustment Used to compensate Modem&RF Tx delay. When used, rtrip_delay should be set as Rx delay Expected bit offset when rx symbol flag found. Used to compensate Modem&RF Rx delay. Defines Rx window time threshold that forces Ripple AGC to max gain BR/EDR Frequency Table pointer Defines round trip delay value. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s This register holds the length in us of the RX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. This register extends the length in us of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on the selected radio. This register holds the length in us of the TX power up phase for the current radio device. Default value is 210us (reset value). Operating range depends on the selected radio. Defines round trip delay value for 2M mode. This value correspond to the addition of data latency in Tx and data latency in Rx. Value is in s Expected bit offset when rx symbol flag found for 2M mode. Used to compensate Modem&RF Rx delay. Advertising Channel Map, defined as per the advertising connection settings. Contains advertising channels index 37 to 39. If ADVCHMAP[i] equals: 0: Do not use data channel i+37. 1: Use data channel i+37. Advertising Packet Interval defines the time interval in between two ADV_xxx packet sent. Value is in s. Value to program depends on the used Advertising Packet type and the device filtering policy. Please refer to Table 3-11 for details about ADVINT programming range. Active scan mode back-off counter initialization value. Active scan mode upper limit counter value. Start address pointer of the public devices white list. Start address pointer of the private devices white list. Number of private devices in the white list. Number of public devices in the white list. 0: Cipher mode 1: Decipher mode Writing a 1 starts AES-128 ciphering/deciphering process. This bit is reset once the process is finished (i.e. ble_crypt_irq interrupt occurs, even masked) AES encryption 128-bit key. Bit 31 down to 0 AES encryption 128-bit key. Bit 63 down to 32 AES encryption 128-bit key. Bit 95 down to 64 AES encryption 128-bit key. Bit 127 down to 96 Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored. AES-CCM plain MIC value. Valid on when MIC has been calculated (in Tx) AES-CCM plain MIC value. Valid on once MIC has been extracted from Rx packet. Applicable to all event type 0: Normal mode of operation 1: Infinite Rx window Applicable in RF Direct Rx Test mode only 0: Rx packet count disabled 1: Rx packet count enabled, and reported in CS-RXCCMPKTCNT and RFTESTRXSTAT-RXPKTCNT on RF abort command Applicable to all event type 0: Normal mode of operation. 1: Infinite Tx packet / Normal start of a packet but endless payload Applicable to all event type 0: Normal mode of operation: TxDESC-<TXADVLEN/TXLEN> controls the Tx packet payload size 1: Uses RFTESTCNTL-TXLENGTH packet length (can support up to 512 bytes transmit) Defines the PRBS in use 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type Applicable to all event type 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator Applicable in RF Direct Tx Test mode only 0: Tx packet count disabled 1: Tx packet count enabled, and reported in CS-TXCCMPKTCNT and RFTESTTXSTAT-TXPKTCNT on RF abort command Applicable to all event type, valid when RFTESTCNTL-TXLENGTHSRC = 1 Tx packet length in number of byte Reports number of transmitted packet during Test Modes. Value is valid if RFTESTCNTL-TXPKTCNTEN is set Reports number of correctly received packet during Test Modes (no sync error, no CRC error). Value is valid if RFTESTCNTL-RXPKTCNTEN is set Controls the Anticipated pre-Fetch Abort mechanism 0: Disabled 1: Enabled Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort Defines Exchange Table pre-fetch instant in s Gross Timer Target value on which a ble_grosstgtim_irq must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET[22:0] = BASETIMECNT[26:4] and BASETIMECNT[3:0] = 0. Fine Timer Target value on which a ble_finetgtim_irq must be generated. This timer has a precision of 625s: interrupt is generated only when FINETARGET = BASETIMECNT Start address pointer of the RAL structure Number of devices in RAL Structure Writing a 1 initializes of Local RPA random number generation LFSR This bit is reset once the LFSR is loaded Initialization value for Local RPA random generation when LRDN_INIT is set to 1, else reports the current Local RPA random number LFSR value Writing a 1 initializes of Peer RPA random number generation LFSR This bit is reset once the LFSR is loaded Initialization value for Peer RPA random generation when PRDN_INIT is set to 1, else reports the current Peer RPA random number LFSR value Determine BLE Priority Scheduling Arbitration Mode 0: BLE Decision instant not used 1: BLE Decision instant used Determine the decision instant margin for Priority Scheduling Arbitration. Decision instant is defined as per formula of section 3.6 Version type of bt_core. 1 for BTDM old version. 2 for BTDM new version. 3 for BLE only. Major release number of bt_core Upgrade number of bt_core Set to 1 when working as a plug-in RF&modem board. Set to 0 in all other modes Set to 1 when using plug-in RF&modem board. Set to 0 in all other modes select tport clock select tport trigger select tport data1 select tport data0 select pll frequency for rf/modem for channel 0~31 1 for 214.5MHz and 0 for 208MHz select pll frequency for rf/modem for channel 32~63 1 for 214.5MHz and 0 for 208MHz select pll frequency for rf/modem for channel 64~78 1 for 214.5MHz and 0 for 208MHz tx calibration enable rx calibration enable force txon for rf to txon_value when txon_force is 1 force rxon for rf to rxon_value when rxon_force is 1 delay time in us to enable modem tx after link layer txon enable delay time in us to disable modem&rf tx after link layer txon disable delay time in us to enable modem rx after link layer rxon enable delay time in us to disable modem&rf rx after link layer rxon disable number of rc clock cycles when doing rc calibration enable automatic rc calibration when BT wakeup bit type is changed from w1s to rs. rc calibration start by software indicate rc caliration done number of reference clock cycles when doing rc calibration. F(rc) = F(ref) * rccal_length / rccal_result BT active indicater: 0: rf_txon 1: rf_rxon 2: rf_txon | rf_rxon 3: modem_txon | modem_rxon 0: BT tx will not be masked 1: BT tx will be masked BT tx will be masked when: 0: mws_tx 1: mws_rx 2: mws_tx | mws_rx 3: mws_tx & mws_rx status of osc_en. 1 means BT is using clock derived from oscillator when set to 1, mask bt2pmu_wakeup output to 0 to avoid unnecessary wakeup Reset the complete RW-BT Core except timing generator and register blocks, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. In case of Dual Mode implementation, reset also common blocks. Reset the timing generator, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Reset the complete register block, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Forces the generation of bt_sw_irq when written with a 1, and proper masking is set. Resets at 0 when action is performed. No action happens if it is written with 0. Abort the current Inquiry / Page / Broadcast scan window when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Abort the current RF Testing when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Note that when RFTEST_ABORT is requested 1/ In case of infinite Tx, the Packet Controller FSM stops at the end of the current byte in process, and processes accordingly the packet CRC. 2/ In case of Infinite Rx, the Packet Controller FSM either stops as the end of the current Packet reception (if Access address has been detected), or simply stop the processing switching off the RF. Abort the current Inquiry Mode or Page Mode when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Abort the current Sniff Mode when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. 0: FLOW verification on Rx packets is activated. 1: Packets are accepted regardless of FLOW value (test mode). 0: When FLOW = 0, LMP messages can be sent. 1: When FLOW = 0, LMP messages are not sent. 0: Normal operation. Encryption enabled when required. 1: Encryption disabled. Note this works for both E0 and AES-CCM encryption mechanism 0: Normal operation. Whitening enabled. 1: Whitening disabled. 0: ARQN verification on Rx packets is activated. 1: Packets are accepted regardless of ARQN value (test mode). 0: Normal operation. CRC removed from incoming data stream. 1: CRC stripping disabled on Rx packets. 0: Normal operation. Hopping enabled. 1: Hopping disabled, the frequency is set either by CS-FREQ or by RFTESTFREQ register fields. 0: SEQN verification on Rx packets is activated. 1: Packets are accepted regardless of SEQN value (test mode). This field updates the CS-TXBSY_EN field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. This field updates the CS-RXBSY_EN field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. This field updates the CS-DNABORT field in the control structure when ends a MASTER_PAGE_RESPONSE or a SLAVE_PAGE_RESPONSE frame. 0: Disable RW-BT Core. 1: Enable RW-BT Core. Indicate the maximum number of errors allowed to recognize the Access Code. RW-BT Core Type C 0x8 means BT v4.2 (i.e. correspond LM version assigned number). Correspond to FS v8.0.11 Version of the RW-BT Core C Major release number. Correspond to FS v8.0.11. Version of the RW-BT Core C Upgrade number. Correspond to FS v8.0.11 RW-BT Core Build number 0: RW-BT Core is used as a standalone BR/EDR device 1: RW-BT Core is used in a Dual Mode device 0: MWS Coexistence 2-Wire Interface not supported 1: MWS Coexistence 2-Wire Interface supported 0: MWS Coexistence 1-Wire Interface not supported 1: MWS Coexistence 1-Wire Interface supported Number of supported Audio Channel (0 to 3) 00: No Audio Channel / No PCM. 01: One Audio Channel 10: Two Audio Channels 11: Three Audio Channels. 0: PCM Not Instantiated 1: PCM Instantiated 0: MWS Coexistence mechanism not present 1: MWS Coexistence mechanism present 0: WLAN Coexistence mechanism not present 1: WLAN Coexistence mechanism present RFIF[k]= 0: Control logic supporting radio k not present RFIF[k]= 1: Control logic supporting radio k present Index k values are: 00001: RW-BT Ripple RF. 00010: External Radio Controller Support xxxx00: Reserved 0: Diagnostics port not present 1: Diagnostics port present 0: AES-CCM Encryption block not present 1: AES-CCM Encryption block present Operating Frequency (in MHz) Default is 13 MHz 0: Interrupts are edge level generated, i.e. pulse. 1: Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement Processor Bus Type 0: AHB Bus 1: X-Bar Bus Processor Data bus width: 0 16 bits 1: 32 bits Value of the RW_BT_ADDRESS_WIDTH parameter converted into binary. Skipped Exchange Table entry Interrupt mask 0: Interrupt not generated 1: Interrupt generated SW triggered Interrupt mask 0: Interrupt not generated 1: Interrupt generated End of Frame Interrupt / Anticipated Pre-Fetch Abort mask 0: Interrupt not generated 1: Interrupt generated End of Frame Interrupt mask 0: Interrupt not generated 1: Interrupt generated MWS Serial Interface Rx Interrupt mask 0: Interrupt not generated 1: Interrupt generated MWS Serial Interface Tx Interrupt mask 0: Interrupt not generated 1: Interrupt generated Error Interrupt mask 0: Interrupt not generated 1: Interrupt generated Gross Target Timer Interrupt mask 0: Interrupt not generated 1: Interrupt generated Fine Target Timer Interrupt mask 0: Interrupt not generated 1: Interrupt generated Momentary Offset 1 event Interrupt mask 0: Interrupt not generated 1: Interrupt generated Momentary Offset 0 event Interrupt mask 0: Interrupt not generated 1: Interrupt generated Frame Synchronization Interrupt mask 0: Interrupt not generated 1: Interrupt generated Audio Channel 2 Interrupt mask 0: Interrupt not generated 1: Interrupt generated Audio Channel 1 Interrupt mask 0: Interrupt not generated 1: Interrupt generated Audio Channel 0 Interrupt mask 0: Interrupt not generated 1: Interrupt generated End of Sleep Interrupt Mask 0: Interrupt not generated 1: Interrupt generated Packet Receipt Interrupt mask 0: Interrupt not generated 1: Interrupt generated CLKN / Slot interrupt mask 0: Interrupt not generated 1: Interrupt generated Skipped Exchange Table entry Interrupt status 0: No Skipped Exchange Table entry Interrupt 1: Skipped Exchange Table entry Interrupt is pending SW Triggered Interrupt status 0: No SW triggered Interrupt 1: SW Triggered Interrupt is pending End of Frame / Anticipated Pre-Fetch Abort Interrupt status 0: No End of Frame Interrupt 1: End of Frame Interrupt is pending End of Frame Interrupt status 0: No End of Frame Interrupt 1: End of Frame Interrupt is pending MWS Serial Interface Rx Interrupt status 0: No MWS WCI Interrupt 1: MWS WCI Interrupt is pending MWS Serial Interface Tx Interrupt status 0: No MWS WCI Interrupt 1: MWS WCI Interrupt is pending Error Interrupt status. 0: No Error interrupt. 1: Error interrupt is pending. Gross Timer Interrupt status. 0: No Gross Timer interrupt. 1: Gross Timer interrupt is pending. Fine Timer Interrupt status. 0: No Fine Timer interrupt. 1: Fine Timer interrupt is pending. Momentary Offset 1 Interrupt status. 0: No Momentary Offset interrupt. 1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step Momentary Offset 0 Interrupt status. 0: No Momentary Offset interrupt. 1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step MWS Frame Synchronization Interrupt status. 0: No frame_sync interrupt. 1: A frame_sync interrupt is pending. Audio Channel 2 Interrupt status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. Audio Channel 1 Interrupt status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. Audio Channel 0 Interrupt status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. end of Sleep Interrupt Status. 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. Packet Reception Interrupt status. 0: No Rx interrupt. 1: An Rx interrupt is pending. Slot Interrupt status. 0: No CLKN interrupt. 1: A CLKN interrupt is pending. Skipped Exchange Table entry Interrupt raw status 0: No Skipped Exchange Table entry Interrupt 1: Skipped Exchange Table entry Interrupt is pending SW Triggered Interrupt raw status 0: No SW Triggered Interrupt 1: SW Triggered Interrupt is pending End of Frame / Anticipated Pre-Fetch Abort Interrupt raw status 0: No End of Frame Interrupt 1: End of Frame Interrupt is pending End of Frame Interrupt raw status 0: No End of Frame Interrupt 1: End of Frame Interrupt is pending MWS Serial Interface Rx Interrupt raw status 0: No MWS WCI Interrupt 1: MWS WCI Interrupt is pending MWS Serial Interface Tx Interrupt raw status 0: No MWS WCI Interrupt 1: MWS WCI Interrupt is pending Error Interrupt raw status. 0: No Error interrupt. 1: Error interrupt is pending. Gross Timer Interrupt raw status. 0: No Gross Timer interrupt. 1: Gross Timer interrupt is pending. Fine Timer Interrupt raw status. 0: No Fine Timer interrupt. 1: Fine Timer interrupt is pending. Momentary Offset 1 Interrupt raw status. 0: No Momentary Offset interrupt. 1: Momentary offset interrupt is pending and the newly calculated momentary offset is lower than the correction step Momentary Offset 0 Interrupt raw status. 0: No Momentary Offset interrupt. 1: Momentary offset interrupt is pending and the newly calculated momentary offset is greater than the correction step MWS Frame Synchronization Interrupt raw status. 0: No frame_sync interrupt. 1: A frame_sync interrupt is pending. Audio Channel 2 Interrupt raw status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. Audio Channel 1 Interrupt raw status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. Audio Channel 0 Interrupt raw status. 0: No eSCO SW Transport interrupt. 1: An eSCO SW Transport interrupt is pending. End of Sleep Interrupt raw Status. 0: No End of Sleep Mode interrupt. 1: An End of Sleep Mode interrupt is pending. Packet Reception Interrupt raw status. 0: No Rx interrupt. 1: An Rx interrupt is pending. Slot Interrupt raw status. 0: No CLKN interrupt. 1: A CLKN interrupt is pending. bit type is changed from wos to s. Skipped Exchange Table entry Interrupt acknowledgment. Software writing 1 acknowledges the Skipped Exchange Table entry interrupt. This bit resets SKETINTSTAT and SKETINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. SW triggered Interrupt acknowledgment. Software writing 1 acknowledges the SW triggered interrupt. This bit resets SWINTSTAT and SWINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of Frame / Anticipated Pre-Fetch Abort Interrupt acknowledgment. Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEAPFAINTSTAT and FRAMEAPFAINTRWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of Frame Interrupt acknowledgment. Software writing 1 acknowledges the End of Frame interrupt. This bit resets FRAMEINTSTAT and FRAMEINTRWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. MWS Serial Interface Rx Interrupt acknowledgment. Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. MWS Serial Interface Tx Interrupt acknowledgment. Software writing 1 acknowledges the MWS Serial Interface interrupt. This bit resets MWSWCIINTSTAT and MWSWCIINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Error Interrupt acknowledgment. Software writing 1 acknowledges the Error interrupt. This bit resets ERRORINTSTAT and ERRORINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Gross Timer Interrupt acknowledgment. Software writing 1 acknowledges the Gross Timer interrupt. This bit resets GROSSTGTINTSTAT and GROSSTGTINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Fine Timer Interrupt acknowledgment. Software writing 1 acknowledges the Fine Timer interrupt. This bit resets FINETGTINTSTAT and FINETGTINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Momentary Offset 1 Interrupt acknowledgment. Software writing 1 acknowledges the Momentary offset event interrupt. This bit resets MTOFFINT1STAT and MTOFFINT1RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Momentary Offset 0 Interrupt acknowledgment. Software writing 1 acknowledges the Momentary offset event interrupt. This bit resets MTOFFINT0STAT and MTOFFINT0RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. MWS Frame Synchronization Interrupt acknowledgement. Software writing 1 acknowledges the frame_sync event interrupt. This bit resets FRSYNCINTSTAT and FRSYNCINTRAWSTAT flag. Resets at 0 when action is performed bit type is changed from wos to s. Audio Channel 2 Interrupt acknowledgement. Software writing 1 acknowledges the Audio Channel 2 interrupt. This bit resets AUDIOINT2STAT and AUDIOINT2RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Audio Channel 1 Interrupt acknowledgement. Software writing 1 acknowledges the Audio Channel 1 interrupt. This bit resets AUDIOINT1STAT and AUDIOINT1RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Audio Channel 0 Interrupt acknowledgement. Software writing 1 acknowledges the Audio Channel 0 interrupt. This bit resets AUDIOINT0STAT and AUDIOINT0RAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. End of Sleep Interrupt acknowledgement. Software writing 1 acknowledges the End of Sleep Mode interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Packet Reception Interrupt acknowledgement. Software writing 1 acknowledges the Rx interrupt. This bit resets RXINTSTAT and RXINTRAWSTAT flags. Resets at 0 when action is performed bit type is changed from wos to s. Slot Interrupt acknowledgement. Software writing 1 acknowledges the CLKN interrupt. This bit resets CLKINTSTAT and CLKINTRAWSTAT flags. Resets at 0 when action is performed Writing a 1 samples the CLKN[27:0] value in SLOTCLK-SCLK register field. Resets at 0 when action is performed. No action happens if it is written with 0 Update the Native Bluetooth counter CLKN[27:1] (CLKN[0] is not considered), when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Native Bluetooth counter CLKN sampled at the time the processor has written the SAMP bit (precsision of 312.5s). This value does not change until the next writing of SAMP bit, and can therefore be safely accessed with 8-, 16- or 32-bits accesses. Value of the current s fine time reference counter sampled at the time the processor has written the SAMP bit. Used by the SW in order to synchronize with the HW, and obtain a more precise sleep duration Enable automatic A-train/B-train switch during Page procedure. 0: Page procedure A-train/B-train counter disabled 1: Page procedure A-train/B-train counter enabled Starting train value of Page procedure 0:Start with A-train 1:Start with B-train Load A-train/B-train Page procedure conter, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Defines A-train/B-train duration time during Page procedure, counted by 16-slots. Loaded when ABTPAGELOAD is set. Start when Page procedure starts and ABTPAGEEN is set. Stops when ABTPAGEEN is reset. Switch of train when wrapping. Enable automatic A-train/B-train switch during Inquiry procedure. 0: Inquiry procedure A-train/B-train counter disabled 1: Inquiry procedure A-train/B-train counter enabled Starting train value of Inquiry procedure 0:Start with A-train 1:Start with B-train Load A-train/B-train Inquiry procedure conter, when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Defines A-train/B-train duration time during Inquiry procedure, counted by 16-slots. Loaded when ABTINQLOAD is set. Start when Inquiry procedure starts and ABTINQEN is set. Stops when ABTINQEN is reset. Switch of train when wrapping. Default value equals d26. Should not exceed 'h88. Applies when ET-SNIFF = 1 on first access code detection, in order to process the new bit offset (See section 3.5.5) 0: Broadcast @ 1Mbps / normal mode 1: Broadcast operation in EDR Mode (@ 2/3 Mbps) / special features The EDRCNTL-EDRBCAST bit is used in reception (slave side) as following: if RXLTADDR= 0 (i.e. broadcast packet is received) if EDRCNTL-EDRBCAST=0 , we consider the currently received packet is not an EDR-packet. The 1Mbps modulation is used. if EDRCNTL-EDRBCAST=1, then apply EDR modulation or not depending on the control structure bit " ACLEDR" set in MISCNTL field. 0: normal operation, EDR Rx guard window detection activated 1: EDR Rx guard window detection disabled. 0: Direct order EDR Payload data transmit 1: Reverse order EDR Payload data transmit 0: Direct order EDR Payload data receive 1: Reverse order EDR Payload data receive Time out value before EDR packet reception that allow ending the Rx transaction if an EDR packet is not correctly detected. Default value is set to 212 clock cycles @ 13MHz <-> 16.3us. Timing between Packet Header and EDR packet is defined as 5us+-0.25us + 11 synchronization symbol = 16.25us in the worst case Exchange Table pointer value Rx Descriptor current pointer value External Wake-Up disable 0: RW-BT Core can be woken by external wake-up 1: RW-BT Core cannot be woken up by external wake-up Enable external pin high level wakeup Enable external pin low level wakeup Enable external pin activity wakeup Indicator of current Deep Sleep clock mux status: 0: RW-BT Core is not yet in Deep Sleep Mode 1: RW-BT Core is in Deep Sleep Mode (only low_power_clk is running) Wake Up Request from RW-BT Software. Applies when system is in Deep Sleep Mode. It wakes up the RW-BT Core when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. CLKN integer and fractional part correction (i.e. CLKN Counter and Fine Counter). Applies when system has been woken-up from Deep Sleep Mode. It enables Fine Counter and Base Time counter when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. RW-BT Core sleep mode request control 0: RW-BT Core in normal active mode 1: Request RW-BT Core to switch in deep sleep mode. This bit is reset on DEEP_SLEEP_STAT falling edge. Controls the Radio module 0: Radio stands in normal active mode 1: Allow to disable Radio Controls the RF High frequency crystal oscillator 0: High frequency crystal oscillator stands in normal active mode 1: Allow to disable High frequency crystal oscillator Determines the time in low_power_clk clock cycles to spend in Deep Sleep Mode before waking-up the device. This ensures a maximum of 37 hours and 16mn sleep mode capabilities at 32kHz. This ensures a maximum of 36 hours and 16mn sleep mode capabilities at 32.768kHz Actual duration of the last deep sleep phase measured in low power oscillator cycles. DEEPSLDUR is set to zero at the beginning of the deep sleep phase, and is incremented at each low power clock tick until the end of the deep sleep phase. Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator following an external wake-up request (signal wakeup_req) [064ms for 32kHz) Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator when the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP) [064ms for 32kHz) Time in low power oscillator cycles allowed for the radio module to leave low-power mode [032ms for 32kHz) Phase correction value for the CLKN counter in s. Determines whether CLNCNTCORR is an absolute correction or a signed delta increment correction 0: Absolute correction 1: Signed delta increment correction CLKN Counter correction value / signed delta increment Token Tx delay time after Slave receive completed Token Rx delay time after Slave receive completed 0: Use normal sync pulse for token ID 1: Use quick sync pulse for token ID Size of Token Rx Window Slave arbiter receive token ID but bypass arbitration Slave arbiter enable Slave observer will respond to master Slave observer enable 0: Disable diagnostic port 3 output. All outputs are set to 0. 1: Enable diagnostic port 3 output. Only relevant when DIAGEN3 = 1. Selection of the outputs that are driven to the diagnostic port 3. 0: Disable diagnostic port 2 output. All outputs are set to 0. 1: Enable diagnostic port 2 output. Only relevant when DIAGEN2 = 1. Selection of the outputs that are driven to the diagnostic port 2. 0: Disable diagnostic port 1 output. All outputs are set to 0. 1: Enable diagnostic port 1 output. Only relevant when DIAGEN1 = 1. Selection of the outputs that are driven to the diagnostic port 1. 0: Disable diagnostic port 0 output. All outputs are set to 0. 1: Enable diagnostic port 0 output. Only relevant when DIAGEN0 = 1. Selection of the outputs that are driven to the diagnostic port 0. Directly connected to bt_dbg0[7:0] output. Debug use only Directly connected to bt_dbg1[7:0] output. Debug use only Directly connected to bt_dbg2[7:0] output. Debug use only Directly connected to bt_dbg3[7:0] output. Debug use only Upper limit for the Register zone indicated by the reg_inzone flag (see section 2.19). Upper limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19). Lower limit for the Register zone indicated by the reg_inzone flag (see section 2.19) Lower limit for the Exchange Memory zone indicated by the em_inzone flag (see section 2.19) Indicates whether the Rx eSCO (during Voice over HCI operations) or Rx LM buffer pointer value programmed is null: this is a major programming failure. 0: No error 1: Error occurred Indicates whether Tx eSCO (during Voice over HCI operations) or Tx LM buffer pointer value programmed is null, or if an ACL Tx packet is set with a non null length while no buffer is associated: this is a major programming failure. 0: No error 1: Error occurred Indicates whether Rx Descriptor pointer value programmed in register is null: this is a major programming failure / Valid for non-connected states and Broadcast Scan mode 0: No error 1: Error occurred Indicates whether Tx Descriptor pointer value programmed in Control Structure is null: this is a major programming failure / Valid for non-connected states and Broadcast mode 0: No error 1: Error occurred Indicates whether ATT_NB field in Control Structure is null, or when during eSCO that eSCOLTCNLT<0/1/2>-RETXNB<0/1/2> register field is null: this is a major programming failure 0: No error 1: Error occurred Indicates whether CS-FORMAT has been programmed with an invalid value: this is a major software programming failure. 0: No error 1: Error occurred Channel Map error, happens when actual number of bits set to one in selected CS-CHMAP is different from corresponding CS-NBCHGOOD at the beginning of Frequency Hopping process. Note this is valid only if CS-AFHENA=1 0: No error 1: Error occurred Calculation of the hopping frequency not done before Tx/Rx EN is asserted 0: No error 1: Error occurred Indicates an Frame Controller internal timing error 0: No error 1: Error occurred Indicate a Frame Controller Exchange Memory Access error. 0: No error 1: Error occurred Indicates Anticipated Pre-Fetch Mechanism error in Frame Controller: happens when 2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured Indicates Anticipated Pre-Fetch Mechanism error in Frame Scheduler: happens when 2 consecutive frames are programmed, and when the first frame is not completely finished while second pre-fetch instant is reached. 0: No error 1: Error occured Indicates Frame Scheduler faced Invalid timing programing on two consecutive ET entries (e.g first one with 624s offset and second one with no offset) 0: No error 1: Error occurred MWS WCI Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted 0: No error 1: Error occurred Frame Scheduler Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted 0: No error 1: Error occurred PCM Exchange Memory request access error, happens when Exchange Memory access requests are not served in time and PCM samples are corrupted 0: No error 1: Error occurred Audio EM Access Manager Exchange Memory access error, happens when Exchange Memory access are not served in time and Audio samples are corrupted 0: No error 1: Error occurred Radio Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and data are corrupted. 0: No error 1: Error occurred Packet Controller Exchange Memory access error, happens when Exchange Memory access are not served in time and Tx/Rx data are corrupted 0: No error 1: Error occurred Indicates when the Encryption mode is enabled with Connectionless Slave Broadcast (Master or Slave) 0: No error 1: Error occurred Indicates real time decryption error, happens when AES-CCM decryption is too slow compared to Packet Controller requests. A 16-bytes block has to be decrypted prior the next block is received by the Packet Controller 0: No error 1: Error occurred Indicates Real Time encryption error, happens when AES-CCM encryption is too slow compared to Packet Controller requests. A 16-bytes block has to be encrypted and prepared on Packet Controller request, and needs to be ready before the Packet Controller has to send ti 0: No error 1: Error occurred Software Profiling register: used by RW-BT Software for profiling purpose: this value is copied on Diagnostic port Determines whether SYNC_P output will be dragged as pulse or level maintained till end of the Packet. 0: Access Code detection indicator provided as pulse 1: Access Code detection indicator provided as level Enables the use of the delayed DC offset compensated data path in Radio Correlator block. 1: Enable 0: Disable Control Ripple AGC force mode based on RADIOCNTL2-FORCEAGC_LENGTH value 1: Enable 0: Disable Frequency of the SPI clock 00: SPI clock frequency is baseband master clock frequency divided by 2 (i.e 6.5MHz @ 13MHz) 01: SPI clock frequency is baseband master clock frequency divided by 4 (i.e 3.25MHz @ 13MHz) 10: SPI clock frequency is baseband master clock frequency divided by 8 (i.e 1.67MHz @ 13MHz) 11: Do not use This bit is READ ONLY. 0: Indicates that the SPI transfer is in progress. 1: Indicates that the SPI transfer is complete. The RW-BT Dual Mode is ready to start another transfer. Software writing 1 triggers the SPI access. This bit is always read as 0. Extended radio selection field 5'h00000: No radio selected 5'h00001: RivieraWaves Ripple RF (BT4.0) 5'h00010: External Radio controller support 5'h00011-5'b11111: reserved Pointer to the buffer containing data to be transferred to or received from the SPI port. Used to compensate Modem&RF Tx delay. When used, rtrip_delay should be set as Rx delay Defines sync_p instant when provided to the Modem. Defines Rx window time threshold that forces Ripple AGC to max gain BR/EDR Frequency Table pointer Round Trip Delay. This correspond to the cumulated Tx plus Rx latency of the radio (in us) This register holds the length in us of the RX power up phase for the current radio device. Default value is 210 us (reset value). Operating range depends on supported radio. This register extends the length in us of the TX power down phase for the current radio device. Default value is 3us (reset value). Operating range depends on supported radio. This register holds the length in us of the TX power up phase for the current radio device. Default value is 210 us (reset value). Operating range is depends on supported radio. AES-CCM plain MIC value. AES-CCM plain MIC value. E0 Address pointer Applicable in Slave eSCO reserved slot only 0: Normal mode of operation 1: Allow reply on Sync Error Applicable in Slave eSCO reserved slot only 0: Normal mode of operation 1: Allow reply on HEC Error Applicable for all frame format 0: Normal mode of operation 1: Infinite Rx window Set to 1 to force status of exchange table entry to be ready. Used for repeated tx Applicable for all frame format 0: Normal mode of operation 1: Infinite Tx window Defines the PRBS type in use 0: Tx Packet Payload are PRBS9 type 1: Tx Packet Payload are PRBS15 type Applicable for all frame format 0: Tx Packet Payload source is the Control Structure 1: Tx Packet Payload are PRBS generator Direct Loopback Test Mode enable control 0: Normal mode of operation 1: Direct Loopback Mode enabled (Received Packet Header, Payload Header, and Payload data directly re-transmitted in the next slot) Test Mode enable control, applicable if CS-FH_EN=0 0: Normal mode of operation 1: Test Mode enable, use <TX/RX>FREQ during Tx/Rx operations. Frequency Table index to be used during Rx operation Frequency Table index to be used during Tx operation Controls the Anticipated pre-Fetch Abort mechanism 0: Disabled 1: Enabled Defines the instant in s at which immediate abort is required after anticipated pre-fetch abort Defines Exchange Table pre-fetch instant in s Gross Timer Target value on which an Interrupt must be generated. This timer has a precision of 10ms: interrupt is generated only when GROSSTARGET = CLKN[27:5] and CLKN[4:0] = 0. Fine Timer Target value on which an interrupt must be generated. This timer has a precision of 625s: interrupt is generated only when FINETARGET = CLKN[27:1] Returns the CLKN[27:0] value on each bt_sket_irq generation. Signed number, time offset to the current frame_sync position in s. Valid range is [-625, 625]s. When SYNC_SOURCE=1, the following formula must apply: TARGET_OFFSET = 559 C RF round trip delay C desired CS-BITOFF Applies only when SYNC_SOURCE equals 1. Defines which connection to align piconet clock on. The connection is labelled using CS-LINKLBL the piconet clock is aligned when CS-LINKLBL = SLVLBL field Note the RW-BT Software must ensure the labelled connection is a slave connection, else it cannot work properly Maximum shift size during incremental phase shift. Must be programmed to 1s (0x1) Note CORR_STEP is considered as a signed value when BLINDCORR_EN is set (allows to drift forward and backward) 0: Align piconet clock on frame_sync rising edge (when CORR_INTERVAL is reached) 1: Align piconet clock when CORR_INTERVAL is reached, without frame_sync rising edge Frame sync signal polarity. 0 : rising edge events sensitive 1 : falling edge events sensitive Defines synchronization signal source 0: MWS frame synchronization 1: Scatternet network scheduling optimization (See section 2.17) Enable incremental phase shift Correction interval time in slot interval. Default value is 40 (i.e. 40x625s = 25ms) Performs immediate clock shift update using CLOCK_SHIFT[10:0], when written with a 1. Resets at 0 when action is performed. No action happens if it is written with 0. Signed value of the clock shift to apply when CLOCK_SHIFT_EN is written with a 1 in [-625, 625]s range Indicate the value of the phase when an immediate shift has been programmed or when a frame_sync event occurs, [-625, 625]s Momentary offset, signed number which indicate the time between target_offset and the nearest alignment point, in [-625, 625]s range Toggle command for Voice Channel 0. Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor Please refer to section 2.18.5 for details. Enables eSCO Channel 0 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: 0: Disabled. 1: Enabled. Enables eSCO Channel 0 (controls Audio Path EM Access controller voice channel 0): 0: Disabled. 1: Enabled. 0: bt_audio0_irq is generated on TeSCO/TSCO instant 1: bt_audio0_irq is generated INTDELAY0[5:0] slots after TeSCO/TSCO instant Valid if ITMODE0 = 1 Determines the slot number to wait before generating bt_audio0_irq eSCO interval (in slots). Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) HW mute control: 0: Do not mute on bad reception of an (e)SCO packet. 1: Mute after data or bad reception, with the pattern stored in MUTEPATT0 Note: See Table 2-34 for mute pattern value to apply HW mute control: 0: Provides Source buffer to the Packet Controller for Tx operations 1: Forces POLL/NULL to be sent as a replacement of Audio Packets SW mute status for Audio buffer 1 (i.e updated when TOG0=1): Mute if not null. Please refer to Table 2-35 for details SW mute status for Audio buffer 0 (i.e updated when TOG0=0): Mute if not null. Please refer to Table 2-35 for details Value of the null pattern used when HW muting is enabled. Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. Used when eSCOCHANCNTL0-TOG0 = 1 Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 0. Used when eSCOCHANCNTL0-TOG0 = 0 Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 0. Used when eSCOCHANCNTL0-TOG0 = 1 Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 0. Used when eSCOCHANCNTL0-TOG0 = 0 Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). Default value is 1 1: eSCO EDR Mode (2/3 Mbps) in reception 0: eSCO 1Mbps in reception 1: eSCO EDR Mode (2/3 Mbps) in transmission 0: eSCO 1Mbps in transmission Synchronous packet type: 0: SCO packet 1: eSCO packet LT_ADDR of the Synchronous link (eSCO), used for TX. Value of the SEQN bit in eSCO TX packets. Used as follows: - Initialized by SW during eSCO link establishment - Toggled by HW on each TSCO/TeSCO, written back afterwards Negotiated, maximum number of bytes for eSCO Tx payloads. Negotiated Tx packet type, as defined in [1]. Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. Negotiated Rx packet type, as defined in [1]. Day Counter for AES-CCM nonce. Toggle command for Voice Channel 1. Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor. Please refer to section 2.18.5 for details. Enables eSCO Channel 1 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: 0: Disabled. 1: Enabled. Enables eSCO Channel 1 (controls Audio Path EM Access controller voice channel 1): 0: Disabled. 1: Enabled. 0: bt_audio1_irq is generated on TeSCO/TSCO instant 1: bt_audio1_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant Valid if ITMODE1 = 1 Determines the slot number to wait before generating bt_audio1_irq eSCO interval (in slots). Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) HW mute control: 0: Do not mute on bad reception of an (e)SCO packet. 1: Mute after data or bad reception, with the pattern stored in MUTEPATT1 Note: See Table 2-34 for mute pattern value to apply HW mute control: 0: Provides Source buffer to the Packet Controller for Tx operations 1: Forces POLL/NULL to be sent as a replacement of Audio Packets SW mute status for Audio buffer 1 (i.e updated when TOG1=1): Mute if not null. Please refer to Table 2-35 for details SW mute status for Audio buffer 0 (i.e updated when TOG1=0): Mute if not null. Please refer to Table 2-35 for details Value of the null pattern used when HW muting is enabled. Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. Used when eSCOCHANCNTL1-TOG1 = 1 Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. Used when eSCOCHANCNTL1-TOG1 = 0 Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 1. Used when eSCOCHANCNTL1-TOG1 = 1 Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 1. Used when eSCOCHANCNTL1-TOG1 = 0 Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). Default value is 1 1: eSCO EDR Mode (2/3 Mbps) in reception 0: eSCO 1Mbps in reception 1: eSCO EDR Mode (2/3 Mbps) in transmission 0: eSCO 1Mbps in transmission Synchronous packet type: 0: SCO packet 1: eSCO packet LT_ADDR of the Synchronous link (eSCO), used for TX. Value of the SEQN bit in eSCO TX packets. Used as follows: - Initialized by SW during eSCO link establishment - Toggled by HW each TSCO/TeSCO, written back afterwards Negotiated, maximum number of bytes for eSCO Tx payloads. Negotiated Tx packet type, as defined in [1]. Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. Negotiated Rx packet type, as defined in [1]. Day Counter for AES-CCM nonce. Toggle command for Voice Channel 2. Driven by TeSCO/TSCO toggling instant. Used to perform selection of PCM pointers and Tx/Rx Descriptor Please refer to section 2.18.5 for details. Enables eSCO Channel 2 SW Transport (Enable Audio data to be routed directly to EM (or through AES-CCM if encrypted link), used by Voice Transparent Modes: 0: Disabled. 1: Enabled. Enables eSCO Channel 2 (controls Audio Path EM Access controller voice channel 2): 0: Disabled. 1: Enabled. 0: bt_audio2_irq is generated on TeSCO/TSCO instant 1: bt_audio2_irq is generated INTDELAY1[5:0] slots after TeSCO/TSCO instant Valid if ITMODE2 = 1 Determines the slot number to wait before generating bt_audio2_irq eSCO interval (in slots). Support a [2:16] range in slots so as to support both SCO and eSCO mandatory LMP parameters range (see [1]) HW mute control: 0: Do not mute on bad reception of an (e)SCO packet. 1: Mute after data or bad reception, with the pattern stored in MUTEPATT2 Note: See Table 2-34 for mute pattern value to apply HW mute control: 0: Provides Source buffer to the Packet Controller for Tx operations 1: Forces POLL/NULL to be sent as a replacement of Audio Packets SW mute status for Audio buffer 1 (i.e updated when TOG2=1): Mute if not null. Please refer to Table 2-35 for details SW mute status for Audio buffer 0 (i.e updated when TOG2=0): Mute if not null. Please refer to Table 2-35 for details Value of the null pattern used when HW muting is enabled. Tx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. Used when eSCOCHANCNTL2-TOG2 = 1 Tx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. Used when eSCOCHANCNTL2-TOG2 = 0 Rx (e)SCO Sample Buffer pointer 1 of Voice Channel 2. Used when eSCOCHANCNTL2-TOG2 = 1 Rx (e)SCO Sample Buffer pointer 0 of Voice Channel 2. Used when eSCOCHANCNTL2-TOG2 = 0 Defines the number of transmsission attemtps for SCO/eSCO operations (includes reserved slots and re-Tx slots). Default value is 1 1: eSCO EDR Mode (2/3 Mbps) in reception 0: eSCO 1Mbps in reception 1: eSCO EDR Mode (2/3 Mbps) in transmission 0: eSCO 1Mbps in transmission Synchronous packet type: 0: SCO packet 1: eSCO packet LT_ADDR of the Synchronous link (eSCO), used for TX. Value of the SEQN bit in eSCO TX packets. Used as follows: - Initialized by SW during eSCO link establishment - Toggled by HW each TSCO/TeSCO, written back afterwards Negotiated, maximum number of bytes for eSCO Tx payloads. Negotiated Tx packet type, as defined in [1]. Negotiated, maximum number of bytes for eSCO Rx payloads. The reception of the payload is automatically aborted if this buffer size is exceeded. Negotiated Rx packet type, as defined in [1]. Day Counter for AES-CCM nonce. Sample Linear format for voice channel 0 00: 8-bit samples 01: 13-bit samples 10: 14-bit samples 11: 16-bit samples PCM / VoHCI Sample Type on Audio Path Channel 0 00: Signed 1s complement 01: Signed 2s complement 10: Signed magnitude 11: Unsigned a/-Law control for voice channel 0 1: Enables a/-Law transcoding 0: Disables a/-Law transcoding / bypass mode a/-Law configuration code for voice channel 0. (See Table 2-40) CVSD control for voice channel 0 1: Enables CVSD transcoding 0: Disables CVSD transcoding / bypass mode Bit ordering at Byte interface for voice channel 0 0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. 1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). Sample Linear format for voice channel 1 00: 8-bit samples 01: 13-bit samples 10: 14-bit samples 11: 16-bit samples PCM / VoHCI Sample Type on Audio Path Channel 1 00: Signed 1s complement 01: Signed 2s complement 10: Signed magnitude 11: Unsigned a/-Law control for voice channel 1 1: Enables a/-Law transcoding 0: Disables a/-Law transcoding / bypass mode a/-Law configuration code for voice channel 1. (See Table 2-40) CVSD control for voice channel 1 1: Enables CVSD transcoding 0: Disables CVSD transcoding / bypass mode Bit ordering at Byte interface for voice channel 1 0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. 1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). Sample Linear format for voice channel 2 00: 8-bit samples 01: 13-bit samples 10: 14-bit samples 11: 16-bit samples PCM / VoHCI Sample Format on Audio Path Channel 2 00: Signed 1s complement 01: Signed 2s complement 10: Signed magnitude 11: Unsigned a/-Law control for voice channel 2 1: Enables a/-Law transcoding 0: Disables a/-Law transcoding / bypass mode a/-Law configuration code for voice channel 2. (See Table 2-40) CVSD control for voice channel 2 1: Enables CVSD transcoding 0: Disables CVSD transcoding / bypass mode Bit ordering at Byte interface for voice channel 2 0: LSB fist. Compatible to BT spec. 1.1 (ref. to [1]) Over the air, the bits are sent in the same order they are generated by the CVSD encoder. 1: MSB First. Compatible to BT spec. 1.0B (ref. to [1]) The bits are sent in the reverse order (maintains backward compatibility). Voice channel Selection. Select the voice channel to be routed to the PCM 00: Voice Channel 0 routed to PCM 01: Voice Channel 1 routed to PCM 10: Voice Channel 2 routed to PCM 11: Reserved Loopback Test mode control 1: Loopback Mode enabled 0: Loopback Mode disabled / Normal operations Valid when SAMPTYPE is set to Stereo mode, else not applicable 0: Select Left channel audio samples for Mono operation 1: Select Right channel audio samples for Mono operation Audio channel Mono/Stereo mode control 0: Audio channel carries Mono samples 1: Audio channel carries Stereo samples Master/Slave mode control 0: PCM is master (i.e. PCM generates pcmclk_out and pcmfsync_out from PLL) 1: PCM is slave (i.e. PLL disabled and pcmclk_in and pcmfsync_in are used) Byte swapping control, valid only SAMPSZ is set to 16-bits 0: Samples to be sent used as-is 1: MSB and LSB bytes are swapped within samples Valid in Stereo mode only, defines the Left / Right channel order 0: Left channel then Right channel 1: Right channel then Left channel PCM main control 0: PCM disabled (i.e. pcm_gclk clock not enabled) 1: PCM enabled (i.e. pcm_gclk clock enabled) Configures the first active slot of the frame, in [0:3] range 00: first active slot is slot 0 01: first active slot is slot 1 10: first active slot is slot 2 11: first active slot is slot 3 The maximum value this field can be configured to is determined by the SLOTNB-1 parameters. Number of slots within a PCM frame Valid values are in [1:4] range. Other values are meaningless PCM Codec Sample type 0: PCM codec supports Mono operation 1: PCM codec supports Stereo operation PCM codec Sample size 0: PCM Frame carries 8-bit samples 1: PCM Frame carries 16-bit samples Bit ordering within a PCM Frame 0: Sample are sent/received MSB first 1: Samples are sent/received LSB first PCM / IOM mode selection 0: PCM mode (single clocking) 1: IOM mode (double clocking) Selection of the PCM Frame Synchronization polarity (Valid when SAMPTYPE is set to Stereo mode, else not applicable) 0: Right channel when = 0, Left channel when = 1 1: Right channel when = 1, Left channel when = 0 Physical configuration of the pcmd_out pad. 00: Open-drain, hi-Z outside transmission 01: Push-pull, hi-Z outside transmission 10: Push-pull, driven to 0 outside transmission 11: Reserved Physical shape of the PCM Frame Synchronization signal. 000: LF enclosing the last falling PCM Interface Clock edge in frame (Mono only) 001: FR enclosing the first rising PCM Interface Clock edge in frame (Mono only) 010: FF enclosing the first falling PCM Interface Clock edge in frame (Mono only) 011: LONG enclosing the first slot (8 bits) of the frame (Mono / Stereo 8-bits only) 100: LONG_16 enclosing first two slots (16 bits) of the frame (Mono 16 bits / Stereo 16-bits only) 101: STEREO Left/Right Frame differentiating (Stereo only, covers left or right channel only, polarity is set according to LRCHPOL) Selection of the PCM Interface Clock polarity 0: Data is clocked out with the rising edge (standard) 1: Data is clocked out with the falling edge PCM Clock counter limit PCM Clock Counter value. Right channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first) Left channel sample padding / to be used when non 16-bits PCM sample configuration is used. (LSB are used first) PLL control word, see equation below. Open Loop Correction value, see equation below. PLL control word, see equation below. PLL control word, see equation below. PCM Source Pointer 1 / Air to PCM direction PCM Source Pointer 0 / Air to PCM direction PCM Sink Pointer 1 / PCM to Air direction PCM Sink Pointer 0 / PCM to Air direction Determine BR/EDR Priority Scheduling Arbitration Mode 0: BR/EDR Decision instant not used 1: BR/EDR Decision instant used Determine the decision instant margin for Priority Scheduling Arbitration. Decision instant is defined as per formula of section 3.6 PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool Base Addr PLC Pool buf Addr bit type is changed from wos to s. plc interrput clear pulse plc interrput plc ctrl fsm state bit type is changed from wos to s. plc_start 0: hardware auto 1: software ctrl mask for plc interrupt diag0 selection plc scaling mode frame_mode length_x000D_ 0: 120_x000D_ 1: 90 2:60_x000D_ 3:30 indicate current farme bad or good enable for PLC plc exception swap word order threshold for finding pitch Bypass DC Cancel 1'h0:: not_bypass: RX DC Cancel is not bypassed 1'h1:: bypass: RX DC Cancel is bypassed RESERVED Bypass Mixer 1'h0:: not_bypass: RX Mixer is not bypassed 1'h1:: bypass: RX Mixer is bypassed Bypass Square-root-raised-cosine Filter 1'h0:: not_bypass: RX SRRC filter is not bypassed 1'h1:: bypass: RX SRRC filter is bypassed Bypass GFSK Derr1 1'h0:: not_bypass: RX GFSK Derr1 is not bypassed 1'h1:: bypass: RX GFSK Derr1 is bypassed Bypass GFSK Derr2 1'h0:: not_bypass: RX GFSK Derr2 is not bypassed 1'h1:: bypass: RX GFSK Derr2 is bypassed Bypass GFSK Patch 1'h0:: not_bypass: GFSK Patch is not bypassed 1'h1:: bypass: GFSK Patch is bypassed Bypass GFSK Sample Step 1'h0:: not_bypass: RX GFSK Sample Step is 1 1'h1:: bypass: RX GFSK Sample Step is 0 Bypass DPSK Derr1 1'h0:: not_bypass: RX DPSK Derr1 is not bypassed 1'h1:: bypass: RX DPSK Derr1 is bypassed Bypass DPSK Derr2 1'h0:: not_bypass: RX DPSK Derr2 is not bypassed 1'h1:: bypass: RX DPSK Derr2 is bypassed Bypass DPSK Patch 1'h0:: not_bypass: DPSK Patch is not bypassed 1'h1:: bypass: DPSK Patch is bypassed Bypass DPSK Sample Step 1'h0:: not_bypass: RX DPSK Sample Step is 1 1'h1:: bypass: RX DPSK Sample Step is 0 Switch ADC Clock Edge 1'h0:: not_switch: ADC clock edge is not switched 1'h1:: switch: ADC clock edge is switched Select New Packet 1'h0:: from_LL: newpacket_dsp is from baseband 1'h1:: from_reg: newpacket_dsp is from newpacket_reg Switch DAC Clock Edge 1'h0:: not_switch: DAC clock edge is not switched 1'h1:: switch: DAC clock edge is switched RESERVED LPF Data Width Select 2'h0:: shift_9bits 2'h1:: shift_8bits 2'h2:: shift_7bits 2'h3:: shift_6bits Switch TX DAC datai sign 1'h0:: unsigned: TX DAC datai is unsigned; analog common format 1'h1:: signed: TX DAC datai is signed Switch TX DAC dataq sign 1'h0:: unsigned: TX DAC dataq is unsigned; analog common format 1'h1:: signed: TX DAC dataq is signed Switch RX ADC IQ data sign 1'h0:: unsigned: RX ADC data is unsigned; analog common format 1'h1:: signed: RX ADC data is signed SRRC IQ_SEL Polarity 1'h0:: iq_sel_inv 1'h1:: iq_sel_raw Sum Error Range Control 3'h0 Left shift 3 bits of sum err and limit sumerr within [-2^-4, 2^-4] 3'h1 Left shift 2 bits of sum err and limit sumerr within [-2^-3, 2^-3] 3'h2 Left shift 1 bits of sum err and limit sumerr within [-2^-2, 2^-2] 3'h3 Hold the sum err 3'h4 Right shift 1 bits of sum err 3'h5 Right shift 2 bits of sum err 3'h6 Right shift 3 bits of sum err 3'h7 Right shift 4 bits of sum err; Set the AFC frequency of dem750 of rx link dec2hex(2^16-round(2*740/13e3*2^16)) DPSK TX Gain in EDR Set the delay of input gfsk symbol, delay unit is 13MHz clock cycle. Set the delay of input dpsk symbol, delay unit is 13MHz clock cycle. Control the guard time length of bt frame Guard time = (55-cnt_guard_ini)*T13Mclk LL tx_power and debug tx_apc selection. 1'h1:: selected LL tx_power 1'h0::selected debug tx_apc according to tx_power mapping digital gain. 1'h1:: bypass auto gain mapping function 1'h0:: no bypass GFSK TX Gain in BR after SRRC RSSI Output after mixer before SRRC RSSI Output. after SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal befor SRRC RSSI Receiver Strength Signal Indicator lock by agc done signal Swap I/Q 1'h0:: no_swap: I/Q is not swaped 1'h1:: swap: I/Q is swaped Swap I/Q of ddcl input data 1'h0:: no_swap: I/Q of ddcl input data is not swaped 1'h1:: swap: I/Q of ddcl input data is swaped RESERVED Swap I/Q of Mixer output data 1'h0:: no_swap: I/Q of mixer output data is not swaped 1'h1:: swap: I/Q of mixer output data is swaped Swap ddcl input I data polarity 1'h0:: no_swap: I data polarity of ddcl input is not swaped 1'h1:: swap: I data polarity of ddcl input is swaped Swap ddcl input Q data polarity 1'h0:: no_swap: Q data polarity of ddcl input is not swaped 1'h1:: swap: Q data polarity of ddcl input is swaped Disable the ramping for edr guard time in ramp_gain_tx GFSK TX Gain in EDR BB Newpacket flag enable 1'h0:: Disable: the BB Newpacket flag enable 1'h1:: Enable: the BB Newpacket flag enable Packet select 1'h0:: packet72 1'h1:: new_packet gfsk u_err 10/32 gfsk u_dc 4/512 gfsk ct_u_sp for rx demod Switch err_in_patch for bt_dsp rx demod dpsk u_err 8/32 dpsk u_dc 5/64 Switch dpsk ct_u for bt_dsp rx demod Set the minimum phase error for rx demod. Select the GFSK AFC of demod Select the DPSK AFC of demod RESERVED GFSK demod threshold DPSK diff enable 1'h0:: Disable 1'h1:: Enable GFSK diff enable 1'h0:: Disable 1'h1:: Enable DPSK sample threshold for demod GFSK sample threshold for demod GFSK sample 2nd threshold for demod gfsk sample reference a2 for demod GFSK sample reference a1 for demod GFSK sample reference a3 for demod RESERVED tx guard timing delay to switch amp in ramp_gain_tx; counter in 13M RESERVED DC Cancle ct code for demod DAC Test Enable 1'h0 dac data is 52m_tx IQ 1'h1 dac data depends on dac_data_sel DAC Data Mux Select 6'b000000:: tx_52m_i: tx_52m_q 6'b000001:: tx_26m_i: tx_26m_q 6'b000010:: iqim_cancel_i: iqim_cancel_q 6'b000011:: tx_13m_i: tx_13m_q 6'b000100:: mixer_tx_i: mixer_tx_q 6'b000101:: accu_tx: blend_tx 6'b000110:: gfilter_tx: diff_tx 6'b000111:: ampm_am: ampm_pm 6'b001000:: cordic_tx_amp: cordic_tx_ang 6'b001001:: symbol2iq_tx_i: symbol2iq_tx_q 6'b001010:: tx_test_data0: tx_test_data1 6'b100000:: angle: angle_rc 6'b100001:: adc_data_i: adc_data_q 6'b100010:: adc_din_i: adc_din_q 6'b100011:: lpf_i: lpf_q 6'b100100:: rateconv_i: rateconv_q 6'b100101:: calib_i: calib_q 6'b100110:: dc_calib_i: dc_calib_q 6'b100111:: cancel_flt_i: cancel_flt_q 6'b101000:: notch_i: notch_q 6'b101001:: gain_i: gain_q 6'b101010:: ble_mux_i: ble_mux_q 6'b101011:: mixer_i: mixer_q 6'b101100:: srrc_i: srrc_q 6'b101101:: mixer_i_13_0: mixer_q[13:0] 6'b101110:: srrc_i_11_0: srrc_q[11:0] 6'b101111:: err_gfsk: err_dpsk 6'b110000:: afc_gfsk: afc_in 6'b110001:: angle_offset: angle_offset1 6'b110010:: rssi_out: rssi_out 6'b110011:: rx_test_data0: rx_test_data1 6'b110100:: rx_test_data2: rx_test_data3 1'b1::SRRC RSSI input data from mixer output data 1'b0::SRRC RSSI input data from SRRC output data 1'b1::mixer RSSI input data from mixer output data 1'b0::mixer RSSI input data from SRRC output data 2'h0::rssi_out = rssi_out_noise_pre 2'h1::rssi_out = rssi_out_noise_post 2'h2::rssi_out = rssi_out_pre 2'h3::rssi_out = rssi_out_post after SRRC RSSI threshold DC cancle1 edr dc hold enable before SRRC RSSI threshold Count sample threshold reset for demod. GFSK iph th reference for demod. Sample point initial value Guard time length threshold for demod DPSK Seek Start Count Fix7 enable during demod 1'h0:: Disable 1'h1:: Enable Fix7 mode select during bt dsp demod 1'h0:: threshold_2 1'h1:: threshold_3 Rounding enable after sinc. 1'h0:: Disable 1'h1:: Enable Threshold of Rounding after sinc. AGC maximum threshold for demod AGC minimum threshold for demod AGC maximum large threshold for demod AGC minimum large threshold for demod AGC minimum threshold for demod AGC logarithmic step enable for demod 1'h0:: Disable 1'h1:: Enable AGC step mode for demod 2'b00:: AGC_step_1 2'b01:: AGC_step_2 2'b10:: AGC_step_3 2'b11:: AGC_step_4 AGC step over Delay timer count enable 3'b000:: Delay_0us 3'b001:: Delay_0p5us 3'b010:: Delay_1us 3'b011:: Delay_2us 3'b100:: Delay_3us 3'b101:: Delay_4us 3'b110:: Delay_6us 3'b111:: Delay_8us AGC gain index initial value for bt dsp Demod mode select AGC minimum threshold gain select for demod 2'b00:: Gain_2 2'b01:: Gain_4 2'b10:: Gain_8 2'b11:: Gain_16 AGCtm_intv_int initial value for demod AGC tm_intv_int logarithmic initial value for demod AGC index select 1'h0:: dgc_index_dsp 1'h1:: dgc_index_mx DGC gain index Maximum agc gain index Newpacket select for demod 1'h0 If newpacket from BB has one zero byte, select GID for demod, else select newpacket from BB 1'h1 Select newpacket from BB Newpacket zero bytes number 2'b00 If the 1st byte of newpacket is zero, newpacket_bb_sel is logic high, else low 2'b01 If the 1st & 2nd byte of newpacket is zero, newpacket_bb_sel is logic high, else low 2'b10 If the 1st & 2nd & 3rd byte of newpacket is zero, newpacket_bb_sel is logic high, else low 2'b11 If the 1st & 2nd & 3rd &4th byte of newpacket is zero, newpacket_bb_sel is logic high, else low AGC mode for dsp 3'h0:: Normal 3'h1:: RESERVED 3'h2:: Hold_after_timer 3'h3:: fix_to_index_ini 3'h4:: Hold_by_FSM 3'h5:: Th_large_mode: select by FSM others RESERVED AGC hold waiting time length AGC hold time length RX DC Calibration Done RX DC Calibration Delay for 1 loop 2'h0:: 0p6ms 2'h1:: 1p2ms 2'h2:: 2p4ms 2'h3:: 4p8ms DC offset fix select for rx 1'h0:: by_calib: DC offset data set by calibration 1'h1:: by_reg: DC offset data set by register RX DC fixed offset data for I path when if_fix_dcofst is 1; otherwise use the auto calc values. RX DC fixed offset data for Q path when if_fix_dcofst is 1; otherwise use the auto calc values. rx dc offset for dc calibration; selected from dc_cali_i_fix & dc_i2d_work_i rx dc offset for dc calibration; selected from dc_cali_q_fix & dc_i2d_work_q TX Calibration Done tx calib out i tx calib out q Fix TX DC Offset TX Calibration Step Counters for 25KHz 2'b00:: 0p125_range 2'b01:: 0p25_range 2'b10:: 0p5_range 2'b11:: full_range TX Calibration Comparison Polarity TX Calibration Offset Polarity 0:: no_switch: the polarity of TX calibration offset 1:: switch: the polarity of TX calibration offset TX Calibration Selection 2'b00:: mean: (tx_cal1 + tx_cal2)/2 2'b01:: tx_cal1 2'b10:: tx_cal2 TX Calibration Offset Shift 2'b00:: x4: left shift by 2 bits 2'b01:: x2: left shift by 1 bit 2'b10:: x1: no shift TX Gain Table Pointer during work Bypass TX Calibration Offset 1'b0:: not_bypass 1'b1:: bypass Fixed TX I Signed Data for DC offset TX Q Signed Data for DC offset TX I Signed Data offset in use TX Q Signed Data offset in use RSSI gain 0000 ARSSI gain 0001 RSSI gain 0010 ARSSI gain 0011 RSSI gain 0100 ARSSI gain 0101 RSSI gain 0110 ARSSI gain 0111 RSSI gain 1000 ARSSI gain 1001 RSSI gain 1010 ARSSI gain 1011 RSSI gain 1100 ARSSI gain 1101 RSSI gain 1110 ARSSI gain 1111 DAC Clock Force Enable while rx data to dac Test Ports Clock Select 0:: clk_rx 1:: clk_tx Test Ports Data Select 4'h0:: dac_data_i 4'h1:: dac_data_q 4'h2:: dout_tx_i_sum 4'h3:: dout_tx_q_sum 4'h4:: dout_tx_dac_i: depends on dac_data_sel 4'h5:: dout_tx_dac_q 4'h6:: dout_rx_dac_i 4'h7:: dout_rx_dac_q 4'h8:: dout_tx_dac_i_13m: by en_tx_13m 4'h9:: dout_tx_dac_q_13m: by en_tx_13m 4'ha:: dout_rx_dac_i_13m: by en_rx_13m 4'hb:: dout_rx_dac_q_13m: by en_rx_13m 4'hc:: dout_rx_dac_i_14m: by en_rx_14m 4'hd:: dout_rx_dac_q_14m: by en_rx_14m 4'he:: dout_tx_dac_i_26m: by en_tx_26m 4'hf:: dout_tx_dac_q_26m: by en_tx_26m Test Ports Trigger Select 4'h0:: dem_st_chg 4'h1:: agc_st_chg 4'h2:: agc_flg_dem 4'h3:: ble_access_rb 4'h4:: if_peak 4'h5:: if_seeked_all 4'h6:: seek_en 4'h7:: flg_getsymbol 4'h8:: tx_symbol_off_gfsk 4'h9:: tx_amp_sel 4'ha:: tx_flg_start Demod sample threshold2 Demod sample threshold1 The 4th byte newpacket for demod when sel_sync(register_41[13]) is 1 The 3rd byte newpacket for demod when sel_sync(register_41[13]) is 1 The 2nd byte newpacket for demod when sel_sync(register_41[13]) is 1 The 1st byte newpacket for demod when sel_sync(register_41[13]) is 1 SRRC RSSI gain control Bluetooth GFSK modulation filter select MIXER RSSI gain control GFSK demod a2 reference for rx demod GFSK demod a1 reference for rx demod GFSK demod a3 reference for rx demod GFSK ramp speed select 1'h0:: Slow 1'h1:: Fast GFSK symbol end flag delay, with 13MHz clk step GFSK symbol end flag delay, with 1MHz clk step DPSK symbol delay, with 1MHz clk step GFSK symbol delay, with 1MHz clk step after SRRC RSSI noise out after mixer before SRRC RSSI noise out Switch the clk edge to sample rf ADC data 1'h0:: negedge: to sample the RF ADC data 1'h1:: posedge: to sample the RF ADC data TX/RX direction 1'h0:: by_hw: TX/RX flag setting by deleying resetn_dsp_tx 1'h1:: by_reg: TX/RX flag setting by register TX/RX flag 1'h0:: RX 1'h1:: TX RESERVED TX link 52M clk edge switch 1'h0:: Not_Switch 1'h1:: Switch Digital gain2 output I/Q swap 1'h0:: Not_Swap 1'h1:: Swap Rate converter LPF filter output I/Q swap 1'h0:: Not_Swap 1'h1:: Swap SRRC filter output I/Q swap 1'h0:: Not_Swap 1'h1:: Swap Low Pass Filter Enable in Channel Group1 1'h0:: bypass 1'h1:: enable Rate Converter Enable in Channel Group1 1'h0:: bypass 1'h1:: enable Notch Filter Enable in Channel Group1 1'h0:: bypass 1'h1:: enable Low Pass Filter Enable in Channel Group0 1'h0:: bypass 1'h1:: enable Rate Converter Enable in Channel Group0 1'h0:: bypass 1'h1:: enable Notch Filter Enable in Channel Group0 1'h0:: bypass 1'h1:: enable Dynamic sync enable for demod of rx link 1'h0:: static 1'h1:: Dynamic Dynamic sync threshold The 2nd minimum sync phase error threshold GFSK modulation index Tx link IQ swap 1'h0:: Not_swap 1'h1:: Swap GFSK delay after gfsk modulation DPSK delay after dpsk modulation DPSK amplitude delay after dpsk modulation Debug Master Data Select 5'h0:: gfilter_tx_dout 5'h1:: symbol2iq_tx_dout_q: symbol2iq_tx_dout_i 5'h2:: cordic_tx_amp_dout: cordic_tx_angle_dout 5'h3:: ampm_tx_dout_am: ampm_tx_dout_pm 5'h4:: diff_tx_dout 5'h5:: freq_blend_tx_dout 5'h6:: intigrate_tx_dout 5'h7:: cordic_iq_tx_dout_q: cordic_iq_tx_dout_i 5'h8:: dout_tx_13m_q: dout_tx_13m_i 5'h9:: iqim_cancel_dout_q: iqim_cancel_dout_i 5'ha:: dout_tx_26m_q: dout_tx_26m_i 5'hb:: dout_tx_52m_q: dout_tx_52m_i 5'hc:: dac_grp_bit_q_outp: dac_grp_bit_i_outp 5'h10:: adc_data_q: adc_data_i 5'h11:: adc_din_q: adc_din_i 5'h12:: lpf_q: lpf_i 5'h13:: rateconv_q: rateconv_i 5'h14:: calib_q: calib_i 5'h15:: dc_calib_q: dc_calib_i 5'h16:: cancel_flt_i: cancel_flt_q 5'h17:: notch_q: notch_i 5'h18:: gain_q: gain_i 5'h19:: ble_mux_q: ble_mux_i 5'h1a:: mixer_q: mixer_i 5'h1b:: srrc_q: srrc_i 5'h1c:: rssi_out 5'h1d:: angle_rc: angle 5'h1e:: angle_offset1: angle_offset 5'h1f:: err_dpsk: err_gfsk GFSK modulation index for BLE mode newpacket byte 4 inuse; selected from newpacket_reg, GID & newpacket_bb newpacket byte 3 inuse; selected from newpacket_reg, GID & newpacket_bb newpacket byte 2 inuse; selected from newpacket_reg, GID & newpacket_bb newpacket byte 1 inuse; selected from newpacket_reg, GID & newpacket_bb ?? ?? ?? ?? ?? ?? ?? RESERVED ?? ?? ?? ?? Error on Q to reduce IQ mismatch Image Error on I to reduce IQ mismatch Image PM Compensation Shift PM Compensation Bypass 1'b0:: enable 1'b1:: bypass AM Compensation Bypass 1'b0:: enable 1'b1:: bypass AMAM Compensation Coef0 AMAM Compensation Coef1 AMAM Compensation Coef2 AMAM Compensation Coef3 AMAM Compensation Coef4 AMAM Compensation Coef5 AMAM Compensation Coef6 AMAM Compensation Coef7 AMAM Compensation Coef8 AMAM Compensation Coef9 AMAM Compensation Coef10 AMAM Compensation Coef11 AMAM Compensation Coef12 AMAM Compensation Coef13 AMAM Compensation Coef14 AMAM Compensation Coef15 AMAM Compensation Coef16 AMPM Compensation Coef0 AMPM Compensation Coef1 AMPM Compensation Coef2 AMPM Compensation Coef3 AMPM Compensation Coef4 AMPM Compensation Coef5 AMPM Compensation Coef6 AMPM Compensation Coef7 AMPM Compensation Coef8 AMPM Compensation Coef9 AMPM Compensation Coef10 AMPM Compensation Coef11 AMPM Compensation Coef12 AMPM Compensation Coef13 AMPM Compensation Coef14 AMPM Compensation Coef15 AMPM Compensation Coef16 Notch Filter Coefficient B Notch Filter Coefficient A EDR3 Adapt Demodulation Enable 1'b0:: disable 1'b1:: enable second u_err of the dpsk 2/32 second u_dc of the dpsk 2/512 EDR3 Adapt Demodulation Threshold auto gfsk digital gain high 4bits. Tx_power=3'h7 auto gfsk digital gain high 4bits. Tx_power=3'h6 auto gfsk digital gain high 4bits. Tx_power=3'h5 auto gfsk digital gain high 4bits. Tx_power=3'h4 auto gfsk digital gain high 4bits. Tx_power=3'h3 auto gfsk digital gain high 4bits. Tx_power=3'h2 auto gfsk digital gain high 4bits. Tx_power=3'h1 auto gfsk digital gain high 4bits. Tx_power=3'h0 auto gfsk edr digital gain high 4bits. Tx_power=3'h7 auto gfsk edr digital gain high 4bits. Tx_power=3'h6 auto gfsk edr digital gain high 4bits. Tx_power=3'h5 auto gfsk edr digital gain high 4bits. Tx_power=3'h4 auto gfsk edr digital gain high 4bits. Tx_power=3'h3 auto gfsk edr digital gain high 4bits. Tx_power=3'h2 auto gfsk edr digital gain high 4bits. Tx_power=3'h1 auto gfsk edr digital gain high 4bits. Tx_power=3'h0 auto dpsk digital gain high 4bits. Tx_power=3'h7 auto dpsk digital gain high 4bits. Tx_power=3'h6 auto dpsk digital gain high 4bits. Tx_power=3'h5 auto dpsk digital gain high 4bits. Tx_power=3'h4 auto dpsk digital gain high 4bits. Tx_power=3'h3 auto dpsk digital gain high 4bits. Tx_power=3'h2 auto dpsk digital gain high 4bits. Tx_power=3'h1 auto dpsk digital gain high 4bits. Tx_power=3'h0 GFSK modulation equalization gain Phase path delay number 2, with 26MHz clk step Phase path delay number 1, with 26MHz clk step GFSK Low pass filter bypass 1'h0 Not bypass 1'h1 bypass Note: IQ Tx mode: register_c9[5:4]=00 Polar Loop & IQ Tx mode: register_c9[5:4]=01 All Polar Loop Tx mode: register_c9[5:4]=11 GFSK low pass filter enable 1'h0: Enable LPFil, output low pass gfsk signal 1'h1: Disable LPFil, output is zero GFSK low pass filter pass band width select 1: lpfil_freq_tx_bw_ct[4]=0 BW = 100K + lpfil_freq_tx_bw_ct* 20 2: lpfil_freq_tx_bw_ct[4]=1 BW = 50K Delay of the gfsk and dpsk mixed phase I/Q path delay number 1, with 26MHz clk step I/Q path delay number 2, with 26MHz clk step High frequency path delay amp tmp delay tx polar modulation mode selected 1'b0::phase mode 1'b1::frequency mode tx polar modulation all pass filter bypass ctl 1'b1::bypass 1'b0::no bypass tx polar modulation apf num coe-2.14 tx polar modulation apf num coe tx polar modulation apf num coe tx polar modulation apf num coe tx polar modulation apf den coe-2.14 tx polar modulation apf den coe tx polar modulation apf den coe ErrSum beta coef 3'h0:: 1div2 3'h1:: 1div4 3'h2:: 1div8 3'h3:: 1div16 3'h4:: 1div32 3'h5:: 1div64 third u_err of the dpsk 8/32 third u_dc of the dpsk 1/512 0: block7, protect disabled or access permitted 1: block7, protect enabled or access forbidden 0: block6, protect disabled or access permitted 1: block6, protect enabled or access forbidden 0: block5, protect disabled or access permitted 1: block5, protect enabled or access forbidden 0: block4, protect disabled or access permitted 1: block4, protect enabled or access forbidden 0: block3, protect disabled or access permitted 1: block3, protect enabled or access forbidden 0: block2, protect disabled or access permitted 1: block2, protect enabled or access forbidden 0: block1, protect disabled or access permitted 1: block1, protect enabled or access forbidden 0: block0, protect disabled or access permitted 1: block0, protect enabled or access forbidden 0: block7, cache remap disabled 1: block7, cache remap enabled 0: block6, cache remap disabled 1: block6, cache remap enabled 0: block5, cache remap disabled 1: block5, cache remap enabled 0: block4, cache remap disabled 1: block4, cache remap enabled 0: block3, cache remap disabled 1: block3, cache remap enabled 0: block2, cache remap disabled 1: block2, cache remap enabled 0: block1, cache remap disabled 1: block1, cache remap enabled 0: block0, cache remap disabled 1: block0, cache remap enabled 0: block7, cache disabled 1: block7, cache enabled 0: block6, cache disabled 1: block6, cache enabled 0: block5, cache disabled 1: block5, cache enabled 0: block4, cache disabled 1: block4, cache enabled 0: block3, cache disabled 1: block3, cache enabled 0: block2, cache disabled 1: block2, cache enabled 0: block1, cache disabled 1: block1, cache enabled 0: block0, cache disabled 1: block0, cache enabled block 1 start address block 2 start address block 3 start address block 4 start address block 5 start address block 6 start address block 7 start address block 0 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk0_remap_offset block 1 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk1_remap_offset block 2 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk2_remap_offset block 3 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk3_remap_offset block 4 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk4_remap_offset block 5 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk5_remap_offset block 6 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk6_remap_offset block 7 remap offset when the block remap function is enabled, the address after remap will be original addr + rf_blk7_remap_offset cache debug mode enable: 0: normal mode 1: debug mode This bit MUST always be cleared during cache operating 0: (recommended) software can run in cacheable region during software command processing 1: software cannot run in cacheable region during software command processing cache size selection: 0: 4K Byte 1: 8K Byte 2: 16K Byte 3: 32K Byte hprot control register which provide 4bit hprot for cache ctrl AHB? hprot control register which provide 4bit hprot for cache bus AHB Bit [5]: 1b1: hprot[3] from CM4 go through cache controller without modification 1b0: hprot[3] is provided by cache controller register Bit [4]: 1b1: hprot[2] from CM4 go through cache controller without modification 1b0: hprot[2] is provided by cache controller register Bit [3]: 1b1: hprot[1] from CM4 go through cache controller without modification 1b0: hprot[1] is provided by cache controller register Bit [2]: 1b1: hprot[0] from CM4 go through cache controller without modification 1b0: hprot[0] is provided by cache controller register cache write operation mode 2b00: write through 2b01: write back, no write allocate 2b10: write back, write allocate trigging address for protect block? rf_write_ongoing, this is a status register for write through mode to avoid potential coherence issue. 1b1: the cache is still doing AHB write transaction to the main memory and the data is not written into the main memory. 1b0: the cache has finished AHB write transaction and the data is written into the main memory. rf_cmd_st rf_cache_st cmd_all : not used cmd_range : start address cmd_entry : entry address cmd_all : not used cmd_range : start address cmd_entry : entry address software command start: write 1 to this bit to issue one command software command type: 6h0 : clean all 6h1 : clean range 6h2 : clean entry 6h3 : reserved 6h4 : invalid all 6h5 : invalid range 6h6 : invalid entry 6h7 : reserved 6h8 : clean and invalid all 6h9 : clean and invalid range 6hA : clean and invalid entry 6hB : reserved interrupt enable for protect block trigging? interrupt enable for software command done interrupt raw status for protect block trigging interrupt raw status for software command done? interrupt masked status for protect block trigging interrupt masked status for software command done? interrupt clear for protect block trigging interrupt clear for software command done? Cache write hit times. When cache write hit, the counter value increment by 1 clear write counter values to zero? 1: write hit/miss counter will run 0: write hit/miss counter will stop Cache write hit times. When cache write hit, the counter value increment by 1 Cache read hit times. When cache read hit, the counter value increment by 1? clear read counter values to zero? 1: read hit/miss counter will run 0: read hit/miss counter will stop Cache read miss times. When cache read miss, the counter value increment by 1 Cache master AHB active cycles in total. When master AHB is active (hsel and htrans[1]), the counter value increment by 1? clear HACT and HRDY counter values to zero 1: HACT and HRDY counters will run 0: HACT and HRDY counters will stop The HRDY counter counts the valid cycles of HREADY signal from the cache controller to the master when the master AHB is active. When HREADY signal to the master is high and the master AHB is active, the counter value increment by 1? Value of snapshots, snapshot value is automatically incremented at frame interrupt. This snapshot counter wrap at the value given by Snapshot_Cfg number of snapshot When read from the Xcpu, this return the cause of interruption, basically the set/clear register X_Irq1 part masked with X_Irq1_Mask When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask When read from the Xcpu, this return the cause of interruption, basically the set/clear register Irq0 part masked with Irq0_Mask When read from the Bcpu, this return the cause of interruption, basically the set/clear register Irq1 part masked with Irq1_Mask bit type is changed from rs to r. When read: returns the value of the Irq1_Mask register. When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged. The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 bit type is changed from rs to r. When read: returns the value of the Irq0_Mask register. When written: value is used as a bit field, each bit at '1' sets the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged. The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 bit type is changed from rc to r. When read: returns the value of the Irq1_Mask register. When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq1_Mask register, bits at '0' leave the corresponding bit unchanged. The Irq1_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 1 bit type is changed from rc to r. When read: returns the value of the Irq0_Mask register. When written: value is used as a bit field, each bit at '1' clears the corresponding bit in the Irq0_Mask register, bits at '0' leave the corresponding bit unchanged. The Irq0_Mask masks the set/clear register to trigger interrupts on the XCPU/BCPU using line 0 bit type is changed from rs to r. When read, returns the value of the set/clear register. When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. These bits can also trigger interrupts on the XCPU/BCPU if enabled bit type is changed from rs to r. When read, returns the value of the set/clear register. When written, value is used as a bit field, each bit at '1' sets the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. These bits can also trigger interrupts on the XCPU/BCPU if enabled. bit type is changed from rc to r. When read, returns the value of the set/clear register. When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. These bits can also trigger interrupts on the XCPU/BCPU if enabled. bit type is changed from rc to r. When read, returns the value of the set/clear register. When written, value is used as a bit field, each bit at '1' clears the corresponding bit in the set/clear register, bits at '0' leave the corresponding bit unchanged. These bits can also trigger interrupts on the XCPU/BCPU if enabled debug bus master enable transfer word length data selection dump trigger selection select trigger from soft or hardware wrap the whole fifo, when EOF, keep on write by the start addr burst type 2'b00:: single 2'b01:: incr4 2'b10:: incr8 2'b11:: incrx length of burst when incrx max incr16 start address of transfer mask for transfer error mask for ovfl mask for comp half mask for comp end bit type is changed from w1c to rc. interrupt for ahb transfer error bit type is changed from w1c to rc. interrupt from fifo overfolw bit type is changed from w1c to rc. half interrupt from transfer complete bit type is changed from w1c to rc. end interrupt from transfer complete bit type is changed from w1c to rc. data_packer soft reset done bit type is changed from wos to s. soft reset bit type is changed from wos to s. dump trigger from soft TX data I. Everytime this register is read, the data will be popped out of the tx_data_fifo. TX data Q. Everytime this register is read, the data will be popped out of the tx_data_fifo. revision id. debug output enable. 1'd0:: unsigned 1'd1:: 2s_complementary force clock on. tx data enable. 1'd0:: disable 1'd1:: enable i2s delay 1t enable. i2s enable. 1'd0:: disable 1'd1:: enable coherent fmdemsource selection. 1'd0:: output_lpfil 1'd1:: output_dig_gain offset source selection. 1'd0:: output_afc 1'd1:: output_offset_filter rssi source during seek seelction. 1'd0:: rssi_db1 1'd1:: signal_db1 noise cancel source source selection. 1'd0:: noise_db2 1'd1:: rssi_db2 noise source selection. 2'd0:: dangle0 2'd1:: dangle1 2'd2:: dangle 2 adc clock invert. pilot phase. 1'd0:: sin 1'd1:: cos bypass deemphasis. bypass 15KHz LPF. bypass fircut during seeking. bypass fircut. LR swap. IQ swap for fmdem. IQ swap after 125KHz mixer. IQ swap before 125KHz mixer. lo selection. 1'd0:: low low if; Default is +125KHz. 1'd1:: high high if. Default is -125KHz AFC disable. 1'd0:: enable 1'd1:: disable soft blend off. 1'd0:: enable 1'd1:: disable soft mute enable. 1'd0:: disable 1'd1:: enable de-emphasis. 1'd0:: 75us 1'd1:: 50us mono select. 1'd0:: force : mono 1'd1:: stereo mute. 1'd0:: normal 1'd1:: mute the number of data words in tx fifowhich are valid for read. tx fifo underflow. User reads tx_fifo_rdata while no data valid in it. tx fifo overflow. User is not able to read tx_fifo_rdata in time so that fm_dsp discard valid data. clear tx fifo. tx data selection. SNR counter threshold. delta rssi threshold during UPPER/LOWER seeking. Unit is db. threshold for SNR. Unit is db. seek upper/lower adjacent freq setting. Unit is 5.12KHz. 1'd0:: disable disable afc during seeking; 1'd1:: enable enable afc during seeking. seek mode. 3'd0:: seek_current_only 3'd1:: seek_current_or_adjacent success when either current or adjacent freq is successful; 3'd2:: seek_current_and_adjacent success when both current and adjacent freq are successful; 3'd3:: snr_st test mode. stop at SNR_ST; 3'd4:: center_st test mode. stop at CENTER_ST; 3'd5:: upper_st test mode. stop at UPPER_ST; 3'd6:: lower_st testmode. stop at LOWER_ST; 3'd7:: seek_bypass 1'd0: disable 1'd1: enable [4]: seek with pilot; [3]: seek with offset; [2]: seek with snr; [1]: seek with rssi; [0]: seek with noise. pilot counter threshold. rssi counter threshold. noise counter threshold. offset counter threshold. noise low threshold. Unit is db. noise high threshold. Unit is db. RSSI low threshold. Unit is db. RSSI high threshold. Unit is db. offset low threshold. Unit is db. offset high threshold. Unit is db. pilot low threshold. Unit is db. pilot high threshold. Unit is db. seek time for SNR detect. Unit is 0.75ms. seek time for upper/lower adjacent freq. Unit is 0.75ms. seek time for current freq. Unit is 0.75ms. seek time for agc/afc stable. Unit is 0.75ms. [5:3]: afc dc filter bandwidth setting during seeking. [2:0]: afc acc step setting during seeking. [5:3]: afc dc filter bandwidth setting during seek is ready. [2:0]: afc acc step setting during seek is ready. afc following range. Unit is 2.5KHz. inverse afc adjust value. agc target power. Unit is 2db. agc test mode. Fix gain. agc loop gain during normal. agc loop gian during seeking. agc update time during normal. agc update time during seeking. agc digital gain threshold. Unit is 2db. agc initial index. agc enable delay time after reset. 3'd0:: 0 : 0.375us 3'd1:: 1 : 3us 3'd2:: 2 : 6us 3'd3:: 3 : 9.74us 3'd4:: 4 : 13.875us 3'd5:: 5 : 18us 3'd6:: 6 : 21us 3'd7: 7 : 24us basic dig gain. Unit is db. agc IIR bandwidth. [5:3]: agc loop sub step when sinc_over or log_agc>log_agc_th [2:0]: agc loop sub step when acc I saturation. threshold for agc lopp adjust. Unit is 1db. if 1, adjust agc_index sub step when log_agc>log_agc_th ana gain rssi for agc_index=3 ana gain rssi for agc_index=2 ana gain rssi for agc_index=1 ana gain rssi for agc_index=0 ana gain rssi for agc_index=7 ana gain rssi for agc_index=6 ana gain rssi for agc_index=5 ana gain rssi for agc_index=4 ana gain rssi for agc_index=b ana gain rssi for agc_index=a ana gain rssi for agc_index=9 ana gain rssi for agc_index=8 ana gain rssi for agc_index=f ana gain rssi for agc_index=e ana gain rssi for agc_index=d ana gain rssi for agc_index=c fircut/gain38k change low threshold for RSSI. Unit is 1db. fircut/gain38k change high threshold for RSSI. Unit is 1db. threshold. Unit is 2db. threshold. Unit is 2db. 1'd0: select cordic fmdem 1'd1: select dpll fmdem. [2]: for seeing; [1]: for nosie<th_min; [0]: for noise>th_max. fircut/gain38k change force on fircut bandwidth select during seeking UPPER/LOWER[2:0] and CENTER[5:3]. [40KHz:20KHz:180KHz] fircut bandwidth select during seeready and bad conditiong. Offset is over th. CENTER. [40KHz:20KHz:180KHz] fircut bandwidth select during seek ready and bad condition. Offset is under th. [40KHz:20KHz:180KHz] fircut bandwidth select during seek ready and good condition. [40KHz:20KHz:180KHz] bandwidth threshold. Unit is 2db fircut bandwidth select during bad condition. [40KHz:20KHz:180KHz] bandwidth threshold. Unit is 2db [8:6]: gain for mpx signal. [5:0]: gain for stereo. [5:3]:6db;[2:1]:2db;[0]:1db. dig gain change delay setting. Unit is 0.375us dig gain for signal before 125KHz mixer. 2'd0:: 0db 2'd1:: 6db 2'd2:: 12db 3'd3:: 18db [2]: enable over threshold detection. [1:0]: over threshold selection. 2'd0:: 0 : 0.75 2'd1:: 1 : 0.9 2'd2:: 2 : 0.95 2'd3:: 3 : 1 1'd0: *0.75 1'd1: *1 for sinc_limit. dc cancel control. [3]: dccancel mode. 1'd0: bypass; 1'd1: enable [2:0]: bandwidth. 19kHz tone detect bandwidthduring normal. 19kHz tone detect bandwidth during seeking. nco 2ord bandwidth. nco dc bandwidth. softmute threshold for RSSI. softmute threshold for noise. softmute threshold for SNR. softmute threshold for offset. softmute rate. Fast->slow. softmute attenu setting. softblend threshold for RSSI. softblend threshold for noise. offset filter bandwidth. direct deemphasis hcc reg. step 19k value interval value [5:3]: noise_db1 bandwidth [2:0]: noise_db2 bandwidth [5:3]: signal_db1 bandwidth [2:0]: signal_db2 bandwidth [5:3]: rssi_db1 bandwidth [2:0]: rssi_db2 bandwidth [5:3]: pilot_db1 bandwidth [2:0]: pilot_db2 bandwitdh rssi. Unit is db. snr. Unit is db. signal. Unit is db. frequency offset. Unit is db. [4]: 19k pilot flag [3]: offset flag [2]: snr flag [1]: rssi flag [0]: noise flag interrupt enable interrupt pending bit type is changed from w1s to rs. set interrupt pending bit type is changed from w1c to rc. clear interrupt pending Enable sleep sleep stauts 0: not_sleep 1: sleep when 1 written,core enters debug mode, when 0 written, core exits debug mode when read, 1 means core is in debug mode single step enable set when the core is a sleeping state and wait for an event single-step hit, sticky bit that must be cleared by external debugger environment call for M-mode store access fault (together with laf) store address Misaligned (never traps) load access fault (together with saf) load access Misaligned (never traps) ebreak instruction causes trap illegal instruction instruction access fault (not implemented) instruction address misaligned (never traps) interrupt caused us to enter debug mode exception/interrupt number general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register general purpose register Next PC to be executed previous PC, already executed Statically 2'b11 and cannot be altered Interrupt enable: When an exception is encountered, Interrupt Enable will be set to 1'b0. When the eret instruction is executed, the original value of the Interrupt Enable will be restored, as MESTATUS will replace MSTATUS. If you want to be enable interrupt handling in your exception handler, set the Interrupt Enable to 1'b1 inside your handler code. When an exception is encountered, the current program counter is saved in MEPC, and the core jumps to the exception address. When an eret instruction is executed, the value from MEPC replaces the current program counter. this bit is set when the exception was triggerd by an interrupt exception code hardware loop 0 start hardware loop 0 end hardware loop 0 counter hardware loop 1 start hardware loop 1 end hardware loop 1 counter Statically 2'b11 and cannot be altered Interrupt enable: When an exception is encountered, the current value of MSTATUS is saved in MESTATUS. When an eret instruction is executed, the value from MESTATUS replaces MSTATUS register. read as 0, which means RV32I RI5CY only supports the I and M extension, plus the RI5CY non-standard extensions. This means bits 8(I), 12(M) and 23(X) are 1, the rest is 0. ID of the cluster ID of the within the cluster Revision ID. BT channel control selection. 1'h0:: bt 1'h1:: reg fm adc clock mode. 1'd0:: divider divider of pll 1'd1:: adpll 43.008MHz enable bt hopping while channel is muliplier of 26MHz during rx procedure. If this bit is set to 1'd1, rf_interface will change the ADC clock to 28/56MHz generated by adpll instead of 26/52MHz crystal clock to avoid the receiving interference caused by 26MHz adc clock. enable BT ARFCN tune diff mode. If this bit is set to 1'd1, rf_interface will redo the rx/tx procedure (including pll calibration process) if ARFCN changes during one rx/tx procedure. enable all digital clock. If this bit is set to 1'd1, all digital clocks including gating ones will be forcely on. RF mode. 2'd0:: BT 2'd1:: WIFI 2'd2:: FM Chip self_cal enable. Self cal process will be triggered at posedge of chip_self_cal_enable. soft reset. Active low. BT channel type. 1'd0:: normal 1'd1:: multiplier Multiplier of 26MHz. _x000D_ BT Channel number. _x000D_ 7'h00 : Channel0 _x000D_ 7'h4E : Channel78 frequency direct reg. u7.10, unit is MHz WIFI freq mode. 1'd0:: channel channel number mode. Channel Freq = 2407MHz + 5MH*wf_chn 1'd1:: direct direct mode. Channel Freq = 2412MH + wf_freq_direct WIFI channel. Start tune. WIFI will be started at the posedge of wf_tune. frequency direct reg. u6.10, unit is MHz FM band select. 2'd0:: 87_108MHz : (US/Europe) 2'd1:: 76_91MHz : (Japan) 2'd2:: 76_108MHz : (World Wide) 2'd3:: 65_76MHz : (East Europe) FM freq mode. 1'd0:: channel channel number mode. Channel Freq = 25KHz*fm_chan_reg + bottom freq 1'd1:: direct direct mode. Channel Freq = bottom freq + fm_freq_direct FM channel. Start tune. FM will be started at the posedge of fm_tune. FM intermediate frequency mode. 1'd0:: positive 1'd1:: negtive FM intermediate freqeuncy. u1.10. Unit is Mhz. Default is 125KHz. _x000D_ enable zero intermediate frequency. 1'd0:: use_bt_freq use intermediate frequency defined by bt_digital_lo_freq; 1'd1:: use_0hz use 0Hz intermediate frequency. BT intermediate frequency mode. 1'd0:: positive 1'd1:: negtive BT intermediate freqeuncy. u1.10. Unit is Mhz. Default is740KHz. To be used when pll_pll_freq_dr=1._x000D_ Fomula is freq*2^24/(mdll_div*crystal_clk) If 1, pll frequency is decided by freq register;_x000D_ If 1, adpll sdm resetn uses sdm_resetn_reg; _x000D_ if 0, use logic value. adpll Sdm modulator module reset register Invert SDM clock edge. SDM dither bypass enable. To be used when adpll_sdm_freq_dr=1._x000D_ Fomula is freq*2^23/crystal_clk Pll_vco_band_reg direct reg enable. VCO band setting. Vco bit hold time when vco bit changed during pll vco band calibration._x000D_ 3'd0:: vco_bit_hold_time_0 : 0.25us_x000D_ 3'd1:: vco_bit_hold_time_1 : 0.5us_x000D_ 3'd2:: vco_bit_hold_time_2 : 0.75us_x000D_ 3'd3:: vco_bit_hold_time_3 : 1us_x000D_ 3'd4:: vco_bit_hold_time_4 : 1.25us_x000D_ 3'd5:: vco_bit_hold_time_5 : 1.5us_x000D_ 3'd6:: vco_bit_hold_time_6 : 1.75us_x000D_ 3'd7:: vco_bit_hold_time_7 : 2us If 1, select the best vco band bit pll cal count time select_x000D_ 3'd0:: each_cnt_time_0 : 0.5us_x000D_ 3'd1:: each_cnt_time_1 : 1us_x000D_ 3'd2:: each_cnt_time_2 : 2us_x000D_ 3'd4:: each_cnt_time_3 : 4us_x000D_ 3'd5:: each_cnt_time_4 : 8us Define pll_cal initial delay, which is the time between RXON(TXON) and rxpll_cal_enable._x000D_ Unit is us. Global reset. 1:: unreset 0:: reset debug host uart clock domain reset, active low riscv debug unit rstb. Active low. watch dog reset wcn system enable, 1 enable the reset, else no. wake up logic reset. for bt hclk reset. 1:: unreset 0:: reset for bt 32k clock reset. 1:: unreset 0:: reset uart clock domain reset. 1:: unreset 0:: reset watch dog clock domain reset, 32k actually. 1:: unreset 0:: reset bt master clock reset. 1:: unreset 0:: reset bt core's debug master bus reset. 1:: unreset 0:: reset AUDIFC function reset. Active low. 1:: unreset 0:: reset sys_ifc module bus reset. 1:: unreset 0:: reset riscv jtag-> ahb protocol bus reset. 1:: unreset 0:: reset riscv reset. 1:: unreset 0:: reset bt_dig memory datapath reset. 1:: unreset 0:: reset not used, reserved bus clock selection: 0 sel hclk, 1 sel 26m, others sel 32k wake up logic clock enable bt core master clock indicator, 13M as default. bt master clock divider's denom, bt_master_clk = bus_clk/reg_bt_master_clk_denom bit type is changed from w1s to rs. load the bt_master_clk_denom into the clock divider. bt master clock divider enable, this divider source is hclk. low power clock enable for bt jtag bus clock enable manually to set the sys_ifc bus clock to be open always. manually to set the sys_ifc channels' clock to be open always. manually to set the aud_ifc bus clock to be open always. manually to set the aud_ifc channel 0' clock to be open always. bt_dig memory module's bus clock enable bt core's bus clock enable debug master bus clock enable manually to set the uart clock to be open always. manually to set the uart sys(function) clock to be open always. watch dog clock enable riscv bus clock enable apb bus clock to be open always. memory access with clock enable. 13m from osc 26m, for bt master clock sel. bit[21] when 1 sel the result of bit[20], otherwise from hclk divider; bit [20] when 1 sel 26m otherwise 13m bt_master_clk to bt core. ifc debug host dma hclk force on. debug host pclk force enable debug uart pclk force enable debug host sclk force enable bit type is changed from w1s to rs. use new div parameters for divider. uart clock divider enable. uart clock divider denom's configuration bit type is changed from w1s to rs. Debug host uart clock load configuration Debug host uart clock numerator Debug host uart clock denominator Debug host clock divider enable bit type is changed from w1s to rs. use new div parameters for divider. clock 208m divider enable. clock 208m divider num's configuration clock 208m divider denom's configuration sys to bt irq, read only for check wdt gen irq to system enable control, 1 indicates enable. reserved for future use, the wakeup to sys now use comregs's. generate interrupt to system the start address for riscv RF Register Interface Selection 1:: SPI 0:: APB tx clk sel 1'b1::selected sdm div clk as tx clk tx clk sel 1'b1::selected sdm ref clk as tx clk RX Mode 0:: BT 1:: FM 2:: WLAN Data Source for LVDS Output 1:: internal DFE TX 0:: internal ADC Data Source for Internal DAC 1:: external DFE TX 0:: internal DFE TX Data Source for Internal DFE RX 1:: external ADC 0:: internal ADC Debug trigger selection The triger is forced to 0 when disabled. Debug clock selection The debug clock is forced to 0 when disabled. nibble shift mode 0:: nibble_shift_mode0 Ouptut is {dbg_out[11::0], dbg_out[15::12]} 1:: nibble_shift_mode1 Ouptut is {dbg_out[15::12], dbg_out[7::4], dbg_out[11::8], dbg_out[3::0]} nibble shift enable 0:: nibble_shift_disable Output is dbg_out[15::0] 1:: nibble_shift_en Output is prcoess according dbg_out_nibble_mode Byte swap of dbg_out Half Byte swap of dbg_out when 0, all the mux data is forced to be 0. Debug out selection enable external wakeup request enable hci uart break wakeup request enable hci activity wakeup request bt2host wakeup mode 1::level mode 0::pulse mode bt2host wakeup level mode active cycle bit type is changed from wos to s. bt2host wakeup trigger bt2host wakeup status i2s_sel when 1, select the i2s output, else select the pcm. LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) LS+RME+RM(4Bits) + PGEN +KEN +EMA(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) dual port: LS + RMEB + TEST1B + RMB(4Bits)+RMEA+TEST1A+RMA(4Bits)+RET1N+EMAA/EMB(3Bits) LS+RME+RM(4Bits) + RET1N + EMAW(2Bits) + EMA(3Bits) the unit is 1M, 48M in 8910m as default. the address for riscv branch from rom, configured by ap CPU Interactive reg1 CPU Interactive reg0 This field indicates which standard channel to use. Before using a channel, the CPU read this register to know which channel must be used. After reading this registers, the channel is to be regarded as busy. After reading this register, if the CPU doesn't want to use the specified channel, the CPU must write a disable_ in the control register of the channel to release the channel. 4'h0::use_ch0: use Channel0 4'h1::use_ch1: use Channel1 4'h2::use_ch2: use Channel2 4'h3::use_ch3: use Channel3 4'h4::use_ch4: use Channel4 4'h5::use_ch5: use Channel5 4'h6::use_ch6: use Channel6 4'h7::use_ch7: use Channel7 4'hf::all_busy: all channels are busy This register indicates which standard channel is busy (this field doesn't include the RF_SPI channel). A standard channel is mark as busy, when a channel is eNonebled or a previous reading of the GET_CH register, the field CH_TO_USE indicates this channel. One bit per channel This register indicates which channel is eNonebled. It is a copy of the enable bit of the control register of each channel. One bit per channel, for example:: 8'h00::all_ch_disabled: all channel disabled 8'h01::ch0_enabled: Ch0 enabled 8'h02::ch1_enabled: Ch1 enabled 8'h04::ch2_enabled: Ch2 enabled 8'h05::ch_0_2_enabled: Ch0 and Ch2 enabled 8'h07::ch_0_1_2_enabled: Ch0, Ch1 and Ch2 enabled 8'hff::ch_all_enabled: all channels eNonebled Debug Channel Status . 0:: dbg_ch_run: The debug channel is running (not idle) 1::dbg_ch_idle: The debug channel is in idle mode When one, flush the interNonel FIFO channel. This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. Before writting back this bit to zero the interNonel fifo must empty. Select DMA Request source 0:: SYS_ID_TX_UART 1:: SYS_ID_RX_UART 2:: SYS_ID_TX_SDMMC 3:: SYS_ID_RX_SDMMC 4:: SYS_ID_TX_SPI1 5:: SYS_ID_RX_SPI1 6:: SYS_ID_TX_DEBUG_UART 7:: SYS_ID_RX_DEBUG_UART Peripheral Size 0::per_size_8: 8-bit peripheral 1::per_size_32: 32-bit peripheral Set Auto-disable_ mode 0::auto_disable_close: when TC reach zero the channel is not automatically released. 1::auto_disable_open: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. Set Auto-disable_ mode 0:: auto_dis_mode0: when TC reach zero the channel is not automatically released. 1:: auto_dis_mode1: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. Read FIFO data exchange high 8-bit and low 8-bit. 0:: Exchange 1:: No_exchange bit type is changed from wrc to rc. Channel Disable, write one in this bit disable_ the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d. bit type is changed from wrc to rc. Channel Enable, write one in this bit eNoneble the channel. When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. The internal channel fifo is empty Enable bit, when '1' the channel is running AHB Address. This field represent the start address of the transfer. For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size_ in bytes to perform. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. When one, flush the interNonel FIFO channel. This bit must be used only in case of Rx transfer. Until this bit is 1, the APB request is masked. The flush doesn't release the channel. Before writting back this bit to zero the interNonel fifo must empty. Select DMA Request source 0:: SYS_ID_TX_UART 1:: SYS_ID_RX_UART 2:: SYS_ID_TX_SDMMC 3:: SYS_ID_RX_SDMMC 4:: SYS_ID_TX_SPI1 5:: SYS_ID_RX_SPI1 6:: SYS_ID_TX_DEBUG_UART 7:: SYS_ID_RX_DEBUG_UART Peripheral Size 0::per_size_8: 8-bit peripheral 1::per_size_32: 32-bit peripheral Set Auto-disable_ mode 0::auto_disable_close: when TC reach zero the channel is not automatically released. 1::auto_disable_open: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. Set Auto-disable_ mode 0:: auto_dis_mode0: when TC reach zero the channel is not automatically released. 1:: auto_dis_mode1: At the end of the transfer when TC reach zero the channel is automatically disable_d. the current channel is released. Read FIFO data exchange high 8-bit and low 8-bit. 0:: Exchange 1:: No_exchange bit type is changed from wrc to rc. Channel Disable, write one in this bit disable_ the channel. When writing one in this bit, the current AHB transfer and current APB transfer (if one in progress) is completed and the channel is then disable_d. bit type is changed from wrc to rc. Channel Enable, write one in this bit eNoneble the channel. When the channel is eNonebled, for a peripheral to memory transfer the DMA wait request from peripheral to start transfer. The internal channel fifo is empty Enable bit, when '1' the channel is running AHB Address. This field represent the start address of the transfer. For a 32-bit peripheral, this address must be aligned 32-bit. Transfer Count, this field indicated the transfer size_ in bytes to perform. During a transfer a write in this register add the new value to the current TC. A read of this register return the current current transfer count. indicates the counter decreasing to 0. indicates clock source, 0 is reference clock, 1 is mcu clk. interrupte enable systick counter enable the value to load into cvr when counter decreases to 0. the current cvr value. indicates whether ref clk is implemented. 0 means implemented. indicates whether 10ms calibration value is exact. calibration value of the reload value to be used for 10ms timing clear the interrupte. address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc address to be trapped. Range 0x00000000~0x0003fffc trap enable for 32 channels base address to trapped to. Should be 32 words aligned (such as 0x00053e80 or 0x0004ff00).For the nth patch, the actual address is trap_out_base+4n Length of a break, in number of bits. Allow to stop the data receiving when an error is detected (framing, parity or break). The data in the fifo are kept. When set, data on the Uart_Tx line is held high, while the serial output is looped back to the serial input line, internally. In this mode all the interrupts are fully functional. This feature is used for diagnostic purposes. Also, in loop back mode, the modem control input Uart_CTS is disconnected and the modem control output Uart_RTS are looped back to the inputs, internally. In IrDA mode, Uart_Tx signal is inverted (see IrDA SIR Mode Support). Enables the auto flow control. Uart_RTS is controlled by the Rx RTS bit and the UART Auto Control Flow System. If Uart_CTS become inactive high, the Tx data flow is stopped. 1::ENABLE 0:: DISABLE Enables the DMA signaling for the Uart_Dma_Tx_Req_H and Uart_Dma_Rx_Req_H to the IFC. 0:: DISABLE 1::ENABLE When set, the UART is in IrDA mode and the baud rate divisor used is 16 (see UART Operation for details). Selects the divisor value used to generate the baud rate frequency (BCLK) from the SCLK (see UART Operation for details). If IrDA is enable, this bit is ignored and the divisor used will be 16. 0 = (BCLK = SCLK / 4) 1 = (BCLK = SCLK / 16) 0:div_4 1:div_16 Controls the parity format when parity is enabled: 0::odd: an odd number of received 1 bits is checked, or transmitted (the parity bit is included). 1::even: an even number of received 1 bits is checked or transmitted (the parity bit is included). 2::space: space a space is generated and received as parity bit. 3::mark: a mark is generated and received as parity bit. Parity is enabled when this bit is set. 0::NO 1:: YES Stop bits controls the number of stop bits transmitted. Can receive with one stop bit (more inaccuracy can be compensated with two stop bits when divisor mode is set to 0). 0::1_bit :one stop bit is transmitted in the serial data. 1:: 2_bits:two stop bits are generated and transmitted in the serial data out. Number of data bits per character (least significant bit first): 0::7_bits 1::8_bits Allows to turn off the UART: 0:: Disable 1::Enable This bit is set when Uart Clk has been enabled and received by UART after Need Uart Clock becomes active. It serves to avoid enabling RTS too early. Current value of the DTR line. current value of the Uart_CTS line. 1::Tx_allow_n:Tx not allowed. 0::Tx_alllow:Tx allowed. This bit is set when the Uart_CTS line changed since the last time this register has been written. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever the serial input is held in a logic 0 state for longer than the length of x bits, where x is the value programmed Rx Break Length. A null word will be written in the Rx Fifo. This bit is cleared when the UART_STATUS register is written with any value. This bit is set whenever there is a framing error occured. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit is set if the parity is enabled and a parity error occurred in the received data. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the user tried to write a character when fifo was already full. The written data will not be kept. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the receiver received a new character when the fifo was already full. The new character is discarded. This bit is cleared when the UART_STATUS register is written with any value. This bit indicates that the UART is receiving a byte. This bit indicates that the UART is sending data. If no data is in the fifo, the UART is currently sending the last one through the serial interface. Those bits indicate the number of space available in the Tx Fifo. Those bits indicate the number of data available in the Rx Fifo. Those data can be read. The UART_TRANSMIT_HOLDING register is a write-only register that contains data to be transmitted on the serial output port. 16 characters of data may be written to the UART_TRANSMIT_HOLDING register before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Falling edge detected on the UART_DTR signal. Rising edge detected on the UART_DTR signal. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. Pulse detected on Uart_Dma_Rx_Done_H signal Pulse detected on Uart_Dma_Tx_Done_H signal. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Clear to send signal change detected. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. Same as previous, not masked. This interrupt is generated when a falling edge is detected on the UART_DTR signal. Reset control: Write one in this register. This interrupt is generated when a rising edge is detected on the UART_DTR signal. Reset control: Write one in this register. In DMA mode, there is at least 1 character that has been read in or out the Rx Fifo. Then before received Rx DMA Done, No characters in or out of the Rx Fifo during the last 4 character times. This interrupt is generated when a pulse is detected on the Uart_Dma_Rx_Done_H signal. Reset control: Write one in this register. This interrupt is generated when a pulse is detected on the Uart_Dma_Tx_Done_H signal. Reset control: Write one in this register. Tx Overflow, Rx Overflow, Parity Error, Framing Error or Break Interrupt. Reset control: This bit is cleared when the UART_STATUS register is written with any value. No characters in or out of the Rx Fifo during the last 4 character times and there is at least 1 character in it during this time. Reset control: Reading from the UART_RECEIVE_BUFFER register. Tx Fifo at or below threshold level (current level <= Tx Fifo trigger level). Reset control: Writing into UART_TRANSMIT_HOLDING register above threshold level. Rx Fifo at or upper threshold level (current level >= Rx Fifo trigger level). Reset control: Reading the UART_RECEIVE_BUFFER until the Fifo drops below the trigger level. Clear to send signal detected. Reset control: This bit is cleared when the UART_STATUS register is written with any value. Controls the Rx Fifo level at which the Uart_RTS Auto Flow Control will be set inactive high (see UART Operation for more details on AFC). The Uart_RTS Auto Flow Control will be set inactive high when quantity of data in Rx Fifo > AFC Level. Defines the empty threshold level at which the Data Needed Interrupt will be generated. The Data Needed Interrupt is generated when quantity of data in Tx Fifo <= Tx Trigger. Defines the empty threshold level at which the Data Available Interrupt will be generated. The Data Available interrupt is generated when quantity of data in Rx Fifo > Rx Trigger. Writing a 1 to this bit resets and flushes the Transmit Fifo. This bit does not need to be cleared. Writing a 1 to this bit resets and flushes the Receive Fifo. This bit does not need to be cleared. bit type is changed from w1s to rs. this bit is set to 1 when writing 1, cleared to 0 when corresponding filed is cleared in UART_CMD_CLR bit type is changed from w1s to rs. refer to bit [5] bit type is changed from w1s to rs. refer to bit [5] bit type is changed from w1s to rs. refer to bit [5] bit type is changed from w1s to rs. refer to bit [5] bit type is changed from w1s to rs. refer to bit [5] bit type is changed from w1c to rc. this bit is cleared to 0 when writing 1, set to 1 when corresponding filed is set in UART_CMD_SET bit type is changed from w1c to rc. refer to bit [5] bit type is changed from w1c to rc. refer to bit [5] bit type is changed from w1c to rc. refer to bit [5] bit type is changed from w1c to rc. refer to bit [5] bit type is changed from w1c to rc. refer to bit [5] wdt_cvr0_count_value_0 wdt_cvr1_count_value_1 0: enalbe, 1: disable Ap APB base System AHB base PSRAM base PSRAM base ADI mst base System AON APB base COREISHGT Base BB_SYS ADDR base ZSP_SYS ADDR base GGE_BB_APB ADDR base GGE_SYS_APB ADDR base RF_APB ADDR base WCN SYS APB ADDR base