/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _CP_GLB_H_ #define _CP_GLB_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_CP_GLB_SET_OFFSET (1024) #define REG_CP_GLB_CLR_OFFSET (2048) #define REG_CP_GLB_BASE (0x120c0000) typedef volatile struct { uint32_t sysctrl00; // 0x00000000 uint32_t sysctrl01; // 0x00000004 uint32_t sysctrl02; // 0x00000008 uint32_t sysctrl03; // 0x0000000c uint32_t sysctrl04; // 0x00000010 uint32_t sysctrl05; // 0x00000014 uint32_t sysctrl06; // 0x00000018 uint32_t sysctrl07; // 0x0000001c uint32_t sysctrl08; // 0x00000020 uint32_t sysctrl09; // 0x00000024 uint32_t sysctrl10; // 0x00000028 uint32_t sysctrl11; // 0x0000002c uint32_t sysctrl12; // 0x00000030 uint32_t sysctrl13; // 0x00000034 uint32_t sysctrl14; // 0x00000038 uint32_t sysctrl15; // 0x0000003c uint32_t sysctrl16; // 0x00000040 uint32_t sysctrl17; // 0x00000044 uint32_t sysctrl18; // 0x00000048 uint32_t sysctrl19; // 0x0000004c uint32_t sysctrl20; // 0x00000050 uint32_t sysctrl21; // 0x00000054 uint32_t sysctrl22; // 0x00000058 uint32_t sysstat01; // 0x0000005c uint32_t sysstat02; // 0x00000060 uint32_t sysstat03; // 0x00000064 uint32_t sysstat04; // 0x00000068 uint32_t sysstat05; // 0x0000006c uint32_t sysstat06; // 0x00000070 uint32_t sysstat07; // 0x00000074 uint32_t sysstat08; // 0x00000078 uint32_t sysctrl23; // 0x0000007c uint32_t sysctrl24; // 0x00000080 uint32_t sysctrl25; // 0x00000084 uint32_t sysctrl26; // 0x00000088 uint32_t sysctrl27; // 0x0000008c uint32_t sysctrl28; // 0x00000090 uint32_t sysstat09; // 0x00000094 uint32_t sysctrl29; // 0x00000098 uint32_t sysctrl30; // 0x0000009c uint32_t sysstat10; // 0x000000a0 uint32_t sysstat11; // 0x000000a4 uint32_t sysstat12; // 0x000000a8 uint32_t sysstat13; // 0x000000ac uint32_t sysstat14; // 0x000000b0 uint32_t sysstat15; // 0x000000b4 uint32_t sysstat16; // 0x000000b8 uint32_t sysstat17; // 0x000000bc uint32_t sysstat18; // 0x000000c0 uint32_t sysstat19; // 0x000000c4 uint32_t __200[206]; // 0x000000c8 uint32_t sysctrl00_set; // 0x00000400 uint32_t __1028[2]; // 0x00000404 uint32_t sysctrl03_set; // 0x0000040c uint32_t __1040[12]; // 0x00000410 uint32_t sysctrl16_set; // 0x00000440 uint32_t sysctrl17_set; // 0x00000444 uint32_t sysctrl18_set; // 0x00000448 uint32_t sysctrl19_set; // 0x0000044c uint32_t sysctrl20_set; // 0x00000450 uint32_t sysctrl21_set; // 0x00000454 uint32_t sysctrl22_set; // 0x00000458 uint32_t __1116[8]; // 0x0000045c uint32_t sysctrl23_set; // 0x0000047c uint32_t sysctrl24_set; // 0x00000480 uint32_t sysctrl25_set; // 0x00000484 uint32_t sysctrl26_set; // 0x00000488 uint32_t sysctrl27_set; // 0x0000048c uint32_t sysctrl28_set; // 0x00000490 uint32_t __1172[219]; // 0x00000494 uint32_t sysctrl00_clr; // 0x00000800 uint32_t __2052[2]; // 0x00000804 uint32_t sysctrl03_clr; // 0x0000080c uint32_t __2064[12]; // 0x00000810 uint32_t sysctrl16_clr; // 0x00000840 uint32_t sysctrl17_clr; // 0x00000844 uint32_t sysctrl18_clr; // 0x00000848 uint32_t sysctrl19_clr; // 0x0000084c uint32_t sysctrl20_clr; // 0x00000850 uint32_t sysctrl21_clr; // 0x00000854 uint32_t sysctrl22_clr; // 0x00000858 uint32_t __2140[8]; // 0x0000085c uint32_t sysctrl23_clr; // 0x0000087c uint32_t sysctrl24_clr; // 0x00000880 uint32_t sysctrl25_clr; // 0x00000884 uint32_t sysctrl26_clr; // 0x00000888 uint32_t sysctrl27_clr; // 0x0000088c uint32_t sysctrl28_clr; // 0x00000890 } HWP_CP_GLB_T; #define hwp_cpGlb ((HWP_CP_GLB_T *)REG_ACCESS_ADDRESS(REG_CP_GLB_BASE)) // sysctrl00 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t rg_cp2aon_xhb400_awsparse : 1; // [3] uint32_t __6_4 : 3; // [6:4] uint32_t rg_cp2gnss_xhb400_awsparse : 1; // [7] uint32_t rg_aon2cp_nonbuf_early_resp_en : 1; // [8] uint32_t rg_aon2cp_mclk_auto_gate_en : 1; // [9] uint32_t rg_aon2cp_sclk_auto_gate_en : 1; // [10] uint32_t rg_tsx_nonbuf_early_resp_en : 1; // [11] uint32_t rg_tsx_mclk_auto_gate_en : 1; // [12] uint32_t rg_tsx_sclk_auto_gate_en : 1; // [13] uint32_t rg_cp_ahb_xhb400_awsparse : 1; // [14] uint32_t rg_ifc2cp_nonbuf_early_resp_en : 1; // [15] uint32_t rg_ifc2cp_clk_auto_gate_en : 1; // [16] uint32_t __17_17 : 1; // [17] uint32_t slv_disable_req_cp_gnss_force : 1; // [18] uint32_t slv_disable_req_cp_psram_sel : 1; // [19] uint32_t slv_disable_req_cp_psram_force : 1; // [20] uint32_t slv_disable_req_cp_ltedma_sel : 1; // [21] uint32_t slv_disable_req_cp_ltedma_force : 1; // [22] uint32_t slv_disable_req_cp_ltecpu_sel : 1; // [23] uint32_t slv_disable_req_cp_ltecpu_force : 1; // [24] uint32_t __31_25 : 7; // [31:25] } b; } REG_CP_GLB_SYSCTRL00_T; // sysctrl01 typedef union { uint32_t v; struct { uint32_t awqos_cp_a5 : 4; // [3:0] uint32_t arqos_cp_a5 : 4; // [7:4] uint32_t awqos_f8 : 4; // [11:8] uint32_t arqos_f8 : 4; // [15:12] uint32_t awqos_axidma : 4; // [19:16] uint32_t arqos_axidma : 4; // [23:20] uint32_t awqos_cp_ifc : 4; // [27:24] uint32_t arqos_cp_ifc : 4; // [31:28] } b; } REG_CP_GLB_SYSCTRL01_T; // sysctrl02 typedef union { uint32_t v; struct { uint32_t awqos_aon_m : 4; // [3:0] uint32_t arqos_aon_m : 4; // [7:4] uint32_t awqos_lte_cpu : 4; // [11:8] uint32_t arqos_lte_cpu : 4; // [15:12] uint32_t awqos_lte_dma : 4; // [19:16] uint32_t arqos_lte_dma : 4; // [23:20] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL02_T; // sysctrl03 typedef union { uint32_t v; struct { uint32_t lp_eb_m0 : 1; // [0] uint32_t lp_eb_m1 : 1; // [1] uint32_t lp_eb_m2 : 1; // [2] uint32_t lp_eb_m3 : 1; // [3] uint32_t lp_eb_m4 : 1; // [4] uint32_t lp_eb_main : 1; // [5] uint32_t lp_eb_s0 : 1; // [6] uint32_t lp_eb_s1 : 1; // [7] uint32_t lp_eb_s2 : 1; // [8] uint32_t lp_eb_s3 : 1; // [9] uint32_t lp_eb_s4 : 1; // [10] uint32_t lp_eb_s5 : 1; // [11] uint32_t lp_eb_s6 : 1; // [12] uint32_t lp_force_m0 : 1; // [13] uint32_t lp_force_m1 : 1; // [14] uint32_t lp_force_m2 : 1; // [15] uint32_t lp_force_m3 : 1; // [16] uint32_t lp_force_m4 : 1; // [17] uint32_t lp_force_main : 1; // [18] uint32_t lp_force_s0 : 1; // [19] uint32_t lp_force_s1 : 1; // [20] uint32_t lp_force_s2 : 1; // [21] uint32_t lp_force_s3 : 1; // [22] uint32_t lp_force_s4 : 1; // [23] uint32_t lp_force_s5 : 1; // [24] uint32_t lp_force_s6 : 1; // [25] uint32_t lpc_main_early_wakeup_bypass : 1; // [26] uint32_t __31_27 : 5; // [31:27] } b; } REG_CP_GLB_SYSCTRL03_T; // sysctrl04 typedef union { uint32_t v; struct { uint32_t lp_num_m0 : 16; // [15:0] uint32_t pu_num_m0 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL04_T; // sysctrl05 typedef union { uint32_t v; struct { uint32_t lp_num_m1 : 16; // [15:0] uint32_t pu_num_m1 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL05_T; // sysctrl06 typedef union { uint32_t v; struct { uint32_t lp_num_m2 : 16; // [15:0] uint32_t pu_num_m2 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL06_T; // sysctrl07 typedef union { uint32_t v; struct { uint32_t lp_num_m3 : 16; // [15:0] uint32_t pu_num_m3 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL07_T; // sysctrl08 typedef union { uint32_t v; struct { uint32_t lp_num_m4 : 16; // [15:0] uint32_t pu_num_m4 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL08_T; // sysctrl09 typedef union { uint32_t v; struct { uint32_t lp_num_s0 : 16; // [15:0] uint32_t pu_num_s0 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL09_T; // sysctrl10 typedef union { uint32_t v; struct { uint32_t lp_num_s1 : 16; // [15:0] uint32_t pu_num_s1 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL10_T; // sysctrl11 typedef union { uint32_t v; struct { uint32_t lp_num_s2 : 16; // [15:0] uint32_t pu_num_s2 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL11_T; // sysctrl12 typedef union { uint32_t v; struct { uint32_t lp_num_s3 : 16; // [15:0] uint32_t pu_num_s3 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL12_T; // sysctrl13 typedef union { uint32_t v; struct { uint32_t lp_num_s4 : 16; // [15:0] uint32_t pu_num_s4 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL13_T; // sysctrl14 typedef union { uint32_t v; struct { uint32_t lp_num_s5 : 16; // [15:0] uint32_t pu_num_s5 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL14_T; // sysctrl15 typedef union { uint32_t v; struct { uint32_t lp_num_s6 : 16; // [15:0] uint32_t pu_num_s6 : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL15_T; // sysctrl16 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t wlan_iq_sync_sel : 1; // [2] uint32_t cp_ifc_hresp_err_mask : 1; // [3] uint32_t cp_a5_resp_err_mask : 1; // [4] uint32_t freq_bias_ch0_en : 1; // [5] uint32_t freq_bias_ch1_en : 1; // [6] uint32_t freq_bias_ch2_en : 1; // [7] uint32_t freq_bias_ch3_en : 1; // [8] uint32_t rg_tsx_clkedge_sel : 1; // [9] uint32_t rg_osc_clkedge_sel : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_CP_GLB_SYSCTRL16_T; // sysctrl17 typedef union { uint32_t v; struct { uint32_t cgm_cp_axi_sel : 3; // [2:0] uint32_t cgm_cp_axi_div : 3; // [5:3] uint32_t cgm_cp_ahb_div : 3; // [8:6] uint32_t cgm_cp_axi_update : 1; // [9] uint32_t cgm_cp_a5_en : 1; // [10] uint32_t cgm_cp_axi_en : 1; // [11] uint32_t cgm_cp_ahb_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_CP_GLB_SYSCTRL17_T; // sysctrl18 typedef union { uint32_t v; struct { uint32_t cp_ahb_irq0_en : 1; // [0] uint32_t cp_ahb_irq1_en : 1; // [1] uint32_t cp_ahb_f8_en : 1; // [2] uint32_t cp_ahb_ch_dbg_en : 1; // [3] uint32_t cp_ahb_ch0_en : 1; // [4] uint32_t cp_ahb_ch1_en : 1; // [5] uint32_t cp_ahb_ch2_en : 1; // [6] uint32_t cp_ahb_ch3_en : 1; // [7] uint32_t cp_ahb_axidma_en : 1; // [8] uint32_t cp_ahb_sysram_conf_en : 1; // [9] uint32_t cp_ahb_timer4_conf_en : 1; // [10] uint32_t cp_ahb_timer4_mod_en : 1; // [11] uint32_t cp_ahb_timer3_conf_en : 1; // [12] uint32_t cp_ahb_timer3_mod_en : 1; // [13] uint32_t cp_ahb_sci1_conf_en : 1; // [14] uint32_t cp_ahb_sci1_mod_en : 1; // [15] uint32_t cp_ahb_sci1_func_en : 1; // [16] uint32_t cp_ahb_sci2_mod_en : 1; // [17] uint32_t cp_ahb_sci2_conf_en : 1; // [18] uint32_t cp_ahb_sci2_func_en : 1; // [19] uint32_t cp_ahb_busmon_func_en : 1; // [20] uint32_t wlan_11b_en : 1; // [21] uint32_t freq_bias_func_en : 1; // [22] uint32_t dap_dap_en : 1; // [23] uint32_t __25_24 : 2; // [25:24] uint32_t cp_apb_ifc_en : 1; // [26] uint32_t cp_ahb_ifc_en : 1; // [27] uint32_t aon2cp_ahb_en : 1; // [28] uint32_t freq_bias_ahb_en : 1; // [29] uint32_t __31_30 : 2; // [31:30] } b; } REG_CP_GLB_SYSCTRL18_T; // sysctrl19 typedef union { uint32_t v; struct { uint32_t cgm_wcn_11b_dfe_en : 1; // [0] uint32_t cgm_timer_26m_en : 1; // [1] uint32_t cgm_wdg_32k_en : 1; // [2] uint32_t cgm_wcn_11b_adc_en : 1; // [3] uint32_t cgm_gnss_tsx_sel : 1; // [4] uint32_t cgm_gnss_tsx_en : 1; // [5] uint32_t cgm_thm_tsx_en : 1; // [6] uint32_t cgm_thm_osc_en : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_CP_GLB_SYSCTRL19_T; // sysctrl20 typedef union { uint32_t v; struct { uint32_t cp_a5_soft_rst : 1; // [0] uint32_t cp_a5cs_soft_rst : 1; // [1] uint32_t cp_a5dbg_soft_rst : 1; // [2] uint32_t cp_irq1_soft_rst : 1; // [3] uint32_t cp_irq0_soft_rst : 1; // [4] uint32_t cp_timer3_soft_rst : 1; // [5] uint32_t cp_imem_apb_soft_rst : 1; // [6] uint32_t cp_imem_axi_soft_rst : 1; // [7] uint32_t cp_axidma_soft_rst : 1; // [8] uint32_t cp_f8_soft_rst : 1; // [9] uint32_t cp_wlan_soft_rst : 1; // [10] uint32_t cp_busmon_m4_soft_rst : 1; // [11] uint32_t cp_busmon_m3_soft_rst : 1; // [12] uint32_t cp_busmon_m2_soft_rst : 1; // [13] uint32_t cp_busmon_m1_soft_rst : 1; // [14] uint32_t cp_busmon_m0_soft_rst : 1; // [15] uint32_t cp_bsumon_apb_soft_rst : 1; // [16] uint32_t cp_sci2_soft_rst : 1; // [17] uint32_t cp_sci1_soft_rst : 1; // [18] uint32_t cp_timer4_soft_rst : 1; // [19] uint32_t aon2cp_soft_rst : 1; // [20] uint32_t cp2gnss_soft_rst : 1; // [21] uint32_t cp2aon_soft_rst : 1; // [22] uint32_t cp_ltecpu_async_soft_rst : 1; // [23] uint32_t cp_ltedma_async_soft_rst : 1; // [24] uint32_t cp_psram_async_soft_rst : 1; // [25] uint32_t tsx_ab_soft_rst : 1; // [26] uint32_t tsx_ip_soft_rst : 1; // [27] uint32_t __31_28 : 4; // [31:28] } b; } REG_CP_GLB_SYSCTRL20_T; // sysctrl21 typedef union { uint32_t v; struct { uint32_t cp_ifc_ch_dbg_auto_gate_en : 1; // [0] uint32_t cp_ifc_ch0_auto_gate_en : 1; // [1] uint32_t cp_ifc_ch1_auto_gate_en : 1; // [2] uint32_t cp_ifc_ch2_auto_gate_en : 1; // [3] uint32_t cp_ifc_ch3_auto_gate_en : 1; // [4] uint32_t cp_ifc_auto_gate_en : 1; // [5] uint32_t cp_sci1_auto_gate_en : 1; // [6] uint32_t cp_sci2_auto_gate_en : 1; // [7] uint32_t aon2cp_ahb_auto_gate_en : 1; // [8] uint32_t ifc2cp_ahb_auto_gate_en : 1; // [9] uint32_t __11_10 : 2; // [11:10] uint32_t cp2freq_ahb_auto_gate_en : 1; // [12] uint32_t cp_a5_auto_gate_en : 1; // [13] uint32_t cp_axi_auto_gate_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_CP_GLB_SYSCTRL21_T; // sysctrl22 typedef union { uint32_t v; struct { uint32_t cp_apbreg_soft_rst : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_CP_GLB_SYSCTRL22_T; // sysstat04 typedef union { uint32_t v; struct { uint32_t axi_detector_overflow_cp_psram : 1; // [0], read only uint32_t pwr_handshk_clk_req_cp_psram : 1; // [1], read only uint32_t bridge_trans_idle_cp_psram : 1; // [2], read only uint32_t axi_detector_overflow_cp_ltedma : 1; // [3], read only uint32_t pwr_handshk_clk_req_cp_ltedma : 1; // [4], read only uint32_t bridge_trans_idle_cp_ltedma : 1; // [5], read only uint32_t axi_detector_overflow_cp_ltecpu : 1; // [6], read only uint32_t pwr_handshk_clk_req_cp_ltecpu : 1; // [7], read only uint32_t bridge_trans_idle_cp_ltecpu : 1; // [8], read only uint32_t __31_9 : 23; // [31:9] } b; } REG_CP_GLB_SYSSTAT04_T; // sysstat05 typedef union { uint32_t v; struct { uint32_t lp_stat_m0 : 1; // [0], read only uint32_t lp_stat_m1 : 1; // [1], read only uint32_t lp_stat_m2 : 1; // [2], read only uint32_t lp_stat_m3 : 1; // [3], read only uint32_t lp_stat_m4 : 1; // [4], read only uint32_t lp_stat_main : 1; // [5], read only uint32_t lp_stat_s0 : 1; // [6], read only uint32_t lp_stat_s1 : 1; // [7], read only uint32_t lp_stat_s2 : 1; // [8], read only uint32_t lp_stat_s3 : 1; // [9], read only uint32_t lp_stat_s4 : 1; // [10], read only uint32_t lp_stat_s5 : 1; // [11], read only uint32_t lp_stat_s6 : 1; // [12], read only uint32_t cgm_busy_lpc_m0 : 1; // [13], read only uint32_t cgm_busy_lpc_m1 : 1; // [14], read only uint32_t cgm_busy_lpc_m2 : 1; // [15], read only uint32_t cgm_busy_lpc_m3 : 1; // [16], read only uint32_t cgm_busy_lpc_m4 : 1; // [17], read only uint32_t cgm_busy_lpc_main : 1; // [18], read only uint32_t cgm_busy_lpc_s0 : 1; // [19], read only uint32_t cgm_busy_lpc_s1 : 1; // [20], read only uint32_t cgm_busy_lpc_s2 : 1; // [21], read only uint32_t cgm_busy_lpc_s3 : 1; // [22], read only uint32_t cgm_busy_lpc_s4 : 1; // [23], read only uint32_t cgm_busy_lpc_s5 : 1; // [24], read only uint32_t cgm_busy_lpc_s6 : 1; // [25], read only uint32_t cp_light_stop : 1; // [26], read only uint32_t cp_slp_ack : 1; // [27], read only uint32_t all_master_force_slp : 1; // [28], read only uint32_t all_slave_force_slp : 1; // [29], read only uint32_t __31_30 : 2; // [31:30] } b; } REG_CP_GLB_SYSSTAT05_T; // sysstat06 typedef union { uint32_t v; struct { uint32_t force_ack_m0 : 1; // [0], read only uint32_t force_ack_m1 : 1; // [1], read only uint32_t force_ack_m2 : 1; // [2], read only uint32_t force_ack_m3 : 1; // [3], read only uint32_t force_ack_m4 : 1; // [4], read only uint32_t force_ack_main : 1; // [5], read only uint32_t force_ack_s0 : 1; // [6], read only uint32_t force_ack_s1 : 1; // [7], read only uint32_t force_ack_s2 : 1; // [8], read only uint32_t force_ack_s3 : 1; // [9], read only uint32_t force_ack_s4 : 1; // [10], read only uint32_t force_ack_s5 : 1; // [11], read only uint32_t force_ack_s6 : 1; // [12], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_CP_GLB_SYSSTAT06_T; // sysstat07 typedef union { uint32_t v; struct { uint32_t busmon0_lock : 1; // [0], read only uint32_t busmon1_lock : 1; // [1], read only uint32_t busmon2_lock : 1; // [2], read only uint32_t busmon3_lock : 1; // [3], read only uint32_t busmon4_lock : 1; // [4], read only uint32_t busmon_rbusy0 : 1; // [5], read only uint32_t busmon_wbusy0 : 1; // [6], read only uint32_t busmon_busy0 : 1; // [7], read only uint32_t busmon_rbusy1 : 1; // [8], read only uint32_t busmon_wbusy1 : 1; // [9], read only uint32_t busmon_busy1 : 1; // [10], read only uint32_t busmon_rbusy2 : 1; // [11], read only uint32_t busmon_wbusy2 : 1; // [12], read only uint32_t busmon_busy2 : 1; // [13], read only uint32_t busmon_rbusy3 : 1; // [14], read only uint32_t busmon_wbusy3 : 1; // [15], read only uint32_t busmon_busy3 : 1; // [16], read only uint32_t busmon_rbusy4 : 1; // [17], read only uint32_t busmon_wbusy4 : 1; // [18], read only uint32_t busmon_busy4 : 1; // [19], read only uint32_t cp_dbg_monitor : 8; // [27:20], read only uint32_t __31_28 : 4; // [31:28] } b; } REG_CP_GLB_SYSSTAT07_T; // sysctrl28 typedef union { uint32_t v; struct { uint32_t core_int_disable : 1; // [0] uint32_t cp_light_stop_en : 1; // [1] uint32_t light_bypass_m0_lpc : 1; // [2] uint32_t light_bypass_m1_lpc : 1; // [3] uint32_t light_bypass_m2_lpc : 1; // [4] uint32_t light_bypass_m3_lpc : 1; // [5] uint32_t light_bypass_m4_lpc : 1; // [6] uint32_t light_bypass_main_lpc : 1; // [7] uint32_t light_bypass_m0 : 1; // [8] uint32_t light_bypass_m1 : 1; // [9] uint32_t light_bypass_m2 : 1; // [10] uint32_t light_bypass_m3 : 1; // [11] uint32_t light_bypass_m4 : 1; // [12] uint32_t light_bypass_s0 : 1; // [13] uint32_t light_bypass_s1 : 1; // [14] uint32_t light_bypass_s2 : 1; // [15] uint32_t light_bypass_s3 : 1; // [16] uint32_t light_bypass_s4 : 1; // [17] uint32_t light_bypass_s5 : 1; // [18] uint32_t light_bypass_s6 : 1; // [19] uint32_t light_bypass_sci1 : 1; // [20] uint32_t light_bypass_sci2 : 1; // [21] uint32_t light_bypass_timer3 : 1; // [22] uint32_t light_bypass_timer4 : 1; // [23] uint32_t light_bypass_wlan : 1; // [24] uint32_t core_stop_bypass : 1; // [25] uint32_t __31_26 : 6; // [31:26] } b; } REG_CP_GLB_SYSCTRL28_T; // sysstat09 typedef union { uint32_t v; struct { uint32_t dc_est_i : 15; // [14:0], read only uint32_t set_dc : 1; // [15], read only uint32_t dc_est_q : 15; // [30:16], read only uint32_t reset_dc : 1; // [31], read only } b; } REG_CP_GLB_SYSSTAT09_T; // sysctrl29 typedef union { uint32_t v; struct { uint32_t lp_num_main : 16; // [15:0] uint32_t pu_num_main : 8; // [23:16] uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSCTRL29_T; // sysctrl30 typedef union { uint32_t v; struct { uint32_t cp_latch_bitmap : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_CP_GLB_SYSCTRL30_T; // sysstat10 typedef union { uint32_t v; struct { uint32_t latch_cnt_122m88_value_l : 16; // [15:0], read only uint32_t latch_cnt_122m88_value_m : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT10_T; // sysstat11 typedef union { uint32_t v; struct { uint32_t latch_cnt_122m88_value_h : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_wptr : 8; // [23:16], read only uint32_t __31_24 : 8; // [31:24] } b; } REG_CP_GLB_SYSSTAT11_T; // sysstat12 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num0 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num1 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT12_T; // sysstat13 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num2 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num3 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT13_T; // sysstat14 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num4 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num5 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT14_T; // sysstat15 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num6 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num7 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT15_T; // sysstat16 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num8 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num9 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT16_T; // sysstat17 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num10 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num11 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT17_T; // sysstat18 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num12 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num13 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT18_T; // sysstat19 typedef union { uint32_t v; struct { uint32_t latch_bitmap_cycle_index_num14 : 16; // [15:0], read only uint32_t latch_bitmap_cycle_index_num15 : 16; // [31:16], read only } b; } REG_CP_GLB_SYSSTAT19_T; // sysctrl00 #define CP_GLB_RG_CP2AON_XHB400_AWSPARSE (1 << 3) #define CP_GLB_RG_CP2GNSS_XHB400_AWSPARSE (1 << 7) #define CP_GLB_RG_AON2CP_NONBUF_EARLY_RESP_EN (1 << 8) #define CP_GLB_RG_AON2CP_MCLK_AUTO_GATE_EN (1 << 9) #define CP_GLB_RG_AON2CP_SCLK_AUTO_GATE_EN (1 << 10) #define CP_GLB_RG_TSX_NONBUF_EARLY_RESP_EN (1 << 11) #define CP_GLB_RG_TSX_MCLK_AUTO_GATE_EN (1 << 12) #define CP_GLB_RG_TSX_SCLK_AUTO_GATE_EN (1 << 13) #define CP_GLB_RG_CP_AHB_XHB400_AWSPARSE (1 << 14) #define CP_GLB_RG_IFC2CP_NONBUF_EARLY_RESP_EN (1 << 15) #define CP_GLB_RG_IFC2CP_CLK_AUTO_GATE_EN (1 << 16) #define CP_GLB_SLV_DISABLE_REQ_CP_GNSS_FORCE (1 << 18) #define CP_GLB_SLV_DISABLE_REQ_CP_PSRAM_SEL (1 << 19) #define CP_GLB_SLV_DISABLE_REQ_CP_PSRAM_FORCE (1 << 20) #define CP_GLB_SLV_DISABLE_REQ_CP_LTEDMA_SEL (1 << 21) #define CP_GLB_SLV_DISABLE_REQ_CP_LTEDMA_FORCE (1 << 22) #define CP_GLB_SLV_DISABLE_REQ_CP_LTECPU_SEL (1 << 23) #define CP_GLB_SLV_DISABLE_REQ_CP_LTECPU_FORCE (1 << 24) // sysctrl01 #define CP_GLB_AWQOS_CP_A5(n) (((n)&0xf) << 0) #define CP_GLB_ARQOS_CP_A5(n) (((n)&0xf) << 4) #define CP_GLB_AWQOS_F8(n) (((n)&0xf) << 8) #define CP_GLB_ARQOS_F8(n) (((n)&0xf) << 12) #define CP_GLB_AWQOS_AXIDMA(n) (((n)&0xf) << 16) #define CP_GLB_ARQOS_AXIDMA(n) (((n)&0xf) << 20) #define CP_GLB_AWQOS_CP_IFC(n) (((n)&0xf) << 24) #define CP_GLB_ARQOS_CP_IFC(n) (((n)&0xf) << 28) // sysctrl02 #define CP_GLB_AWQOS_AON_M(n) (((n)&0xf) << 0) #define CP_GLB_ARQOS_AON_M(n) (((n)&0xf) << 4) #define CP_GLB_AWQOS_LTE_CPU(n) (((n)&0xf) << 8) #define CP_GLB_ARQOS_LTE_CPU(n) (((n)&0xf) << 12) #define CP_GLB_AWQOS_LTE_DMA(n) (((n)&0xf) << 16) #define CP_GLB_ARQOS_LTE_DMA(n) (((n)&0xf) << 20) // sysctrl03 #define CP_GLB_LP_EB_M0 (1 << 0) #define CP_GLB_LP_EB_M1 (1 << 1) #define CP_GLB_LP_EB_M2 (1 << 2) #define CP_GLB_LP_EB_M3 (1 << 3) #define CP_GLB_LP_EB_M4 (1 << 4) #define CP_GLB_LP_EB_MAIN (1 << 5) #define CP_GLB_LP_EB_S0 (1 << 6) #define CP_GLB_LP_EB_S1 (1 << 7) #define CP_GLB_LP_EB_S2 (1 << 8) #define CP_GLB_LP_EB_S3 (1 << 9) #define CP_GLB_LP_EB_S4 (1 << 10) #define CP_GLB_LP_EB_S5 (1 << 11) #define CP_GLB_LP_EB_S6 (1 << 12) #define CP_GLB_LP_FORCE_M0 (1 << 13) #define CP_GLB_LP_FORCE_M1 (1 << 14) #define CP_GLB_LP_FORCE_M2 (1 << 15) #define CP_GLB_LP_FORCE_M3 (1 << 16) #define CP_GLB_LP_FORCE_M4 (1 << 17) #define CP_GLB_LP_FORCE_MAIN (1 << 18) #define CP_GLB_LP_FORCE_S0 (1 << 19) #define CP_GLB_LP_FORCE_S1 (1 << 20) #define CP_GLB_LP_FORCE_S2 (1 << 21) #define CP_GLB_LP_FORCE_S3 (1 << 22) #define CP_GLB_LP_FORCE_S4 (1 << 23) #define CP_GLB_LP_FORCE_S5 (1 << 24) #define CP_GLB_LP_FORCE_S6 (1 << 25) #define CP_GLB_LPC_MAIN_EARLY_WAKEUP_BYPASS (1 << 26) // sysctrl04 #define CP_GLB_LP_NUM_M0(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_M0(n) (((n)&0xff) << 16) // sysctrl05 #define CP_GLB_LP_NUM_M1(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_M1(n) (((n)&0xff) << 16) // sysctrl06 #define CP_GLB_LP_NUM_M2(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_M2(n) (((n)&0xff) << 16) // sysctrl07 #define CP_GLB_LP_NUM_M3(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_M3(n) (((n)&0xff) << 16) // sysctrl08 #define CP_GLB_LP_NUM_M4(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_M4(n) (((n)&0xff) << 16) // sysctrl09 #define CP_GLB_LP_NUM_S0(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S0(n) (((n)&0xff) << 16) // sysctrl10 #define CP_GLB_LP_NUM_S1(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S1(n) (((n)&0xff) << 16) // sysctrl11 #define CP_GLB_LP_NUM_S2(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S2(n) (((n)&0xff) << 16) // sysctrl12 #define CP_GLB_LP_NUM_S3(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S3(n) (((n)&0xff) << 16) // sysctrl13 #define CP_GLB_LP_NUM_S4(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S4(n) (((n)&0xff) << 16) // sysctrl14 #define CP_GLB_LP_NUM_S5(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S5(n) (((n)&0xff) << 16) // sysctrl15 #define CP_GLB_LP_NUM_S6(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_S6(n) (((n)&0xff) << 16) // sysctrl16 #define CP_GLB_WLAN_IQ_SYNC_SEL (1 << 2) #define CP_GLB_CP_IFC_HRESP_ERR_MASK (1 << 3) #define CP_GLB_CP_A5_RESP_ERR_MASK (1 << 4) #define CP_GLB_FREQ_BIAS_CH0_EN (1 << 5) #define CP_GLB_FREQ_BIAS_CH1_EN (1 << 6) #define CP_GLB_FREQ_BIAS_CH2_EN (1 << 7) #define CP_GLB_FREQ_BIAS_CH3_EN (1 << 8) #define CP_GLB_RG_TSX_CLKEDGE_SEL (1 << 9) #define CP_GLB_RG_OSC_CLKEDGE_SEL (1 << 10) // sysctrl17 #define CP_GLB_CGM_CP_AXI_SEL(n) (((n)&0x7) << 0) #define CP_GLB_CGM_CP_AXI_DIV(n) (((n)&0x7) << 3) #define CP_GLB_CGM_CP_AHB_DIV(n) (((n)&0x7) << 6) #define CP_GLB_CGM_CP_AXI_UPDATE (1 << 9) #define CP_GLB_CGM_CP_A5_EN (1 << 10) #define CP_GLB_CGM_CP_AXI_EN (1 << 11) #define CP_GLB_CGM_CP_AHB_EN (1 << 12) // sysctrl18 #define CP_GLB_CP_AHB_IRQ0_EN (1 << 0) #define CP_GLB_CP_AHB_IRQ1_EN (1 << 1) #define CP_GLB_CP_AHB_F8_EN (1 << 2) #define CP_GLB_CP_AHB_CH_DBG_EN (1 << 3) #define CP_GLB_CP_AHB_CH0_EN (1 << 4) #define CP_GLB_CP_AHB_CH1_EN (1 << 5) #define CP_GLB_CP_AHB_CH2_EN (1 << 6) #define CP_GLB_CP_AHB_CH3_EN (1 << 7) #define CP_GLB_CP_AHB_AXIDMA_EN (1 << 8) #define CP_GLB_CP_AHB_SYSRAM_CONF_EN (1 << 9) #define CP_GLB_CP_AHB_TIMER4_CONF_EN (1 << 10) #define CP_GLB_CP_AHB_TIMER4_MOD_EN (1 << 11) #define CP_GLB_CP_AHB_TIMER3_CONF_EN (1 << 12) #define CP_GLB_CP_AHB_TIMER3_MOD_EN (1 << 13) #define CP_GLB_CP_AHB_SCI1_CONF_EN (1 << 14) #define CP_GLB_CP_AHB_SCI1_MOD_EN (1 << 15) #define CP_GLB_CP_AHB_SCI1_FUNC_EN (1 << 16) #define CP_GLB_CP_AHB_SCI2_MOD_EN (1 << 17) #define CP_GLB_CP_AHB_SCI2_CONF_EN (1 << 18) #define CP_GLB_CP_AHB_SCI2_FUNC_EN (1 << 19) #define CP_GLB_CP_AHB_BUSMON_FUNC_EN (1 << 20) #define CP_GLB_WLAN_11B_EN (1 << 21) #define CP_GLB_FREQ_BIAS_FUNC_EN (1 << 22) #define CP_GLB_DAP_DAP_EN (1 << 23) #define CP_GLB_CP_APB_IFC_EN (1 << 26) #define CP_GLB_CP_AHB_IFC_EN (1 << 27) #define CP_GLB_AON2CP_AHB_EN (1 << 28) #define CP_GLB_FREQ_BIAS_AHB_EN (1 << 29) // sysctrl19 #define CP_GLB_CGM_WCN_11B_DFE_EN (1 << 0) #define CP_GLB_CGM_TIMER_26M_EN (1 << 1) #define CP_GLB_CGM_WDG_32K_EN (1 << 2) #define CP_GLB_CGM_WCN_11B_ADC_EN (1 << 3) #define CP_GLB_CGM_GNSS_TSX_SEL (1 << 4) #define CP_GLB_CGM_GNSS_TSX_EN (1 << 5) #define CP_GLB_CGM_THM_TSX_EN (1 << 6) #define CP_GLB_CGM_THM_OSC_EN (1 << 7) // sysctrl20 #define CP_GLB_CP_A5_SOFT_RST (1 << 0) #define CP_GLB_CP_A5CS_SOFT_RST (1 << 1) #define CP_GLB_CP_A5DBG_SOFT_RST (1 << 2) #define CP_GLB_CP_IRQ1_SOFT_RST (1 << 3) #define CP_GLB_CP_IRQ0_SOFT_RST (1 << 4) #define CP_GLB_CP_TIMER3_SOFT_RST (1 << 5) #define CP_GLB_CP_IMEM_APB_SOFT_RST (1 << 6) #define CP_GLB_CP_IMEM_AXI_SOFT_RST (1 << 7) #define CP_GLB_CP_AXIDMA_SOFT_RST (1 << 8) #define CP_GLB_CP_F8_SOFT_RST (1 << 9) #define CP_GLB_CP_WLAN_SOFT_RST (1 << 10) #define CP_GLB_CP_BUSMON_M4_SOFT_RST (1 << 11) #define CP_GLB_CP_BUSMON_M3_SOFT_RST (1 << 12) #define CP_GLB_CP_BUSMON_M2_SOFT_RST (1 << 13) #define CP_GLB_CP_BUSMON_M1_SOFT_RST (1 << 14) #define CP_GLB_CP_BUSMON_M0_SOFT_RST (1 << 15) #define CP_GLB_CP_BSUMON_APB_SOFT_RST (1 << 16) #define CP_GLB_CP_SCI2_SOFT_RST (1 << 17) #define CP_GLB_CP_SCI1_SOFT_RST (1 << 18) #define CP_GLB_CP_TIMER4_SOFT_RST (1 << 19) #define CP_GLB_AON2CP_SOFT_RST (1 << 20) #define CP_GLB_CP2GNSS_SOFT_RST (1 << 21) #define CP_GLB_CP2AON_SOFT_RST (1 << 22) #define CP_GLB_CP_LTECPU_ASYNC_SOFT_RST (1 << 23) #define CP_GLB_CP_LTEDMA_ASYNC_SOFT_RST (1 << 24) #define CP_GLB_CP_PSRAM_ASYNC_SOFT_RST (1 << 25) #define CP_GLB_TSX_AB_SOFT_RST (1 << 26) #define CP_GLB_TSX_IP_SOFT_RST (1 << 27) // sysctrl21 #define CP_GLB_CP_IFC_CH_DBG_AUTO_GATE_EN (1 << 0) #define CP_GLB_CP_IFC_CH0_AUTO_GATE_EN (1 << 1) #define CP_GLB_CP_IFC_CH1_AUTO_GATE_EN (1 << 2) #define CP_GLB_CP_IFC_CH2_AUTO_GATE_EN (1 << 3) #define CP_GLB_CP_IFC_CH3_AUTO_GATE_EN (1 << 4) #define CP_GLB_CP_IFC_AUTO_GATE_EN (1 << 5) #define CP_GLB_CP_SCI1_AUTO_GATE_EN (1 << 6) #define CP_GLB_CP_SCI2_AUTO_GATE_EN (1 << 7) #define CP_GLB_AON2CP_AHB_AUTO_GATE_EN (1 << 8) #define CP_GLB_IFC2CP_AHB_AUTO_GATE_EN (1 << 9) #define CP_GLB_CP2FREQ_AHB_AUTO_GATE_EN (1 << 12) #define CP_GLB_CP_A5_AUTO_GATE_EN (1 << 13) #define CP_GLB_CP_AXI_AUTO_GATE_EN (1 << 14) // sysctrl22 #define CP_GLB_CP_APBREG_SOFT_RST (1 << 0) // sysstat04 #define CP_GLB_AXI_DETECTOR_OVERFLOW_CP_PSRAM (1 << 0) #define CP_GLB_PWR_HANDSHK_CLK_REQ_CP_PSRAM (1 << 1) #define CP_GLB_BRIDGE_TRANS_IDLE_CP_PSRAM (1 << 2) #define CP_GLB_AXI_DETECTOR_OVERFLOW_CP_LTEDMA (1 << 3) #define CP_GLB_PWR_HANDSHK_CLK_REQ_CP_LTEDMA (1 << 4) #define CP_GLB_BRIDGE_TRANS_IDLE_CP_LTEDMA (1 << 5) #define CP_GLB_AXI_DETECTOR_OVERFLOW_CP_LTECPU (1 << 6) #define CP_GLB_PWR_HANDSHK_CLK_REQ_CP_LTECPU (1 << 7) #define CP_GLB_BRIDGE_TRANS_IDLE_CP_LTECPU (1 << 8) // sysstat05 #define CP_GLB_LP_STAT_M0 (1 << 0) #define CP_GLB_LP_STAT_M1 (1 << 1) #define CP_GLB_LP_STAT_M2 (1 << 2) #define CP_GLB_LP_STAT_M3 (1 << 3) #define CP_GLB_LP_STAT_M4 (1 << 4) #define CP_GLB_LP_STAT_MAIN (1 << 5) #define CP_GLB_LP_STAT_S0 (1 << 6) #define CP_GLB_LP_STAT_S1 (1 << 7) #define CP_GLB_LP_STAT_S2 (1 << 8) #define CP_GLB_LP_STAT_S3 (1 << 9) #define CP_GLB_LP_STAT_S4 (1 << 10) #define CP_GLB_LP_STAT_S5 (1 << 11) #define CP_GLB_LP_STAT_S6 (1 << 12) #define CP_GLB_CGM_BUSY_LPC_M0 (1 << 13) #define CP_GLB_CGM_BUSY_LPC_M1 (1 << 14) #define CP_GLB_CGM_BUSY_LPC_M2 (1 << 15) #define CP_GLB_CGM_BUSY_LPC_M3 (1 << 16) #define CP_GLB_CGM_BUSY_LPC_M4 (1 << 17) #define CP_GLB_CGM_BUSY_LPC_MAIN (1 << 18) #define CP_GLB_CGM_BUSY_LPC_S0 (1 << 19) #define CP_GLB_CGM_BUSY_LPC_S1 (1 << 20) #define CP_GLB_CGM_BUSY_LPC_S2 (1 << 21) #define CP_GLB_CGM_BUSY_LPC_S3 (1 << 22) #define CP_GLB_CGM_BUSY_LPC_S4 (1 << 23) #define CP_GLB_CGM_BUSY_LPC_S5 (1 << 24) #define CP_GLB_CGM_BUSY_LPC_S6 (1 << 25) #define CP_GLB_CP_LIGHT_STOP (1 << 26) #define CP_GLB_CP_SLP_ACK (1 << 27) #define CP_GLB_ALL_MASTER_FORCE_SLP (1 << 28) #define CP_GLB_ALL_SLAVE_FORCE_SLP (1 << 29) // sysstat06 #define CP_GLB_FORCE_ACK_M0 (1 << 0) #define CP_GLB_FORCE_ACK_M1 (1 << 1) #define CP_GLB_FORCE_ACK_M2 (1 << 2) #define CP_GLB_FORCE_ACK_M3 (1 << 3) #define CP_GLB_FORCE_ACK_M4 (1 << 4) #define CP_GLB_FORCE_ACK_MAIN (1 << 5) #define CP_GLB_FORCE_ACK_S0 (1 << 6) #define CP_GLB_FORCE_ACK_S1 (1 << 7) #define CP_GLB_FORCE_ACK_S2 (1 << 8) #define CP_GLB_FORCE_ACK_S3 (1 << 9) #define CP_GLB_FORCE_ACK_S4 (1 << 10) #define CP_GLB_FORCE_ACK_S5 (1 << 11) #define CP_GLB_FORCE_ACK_S6 (1 << 12) // sysstat07 #define CP_GLB_BUSMON0_LOCK (1 << 0) #define CP_GLB_BUSMON1_LOCK (1 << 1) #define CP_GLB_BUSMON2_LOCK (1 << 2) #define CP_GLB_BUSMON3_LOCK (1 << 3) #define CP_GLB_BUSMON4_LOCK (1 << 4) #define CP_GLB_BUSMON_RBUSY0 (1 << 5) #define CP_GLB_BUSMON_WBUSY0 (1 << 6) #define CP_GLB_BUSMON_BUSY0 (1 << 7) #define CP_GLB_BUSMON_RBUSY1 (1 << 8) #define CP_GLB_BUSMON_WBUSY1 (1 << 9) #define CP_GLB_BUSMON_BUSY1 (1 << 10) #define CP_GLB_BUSMON_RBUSY2 (1 << 11) #define CP_GLB_BUSMON_WBUSY2 (1 << 12) #define CP_GLB_BUSMON_BUSY2 (1 << 13) #define CP_GLB_BUSMON_RBUSY3 (1 << 14) #define CP_GLB_BUSMON_WBUSY3 (1 << 15) #define CP_GLB_BUSMON_BUSY3 (1 << 16) #define CP_GLB_BUSMON_RBUSY4 (1 << 17) #define CP_GLB_BUSMON_WBUSY4 (1 << 18) #define CP_GLB_BUSMON_BUSY4 (1 << 19) #define CP_GLB_CP_DBG_MONITOR(n) (((n)&0xff) << 20) // sysctrl28 #define CP_GLB_CORE_INT_DISABLE (1 << 0) #define CP_GLB_CP_LIGHT_STOP_EN (1 << 1) #define CP_GLB_LIGHT_BYPASS_M0_LPC (1 << 2) #define CP_GLB_LIGHT_BYPASS_M1_LPC (1 << 3) #define CP_GLB_LIGHT_BYPASS_M2_LPC (1 << 4) #define CP_GLB_LIGHT_BYPASS_M3_LPC (1 << 5) #define CP_GLB_LIGHT_BYPASS_M4_LPC (1 << 6) #define CP_GLB_LIGHT_BYPASS_MAIN_LPC (1 << 7) #define CP_GLB_LIGHT_BYPASS_M0 (1 << 8) #define CP_GLB_LIGHT_BYPASS_M1 (1 << 9) #define CP_GLB_LIGHT_BYPASS_M2 (1 << 10) #define CP_GLB_LIGHT_BYPASS_M3 (1 << 11) #define CP_GLB_LIGHT_BYPASS_M4 (1 << 12) #define CP_GLB_LIGHT_BYPASS_S0 (1 << 13) #define CP_GLB_LIGHT_BYPASS_S1 (1 << 14) #define CP_GLB_LIGHT_BYPASS_S2 (1 << 15) #define CP_GLB_LIGHT_BYPASS_S3 (1 << 16) #define CP_GLB_LIGHT_BYPASS_S4 (1 << 17) #define CP_GLB_LIGHT_BYPASS_S5 (1 << 18) #define CP_GLB_LIGHT_BYPASS_S6 (1 << 19) #define CP_GLB_LIGHT_BYPASS_SCI1 (1 << 20) #define CP_GLB_LIGHT_BYPASS_SCI2 (1 << 21) #define CP_GLB_LIGHT_BYPASS_TIMER3 (1 << 22) #define CP_GLB_LIGHT_BYPASS_TIMER4 (1 << 23) #define CP_GLB_LIGHT_BYPASS_WLAN (1 << 24) #define CP_GLB_CORE_STOP_BYPASS (1 << 25) // sysstat09 #define CP_GLB_DC_EST_I(n) (((n)&0x7fff) << 0) #define CP_GLB_SET_DC (1 << 15) #define CP_GLB_DC_EST_Q(n) (((n)&0x7fff) << 16) #define CP_GLB_RESET_DC (1 << 31) // sysctrl29 #define CP_GLB_LP_NUM_MAIN(n) (((n)&0xffff) << 0) #define CP_GLB_PU_NUM_MAIN(n) (((n)&0xff) << 16) // sysctrl30 #define CP_GLB_CP_LATCH_BITMAP (1 << 0) // sysstat10 #define CP_GLB_LATCH_CNT_122M88_VALUE_L(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_CNT_122M88_VALUE_M(n) (((n)&0xffff) << 16) // sysstat11 #define CP_GLB_LATCH_CNT_122M88_VALUE_H(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_WPTR(n) (((n)&0xff) << 16) // sysstat12 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM0(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM1(n) (((n)&0xffff) << 16) // sysstat13 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM2(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM3(n) (((n)&0xffff) << 16) // sysstat14 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM4(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM5(n) (((n)&0xffff) << 16) // sysstat15 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM6(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM7(n) (((n)&0xffff) << 16) // sysstat16 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM8(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM9(n) (((n)&0xffff) << 16) // sysstat17 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM10(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM11(n) (((n)&0xffff) << 16) // sysstat18 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM12(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM13(n) (((n)&0xffff) << 16) // sysstat19 #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM14(n) (((n)&0xffff) << 0) #define CP_GLB_LATCH_BITMAP_CYCLE_INDEX_NUM15(n) (((n)&0xffff) << 16) #endif // _CP_GLB_H_