/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _GIC400_REG_H_ #define _GIC400_REG_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_GIC400_BASE (0x00800000) typedef volatile struct { uint32_t __0[1024]; // 0x00000000 uint32_t gicd_ctrl; // 0x00001000 uint32_t gicd_typer; // 0x00001004 uint32_t gicd_iddr; // 0x00001008 uint32_t __4108[29]; // 0x0000100c uint32_t gicd_igrouprn[4]; // 0x00001080 uint32_t __4240[28]; // 0x00001090 uint32_t gicd_isenabler0; // 0x00001100 uint32_t gicd_isenabler1; // 0x00001104 uint32_t gicd_isenabler2; // 0x00001108 uint32_t gicd_isenabler3; // 0x0000110c uint32_t __4368[28]; // 0x00001110 uint32_t gicd_icenabler0; // 0x00001180 uint32_t gicd_icenabler1; // 0x00001184 uint32_t gicd_icenabler2; // 0x00001188 uint32_t gicd_icenabler3; // 0x0000118c uint32_t __4496[28]; // 0x00001190 uint32_t gicd_ispendrn[4]; // 0x00001200 uint32_t __4624[28]; // 0x00001210 uint32_t gicd_icpendrn[4]; // 0x00001280 uint32_t __4752[28]; // 0x00001290 uint32_t gicd_isactivern[4]; // 0x00001300 uint32_t __4880[28]; // 0x00001310 uint32_t gicd_icactivern[4]; // 0x00001380 uint32_t __5008[28]; // 0x00001390 uint32_t gicd_ipriorityrn[32]; // 0x00001400 uint32_t __5248[224]; // 0x00001480 uint32_t gicd_itargetsr0; // 0x00001800 uint32_t gicd_itargetsr1; // 0x00001804 uint32_t gicd_itargetsr2; // 0x00001808 uint32_t gicd_itargetsr3; // 0x0000180c uint32_t gicd_itargetsr4; // 0x00001810 uint32_t gicd_itargetsr5; // 0x00001814 uint32_t gicd_itargetsr6; // 0x00001818 uint32_t gicd_itargetsr7; // 0x0000181c uint32_t gicd_itargetsr8; // 0x00001820 uint32_t gicd_itargetsr9; // 0x00001824 uint32_t gicd_itargetsr10; // 0x00001828 uint32_t gicd_itargetsr11; // 0x0000182c uint32_t gicd_itargetsr12; // 0x00001830 uint32_t gicd_itargetsr13; // 0x00001834 uint32_t gicd_itargetsr14; // 0x00001838 uint32_t gicd_itargetsr15; // 0x0000183c uint32_t gicd_itargetsr16; // 0x00001840 uint32_t gicd_itargetsr17; // 0x00001844 uint32_t gicd_itargetsr18; // 0x00001848 uint32_t gicd_itargetsr19; // 0x0000184c uint32_t gicd_itargetsr20; // 0x00001850 uint32_t gicd_itargetsr21; // 0x00001854 uint32_t gicd_itargetsr22; // 0x00001858 uint32_t gicd_itargetsr23; // 0x0000185c uint32_t gicd_itargetsr24; // 0x00001860 uint32_t gicd_itargetsr25; // 0x00001864 uint32_t gicd_itargetsr26; // 0x00001868 uint32_t gicd_itargetsr27; // 0x0000186c uint32_t gicd_itargetsr28; // 0x00001870 uint32_t gicd_itargetsr29; // 0x00001874 uint32_t gicd_itargetsr30; // 0x00001878 uint32_t gicd_itargetsr31; // 0x0000187c uint32_t __6272[224]; // 0x00001880 uint32_t gicd_icfgr0; // 0x00001c00 uint32_t gicd_icfgr1; // 0x00001c04 uint32_t gicd_icfgr2; // 0x00001c08 uint32_t gicd_icfgr3; // 0x00001c0c uint32_t gicd_icfgr4; // 0x00001c10 uint32_t gicd_icfgr5; // 0x00001c14 uint32_t gicd_icfgr6; // 0x00001c18 uint32_t gicd_icfgr7; // 0x00001c1c uint32_t __7200[56]; // 0x00001c20 uint32_t gicd_ppisr; // 0x00001d00 uint32_t gicd_spisrn[3]; // 0x00001d04 uint32_t __7440[60]; // 0x00001d10 uint32_t gicd_nsacrn[8]; // 0x00001e00 uint32_t __7712[56]; // 0x00001e20 uint32_t gicd_sgir; // 0x00001f00 uint32_t __7940[3]; // 0x00001f04 uint32_t gicd_cpendsgirn[4]; // 0x00001f10 uint32_t gicd_spendsgirn[4]; // 0x00001f20 uint32_t __7984[52]; // 0x00001f30 uint32_t gicc_ctrl; // 0x00002000 uint32_t gicc_pmr; // 0x00002004 uint32_t gicc_bpr; // 0x00002008 uint32_t gicc_iar; // 0x0000200c uint32_t gicc_eoir; // 0x00002010 uint32_t gicc_rpr; // 0x00002014 uint32_t gicc_hppir; // 0x00002018 uint32_t gicc_abpr; // 0x0000201c uint32_t gicc_aiar; // 0x00002020 uint32_t gicc_aeoir; // 0x00002024 uint32_t gicc_ahppir; // 0x00002028 uint32_t __8236[41]; // 0x0000202c uint32_t gicc_aprn; // 0x000020d0 uint32_t __8404[3]; // 0x000020d4 uint32_t gicc_nsaprn; // 0x000020e0 uint32_t __8420[6]; // 0x000020e4 uint32_t gicc_iidr; // 0x000020fc uint32_t __8448[960]; // 0x00002100 uint32_t gicc_dir; // 0x00003000 } HWP_GIC400_T; #define hwp_gic400 ((HWP_GIC400_T *)REG_ACCESS_ADDRESS(REG_GIC400_BASE)) // gicd_ctrl typedef union { uint32_t v; struct { uint32_t enablegrp0 : 1; // [0] uint32_t enablegrp1 : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_GIC400_GICD_CTRL_T; // gicd_typer typedef union { uint32_t v; struct { uint32_t itlinesnumber : 5; // [4:0], read only uint32_t cpunumber : 3; // [7:5], read only uint32_t __9_8 : 2; // [9:8] uint32_t securityextn : 1; // [10], read only uint32_t lspi : 5; // [15:11], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_GIC400_GICD_TYPER_T; // gicd_iddr typedef union { uint32_t v; struct { uint32_t implementer : 12; // [11:0], read only uint32_t revision : 4; // [15:12], read only uint32_t variant : 4; // [19:16], read only uint32_t __23_20 : 4; // [23:20] uint32_t productid : 8; // [31:24], read only } b; } REG_GIC400_GICD_IDDR_T; // gicd_ppisr typedef union { uint32_t v; struct { uint32_t __8_0 : 9; // [8:0] uint32_t ppi_status : 7; // [15:9], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_GIC400_GICD_PPISR_T; // gicd_sgir typedef union { uint32_t v; struct { uint32_t sgiintid : 4; // [3:0] uint32_t __14_4 : 11; // [14:4] uint32_t nsatt : 1; // [15] uint32_t cputargetlist : 8; // [23:16] uint32_t targetlistfilter : 2; // [25:24] uint32_t __31_26 : 6; // [31:26] } b; } REG_GIC400_GICD_SGIR_T; // gicc_ctrl typedef union { uint32_t v; struct { uint32_t enablegrp0 : 1; // [0] uint32_t enablegrp1 : 1; // [1] uint32_t ackctl : 1; // [2] uint32_t fiqen : 1; // [3] uint32_t cbpr : 1; // [4] uint32_t fiqbypdisgrp0 : 1; // [5] uint32_t irqbypdisgrp0 : 1; // [6] uint32_t fiqbypdisgrp1 : 1; // [7] uint32_t irqbypdisgrp1 : 1; // [8] uint32_t eoimodes : 1; // [9] uint32_t eoimodens : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_GIC400_GICC_CTRL_T; // gicc_pmr typedef union { uint32_t v; struct { uint32_t priority : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_GIC400_GICC_PMR_T; // gicc_bpr typedef union { uint32_t v; struct { uint32_t binary_point : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_GIC400_GICC_BPR_T; // gicc_iar typedef union { uint32_t v; struct { uint32_t interrupt_id : 10; // [9:0], read only uint32_t cpuid : 3; // [12:10], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_IAR_T; // gicc_eoir typedef union { uint32_t v; struct { uint32_t eoiintid : 10; // [9:0] uint32_t cpuid : 3; // [12:10] uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_EOIR_T; // gicc_rpr typedef union { uint32_t v; struct { uint32_t priority : 8; // [7:0], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_GIC400_GICC_RPR_T; // gicc_hppir typedef union { uint32_t v; struct { uint32_t pendintid : 10; // [9:0], read only uint32_t cpuid : 3; // [12:10], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_HPPIR_T; // gicc_abpr typedef union { uint32_t v; struct { uint32_t binary_point : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_GIC400_GICC_ABPR_T; // gicc_aiar typedef union { uint32_t v; struct { uint32_t interrupt_id : 10; // [9:0], read only uint32_t cpuid : 3; // [12:10], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_AIAR_T; // gicc_aeoir typedef union { uint32_t v; struct { uint32_t interrupt_id : 10; // [9:0] uint32_t cpuid : 3; // [12:10] uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_AEOIR_T; // gicc_ahppir typedef union { uint32_t v; struct { uint32_t pendintid : 10; // [9:0], read only uint32_t cpuid : 3; // [12:10], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_AHPPIR_T; // gicc_iidr typedef union { uint32_t v; struct { uint32_t implementer : 12; // [11:0], read only uint32_t revision : 4; // [15:12], read only uint32_t architecture_version : 4; // [19:16], read only uint32_t __23_20 : 4; // [23:20] uint32_t productid : 8; // [31:24], read only } b; } REG_GIC400_GICC_IIDR_T; // gicc_dir typedef union { uint32_t v; struct { uint32_t interrupt_id : 10; // [9:0] uint32_t cpuid : 3; // [12:10] uint32_t __31_13 : 19; // [31:13] } b; } REG_GIC400_GICC_DIR_T; // gicd_ctrl #define GIC400_ENABLEGRP0 (1 << 0) #define GIC400_ENABLEGRP1 (1 << 1) // gicd_typer #define GIC400_ITLINESNUMBER(n) (((n)&0x1f) << 0) #define GIC400_CPUNUMBER(n) (((n)&0x7) << 5) #define GIC400_SECURITYEXTN (1 << 10) #define GIC400_LSPI(n) (((n)&0x1f) << 11) // gicd_iddr #define GIC400_IMPLEMENTER(n) (((n)&0xfff) << 0) #define GIC400_REVISION(n) (((n)&0xf) << 12) #define GIC400_VARIANT(n) (((n)&0xf) << 16) #define GIC400_PRODUCTID(n) (((n)&0xff) << 24) // gicd_ppisr #define GIC400_PPI_STATUS(n) (((n)&0x7f) << 9) // gicd_sgir #define GIC400_SGIINTID(n) (((n)&0xf) << 0) #define GIC400_NSATT (1 << 15) #define GIC400_CPUTARGETLIST(n) (((n)&0xff) << 16) #define GIC400_TARGETLISTFILTER(n) (((n)&0x3) << 24) // gicc_ctrl #define GIC400_ENABLEGRP0 (1 << 0) #define GIC400_ENABLEGRP1 (1 << 1) #define GIC400_ACKCTL (1 << 2) #define GIC400_FIQEN (1 << 3) #define GIC400_CBPR (1 << 4) #define GIC400_FIQBYPDISGRP0 (1 << 5) #define GIC400_IRQBYPDISGRP0 (1 << 6) #define GIC400_FIQBYPDISGRP1 (1 << 7) #define GIC400_IRQBYPDISGRP1 (1 << 8) #define GIC400_EOIMODES (1 << 9) #define GIC400_EOIMODENS (1 << 10) // gicc_pmr #define GIC400_PRIORITY(n) (((n)&0xff) << 0) // gicc_bpr #define GIC400_BINARY_POINT(n) (((n)&0x7) << 0) // gicc_iar #define GIC400_INTERRUPT_ID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_eoir #define GIC400_EOIINTID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_rpr #define GIC400_PRIORITY(n) (((n)&0xff) << 0) // gicc_hppir #define GIC400_PENDINTID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_abpr #define GIC400_BINARY_POINT(n) (((n)&0x7) << 0) // gicc_aiar #define GIC400_INTERRUPT_ID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_aeoir #define GIC400_INTERRUPT_ID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_ahppir #define GIC400_PENDINTID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) // gicc_iidr #define GIC400_IMPLEMENTER(n) (((n)&0xfff) << 0) #define GIC400_REVISION(n) (((n)&0xf) << 12) #define GIC400_ARCHITECTURE_VERSION(n) (((n)&0xf) << 16) #define GIC400_PRODUCTID(n) (((n)&0xff) << 24) // gicc_dir #define GIC400_INTERRUPT_ID(n) (((n)&0x3ff) << 0) #define GIC400_CPUID(n) (((n)&0x7) << 10) #endif // _GIC400_REG_H_