/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _MED_H_ #define _MED_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_MED_BASE (0x04000000) typedef volatile struct { uint32_t med_ch0_work_cfg; // 0x00000000 uint32_t med_ch0_base_addr_cfg; // 0x00000004 uint32_t med_ch0_addr_size_cfg; // 0x00000008 uint32_t med_ch0_read_addr_remap; // 0x0000000c uint32_t __16[4]; // 0x00000010 uint32_t med_ch1_work_cfg; // 0x00000020 uint32_t med_ch1_base_addr_cfg; // 0x00000024 uint32_t med_ch1_addr_size_cfg; // 0x00000028 uint32_t med_ch1_read_addr_remap; // 0x0000002c uint32_t __48[4]; // 0x00000030 uint32_t med_ch2_work_cfg; // 0x00000040 uint32_t med_ch2_base_addr_cfg; // 0x00000044 uint32_t med_ch2_addr_size_cfg; // 0x00000048 uint32_t med_ch2_read_addr_remap; // 0x0000004c uint32_t __80[4]; // 0x00000050 uint32_t med_ch3_work_cfg; // 0x00000060 uint32_t med_ch3_base_addr_cfg; // 0x00000064 uint32_t med_ch3_addr_size_cfg; // 0x00000068 uint32_t med_ch3_read_addr_remap; // 0x0000006c uint32_t __112[32]; // 0x00000070 uint32_t med_write_addr_remap; // 0x000000f0 uint32_t med_write_base_addr_cfg; // 0x000000f4 uint32_t med_write_addr_size_cfg; // 0x000000f8 uint32_t __252[1]; // 0x000000fc uint32_t med_clr; // 0x00000100 uint32_t med_work_mode; // 0x00000104 uint32_t med_int_en; // 0x00000108 uint32_t med_int_raw; // 0x0000010c uint32_t med_int_clear; // 0x00000110 uint32_t med_error_addr; // 0x00000114 uint32_t med_status0; // 0x00000118 uint32_t med_status1; // 0x0000011c uint32_t med_status2; // 0x00000120 uint32_t med_status3; // 0x00000124 uint32_t med_soft_key; // 0x00000128 } HWP_MED_T; #define hwp_med ((HWP_MED_T *)REG_ACCESS_ADDRESS(REG_MED_BASE)) // med_ch0_work_cfg typedef union { uint32_t v; struct { uint32_t med_ch0_enable : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t med_ch0_bypass_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_MED_MED_CH0_WORK_CFG_T; // med_ch0_base_addr_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch0_base_addr : 27; // [31:5] } b; } REG_MED_MED_CH0_BASE_ADDR_CFG_T; // med_ch0_addr_size_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch0_addr_size : 19; // [23:5] uint32_t __31_24 : 8; // [31:24] } b; } REG_MED_MED_CH0_ADDR_SIZE_CFG_T; // med_ch0_read_addr_remap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch0_remap_read_addr : 27; // [31:5] } b; } REG_MED_MED_CH0_READ_ADDR_REMAP_T; // med_ch1_work_cfg typedef union { uint32_t v; struct { uint32_t med_ch1_enable : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t med_ch1_bypass_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_MED_MED_CH1_WORK_CFG_T; // med_ch1_base_addr_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch1_base_addr : 27; // [31:5] } b; } REG_MED_MED_CH1_BASE_ADDR_CFG_T; // med_ch1_addr_size_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch1_addr_size : 19; // [23:5] uint32_t __31_24 : 8; // [31:24] } b; } REG_MED_MED_CH1_ADDR_SIZE_CFG_T; // med_ch1_read_addr_remap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch1_remap_read_addr : 27; // [31:5] } b; } REG_MED_MED_CH1_READ_ADDR_REMAP_T; // med_ch2_work_cfg typedef union { uint32_t v; struct { uint32_t med_ch2_enable : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t med_ch2_bypass_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_MED_MED_CH2_WORK_CFG_T; // med_ch2_base_addr_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch2_base_addr : 27; // [31:5] } b; } REG_MED_MED_CH2_BASE_ADDR_CFG_T; // med_ch2_addr_size_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch2_addr_size : 19; // [23:5] uint32_t __31_24 : 8; // [31:24] } b; } REG_MED_MED_CH2_ADDR_SIZE_CFG_T; // med_ch2_read_addr_remap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch2_remap_read_addr : 27; // [31:5] } b; } REG_MED_MED_CH2_READ_ADDR_REMAP_T; // med_ch3_work_cfg typedef union { uint32_t v; struct { uint32_t med_ch3_enable : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t med_ch3_bypass_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_MED_MED_CH3_WORK_CFG_T; // med_ch3_base_addr_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch3_base_addr : 27; // [31:5] } b; } REG_MED_MED_CH3_BASE_ADDR_CFG_T; // med_ch3_addr_size_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch3_addr_size : 19; // [23:5] uint32_t __31_24 : 8; // [31:24] } b; } REG_MED_MED_CH3_ADDR_SIZE_CFG_T; // med_ch3_read_addr_remap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_ch3_remap_read_addr : 27; // [31:5] } b; } REG_MED_MED_CH3_READ_ADDR_REMAP_T; // med_write_addr_remap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_remap_write_addr : 27; // [31:5] } b; } REG_MED_MED_WRITE_ADDR_REMAP_T; // med_write_base_addr_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_write_base_addr : 27; // [31:5] } b; } REG_MED_MED_WRITE_BASE_ADDR_CFG_T; // med_write_addr_size_cfg typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t med_write_addr_size : 19; // [23:5] uint32_t __31_24 : 8; // [31:24] } b; } REG_MED_MED_WRITE_ADDR_SIZE_CFG_T; // med_clr typedef union { uint32_t v; struct { uint32_t med_read_ram_clr : 1; // [0], write clear uint32_t med_write_ram_clr : 1; // [1], write clear uint32_t __3_2 : 2; // [3:2] uint32_t med_simon_clr : 1; // [4], write clear uint32_t med_write_cnt_clr : 1; // [5], write clear uint32_t __31_6 : 26; // [31:6] } b; } REG_MED_MED_CLR_T; // med_work_mode typedef union { uint32_t v; struct { uint32_t med_key_iv_sel : 1; // [0] uint32_t __7_1 : 7; // [7:1] uint32_t med_bus_error_en : 1; // [8] uint32_t med_read_bus_error_en : 1; // [9] uint32_t med_write_bus_error_en : 1; // [10] uint32_t __15_11 : 5; // [15:11] uint32_t med_clk_force_on : 1; // [16] uint32_t __31_17 : 15; // [31:17] } b; } REG_MED_MED_WORK_MODE_T; // med_int_en typedef union { uint32_t v; struct { uint32_t med_wr_done_int_en : 1; // [0] uint32_t med_ch0_dis_addr_vld_int_en : 1; // [1] uint32_t med_ch1_dis_addr_vld_int_en : 1; // [2] uint32_t med_ch2_dis_addr_vld_int_en : 1; // [3] uint32_t med_ch3_dis_addr_vld_int_en : 1; // [4] uint32_t med_err_resp_int_en : 1; // [5] uint32_t med_addr_err_int_en : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_MED_MED_INT_EN_T; // med_int_raw typedef union { uint32_t v; struct { uint32_t med_wr_done_int_raw : 1; // [0], read only uint32_t med_ch0_dis_addr_vld_int_raw : 1; // [1], read only uint32_t med_ch1_dis_addr_vld_int_raw : 1; // [2], read only uint32_t med_ch2_dis_addr_vld_int_raw : 1; // [3], read only uint32_t med_ch3_dis_addr_vld_int_raw : 1; // [4], read only uint32_t med_err_resp_int_raw : 1; // [5], read only uint32_t med_addr_err_int_raw : 1; // [6], read only uint32_t __31_7 : 25; // [31:7] } b; } REG_MED_MED_INT_RAW_T; // med_int_clear typedef union { uint32_t v; struct { uint32_t med_wr_done_int_clr : 1; // [0], write clear uint32_t med_ch0_dis_addr_vld_int_clr : 1; // [1], write clear uint32_t med_ch1_dis_addr_vld_int_clr : 1; // [2], write clear uint32_t med_ch2_dis_addr_vld_int_clr : 1; // [3], write clear uint32_t med_ch3_dis_addr_vld_int_clr : 1; // [4], write clear uint32_t med_err_resp_int_clr : 1; // [5], write clear uint32_t med_addr_err_int_clr : 1; // [6], write clear uint32_t __31_7 : 25; // [31:7] } b; } REG_MED_MED_INT_CLEAR_T; // med_status0 typedef union { uint32_t v; struct { uint32_t med_simon_odata_ready : 1; // [0], read only uint32_t med_mster_slv_hready : 1; // [1], read only uint32_t med_mster_ahb_hready : 1; // [2], read only uint32_t med_work_busy : 1; // [3], read only uint32_t med_rd_busy : 1; // [4], read only uint32_t med_wr_busy : 1; // [5], read only uint32_t __11_6 : 6; // [11:6] uint32_t med_write_word_cnt : 20; // [31:12], read only } b; } REG_MED_MED_STATUS0_T; // med_ch0_work_cfg #define MED_MED_CH0_ENABLE (1 << 0) #define MED_MED_CH0_BYPASS_EN (1 << 4) // med_ch0_base_addr_cfg #define MED_MED_CH0_BASE_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch0_addr_size_cfg #define MED_MED_CH0_ADDR_SIZE(n) (((n)&0x7ffff) << 5) // med_ch0_read_addr_remap #define MED_MED_CH0_REMAP_READ_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch1_work_cfg #define MED_MED_CH1_ENABLE (1 << 0) #define MED_MED_CH1_BYPASS_EN (1 << 4) // med_ch1_base_addr_cfg #define MED_MED_CH1_BASE_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch1_addr_size_cfg #define MED_MED_CH1_ADDR_SIZE(n) (((n)&0x7ffff) << 5) // med_ch1_read_addr_remap #define MED_MED_CH1_REMAP_READ_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch2_work_cfg #define MED_MED_CH2_ENABLE (1 << 0) #define MED_MED_CH2_BYPASS_EN (1 << 4) // med_ch2_base_addr_cfg #define MED_MED_CH2_BASE_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch2_addr_size_cfg #define MED_MED_CH2_ADDR_SIZE(n) (((n)&0x7ffff) << 5) // med_ch2_read_addr_remap #define MED_MED_CH2_REMAP_READ_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch3_work_cfg #define MED_MED_CH3_ENABLE (1 << 0) #define MED_MED_CH3_BYPASS_EN (1 << 4) // med_ch3_base_addr_cfg #define MED_MED_CH3_BASE_ADDR(n) (((n)&0x7ffffff) << 5) // med_ch3_addr_size_cfg #define MED_MED_CH3_ADDR_SIZE(n) (((n)&0x7ffff) << 5) // med_ch3_read_addr_remap #define MED_MED_CH3_REMAP_READ_ADDR(n) (((n)&0x7ffffff) << 5) // med_write_addr_remap #define MED_MED_REMAP_WRITE_ADDR(n) (((n)&0x7ffffff) << 5) // med_write_base_addr_cfg #define MED_MED_WRITE_BASE_ADDR(n) (((n)&0x7ffffff) << 5) // med_write_addr_size_cfg #define MED_MED_WRITE_ADDR_SIZE(n) (((n)&0x7ffff) << 5) // med_clr #define MED_MED_READ_RAM_CLR (1 << 0) #define MED_MED_WRITE_RAM_CLR (1 << 1) #define MED_MED_SIMON_CLR (1 << 4) #define MED_MED_WRITE_CNT_CLR (1 << 5) // med_work_mode #define MED_MED_KEY_IV_SEL (1 << 0) #define MED_MED_BUS_ERROR_EN (1 << 8) #define MED_MED_READ_BUS_ERROR_EN (1 << 9) #define MED_MED_WRITE_BUS_ERROR_EN (1 << 10) #define MED_MED_CLK_FORCE_ON (1 << 16) // med_int_en #define MED_MED_WR_DONE_INT_EN (1 << 0) #define MED_MED_CH0_DIS_ADDR_VLD_INT_EN (1 << 1) #define MED_MED_CH1_DIS_ADDR_VLD_INT_EN (1 << 2) #define MED_MED_CH2_DIS_ADDR_VLD_INT_EN (1 << 3) #define MED_MED_CH3_DIS_ADDR_VLD_INT_EN (1 << 4) #define MED_MED_ERR_RESP_INT_EN (1 << 5) #define MED_MED_ADDR_ERR_INT_EN (1 << 6) // med_int_raw #define MED_MED_WR_DONE_INT_RAW (1 << 0) #define MED_MED_CH0_DIS_ADDR_VLD_INT_RAW (1 << 1) #define MED_MED_CH1_DIS_ADDR_VLD_INT_RAW (1 << 2) #define MED_MED_CH2_DIS_ADDR_VLD_INT_RAW (1 << 3) #define MED_MED_CH3_DIS_ADDR_VLD_INT_RAW (1 << 4) #define MED_MED_ERR_RESP_INT_RAW (1 << 5) #define MED_MED_ADDR_ERR_INT_RAW (1 << 6) // med_int_clear #define MED_MED_WR_DONE_INT_CLR (1 << 0) #define MED_MED_CH0_DIS_ADDR_VLD_INT_CLR (1 << 1) #define MED_MED_CH1_DIS_ADDR_VLD_INT_CLR (1 << 2) #define MED_MED_CH2_DIS_ADDR_VLD_INT_CLR (1 << 3) #define MED_MED_CH3_DIS_ADDR_VLD_INT_CLR (1 << 4) #define MED_MED_ERR_RESP_INT_CLR (1 << 5) #define MED_MED_ADDR_ERR_INT_CLR (1 << 6) // med_status0 #define MED_MED_SIMON_ODATA_READY (1 << 0) #define MED_MED_MSTER_SLV_HREADY (1 << 1) #define MED_MED_MSTER_AHB_HREADY (1 << 2) #define MED_MED_WORK_BUSY (1 << 3) #define MED_MED_RD_BUSY (1 << 4) #define MED_MED_WR_BUSY (1 << 5) #define MED_MED_WRITE_WORD_CNT(n) (((n)&0xfffff) << 12) #endif // _MED_H_