/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _PMIC_ANA_H_ #define _PMIC_ANA_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_PMIC_ANA_SET_OFFSET (256) #define REG_PMIC_ANA_CLR_OFFSET (512) #define REG_PMIC_ANA_BASE (0x51108c00) typedef volatile struct { uint32_t chip_id_low; // 0x00000000 uint32_t chip_id_high; // 0x00000004 uint32_t module_en0; // 0x00000008 uint32_t dig_clk_en0; // 0x0000000c uint32_t rtc_clk_en0; // 0x00000010 uint32_t soft_rst0; // 0x00000014 uint32_t xtl_wait; // 0x00000018 uint32_t rg_dvdd_reserved1; // 0x0000001c uint32_t vbat_ctrl0; // 0x00000020 uint32_t thm_otp_ctrl; // 0x00000024 uint32_t led_ctrl; // 0x00000028 uint32_t kpled_ctrl1; // 0x0000002c uint32_t ldo_vbat_ctrl1; // 0x00000030 uint32_t ldo_vbat_ctrl2; // 0x00000034 uint32_t ldo_vbat_ctrl3; // 0x00000038 uint32_t ldo_ana_ctrl; // 0x0000003c uint32_t ldo_vio18_ctrl; // 0x00000040 uint32_t ldo_vgen_ctrl1; // 0x00000044 uint32_t ldo_spimem_ctrl; // 0x00000048 uint32_t ldo_camd_ctrl; // 0x0000004c uint32_t ldo_rf15_ctrl; // 0x00000050 uint32_t ldo_vgen_ctrl3; // 0x00000054 uint32_t ldo_lp18_ctrl; // 0x00000058 uint32_t ldo_rf12_ctrl; // 0x0000005c uint32_t dcdc_ctrl1; // 0x00000060 uint32_t vcore_ctrl2; // 0x00000064 uint32_t vcore_ctrl3; // 0x00000068 uint32_t vrf_ctrl0; // 0x0000006c uint32_t vrf_ctrl1; // 0x00000070 uint32_t vgen_ctrl2; // 0x00000074 uint32_t vgen_ctrl3; // 0x00000078 uint32_t chgr_ctrl1; // 0x0000007c uint32_t auxadc_ctrl; // 0x00000080 uint32_t chgr_status; // 0x00000084 uint32_t arch_en; // 0x00000088 uint32_t mcu_wr_prot_value; // 0x0000008c uint32_t __144[1]; // 0x00000090 uint32_t dcdc_core_reg1; // 0x00000094 uint32_t dcdc_gen_reg1; // 0x00000098 uint32_t dcdc_vrf_reg1; // 0x0000009c uint32_t bg_ctrl0; // 0x000000a0 uint32_t ldo_vosel1; // 0x000000a4 uint32_t ldo_vosel3; // 0x000000a8 uint32_t ldo_vosel4; // 0x000000ac uint32_t ldo_lp18_vio33_ctrl1; // 0x000000b0 uint32_t reserved_reg_core; // 0x000000b4 uint32_t reserved_reg1; // 0x000000b8 uint32_t reserved_reg2; // 0x000000bc uint32_t ldo_sim_ctrl0; // 0x000000c0 uint32_t ldo_sim_vosel; // 0x000000c4 uint32_t sim_vpa_ctrl0; // 0x000000c8 uint32_t ldo_sim_ctrl1; // 0x000000cc uint32_t vpa_ctrl0; // 0x000000d0 uint32_t vpa_ctrl1; // 0x000000d4 uint32_t vpa_ctrl2; // 0x000000d8 uint32_t vpa_ctrl3; // 0x000000dc uint32_t dcdc_vpa_reg1; // 0x000000e0 uint32_t __228[57]; // 0x000000e4 uint32_t sim_vpa_ctrl0_set; // 0x000001c8 uint32_t ldo_sim_ctrl1_set; // 0x000001cc uint32_t __464[62]; // 0x000001d0 uint32_t sim_vpa_ctrl0_clr; // 0x000002c8 uint32_t ldo_sim_ctrl1_clr; // 0x000002cc } HWP_PMIC_ANA_T; #define hwp_pmicAna ((HWP_PMIC_ANA_T *)REG_ACCESS_ADDRESS(REG_PMIC_ANA_BASE)) // chip_id_low typedef union { uint32_t v; struct { uint32_t chip_id_low : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_CHIP_ID_LOW_T; // chip_id_high typedef union { uint32_t v; struct { uint32_t chip_id_high : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_CHIP_ID_HIGH_T; // module_en0 typedef union { uint32_t v; struct { uint32_t cal_en : 1; // [0] uint32_t __4_1 : 4; // [4:1] uint32_t adc_en : 1; // [5] uint32_t efs_en : 1; // [6] uint32_t __8_7 : 2; // [8:7] uint32_t bltc_en : 1; // [9] uint32_t __11_10 : 2; // [11:10] uint32_t tmr_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_MODULE_EN0_T; // dig_clk_en0 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t clk_cal_en : 1; // [2] uint32_t clk_cal_src_sel : 2; // [4:3] uint32_t clk_auxadc_en : 1; // [5] uint32_t clk_auxad_en : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_PMIC_ANA_DIG_CLK_EN0_T; // rtc_clk_en0 typedef union { uint32_t v; struct { uint32_t rtc_arch_en : 1; // [0] uint32_t __6_1 : 6; // [6:1] uint32_t rtc_bltc_en : 1; // [7] uint32_t __12_8 : 5; // [12:8] uint32_t rtc_tmr_en : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_ANA_RTC_CLK_EN0_T; // soft_rst0 typedef union { uint32_t v; struct { uint32_t cal_soft_rst : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t tmr_soft_rst : 1; // [4] uint32_t __5_5 : 1; // [5] uint32_t adc_soft_rst : 1; // [6] uint32_t efs_soft_rst : 1; // [7] uint32_t __8_8 : 1; // [8] uint32_t bltc_soft_rst : 1; // [9] uint32_t __31_10 : 22; // [31:10] } b; } REG_PMIC_ANA_SOFT_RST0_T; // xtl_wait typedef union { uint32_t v; struct { uint32_t xtl_wait : 8; // [7:0] uint32_t __14_8 : 7; // [14:8] uint32_t slp_rgb_pd_en : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_XTL_WAIT_T; // rg_dvdd_reserved1 typedef union { uint32_t v; struct { uint32_t rg_dvdd_reserved1 : 8; // [7:0] uint32_t rg_dvdd_reserved0 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_RG_DVDD_RESERVED1_T; // vbat_ctrl0 typedef union { uint32_t v; struct { uint32_t rg_ldo_vbat_auxcal_sel : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_PMIC_ANA_VBAT_CTRL0_T; // thm_otp_ctrl typedef union { uint32_t v; struct { uint32_t rg_otp_op : 3; // [2:0] uint32_t rg_otp_en : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_PMIC_ANA_THM_OTP_CTRL_T; // led_ctrl typedef union { uint32_t v; struct { uint32_t rg_ib_trim : 7; // [6:0] uint32_t rg_ib_rex_en : 1; // [7] uint32_t rg_batdet_cur_i : 3; // [10:8] uint32_t rg_batdet_cur_en : 1; // [11] uint32_t ib_trim_em_sel : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_LED_CTRL_T; // kpled_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_ldo_kpled_shpt_pd : 1; // [0] uint32_t rg_ldo_kpled_v : 3; // [3:1] uint32_t rg_ldo_kpled_cap_sel : 1; // [4] uint32_t rg_ldo_kpled_stb : 2; // [6:5] uint32_t rg_ldo_kpled_shpt_adj : 1; // [7] uint32_t rg_kpled_v : 4; // [11:8] uint32_t rg_ldo_kpled_cl_adj : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_KPLED_CTRL1_T; // ldo_vbat_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_ldo_usb33_discharge_en : 1; // [0] uint32_t rg_ldo_usb33_stb : 2; // [2:1] uint32_t rg_ldo_usb33_rz_adj : 1; // [3] uint32_t rg_ldo_usb33_shpt_en : 1; // [4] uint32_t rg_ldo_usb33_cl_adj : 3; // [7:5] uint32_t __31_8 : 24; // [31:8] } b; } REG_PMIC_ANA_LDO_VBAT_CTRL1_T; // ldo_vbat_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_ldo_cama_discharge_en : 1; // [0] uint32_t rg_ldo_cama_stb : 2; // [2:1] uint32_t rg_ldo_cama_rz_adj : 1; // [3] uint32_t rg_ldo_cama_shpt_en : 1; // [4] uint32_t rg_ldo_cama_cl_adj : 3; // [7:5] uint32_t rg_ldo_vio33_discharge_en : 1; // [8] uint32_t rg_ldo_vio33_stb : 2; // [10:9] uint32_t rg_ldo_vio33_rz_adj : 1; // [11] uint32_t rg_ldo_vio33_shpt_en : 1; // [12] uint32_t rg_ldo_vio33_cl_adj : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_VBAT_CTRL2_T; // ldo_vbat_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_ldo_mmc_discharge_en : 1; // [0] uint32_t rg_ldo_mmc_stb : 2; // [2:1] uint32_t rg_ldo_mmc_rz_adj : 1; // [3] uint32_t rg_ldo_mmc_shpt_en : 1; // [4] uint32_t rg_ldo_mmc_cl_adj : 3; // [7:5] uint32_t rg_ldo_lcd_discharge_en : 1; // [8] uint32_t rg_ldo_lcd_stb : 2; // [10:9] uint32_t rg_ldo_lcd_rz_adj : 1; // [11] uint32_t rg_ldo_lcd_shpt_en : 1; // [12] uint32_t rg_ldo_lcd_cl_adj : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_VBAT_CTRL3_T; // ldo_ana_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_ana_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_ana_cap_sel : 1; // [8] uint32_t rg_ldo_ana_bp : 1; // [9] uint32_t rg_ldo_ana_stb : 2; // [11:10] uint32_t rg_ldo_ana_shpt_adj : 1; // [12] uint32_t rg_ldo_ana_shpt_pd : 1; // [13] uint32_t rg_ldo_ana_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_ANA_CTRL_T; // ldo_vio18_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_vio18_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_vio18_cap_sel : 1; // [8] uint32_t rg_ldo_vio18_bp : 1; // [9] uint32_t rg_ldo_vio18_stb : 2; // [11:10] uint32_t rg_ldo_vio18_shpt_adj : 1; // [12] uint32_t rg_ldo_vio18_shpt_pd : 1; // [13] uint32_t rg_ldo_vio18_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_VIO18_CTRL_T; // ldo_vgen_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_ldo_mem_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_mem_cap_sel : 1; // [8] uint32_t rg_ldo_mem_bp : 1; // [9] uint32_t rg_ldo_mem_stb : 2; // [11:10] uint32_t rg_ldo_mem_shpt_adj : 1; // [12] uint32_t rg_ldo_mem_shpt_pd : 1; // [13] uint32_t rg_ldo_mem_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_VGEN_CTRL1_T; // ldo_spimem_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_spimem_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_spimem_cap_sel : 1; // [8] uint32_t rg_ldo_spimem_bp : 1; // [9] uint32_t rg_ldo_spimem_stb : 2; // [11:10] uint32_t rg_ldo_spimem_shpt_adj : 1; // [12] uint32_t rg_ldo_spimem_shpt_pd : 1; // [13] uint32_t rg_ldo_spimem_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_SPIMEM_CTRL_T; // ldo_camd_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_camd_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_camd_cap_sel : 1; // [8] uint32_t rg_ldo_camd_bp : 1; // [9] uint32_t rg_ldo_camd_stb : 2; // [11:10] uint32_t rg_ldo_camd_shpt_adj : 1; // [12] uint32_t rg_ldo_camd_shpt_pd : 1; // [13] uint32_t rg_ldo_camd_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_CAMD_CTRL_T; // ldo_rf15_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_rf15_v : 6; // [5:0] uint32_t __7_6 : 2; // [7:6] uint32_t rg_ldo_rf15_cap_sel : 1; // [8] uint32_t rg_ldo_rf15_bp : 1; // [9] uint32_t rg_ldo_rf15_stb : 2; // [11:10] uint32_t rg_ldo_rf15_shpt_adj : 1; // [12] uint32_t rg_ldo_rf15_shpt_pd : 1; // [13] uint32_t rg_ldo_rf15_cl_adj : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_ANA_LDO_RF15_CTRL_T; // ldo_lp18_ctrl typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t rg_ldo_lp18_discharge_en : 1; // [8] uint32_t rg_ldo_lp18_stb : 2; // [10:9] uint32_t rg_ldo_lp18_rz_adj : 1; // [11] uint32_t rg_ldo_lp18_shpt_en : 1; // [12] uint32_t rg_ldo_lp18_cl_adj : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_LP18_CTRL_T; // ldo_rf12_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_rf12_cap_sel : 1; // [0] uint32_t rg_ldo_rf12_bp : 1; // [1] uint32_t rg_ldo_rf12_stb : 2; // [3:2] uint32_t rg_ldo_rf12_v : 6; // [9:4] uint32_t rg_ldo_rf12_shpt_adj : 1; // [10] uint32_t rg_ldo_rf12_shpt_pd : 1; // [11] uint32_t rg_ldo_rf12_cl_adj : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_LDO_RF12_CTRL_T; // dcdc_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_dcdc_clkout_sel : 4; // [3:0] uint32_t rg_dcdc_clkout_uniphase : 1; // [4] uint32_t __10_5 : 6; // [10:5] uint32_t rg_clk3m_out_en : 1; // [11] uint32_t rg_dcdc_auxtrim_sel : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_DCDC_CTRL1_T; // vcore_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_vcore_curses_r : 2; // [1:0] uint32_t rg_vcore_curavg : 2; // [3:2] uint32_t rg_vcore_curlimit_r : 2; // [5:4] uint32_t rg_vcore_antiring_en : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_PMIC_ANA_VCORE_CTRL2_T; // vcore_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_vcore_sr_ls : 2; // [1:0] uint32_t rg_vcore_sr_hs : 2; // [3:2] uint32_t rg_vcore_slope : 2; // [5:4] uint32_t rg_vcore_rcomp : 2; // [7:6] uint32_t rg_vcore_pfm_vh : 2; // [9:8] uint32_t rg_vcore_zx_offset : 2; // [11:10] uint32_t rg_vcore_zx_disable : 1; // [12] uint32_t rg_vcore_force_pwm : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_ANA_VCORE_CTRL3_T; // vrf_ctrl0 typedef union { uint32_t v; struct { uint32_t rg_vrf_curses_r : 2; // [1:0] uint32_t rg_vrf_curavg : 2; // [3:2] uint32_t rg_vrf_curlimit_r : 2; // [5:4] uint32_t rg_vrf_antiring_en : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_PMIC_ANA_VRF_CTRL0_T; // vrf_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_vrf_sr_ls : 2; // [1:0] uint32_t rg_vrf_sr_hs : 2; // [3:2] uint32_t rg_vrf_slope : 2; // [5:4] uint32_t rg_vrf_rcomp : 2; // [7:6] uint32_t rg_vrf_pfm_vh : 2; // [9:8] uint32_t rg_vrf_zx_offset : 2; // [11:10] uint32_t rg_vrf_zx_disable : 1; // [12] uint32_t rg_vrf_force_pwm : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_ANA_VRF_CTRL1_T; // vgen_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_vgen_curses_r : 2; // [1:0] uint32_t rg_vgen_curlimit_r : 2; // [3:2] uint32_t rg_vgen_zx_offset : 2; // [5:4] uint32_t rg_vgen_zx_disable : 1; // [6] uint32_t rg_vgen_antiring_en : 1; // [7] uint32_t dcdc_gen_clk_rst : 1; // [8] uint32_t __31_9 : 23; // [31:9] } b; } REG_PMIC_ANA_VGEN_CTRL2_T; // vgen_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_vgen_sr_ls : 2; // [1:0] uint32_t rg_vgen_sr_hs : 2; // [3:2] uint32_t rg_vgen_slope : 2; // [5:4] uint32_t rg_vgen_rcomp : 2; // [7:6] uint32_t rg_vgen_pfm_vh : 2; // [9:8] uint32_t rg_vgen_maxduty_sel : 1; // [10] uint32_t rg_vgen_force_pwm : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_PMIC_ANA_VGEN_CTRL3_T; // chgr_ctrl1 typedef union { uint32_t v; struct { uint32_t chgr_cc_i : 4; // [3:0] uint32_t vchg_ovp_v : 2; // [5:4] uint32_t chgr_iterm : 2; // [7:6] uint32_t chgr_end_v : 2; // [9:8] uint32_t chgr_cc_en : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_PMIC_ANA_CHGR_CTRL1_T; // auxadc_ctrl typedef union { uint32_t v; struct { uint32_t rg_auxad_sgn_code : 1; // [0] uint32_t rg_auxad_ref_sel : 1; // [1] uint32_t rg_auxad_vss_sel : 1; // [2] uint32_t rg_auxad_test_en : 1; // [3] uint32_t rg_auxad_currentsen_en : 1; // [4] uint32_t rg_auxad_thm_cal : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_PMIC_ANA_AUXADC_CTRL_T; // chgr_status typedef union { uint32_t v; struct { uint32_t vchg_ovi : 1; // [0], read only uint32_t __1_1 : 1; // [1] uint32_t chgr_int : 1; // [2], read only uint32_t chgr_on : 1; // [3], read only uint32_t chgr_cv_status : 1; // [4], read only uint32_t cdp_int : 1; // [5], read only uint32_t dcp_int : 1; // [6], read only uint32_t sdp_int : 1; // [7], read only uint32_t chg_det : 1; // [8], read only uint32_t dcp_det : 1; // [9], read only uint32_t dp_low : 1; // [10], read only uint32_t chg_det_done : 1; // [11], read only uint32_t non_dcp_int : 1; // [12], read only uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_CHGR_STATUS_T; // arch_en typedef union { uint32_t v; struct { uint32_t arch_en : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_PMIC_ANA_ARCH_EN_T; // mcu_wr_prot_value typedef union { uint32_t v; struct { uint32_t mcu_wr_prot_value : 15; // [14:0] uint32_t mcu_wr_prot : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_MCU_WR_PROT_VALUE_T; // dcdc_core_reg1 typedef union { uint32_t v; struct { uint32_t div_base_vcore : 6; // [5:0] uint32_t phase_sel_vcore : 6; // [11:6] uint32_t div_clk_vcore_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_DCDC_CORE_REG1_T; // dcdc_gen_reg1 typedef union { uint32_t v; struct { uint32_t div_base_vgen : 6; // [5:0] uint32_t phase_sel_vgen : 6; // [11:6] uint32_t div_clk_vgen_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_DCDC_GEN_REG1_T; // dcdc_vrf_reg1 typedef union { uint32_t v; struct { uint32_t div_base_vrf : 6; // [5:0] uint32_t phase_sel_vrf : 6; // [11:6] uint32_t div_clk_vrf_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_DCDC_VRF_REG1_T; // bg_ctrl0 typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t rg_bg_ts : 1; // [8] uint32_t __11_9 : 3; // [11:9] uint32_t bg_chop_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_BG_CTRL0_T; // ldo_vosel1 typedef union { uint32_t v; struct { uint32_t rg_ldo_cama_vosel : 6; // [5:0] uint32_t __9_6 : 4; // [9:6] uint32_t rg_ldo_usb33_vosel : 6; // [15:10] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_VOSEL1_T; // ldo_vosel3 typedef union { uint32_t v; struct { uint32_t rg_ldo_vio33_vosel : 6; // [5:0] uint32_t __9_6 : 4; // [9:6] uint32_t rg_ldo_mmc_vosel : 6; // [15:10] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_VOSEL3_T; // ldo_vosel4 typedef union { uint32_t v; struct { uint32_t rg_ldo_lp18_vosel : 6; // [5:0] uint32_t __9_6 : 4; // [9:6] uint32_t rg_ldo_lcd_vosel : 6; // [15:10] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_VOSEL4_T; // ldo_lp18_vio33_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_ldo_vio33_ulp_itrim : 2; // [1:0] uint32_t __3_2 : 2; // [3:2] uint32_t rg_ldo_vio33_ulp_ifb_en : 1; // [4] uint32_t __7_5 : 3; // [7:5] uint32_t rg_ldo_lp18_ulp_itrim : 2; // [9:8] uint32_t __11_10 : 2; // [11:10] uint32_t rg_ldo_lp18_ulp_ifb_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_LDO_LP18_VIO33_CTRL1_T; // reserved_reg_core typedef union { uint32_t v; struct { uint32_t reserved_core : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_RESERVED_REG_CORE_T; // ldo_sim_ctrl0 typedef union { uint32_t v; struct { uint32_t rg_ldo_sim0_discharge_en : 1; // [0] uint32_t rg_ldo_sim0_stb : 2; // [2:1] uint32_t rg_ldo_sim0_rz_adj : 1; // [3] uint32_t rg_ldo_sim0_shpt_en : 1; // [4] uint32_t rg_ldo_sim0_cl_adj : 3; // [7:5] uint32_t rg_ldo_sim1_discharge_en : 1; // [8] uint32_t rg_ldo_sim1_stb : 2; // [10:9] uint32_t rg_ldo_sim1_rz_adj : 1; // [11] uint32_t rg_ldo_sim1_shpt_en : 1; // [12] uint32_t rg_ldo_sim1_cl_adj : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_SIM_CTRL0_T; // ldo_sim_vosel typedef union { uint32_t v; struct { uint32_t rg_ldo_sim1_vosel : 6; // [5:0] uint32_t __9_6 : 4; // [9:6] uint32_t rg_ldo_sim0_vosel : 6; // [15:10] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_LDO_SIM_VOSEL_T; // sim_vpa_ctrl0 typedef union { uint32_t v; struct { uint32_t rg_vpa_pd : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t rg_vpa_lp_en : 1; // [4] uint32_t __7_5 : 3; // [7:5] uint32_t da_ldo_sim1_lp_en : 1; // [8] uint32_t da_ldo_sim0_lp_en : 1; // [9] uint32_t __11_10 : 2; // [11:10] uint32_t da_ldo_sim1_pd : 1; // [12] uint32_t da_ldo_sim0_pd : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_ANA_SIM_VPA_CTRL0_T; // ldo_sim_ctrl1 typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t slp_ldosim0_lp_en : 1; // [8] uint32_t slp_ldosim1_lp_en : 1; // [9] uint32_t __11_10 : 2; // [11:10] uint32_t slp_ldosim0_pd_en : 1; // [12] uint32_t slp_ldosim1_pd_en : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_ANA_LDO_SIM_CTRL1_T; // vpa_ctrl0 typedef union { uint32_t v; struct { uint32_t da_vpa_votrim : 5; // [4:0] uint32_t __11_5 : 7; // [11:5] uint32_t ldo_vpa_votrim_sw_sel : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_VPA_CTRL0_T; // vpa_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_vpa_vosel : 7; // [6:0] uint32_t __31_7 : 25; // [31:7] } b; } REG_PMIC_ANA_VPA_CTRL1_T; // vpa_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_vpa_curses_m : 2; // [1:0] uint32_t rg_vpa_curlimit_r : 2; // [3:2] uint32_t rg_vpa_ccomp3 : 2; // [5:4] uint32_t rg_vpa_bypass_threshold : 2; // [7:6] uint32_t rg_vpa_bypass_forceon : 1; // [8] uint32_t rg_vpa_bypass_disable : 1; // [9] uint32_t rg_vpa_apc_ramp_sel : 1; // [10] uint32_t rg_vpa_apc_enable : 1; // [11] uint32_t rg_vpa_antiring_en : 1; // [12] uint32_t rg_vpa_zx_offset : 2; // [14:13] uint32_t rg_vpa_zx_disable : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_VPA_CTRL2_T; // vpa_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_vpa_sr_ls : 2; // [1:0] uint32_t rg_vpa_sr_hs : 2; // [3:2] uint32_t rg_vpa_sawtooth_slope : 2; // [5:4] uint32_t rg_vpa_rcomp3 : 2; // [7:6] uint32_t rg_vpa_rcomp2 : 2; // [9:8] uint32_t rg_vpa_pfm_threshold : 2; // [11:10] uint32_t rg_vpa_maxduty_sel : 1; // [12] uint32_t rg_vpa_force_pwm : 1; // [13] uint32_t rg_vpa_dvs_on : 1; // [14] uint32_t rg_vpa_sawtoothcal_rst : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_ANA_VPA_CTRL3_T; // dcdc_vpa_reg1 typedef union { uint32_t v; struct { uint32_t div_base_vpa : 6; // [5:0] uint32_t phase_sel_vpa : 6; // [11:6] uint32_t div_clk_vpa_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_ANA_DCDC_VPA_REG1_T; // chip_id_low #define PMIC_ANA_CHIP_ID_LOW(n) (((n)&0xffff) << 0) // chip_id_high #define PMIC_ANA_CHIP_ID_HIGH(n) (((n)&0xffff) << 0) // module_en0 #define PMIC_ANA_CAL_EN (1 << 0) #define PMIC_ANA_ADC_EN (1 << 5) #define PMIC_ANA_EFS_EN (1 << 6) #define PMIC_ANA_BLTC_EN (1 << 9) #define PMIC_ANA_TMR_EN (1 << 12) // dig_clk_en0 #define PMIC_ANA_CLK_CAL_EN (1 << 2) #define PMIC_ANA_CLK_CAL_SRC_SEL(n) (((n)&0x3) << 3) #define PMIC_ANA_CLK_AUXADC_EN (1 << 5) #define PMIC_ANA_CLK_AUXAD_EN (1 << 6) // rtc_clk_en0 #define PMIC_ANA_RTC_ARCH_EN (1 << 0) #define PMIC_ANA_RTC_BLTC_EN (1 << 7) #define PMIC_ANA_RTC_TMR_EN (1 << 13) // soft_rst0 #define PMIC_ANA_CAL_SOFT_RST (1 << 0) #define PMIC_ANA_TMR_SOFT_RST (1 << 4) #define PMIC_ANA_ADC_SOFT_RST (1 << 6) #define PMIC_ANA_EFS_SOFT_RST (1 << 7) #define PMIC_ANA_BLTC_SOFT_RST (1 << 9) // xtl_wait #define PMIC_ANA_XTL_WAIT(n) (((n)&0xff) << 0) #define PMIC_ANA_SLP_RGB_PD_EN (1 << 15) // rg_dvdd_reserved1 #define PMIC_ANA_RG_DVDD_RESERVED1(n) (((n)&0xff) << 0) #define PMIC_ANA_RG_DVDD_RESERVED0(n) (((n)&0xff) << 8) // vbat_ctrl0 #define PMIC_ANA_RG_LDO_VBAT_AUXCAL_SEL(n) (((n)&0x7) << 0) // thm_otp_ctrl #define PMIC_ANA_RG_OTP_OP(n) (((n)&0x7) << 0) #define PMIC_ANA_RG_OTP_EN (1 << 3) // led_ctrl #define PMIC_ANA_RG_IB_TRIM(n) (((n)&0x7f) << 0) #define PMIC_ANA_RG_IB_REX_EN (1 << 7) #define PMIC_ANA_RG_BATDET_CUR_I(n) (((n)&0x7) << 8) #define PMIC_ANA_RG_BATDET_CUR_EN (1 << 11) #define PMIC_ANA_IB_TRIM_EM_SEL (1 << 12) // kpled_ctrl1 #define PMIC_ANA_RG_LDO_KPLED_SHPT_PD (1 << 0) #define PMIC_ANA_RG_LDO_KPLED_V(n) (((n)&0x7) << 1) #define PMIC_ANA_RG_LDO_KPLED_CAP_SEL (1 << 4) #define PMIC_ANA_RG_LDO_KPLED_STB(n) (((n)&0x3) << 5) #define PMIC_ANA_RG_LDO_KPLED_SHPT_ADJ (1 << 7) #define PMIC_ANA_RG_KPLED_V(n) (((n)&0xf) << 8) #define PMIC_ANA_RG_LDO_KPLED_CL_ADJ (1 << 12) // ldo_vbat_ctrl1 #define PMIC_ANA_RG_LDO_USB33_DISCHARGE_EN (1 << 0) #define PMIC_ANA_RG_LDO_USB33_STB(n) (((n)&0x3) << 1) #define PMIC_ANA_RG_LDO_USB33_RZ_ADJ (1 << 3) #define PMIC_ANA_RG_LDO_USB33_SHPT_EN (1 << 4) #define PMIC_ANA_RG_LDO_USB33_CL_ADJ(n) (((n)&0x7) << 5) // ldo_vbat_ctrl2 #define PMIC_ANA_RG_LDO_CAMA_DISCHARGE_EN (1 << 0) #define PMIC_ANA_RG_LDO_CAMA_STB(n) (((n)&0x3) << 1) #define PMIC_ANA_RG_LDO_CAMA_RZ_ADJ (1 << 3) #define PMIC_ANA_RG_LDO_CAMA_SHPT_EN (1 << 4) #define PMIC_ANA_RG_LDO_CAMA_CL_ADJ(n) (((n)&0x7) << 5) #define PMIC_ANA_RG_LDO_VIO33_DISCHARGE_EN (1 << 8) #define PMIC_ANA_RG_LDO_VIO33_STB(n) (((n)&0x3) << 9) #define PMIC_ANA_RG_LDO_VIO33_RZ_ADJ (1 << 11) #define PMIC_ANA_RG_LDO_VIO33_SHPT_EN (1 << 12) #define PMIC_ANA_RG_LDO_VIO33_CL_ADJ(n) (((n)&0x7) << 13) // ldo_vbat_ctrl3 #define PMIC_ANA_RG_LDO_MMC_DISCHARGE_EN (1 << 0) #define PMIC_ANA_RG_LDO_MMC_STB(n) (((n)&0x3) << 1) #define PMIC_ANA_RG_LDO_MMC_RZ_ADJ (1 << 3) #define PMIC_ANA_RG_LDO_MMC_SHPT_EN (1 << 4) #define PMIC_ANA_RG_LDO_MMC_CL_ADJ(n) (((n)&0x7) << 5) #define PMIC_ANA_RG_LDO_LCD_DISCHARGE_EN (1 << 8) #define PMIC_ANA_RG_LDO_LCD_STB(n) (((n)&0x3) << 9) #define PMIC_ANA_RG_LDO_LCD_RZ_ADJ (1 << 11) #define PMIC_ANA_RG_LDO_LCD_SHPT_EN (1 << 12) #define PMIC_ANA_RG_LDO_LCD_CL_ADJ(n) (((n)&0x7) << 13) // ldo_ana_ctrl #define PMIC_ANA_RG_LDO_ANA_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_ANA_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_ANA_BP (1 << 9) #define PMIC_ANA_RG_LDO_ANA_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_ANA_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_ANA_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_ANA_CL_ADJ (1 << 14) // ldo_vio18_ctrl #define PMIC_ANA_RG_LDO_VIO18_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_VIO18_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_VIO18_BP (1 << 9) #define PMIC_ANA_RG_LDO_VIO18_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_VIO18_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_VIO18_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_VIO18_CL_ADJ (1 << 14) // ldo_vgen_ctrl1 #define PMIC_ANA_RG_LDO_MEM_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_MEM_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_MEM_BP (1 << 9) #define PMIC_ANA_RG_LDO_MEM_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_MEM_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_MEM_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_MEM_CL_ADJ (1 << 14) // ldo_spimem_ctrl #define PMIC_ANA_RG_LDO_SPIMEM_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_SPIMEM_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_SPIMEM_BP (1 << 9) #define PMIC_ANA_RG_LDO_SPIMEM_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_SPIMEM_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_SPIMEM_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_SPIMEM_CL_ADJ (1 << 14) // ldo_camd_ctrl #define PMIC_ANA_RG_LDO_CAMD_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_CAMD_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_CAMD_BP (1 << 9) #define PMIC_ANA_RG_LDO_CAMD_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_CAMD_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_CAMD_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_CAMD_CL_ADJ (1 << 14) // ldo_rf15_ctrl #define PMIC_ANA_RG_LDO_RF15_V(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_RF15_CAP_SEL (1 << 8) #define PMIC_ANA_RG_LDO_RF15_BP (1 << 9) #define PMIC_ANA_RG_LDO_RF15_STB(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_LDO_RF15_SHPT_ADJ (1 << 12) #define PMIC_ANA_RG_LDO_RF15_SHPT_PD (1 << 13) #define PMIC_ANA_RG_LDO_RF15_CL_ADJ (1 << 14) // ldo_lp18_ctrl #define PMIC_ANA_RG_LDO_LP18_DISCHARGE_EN (1 << 8) #define PMIC_ANA_RG_LDO_LP18_STB(n) (((n)&0x3) << 9) #define PMIC_ANA_RG_LDO_LP18_RZ_ADJ (1 << 11) #define PMIC_ANA_RG_LDO_LP18_SHPT_EN (1 << 12) #define PMIC_ANA_RG_LDO_LP18_CL_ADJ(n) (((n)&0x7) << 13) // ldo_rf12_ctrl #define PMIC_ANA_RG_LDO_RF12_CAP_SEL (1 << 0) #define PMIC_ANA_RG_LDO_RF12_BP (1 << 1) #define PMIC_ANA_RG_LDO_RF12_STB(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_LDO_RF12_V(n) (((n)&0x3f) << 4) #define PMIC_ANA_RG_LDO_RF12_SHPT_ADJ (1 << 10) #define PMIC_ANA_RG_LDO_RF12_SHPT_PD (1 << 11) #define PMIC_ANA_RG_LDO_RF12_CL_ADJ (1 << 12) // dcdc_ctrl1 #define PMIC_ANA_RG_DCDC_CLKOUT_SEL(n) (((n)&0xf) << 0) #define PMIC_ANA_RG_DCDC_CLKOUT_UNIPHASE (1 << 4) #define PMIC_ANA_RG_CLK3M_OUT_EN (1 << 11) #define PMIC_ANA_RG_DCDC_AUXTRIM_SEL(n) (((n)&0xf) << 12) // vcore_ctrl2 #define PMIC_ANA_RG_VCORE_CURSES_R(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VCORE_CURAVG(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VCORE_CURLIMIT_R(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VCORE_ANTIRING_EN (1 << 6) // vcore_ctrl3 #define PMIC_ANA_RG_VCORE_SR_LS(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VCORE_SR_HS(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VCORE_SLOPE(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VCORE_RCOMP(n) (((n)&0x3) << 6) #define PMIC_ANA_RG_VCORE_PFM_VH(n) (((n)&0x3) << 8) #define PMIC_ANA_RG_VCORE_ZX_OFFSET(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_VCORE_ZX_DISABLE (1 << 12) #define PMIC_ANA_RG_VCORE_FORCE_PWM (1 << 13) // vrf_ctrl0 #define PMIC_ANA_RG_VRF_CURSES_R(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VRF_CURAVG(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VRF_CURLIMIT_R(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VRF_ANTIRING_EN (1 << 6) // vrf_ctrl1 #define PMIC_ANA_RG_VRF_SR_LS(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VRF_SR_HS(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VRF_SLOPE(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VRF_RCOMP(n) (((n)&0x3) << 6) #define PMIC_ANA_RG_VRF_PFM_VH(n) (((n)&0x3) << 8) #define PMIC_ANA_RG_VRF_ZX_OFFSET(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_VRF_ZX_DISABLE (1 << 12) #define PMIC_ANA_RG_VRF_FORCE_PWM (1 << 13) // vgen_ctrl2 #define PMIC_ANA_RG_VGEN_CURSES_R(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VGEN_CURLIMIT_R(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VGEN_ZX_OFFSET(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VGEN_ZX_DISABLE (1 << 6) #define PMIC_ANA_RG_VGEN_ANTIRING_EN (1 << 7) #define PMIC_ANA_DCDC_GEN_CLK_RST (1 << 8) // vgen_ctrl3 #define PMIC_ANA_RG_VGEN_SR_LS(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VGEN_SR_HS(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VGEN_SLOPE(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VGEN_RCOMP(n) (((n)&0x3) << 6) #define PMIC_ANA_RG_VGEN_PFM_VH(n) (((n)&0x3) << 8) #define PMIC_ANA_RG_VGEN_MAXDUTY_SEL (1 << 10) #define PMIC_ANA_RG_VGEN_FORCE_PWM (1 << 11) // chgr_ctrl1 #define PMIC_ANA_CHGR_CC_I(n) (((n)&0xf) << 0) #define PMIC_ANA_VCHG_OVP_V(n) (((n)&0x3) << 4) #define PMIC_ANA_CHGR_ITERM(n) (((n)&0x3) << 6) #define PMIC_ANA_CHGR_END_V(n) (((n)&0x3) << 8) #define PMIC_ANA_CHGR_CC_EN (1 << 10) // auxadc_ctrl #define PMIC_ANA_RG_AUXAD_SGN_CODE (1 << 0) #define PMIC_ANA_RG_AUXAD_REF_SEL (1 << 1) #define PMIC_ANA_RG_AUXAD_VSS_SEL (1 << 2) #define PMIC_ANA_RG_AUXAD_TEST_EN (1 << 3) #define PMIC_ANA_RG_AUXAD_CURRENTSEN_EN (1 << 4) #define PMIC_ANA_RG_AUXAD_THM_CAL (1 << 5) // chgr_status #define PMIC_ANA_VCHG_OVI (1 << 0) #define PMIC_ANA_CHGR_INT (1 << 2) #define PMIC_ANA_CHGR_ON (1 << 3) #define PMIC_ANA_CHGR_CV_STATUS (1 << 4) #define PMIC_ANA_CDP_INT (1 << 5) #define PMIC_ANA_DCP_INT (1 << 6) #define PMIC_ANA_SDP_INT (1 << 7) #define PMIC_ANA_CHG_DET (1 << 8) #define PMIC_ANA_DCP_DET (1 << 9) #define PMIC_ANA_DP_LOW (1 << 10) #define PMIC_ANA_CHG_DET_DONE (1 << 11) #define PMIC_ANA_NON_DCP_INT (1 << 12) // arch_en #define PMIC_ANA_ARCH_EN (1 << 0) // mcu_wr_prot_value #define PMIC_ANA_MCU_WR_PROT_VALUE(n) (((n)&0x7fff) << 0) #define PMIC_ANA_MCU_WR_PROT (1 << 15) // dcdc_core_reg1 #define PMIC_ANA_DIV_BASE_VCORE(n) (((n)&0x3f) << 0) #define PMIC_ANA_PHASE_SEL_VCORE(n) (((n)&0x3f) << 6) #define PMIC_ANA_DIV_CLK_VCORE_EN (1 << 12) // dcdc_gen_reg1 #define PMIC_ANA_DIV_BASE_VGEN(n) (((n)&0x3f) << 0) #define PMIC_ANA_PHASE_SEL_VGEN(n) (((n)&0x3f) << 6) #define PMIC_ANA_DIV_CLK_VGEN_EN (1 << 12) // dcdc_vrf_reg1 #define PMIC_ANA_DIV_BASE_VRF(n) (((n)&0x3f) << 0) #define PMIC_ANA_PHASE_SEL_VRF(n) (((n)&0x3f) << 6) #define PMIC_ANA_DIV_CLK_VRF_EN (1 << 12) // bg_ctrl0 #define PMIC_ANA_RG_BG_TS (1 << 8) #define PMIC_ANA_BG_CHOP_EN (1 << 12) // ldo_vosel1 #define PMIC_ANA_RG_LDO_CAMA_VOSEL(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_USB33_VOSEL(n) (((n)&0x3f) << 10) // ldo_vosel3 #define PMIC_ANA_RG_LDO_VIO33_VOSEL(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_MMC_VOSEL(n) (((n)&0x3f) << 10) // ldo_vosel4 #define PMIC_ANA_RG_LDO_LP18_VOSEL(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_LCD_VOSEL(n) (((n)&0x3f) << 10) // ldo_lp18_vio33_ctrl1 #define PMIC_ANA_RG_LDO_VIO33_ULP_ITRIM(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_LDO_VIO33_ULP_IFB_EN (1 << 4) #define PMIC_ANA_RG_LDO_LP18_ULP_ITRIM(n) (((n)&0x3) << 8) #define PMIC_ANA_RG_LDO_LP18_ULP_IFB_EN (1 << 12) // reserved_reg_core #define PMIC_ANA_RESERVED_CORE(n) (((n)&0xffff) << 0) // ldo_sim_ctrl0 #define PMIC_ANA_RG_LDO_SIM0_DISCHARGE_EN (1 << 0) #define PMIC_ANA_RG_LDO_SIM0_STB(n) (((n)&0x3) << 1) #define PMIC_ANA_RG_LDO_SIM0_RZ_ADJ (1 << 3) #define PMIC_ANA_RG_LDO_SIM0_SHPT_EN (1 << 4) #define PMIC_ANA_RG_LDO_SIM0_CL_ADJ(n) (((n)&0x7) << 5) #define PMIC_ANA_RG_LDO_SIM1_DISCHARGE_EN (1 << 8) #define PMIC_ANA_RG_LDO_SIM1_STB(n) (((n)&0x3) << 9) #define PMIC_ANA_RG_LDO_SIM1_RZ_ADJ (1 << 11) #define PMIC_ANA_RG_LDO_SIM1_SHPT_EN (1 << 12) #define PMIC_ANA_RG_LDO_SIM1_CL_ADJ(n) (((n)&0x7) << 13) // ldo_sim_vosel #define PMIC_ANA_RG_LDO_SIM1_VOSEL(n) (((n)&0x3f) << 0) #define PMIC_ANA_RG_LDO_SIM0_VOSEL(n) (((n)&0x3f) << 10) // sim_vpa_ctrl0 #define PMIC_ANA_RG_VPA_PD (1 << 0) #define PMIC_ANA_RG_VPA_LP_EN (1 << 4) #define PMIC_ANA_DA_LDO_SIM1_LP_EN (1 << 8) #define PMIC_ANA_DA_LDO_SIM0_LP_EN (1 << 9) #define PMIC_ANA_DA_LDO_SIM1_PD (1 << 12) #define PMIC_ANA_DA_LDO_SIM0_PD (1 << 13) // ldo_sim_ctrl1 #define PMIC_ANA_SLP_LDOSIM0_LP_EN (1 << 8) #define PMIC_ANA_SLP_LDOSIM1_LP_EN (1 << 9) #define PMIC_ANA_SLP_LDOSIM0_PD_EN (1 << 12) #define PMIC_ANA_SLP_LDOSIM1_PD_EN (1 << 13) // vpa_ctrl0 #define PMIC_ANA_DA_VPA_VOTRIM(n) (((n)&0x1f) << 0) #define PMIC_ANA_LDO_VPA_VOTRIM_SW_SEL (1 << 12) // vpa_ctrl1 #define PMIC_ANA_RG_VPA_VOSEL(n) (((n)&0x7f) << 0) // vpa_ctrl2 #define PMIC_ANA_RG_VPA_CURSES_M(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VPA_CURLIMIT_R(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VPA_CCOMP3(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VPA_BYPASS_THRESHOLD(n) (((n)&0x3) << 6) #define PMIC_ANA_RG_VPA_BYPASS_FORCEON (1 << 8) #define PMIC_ANA_RG_VPA_BYPASS_DISABLE (1 << 9) #define PMIC_ANA_RG_VPA_APC_RAMP_SEL (1 << 10) #define PMIC_ANA_RG_VPA_APC_ENABLE (1 << 11) #define PMIC_ANA_RG_VPA_ANTIRING_EN (1 << 12) #define PMIC_ANA_RG_VPA_ZX_OFFSET(n) (((n)&0x3) << 13) #define PMIC_ANA_RG_VPA_ZX_DISABLE (1 << 15) // vpa_ctrl3 #define PMIC_ANA_RG_VPA_SR_LS(n) (((n)&0x3) << 0) #define PMIC_ANA_RG_VPA_SR_HS(n) (((n)&0x3) << 2) #define PMIC_ANA_RG_VPA_SAWTOOTH_SLOPE(n) (((n)&0x3) << 4) #define PMIC_ANA_RG_VPA_RCOMP3(n) (((n)&0x3) << 6) #define PMIC_ANA_RG_VPA_RCOMP2(n) (((n)&0x3) << 8) #define PMIC_ANA_RG_VPA_PFM_THRESHOLD(n) (((n)&0x3) << 10) #define PMIC_ANA_RG_VPA_MAXDUTY_SEL (1 << 12) #define PMIC_ANA_RG_VPA_FORCE_PWM (1 << 13) #define PMIC_ANA_RG_VPA_DVS_ON (1 << 14) #define PMIC_ANA_RG_VPA_SAWTOOTHCAL_RST (1 << 15) // dcdc_vpa_reg1 #define PMIC_ANA_DIV_BASE_VPA(n) (((n)&0x3f) << 0) #define PMIC_ANA_PHASE_SEL_VPA(n) (((n)&0x3f) << 6) #define PMIC_ANA_DIV_CLK_VPA_EN (1 << 12) #endif // _PMIC_ANA_H_