/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _PMIC_RTC_ANA_H_ #define _PMIC_RTC_ANA_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_PMIC_RTC_ANA_SET_OFFSET (256) #define REG_PMIC_RTC_ANA_CLR_OFFSET (272) #define REG_PMIC_RTC_ANA_BASE (0x51108800) typedef volatile struct { uint32_t module_en0; // 0x00000000 uint32_t dig_clk_en0; // 0x00000004 uint32_t rtc_clk_en0; // 0x00000008 uint32_t soft_rst0; // 0x0000000c uint32_t vbat_ctrl1; // 0x00000010 uint32_t ldo_vgen_ctrl3; // 0x00000014 uint32_t dcdc_ctrl1; // 0x00000018 uint32_t pm2_pd_en; // 0x0000001c uint32_t vgen_ctrl1; // 0x00000020 uint32_t ldo_vbat_ctrl1; // 0x00000024 uint32_t chgr_status; // 0x00000028 uint32_t power_pd_sw0; // 0x0000002c uint32_t power_pd_hw; // 0x00000030 uint32_t soft_rst_hw; // 0x00000034 uint32_t xtal_rc_ctrl; // 0x00000038 uint32_t rtc_ctrl; // 0x0000003c uint32_t rg_rtc_reserved1; // 0x00000040 uint32_t dvdd_ctrl; // 0x00000044 uint32_t powon_ctrl; // 0x00000048 uint32_t kpled_ctrl0; // 0x0000004c uint32_t power_pd_sw1; // 0x00000050 uint32_t power_lp_sw0; // 0x00000054 uint32_t ldo_vosel1; // 0x00000058 uint32_t slp_ldo_ulp_ctrl; // 0x0000005c uint32_t ldo_vgen_ctrl; // 0x00000060 uint32_t ldo_lp18_vio33_ulp_en; // 0x00000064 uint32_t vcore_ctrl0; // 0x00000068 uint32_t vcore_ctrl1; // 0x0000006c uint32_t vrf_ctrl2; // 0x00000070 uint32_t vrf_ctrl3; // 0x00000074 uint32_t vgen_ctrl0; // 0x00000078 uint32_t chgr_ctrl0; // 0x0000007c uint32_t chgr_det_ctrl0; // 0x00000080 uint32_t slp_ldo_pd_ctrl0; // 0x00000084 uint32_t slp_ldo_pd_ctrl1; // 0x00000088 uint32_t slp_dcdc_pd_ctrl; // 0x0000008c uint32_t dcdc_core_slp_ctrl0; // 0x00000090 uint32_t dcdc_core_slp_ctrl1; // 0x00000094 uint32_t slp_dcdc_lp_ctrl; // 0x00000098 uint32_t slp_ldo_lp_ctrl0; // 0x0000009c uint32_t slp_ldo_lp_ctrl1; // 0x000000a0 uint32_t reserved_reg_rtc; // 0x000000a4 uint32_t dcdc_vlg_sel; // 0x000000a8 uint32_t ldo_vlg_sel0; // 0x000000ac uint32_t clk32kless_ctrl0; // 0x000000b0 uint32_t clk32kless_ctrl1; // 0x000000b4 uint32_t xtl_wait_ctrl0; // 0x000000b8 uint32_t por_rst_monitor; // 0x000000bc uint32_t wdg_rst_monitor; // 0x000000c0 uint32_t por_pin_rst_monitor; // 0x000000c4 uint32_t por_src_flag; // 0x000000c8 uint32_t por_7s_ctrl; // 0x000000cc uint32_t hwrst_rtc; // 0x000000d0 uint32_t smpl_ctrl0; // 0x000000d4 uint32_t rtc_rst0; // 0x000000d8 uint32_t rtc_rst1; // 0x000000dc uint32_t rtc_rst2; // 0x000000e0 uint32_t rtc_clk_stop; // 0x000000e4 uint32_t vbat_drop_cnt; // 0x000000e8 uint32_t mixed_ctrl; // 0x000000ec uint32_t por_off_flag; // 0x000000f0 uint32_t swrst_ctrl0; // 0x000000f4 uint32_t swrst_ctrl1; // 0x000000f8 uint32_t free_timer_low; // 0x000000fc uint32_t free_timer_high; // 0x00000100 uint32_t reserved_reg1; // 0x00000104 uint32_t reserved_reg2; // 0x00000108 uint32_t reserved_reg3; // 0x0000010c uint32_t reserved_reg4; // 0x00000110 uint32_t reserved_reg5; // 0x00000114 uint32_t reserved_reg6; // 0x00000118 uint32_t pwr_wr_prot_value; // 0x0000011c uint32_t vol_tune_ctrl_core; // 0x00000120 uint32_t smpl_ctrl1; // 0x00000124 uint32_t __296[1]; // 0x00000128 uint32_t power_pd_sw0_set; // 0x0000012c uint32_t __304[3]; // 0x00000130 uint32_t power_pd_sw0_clr; // 0x0000013c uint32_t __320[4]; // 0x00000140 uint32_t power_pd_sw1_set; // 0x00000150 uint32_t __340[3]; // 0x00000154 uint32_t power_pd_sw1_clr; // 0x00000160 } HWP_PMIC_RTC_ANA_T; #define hwp_pmicRtcAna ((HWP_PMIC_RTC_ANA_T *)REG_ACCESS_ADDRESS(REG_PMIC_RTC_ANA_BASE)) // module_en0 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t rtc_en : 1; // [1] uint32_t wdg_en : 1; // [2] uint32_t eic_en : 1; // [3] uint32_t psm_topa_en : 1; // [4] uint32_t __6_5 : 2; // [6:5] uint32_t rtc_topa_en : 1; // [7] uint32_t iomux_en : 1; // [8] uint32_t __31_9 : 23; // [31:9] } b; } REG_PMIC_RTC_ANA_MODULE_EN0_T; // dig_clk_en0 typedef union { uint32_t v; struct { uint32_t clk_wdg_sel : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_PMIC_RTC_ANA_DIG_CLK_EN0_T; // rtc_clk_en0 typedef union { uint32_t v; struct { uint32_t rtc_arch_en : 1; // [0] uint32_t rtc_rtc_en : 1; // [1] uint32_t rtc_wdg_en : 1; // [2] uint32_t rtc_eic_en : 1; // [3] uint32_t __10_4 : 7; // [10:4] uint32_t rtc_efs_en : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_PMIC_RTC_ANA_RTC_CLK_EN0_T; // soft_rst0 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t rtc_soft_rst : 1; // [1] uint32_t wdg_soft_rst : 1; // [2] uint32_t eic_soft_rst : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_PMIC_RTC_ANA_SOFT_RST0_T; // vbat_ctrl1 typedef union { uint32_t v; struct { uint32_t da_ldo_vbat_reftrim : 5; // [4:0] uint32_t __7_5 : 3; // [7:5] uint32_t da_ldo_vbat_reftrim_ulp : 5; // [12:8] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_RTC_ANA_VBAT_CTRL1_T; // ldo_vgen_ctrl3 typedef union { uint32_t v; struct { uint32_t da_ldo_vgen_reftrim : 5; // [4:0] uint32_t __31_5 : 27; // [31:5] } b; } REG_PMIC_RTC_ANA_LDO_VGEN_CTRL3_T; // dcdc_ctrl1 typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t da_dcdc_osc3m_freq : 5; // [9:5] uint32_t da_dcdc_osc3m_en : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_PMIC_RTC_ANA_DCDC_CTRL1_T; // pm2_pd_en typedef union { uint32_t v; struct { uint32_t pm2_ldovio18_pd_en : 1; // [0] uint32_t pm2_ldovio33_pd_en : 1; // [1] uint32_t pm2_ldodcxo_pd_en : 1; // [2] uint32_t pm2_ldolp18_pd_en : 1; // [3] uint32_t pm2_dcdcgen_pd_en : 1; // [4] uint32_t pm2_dcdccore_pd_en : 1; // [5] uint32_t pm2_ldovio18_lp_en : 1; // [6] uint32_t pm2_ldovio33_lp_en : 1; // [7] uint32_t pm2_ldodcxo_lp_en : 1; // [8] uint32_t pm2_ldolp18_lp_en : 1; // [9] uint32_t pm2_dcdcgen_lp_en : 1; // [10] uint32_t pm2_dcdccore_lp_en : 1; // [11] uint32_t pm2_ldolp18_ulp_en : 1; // [12] uint32_t pm2_ldovio33_ulp_en : 1; // [13] uint32_t pm2_dcdc_core_ulp_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_PM2_PD_EN_T; // vgen_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_vgen_vosel : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_PMIC_RTC_ANA_VGEN_CTRL1_T; // chgr_status typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t dcp_switch_en : 1; // [1] uint32_t __12_2 : 11; // [12:2] uint32_t chgr_int_en : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_RTC_ANA_CHGR_STATUS_T; // power_pd_sw0 typedef union { uint32_t v; struct { uint32_t bg_pd : 1; // [0] uint32_t da_ldo_mmc_pd : 1; // [1] uint32_t da_vcore_pd : 1; // [2] uint32_t da_vrf_pd : 1; // [3] uint32_t da_vgen_pd : 1; // [4] uint32_t da_ldo_vio18_pd : 1; // [5] uint32_t da_ldo_mem_pd : 1; // [6] uint32_t da_ldo_dcxo_pd : 1; // [7] uint32_t ldo_cp_pd : 1; // [8] uint32_t ldo_emm_pd : 1; // [9] uint32_t da_ldo_vio33_pd : 1; // [10] uint32_t da_ldo_lp18_pd : 1; // [11] uint32_t da_ldo_rf12_pd : 1; // [12] uint32_t da_ldo_ana_pd : 1; // [13] uint32_t da_ldo_usb33_pd : 1; // [14] uint32_t da_ldo_spimem_pd : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POWER_PD_SW0_T; // power_pd_hw typedef union { uint32_t v; struct { uint32_t pwr_off_seq_en : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_PMIC_RTC_ANA_POWER_PD_HW_T; // soft_rst_hw typedef union { uint32_t v; struct { uint32_t reg_soft_rst_sw : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_PMIC_RTC_ANA_SOFT_RST_HW_T; // xtal_rc_ctrl typedef union { uint32_t v; struct { uint32_t rg_xtal32k_fine : 3; // [2:0] uint32_t rg_xtal32k_coarse : 3; // [5:3] uint32_t rg_xtal32k_pu : 1; // [6] uint32_t rg_rc64k_pu : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_PMIC_RTC_ANA_XTAL_RC_CTRL_T; // rtc_ctrl typedef union { uint32_t v; struct { uint32_t da_rtcbg_trim : 5; // [4:0] uint32_t rg_vbatbk_vosel : 3; // [7:5] uint32_t rg_rtc_vosel : 3; // [10:8] uint32_t __31_11 : 21; // [31:11] } b; } REG_PMIC_RTC_ANA_RTC_CTRL_T; // rg_rtc_reserved1 typedef union { uint32_t v; struct { uint32_t rg_rtc_reserved1 : 8; // [7:0] uint32_t rg_rtc_reserved0 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RG_RTC_RESERVED1_T; // dvdd_ctrl typedef union { uint32_t v; struct { uint32_t da_dvdd_pd : 1; // [0] uint32_t da_dvdd_iso : 1; // [1] uint32_t da_psm_vref_pd : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_PMIC_RTC_ANA_DVDD_CTRL_T; // powon_ctrl typedef union { uint32_t v; struct { uint32_t rg_uvlo_en : 1; // [0] uint32_t rg_vbatlow_en : 1; // [1] uint32_t da_powerdet_en : 1; // [2] uint32_t rg_pbint_pullh_enb : 1; // [3] uint32_t rg_buadet_en : 1; // [4] uint32_t rg_vbat_crash_v : 2; // [6:5] uint32_t rg_uvlo_v : 2; // [8:7] uint32_t rg_ovlo_v : 2; // [10:9] uint32_t rg_ovlo_t : 2; // [12:11] uint32_t rg_ovlo_en : 1; // [13] uint32_t rg_baton_t : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POWON_CTRL_T; // kpled_ctrl0 typedef union { uint32_t v; struct { uint32_t rg_ldo_kpled_reftrim : 5; // [4:0] uint32_t rg_ldo_kpled_pd : 1; // [5] uint32_t rg_kpled_pulldown_en : 1; // [6] uint32_t rg_kpled_pd : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_PMIC_RTC_ANA_KPLED_CTRL0_T; // power_pd_sw1 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t da_ldo_rf15_pd : 1; // [3] uint32_t __7_4 : 4; // [7:4] uint32_t da_ldo_lcd_pd : 1; // [8] uint32_t __9_9 : 1; // [9] uint32_t da_ldo_camd_pd : 1; // [10] uint32_t da_ldo_cama_pd : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_PMIC_RTC_ANA_POWER_PD_SW1_T; // power_lp_sw0 typedef union { uint32_t v; struct { uint32_t da_ldo_vio33_lp_en : 1; // [0] uint32_t da_ldo_lp18_lp_en : 1; // [1] uint32_t da_ldo_rf12_lp_en : 1; // [2] uint32_t da_ldo_rf15_lp_en : 1; // [3] uint32_t da_ldo_spimem_lp_en : 1; // [4] uint32_t da_ldo_mem_lp_en : 1; // [5] uint32_t da_ldo_ana_lp_en : 1; // [6] uint32_t da_ldo_vio18_lp_en : 1; // [7] uint32_t da_ldo_lcd_lp_en : 1; // [8] uint32_t da_ldo_mmc_lp_en : 1; // [9] uint32_t da_ldo_camd_lp_en : 1; // [10] uint32_t da_ldo_cama_lp_en : 1; // [11] uint32_t da_ldo_dcxo_lp_en : 1; // [12] uint32_t da_ldo_usb33_lp_en : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_RTC_ANA_POWER_LP_SW0_T; // ldo_vosel1 typedef union { uint32_t v; struct { uint32_t rg_ldo_dcxo_vosel : 6; // [5:0] uint32_t __31_6 : 26; // [31:6] } b; } REG_PMIC_RTC_ANA_LDO_VOSEL1_T; // slp_ldo_ulp_ctrl typedef union { uint32_t v; struct { uint32_t pm1_ldo_lp18_ulp_en : 1; // [0] uint32_t pm1_ldo_vio33_ulp_en : 1; // [1] uint32_t pm1_dcdc_core_ulp_en : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_PMIC_RTC_ANA_SLP_LDO_ULP_CTRL_T; // ldo_vgen_ctrl typedef union { uint32_t v; struct { uint32_t rg_ldo_vgen_auxcal_sel : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_PMIC_RTC_ANA_LDO_VGEN_CTRL_T; // ldo_lp18_vio33_ulp_en typedef union { uint32_t v; struct { uint32_t da_ldo_lp18_ulp_en : 1; // [0] uint32_t da_ldo_vio33_ulp_en : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_PMIC_RTC_ANA_LDO_LP18_VIO33_ULP_EN_T; // vcore_ctrl0 typedef union { uint32_t v; struct { uint32_t da_vcore_vosel : 9; // [8:0] uint32_t __31_9 : 23; // [31:9] } b; } REG_PMIC_RTC_ANA_VCORE_CTRL0_T; // vcore_ctrl1 typedef union { uint32_t v; struct { uint32_t da_vcore_votrim_lp : 5; // [4:0] uint32_t da_vcore_votrim : 5; // [9:5] uint32_t __11_10 : 2; // [11:10] uint32_t da_vcore_ulp_ret : 1; // [12] uint32_t da_vcore_ulp_en : 1; // [13] uint32_t rg_vcore_lp_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_VCORE_CTRL1_T; // vrf_ctrl2 typedef union { uint32_t v; struct { uint32_t da_vrf_votrim : 5; // [4:0] uint32_t da_vrf_lp_en : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_PMIC_RTC_ANA_VRF_CTRL2_T; // vrf_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_vrf_vosel : 9; // [8:0] uint32_t __31_9 : 23; // [31:9] } b; } REG_PMIC_RTC_ANA_VRF_CTRL3_T; // vgen_ctrl0 typedef union { uint32_t v; struct { uint32_t da_vgen_votrim : 5; // [4:0] uint32_t da_vgen_lp_en : 1; // [5] uint32_t __7_6 : 2; // [7:6] uint32_t pm2_ldo_mem_powersel : 1; // [8] uint32_t slp_ldo_mem_powersel_en : 1; // [9] uint32_t __31_10 : 22; // [31:10] } b; } REG_PMIC_RTC_ANA_VGEN_CTRL0_T; // chgr_ctrl0 typedef union { uint32_t v; struct { uint32_t chgr_cv_v : 6; // [5:0] uint32_t chgr_dpm : 2; // [7:6] uint32_t chgr_expower_device : 1; // [8] uint32_t chgr_ptest : 1; // [9] uint32_t chgr_pd : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_PMIC_RTC_ANA_CHGR_CTRL0_T; // chgr_det_ctrl0 typedef union { uint32_t v; struct { uint32_t chg_int_delay : 3; // [2:0] uint32_t __3_3 : 1; // [3] uint32_t rg_dp_dm_aux_en : 1; // [4] uint32_t dp_dm_bc_enb : 1; // [5] uint32_t __31_6 : 26; // [31:6] } b; } REG_PMIC_RTC_ANA_CHGR_DET_CTRL0_T; // slp_ldo_pd_ctrl0 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t slp_ldocama_pd_en : 1; // [2] uint32_t slp_ldocamd_pd_en : 1; // [3] uint32_t slp_ldolcd_pd_en : 1; // [4] uint32_t slp_ldommc_pd_en : 1; // [5] uint32_t slp_ldokpled_pd_en : 1; // [6] uint32_t pm1_ldousb_pd_en : 1; // [7] uint32_t slp_ldospimem_pd_en : 1; // [8] uint32_t slp_ldorf15_pd_en : 1; // [9] uint32_t pm1_ldovio33_pd_en : 1; // [10] uint32_t pm1_ldodcxo_pd_en : 1; // [11] uint32_t pm1_ldolp18_pd_en : 1; // [12] uint32_t slp_ldorf12_pd_en : 1; // [13] uint32_t slp_ldoana_pd_en : 1; // [14] uint32_t pm1_ldovio18_pd_en : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SLP_LDO_PD_CTRL0_T; // slp_ldo_pd_ctrl1 typedef union { uint32_t v; struct { uint32_t pm1_ldomem_pd_en : 1; // [0] uint32_t ldo_xtl_en : 1; // [1] uint32_t slp_io_en : 1; // [2] uint32_t slp_ldo_pd_en : 1; // [3] uint32_t pm1_ldocp_pd_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_PMIC_RTC_ANA_SLP_LDO_PD_CTRL1_T; // slp_dcdc_pd_ctrl typedef union { uint32_t v; struct { uint32_t pm1_dcdcgen_pd_en : 1; // [0] uint32_t slp_dcdcvrf_pd_en : 1; // [1] uint32_t __2_2 : 1; // [2] uint32_t slp_dcdccore_drop_en : 1; // [3] uint32_t __5_4 : 2; // [5:4] uint32_t slp_dcdccore_pu_rstn_th : 6; // [11:6] uint32_t slp_dcdccore_pd_rstn_th : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SLP_DCDC_PD_CTRL_T; // dcdc_core_slp_ctrl0 typedef union { uint32_t v; struct { uint32_t dcdc_core_slp_step_en : 1; // [0] uint32_t pm1_dcdccore_pd_en : 1; // [1] uint32_t __2_2 : 1; // [2] uint32_t pm1_dcdc_core_slp_step_vol : 5; // [7:3] uint32_t pm1_dcdc_core_slp_step_num : 4; // [11:8] uint32_t pm1_dcdc_core_slp_step_delay : 2; // [13:12] uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_RTC_ANA_DCDC_CORE_SLP_CTRL0_T; // dcdc_core_slp_ctrl1 typedef union { uint32_t v; struct { uint32_t pm1_dcdc_core_vosel_ds_sw : 9; // [8:0] uint32_t __31_9 : 23; // [31:9] } b; } REG_PMIC_RTC_ANA_DCDC_CORE_SLP_CTRL1_T; // slp_dcdc_lp_ctrl typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t pm1_dcdcgen_lp_en : 1; // [1] uint32_t slp_dcdcvrf_lp_en : 1; // [2] uint32_t __3_3 : 1; // [3] uint32_t pm1_dcdccore_lp_en : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_PMIC_RTC_ANA_SLP_DCDC_LP_CTRL_T; // slp_ldo_lp_ctrl0 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t slp_ldocama_lp_en : 1; // [2] uint32_t slp_ldocamd_lp_en : 1; // [3] uint32_t slp_ldolcd_lp_en : 1; // [4] uint32_t __5_5 : 1; // [5] uint32_t pm1_ldousb_lp_en : 1; // [6] uint32_t slp_ldommc_lp_en : 1; // [7] uint32_t slp_ldospimem_lp_en : 1; // [8] uint32_t slp_ldoana_lp_en : 1; // [9] uint32_t pm1_ldovio18_lp_en : 1; // [10] uint32_t pm1_ldodcxo_lp_en : 1; // [11] uint32_t pm1_ldovio33_lp_en : 1; // [12] uint32_t slp_ldorf12_lp_en : 1; // [13] uint32_t slp_ldorf15_lp_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_SLP_LDO_LP_CTRL0_T; // slp_ldo_lp_ctrl1 typedef union { uint32_t v; struct { uint32_t pm1_ldomem_lp_en : 1; // [0] uint32_t __2_1 : 2; // [2:1] uint32_t pm1_ldolp18_lp_en : 1; // [3] uint32_t __6_4 : 3; // [6:4] uint32_t pm2_dcdc_core_vosel_ds_sw : 9; // [15:7] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SLP_LDO_LP_CTRL1_T; // reserved_reg_rtc typedef union { uint32_t v; struct { uint32_t reserved_rtc : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RESERVED_REG_RTC_T; // dcdc_vlg_sel typedef union { uint32_t v; struct { uint32_t dcdc_core_nor_sw_sel : 1; // [0] uint32_t dcdc_core_slp_sw_sel : 1; // [1] uint32_t dcdc_core_votrim_sw_sel : 1; // [2] uint32_t dcdc_gen_sw_sel : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_PMIC_RTC_ANA_DCDC_VLG_SEL_T; // ldo_vlg_sel0 typedef union { uint32_t v; struct { uint32_t ldo_vcore_votrim_sw_sel : 1; // [0] uint32_t ldo_vcore_votrim_ulp_sw_sel : 1; // [1] uint32_t vgen_votrim_sw_sel : 1; // [2] uint32_t __3_3 : 1; // [3] uint32_t vrf_votrim_sw_sel : 1; // [4] uint32_t rtcbg_trim_sw_sel : 1; // [5] uint32_t dcdc_osc3m_freq_sw_sel : 1; // [6] uint32_t vbat_reftrim_sw_sel : 1; // [7] uint32_t vbat_reftrim_ulp_sw_sel : 1; // [8] uint32_t vgen_reftrim_sw_sel : 1; // [9] uint32_t __31_10 : 22; // [31:10] } b; } REG_PMIC_RTC_ANA_LDO_VLG_SEL0_T; // clk32kless_ctrl0 typedef union { uint32_t v; struct { uint32_t rc_32k_en : 1; // [0] uint32_t rc_32k_sel : 1; // [1] uint32_t __3_2 : 2; // [3:2] uint32_t rtc_mode : 1; // [4], read only uint32_t __5_5 : 1; // [5] uint32_t ldo_dcxo_lp_en_rtcclr : 1; // [6] uint32_t ldo_dcxo_lp_en_rtcset : 1; // [7] uint32_t __9_8 : 2; // [9:8] uint32_t rc_mode_wr_ack_flag_clr : 1; // [10], write clear uint32_t __13_11 : 3; // [13:11] uint32_t rc_mode_wr_ack_flag : 1; // [14], read only uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_CLK32KLESS_CTRL0_T; // clk32kless_ctrl1 typedef union { uint32_t v; struct { uint32_t rc_mode : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_CLK32KLESS_CTRL1_T; // por_rst_monitor typedef union { uint32_t v; struct { uint32_t por_rst_monitor : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POR_RST_MONITOR_T; // wdg_rst_monitor typedef union { uint32_t v; struct { uint32_t wdg_rst_monitor : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_WDG_RST_MONITOR_T; // por_pin_rst_monitor typedef union { uint32_t v; struct { uint32_t por_pin_rst_monitor : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POR_PIN_RST_MONITOR_T; // por_src_flag typedef union { uint32_t v; struct { uint32_t por_src_flag : 14; // [13:0], read only uint32_t reg_soft_rst_flag_clr : 1; // [14], write clear uint32_t por_sw_force_on : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POR_SRC_FLAG_T; // por_7s_ctrl typedef union { uint32_t v; struct { uint32_t pbint_7s_rst_mode : 1; // [0] uint32_t pbint_7s_rst_disable : 1; // [1] uint32_t pbint_7s_auto_on_en : 1; // [2] uint32_t ext_rstn_mode : 1; // [3] uint32_t pbint_7s_rst_threshold : 4; // [7:4] uint32_t pbint_7s_rst_swmode : 1; // [8] uint32_t key2_7s_rst_en : 1; // [9] uint32_t __10_10 : 1; // [10] uint32_t pbint_flag_clr : 1; // [11] uint32_t __12_12 : 1; // [12] uint32_t chgr_int_flag_clr : 1; // [13] uint32_t ext_rstn_flag_clr : 1; // [14] uint32_t pbint_7s_flag_clr : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_POR_7S_CTRL_T; // hwrst_rtc typedef union { uint32_t v; struct { uint32_t hwrst_rtc_reg_set : 8; // [7:0] uint32_t hwrst_rtc_reg_sts : 8; // [15:8], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_HWRST_RTC_T; // smpl_ctrl0 typedef union { uint32_t v; struct { uint32_t smpl_mode : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SMPL_CTRL0_T; // rtc_rst0 typedef union { uint32_t v; struct { uint32_t rtc_clk_flag_set : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RTC_RST0_T; // rtc_rst1 typedef union { uint32_t v; struct { uint32_t rtc_clk_flag_clr : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RTC_RST1_T; // rtc_rst2 typedef union { uint32_t v; struct { uint32_t rtc_clk_flag_rtc : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RTC_RST2_T; // rtc_clk_stop typedef union { uint32_t v; struct { uint32_t rtc_clk_stop_threshold : 7; // [6:0] uint32_t rtc_clk_stop_flag : 1; // [7], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_PMIC_RTC_ANA_RTC_CLK_STOP_T; // vbat_drop_cnt typedef union { uint32_t v; struct { uint32_t vbat_drop_cnt : 12; // [11:0], read only uint32_t __31_12 : 20; // [31:12] } b; } REG_PMIC_RTC_ANA_VBAT_DROP_CNT_T; // mixed_ctrl typedef union { uint32_t v; struct { uint32_t int_debug_en : 1; // [0] uint32_t all_int_deb : 1; // [1] uint32_t gpi_debug_en : 1; // [2] uint32_t all_gpi_deb : 1; // [3] uint32_t __4_4 : 1; // [4] uint32_t vbat_ok : 1; // [5], read only uint32_t __7_6 : 2; // [7:6] uint32_t batdet_ok : 1; // [8], read only uint32_t __14_9 : 6; // [14:9] uint32_t ad_buadet : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_MIXED_CTRL_T; // por_off_flag typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t otp_chip_pd_flag_clr : 1; // [2], write clear uint32_t otp_chip_pd_flag : 1; // [3], read only uint32_t hw_chip_pd_flag_clr : 1; // [4], write clear uint32_t hw_chip_pd_flag : 1; // [5], read only uint32_t sw_chip_pd_flag_clr : 1; // [6], write clear uint32_t sw_chip_pd_flag : 1; // [7], read only uint32_t hard_7s_chip_pd_flag_clr : 1; // [8], write clear uint32_t hard_7s_chip_pd_flag : 1; // [9], read only uint32_t uvlo_chip_pd_flag_clr : 1; // [10], write clear uint32_t uvlo_chip_pd_flag : 1; // [11], read only uint32_t por_chip_pd_flag_clr : 1; // [12], write clear uint32_t por_chip_pd_flag : 1; // [13], read only uint32_t __31_14 : 18; // [31:14] } b; } REG_PMIC_RTC_ANA_POR_OFF_FLAG_T; // swrst_ctrl0 typedef union { uint32_t v; struct { uint32_t sw_rst_pd_threshold : 4; // [3:0] uint32_t reg_rst_en : 1; // [4] uint32_t __6_5 : 2; // [6:5] uint32_t wdg_rst_pd_en : 1; // [7] uint32_t reg_rst_pd_en : 1; // [8] uint32_t pb_7s_rst_pd_en : 1; // [9] uint32_t ext_rstn_pd_en : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_PMIC_RTC_ANA_SWRST_CTRL0_T; // swrst_ctrl1 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t sw_rst_vio33_pd_en : 1; // [2] uint32_t sw_rst_usb_pd_en : 1; // [3] uint32_t sw_rst_rf15_pd_en : 1; // [4] uint32_t sw_rst_ana_pd_en : 1; // [5] uint32_t sw_rst_rf12_pd_en : 1; // [6] uint32_t sw_rst_dcxo_pd_en : 1; // [7] uint32_t sw_rst_mem_pd_en : 1; // [8] uint32_t sw_rst_dcdccore_pd_en : 1; // [9] uint32_t sw_rst_dcdcgen_pd_en : 1; // [10] uint32_t __13_11 : 3; // [13:11] uint32_t sw_rst_vio18_pd_en : 1; // [14] uint32_t sw_rst_spimem_pd_en : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SWRST_CTRL1_T; // free_timer_low typedef union { uint32_t v; struct { uint32_t timer_low : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_FREE_TIMER_LOW_T; // free_timer_high typedef union { uint32_t v; struct { uint32_t timer_high : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_FREE_TIMER_HIGH_T; // reserved_reg1 typedef union { uint32_t v; struct { uint32_t pm1_dvdd_en : 1; // [0] uint32_t pm1_osw_3m_en : 1; // [1] uint32_t pm1_bg_pd_en : 1; // [2] uint32_t pm1_power_det_en : 1; // [3] uint32_t uvlo_dbnc_en : 1; // [4] uint32_t ovlo_dbnc_en : 1; // [5] uint32_t pm1_ldo_mem_powersel : 1; // [6] uint32_t __7_7 : 1; // [7] uint32_t pm2_dcdc_core_slp_step_vol : 5; // [12:8] uint32_t __31_13 : 19; // [31:13] } b; } REG_PMIC_RTC_ANA_RESERVED_REG1_T; // reserved_reg2 typedef union { uint32_t v; struct { uint32_t ulp_cycle_sel0 : 4; // [3:0] uint32_t ulp_cycle_sel1 : 4; // [7:4] uint32_t pm1_sleep_dly1 : 4; // [11:8] uint32_t pm1_sleep_dly2 : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RESERVED_REG2_T; // reserved_reg3 typedef union { uint32_t v; struct { uint32_t uvlo_dbnc_time : 8; // [7:0] uint32_t ovlo_dbnc_time : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RESERVED_REG3_T; // reserved_reg4 typedef union { uint32_t v; struct { uint32_t pm2_sleep_dly1 : 8; // [7:0] uint32_t pm2_sleep_dly2 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_RESERVED_REG4_T; // reserved_reg5 typedef union { uint32_t v; struct { uint32_t pm2_ldomem_pd_en : 1; // [0] uint32_t pm2_ldousb_pd_en : 1; // [1] uint32_t pm2_ldomem_lp_en : 1; // [2] uint32_t pm2_ldousb_lp_en : 1; // [3] uint32_t pm2_dvdd_en : 1; // [4] uint32_t pm2_osw_3m_en : 1; // [5] uint32_t pm2_slp_bg_pd_en : 1; // [6] uint32_t pm2_power_det_en : 1; // [7] uint32_t pm2_dcdc_core_slp_step_num : 4; // [11:8] uint32_t pm2_dcdc_core_slp_step_delay : 2; // [13:12] uint32_t pm2_ldocp_pd_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_RESERVED_REG5_T; // reserved_reg6 typedef union { uint32_t v; struct { uint32_t pm2_en : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_PMIC_RTC_ANA_RESERVED_REG6_T; // pwr_wr_prot_value typedef union { uint32_t v; struct { uint32_t pwr_wr_prot_value : 15; // [14:0] uint32_t pwr_wr_prot : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_PWR_WR_PROT_VALUE_T; // vol_tune_ctrl_core typedef union { uint32_t v; struct { uint32_t core_vol_tune_en : 1; // [0] uint32_t core_vol_tune_flag : 1; // [1], read only uint32_t core_vol_tune_start : 1; // [2], write clear uint32_t core_step_vol : 5; // [7:3] uint32_t core_step_num : 4; // [11:8] uint32_t core_step_delay : 2; // [13:12] uint32_t core_clk_sel : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_PMIC_RTC_ANA_VOL_TUNE_CTRL_CORE_T; // smpl_ctrl1 typedef union { uint32_t v; struct { uint32_t smpl_en : 1; // [0], read only uint32_t __10_1 : 10; // [10:1] uint32_t smpl_pwr_on_set : 1; // [11], read only uint32_t smpl_mode_wr_ack_flag_clr : 1; // [12], write clear uint32_t smpl_pwr_on_flag_clr : 1; // [13], write clear uint32_t smpl_mode_wr_ack_flag : 1; // [14], read only uint32_t smpl_pwr_on_flag : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_PMIC_RTC_ANA_SMPL_CTRL1_T; // module_en0 #define PMIC_RTC_ANA_RTC_EN (1 << 1) #define PMIC_RTC_ANA_WDG_EN (1 << 2) #define PMIC_RTC_ANA_EIC_EN (1 << 3) #define PMIC_RTC_ANA_PSM_TOPA_EN (1 << 4) #define PMIC_RTC_ANA_RTC_TOPA_EN (1 << 7) #define PMIC_RTC_ANA_IOMUX_EN (1 << 8) // dig_clk_en0 #define PMIC_RTC_ANA_CLK_WDG_SEL (1 << 0) // rtc_clk_en0 #define PMIC_RTC_ANA_RTC_ARCH_EN (1 << 0) #define PMIC_RTC_ANA_RTC_RTC_EN (1 << 1) #define PMIC_RTC_ANA_RTC_WDG_EN (1 << 2) #define PMIC_RTC_ANA_RTC_EIC_EN (1 << 3) #define PMIC_RTC_ANA_RTC_EFS_EN (1 << 11) // soft_rst0 #define PMIC_RTC_ANA_RTC_SOFT_RST (1 << 1) #define PMIC_RTC_ANA_WDG_SOFT_RST (1 << 2) #define PMIC_RTC_ANA_EIC_SOFT_RST (1 << 3) // vbat_ctrl1 #define PMIC_RTC_ANA_DA_LDO_VBAT_REFTRIM(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_DA_LDO_VBAT_REFTRIM_ULP(n) (((n)&0x1f) << 8) // ldo_vgen_ctrl3 #define PMIC_RTC_ANA_DA_LDO_VGEN_REFTRIM(n) (((n)&0x1f) << 0) // dcdc_ctrl1 #define PMIC_RTC_ANA_DA_DCDC_OSC3M_FREQ(n) (((n)&0x1f) << 5) #define PMIC_RTC_ANA_DA_DCDC_OSC3M_EN (1 << 10) // pm2_pd_en #define PMIC_RTC_ANA_PM2_LDOVIO18_PD_EN (1 << 0) #define PMIC_RTC_ANA_PM2_LDOVIO33_PD_EN (1 << 1) #define PMIC_RTC_ANA_PM2_LDODCXO_PD_EN (1 << 2) #define PMIC_RTC_ANA_PM2_LDOLP18_PD_EN (1 << 3) #define PMIC_RTC_ANA_PM2_DCDCGEN_PD_EN (1 << 4) #define PMIC_RTC_ANA_PM2_DCDCCORE_PD_EN (1 << 5) #define PMIC_RTC_ANA_PM2_LDOVIO18_LP_EN (1 << 6) #define PMIC_RTC_ANA_PM2_LDOVIO33_LP_EN (1 << 7) #define PMIC_RTC_ANA_PM2_LDODCXO_LP_EN (1 << 8) #define PMIC_RTC_ANA_PM2_LDOLP18_LP_EN (1 << 9) #define PMIC_RTC_ANA_PM2_DCDCGEN_LP_EN (1 << 10) #define PMIC_RTC_ANA_PM2_DCDCCORE_LP_EN (1 << 11) #define PMIC_RTC_ANA_PM2_LDOLP18_ULP_EN (1 << 12) #define PMIC_RTC_ANA_PM2_LDOVIO33_ULP_EN (1 << 13) #define PMIC_RTC_ANA_PM2_DCDC_CORE_ULP_EN (1 << 14) // vgen_ctrl1 #define PMIC_RTC_ANA_RG_VGEN_VOSEL(n) (((n)&0xff) << 0) // chgr_status #define PMIC_RTC_ANA_DCP_SWITCH_EN (1 << 1) #define PMIC_RTC_ANA_CHGR_INT_EN (1 << 13) // power_pd_sw0 #define PMIC_RTC_ANA_BG_PD (1 << 0) #define PMIC_RTC_ANA_DA_LDO_MMC_PD (1 << 1) #define PMIC_RTC_ANA_DA_VCORE_PD (1 << 2) #define PMIC_RTC_ANA_DA_VRF_PD (1 << 3) #define PMIC_RTC_ANA_DA_VGEN_PD (1 << 4) #define PMIC_RTC_ANA_DA_LDO_VIO18_PD (1 << 5) #define PMIC_RTC_ANA_DA_LDO_MEM_PD (1 << 6) #define PMIC_RTC_ANA_DA_LDO_DCXO_PD (1 << 7) #define PMIC_RTC_ANA_LDO_CP_PD (1 << 8) #define PMIC_RTC_ANA_LDO_EMM_PD (1 << 9) #define PMIC_RTC_ANA_DA_LDO_VIO33_PD (1 << 10) #define PMIC_RTC_ANA_DA_LDO_LP18_PD (1 << 11) #define PMIC_RTC_ANA_DA_LDO_RF12_PD (1 << 12) #define PMIC_RTC_ANA_DA_LDO_ANA_PD (1 << 13) #define PMIC_RTC_ANA_DA_LDO_USB33_PD (1 << 14) #define PMIC_RTC_ANA_DA_LDO_SPIMEM_PD (1 << 15) // power_pd_hw #define PMIC_RTC_ANA_PWR_OFF_SEQ_EN (1 << 0) // soft_rst_hw #define PMIC_RTC_ANA_REG_SOFT_RST_SW (1 << 0) // xtal_rc_ctrl #define PMIC_RTC_ANA_RG_XTAL32K_FINE(n) (((n)&0x7) << 0) #define PMIC_RTC_ANA_RG_XTAL32K_COARSE(n) (((n)&0x7) << 3) #define PMIC_RTC_ANA_RG_XTAL32K_PU (1 << 6) #define PMIC_RTC_ANA_RG_RC64K_PU (1 << 7) // rtc_ctrl #define PMIC_RTC_ANA_DA_RTCBG_TRIM(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_RG_VBATBK_VOSEL(n) (((n)&0x7) << 5) #define PMIC_RTC_ANA_RG_RTC_VOSEL(n) (((n)&0x7) << 8) // rg_rtc_reserved1 #define PMIC_RTC_ANA_RG_RTC_RESERVED1(n) (((n)&0xff) << 0) #define PMIC_RTC_ANA_RG_RTC_RESERVED0(n) (((n)&0xff) << 8) // dvdd_ctrl #define PMIC_RTC_ANA_DA_DVDD_PD (1 << 0) #define PMIC_RTC_ANA_DA_DVDD_ISO (1 << 1) #define PMIC_RTC_ANA_DA_PSM_VREF_PD (1 << 2) // powon_ctrl #define PMIC_RTC_ANA_RG_UVLO_EN (1 << 0) #define PMIC_RTC_ANA_RG_VBATLOW_EN (1 << 1) #define PMIC_RTC_ANA_DA_POWERDET_EN (1 << 2) #define PMIC_RTC_ANA_RG_PBINT_PULLH_ENB (1 << 3) #define PMIC_RTC_ANA_RG_BUADET_EN (1 << 4) #define PMIC_RTC_ANA_RG_VBAT_CRASH_V(n) (((n)&0x3) << 5) #define PMIC_RTC_ANA_RG_UVLO_V(n) (((n)&0x3) << 7) #define PMIC_RTC_ANA_RG_OVLO_V(n) (((n)&0x3) << 9) #define PMIC_RTC_ANA_RG_OVLO_T(n) (((n)&0x3) << 11) #define PMIC_RTC_ANA_RG_OVLO_EN (1 << 13) #define PMIC_RTC_ANA_RG_BATON_T(n) (((n)&0x3) << 14) // kpled_ctrl0 #define PMIC_RTC_ANA_RG_LDO_KPLED_REFTRIM(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_RG_LDO_KPLED_PD (1 << 5) #define PMIC_RTC_ANA_RG_KPLED_PULLDOWN_EN (1 << 6) #define PMIC_RTC_ANA_RG_KPLED_PD (1 << 7) // power_pd_sw1 #define PMIC_RTC_ANA_DA_LDO_RF15_PD (1 << 3) #define PMIC_RTC_ANA_DA_LDO_LCD_PD (1 << 8) #define PMIC_RTC_ANA_DA_LDO_CAMD_PD (1 << 10) #define PMIC_RTC_ANA_DA_LDO_CAMA_PD (1 << 11) // power_lp_sw0 #define PMIC_RTC_ANA_DA_LDO_VIO33_LP_EN (1 << 0) #define PMIC_RTC_ANA_DA_LDO_LP18_LP_EN (1 << 1) #define PMIC_RTC_ANA_DA_LDO_RF12_LP_EN (1 << 2) #define PMIC_RTC_ANA_DA_LDO_RF15_LP_EN (1 << 3) #define PMIC_RTC_ANA_DA_LDO_SPIMEM_LP_EN (1 << 4) #define PMIC_RTC_ANA_DA_LDO_MEM_LP_EN (1 << 5) #define PMIC_RTC_ANA_DA_LDO_ANA_LP_EN (1 << 6) #define PMIC_RTC_ANA_DA_LDO_VIO18_LP_EN (1 << 7) #define PMIC_RTC_ANA_DA_LDO_LCD_LP_EN (1 << 8) #define PMIC_RTC_ANA_DA_LDO_MMC_LP_EN (1 << 9) #define PMIC_RTC_ANA_DA_LDO_CAMD_LP_EN (1 << 10) #define PMIC_RTC_ANA_DA_LDO_CAMA_LP_EN (1 << 11) #define PMIC_RTC_ANA_DA_LDO_DCXO_LP_EN (1 << 12) #define PMIC_RTC_ANA_DA_LDO_USB33_LP_EN (1 << 13) // ldo_vosel1 #define PMIC_RTC_ANA_RG_LDO_DCXO_VOSEL(n) (((n)&0x3f) << 0) // slp_ldo_ulp_ctrl #define PMIC_RTC_ANA_PM1_LDO_LP18_ULP_EN (1 << 0) #define PMIC_RTC_ANA_PM1_LDO_VIO33_ULP_EN (1 << 1) #define PMIC_RTC_ANA_PM1_DCDC_CORE_ULP_EN (1 << 2) // ldo_vgen_ctrl #define PMIC_RTC_ANA_RG_LDO_VGEN_AUXCAL_SEL(n) (((n)&0x7) << 0) // ldo_lp18_vio33_ulp_en #define PMIC_RTC_ANA_DA_LDO_LP18_ULP_EN (1 << 0) #define PMIC_RTC_ANA_DA_LDO_VIO33_ULP_EN (1 << 1) // vcore_ctrl0 #define PMIC_RTC_ANA_DA_VCORE_VOSEL(n) (((n)&0x1ff) << 0) // vcore_ctrl1 #define PMIC_RTC_ANA_DA_VCORE_VOTRIM_LP(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_DA_VCORE_VOTRIM(n) (((n)&0x1f) << 5) #define PMIC_RTC_ANA_DA_VCORE_ULP_RET (1 << 12) #define PMIC_RTC_ANA_DA_VCORE_ULP_EN (1 << 13) #define PMIC_RTC_ANA_RG_VCORE_LP_EN (1 << 14) // vrf_ctrl2 #define PMIC_RTC_ANA_DA_VRF_VOTRIM(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_DA_VRF_LP_EN (1 << 5) // vrf_ctrl3 #define PMIC_RTC_ANA_RG_VRF_VOSEL(n) (((n)&0x1ff) << 0) // vgen_ctrl0 #define PMIC_RTC_ANA_DA_VGEN_VOTRIM(n) (((n)&0x1f) << 0) #define PMIC_RTC_ANA_DA_VGEN_LP_EN (1 << 5) #define PMIC_RTC_ANA_PM2_LDO_MEM_POWERSEL (1 << 8) #define PMIC_RTC_ANA_SLP_LDO_MEM_POWERSEL_EN (1 << 9) // chgr_ctrl0 #define PMIC_RTC_ANA_CHGR_CV_V(n) (((n)&0x3f) << 0) #define PMIC_RTC_ANA_CHGR_DPM(n) (((n)&0x3) << 6) #define PMIC_RTC_ANA_CHGR_EXPOWER_DEVICE (1 << 8) #define PMIC_RTC_ANA_CHGR_PTEST (1 << 9) #define PMIC_RTC_ANA_CHGR_PD (1 << 10) // chgr_det_ctrl0 #define PMIC_RTC_ANA_CHG_INT_DELAY(n) (((n)&0x7) << 0) #define PMIC_RTC_ANA_RG_DP_DM_AUX_EN (1 << 4) #define PMIC_RTC_ANA_DP_DM_BC_ENB (1 << 5) // slp_ldo_pd_ctrl0 #define PMIC_RTC_ANA_SLP_LDOCAMA_PD_EN (1 << 2) #define PMIC_RTC_ANA_SLP_LDOCAMD_PD_EN (1 << 3) #define PMIC_RTC_ANA_SLP_LDOLCD_PD_EN (1 << 4) #define PMIC_RTC_ANA_SLP_LDOMMC_PD_EN (1 << 5) #define PMIC_RTC_ANA_SLP_LDOKPLED_PD_EN (1 << 6) #define PMIC_RTC_ANA_PM1_LDOUSB_PD_EN (1 << 7) #define PMIC_RTC_ANA_SLP_LDOSPIMEM_PD_EN (1 << 8) #define PMIC_RTC_ANA_SLP_LDORF15_PD_EN (1 << 9) #define PMIC_RTC_ANA_PM1_LDOVIO33_PD_EN (1 << 10) #define PMIC_RTC_ANA_PM1_LDODCXO_PD_EN (1 << 11) #define PMIC_RTC_ANA_PM1_LDOLP18_PD_EN (1 << 12) #define PMIC_RTC_ANA_SLP_LDORF12_PD_EN (1 << 13) #define PMIC_RTC_ANA_SLP_LDOANA_PD_EN (1 << 14) #define PMIC_RTC_ANA_PM1_LDOVIO18_PD_EN (1 << 15) // slp_ldo_pd_ctrl1 #define PMIC_RTC_ANA_PM1_LDOMEM_PD_EN (1 << 0) #define PMIC_RTC_ANA_LDO_XTL_EN (1 << 1) #define PMIC_RTC_ANA_SLP_IO_EN (1 << 2) #define PMIC_RTC_ANA_SLP_LDO_PD_EN (1 << 3) #define PMIC_RTC_ANA_PM1_LDOCP_PD_EN (1 << 4) // slp_dcdc_pd_ctrl #define PMIC_RTC_ANA_PM1_DCDCGEN_PD_EN (1 << 0) #define PMIC_RTC_ANA_SLP_DCDCVRF_PD_EN (1 << 1) #define PMIC_RTC_ANA_SLP_DCDCCORE_DROP_EN (1 << 3) #define PMIC_RTC_ANA_SLP_DCDCCORE_PU_RSTN_TH(n) (((n)&0x3f) << 6) #define PMIC_RTC_ANA_SLP_DCDCCORE_PD_RSTN_TH(n) (((n)&0xf) << 12) // dcdc_core_slp_ctrl0 #define PMIC_RTC_ANA_DCDC_CORE_SLP_STEP_EN (1 << 0) #define PMIC_RTC_ANA_PM1_DCDCCORE_PD_EN (1 << 1) #define PMIC_RTC_ANA_PM1_DCDC_CORE_SLP_STEP_VOL(n) (((n)&0x1f) << 3) #define PMIC_RTC_ANA_PM1_DCDC_CORE_SLP_STEP_NUM(n) (((n)&0xf) << 8) #define PMIC_RTC_ANA_PM1_DCDC_CORE_SLP_STEP_DELAY(n) (((n)&0x3) << 12) // dcdc_core_slp_ctrl1 #define PMIC_RTC_ANA_PM1_DCDC_CORE_VOSEL_DS_SW(n) (((n)&0x1ff) << 0) // slp_dcdc_lp_ctrl #define PMIC_RTC_ANA_PM1_DCDCGEN_LP_EN (1 << 1) #define PMIC_RTC_ANA_SLP_DCDCVRF_LP_EN (1 << 2) #define PMIC_RTC_ANA_PM1_DCDCCORE_LP_EN (1 << 4) // slp_ldo_lp_ctrl0 #define PMIC_RTC_ANA_SLP_LDOCAMA_LP_EN (1 << 2) #define PMIC_RTC_ANA_SLP_LDOCAMD_LP_EN (1 << 3) #define PMIC_RTC_ANA_SLP_LDOLCD_LP_EN (1 << 4) #define PMIC_RTC_ANA_PM1_LDOUSB_LP_EN (1 << 6) #define PMIC_RTC_ANA_SLP_LDOMMC_LP_EN (1 << 7) #define PMIC_RTC_ANA_SLP_LDOSPIMEM_LP_EN (1 << 8) #define PMIC_RTC_ANA_SLP_LDOANA_LP_EN (1 << 9) #define PMIC_RTC_ANA_PM1_LDOVIO18_LP_EN (1 << 10) #define PMIC_RTC_ANA_PM1_LDODCXO_LP_EN (1 << 11) #define PMIC_RTC_ANA_PM1_LDOVIO33_LP_EN (1 << 12) #define PMIC_RTC_ANA_SLP_LDORF12_LP_EN (1 << 13) #define PMIC_RTC_ANA_SLP_LDORF15_LP_EN (1 << 14) // slp_ldo_lp_ctrl1 #define PMIC_RTC_ANA_PM1_LDOMEM_LP_EN (1 << 0) #define PMIC_RTC_ANA_PM1_LDOLP18_LP_EN (1 << 3) #define PMIC_RTC_ANA_PM2_DCDC_CORE_VOSEL_DS_SW(n) (((n)&0x1ff) << 7) // reserved_reg_rtc #define PMIC_RTC_ANA_RESERVED_RTC(n) (((n)&0xffff) << 0) // dcdc_vlg_sel #define PMIC_RTC_ANA_DCDC_CORE_NOR_SW_SEL (1 << 0) #define PMIC_RTC_ANA_DCDC_CORE_SLP_SW_SEL (1 << 1) #define PMIC_RTC_ANA_DCDC_CORE_VOTRIM_SW_SEL (1 << 2) #define PMIC_RTC_ANA_DCDC_GEN_SW_SEL (1 << 3) // ldo_vlg_sel0 #define PMIC_RTC_ANA_LDO_VCORE_VOTRIM_SW_SEL (1 << 0) #define PMIC_RTC_ANA_LDO_VCORE_VOTRIM_ULP_SW_SEL (1 << 1) #define PMIC_RTC_ANA_VGEN_VOTRIM_SW_SEL (1 << 2) #define PMIC_RTC_ANA_VRF_VOTRIM_SW_SEL (1 << 4) #define PMIC_RTC_ANA_RTCBG_TRIM_SW_SEL (1 << 5) #define PMIC_RTC_ANA_DCDC_OSC3M_FREQ_SW_SEL (1 << 6) #define PMIC_RTC_ANA_VBAT_REFTRIM_SW_SEL (1 << 7) #define PMIC_RTC_ANA_VBAT_REFTRIM_ULP_SW_SEL (1 << 8) #define PMIC_RTC_ANA_VGEN_REFTRIM_SW_SEL (1 << 9) // clk32kless_ctrl0 #define PMIC_RTC_ANA_RC_32K_EN (1 << 0) #define PMIC_RTC_ANA_RC_32K_SEL (1 << 1) #define PMIC_RTC_ANA_RTC_MODE (1 << 4) #define PMIC_RTC_ANA_LDO_DCXO_LP_EN_RTCCLR (1 << 6) #define PMIC_RTC_ANA_LDO_DCXO_LP_EN_RTCSET (1 << 7) #define PMIC_RTC_ANA_RC_MODE_WR_ACK_FLAG_CLR (1 << 10) #define PMIC_RTC_ANA_RC_MODE_WR_ACK_FLAG (1 << 14) // clk32kless_ctrl1 #define PMIC_RTC_ANA_RC_MODE(n) (((n)&0xffff) << 0) // por_rst_monitor #define PMIC_RTC_ANA_POR_RST_MONITOR(n) (((n)&0xffff) << 0) // wdg_rst_monitor #define PMIC_RTC_ANA_WDG_RST_MONITOR(n) (((n)&0xffff) << 0) // por_pin_rst_monitor #define PMIC_RTC_ANA_POR_PIN_RST_MONITOR(n) (((n)&0xffff) << 0) // por_src_flag #define PMIC_RTC_ANA_POR_SRC_FLAG(n) (((n)&0x3fff) << 0) #define PMIC_RTC_ANA_REG_SOFT_RST_FLAG_CLR (1 << 14) #define PMIC_RTC_ANA_POR_SW_FORCE_ON (1 << 15) // por_7s_ctrl #define PMIC_RTC_ANA_PBINT_7S_RST_MODE (1 << 0) #define PMIC_RTC_ANA_PBINT_7S_RST_DISABLE (1 << 1) #define PMIC_RTC_ANA_PBINT_7S_AUTO_ON_EN (1 << 2) #define PMIC_RTC_ANA_EXT_RSTN_MODE (1 << 3) #define PMIC_RTC_ANA_PBINT_7S_RST_THRESHOLD(n) (((n)&0xf) << 4) #define PMIC_RTC_ANA_PBINT_7S_RST_SWMODE (1 << 8) #define PMIC_RTC_ANA_KEY2_7S_RST_EN (1 << 9) #define PMIC_RTC_ANA_PBINT_FLAG_CLR (1 << 11) #define PMIC_RTC_ANA_CHGR_INT_FLAG_CLR (1 << 13) #define PMIC_RTC_ANA_EXT_RSTN_FLAG_CLR (1 << 14) #define PMIC_RTC_ANA_PBINT_7S_FLAG_CLR (1 << 15) // hwrst_rtc #define PMIC_RTC_ANA_HWRST_RTC_REG_SET(n) (((n)&0xff) << 0) #define PMIC_RTC_ANA_HWRST_RTC_REG_STS(n) (((n)&0xff) << 8) // smpl_ctrl0 #define PMIC_RTC_ANA_SMPL_MODE(n) (((n)&0xffff) << 0) // rtc_rst0 #define PMIC_RTC_ANA_RTC_CLK_FLAG_SET(n) (((n)&0xffff) << 0) // rtc_rst1 #define PMIC_RTC_ANA_RTC_CLK_FLAG_CLR(n) (((n)&0xffff) << 0) // rtc_rst2 #define PMIC_RTC_ANA_RTC_CLK_FLAG_RTC(n) (((n)&0xffff) << 0) // rtc_clk_stop #define PMIC_RTC_ANA_RTC_CLK_STOP_THRESHOLD(n) (((n)&0x7f) << 0) #define PMIC_RTC_ANA_RTC_CLK_STOP_FLAG (1 << 7) // vbat_drop_cnt #define PMIC_RTC_ANA_VBAT_DROP_CNT(n) (((n)&0xfff) << 0) // mixed_ctrl #define PMIC_RTC_ANA_INT_DEBUG_EN (1 << 0) #define PMIC_RTC_ANA_ALL_INT_DEB (1 << 1) #define PMIC_RTC_ANA_GPI_DEBUG_EN (1 << 2) #define PMIC_RTC_ANA_ALL_GPI_DEB (1 << 3) #define PMIC_RTC_ANA_VBAT_OK (1 << 5) #define PMIC_RTC_ANA_BATDET_OK (1 << 8) #define PMIC_RTC_ANA_AD_BUADET (1 << 15) // por_off_flag #define PMIC_RTC_ANA_OTP_CHIP_PD_FLAG_CLR (1 << 2) #define PMIC_RTC_ANA_OTP_CHIP_PD_FLAG (1 << 3) #define PMIC_RTC_ANA_HW_CHIP_PD_FLAG_CLR (1 << 4) #define PMIC_RTC_ANA_HW_CHIP_PD_FLAG (1 << 5) #define PMIC_RTC_ANA_SW_CHIP_PD_FLAG_CLR (1 << 6) #define PMIC_RTC_ANA_SW_CHIP_PD_FLAG (1 << 7) #define PMIC_RTC_ANA_HARD_7S_CHIP_PD_FLAG_CLR (1 << 8) #define PMIC_RTC_ANA_HARD_7S_CHIP_PD_FLAG (1 << 9) #define PMIC_RTC_ANA_UVLO_CHIP_PD_FLAG_CLR (1 << 10) #define PMIC_RTC_ANA_UVLO_CHIP_PD_FLAG (1 << 11) #define PMIC_RTC_ANA_POR_CHIP_PD_FLAG_CLR (1 << 12) #define PMIC_RTC_ANA_POR_CHIP_PD_FLAG (1 << 13) // swrst_ctrl0 #define PMIC_RTC_ANA_SW_RST_PD_THRESHOLD(n) (((n)&0xf) << 0) #define PMIC_RTC_ANA_REG_RST_EN (1 << 4) #define PMIC_RTC_ANA_WDG_RST_PD_EN (1 << 7) #define PMIC_RTC_ANA_REG_RST_PD_EN (1 << 8) #define PMIC_RTC_ANA_PB_7S_RST_PD_EN (1 << 9) #define PMIC_RTC_ANA_EXT_RSTN_PD_EN (1 << 10) // swrst_ctrl1 #define PMIC_RTC_ANA_SW_RST_VIO33_PD_EN (1 << 2) #define PMIC_RTC_ANA_SW_RST_USB_PD_EN (1 << 3) #define PMIC_RTC_ANA_SW_RST_RF15_PD_EN (1 << 4) #define PMIC_RTC_ANA_SW_RST_ANA_PD_EN (1 << 5) #define PMIC_RTC_ANA_SW_RST_RF12_PD_EN (1 << 6) #define PMIC_RTC_ANA_SW_RST_DCXO_PD_EN (1 << 7) #define PMIC_RTC_ANA_SW_RST_MEM_PD_EN (1 << 8) #define PMIC_RTC_ANA_SW_RST_DCDCCORE_PD_EN (1 << 9) #define PMIC_RTC_ANA_SW_RST_DCDCGEN_PD_EN (1 << 10) #define PMIC_RTC_ANA_SW_RST_VIO18_PD_EN (1 << 14) #define PMIC_RTC_ANA_SW_RST_SPIMEM_PD_EN (1 << 15) // free_timer_low #define PMIC_RTC_ANA_TIMER_LOW(n) (((n)&0xffff) << 0) // free_timer_high #define PMIC_RTC_ANA_TIMER_HIGH(n) (((n)&0xffff) << 0) // reserved_reg1 #define PMIC_RTC_ANA_PM1_DVDD_EN (1 << 0) #define PMIC_RTC_ANA_PM1_OSW_3M_EN (1 << 1) #define PMIC_RTC_ANA_PM1_BG_PD_EN (1 << 2) #define PMIC_RTC_ANA_PM1_POWER_DET_EN (1 << 3) #define PMIC_RTC_ANA_UVLO_DBNC_EN (1 << 4) #define PMIC_RTC_ANA_OVLO_DBNC_EN (1 << 5) #define PMIC_RTC_ANA_PM1_LDO_MEM_POWERSEL (1 << 6) #define PMIC_RTC_ANA_PM2_DCDC_CORE_SLP_STEP_VOL(n) (((n)&0x1f) << 8) // reserved_reg2 #define PMIC_RTC_ANA_ULP_CYCLE_SEL0(n) (((n)&0xf) << 0) #define PMIC_RTC_ANA_ULP_CYCLE_SEL1(n) (((n)&0xf) << 4) #define PMIC_RTC_ANA_PM1_SLEEP_DLY1(n) (((n)&0xf) << 8) #define PMIC_RTC_ANA_PM1_SLEEP_DLY2(n) (((n)&0xf) << 12) // reserved_reg3 #define PMIC_RTC_ANA_UVLO_DBNC_TIME(n) (((n)&0xff) << 0) #define PMIC_RTC_ANA_OVLO_DBNC_TIME(n) (((n)&0xff) << 8) // reserved_reg4 #define PMIC_RTC_ANA_PM2_SLEEP_DLY1(n) (((n)&0xff) << 0) #define PMIC_RTC_ANA_PM2_SLEEP_DLY2(n) (((n)&0xff) << 8) // reserved_reg5 #define PMIC_RTC_ANA_PM2_LDOMEM_PD_EN (1 << 0) #define PMIC_RTC_ANA_PM2_LDOUSB_PD_EN (1 << 1) #define PMIC_RTC_ANA_PM2_LDOMEM_LP_EN (1 << 2) #define PMIC_RTC_ANA_PM2_LDOUSB_LP_EN (1 << 3) #define PMIC_RTC_ANA_PM2_DVDD_EN (1 << 4) #define PMIC_RTC_ANA_PM2_OSW_3M_EN (1 << 5) #define PMIC_RTC_ANA_PM2_SLP_BG_PD_EN (1 << 6) #define PMIC_RTC_ANA_PM2_POWER_DET_EN (1 << 7) #define PMIC_RTC_ANA_PM2_DCDC_CORE_SLP_STEP_NUM(n) (((n)&0xf) << 8) #define PMIC_RTC_ANA_PM2_DCDC_CORE_SLP_STEP_DELAY(n) (((n)&0x3) << 12) #define PMIC_RTC_ANA_PM2_LDOCP_PD_EN (1 << 14) // reserved_reg6 #define PMIC_RTC_ANA_PM2_EN (1 << 0) // pwr_wr_prot_value #define PMIC_RTC_ANA_PWR_WR_PROT_VALUE(n) (((n)&0x7fff) << 0) #define PMIC_RTC_ANA_PWR_WR_PROT (1 << 15) // vol_tune_ctrl_core #define PMIC_RTC_ANA_CORE_VOL_TUNE_EN (1 << 0) #define PMIC_RTC_ANA_CORE_VOL_TUNE_FLAG (1 << 1) #define PMIC_RTC_ANA_CORE_VOL_TUNE_START (1 << 2) #define PMIC_RTC_ANA_CORE_STEP_VOL(n) (((n)&0x1f) << 3) #define PMIC_RTC_ANA_CORE_STEP_NUM(n) (((n)&0xf) << 8) #define PMIC_RTC_ANA_CORE_STEP_DELAY(n) (((n)&0x3) << 12) #define PMIC_RTC_ANA_CORE_CLK_SEL (1 << 14) // smpl_ctrl1 #define PMIC_RTC_ANA_SMPL_EN (1 << 0) #define PMIC_RTC_ANA_SMPL_PWR_ON_SET (1 << 11) #define PMIC_RTC_ANA_SMPL_MODE_WR_ACK_FLAG_CLR (1 << 12) #define PMIC_RTC_ANA_SMPL_PWR_ON_FLAG_CLR (1 << 13) #define PMIC_RTC_ANA_SMPL_MODE_WR_ACK_FLAG (1 << 14) #define PMIC_RTC_ANA_SMPL_PWR_ON_FLAG (1 << 15) #endif // _PMIC_RTC_ANA_H_