/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _REG_FW_LPS_APB_H_ #define _REG_FW_LPS_APB_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_REG_FW_LPS_APB_BASE (0x51316000) typedef volatile struct { uint32_t reg_rd_ctrl_0; // 0x00000000 uint32_t reg_rd_ctrl_1; // 0x00000004 uint32_t reg_wr_ctrl_0; // 0x00000008 uint32_t reg_wr_ctrl_1; // 0x0000000c uint32_t bit_ctrl_addr_array0; // 0x00000010 uint32_t bit_ctrl_addr_array1; // 0x00000014 uint32_t bit_ctrl_addr_array2; // 0x00000018 uint32_t bit_ctrl_addr_array3; // 0x0000001c uint32_t bit_ctrl_addr_array4; // 0x00000020 uint32_t bit_ctrl_addr_array5; // 0x00000024 uint32_t bit_ctrl_addr_array6; // 0x00000028 uint32_t bit_ctrl_addr_array7; // 0x0000002c uint32_t bit_ctrl_array0; // 0x00000030 uint32_t bit_ctrl_array1; // 0x00000034 uint32_t bit_ctrl_array2; // 0x00000038 uint32_t bit_ctrl_array3; // 0x0000003c uint32_t bit_ctrl_array4; // 0x00000040 uint32_t bit_ctrl_array5; // 0x00000044 uint32_t bit_ctrl_array6; // 0x00000048 uint32_t bit_ctrl_array7; // 0x0000004c } HWP_REG_FW_LPS_APB_T; #define hwp_regFwLpsApb ((HWP_REG_FW_LPS_APB_T *)REG_ACCESS_ADDRESS(REG_REG_FW_LPS_APB_BASE)) // reg_rd_ctrl_0 typedef union { uint32_t v; struct { uint32_t reset_sys_soft_rd_sec : 1; // [0] uint32_t reset_lps_soft_rd_sec : 1; // [1] uint32_t efuse_por_read_disable_rd_sec : 1; // [2] uint32_t lps_clk_en_rd_sec : 1; // [3] uint32_t lps_clk_auto_sel_rd_sec : 1; // [4] uint32_t lps_clk_force_en_rd_sec : 1; // [5] uint32_t lps_clk_gate_en_status_rd_sec : 1; // [6] uint32_t lps_clk_busy_status_rd_sec : 1; // [7] uint32_t cfg_clk_uart1_rd_sec : 1; // [8] uint32_t cfg_clk_rc26m_rd_sec : 1; // [9] uint32_t cfg_debug_bond_option_rd_sec : 1; // [10] uint32_t cfg_psram_half_slp_rd_sec : 1; // [11] uint32_t cfg_lps_ahb_clock_sel_rd_sec : 1; // [12] uint32_t cfg_uart1_clock_sel_rd_sec : 1; // [13] uint32_t cfg_gpt_lite_clock_sel_rd_sec : 1; // [14] uint32_t cfg_boot_mode_rd_sec : 1; // [15] uint32_t cfg_reset_enable_rd_sec : 1; // [16] uint32_t reset_cause_rd_sec : 1; // [17] uint32_t cfg_plls_rd_sec : 1; // [18] uint32_t apll_wait_number_rd_sec : 1; // [19] uint32_t mpll_wait_number_rd_sec : 1; // [20] uint32_t iispll_wait_number_rd_sec : 1; // [21] uint32_t aon_iram_ctrl_rd_sec : 1; // [22] uint32_t iomux_g4_func_sel_latch_rd_sec : 1; // [23] uint32_t cfg_por_usb_phy_rd_sec : 1; // [24] uint32_t efs_por_read_block3_rd_sec : 1; // [25] uint32_t efs_por_read_block89_rd_sec : 1; // [26] uint32_t rc26m_pu_ctrl_rd_sec : 1; // [27] uint32_t aon_ahb_lp_ctrl_rd_sec : 1; // [28] uint32_t usb_uart_swj_share_cfg_rd_sec : 1; // [29] uint32_t pu_clk26m_lp_iso_cfg_rd_sec : 1; // [30] uint32_t cfg_io_deep_sleep_rd_sec : 1; // [31] } b; } REG_REG_FW_LPS_APB_REG_RD_CTRL_0_T; // reg_rd_ctrl_1 typedef union { uint32_t v; struct { uint32_t cfg_lps_io_core_ie_rd_sec : 1; // [0] uint32_t cfg_simc_io_rd_sec : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_REG_FW_LPS_APB_REG_RD_CTRL_1_T; // reg_wr_ctrl_0 typedef union { uint32_t v; struct { uint32_t reset_sys_soft_wr_sec : 1; // [0] uint32_t reset_lps_soft_wr_sec : 1; // [1] uint32_t efuse_por_read_disable_wr_sec : 1; // [2] uint32_t lps_clk_en_wr_sec : 1; // [3] uint32_t lps_clk_auto_sel_wr_sec : 1; // [4] uint32_t lps_clk_force_en_wr_sec : 1; // [5] uint32_t lps_clk_gate_en_status_wr_sec : 1; // [6] uint32_t lps_clk_busy_status_wr_sec : 1; // [7] uint32_t cfg_clk_uart1_wr_sec : 1; // [8] uint32_t cfg_clk_rc26m_wr_sec : 1; // [9] uint32_t cfg_debug_bond_option_wr_sec : 1; // [10] uint32_t cfg_psram_half_slp_wr_sec : 1; // [11] uint32_t cfg_lps_ahb_clock_sel_wr_sec : 1; // [12] uint32_t cfg_uart1_clock_sel_wr_sec : 1; // [13] uint32_t cfg_gpt_lite_clock_sel_wr_sec : 1; // [14] uint32_t cfg_boot_mode_wr_sec : 1; // [15] uint32_t cfg_reset_enable_wr_sec : 1; // [16] uint32_t reset_cause_wr_sec : 1; // [17] uint32_t cfg_plls_wr_sec : 1; // [18] uint32_t apll_wait_number_wr_sec : 1; // [19] uint32_t mpll_wait_number_wr_sec : 1; // [20] uint32_t iispll_wait_number_wr_sec : 1; // [21] uint32_t aon_iram_ctrl_wr_sec : 1; // [22] uint32_t iomux_g4_func_sel_latch_wr_sec : 1; // [23] uint32_t cfg_por_usb_phy_wr_sec : 1; // [24] uint32_t efs_por_read_block3_wr_sec : 1; // [25] uint32_t efs_por_read_block89_wr_sec : 1; // [26] uint32_t rc26m_pu_ctrl_wr_sec : 1; // [27] uint32_t aon_ahb_lp_ctrl_wr_sec : 1; // [28] uint32_t usb_uart_swj_share_cfg_wr_sec : 1; // [29] uint32_t pu_clk26m_lp_iso_cfg_wr_sec : 1; // [30] uint32_t cfg_io_deep_sleep_wr_sec : 1; // [31] } b; } REG_REG_FW_LPS_APB_REG_WR_CTRL_0_T; // reg_wr_ctrl_1 typedef union { uint32_t v; struct { uint32_t cfg_lps_io_core_ie_wr_sec : 1; // [0] uint32_t cfg_simc_io_wr_sec : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_REG_FW_LPS_APB_REG_WR_CTRL_1_T; // bit_ctrl_addr_array0 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array0 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY0_T; // bit_ctrl_addr_array1 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array1 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY1_T; // bit_ctrl_addr_array2 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array2 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY2_T; // bit_ctrl_addr_array3 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array3 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY3_T; // bit_ctrl_addr_array4 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array4 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY4_T; // bit_ctrl_addr_array5 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array5 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY5_T; // bit_ctrl_addr_array6 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array6 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY6_T; // bit_ctrl_addr_array7 typedef union { uint32_t v; struct { uint32_t bit_ctrl_addr_array7 : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY7_T; // reg_rd_ctrl_0 #define REG_FW_LPS_APB_RESET_SYS_SOFT_RD_SEC (1 << 0) #define REG_FW_LPS_APB_RESET_LPS_SOFT_RD_SEC (1 << 1) #define REG_FW_LPS_APB_EFUSE_POR_READ_DISABLE_RD_SEC (1 << 2) #define REG_FW_LPS_APB_LPS_CLK_EN_RD_SEC (1 << 3) #define REG_FW_LPS_APB_LPS_CLK_AUTO_SEL_RD_SEC (1 << 4) #define REG_FW_LPS_APB_LPS_CLK_FORCE_EN_RD_SEC (1 << 5) #define REG_FW_LPS_APB_LPS_CLK_GATE_EN_STATUS_RD_SEC (1 << 6) #define REG_FW_LPS_APB_LPS_CLK_BUSY_STATUS_RD_SEC (1 << 7) #define REG_FW_LPS_APB_CFG_CLK_UART1_RD_SEC (1 << 8) #define REG_FW_LPS_APB_CFG_CLK_RC26M_RD_SEC (1 << 9) #define REG_FW_LPS_APB_CFG_DEBUG_BOND_OPTION_RD_SEC (1 << 10) #define REG_FW_LPS_APB_CFG_PSRAM_HALF_SLP_RD_SEC (1 << 11) #define REG_FW_LPS_APB_CFG_LPS_AHB_CLOCK_SEL_RD_SEC (1 << 12) #define REG_FW_LPS_APB_CFG_UART1_CLOCK_SEL_RD_SEC (1 << 13) #define REG_FW_LPS_APB_CFG_GPT_LITE_CLOCK_SEL_RD_SEC (1 << 14) #define REG_FW_LPS_APB_CFG_BOOT_MODE_RD_SEC (1 << 15) #define REG_FW_LPS_APB_CFG_RESET_ENABLE_RD_SEC (1 << 16) #define REG_FW_LPS_APB_RESET_CAUSE_RD_SEC (1 << 17) #define REG_FW_LPS_APB_CFG_PLLS_RD_SEC (1 << 18) #define REG_FW_LPS_APB_APLL_WAIT_NUMBER_RD_SEC (1 << 19) #define REG_FW_LPS_APB_MPLL_WAIT_NUMBER_RD_SEC (1 << 20) #define REG_FW_LPS_APB_IISPLL_WAIT_NUMBER_RD_SEC (1 << 21) #define REG_FW_LPS_APB_AON_IRAM_CTRL_RD_SEC (1 << 22) #define REG_FW_LPS_APB_IOMUX_G4_FUNC_SEL_LATCH_RD_SEC (1 << 23) #define REG_FW_LPS_APB_CFG_POR_USB_PHY_RD_SEC (1 << 24) #define REG_FW_LPS_APB_EFS_POR_READ_BLOCK3_RD_SEC (1 << 25) #define REG_FW_LPS_APB_EFS_POR_READ_BLOCK89_RD_SEC (1 << 26) #define REG_FW_LPS_APB_RC26M_PU_CTRL_RD_SEC (1 << 27) #define REG_FW_LPS_APB_AON_AHB_LP_CTRL_RD_SEC (1 << 28) #define REG_FW_LPS_APB_USB_UART_SWJ_SHARE_CFG_RD_SEC (1 << 29) #define REG_FW_LPS_APB_PU_CLK26M_LP_ISO_CFG_RD_SEC (1 << 30) #define REG_FW_LPS_APB_CFG_IO_DEEP_SLEEP_RD_SEC (1 << 31) // reg_rd_ctrl_1 #define REG_FW_LPS_APB_CFG_LPS_IO_CORE_IE_RD_SEC (1 << 0) #define REG_FW_LPS_APB_CFG_SIMC_IO_RD_SEC (1 << 1) // reg_wr_ctrl_0 #define REG_FW_LPS_APB_RESET_SYS_SOFT_WR_SEC (1 << 0) #define REG_FW_LPS_APB_RESET_LPS_SOFT_WR_SEC (1 << 1) #define REG_FW_LPS_APB_EFUSE_POR_READ_DISABLE_WR_SEC (1 << 2) #define REG_FW_LPS_APB_LPS_CLK_EN_WR_SEC (1 << 3) #define REG_FW_LPS_APB_LPS_CLK_AUTO_SEL_WR_SEC (1 << 4) #define REG_FW_LPS_APB_LPS_CLK_FORCE_EN_WR_SEC (1 << 5) #define REG_FW_LPS_APB_LPS_CLK_GATE_EN_STATUS_WR_SEC (1 << 6) #define REG_FW_LPS_APB_LPS_CLK_BUSY_STATUS_WR_SEC (1 << 7) #define REG_FW_LPS_APB_CFG_CLK_UART1_WR_SEC (1 << 8) #define REG_FW_LPS_APB_CFG_CLK_RC26M_WR_SEC (1 << 9) #define REG_FW_LPS_APB_CFG_DEBUG_BOND_OPTION_WR_SEC (1 << 10) #define REG_FW_LPS_APB_CFG_PSRAM_HALF_SLP_WR_SEC (1 << 11) #define REG_FW_LPS_APB_CFG_LPS_AHB_CLOCK_SEL_WR_SEC (1 << 12) #define REG_FW_LPS_APB_CFG_UART1_CLOCK_SEL_WR_SEC (1 << 13) #define REG_FW_LPS_APB_CFG_GPT_LITE_CLOCK_SEL_WR_SEC (1 << 14) #define REG_FW_LPS_APB_CFG_BOOT_MODE_WR_SEC (1 << 15) #define REG_FW_LPS_APB_CFG_RESET_ENABLE_WR_SEC (1 << 16) #define REG_FW_LPS_APB_RESET_CAUSE_WR_SEC (1 << 17) #define REG_FW_LPS_APB_CFG_PLLS_WR_SEC (1 << 18) #define REG_FW_LPS_APB_APLL_WAIT_NUMBER_WR_SEC (1 << 19) #define REG_FW_LPS_APB_MPLL_WAIT_NUMBER_WR_SEC (1 << 20) #define REG_FW_LPS_APB_IISPLL_WAIT_NUMBER_WR_SEC (1 << 21) #define REG_FW_LPS_APB_AON_IRAM_CTRL_WR_SEC (1 << 22) #define REG_FW_LPS_APB_IOMUX_G4_FUNC_SEL_LATCH_WR_SEC (1 << 23) #define REG_FW_LPS_APB_CFG_POR_USB_PHY_WR_SEC (1 << 24) #define REG_FW_LPS_APB_EFS_POR_READ_BLOCK3_WR_SEC (1 << 25) #define REG_FW_LPS_APB_EFS_POR_READ_BLOCK89_WR_SEC (1 << 26) #define REG_FW_LPS_APB_RC26M_PU_CTRL_WR_SEC (1 << 27) #define REG_FW_LPS_APB_AON_AHB_LP_CTRL_WR_SEC (1 << 28) #define REG_FW_LPS_APB_USB_UART_SWJ_SHARE_CFG_WR_SEC (1 << 29) #define REG_FW_LPS_APB_PU_CLK26M_LP_ISO_CFG_WR_SEC (1 << 30) #define REG_FW_LPS_APB_CFG_IO_DEEP_SLEEP_WR_SEC (1 << 31) // reg_wr_ctrl_1 #define REG_FW_LPS_APB_CFG_LPS_IO_CORE_IE_WR_SEC (1 << 0) #define REG_FW_LPS_APB_CFG_SIMC_IO_WR_SEC (1 << 1) // bit_ctrl_addr_array0 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY0(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array1 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY1(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array2 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY2(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array3 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY3(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array4 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY4(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array5 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY5(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array6 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY6(n) (((n)&0xfff) << 0) // bit_ctrl_addr_array7 #define REG_FW_LPS_APB_BIT_CTRL_ADDR_ARRAY7(n) (((n)&0xfff) << 0) #endif // _REG_FW_LPS_APB_H_