/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _RF_ANA_H_ #define _RF_ANA_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_RF_ANA_SET_OFFSET (1024) #define REG_RF_ANA_CLR_OFFSET (2048) #define REG_RF_ANA_BASE (0x50031000) typedef volatile struct { uint32_t bandgap_ctrl_0; // 0x00000000 uint32_t ldo_pu_ctrl_0; // 0x00000004 uint32_t ldo_pu_ctrl_1; // 0x00000008 uint32_t ldo_pu_ctrl_2; // 0x0000000c uint32_t trx_pu_0; // 0x00000010 uint32_t trx_pu_1; // 0x00000014 uint32_t trx_pu_2; // 0x00000018 uint32_t trx_pu_3; // 0x0000001c uint32_t trx_pu_4; // 0x00000020 uint32_t trx_pu_5; // 0x00000024 uint32_t mdll_ctrl_0; // 0x00000028 uint32_t mdll_ctrl_1; // 0x0000002c uint32_t xtal_ctrl_0; // 0x00000030 uint32_t rxvco_ldo_ctrl; // 0x00000034 uint32_t rxvco_buf_ldo_ctrl; // 0x00000038 uint32_t rxvco_ctrl_0; // 0x0000003c uint32_t rxvco_ctrl_1; // 0x00000040 uint32_t rxvco_ctrl_2; // 0x00000044 uint32_t rxpll_ldo_ctrl_0; // 0x00000048 uint32_t rxpll_ldo_ctrl_1; // 0x0000004c uint32_t rxpll_ldo_ctrl_2; // 0x00000050 uint32_t rxpll_gro_ctrl_0; // 0x00000054 uint32_t rxpll_gro_ctrl_1; // 0x00000058 uint32_t rxpll_gro_ctrl_2; // 0x0000005c uint32_t rxpll_gro_ctrl_3; // 0x00000060 uint32_t rxpll_ctrl_0; // 0x00000064 uint32_t lna_sel_ctrl; // 0x00000068 uint32_t lna_ctrl; // 0x0000006c uint32_t lna_pkd_ctrl; // 0x00000070 uint32_t rxmixer_ctrl; // 0x00000074 uint32_t pga_ctrl_0; // 0x00000078 uint32_t pga_ctrl_1; // 0x0000007c uint32_t pga_ctrl_2; // 0x00000080 uint32_t pga_ctrl_3; // 0x00000084 uint32_t rxabb_dccal_ctrl_0; // 0x00000088 uint32_t rxabb_dccal_ctrl_1; // 0x0000008c uint32_t rxflt_ctrl_0; // 0x00000090 uint32_t rxflt_ctrl_1; // 0x00000094 uint32_t rxflt_ctrl_2; // 0x00000098 uint32_t adc_ldo_ctrl; // 0x0000009c uint32_t adc_ctrl_0; // 0x000000a0 uint32_t adc_ctrl_1; // 0x000000a4 uint32_t adc_ctrl_2; // 0x000000a8 uint32_t adc_ctrl_3; // 0x000000ac uint32_t adc_rsv_0; // 0x000000b0 uint32_t pwdadc_ctrl_0; // 0x000000b4 uint32_t pwdadc_ctrl_1; // 0x000000b8 uint32_t pwdadc_ctrl_2; // 0x000000bc uint32_t pwdadc_ctrl_3; // 0x000000c0 uint32_t rx_gain_ctrl; // 0x000000c4 uint32_t rx_reserve1; // 0x000000c8 uint32_t rx_reserve2; // 0x000000cc uint32_t rx_reserve3; // 0x000000d0 uint32_t txvco_ldo_ctrl; // 0x000000d4 uint32_t txvco_buf_ldo_ctrl; // 0x000000d8 uint32_t txvco_ctrl_0; // 0x000000dc uint32_t txvco_ctrl_1; // 0x000000e0 uint32_t txvco_ctrl_2; // 0x000000e4 uint32_t txpll_ldo_ctrl_0; // 0x000000e8 uint32_t txpll_ldo_ctrl_1; // 0x000000ec uint32_t txpll_ldo_ctrl_2; // 0x000000f0 uint32_t txpll_gro_ctrl_0; // 0x000000f4 uint32_t txpll_gro_ctrl_1; // 0x000000f8 uint32_t txpll_gro_ctrl_2; // 0x000000fc uint32_t txpll_gro_ctrl_3; // 0x00000100 uint32_t txpll_ctrl_0; // 0x00000104 uint32_t txrf_gain; // 0x00000108 uint32_t txrf_gain_compensation; // 0x0000010c uint32_t txrf_gain_adj; // 0x00000110 uint32_t txrf_matchcap; // 0x00000114 uint32_t txflt_ctrl_0; // 0x00000118 uint32_t txflt_ctrl_1; // 0x0000011c uint32_t dac_ctrl_0; // 0x00000120 uint32_t dac_ctrl_1; // 0x00000124 uint32_t gnss_clkgen_ctrl_0; // 0x00000128 uint32_t gnss_clkgen_ctrl_1; // 0x0000012c uint32_t gnss_clkgen_ctrl_2; // 0x00000130 uint32_t gnss_clkgen_ctrl_3; // 0x00000134 uint32_t gnss_clkgen_ctrl_4; // 0x00000138 uint32_t rxflt_dccal; // 0x0000013c uint32_t tx_reserve_0; // 0x00000140 uint32_t tx_reserve_1; // 0x00000144 uint32_t pwd_ctrl_0; // 0x00000148 uint32_t pwd_ctrl_1; // 0x0000014c uint32_t pwd_ctrl_2; // 0x00000150 uint32_t ts_ctrl_0; // 0x00000154 uint32_t ts_ctrl_1; // 0x00000158 uint32_t ts_ctrl_2; // 0x0000015c uint32_t cm_reserve1; // 0x00000160 uint32_t cm_reserve2; // 0x00000164 uint32_t cm_reserve3; // 0x00000168 uint32_t revid_reg; // 0x0000016c uint32_t test_ctrl_0; // 0x00000170 uint32_t test_ctrl_1; // 0x00000174 uint32_t cal_ctrl_0; // 0x00000178 uint32_t rf_output_readonly_0; // 0x0000017c uint32_t rf_output_readonly_1; // 0x00000180 uint32_t tsenadc_ctrl_0; // 0x00000184 uint32_t tsenadc_ctrl_1; // 0x00000188 uint32_t tsenadc_ctrl_2; // 0x0000018c uint32_t apc_ctrl_0; // 0x00000190 uint32_t apc_ctrl_1; // 0x00000194 uint32_t __408[154]; // 0x00000198 uint32_t bandgap_ctrl_0_set; // 0x00000400 uint32_t ldo_pu_ctrl_0_set; // 0x00000404 uint32_t ldo_pu_ctrl_1_set; // 0x00000408 uint32_t ldo_pu_ctrl_2_set; // 0x0000040c uint32_t trx_pu_0_set; // 0x00000410 uint32_t trx_pu_1_set; // 0x00000414 uint32_t trx_pu_2_set; // 0x00000418 uint32_t trx_pu_3_set; // 0x0000041c uint32_t trx_pu_4_set; // 0x00000420 uint32_t trx_pu_5_set; // 0x00000424 uint32_t mdll_ctrl_0_set; // 0x00000428 uint32_t mdll_ctrl_1_set; // 0x0000042c uint32_t xtal_ctrl_0_set; // 0x00000430 uint32_t rxvco_ldo_ctrl_set; // 0x00000434 uint32_t rxvco_buf_ldo_ctrl_set; // 0x00000438 uint32_t rxvco_ctrl_0_set; // 0x0000043c uint32_t rxvco_ctrl_1_set; // 0x00000440 uint32_t rxvco_ctrl_2_set; // 0x00000444 uint32_t rxpll_ldo_ctrl_0_set; // 0x00000448 uint32_t rxpll_ldo_ctrl_1_set; // 0x0000044c uint32_t rxpll_ldo_ctrl_2_set; // 0x00000450 uint32_t rxpll_gro_ctrl_0_set; // 0x00000454 uint32_t rxpll_gro_ctrl_1_set; // 0x00000458 uint32_t rxpll_gro_ctrl_2_set; // 0x0000045c uint32_t rxpll_gro_ctrl_3_set; // 0x00000460 uint32_t rxpll_ctrl_0_set; // 0x00000464 uint32_t lna_sel_ctrl_set; // 0x00000468 uint32_t lna_ctrl_set; // 0x0000046c uint32_t lna_pkd_ctrl_set; // 0x00000470 uint32_t rxmixer_ctrl_set; // 0x00000474 uint32_t pga_ctrl_0_set; // 0x00000478 uint32_t pga_ctrl_1_set; // 0x0000047c uint32_t pga_ctrl_2_set; // 0x00000480 uint32_t pga_ctrl_3_set; // 0x00000484 uint32_t rxabb_dccal_ctrl_0_set; // 0x00000488 uint32_t rxabb_dccal_ctrl_1_set; // 0x0000048c uint32_t rxflt_ctrl_0_set; // 0x00000490 uint32_t rxflt_ctrl_1_set; // 0x00000494 uint32_t rxflt_ctrl_2_set; // 0x00000498 uint32_t adc_ldo_ctrl_set; // 0x0000049c uint32_t adc_ctrl_0_set; // 0x000004a0 uint32_t adc_ctrl_1_set; // 0x000004a4 uint32_t adc_ctrl_2_set; // 0x000004a8 uint32_t adc_ctrl_3_set; // 0x000004ac uint32_t adc_rsv_0_set; // 0x000004b0 uint32_t pwdadc_ctrl_0_set; // 0x000004b4 uint32_t pwdadc_ctrl_1_set; // 0x000004b8 uint32_t pwdadc_ctrl_2_set; // 0x000004bc uint32_t pwdadc_ctrl_3_set; // 0x000004c0 uint32_t rx_gain_ctrl_set; // 0x000004c4 uint32_t rx_reserve1_set; // 0x000004c8 uint32_t rx_reserve2_set; // 0x000004cc uint32_t rx_reserve3_set; // 0x000004d0 uint32_t txvco_ldo_ctrl_set; // 0x000004d4 uint32_t txvco_buf_ldo_ctrl_set; // 0x000004d8 uint32_t txvco_ctrl_0_set; // 0x000004dc uint32_t txvco_ctrl_1_set; // 0x000004e0 uint32_t txvco_ctrl_2_set; // 0x000004e4 uint32_t txpll_ldo_ctrl_0_set; // 0x000004e8 uint32_t txpll_ldo_ctrl_1_set; // 0x000004ec uint32_t txpll_ldo_ctrl_2_set; // 0x000004f0 uint32_t txpll_gro_ctrl_0_set; // 0x000004f4 uint32_t txpll_gro_ctrl_1_set; // 0x000004f8 uint32_t txpll_gro_ctrl_2_set; // 0x000004fc uint32_t txpll_gro_ctrl_3_set; // 0x00000500 uint32_t txpll_ctrl_0_set; // 0x00000504 uint32_t txrf_gain_set; // 0x00000508 uint32_t txrf_gain_compensation_set; // 0x0000050c uint32_t txrf_gain_adj_set; // 0x00000510 uint32_t txrf_matchcap_set; // 0x00000514 uint32_t txflt_ctrl_0_set; // 0x00000518 uint32_t txflt_ctrl_1_set; // 0x0000051c uint32_t dac_ctrl_0_set; // 0x00000520 uint32_t dac_ctrl_1_set; // 0x00000524 uint32_t gnss_clkgen_ctrl_0_set; // 0x00000528 uint32_t gnss_clkgen_ctrl_1_set; // 0x0000052c uint32_t gnss_clkgen_ctrl_2_set; // 0x00000530 uint32_t gnss_clkgen_ctrl_3_set; // 0x00000534 uint32_t gnss_clkgen_ctrl_4_set; // 0x00000538 uint32_t rxflt_dccal_set; // 0x0000053c uint32_t tx_reserve_0_set; // 0x00000540 uint32_t tx_reserve_1_set; // 0x00000544 uint32_t pwd_ctrl_0_set; // 0x00000548 uint32_t pwd_ctrl_1_set; // 0x0000054c uint32_t pwd_ctrl_2_set; // 0x00000550 uint32_t ts_ctrl_0_set; // 0x00000554 uint32_t ts_ctrl_1_set; // 0x00000558 uint32_t ts_ctrl_2_set; // 0x0000055c uint32_t cm_reserve1_set; // 0x00000560 uint32_t cm_reserve2_set; // 0x00000564 uint32_t cm_reserve3_set; // 0x00000568 uint32_t __1388[1]; // 0x0000056c uint32_t test_ctrl_0_set; // 0x00000570 uint32_t test_ctrl_1_set; // 0x00000574 uint32_t cal_ctrl_0_set; // 0x00000578 uint32_t __1404[2]; // 0x0000057c uint32_t tsenadc_ctrl_0_set; // 0x00000584 uint32_t tsenadc_ctrl_1_set; // 0x00000588 uint32_t tsenadc_ctrl_2_set; // 0x0000058c uint32_t apc_ctrl_0_set; // 0x00000590 uint32_t apc_ctrl_1_set; // 0x00000594 uint32_t __1432[154]; // 0x00000598 uint32_t bandgap_ctrl_0_clr; // 0x00000800 uint32_t ldo_pu_ctrl_0_clr; // 0x00000804 uint32_t ldo_pu_ctrl_1_clr; // 0x00000808 uint32_t ldo_pu_ctrl_2_clr; // 0x0000080c uint32_t trx_pu_0_clr; // 0x00000810 uint32_t trx_pu_1_clr; // 0x00000814 uint32_t trx_pu_2_clr; // 0x00000818 uint32_t trx_pu_3_clr; // 0x0000081c uint32_t trx_pu_4_clr; // 0x00000820 uint32_t trx_pu_5_clr; // 0x00000824 uint32_t mdll_ctrl_0_clr; // 0x00000828 uint32_t mdll_ctrl_1_clr; // 0x0000082c uint32_t xtal_ctrl_0_clr; // 0x00000830 uint32_t rxvco_ldo_ctrl_clr; // 0x00000834 uint32_t rxvco_buf_ldo_ctrl_clr; // 0x00000838 uint32_t rxvco_ctrl_0_clr; // 0x0000083c uint32_t rxvco_ctrl_1_clr; // 0x00000840 uint32_t rxvco_ctrl_2_clr; // 0x00000844 uint32_t rxpll_ldo_ctrl_0_clr; // 0x00000848 uint32_t rxpll_ldo_ctrl_1_clr; // 0x0000084c uint32_t rxpll_ldo_ctrl_2_clr; // 0x00000850 uint32_t rxpll_gro_ctrl_0_clr; // 0x00000854 uint32_t rxpll_gro_ctrl_1_clr; // 0x00000858 uint32_t rxpll_gro_ctrl_2_clr; // 0x0000085c uint32_t rxpll_gro_ctrl_3_clr; // 0x00000860 uint32_t rxpll_ctrl_0_clr; // 0x00000864 uint32_t lna_sel_ctrl_clr; // 0x00000868 uint32_t lna_ctrl_clr; // 0x0000086c uint32_t lna_pkd_ctrl_clr; // 0x00000870 uint32_t rxmixer_ctrl_clr; // 0x00000874 uint32_t pga_ctrl_0_clr; // 0x00000878 uint32_t pga_ctrl_1_clr; // 0x0000087c uint32_t pga_ctrl_2_clr; // 0x00000880 uint32_t pga_ctrl_3_clr; // 0x00000884 uint32_t rxabb_dccal_ctrl_0_clr; // 0x00000888 uint32_t rxabb_dccal_ctrl_1_clr; // 0x0000088c uint32_t rxflt_ctrl_0_clr; // 0x00000890 uint32_t rxflt_ctrl_1_clr; // 0x00000894 uint32_t rxflt_ctrl_2_clr; // 0x00000898 uint32_t adc_ldo_ctrl_clr; // 0x0000089c uint32_t adc_ctrl_0_clr; // 0x000008a0 uint32_t adc_ctrl_1_clr; // 0x000008a4 uint32_t adc_ctrl_2_clr; // 0x000008a8 uint32_t adc_ctrl_3_clr; // 0x000008ac uint32_t adc_rsv_0_clr; // 0x000008b0 uint32_t pwdadc_ctrl_0_clr; // 0x000008b4 uint32_t pwdadc_ctrl_1_clr; // 0x000008b8 uint32_t pwdadc_ctrl_2_clr; // 0x000008bc uint32_t pwdadc_ctrl_3_clr; // 0x000008c0 uint32_t rx_gain_ctrl_clr; // 0x000008c4 uint32_t rx_reserve1_clr; // 0x000008c8 uint32_t rx_reserve2_clr; // 0x000008cc uint32_t rx_reserve3_clr; // 0x000008d0 uint32_t txvco_ldo_ctrl_clr; // 0x000008d4 uint32_t txvco_buf_ldo_ctrl_clr; // 0x000008d8 uint32_t txvco_ctrl_0_clr; // 0x000008dc uint32_t txvco_ctrl_1_clr; // 0x000008e0 uint32_t txvco_ctrl_2_clr; // 0x000008e4 uint32_t txpll_ldo_ctrl_0_clr; // 0x000008e8 uint32_t txpll_ldo_ctrl_1_clr; // 0x000008ec uint32_t txpll_ldo_ctrl_2_clr; // 0x000008f0 uint32_t txpll_gro_ctrl_0_clr; // 0x000008f4 uint32_t txpll_gro_ctrl_1_clr; // 0x000008f8 uint32_t txpll_gro_ctrl_2_clr; // 0x000008fc uint32_t txpll_gro_ctrl_3_clr; // 0x00000900 uint32_t txpll_ctrl_0_clr; // 0x00000904 uint32_t txrf_gain_clr; // 0x00000908 uint32_t txrf_gain_compensation_clr; // 0x0000090c uint32_t txrf_gain_adj_clr; // 0x00000910 uint32_t txrf_matchcap_clr; // 0x00000914 uint32_t txflt_ctrl_0_clr; // 0x00000918 uint32_t txflt_ctrl_1_clr; // 0x0000091c uint32_t dac_ctrl_0_clr; // 0x00000920 uint32_t dac_ctrl_1_clr; // 0x00000924 uint32_t gnss_clkgen_ctrl_0_clr; // 0x00000928 uint32_t gnss_clkgen_ctrl_1_clr; // 0x0000092c uint32_t gnss_clkgen_ctrl_2_clr; // 0x00000930 uint32_t gnss_clkgen_ctrl_3_clr; // 0x00000934 uint32_t gnss_clkgen_ctrl_4_clr; // 0x00000938 uint32_t rxflt_dccal_clr; // 0x0000093c uint32_t tx_reserve_0_clr; // 0x00000940 uint32_t tx_reserve_1_clr; // 0x00000944 uint32_t pwd_ctrl_0_clr; // 0x00000948 uint32_t pwd_ctrl_1_clr; // 0x0000094c uint32_t pwd_ctrl_2_clr; // 0x00000950 uint32_t ts_ctrl_0_clr; // 0x00000954 uint32_t ts_ctrl_1_clr; // 0x00000958 uint32_t ts_ctrl_2_clr; // 0x0000095c uint32_t cm_reserve1_clr; // 0x00000960 uint32_t cm_reserve2_clr; // 0x00000964 uint32_t cm_reserve3_clr; // 0x00000968 uint32_t __2412[1]; // 0x0000096c uint32_t test_ctrl_0_clr; // 0x00000970 uint32_t test_ctrl_1_clr; // 0x00000974 uint32_t cal_ctrl_0_clr; // 0x00000978 uint32_t __2428[2]; // 0x0000097c uint32_t tsenadc_ctrl_0_clr; // 0x00000984 uint32_t tsenadc_ctrl_1_clr; // 0x00000988 uint32_t tsenadc_ctrl_2_clr; // 0x0000098c uint32_t apc_ctrl_0_clr; // 0x00000990 uint32_t apc_ctrl_1_clr; // 0x00000994 } HWP_RF_ANA_T; #define hwp_rfAna ((HWP_RF_ANA_T *)REG_ACCESS_ADDRESS(REG_RF_ANA_BASE)) // bandgap_ctrl_0 typedef union { uint32_t v; struct { uint32_t __6_0 : 7; // [6:0] uint32_t ldo_levelshifter_cp_tune : 2; // [8:7] uint32_t ldo_levelshifter_out : 3; // [11:9] uint32_t bg_cal_r_d_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_BANDGAP_CTRL_0_T; // ldo_pu_ctrl_0 typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t pwdadc_ldo_en_bb : 1; // [4] uint32_t pwdadc_ldo_bias_en_bb : 1; // [5] uint32_t dac_ldo_fc_pulse_bb : 1; // [6] uint32_t dac_ldo_en_bb : 1; // [7] uint32_t txflt_ldo_fc_pulse_bb : 1; // [8] uint32_t txflt_ldo_en_bb : 1; // [9] uint32_t adc_ldo_en_bb : 1; // [10] uint32_t adc_ldo_bias_en_bb : 1; // [11] uint32_t rxabb_ldo_fc_pulse_bb : 1; // [12] uint32_t rxabb_ldo_en_bb : 1; // [13] uint32_t lna_ldo_fast_charge_en_bb : 1; // [14] uint32_t lna_ldo_en_in_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LDO_PU_CTRL_0_T; // ldo_pu_ctrl_1 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t rxvco_tc_fc_bb : 1; // [1] uint32_t rxvco_tc_en_bb : 1; // [2] uint32_t rxvco_buf_ldo_load_bb : 1; // [3] uint32_t rxvco_buf_ldo_fc_bb : 1; // [4] uint32_t rxvco_buf_ldo_en_bb : 1; // [5] uint32_t rxvco_ldo_load_bb : 1; // [6] uint32_t rxvco_ldo_fc_bb : 1; // [7] uint32_t rxvco_ldo_en_bb : 1; // [8] uint32_t rxpll_rdac_ldo_vref_fc_en_bb : 1; // [9] uint32_t rxpll_rdac_ldo_vref_en_bb : 1; // [10] uint32_t rxpll_rdac_ldo_dig_en_bb : 1; // [11] uint32_t rxpll_presc_ldo_fast_charge_en_bb : 1; // [12] uint32_t rxpll_presc_ldo_en_bb : 1; // [13] uint32_t rxpll_gro_ldo_en_bb : 1; // [14] uint32_t rxpll_gro_ldo_bias_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LDO_PU_CTRL_1_T; // ldo_pu_ctrl_2 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t txvco_tc_fc_bb : 1; // [1] uint32_t txvco_tc_en_bb : 1; // [2] uint32_t txvcobuf_ldo_load_bb : 1; // [3] uint32_t txvcobuf_ldo_fc_bb : 1; // [4] uint32_t txvcobuf_ldo_en_bb : 1; // [5] uint32_t txvco_ldo_load_bb : 1; // [6] uint32_t txvco_ldo_fc_bb : 1; // [7] uint32_t txvco_ldo_en_bb : 1; // [8] uint32_t txpll_rdac_ldo_vref_fc_en_bb : 1; // [9] uint32_t txpll_rdac_ldo_vref_en_bb : 1; // [10] uint32_t txpll_rdac_ldo_dig_en_bb : 1; // [11] uint32_t txpll_presc_ldo_fast_charge_en_bb : 1; // [12] uint32_t txpll_presc_ldo_en_bb : 1; // [13] uint32_t txpll_gro_ldo_en_bb : 1; // [14] uint32_t txpll_gro_ldo_bias_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LDO_PU_CTRL_2_T; // trx_pu_0 typedef union { uint32_t v; struct { uint32_t __11_0 : 12; // [11:0] uint32_t pu_xdrv_bb : 1; // [12] uint32_t mdll_startup_bb : 1; // [13] uint32_t pu_mdll_bb : 1; // [14] uint32_t pu_bg_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TRX_PU_0_T; // trx_pu_1 typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t rxpll_rdac_rstn_bb : 1; // [6] uint32_t rxpll_gro_rstn_bb : 1; // [7] uint32_t pu_rxpll_rdac_bb : 1; // [8] uint32_t pu_rxpll_gro_bb : 1; // [9] uint32_t pu_rxpll_presc_bb : 1; // [10] uint32_t rxvco_pkdet_en_bb : 1; // [11] uint32_t rxvco_vcol_sel_bb : 1; // [12] uint32_t rxvco_vcoh_sel_bb : 1; // [13] uint32_t rxvco_ibias_en_bb : 1; // [14] uint32_t rxvco_bias_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TRX_PU_1_T; // trx_pu_2 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t adc_rstn_bb : 1; // [1] uint32_t adc_enh_bb : 1; // [2] uint32_t adc_clk_enh_bb : 1; // [3] uint32_t adc_ref_enh_bb : 1; // [4] uint32_t adc_bias_en_bb : 1; // [5] uint32_t pu_tia_bb : 1; // [6] uint32_t pu_rxmixer_bb : 1; // [7] uint32_t rxflt_en_bb : 1; // [8] uint32_t rxflt_rstn_bb : 1; // [9] uint32_t pu_rxflt_bb : 1; // [10] uint32_t pu_pga_bb : 1; // [11] uint32_t pga_pkd_en_bb : 1; // [12] uint32_t pga_en_bb : 1; // [13] uint32_t lna_pkd_en_bb : 1; // [14] uint32_t pu_lna_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TRX_PU_2_T; // trx_pu_3 typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t txpll_rdac_rstn_bb : 1; // [6] uint32_t txpll_gro_rstn_bb : 1; // [7] uint32_t pu_txpll_rdac_bb : 1; // [8] uint32_t pu_txpll_gro_bb : 1; // [9] uint32_t pu_txpll_presc_bb : 1; // [10] uint32_t txvco_pkdet_en_bb : 1; // [11] uint32_t txvco_vcol_sel_bb : 1; // [12] uint32_t txvco_vcoh_sel_bb : 1; // [13] uint32_t txvco_ibias_en_bb : 1; // [14] uint32_t txvco_bias_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TRX_PU_3_T; // trx_pu_4 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t pwd_rstn_bb : 1; // [1] uint32_t pwdadc_enh_bb : 1; // [2] uint32_t pwdadc_clk_enh_bb : 1; // [3] uint32_t pwdadc_ref_enh_bb : 1; // [4] uint32_t pwdadc_bias_en_bb : 1; // [5] uint32_t pu_pwd_pga_bb : 1; // [6] uint32_t pwdadc_rstn_bb : 1; // [7] uint32_t pu_pwd_bb : 1; // [8] uint32_t txpad_en_bb : 1; // [9] uint32_t pu_txrf_bb : 1; // [10] uint32_t pu_txflt_bb : 1; // [11] uint32_t txmixer_en_bb : 1; // [12] uint32_t dac_rstn_bb : 1; // [13] uint32_t pu_dac_bb : 1; // [14] uint32_t txflt_rstn_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TRX_PU_4_T; // trx_pu_5 typedef union { uint32_t v; struct { uint32_t __11_0 : 12; // [11:0] uint32_t pu_dly_txrf_bb : 1; // [12] uint32_t pu_dly_txflt_bb : 1; // [13] uint32_t pu_dly_pwd_bb : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_ANA_TRX_PU_5_T; // mdll_ctrl_0 typedef union { uint32_t v; struct { uint32_t mdll_dither_mode_bb : 1; // [0] uint32_t mdll_cp_ibit_bb : 3; // [3:1] uint32_t mdll_dither_bit_bb : 3; // [6:4] uint32_t mdll_band_sel_bb : 1; // [7] uint32_t mdll_band_bit_bb : 3; // [10:8] uint32_t mdll_dither_en_bb : 1; // [11] uint32_t mdll_div_bit_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_MDLL_CTRL_0_T; // mdll_ctrl_1 typedef union { uint32_t v; struct { uint32_t __6_0 : 7; // [6:0] uint32_t disable_refclk_txpll_bb : 1; // [7] uint32_t disable_refclk_rxpll_bb : 1; // [8] uint32_t mdll_vctrl_test_en_bb : 1; // [9] uint32_t mdll_refclk_test_en_bb : 1; // [10] uint32_t mdll_clk_divn_bb : 2; // [12:11] uint32_t mdll_regu_vcosel_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_MDLL_CTRL_1_T; // xtal_ctrl_0 typedef union { uint32_t v; struct { uint32_t xtal26m_refpll_crf_en_bb : 1; // [0] uint32_t xtal_iptat_en_bb : 1; // [1] uint32_t __31_2 : 30; // [31:2] } b; } REG_RF_ANA_XTAL_CTRL_0_T; // rxvco_ldo_ctrl typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t rxvco_ldo_trim_bb : 4; // [9:6] uint32_t rxvco_ldo_out_bb : 3; // [12:10] uint32_t rxvco_ldo_short_en_bb : 1; // [13] uint32_t rxvco_ldo_powermode_sel_bb : 1; // [14] uint32_t rxvco_ldo_vcomode_sel_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXVCO_LDO_CTRL_T; // rxvco_buf_ldo_ctrl typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t rxvco_buf_ldo_trim_bb : 4; // [9:6] uint32_t rxvco_buf_ldo_out_bb : 3; // [12:10] uint32_t rxvco_buf_ldo_short_en_bb : 1; // [13] uint32_t rxvco_buf_ldo_powermode_sel_bb : 1; // [14] uint32_t rxvco_buf_ldo_vcomode_sel_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXVCO_BUF_LDO_CTRL_T; // rxvco_ctrl_0 typedef union { uint32_t v; struct { uint32_t rxvco_var_reverse_bb : 1; // [0] uint32_t rxvco_varbias_vbsel_ptat_bb : 2; // [2:1] uint32_t rxvco_varbias_vbsel_ctat_bb : 2; // [4:3] uint32_t rxvco_varbias_rcsel_bb : 2; // [6:5] uint32_t rxvco_var_short_bb : 1; // [7] uint32_t rxvco_ktc_ptat_bb : 3; // [10:8] uint32_t rxvco_ktc_ctat_bb : 3; // [13:11] uint32_t rxvco_bias_sel_bb : 1; // [14] uint32_t rxvco_bias_extra_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXVCO_CTRL_0_T; // rxvco_ctrl_1 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t rxvco_pkd_ref_ctrl_bb : 1; // [3] uint32_t rxvco_pkd_ref_bb : 3; // [6:4] uint32_t rxvco_pkd_pdt_bb : 3; // [9:7] uint32_t rxvco_vardif_bb : 3; // [12:10] uint32_t rxvco_varcom_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXVCO_CTRL_1_T; // rxvco_ctrl_2 typedef union { uint32_t v; struct { uint32_t __8_0 : 9; // [8:0] uint32_t rxvco_lte_en_bb : 1; // [9] uint32_t rxvco_lcl_div2_bb : 1; // [10] uint32_t rxvco_lcl_div1_bb : 1; // [11] uint32_t rxvco_cm_sca_ctrl_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXVCO_CTRL_2_T; // rxpll_ldo_ctrl_0 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t rxpll_gro_ldo_out_trim_bb : 2; // [2:1] uint32_t rxpll_gro_ldo_in_trim_bb : 4; // [6:3] uint32_t rxpll_presc_ldo_cripple_bb : 2; // [8:7] uint32_t rxpll_presc_ldo_out_bb : 3; // [11:9] uint32_t rxpll_presc_ldo_ref_trim_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_LDO_CTRL_0_T; // rxpll_ldo_ctrl_1 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t rxpll_rdac_ldo_dig_cripple_bb : 2; // [3:2] uint32_t rxpll_rdac_ldo_dig_out_bb : 3; // [6:4] uint32_t rxpll_rdac_ldo_dig_ref_trim_bb : 4; // [10:7] uint32_t rxpll_gro_ldo_res_adjust_bb : 2; // [12:11] uint32_t rxpll_gro_ldo_cp_trim_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_LDO_CTRL_1_T; // rxpll_ldo_ctrl_2 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t rxpll_fbdiv_vddres_bb : 3; // [5:3] uint32_t rxpll_rdac_ldo_vref_cripple_bb : 2; // [7:6] uint32_t rxpll_rdac_ldo_vref_out_bb : 4; // [11:8] uint32_t rxpll_rdac_ldo_vref_ref_trim_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_LDO_CTRL_2_T; // rxpll_gro_ctrl_0 typedef union { uint32_t v; struct { uint32_t rxpll_gro_reg0_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_GRO_CTRL_0_T; // rxpll_gro_ctrl_1 typedef union { uint32_t v; struct { uint32_t rxpll_gro_reg1_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_GRO_CTRL_1_T; // rxpll_gro_ctrl_2 typedef union { uint32_t v; struct { uint32_t rxpll_gro_reg2_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_GRO_CTRL_2_T; // rxpll_gro_ctrl_3 typedef union { uint32_t v; struct { uint32_t rxpll_gro_reg3_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_GRO_CTRL_3_T; // rxpll_ctrl_0 typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t rxpll_rdac_rcflt_r_bb : 3; // [6:4] uint32_t rxpll_open_en_bb : 1; // [7] uint32_t rxpll_sdmclk_sel_bb : 1; // [8] uint32_t rxpll_fbcsel_bit_bb : 3; // [11:9] uint32_t rxpll_rdac_clk_edgesel_bb : 1; // [12] uint32_t rxpll_rdac_vlow_selb_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXPLL_CTRL_0_T; // lna_sel_ctrl typedef union { uint32_t v; struct { uint32_t rxmixer_vco_selrx_bb : 1; // [0] uint32_t rxmixer_vco_sel5g_bb : 1; // [1] uint32_t en_lna_lte_l5_bb : 1; // [2] uint32_t en_lna_lte_l4_bb : 1; // [3] uint32_t en_lna_lte_l3_bb : 1; // [4] uint32_t en_lna_lte_l2_bb : 1; // [5] uint32_t en_lna_lte_l1_bb : 1; // [6] uint32_t en_lna_gnss_bb : 1; // [7] uint32_t en_lna_lte_m5_bb : 1; // [8] uint32_t en_lna_lte_m4_bb : 1; // [9] uint32_t en_lna_lte_m3_bb : 1; // [10] uint32_t en_lna_lte_m2_bb : 1; // [11] uint32_t en_lna_lte_m1_bb : 1; // [12] uint32_t en_lna_lte_h2_bb : 1; // [13] uint32_t en_lna_lte_h1_bb : 1; // [14] uint32_t en_lna_wifi_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LNA_SEL_CTRL_T; // lna_ctrl typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t lna_resf_en_bb : 1; // [3] uint32_t __5_4 : 2; // [5:4] uint32_t lna_gain0_bit_bb : 1; // [6] uint32_t lna_ldo_out_bb : 3; // [9:7] uint32_t lna_ldo_cp_tune_bb : 2; // [11:10] uint32_t lna_ldo_bypass_bb : 1; // [12] uint32_t lna_power_res_bit_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LNA_CTRL_T; // lna_pkd_ctrl typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t lna_in_capbank_bb : 3; // [5:3] uint32_t lna_pkd_ref_ctrl_bb : 1; // [6] uint32_t lna_pkd_ref_2_bb : 3; // [9:7] uint32_t lna_pkd_ref_1_bb : 3; // [12:10] uint32_t lna_pkd_pdt_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_LNA_PKD_CTRL_T; // rxmixer_ctrl typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t lna_m3_capbank_bb : 3; // [6:4] uint32_t lna_h2_capbank_bb : 3; // [9:7] uint32_t tia_bypass_bb : 1; // [10] uint32_t tia_rin_bit_bb : 2; // [12:11] uint32_t rxmixer_lodc_lte_bit_bb : 2; // [14:13] uint32_t rxmixer_lodc_h_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXMIXER_CTRL_T; // pga_ctrl_0 typedef union { uint32_t v; struct { uint32_t pga_op_millercn_bit_bb : 2; // [1:0] uint32_t pga_op_millercc_bit_bb : 2; // [3:2] uint32_t pga_rs_bit_bb : 5; // [8:4] uint32_t pga_i_bit_bb : 2; // [10:9] uint32_t rxabb_ldo_cp_tun_bb : 2; // [12:11] uint32_t rxabb_ldo_out_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PGA_CTRL_0_T; // pga_ctrl_1 typedef union { uint32_t v; struct { uint32_t pga_bw_tune_bit_bb : 3; // [2:0] uint32_t pga_c2nd_bit_bb : 2; // [4:3] uint32_t pga_rpre_bit_bb : 2; // [6:5] uint32_t pga_blk_mode_bb : 1; // [7] uint32_t pga_cf_bit_bb : 5; // [12:8] uint32_t pga_bw_mode_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PGA_CTRL_1_T; // pga_ctrl_2 typedef union { uint32_t v; struct { uint32_t pga_pkd_ref_ctrl_bb : 1; // [0] uint32_t pga_pkd_ref2_bb : 3; // [3:1] uint32_t pga_pkd_ref1_bb : 3; // [6:4] uint32_t pga_ctun_bit_bb : 9; // [15:7] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PGA_CTRL_2_T; // pga_ctrl_3 typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t pga_cm_con_bb : 3; // [7:5] uint32_t rxabb_ldo_trim_bb : 4; // [11:8] uint32_t pga_pkd_ibias_sel_bb : 2; // [13:12] uint32_t pga_pkd_rctime_sel_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PGA_CTRL_3_T; // rxabb_dccal_ctrl_0 typedef union { uint32_t v; struct { uint32_t rx_dccal_q_bit_bb : 8; // [7:0] uint32_t rx_dccal_i_bit_bb : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXABB_DCCAL_CTRL_0_T; // rxabb_dccal_ctrl_1 typedef union { uint32_t v; struct { uint32_t __13_0 : 14; // [13:0] uint32_t rx_dccal_range_bit_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXABB_DCCAL_CTRL_1_T; // rxflt_ctrl_0 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t rxflt_if_freq_bit_bb : 3; // [5:3] uint32_t rxflt_if_en_bb : 1; // [6] uint32_t rxflt_if_swap_bb : 1; // [7] uint32_t rxflt_bwtun_bit_bb : 4; // [11:8] uint32_t rxflt_bwmode_bit_bb : 3; // [14:12] uint32_t rxflt_aux_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXFLT_CTRL_0_T; // rxflt_ctrl_1 typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t rxflt_i_bit_bb : 2; // [9:8] uint32_t rxflt_op_millercn_bit_bb : 2; // [11:10] uint32_t rxflt_op_millercc_bit_bb : 2; // [13:12] uint32_t anti_kick_back_filter_bw_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXFLT_CTRL_1_T; // rxflt_ctrl_2 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t rxflt_bwtun_c2_bb : 7; // [7:1] uint32_t rxflt_bwtun_c1_bb : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXFLT_CTRL_2_T; // adc_ldo_ctrl typedef union { uint32_t v; struct { uint32_t __6_0 : 7; // [6:0] uint32_t adc_ldo_out_trim_bb : 2; // [8:7] uint32_t adc_ldo_in_trim_bb : 4; // [12:9] uint32_t adc_ldo_cp_trim_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_ADC_LDO_CTRL_T; // adc_ctrl_0 typedef union { uint32_t v; struct { uint32_t adc_ns_enh_bb : 1; // [0] uint32_t adc_ns_charge_set_time_ctrl_bb : 2; // [2:1] uint32_t adc_msb_delay_ctrl_bb : 2; // [4:3] uint32_t adc_loop_delay_ctrl_bb : 4; // [8:5] uint32_t adc_en_latch_adjust_bb : 2; // [10:9] uint32_t adc_clkout_polarity_bb : 1; // [11] uint32_t adc_clk_vin_delay_ctrl_bb : 2; // [13:12] uint32_t adc_clk_rst_ctrl_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_ADC_CTRL_0_T; // adc_ctrl_1 typedef union { uint32_t v; struct { uint32_t adc_os_code_0p25_i_bb : 1; // [0] uint32_t adc_os_code_0p5_i_bb : 1; // [1] uint32_t adc_os_code_i_bb : 5; // [6:2] uint32_t __7_7 : 1; // [7] uint32_t adc_os_code_0p25_q_bb : 1; // [8] uint32_t adc_os_code_0p5_q_bb : 1; // [9] uint32_t adc_os_code_q_bb : 5; // [14:10] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_ANA_ADC_CTRL_1_T; // adc_ctrl_2 typedef union { uint32_t v; struct { uint32_t adc_input_os_vcm_ctrl_bb : 3; // [2:0] uint32_t adc_stb_ctrl_bb : 3; // [5:3] uint32_t adc_samp_hold_ctrl_bb : 2; // [7:6] uint32_t adc_residual_comp_en_bb : 1; // [8] uint32_t adc_res_adjust_bb : 2; // [10:9] uint32_t adc_os_cap_flow_q_bb : 1; // [11] uint32_t adc_os_cap_flow_i_bb : 1; // [12] uint32_t adc_ns_vcm_ctrl_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_ADC_CTRL_2_T; // adc_ctrl_3 typedef union { uint32_t v; struct { uint32_t adc_input_short_bb : 1; // [0] uint32_t adc_ns_slap_ctrl_bb : 1; // [1] uint32_t __2_2 : 1; // [2] uint32_t adc_clk_sel_bb : 2; // [4:3] uint32_t adc_vrp_i_ctrl_bb : 4; // [8:5] uint32_t adc_vrp_ctrl_bb : 4; // [12:9] uint32_t adc_vcm_ctrl_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_ADC_CTRL_3_T; // pwdadc_ctrl_0 typedef union { uint32_t v; struct { uint32_t pwdadc_ns_enh_bb : 1; // [0] uint32_t pwdadc_ns_charge_set_time_ctrl_bb : 2; // [2:1] uint32_t pwdadc_msb_delay_ctrl_bb : 2; // [4:3] uint32_t pwdadc_loop_delay_ctrl_bb : 4; // [8:5] uint32_t pwdadc_en_latch_adjust_bb : 2; // [10:9] uint32_t pwdadc_clkout_polarity_bb : 1; // [11] uint32_t pwdadc_clk_vin_delay_ctrl_bb : 2; // [13:12] uint32_t pwdadc_clk_rst_ctrl_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWDADC_CTRL_0_T; // pwdadc_ctrl_1 typedef union { uint32_t v; struct { uint32_t pwdadc_input_short_bb : 1; // [0] uint32_t pwdadc_os_code_i_bb : 5; // [5:1] uint32_t pwdadc_os_code_0p25_q_bb : 1; // [6] uint32_t pwdadc_os_code_0p25_i_bb : 1; // [7] uint32_t pwdadc_os_code_0p5_q_bb : 1; // [8] uint32_t pwdadc_os_code_0p5_i_bb : 1; // [9] uint32_t pwdadc_os_cap_flow_q_bb : 1; // [10] uint32_t pwdadc_os_cap_flow_i_bb : 1; // [11] uint32_t pwdadc_ns_vcm_ctrl_bb : 3; // [14:12] uint32_t pwdadc_ns_slap_ctrl_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWDADC_CTRL_1_T; // pwdadc_ctrl_2 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t pwdadc_clk_sel_bb : 2; // [2:1] uint32_t pwdadc_stb_ctrl_bb : 3; // [5:3] uint32_t pwdadc_samp_hold_ctrl_bb : 2; // [7:6] uint32_t pwdadc_residual_comp_en_bb : 1; // [8] uint32_t pwdadc_res_adjust_bb : 2; // [10:9] uint32_t pwdadc_os_code_q_bb : 5; // [15:11] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWDADC_CTRL_2_T; // pwdadc_ctrl_3 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t pwdadc_input_os_vcm_ctrl_bb : 3; // [4:2] uint32_t pwdadc_vrp_i_ctrl_bb : 4; // [8:5] uint32_t pwdadc_vrp_ctrl_bb : 4; // [12:9] uint32_t pwdadc_vcm_ctrl_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWDADC_CTRL_3_T; // rx_gain_ctrl typedef union { uint32_t v; struct { uint32_t lna_resf_bit_bb : 3; // [2:0] uint32_t rxflt_gain_bit_bb : 4; // [6:3] uint32_t pga_gain_bit_bb : 2; // [8:7] uint32_t lna_vbc_bit_bb : 3; // [11:9] uint32_t lna_bias_bb : 2; // [13:12] uint32_t lna_gain_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RX_GAIN_CTRL_T; // rx_reserve1 typedef union { uint32_t v; struct { uint32_t rx_reserve1_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RX_RESERVE1_T; // rx_reserve2 typedef union { uint32_t v; struct { uint32_t rx_reserve2_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RX_RESERVE2_T; // rx_reserve3 typedef union { uint32_t v; struct { uint32_t rx_reserve3_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RX_RESERVE3_T; // txvco_ldo_ctrl typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t txvco_ldo_trim_bb : 4; // [9:6] uint32_t txvco_ldo_out_bb : 3; // [12:10] uint32_t txvco_ldo_short_en_bb : 1; // [13] uint32_t txvco_ldo_powermode_sel_bb : 1; // [14] uint32_t txvco_ldo_vcomode_sel_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXVCO_LDO_CTRL_T; // txvco_buf_ldo_ctrl typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t txvcobuf_ldo_trim_bb : 4; // [9:6] uint32_t txvcobuf_ldo_out_bb : 3; // [12:10] uint32_t txvcobuf_ldo_short_en_bb : 1; // [13] uint32_t txvcobuf_ldo_powermode_sel_bb : 1; // [14] uint32_t txvcobuf_ldo_vcomode_sel_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXVCO_BUF_LDO_CTRL_T; // txvco_ctrl_0 typedef union { uint32_t v; struct { uint32_t txvco_var_reverse_bb : 1; // [0] uint32_t txvco_varbias_vbsel_ptat_bb : 2; // [2:1] uint32_t txvco_varbias_vbsel_ctat_bb : 2; // [4:3] uint32_t txvco_varbias_rcsel_bb : 2; // [6:5] uint32_t txvco_var_short_bb : 1; // [7] uint32_t txvco_ktc_ptat_bb : 3; // [10:8] uint32_t txvco_ktc_ctat_bb : 3; // [13:11] uint32_t txvco_bias_sel_bb : 1; // [14] uint32_t txvco_bias_extra_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXVCO_CTRL_0_T; // txvco_ctrl_1 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t txvco_pkd_ref_ctrl_bb : 1; // [3] uint32_t txvco_pkd_ref_bb : 3; // [6:4] uint32_t txvco_pkd_pdt_bb : 3; // [9:7] uint32_t txvco_vardif_bb : 3; // [12:10] uint32_t txvco_varcom_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXVCO_CTRL_1_T; // txvco_ctrl_2 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t txrfdiv_pwd_en_bb : 1; // [1] uint32_t txrfdiv_lte_en_bb : 1; // [2] uint32_t txrfdiv_div4_en_bb : 1; // [3] uint32_t txrfdiv_div2_en_bb : 1; // [4] uint32_t txvco_rx_div1_en_bb : 1; // [5] uint32_t txvco_gnss_en_bb : 1; // [6] uint32_t txvco_rxlte_en_bb : 1; // [7] uint32_t txvco_tx_en_bb : 1; // [8] uint32_t __9_9 : 1; // [9] uint32_t txvco_lcl_div2_bb : 1; // [10] uint32_t txvco_lcl_div1_bb : 1; // [11] uint32_t txvco_cm_sca_ctrl_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXVCO_CTRL_2_T; // txpll_ldo_ctrl_0 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t txpll_gro_ldo_out_trim_bb : 2; // [2:1] uint32_t txpll_gro_ldo_in_trim_bb : 4; // [6:3] uint32_t txpll_presc_ldo_cripple_bb : 2; // [8:7] uint32_t txpll_presc_ldo_out_bb : 3; // [11:9] uint32_t txpll_presc_ldo_ref_trim_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_LDO_CTRL_0_T; // txpll_ldo_ctrl_1 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t txpll_rdac_ldo_dig_cripple_bb : 2; // [3:2] uint32_t txpll_rdac_ldo_dig_out_bb : 3; // [6:4] uint32_t txpll_rdac_ldo_dig_ref_trim_bb : 4; // [10:7] uint32_t txpll_gro_ldo_res_adjust_bb : 2; // [12:11] uint32_t txpll_gro_ldo_cp_trim_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_LDO_CTRL_1_T; // txpll_ldo_ctrl_2 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t txpll_fbdiv_vddres_bb : 3; // [5:3] uint32_t txpll_rdac_ldo_vref_cripple_bb : 2; // [7:6] uint32_t txpll_rdac_ldo_vref_out_bb : 4; // [11:8] uint32_t txpll_rdac_ldo_vref_ref_trim_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_LDO_CTRL_2_T; // txpll_gro_ctrl_0 typedef union { uint32_t v; struct { uint32_t txpll_gro_reg0_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_GRO_CTRL_0_T; // txpll_gro_ctrl_1 typedef union { uint32_t v; struct { uint32_t txpll_gro_reg1_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_GRO_CTRL_1_T; // txpll_gro_ctrl_2 typedef union { uint32_t v; struct { uint32_t txpll_gro_reg2_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_GRO_CTRL_2_T; // txpll_gro_ctrl_3 typedef union { uint32_t v; struct { uint32_t txpll_gro_reg3_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_GRO_CTRL_3_T; // txpll_ctrl_0 typedef union { uint32_t v; struct { uint32_t __3_0 : 4; // [3:0] uint32_t txpll_rdac_rcflt_r_bb : 3; // [6:4] uint32_t txpll_open_en_bb : 1; // [7] uint32_t txpll_sdmclk_sel_bb : 1; // [8] uint32_t txpll_fbcsel_bit_bb : 3; // [11:9] uint32_t txpll_rdac_clk_edgesel_bb : 1; // [12] uint32_t txpll_rdac_vlow_selb_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXPLL_CTRL_0_T; // txrf_gain typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t txrf_gain3_bit_bb : 3; // [3:1] uint32_t txrf_gain2_bit_bb : 5; // [8:4] uint32_t txrf_gain1_bit_bb : 5; // [13:9] uint32_t txflt_ph45_en_bb : 1; // [14] uint32_t txrf_ph45_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXRF_GAIN_T; // txrf_gain_compensation typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t txpad_bias_ibit_bb : 3; // [3:1] uint32_t txrf_gain2c_n45_bit_bb : 4; // [7:4] uint32_t txrf_gain2c_p45_bit_bb : 4; // [11:8] uint32_t txrf_gain2c_bit_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXRF_GAIN_COMPENSATION_T; // txrf_gain_adj typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t txrf_lb2_en_bb : 1; // [3] uint32_t txrf_lb1_en_bb : 1; // [4] uint32_t txrf_hb2_en_bb : 1; // [5] uint32_t txrf_hb1_en_bb : 1; // [6] uint32_t txrf_bandbalance_bit_bb : 2; // [8:7] uint32_t txrf_en_bbload_bb : 1; // [9] uint32_t txrf_sw_sel2_bb : 1; // [10] uint32_t txrf_sw_sel1_bb : 1; // [11] uint32_t txpad_cas_vbit_bb : 2; // [13:12] uint32_t txpad_aux_vbit_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXRF_GAIN_ADJ_T; // txrf_matchcap typedef union { uint32_t v; struct { uint32_t __4_0 : 5; // [4:0] uint32_t txrf_mix_r2r_cbit_bb : 1; // [5] uint32_t txrf_rcflt_rbit_bb : 2; // [7:6] uint32_t txpad_deq_bit_bb : 2; // [9:8] uint32_t txpad_cap_ulb_bit_bb : 2; // [11:10] uint32_t txpad_cap_bit_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXRF_MATCHCAP_T; // txflt_ctrl_0 typedef union { uint32_t v; struct { uint32_t txflt_vcm_ref_bb : 3; // [2:0] uint32_t txflt_ibias_bit_bb : 2; // [4:3] uint32_t txflt_cn_bb : 2; // [6:5] uint32_t txflt_cc_bb : 2; // [8:7] uint32_t tx_dccal_clk_edgesel_bb : 1; // [9] uint32_t tx_dccal_en_bb : 1; // [10] uint32_t txflt_ldo_cp_tune_bb : 2; // [12:11] uint32_t txflt_ldo_out_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXFLT_CTRL_0_T; // txflt_ctrl_1 typedef union { uint32_t v; struct { uint32_t txflt_buffer_ibit_bb : 2; // [1:0] uint32_t txflt_bwtun_bit_bb : 8; // [9:2] uint32_t txflt_bw_bit_bb : 3; // [12:10] uint32_t txflt_testin_en_bb : 1; // [13] uint32_t txflt_hp_bit_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TXFLT_CTRL_1_T; // dac_ctrl_0 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t dac_core_bit_bb : 3; // [5:3] uint32_t dac_vhigh_bit_bb : 3; // [8:6] uint32_t dac_clkedge_sel_bb : 1; // [9] uint32_t dac_muxen_bit_bb : 2; // [11:10] uint32_t dac_iout_en_bb : 1; // [12] uint32_t dac_auxout_en_bb : 1; // [13] uint32_t dac_range_bit_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_DAC_CTRL_0_T; // dac_ctrl_1 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t dac_ldo_out_bb : 3; // [3:1] uint32_t dac_ldo_cp_tune_bb : 2; // [5:4] uint32_t dac_tia_opamp_fbcap_bit_bb : 2; // [7:6] uint32_t dac_tia_cmo_bit_bb : 2; // [9:8] uint32_t dac_tia_cmi_bit_bb : 2; // [11:10] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_ANA_DAC_CTRL_1_T; // gnss_clkgen_ctrl_0 typedef union { uint32_t v; struct { uint32_t gnss_clkgen_m4_clk_div_bb : 4; // [3:0] uint32_t gnss_clkgen_m4_clk_bufsel_bb : 2; // [5:4] uint32_t gnss_clkgen_adc_clk_out_vres_bb : 3; // [8:6] uint32_t gnss_clkgen_adc_clk_out_div_bb : 5; // [13:9] uint32_t gnss_clkgen_adc_clk_out_bufsel_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_GNSS_CLKGEN_CTRL_0_T; // gnss_clkgen_ctrl_1 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t gnss_clkgen_tsx_adc_clk_bufsel_bb : 2; // [2:1] uint32_t gnss_clkgen_pp_clk_vres_bb : 3; // [5:3] uint32_t gnss_clkgen_pp_clk_div_bb : 5; // [10:6] uint32_t gnss_clkgen_pp_clk_bufsel_bb : 2; // [12:11] uint32_t gnss_clkgen_m4_clk_vres_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_GNSS_CLKGEN_CTRL_1_T; // gnss_clkgen_ctrl_2 typedef union { uint32_t v; struct { uint32_t gnss_clkgen_ana_adc_clk_div_bb : 7; // [6:0] uint32_t gnss_clkgen_ana_adc_clk_bufsel_bb : 2; // [8:7] uint32_t gnss_clkgen_tsx_adc_clk_vres_bb : 3; // [11:9] uint32_t gnss_clkgen_tsx_adc_clk_div_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_GNSS_CLKGEN_CTRL_2_T; // gnss_clkgen_ctrl_3 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t gnss_clkgen_m4_clk_frac_sel_bb : 1; // [1] uint32_t gnss_clkgen_m4_clk_frac_divn_bb : 3; // [4:2] uint32_t gnss_clkgen_m4_clk_frac_divf_bb : 3; // [7:5] uint32_t gnss_clkgen_m4_clk_div_frac_en_bb : 1; // [8] uint32_t gnss_clkgen_pp_clk_mux_bb : 2; // [10:9] uint32_t gnss_clkgen_adc_clk_out_mux_bb : 2; // [12:11] uint32_t gnss_clkgen_ana_adc_clk_vres_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_GNSS_CLKGEN_CTRL_3_T; // gnss_clkgen_ctrl_4 typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t gnss_clkgen_ana_adc_clk_en_bb : 1; // [6] uint32_t gnss_clkgen_ana_adc_clk_div_en_bb : 1; // [7] uint32_t gnss_clkgen_tsx_adc_clk_en_bb : 1; // [8] uint32_t gnss_clkgen_tsx_adc_clk_div_en_bb : 1; // [9] uint32_t gnss_clkgen_pp_clk_en_bb : 1; // [10] uint32_t gnss_clkgen_pp_clk_div_en_bb : 1; // [11] uint32_t gnss_clkgen_m4_clk_en_bb : 1; // [12] uint32_t gnss_clkgen_m4_clk_div_en_bb : 1; // [13] uint32_t gnss_clkgen_adc_clk_out_en_bb : 1; // [14] uint32_t gnss_clkgen_adc_clk_out_div_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_GNSS_CLKGEN_CTRL_4_T; // rxflt_dccal typedef union { uint32_t v; struct { uint32_t rxflt_dccal_q_bit_bb : 8; // [7:0] uint32_t rxflt_dccal_i_bit_bb : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RXFLT_DCCAL_T; // tx_reserve_0 typedef union { uint32_t v; struct { uint32_t lte_tx_rsv_09_h_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TX_RESERVE_0_T; // tx_reserve_1 typedef union { uint32_t v; struct { uint32_t lte_tx_rsv_18_bb : 8; // [7:0] uint32_t lte_tx_rsv_09_l_bb : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TX_RESERVE_1_T; // pwd_ctrl_0 typedef union { uint32_t v; struct { uint32_t __2_0 : 3; // [2:0] uint32_t pwd_pga_cc_bit_bb : 2; // [4:3] uint32_t pwd_pga_cn_bit_bb : 2; // [6:5] uint32_t pwd_pga_ldo_res_adj_bb : 2; // [8:7] uint32_t pwd_mgain_bit_bb : 3; // [11:9] uint32_t pwd_pga_res_bit_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWD_CTRL_0_T; // pwd_ctrl_1 typedef union { uint32_t v; struct { uint32_t __11_0 : 12; // [11:0] uint32_t pwd_pga_cap_bit_bb : 4; // [15:12] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWD_CTRL_1_T; // pwd_ctrl_2 typedef union { uint32_t v; struct { uint32_t pwd_cal_q_en_bb : 1; // [0] uint32_t pwd_cal_q_done_bb : 1; // [1] uint32_t pwd_cal_q_bb : 6; // [7:2] uint32_t pwd_cal_i_en_bb : 1; // [8] uint32_t pwd_cal_i_done_bb : 1; // [9] uint32_t pwd_cal_i_bb : 6; // [15:10] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_PWD_CTRL_2_T; // ts_ctrl_0 typedef union { uint32_t v; struct { uint32_t ts_adc_ibit_bb : 3; // [2:0] uint32_t ts_refsel_bit_bb : 2; // [4:3] uint32_t ts_div_bit_bb : 4; // [8:5] uint32_t ts_chopper_en_bb : 1; // [9] uint32_t ts_xtaltest_en_bb : 1; // [10] uint32_t ts_pwdext_en_bb : 1; // [11] uint32_t ts_pwdint_en_bb : 1; // [12] uint32_t pu_ts_bb : 1; // [13] uint32_t ts_ldo_fast_charge_en_bb : 1; // [14] uint32_t ts_ldo_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TS_CTRL_0_T; // ts_ctrl_1 typedef union { uint32_t v; struct { uint32_t ts_clk_divedge_sel_bb : 1; // [0] uint32_t ts_clk_edgesel_bb : 1; // [1] uint32_t ts_clksel_bit_bb : 2; // [3:2] uint32_t ts_beta_en_bb : 1; // [4] uint32_t ts_vbe_sdmbit_bb : 1; // [5] uint32_t ts_testmode_en_bb : 1; // [6] uint32_t ts_resetn_bb : 1; // [7] uint32_t ts_vbe_bit_bb : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TS_CTRL_1_T; // ts_ctrl_2 typedef union { uint32_t v; struct { uint32_t __10_0 : 11; // [10:0] uint32_t ts_ldo_out_bb : 3; // [13:11] uint32_t ts_ldo_cp_tune_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TS_CTRL_2_T; // cm_reserve1 typedef union { uint32_t v; struct { uint32_t cm_reserve1_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_CM_RESERVE1_T; // cm_reserve2 typedef union { uint32_t v; struct { uint32_t cm_reserve2_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_CM_RESERVE2_T; // cm_reserve3 typedef union { uint32_t v; struct { uint32_t cm_reserve3_bb : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_CM_RESERVE3_T; // revid_reg typedef union { uint32_t v; struct { uint32_t revid : 8; // [7:0], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_ANA_REVID_REG_T; // test_ctrl_0 typedef union { uint32_t v; struct { uint32_t rx_lo_test_en_bb : 1; // [0] uint32_t rx_4g_test_en_bb : 1; // [1] uint32_t rx_5g_test_en_bb : 1; // [2] uint32_t test_txvco_en_bb : 1; // [3] uint32_t test_ldoref_rxvcobuf_sw_en_bb : 1; // [4] uint32_t test_ldoref_rxvco_sw_en_bb : 1; // [5] uint32_t test_ldoref_rxabb_sw_en_bb : 1; // [6] uint32_t test_ldoref_txvcobuf_sw_en_bb : 1; // [7] uint32_t test_ldoref_txvco_sw_en_bb : 1; // [8] uint32_t test_bg_cal_r_en_bb : 1; // [9] uint32_t test_clk_mdll_sw_en_bb : 1; // [10] uint32_t test_ldoref_adc_sw_en_bb : 1; // [11] uint32_t test_mdll_vctrl_sw_en_bb : 1; // [12] uint32_t pll_test_en_bb : 1; // [13] uint32_t dac_out_en_bb : 1; // [14] uint32_t tx_if_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TEST_CTRL_0_T; // test_ctrl_1 typedef union { uint32_t v; struct { uint32_t __0_0 : 1; // [0] uint32_t cal_rxiq_att_ctrl_bb : 5; // [5:1] uint32_t cal_rxiq_div4_en_bb : 1; // [6] uint32_t cal_rxiq_div2_en_bb : 1; // [7] uint32_t test_iq_adcinput_sw_en_bb : 1; // [8] uint32_t test_ldoref_txpll_rdac_sw_en_bb : 1; // [9] uint32_t test_ldoref_rxpll_rdac_sw_en_bb : 1; // [10] uint32_t test_vpa_ts_sw_en_bb : 1; // [11] uint32_t test_vref_ts_sw_en_bb : 1; // [12] uint32_t test_vr_ts_sw_en_bb : 1; // [13] uint32_t test_vl_ts_sw_en_bb : 1; // [14] uint32_t test_clk_ts_sw_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TEST_CTRL_1_T; // cal_ctrl_0 typedef union { uint32_t v; struct { uint32_t cal_rxiq_att_adj_bb : 4; // [3:0] uint32_t tx_ed_ibg_bb : 3; // [6:4] uint32_t tx_ed_ibp_bb : 3; // [9:7] uint32_t txpad_att_ctl_bb : 2; // [11:10] uint32_t cal_rxiq_en_bb : 1; // [12] uint32_t cal_rxiq_mix_sel_bb : 1; // [13] uint32_t cal_txiq_en_bb : 1; // [14] uint32_t cal_txiq_sel_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_CAL_CTRL_0_T; // rf_output_readonly_0 typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t txpll_lock_bb : 1; // [6], read only uint32_t rxpll_lock_bb : 1; // [7], read only uint32_t txvco_pkdet_out_bb : 1; // [8], read only uint32_t rxvco_pkdet_out_bb : 1; // [9], read only uint32_t pga_pkd_out_bb : 2; // [11:10], read only uint32_t lna_pkd_out_2_bb : 1; // [12], read only uint32_t lna_pkd_out_1_bb : 1; // [13], read only uint32_t tx_dccal_outq_bb : 1; // [14], read only uint32_t tx_dccal_outi_bb : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RF_OUTPUT_READONLY_0_T; // rf_output_readonly_1 typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t pwdadc_conv_done_q_wo_ns_bb : 1; // [8], read only uint32_t pwdadc_conv_done_i_wo_ns_bb : 1; // [9], read only uint32_t pwdadc_conv_done_q_wi_ns_bb : 1; // [10], read only uint32_t pwdadc_conv_done_i_wi_ns_bb : 1; // [11], read only uint32_t adc_conv_done_q_wo_ns_bb : 1; // [12], read only uint32_t adc_conv_done_i_wo_ns_bb : 1; // [13], read only uint32_t adc_conv_done_q_wi_ns_bb : 1; // [14], read only uint32_t adc_conv_done_i_wi_ns_bb : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_RF_OUTPUT_READONLY_1_T; // tsenadc_ctrl_0 typedef union { uint32_t v; struct { uint32_t rg_tsen_chop_clksel_bb : 2; // [1:0] uint32_t __5_2 : 4; // [5:2] uint32_t rg_tsen_adcldoref_bb : 5; // [10:6] uint32_t rg_tsen_adcldo_v_bb : 4; // [14:11] uint32_t rg_tsen_adcldo_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TSENADC_CTRL_0_T; // tsenadc_ctrl_1 typedef union { uint32_t v; struct { uint32_t __7_0 : 8; // [7:0] uint32_t rg_tsen_sdadc_en_bb : 1; // [8] uint32_t rg_tsen_sdadc_data_edge_sel_bb : 1; // [9] uint32_t rg_tsen_sdadc_chop_en_bb : 1; // [10] uint32_t rg_tsen_sdadc_capchop_en_bb : 1; // [11] uint32_t rg_tsen_sdadc_bias_bb : 2; // [13:12] uint32_t rg_tsen_clksel_bb : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TSENADC_CTRL_1_T; // tsenadc_ctrl_2 typedef union { uint32_t v; struct { uint32_t __1_0 : 2; // [1:0] uint32_t rg_tsen_ugbuf_ctrl_bb : 2; // [3:2] uint32_t rg_tsen_ugbuf_chop_en_bb : 1; // [4] uint32_t rg_tsen_ugbuf_bias_bb : 2; // [6:5] uint32_t rg_tsen_test_clk_sel_bb : 1; // [7] uint32_t rg_tsen_sdadc_vcmo_bb : 2; // [9:8] uint32_t rg_tsen_sdadc_vcmi_bb : 2; // [11:10] uint32_t rg_tsen_sdadc_ugbuf_en_bb : 1; // [12] uint32_t rg_tsen_sdadc_rst_bb : 1; // [13] uint32_t rg_tsen_sdadc_offset_en_bb : 1; // [14] uint32_t rg_tsen_sdadc_input_en_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_TSENADC_CTRL_2_T; // apc_ctrl_0 typedef union { uint32_t v; struct { uint32_t __5_0 : 6; // [5:0] uint32_t pu_ramp_dac_bb : 1; // [6] uint32_t apc_pga_ibit_bb : 2; // [8:7] uint32_t apc_lv_gain_bit_bb : 3; // [11:9] uint32_t apc_hv_gain_bit_bb : 3; // [14:12] uint32_t apc_bprc_bb : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_ANA_APC_CTRL_0_T; // apc_ctrl_1 typedef union { uint32_t v; struct { uint32_t ramp_dac_din_bb : 10; // [9:0] uint32_t __31_10 : 22; // [31:10] } b; } REG_RF_ANA_APC_CTRL_1_T; // bandgap_ctrl_0 #define RF_ANA_LDO_LEVELSHIFTER_CP_TUNE(n) (((n)&0x3) << 7) #define RF_ANA_LDO_LEVELSHIFTER_OUT(n) (((n)&0x7) << 9) #define RF_ANA_BG_CAL_R_D_BB(n) (((n)&0xf) << 12) // ldo_pu_ctrl_0 #define RF_ANA_PWDADC_LDO_EN_BB (1 << 4) #define RF_ANA_PWDADC_LDO_BIAS_EN_BB (1 << 5) #define RF_ANA_DAC_LDO_FC_PULSE_BB (1 << 6) #define RF_ANA_DAC_LDO_EN_BB (1 << 7) #define RF_ANA_TXFLT_LDO_FC_PULSE_BB (1 << 8) #define RF_ANA_TXFLT_LDO_EN_BB (1 << 9) #define RF_ANA_ADC_LDO_EN_BB (1 << 10) #define RF_ANA_ADC_LDO_BIAS_EN_BB (1 << 11) #define RF_ANA_RXABB_LDO_FC_PULSE_BB (1 << 12) #define RF_ANA_RXABB_LDO_EN_BB (1 << 13) #define RF_ANA_LNA_LDO_FAST_CHARGE_EN_BB (1 << 14) #define RF_ANA_LNA_LDO_EN_IN_BB (1 << 15) // ldo_pu_ctrl_1 #define RF_ANA_RXVCO_TC_FC_BB (1 << 1) #define RF_ANA_RXVCO_TC_EN_BB (1 << 2) #define RF_ANA_RXVCO_BUF_LDO_LOAD_BB (1 << 3) #define RF_ANA_RXVCO_BUF_LDO_FC_BB (1 << 4) #define RF_ANA_RXVCO_BUF_LDO_EN_BB (1 << 5) #define RF_ANA_RXVCO_LDO_LOAD_BB (1 << 6) #define RF_ANA_RXVCO_LDO_FC_BB (1 << 7) #define RF_ANA_RXVCO_LDO_EN_BB (1 << 8) #define RF_ANA_RXPLL_RDAC_LDO_VREF_FC_EN_BB (1 << 9) #define RF_ANA_RXPLL_RDAC_LDO_VREF_EN_BB (1 << 10) #define RF_ANA_RXPLL_RDAC_LDO_DIG_EN_BB (1 << 11) #define RF_ANA_RXPLL_PRESC_LDO_FAST_CHARGE_EN_BB (1 << 12) #define RF_ANA_RXPLL_PRESC_LDO_EN_BB (1 << 13) #define RF_ANA_RXPLL_GRO_LDO_EN_BB (1 << 14) #define RF_ANA_RXPLL_GRO_LDO_BIAS_EN_BB (1 << 15) // ldo_pu_ctrl_2 #define RF_ANA_TXVCO_TC_FC_BB (1 << 1) #define RF_ANA_TXVCO_TC_EN_BB (1 << 2) #define RF_ANA_TXVCOBUF_LDO_LOAD_BB (1 << 3) #define RF_ANA_TXVCOBUF_LDO_FC_BB (1 << 4) #define RF_ANA_TXVCOBUF_LDO_EN_BB (1 << 5) #define RF_ANA_TXVCO_LDO_LOAD_BB (1 << 6) #define RF_ANA_TXVCO_LDO_FC_BB (1 << 7) #define RF_ANA_TXVCO_LDO_EN_BB (1 << 8) #define RF_ANA_TXPLL_RDAC_LDO_VREF_FC_EN_BB (1 << 9) #define RF_ANA_TXPLL_RDAC_LDO_VREF_EN_BB (1 << 10) #define RF_ANA_TXPLL_RDAC_LDO_DIG_EN_BB (1 << 11) #define RF_ANA_TXPLL_PRESC_LDO_FAST_CHARGE_EN_BB (1 << 12) #define RF_ANA_TXPLL_PRESC_LDO_EN_BB (1 << 13) #define RF_ANA_TXPLL_GRO_LDO_EN_BB (1 << 14) #define RF_ANA_TXPLL_GRO_LDO_BIAS_EN_BB (1 << 15) // trx_pu_0 #define RF_ANA_PU_XDRV_BB (1 << 12) #define RF_ANA_MDLL_STARTUP_BB (1 << 13) #define RF_ANA_PU_MDLL_BB (1 << 14) #define RF_ANA_PU_BG_BB (1 << 15) // trx_pu_1 #define RF_ANA_RXPLL_RDAC_RSTN_BB (1 << 6) #define RF_ANA_RXPLL_GRO_RSTN_BB (1 << 7) #define RF_ANA_PU_RXPLL_RDAC_BB (1 << 8) #define RF_ANA_PU_RXPLL_GRO_BB (1 << 9) #define RF_ANA_PU_RXPLL_PRESC_BB (1 << 10) #define RF_ANA_RXVCO_PKDET_EN_BB (1 << 11) #define RF_ANA_RXVCO_VCOL_SEL_BB (1 << 12) #define RF_ANA_RXVCO_VCOH_SEL_BB (1 << 13) #define RF_ANA_RXVCO_IBIAS_EN_BB (1 << 14) #define RF_ANA_RXVCO_BIAS_EN_BB (1 << 15) // trx_pu_2 #define RF_ANA_ADC_RSTN_BB (1 << 1) #define RF_ANA_ADC_ENH_BB (1 << 2) #define RF_ANA_ADC_CLK_ENH_BB (1 << 3) #define RF_ANA_ADC_REF_ENH_BB (1 << 4) #define RF_ANA_ADC_BIAS_EN_BB (1 << 5) #define RF_ANA_PU_TIA_BB (1 << 6) #define RF_ANA_PU_RXMIXER_BB (1 << 7) #define RF_ANA_RXFLT_EN_BB (1 << 8) #define RF_ANA_RXFLT_RSTN_BB (1 << 9) #define RF_ANA_PU_RXFLT_BB (1 << 10) #define RF_ANA_PU_PGA_BB (1 << 11) #define RF_ANA_PGA_PKD_EN_BB (1 << 12) #define RF_ANA_PGA_EN_BB (1 << 13) #define RF_ANA_LNA_PKD_EN_BB (1 << 14) #define RF_ANA_PU_LNA_BB (1 << 15) // trx_pu_3 #define RF_ANA_TXPLL_RDAC_RSTN_BB (1 << 6) #define RF_ANA_TXPLL_GRO_RSTN_BB (1 << 7) #define RF_ANA_PU_TXPLL_RDAC_BB (1 << 8) #define RF_ANA_PU_TXPLL_GRO_BB (1 << 9) #define RF_ANA_PU_TXPLL_PRESC_BB (1 << 10) #define RF_ANA_TXVCO_PKDET_EN_BB (1 << 11) #define RF_ANA_TXVCO_VCOL_SEL_BB (1 << 12) #define RF_ANA_TXVCO_VCOH_SEL_BB (1 << 13) #define RF_ANA_TXVCO_IBIAS_EN_BB (1 << 14) #define RF_ANA_TXVCO_BIAS_EN_BB (1 << 15) // trx_pu_4 #define RF_ANA_PWD_RSTN_BB (1 << 1) #define RF_ANA_PWDADC_ENH_BB (1 << 2) #define RF_ANA_PWDADC_CLK_ENH_BB (1 << 3) #define RF_ANA_PWDADC_REF_ENH_BB (1 << 4) #define RF_ANA_PWDADC_BIAS_EN_BB (1 << 5) #define RF_ANA_PU_PWD_PGA_BB (1 << 6) #define RF_ANA_PWDADC_RSTN_BB (1 << 7) #define RF_ANA_PU_PWD_BB (1 << 8) #define RF_ANA_TXPAD_EN_BB (1 << 9) #define RF_ANA_PU_TXRF_BB (1 << 10) #define RF_ANA_PU_TXFLT_BB (1 << 11) #define RF_ANA_TXMIXER_EN_BB (1 << 12) #define RF_ANA_DAC_RSTN_BB (1 << 13) #define RF_ANA_PU_DAC_BB (1 << 14) #define RF_ANA_TXFLT_RSTN_BB (1 << 15) // trx_pu_5 #define RF_ANA_PU_DLY_TXRF_BB (1 << 12) #define RF_ANA_PU_DLY_TXFLT_BB (1 << 13) #define RF_ANA_PU_DLY_PWD_BB (1 << 14) // mdll_ctrl_0 #define RF_ANA_MDLL_DITHER_MODE_BB (1 << 0) #define RF_ANA_MDLL_CP_IBIT_BB(n) (((n)&0x7) << 1) #define RF_ANA_MDLL_DITHER_BIT_BB(n) (((n)&0x7) << 4) #define RF_ANA_MDLL_BAND_SEL_BB (1 << 7) #define RF_ANA_MDLL_BAND_BIT_BB(n) (((n)&0x7) << 8) #define RF_ANA_MDLL_DITHER_EN_BB (1 << 11) #define RF_ANA_MDLL_DIV_BIT_BB(n) (((n)&0xf) << 12) // mdll_ctrl_1 #define RF_ANA_DISABLE_REFCLK_TXPLL_BB (1 << 7) #define RF_ANA_DISABLE_REFCLK_RXPLL_BB (1 << 8) #define RF_ANA_MDLL_VCTRL_TEST_EN_BB (1 << 9) #define RF_ANA_MDLL_REFCLK_TEST_EN_BB (1 << 10) #define RF_ANA_MDLL_CLK_DIVN_BB(n) (((n)&0x3) << 11) #define RF_ANA_MDLL_REGU_VCOSEL_BB(n) (((n)&0x7) << 13) // xtal_ctrl_0 #define RF_ANA_XTAL26M_REFPLL_CRF_EN_BB (1 << 0) #define RF_ANA_XTAL_IPTAT_EN_BB (1 << 1) // rxvco_ldo_ctrl #define RF_ANA_RXVCO_LDO_TRIM_BB(n) (((n)&0xf) << 6) #define RF_ANA_RXVCO_LDO_OUT_BB(n) (((n)&0x7) << 10) #define RF_ANA_RXVCO_LDO_SHORT_EN_BB (1 << 13) #define RF_ANA_RXVCO_LDO_POWERMODE_SEL_BB (1 << 14) #define RF_ANA_RXVCO_LDO_VCOMODE_SEL_BB (1 << 15) // rxvco_buf_ldo_ctrl #define RF_ANA_RXVCO_BUF_LDO_TRIM_BB(n) (((n)&0xf) << 6) #define RF_ANA_RXVCO_BUF_LDO_OUT_BB(n) (((n)&0x7) << 10) #define RF_ANA_RXVCO_BUF_LDO_SHORT_EN_BB (1 << 13) #define RF_ANA_RXVCO_BUF_LDO_POWERMODE_SEL_BB (1 << 14) #define RF_ANA_RXVCO_BUF_LDO_VCOMODE_SEL_BB (1 << 15) // rxvco_ctrl_0 #define RF_ANA_RXVCO_VAR_REVERSE_BB (1 << 0) #define RF_ANA_RXVCO_VARBIAS_VBSEL_PTAT_BB(n) (((n)&0x3) << 1) #define RF_ANA_RXVCO_VARBIAS_VBSEL_CTAT_BB(n) (((n)&0x3) << 3) #define RF_ANA_RXVCO_VARBIAS_RCSEL_BB(n) (((n)&0x3) << 5) #define RF_ANA_RXVCO_VAR_SHORT_BB (1 << 7) #define RF_ANA_RXVCO_KTC_PTAT_BB(n) (((n)&0x7) << 8) #define RF_ANA_RXVCO_KTC_CTAT_BB(n) (((n)&0x7) << 11) #define RF_ANA_RXVCO_BIAS_SEL_BB (1 << 14) #define RF_ANA_RXVCO_BIAS_EXTRA_BB (1 << 15) // rxvco_ctrl_1 #define RF_ANA_RXVCO_PKD_REF_CTRL_BB (1 << 3) #define RF_ANA_RXVCO_PKD_REF_BB(n) (((n)&0x7) << 4) #define RF_ANA_RXVCO_PKD_PDT_BB(n) (((n)&0x7) << 7) #define RF_ANA_RXVCO_VARDIF_BB(n) (((n)&0x7) << 10) #define RF_ANA_RXVCO_VARCOM_BB(n) (((n)&0x7) << 13) // rxvco_ctrl_2 #define RF_ANA_RXVCO_LTE_EN_BB (1 << 9) #define RF_ANA_RXVCO_LCL_DIV2_BB (1 << 10) #define RF_ANA_RXVCO_LCL_DIV1_BB (1 << 11) #define RF_ANA_RXVCO_CM_SCA_CTRL_BB(n) (((n)&0xf) << 12) // rxpll_ldo_ctrl_0 #define RF_ANA_RXPLL_GRO_LDO_OUT_TRIM_BB(n) (((n)&0x3) << 1) #define RF_ANA_RXPLL_GRO_LDO_IN_TRIM_BB(n) (((n)&0xf) << 3) #define RF_ANA_RXPLL_PRESC_LDO_CRIPPLE_BB(n) (((n)&0x3) << 7) #define RF_ANA_RXPLL_PRESC_LDO_OUT_BB(n) (((n)&0x7) << 9) #define RF_ANA_RXPLL_PRESC_LDO_REF_TRIM_BB(n) (((n)&0xf) << 12) // rxpll_ldo_ctrl_1 #define RF_ANA_RXPLL_RDAC_LDO_DIG_CRIPPLE_BB(n) (((n)&0x3) << 2) #define RF_ANA_RXPLL_RDAC_LDO_DIG_OUT_BB(n) (((n)&0x7) << 4) #define RF_ANA_RXPLL_RDAC_LDO_DIG_REF_TRIM_BB(n) (((n)&0xf) << 7) #define RF_ANA_RXPLL_GRO_LDO_RES_ADJUST_BB(n) (((n)&0x3) << 11) #define RF_ANA_RXPLL_GRO_LDO_CP_TRIM_BB(n) (((n)&0x7) << 13) // rxpll_ldo_ctrl_2 #define RF_ANA_RXPLL_FBDIV_VDDRES_BB(n) (((n)&0x7) << 3) #define RF_ANA_RXPLL_RDAC_LDO_VREF_CRIPPLE_BB(n) (((n)&0x3) << 6) #define RF_ANA_RXPLL_RDAC_LDO_VREF_OUT_BB(n) (((n)&0xf) << 8) #define RF_ANA_RXPLL_RDAC_LDO_VREF_REF_TRIM_BB(n) (((n)&0xf) << 12) // rxpll_gro_ctrl_0 #define RF_ANA_RXPLL_GRO_REG0_BB(n) (((n)&0xffff) << 0) // rxpll_gro_ctrl_1 #define RF_ANA_RXPLL_GRO_REG1_BB(n) (((n)&0xffff) << 0) // rxpll_gro_ctrl_2 #define RF_ANA_RXPLL_GRO_REG2_BB(n) (((n)&0xffff) << 0) // rxpll_gro_ctrl_3 #define RF_ANA_RXPLL_GRO_REG3_BB(n) (((n)&0xffff) << 0) // rxpll_ctrl_0 #define RF_ANA_RXPLL_RDAC_RCFLT_R_BB(n) (((n)&0x7) << 4) #define RF_ANA_RXPLL_OPEN_EN_BB (1 << 7) #define RF_ANA_RXPLL_SDMCLK_SEL_BB (1 << 8) #define RF_ANA_RXPLL_FBCSEL_BIT_BB(n) (((n)&0x7) << 9) #define RF_ANA_RXPLL_RDAC_CLK_EDGESEL_BB (1 << 12) #define RF_ANA_RXPLL_RDAC_VLOW_SELB_BB(n) (((n)&0x7) << 13) // lna_sel_ctrl #define RF_ANA_RXMIXER_VCO_SELRX_BB (1 << 0) #define RF_ANA_RXMIXER_VCO_SEL5G_BB (1 << 1) #define RF_ANA_EN_LNA_LTE_L5_BB (1 << 2) #define RF_ANA_EN_LNA_LTE_L4_BB (1 << 3) #define RF_ANA_EN_LNA_LTE_L3_BB (1 << 4) #define RF_ANA_EN_LNA_LTE_L2_BB (1 << 5) #define RF_ANA_EN_LNA_LTE_L1_BB (1 << 6) #define RF_ANA_EN_LNA_GNSS_BB (1 << 7) #define RF_ANA_EN_LNA_LTE_M5_BB (1 << 8) #define RF_ANA_EN_LNA_LTE_M4_BB (1 << 9) #define RF_ANA_EN_LNA_LTE_M3_BB (1 << 10) #define RF_ANA_EN_LNA_LTE_M2_BB (1 << 11) #define RF_ANA_EN_LNA_LTE_M1_BB (1 << 12) #define RF_ANA_EN_LNA_LTE_H2_BB (1 << 13) #define RF_ANA_EN_LNA_LTE_H1_BB (1 << 14) #define RF_ANA_EN_LNA_WIFI_BB (1 << 15) // lna_ctrl #define RF_ANA_LNA_RESF_EN_BB (1 << 3) #define RF_ANA_LNA_GAIN0_BIT_BB (1 << 6) #define RF_ANA_LNA_LDO_OUT_BB(n) (((n)&0x7) << 7) #define RF_ANA_LNA_LDO_CP_TUNE_BB(n) (((n)&0x3) << 10) #define RF_ANA_LNA_LDO_BYPASS_BB (1 << 12) #define RF_ANA_LNA_POWER_RES_BIT_BB(n) (((n)&0x7) << 13) // lna_pkd_ctrl #define RF_ANA_LNA_IN_CAPBANK_BB(n) (((n)&0x7) << 3) #define RF_ANA_LNA_PKD_REF_CTRL_BB (1 << 6) #define RF_ANA_LNA_PKD_REF_2_BB(n) (((n)&0x7) << 7) #define RF_ANA_LNA_PKD_REF_1_BB(n) (((n)&0x7) << 10) #define RF_ANA_LNA_PKD_PDT_BB(n) (((n)&0x7) << 13) // rxmixer_ctrl #define RF_ANA_LNA_M3_CAPBANK_BB(n) (((n)&0x7) << 4) #define RF_ANA_LNA_H2_CAPBANK_BB(n) (((n)&0x7) << 7) #define RF_ANA_TIA_BYPASS_BB (1 << 10) #define RF_ANA_TIA_RIN_BIT_BB(n) (((n)&0x3) << 11) #define RF_ANA_RXMIXER_LODC_LTE_BIT_BB(n) (((n)&0x3) << 13) #define RF_ANA_RXMIXER_LODC_H_BB (1 << 15) // pga_ctrl_0 #define RF_ANA_PGA_OP_MILLERCN_BIT_BB(n) (((n)&0x3) << 0) #define RF_ANA_PGA_OP_MILLERCC_BIT_BB(n) (((n)&0x3) << 2) #define RF_ANA_PGA_RS_BIT_BB(n) (((n)&0x1f) << 4) #define RF_ANA_PGA_I_BIT_BB(n) (((n)&0x3) << 9) #define RF_ANA_RXABB_LDO_CP_TUN_BB(n) (((n)&0x3) << 11) #define RF_ANA_RXABB_LDO_OUT_BB(n) (((n)&0x7) << 13) // pga_ctrl_1 #define RF_ANA_PGA_BW_TUNE_BIT_BB(n) (((n)&0x7) << 0) #define RF_ANA_PGA_C2ND_BIT_BB(n) (((n)&0x3) << 3) #define RF_ANA_PGA_RPRE_BIT_BB(n) (((n)&0x3) << 5) #define RF_ANA_PGA_BLK_MODE_BB (1 << 7) #define RF_ANA_PGA_CF_BIT_BB(n) (((n)&0x1f) << 8) #define RF_ANA_PGA_BW_MODE_BB(n) (((n)&0x7) << 13) // pga_ctrl_2 #define RF_ANA_PGA_PKD_REF_CTRL_BB (1 << 0) #define RF_ANA_PGA_PKD_REF2_BB(n) (((n)&0x7) << 1) #define RF_ANA_PGA_PKD_REF1_BB(n) (((n)&0x7) << 4) #define RF_ANA_PGA_CTUN_BIT_BB(n) (((n)&0x1ff) << 7) // pga_ctrl_3 #define RF_ANA_PGA_CM_CON_BB(n) (((n)&0x7) << 5) #define RF_ANA_RXABB_LDO_TRIM_BB(n) (((n)&0xf) << 8) #define RF_ANA_PGA_PKD_IBIAS_SEL_BB(n) (((n)&0x3) << 12) #define RF_ANA_PGA_PKD_RCTIME_SEL_BB(n) (((n)&0x3) << 14) // rxabb_dccal_ctrl_0 #define RF_ANA_RX_DCCAL_Q_BIT_BB(n) (((n)&0xff) << 0) #define RF_ANA_RX_DCCAL_I_BIT_BB(n) (((n)&0xff) << 8) // rxabb_dccal_ctrl_1 #define RF_ANA_RX_DCCAL_RANGE_BIT_BB(n) (((n)&0x3) << 14) // rxflt_ctrl_0 #define RF_ANA_RXFLT_IF_FREQ_BIT_BB(n) (((n)&0x7) << 3) #define RF_ANA_RXFLT_IF_EN_BB (1 << 6) #define RF_ANA_RXFLT_IF_SWAP_BB (1 << 7) #define RF_ANA_RXFLT_BWTUN_BIT_BB(n) (((n)&0xf) << 8) #define RF_ANA_RXFLT_BWMODE_BIT_BB(n) (((n)&0x7) << 12) #define RF_ANA_RXFLT_AUX_EN_BB (1 << 15) // rxflt_ctrl_1 #define RF_ANA_RXFLT_I_BIT_BB(n) (((n)&0x3) << 8) #define RF_ANA_RXFLT_OP_MILLERCN_BIT_BB(n) (((n)&0x3) << 10) #define RF_ANA_RXFLT_OP_MILLERCC_BIT_BB(n) (((n)&0x3) << 12) #define RF_ANA_ANTI_KICK_BACK_FILTER_BW_BB(n) (((n)&0x3) << 14) // rxflt_ctrl_2 #define RF_ANA_RXFLT_BWTUN_C2_BB(n) (((n)&0x7f) << 1) #define RF_ANA_RXFLT_BWTUN_C1_BB(n) (((n)&0xff) << 8) // adc_ldo_ctrl #define RF_ANA_ADC_LDO_OUT_TRIM_BB(n) (((n)&0x3) << 7) #define RF_ANA_ADC_LDO_IN_TRIM_BB(n) (((n)&0xf) << 9) #define RF_ANA_ADC_LDO_CP_TRIM_BB(n) (((n)&0x7) << 13) // adc_ctrl_0 #define RF_ANA_ADC_NS_ENH_BB (1 << 0) #define RF_ANA_ADC_NS_CHARGE_SET_TIME_CTRL_BB(n) (((n)&0x3) << 1) #define RF_ANA_ADC_MSB_DELAY_CTRL_BB(n) (((n)&0x3) << 3) #define RF_ANA_ADC_LOOP_DELAY_CTRL_BB(n) (((n)&0xf) << 5) #define RF_ANA_ADC_EN_LATCH_ADJUST_BB(n) (((n)&0x3) << 9) #define RF_ANA_ADC_CLKOUT_POLARITY_BB (1 << 11) #define RF_ANA_ADC_CLK_VIN_DELAY_CTRL_BB(n) (((n)&0x3) << 12) #define RF_ANA_ADC_CLK_RST_CTRL_BB(n) (((n)&0x3) << 14) // adc_ctrl_1 #define RF_ANA_ADC_OS_CODE_0P25_I_BB (1 << 0) #define RF_ANA_ADC_OS_CODE_0P5_I_BB (1 << 1) #define RF_ANA_ADC_OS_CODE_I_BB(n) (((n)&0x1f) << 2) #define RF_ANA_ADC_OS_CODE_0P25_Q_BB (1 << 8) #define RF_ANA_ADC_OS_CODE_0P5_Q_BB (1 << 9) #define RF_ANA_ADC_OS_CODE_Q_BB(n) (((n)&0x1f) << 10) // adc_ctrl_2 #define RF_ANA_ADC_INPUT_OS_VCM_CTRL_BB(n) (((n)&0x7) << 0) #define RF_ANA_ADC_STB_CTRL_BB(n) (((n)&0x7) << 3) #define RF_ANA_ADC_SAMP_HOLD_CTRL_BB(n) (((n)&0x3) << 6) #define RF_ANA_ADC_RESIDUAL_COMP_EN_BB (1 << 8) #define RF_ANA_ADC_RES_ADJUST_BB(n) (((n)&0x3) << 9) #define RF_ANA_ADC_OS_CAP_FLOW_Q_BB (1 << 11) #define RF_ANA_ADC_OS_CAP_FLOW_I_BB (1 << 12) #define RF_ANA_ADC_NS_VCM_CTRL_BB(n) (((n)&0x7) << 13) // adc_ctrl_3 #define RF_ANA_ADC_INPUT_SHORT_BB (1 << 0) #define RF_ANA_ADC_NS_SLAP_CTRL_BB (1 << 1) #define RF_ANA_ADC_CLK_SEL_BB(n) (((n)&0x3) << 3) #define RF_ANA_ADC_VRP_I_CTRL_BB(n) (((n)&0xf) << 5) #define RF_ANA_ADC_VRP_CTRL_BB(n) (((n)&0xf) << 9) #define RF_ANA_ADC_VCM_CTRL_BB(n) (((n)&0x7) << 13) // pwdadc_ctrl_0 #define RF_ANA_PWDADC_NS_ENH_BB (1 << 0) #define RF_ANA_PWDADC_NS_CHARGE_SET_TIME_CTRL_BB(n) (((n)&0x3) << 1) #define RF_ANA_PWDADC_MSB_DELAY_CTRL_BB(n) (((n)&0x3) << 3) #define RF_ANA_PWDADC_LOOP_DELAY_CTRL_BB(n) (((n)&0xf) << 5) #define RF_ANA_PWDADC_EN_LATCH_ADJUST_BB(n) (((n)&0x3) << 9) #define RF_ANA_PWDADC_CLKOUT_POLARITY_BB (1 << 11) #define RF_ANA_PWDADC_CLK_VIN_DELAY_CTRL_BB(n) (((n)&0x3) << 12) #define RF_ANA_PWDADC_CLK_RST_CTRL_BB(n) (((n)&0x3) << 14) // pwdadc_ctrl_1 #define RF_ANA_PWDADC_INPUT_SHORT_BB (1 << 0) #define RF_ANA_PWDADC_OS_CODE_I_BB(n) (((n)&0x1f) << 1) #define RF_ANA_PWDADC_OS_CODE_0P25_Q_BB (1 << 6) #define RF_ANA_PWDADC_OS_CODE_0P25_I_BB (1 << 7) #define RF_ANA_PWDADC_OS_CODE_0P5_Q_BB (1 << 8) #define RF_ANA_PWDADC_OS_CODE_0P5_I_BB (1 << 9) #define RF_ANA_PWDADC_OS_CAP_FLOW_Q_BB (1 << 10) #define RF_ANA_PWDADC_OS_CAP_FLOW_I_BB (1 << 11) #define RF_ANA_PWDADC_NS_VCM_CTRL_BB(n) (((n)&0x7) << 12) #define RF_ANA_PWDADC_NS_SLAP_CTRL_BB (1 << 15) // pwdadc_ctrl_2 #define RF_ANA_PWDADC_CLK_SEL_BB(n) (((n)&0x3) << 1) #define RF_ANA_PWDADC_STB_CTRL_BB(n) (((n)&0x7) << 3) #define RF_ANA_PWDADC_SAMP_HOLD_CTRL_BB(n) (((n)&0x3) << 6) #define RF_ANA_PWDADC_RESIDUAL_COMP_EN_BB (1 << 8) #define RF_ANA_PWDADC_RES_ADJUST_BB(n) (((n)&0x3) << 9) #define RF_ANA_PWDADC_OS_CODE_Q_BB(n) (((n)&0x1f) << 11) // pwdadc_ctrl_3 #define RF_ANA_PWDADC_INPUT_OS_VCM_CTRL_BB(n) (((n)&0x7) << 2) #define RF_ANA_PWDADC_VRP_I_CTRL_BB(n) (((n)&0xf) << 5) #define RF_ANA_PWDADC_VRP_CTRL_BB(n) (((n)&0xf) << 9) #define RF_ANA_PWDADC_VCM_CTRL_BB(n) (((n)&0x7) << 13) // rx_gain_ctrl #define RF_ANA_LNA_RESF_BIT_BB(n) (((n)&0x7) << 0) #define RF_ANA_RXFLT_GAIN_BIT_BB(n) (((n)&0xf) << 3) #define RF_ANA_PGA_GAIN_BIT_BB(n) (((n)&0x3) << 7) #define RF_ANA_LNA_VBC_BIT_BB(n) (((n)&0x7) << 9) #define RF_ANA_LNA_BIAS_BB(n) (((n)&0x3) << 12) #define RF_ANA_LNA_GAIN_BB(n) (((n)&0x3) << 14) // rx_reserve1 #define RF_ANA_RX_RESERVE1_BB(n) (((n)&0xffff) << 0) // rx_reserve2 #define RF_ANA_RX_RESERVE2_BB(n) (((n)&0xffff) << 0) // rx_reserve3 #define RF_ANA_RX_RESERVE3_BB(n) (((n)&0xffff) << 0) // txvco_ldo_ctrl #define RF_ANA_TXVCO_LDO_TRIM_BB(n) (((n)&0xf) << 6) #define RF_ANA_TXVCO_LDO_OUT_BB(n) (((n)&0x7) << 10) #define RF_ANA_TXVCO_LDO_SHORT_EN_BB (1 << 13) #define RF_ANA_TXVCO_LDO_POWERMODE_SEL_BB (1 << 14) #define RF_ANA_TXVCO_LDO_VCOMODE_SEL_BB (1 << 15) // txvco_buf_ldo_ctrl #define RF_ANA_TXVCOBUF_LDO_TRIM_BB(n) (((n)&0xf) << 6) #define RF_ANA_TXVCOBUF_LDO_OUT_BB(n) (((n)&0x7) << 10) #define RF_ANA_TXVCOBUF_LDO_SHORT_EN_BB (1 << 13) #define RF_ANA_TXVCOBUF_LDO_POWERMODE_SEL_BB (1 << 14) #define RF_ANA_TXVCOBUF_LDO_VCOMODE_SEL_BB (1 << 15) // txvco_ctrl_0 #define RF_ANA_TXVCO_VAR_REVERSE_BB (1 << 0) #define RF_ANA_TXVCO_VARBIAS_VBSEL_PTAT_BB(n) (((n)&0x3) << 1) #define RF_ANA_TXVCO_VARBIAS_VBSEL_CTAT_BB(n) (((n)&0x3) << 3) #define RF_ANA_TXVCO_VARBIAS_RCSEL_BB(n) (((n)&0x3) << 5) #define RF_ANA_TXVCO_VAR_SHORT_BB (1 << 7) #define RF_ANA_TXVCO_KTC_PTAT_BB(n) (((n)&0x7) << 8) #define RF_ANA_TXVCO_KTC_CTAT_BB(n) (((n)&0x7) << 11) #define RF_ANA_TXVCO_BIAS_SEL_BB (1 << 14) #define RF_ANA_TXVCO_BIAS_EXTRA_BB (1 << 15) // txvco_ctrl_1 #define RF_ANA_TXVCO_PKD_REF_CTRL_BB (1 << 3) #define RF_ANA_TXVCO_PKD_REF_BB(n) (((n)&0x7) << 4) #define RF_ANA_TXVCO_PKD_PDT_BB(n) (((n)&0x7) << 7) #define RF_ANA_TXVCO_VARDIF_BB(n) (((n)&0x7) << 10) #define RF_ANA_TXVCO_VARCOM_BB(n) (((n)&0x7) << 13) // txvco_ctrl_2 #define RF_ANA_TXRFDIV_PWD_EN_BB (1 << 1) #define RF_ANA_TXRFDIV_LTE_EN_BB (1 << 2) #define RF_ANA_TXRFDIV_DIV4_EN_BB (1 << 3) #define RF_ANA_TXRFDIV_DIV2_EN_BB (1 << 4) #define RF_ANA_TXVCO_RX_DIV1_EN_BB (1 << 5) #define RF_ANA_TXVCO_GNSS_EN_BB (1 << 6) #define RF_ANA_TXVCO_RXLTE_EN_BB (1 << 7) #define RF_ANA_TXVCO_TX_EN_BB (1 << 8) #define RF_ANA_TXVCO_LCL_DIV2_BB (1 << 10) #define RF_ANA_TXVCO_LCL_DIV1_BB (1 << 11) #define RF_ANA_TXVCO_CM_SCA_CTRL_BB(n) (((n)&0xf) << 12) // txpll_ldo_ctrl_0 #define RF_ANA_TXPLL_GRO_LDO_OUT_TRIM_BB(n) (((n)&0x3) << 1) #define RF_ANA_TXPLL_GRO_LDO_IN_TRIM_BB(n) (((n)&0xf) << 3) #define RF_ANA_TXPLL_PRESC_LDO_CRIPPLE_BB(n) (((n)&0x3) << 7) #define RF_ANA_TXPLL_PRESC_LDO_OUT_BB(n) (((n)&0x7) << 9) #define RF_ANA_TXPLL_PRESC_LDO_REF_TRIM_BB(n) (((n)&0xf) << 12) // txpll_ldo_ctrl_1 #define RF_ANA_TXPLL_RDAC_LDO_DIG_CRIPPLE_BB(n) (((n)&0x3) << 2) #define RF_ANA_TXPLL_RDAC_LDO_DIG_OUT_BB(n) (((n)&0x7) << 4) #define RF_ANA_TXPLL_RDAC_LDO_DIG_REF_TRIM_BB(n) (((n)&0xf) << 7) #define RF_ANA_TXPLL_GRO_LDO_RES_ADJUST_BB(n) (((n)&0x3) << 11) #define RF_ANA_TXPLL_GRO_LDO_CP_TRIM_BB(n) (((n)&0x7) << 13) // txpll_ldo_ctrl_2 #define RF_ANA_TXPLL_FBDIV_VDDRES_BB(n) (((n)&0x7) << 3) #define RF_ANA_TXPLL_RDAC_LDO_VREF_CRIPPLE_BB(n) (((n)&0x3) << 6) #define RF_ANA_TXPLL_RDAC_LDO_VREF_OUT_BB(n) (((n)&0xf) << 8) #define RF_ANA_TXPLL_RDAC_LDO_VREF_REF_TRIM_BB(n) (((n)&0xf) << 12) // txpll_gro_ctrl_0 #define RF_ANA_TXPLL_GRO_REG0_BB(n) (((n)&0xffff) << 0) // txpll_gro_ctrl_1 #define RF_ANA_TXPLL_GRO_REG1_BB(n) (((n)&0xffff) << 0) // txpll_gro_ctrl_2 #define RF_ANA_TXPLL_GRO_REG2_BB(n) (((n)&0xffff) << 0) // txpll_gro_ctrl_3 #define RF_ANA_TXPLL_GRO_REG3_BB(n) (((n)&0xffff) << 0) // txpll_ctrl_0 #define RF_ANA_TXPLL_RDAC_RCFLT_R_BB(n) (((n)&0x7) << 4) #define RF_ANA_TXPLL_OPEN_EN_BB (1 << 7) #define RF_ANA_TXPLL_SDMCLK_SEL_BB (1 << 8) #define RF_ANA_TXPLL_FBCSEL_BIT_BB(n) (((n)&0x7) << 9) #define RF_ANA_TXPLL_RDAC_CLK_EDGESEL_BB (1 << 12) #define RF_ANA_TXPLL_RDAC_VLOW_SELB_BB(n) (((n)&0x7) << 13) // txrf_gain #define RF_ANA_TXRF_GAIN3_BIT_BB(n) (((n)&0x7) << 1) #define RF_ANA_TXRF_GAIN2_BIT_BB(n) (((n)&0x1f) << 4) #define RF_ANA_TXRF_GAIN1_BIT_BB(n) (((n)&0x1f) << 9) #define RF_ANA_TXFLT_PH45_EN_BB (1 << 14) #define RF_ANA_TXRF_PH45_EN_BB (1 << 15) // txrf_gain_compensation #define RF_ANA_TXPAD_BIAS_IBIT_BB(n) (((n)&0x7) << 1) #define RF_ANA_TXRF_GAIN2C_N45_BIT_BB(n) (((n)&0xf) << 4) #define RF_ANA_TXRF_GAIN2C_P45_BIT_BB(n) (((n)&0xf) << 8) #define RF_ANA_TXRF_GAIN2C_BIT_BB(n) (((n)&0xf) << 12) // txrf_gain_adj #define RF_ANA_TXRF_LB2_EN_BB (1 << 3) #define RF_ANA_TXRF_LB1_EN_BB (1 << 4) #define RF_ANA_TXRF_HB2_EN_BB (1 << 5) #define RF_ANA_TXRF_HB1_EN_BB (1 << 6) #define RF_ANA_TXRF_BANDBALANCE_BIT_BB(n) (((n)&0x3) << 7) #define RF_ANA_TXRF_EN_BBLOAD_BB (1 << 9) #define RF_ANA_TXRF_SW_SEL2_BB (1 << 10) #define RF_ANA_TXRF_SW_SEL1_BB (1 << 11) #define RF_ANA_TXPAD_CAS_VBIT_BB(n) (((n)&0x3) << 12) #define RF_ANA_TXPAD_AUX_VBIT_BB(n) (((n)&0x3) << 14) // txrf_matchcap #define RF_ANA_TXRF_MIX_R2R_CBIT_BB (1 << 5) #define RF_ANA_TXRF_RCFLT_RBIT_BB(n) (((n)&0x3) << 6) #define RF_ANA_TXPAD_DEQ_BIT_BB(n) (((n)&0x3) << 8) #define RF_ANA_TXPAD_CAP_ULB_BIT_BB(n) (((n)&0x3) << 10) #define RF_ANA_TXPAD_CAP_BIT_BB(n) (((n)&0xf) << 12) // txflt_ctrl_0 #define RF_ANA_TXFLT_VCM_REF_BB(n) (((n)&0x7) << 0) #define RF_ANA_TXFLT_IBIAS_BIT_BB(n) (((n)&0x3) << 3) #define RF_ANA_TXFLT_CN_BB(n) (((n)&0x3) << 5) #define RF_ANA_TXFLT_CC_BB(n) (((n)&0x3) << 7) #define RF_ANA_TX_DCCAL_CLK_EDGESEL_BB (1 << 9) #define RF_ANA_TX_DCCAL_EN_BB (1 << 10) #define RF_ANA_TXFLT_LDO_CP_TUNE_BB(n) (((n)&0x3) << 11) #define RF_ANA_TXFLT_LDO_OUT_BB(n) (((n)&0x7) << 13) // txflt_ctrl_1 #define RF_ANA_TXFLT_BUFFER_IBIT_BB(n) (((n)&0x3) << 0) #define RF_ANA_TXFLT_BWTUN_BIT_BB(n) (((n)&0xff) << 2) #define RF_ANA_TXFLT_BW_BIT_BB(n) (((n)&0x7) << 10) #define RF_ANA_TXFLT_TESTIN_EN_BB (1 << 13) #define RF_ANA_TXFLT_HP_BIT_BB(n) (((n)&0x3) << 14) // dac_ctrl_0 #define RF_ANA_DAC_CORE_BIT_BB(n) (((n)&0x7) << 3) #define RF_ANA_DAC_VHIGH_BIT_BB(n) (((n)&0x7) << 6) #define RF_ANA_DAC_CLKEDGE_SEL_BB (1 << 9) #define RF_ANA_DAC_MUXEN_BIT_BB(n) (((n)&0x3) << 10) #define RF_ANA_DAC_IOUT_EN_BB (1 << 12) #define RF_ANA_DAC_AUXOUT_EN_BB (1 << 13) #define RF_ANA_DAC_RANGE_BIT_BB(n) (((n)&0x3) << 14) // dac_ctrl_1 #define RF_ANA_DAC_LDO_OUT_BB(n) (((n)&0x7) << 1) #define RF_ANA_DAC_LDO_CP_TUNE_BB(n) (((n)&0x3) << 4) #define RF_ANA_DAC_TIA_OPAMP_FBCAP_BIT_BB(n) (((n)&0x3) << 6) #define RF_ANA_DAC_TIA_CMO_BIT_BB(n) (((n)&0x3) << 8) #define RF_ANA_DAC_TIA_CMI_BIT_BB(n) (((n)&0x3) << 10) // gnss_clkgen_ctrl_0 #define RF_ANA_GNSS_CLKGEN_M4_CLK_DIV_BB(n) (((n)&0xf) << 0) #define RF_ANA_GNSS_CLKGEN_M4_CLK_BUFSEL_BB(n) (((n)&0x3) << 4) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_VRES_BB(n) (((n)&0x7) << 6) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_DIV_BB(n) (((n)&0x1f) << 9) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_BUFSEL_BB(n) (((n)&0x3) << 14) // gnss_clkgen_ctrl_1 #define RF_ANA_GNSS_CLKGEN_TSX_ADC_CLK_BUFSEL_BB(n) (((n)&0x3) << 1) #define RF_ANA_GNSS_CLKGEN_PP_CLK_VRES_BB(n) (((n)&0x7) << 3) #define RF_ANA_GNSS_CLKGEN_PP_CLK_DIV_BB(n) (((n)&0x1f) << 6) #define RF_ANA_GNSS_CLKGEN_PP_CLK_BUFSEL_BB(n) (((n)&0x3) << 11) #define RF_ANA_GNSS_CLKGEN_M4_CLK_VRES_BB(n) (((n)&0x7) << 13) // gnss_clkgen_ctrl_2 #define RF_ANA_GNSS_CLKGEN_ANA_ADC_CLK_DIV_BB(n) (((n)&0x7f) << 0) #define RF_ANA_GNSS_CLKGEN_ANA_ADC_CLK_BUFSEL_BB(n) (((n)&0x3) << 7) #define RF_ANA_GNSS_CLKGEN_TSX_ADC_CLK_VRES_BB(n) (((n)&0x7) << 9) #define RF_ANA_GNSS_CLKGEN_TSX_ADC_CLK_DIV_BB(n) (((n)&0xf) << 12) // gnss_clkgen_ctrl_3 #define RF_ANA_GNSS_CLKGEN_M4_CLK_FRAC_SEL_BB (1 << 1) #define RF_ANA_GNSS_CLKGEN_M4_CLK_FRAC_DIVN_BB(n) (((n)&0x7) << 2) #define RF_ANA_GNSS_CLKGEN_M4_CLK_FRAC_DIVF_BB(n) (((n)&0x7) << 5) #define RF_ANA_GNSS_CLKGEN_M4_CLK_DIV_FRAC_EN_BB (1 << 8) #define RF_ANA_GNSS_CLKGEN_PP_CLK_MUX_BB(n) (((n)&0x3) << 9) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_MUX_BB(n) (((n)&0x3) << 11) #define RF_ANA_GNSS_CLKGEN_ANA_ADC_CLK_VRES_BB(n) (((n)&0x7) << 13) // gnss_clkgen_ctrl_4 #define RF_ANA_GNSS_CLKGEN_ANA_ADC_CLK_EN_BB (1 << 6) #define RF_ANA_GNSS_CLKGEN_ANA_ADC_CLK_DIV_EN_BB (1 << 7) #define RF_ANA_GNSS_CLKGEN_TSX_ADC_CLK_EN_BB (1 << 8) #define RF_ANA_GNSS_CLKGEN_TSX_ADC_CLK_DIV_EN_BB (1 << 9) #define RF_ANA_GNSS_CLKGEN_PP_CLK_EN_BB (1 << 10) #define RF_ANA_GNSS_CLKGEN_PP_CLK_DIV_EN_BB (1 << 11) #define RF_ANA_GNSS_CLKGEN_M4_CLK_EN_BB (1 << 12) #define RF_ANA_GNSS_CLKGEN_M4_CLK_DIV_EN_BB (1 << 13) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_EN_BB (1 << 14) #define RF_ANA_GNSS_CLKGEN_ADC_CLK_OUT_DIV_EN_BB (1 << 15) // rxflt_dccal #define RF_ANA_RXFLT_DCCAL_Q_BIT_BB(n) (((n)&0xff) << 0) #define RF_ANA_RXFLT_DCCAL_I_BIT_BB(n) (((n)&0xff) << 8) // tx_reserve_0 #define RF_ANA_LTE_TX_RSV_09_H_BB(n) (((n)&0xffff) << 0) // tx_reserve_1 #define RF_ANA_LTE_TX_RSV_18_BB(n) (((n)&0xff) << 0) #define RF_ANA_LTE_TX_RSV_09_L_BB(n) (((n)&0xff) << 8) // pwd_ctrl_0 #define RF_ANA_PWD_PGA_CC_BIT_BB(n) (((n)&0x3) << 3) #define RF_ANA_PWD_PGA_CN_BIT_BB(n) (((n)&0x3) << 5) #define RF_ANA_PWD_PGA_LDO_RES_ADJ_BB(n) (((n)&0x3) << 7) #define RF_ANA_PWD_MGAIN_BIT_BB(n) (((n)&0x7) << 9) #define RF_ANA_PWD_PGA_RES_BIT_BB(n) (((n)&0xf) << 12) // pwd_ctrl_1 #define RF_ANA_PWD_PGA_CAP_BIT_BB(n) (((n)&0xf) << 12) // pwd_ctrl_2 #define RF_ANA_PWD_CAL_Q_EN_BB (1 << 0) #define RF_ANA_PWD_CAL_Q_DONE_BB (1 << 1) #define RF_ANA_PWD_CAL_Q_BB(n) (((n)&0x3f) << 2) #define RF_ANA_PWD_CAL_I_EN_BB (1 << 8) #define RF_ANA_PWD_CAL_I_DONE_BB (1 << 9) #define RF_ANA_PWD_CAL_I_BB(n) (((n)&0x3f) << 10) // ts_ctrl_0 #define RF_ANA_TS_ADC_IBIT_BB(n) (((n)&0x7) << 0) #define RF_ANA_TS_REFSEL_BIT_BB(n) (((n)&0x3) << 3) #define RF_ANA_TS_DIV_BIT_BB(n) (((n)&0xf) << 5) #define RF_ANA_TS_CHOPPER_EN_BB (1 << 9) #define RF_ANA_TS_XTALTEST_EN_BB (1 << 10) #define RF_ANA_TS_PWDEXT_EN_BB (1 << 11) #define RF_ANA_TS_PWDINT_EN_BB (1 << 12) #define RF_ANA_PU_TS_BB (1 << 13) #define RF_ANA_TS_LDO_FAST_CHARGE_EN_BB (1 << 14) #define RF_ANA_TS_LDO_EN_BB (1 << 15) // ts_ctrl_1 #define RF_ANA_TS_CLK_DIVEDGE_SEL_BB (1 << 0) #define RF_ANA_TS_CLK_EDGESEL_BB (1 << 1) #define RF_ANA_TS_CLKSEL_BIT_BB(n) (((n)&0x3) << 2) #define RF_ANA_TS_BETA_EN_BB (1 << 4) #define RF_ANA_TS_VBE_SDMBIT_BB (1 << 5) #define RF_ANA_TS_TESTMODE_EN_BB (1 << 6) #define RF_ANA_TS_RESETN_BB (1 << 7) #define RF_ANA_TS_VBE_BIT_BB(n) (((n)&0xff) << 8) // ts_ctrl_2 #define RF_ANA_TS_LDO_OUT_BB(n) (((n)&0x7) << 11) #define RF_ANA_TS_LDO_CP_TUNE_BB(n) (((n)&0x3) << 14) // cm_reserve1 #define RF_ANA_CM_RESERVE1_BB(n) (((n)&0xffff) << 0) // cm_reserve2 #define RF_ANA_CM_RESERVE2_BB(n) (((n)&0xffff) << 0) // cm_reserve3 #define RF_ANA_CM_RESERVE3_BB(n) (((n)&0xffff) << 0) // revid_reg #define RF_ANA_REVID(n) (((n)&0xff) << 0) // test_ctrl_0 #define RF_ANA_RX_LO_TEST_EN_BB (1 << 0) #define RF_ANA_RX_4G_TEST_EN_BB (1 << 1) #define RF_ANA_RX_5G_TEST_EN_BB (1 << 2) #define RF_ANA_TEST_TXVCO_EN_BB (1 << 3) #define RF_ANA_TEST_LDOREF_RXVCOBUF_SW_EN_BB (1 << 4) #define RF_ANA_TEST_LDOREF_RXVCO_SW_EN_BB (1 << 5) #define RF_ANA_TEST_LDOREF_RXABB_SW_EN_BB (1 << 6) #define RF_ANA_TEST_LDOREF_TXVCOBUF_SW_EN_BB (1 << 7) #define RF_ANA_TEST_LDOREF_TXVCO_SW_EN_BB (1 << 8) #define RF_ANA_TEST_BG_CAL_R_EN_BB (1 << 9) #define RF_ANA_TEST_CLK_MDLL_SW_EN_BB (1 << 10) #define RF_ANA_TEST_LDOREF_ADC_SW_EN_BB (1 << 11) #define RF_ANA_TEST_MDLL_VCTRL_SW_EN_BB (1 << 12) #define RF_ANA_PLL_TEST_EN_BB (1 << 13) #define RF_ANA_DAC_OUT_EN_BB (1 << 14) #define RF_ANA_TX_IF_EN_BB (1 << 15) // test_ctrl_1 #define RF_ANA_CAL_RXIQ_ATT_CTRL_BB(n) (((n)&0x1f) << 1) #define RF_ANA_CAL_RXIQ_DIV4_EN_BB (1 << 6) #define RF_ANA_CAL_RXIQ_DIV2_EN_BB (1 << 7) #define RF_ANA_TEST_IQ_ADCINPUT_SW_EN_BB (1 << 8) #define RF_ANA_TEST_LDOREF_TXPLL_RDAC_SW_EN_BB (1 << 9) #define RF_ANA_TEST_LDOREF_RXPLL_RDAC_SW_EN_BB (1 << 10) #define RF_ANA_TEST_VPA_TS_SW_EN_BB (1 << 11) #define RF_ANA_TEST_VREF_TS_SW_EN_BB (1 << 12) #define RF_ANA_TEST_VR_TS_SW_EN_BB (1 << 13) #define RF_ANA_TEST_VL_TS_SW_EN_BB (1 << 14) #define RF_ANA_TEST_CLK_TS_SW_EN_BB (1 << 15) // cal_ctrl_0 #define RF_ANA_CAL_RXIQ_ATT_ADJ_BB(n) (((n)&0xf) << 0) #define RF_ANA_TX_ED_IBG_BB(n) (((n)&0x7) << 4) #define RF_ANA_TX_ED_IBP_BB(n) (((n)&0x7) << 7) #define RF_ANA_TXPAD_ATT_CTL_BB(n) (((n)&0x3) << 10) #define RF_ANA_CAL_RXIQ_EN_BB (1 << 12) #define RF_ANA_CAL_RXIQ_MIX_SEL_BB (1 << 13) #define RF_ANA_CAL_TXIQ_EN_BB (1 << 14) #define RF_ANA_CAL_TXIQ_SEL_BB (1 << 15) // rf_output_readonly_0 #define RF_ANA_TXPLL_LOCK_BB (1 << 6) #define RF_ANA_RXPLL_LOCK_BB (1 << 7) #define RF_ANA_TXVCO_PKDET_OUT_BB (1 << 8) #define RF_ANA_RXVCO_PKDET_OUT_BB (1 << 9) #define RF_ANA_PGA_PKD_OUT_BB(n) (((n)&0x3) << 10) #define RF_ANA_LNA_PKD_OUT_2_BB (1 << 12) #define RF_ANA_LNA_PKD_OUT_1_BB (1 << 13) #define RF_ANA_TX_DCCAL_OUTQ_BB (1 << 14) #define RF_ANA_TX_DCCAL_OUTI_BB (1 << 15) // rf_output_readonly_1 #define RF_ANA_PWDADC_CONV_DONE_Q_WO_NS_BB (1 << 8) #define RF_ANA_PWDADC_CONV_DONE_I_WO_NS_BB (1 << 9) #define RF_ANA_PWDADC_CONV_DONE_Q_WI_NS_BB (1 << 10) #define RF_ANA_PWDADC_CONV_DONE_I_WI_NS_BB (1 << 11) #define RF_ANA_ADC_CONV_DONE_Q_WO_NS_BB (1 << 12) #define RF_ANA_ADC_CONV_DONE_I_WO_NS_BB (1 << 13) #define RF_ANA_ADC_CONV_DONE_Q_WI_NS_BB (1 << 14) #define RF_ANA_ADC_CONV_DONE_I_WI_NS_BB (1 << 15) // tsenadc_ctrl_0 #define RF_ANA_RG_TSEN_CHOP_CLKSEL_BB(n) (((n)&0x3) << 0) #define RF_ANA_RG_TSEN_ADCLDOREF_BB(n) (((n)&0x1f) << 6) #define RF_ANA_RG_TSEN_ADCLDO_V_BB(n) (((n)&0xf) << 11) #define RF_ANA_RG_TSEN_ADCLDO_EN_BB (1 << 15) // tsenadc_ctrl_1 #define RF_ANA_RG_TSEN_SDADC_EN_BB (1 << 8) #define RF_ANA_RG_TSEN_SDADC_DATA_EDGE_SEL_BB (1 << 9) #define RF_ANA_RG_TSEN_SDADC_CHOP_EN_BB (1 << 10) #define RF_ANA_RG_TSEN_SDADC_CAPCHOP_EN_BB (1 << 11) #define RF_ANA_RG_TSEN_SDADC_BIAS_BB(n) (((n)&0x3) << 12) #define RF_ANA_RG_TSEN_CLKSEL_BB(n) (((n)&0x3) << 14) // tsenadc_ctrl_2 #define RF_ANA_RG_TSEN_UGBUF_CTRL_BB(n) (((n)&0x3) << 2) #define RF_ANA_RG_TSEN_UGBUF_CHOP_EN_BB (1 << 4) #define RF_ANA_RG_TSEN_UGBUF_BIAS_BB(n) (((n)&0x3) << 5) #define RF_ANA_RG_TSEN_TEST_CLK_SEL_BB (1 << 7) #define RF_ANA_RG_TSEN_SDADC_VCMO_BB(n) (((n)&0x3) << 8) #define RF_ANA_RG_TSEN_SDADC_VCMI_BB(n) (((n)&0x3) << 10) #define RF_ANA_RG_TSEN_SDADC_UGBUF_EN_BB (1 << 12) #define RF_ANA_RG_TSEN_SDADC_RST_BB (1 << 13) #define RF_ANA_RG_TSEN_SDADC_OFFSET_EN_BB (1 << 14) #define RF_ANA_RG_TSEN_SDADC_INPUT_EN_BB (1 << 15) // apc_ctrl_0 #define RF_ANA_PU_RAMP_DAC_BB (1 << 6) #define RF_ANA_APC_PGA_IBIT_BB(n) (((n)&0x3) << 7) #define RF_ANA_APC_LV_GAIN_BIT_BB(n) (((n)&0x7) << 9) #define RF_ANA_APC_HV_GAIN_BIT_BB(n) (((n)&0x7) << 12) #define RF_ANA_APC_BPRC_BB (1 << 15) // apc_ctrl_1 #define RF_ANA_RAMP_DAC_DIN_BB(n) (((n)&0x3ff) << 0) #endif // _RF_ANA_H_