/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _RF_INTF_H_ #define _RF_INTF_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_RF_INTF_SET_OFFSET (1024) #define REG_RF_INTF_CLR_OFFSET (2048) #define REG_RF_INTF_BASE (0x50030000) typedef volatile struct { uint32_t __0[64]; // 0x00000000 uint32_t apb_reg_int0; // 0x00000100 uint32_t apb_reg_int1; // 0x00000104 uint32_t apb_reg_int2; // 0x00000108 uint32_t apb_reg_int3; // 0x0000010c uint32_t apb_reg_int4; // 0x00000110 uint32_t apb_reg_int5; // 0x00000114 uint32_t apb_reg_int6; // 0x00000118 uint32_t apb_reg_int7; // 0x0000011c uint32_t apb_reg_int8; // 0x00000120 uint32_t apb_reg_int9; // 0x00000124 uint32_t apb_reg_int_res10; // 0x00000128 uint32_t apb_reg_int_res11; // 0x0000012c uint32_t apb_reg_int_res12; // 0x00000130 uint32_t apb_reg_int_res13; // 0x00000134 uint32_t apb_reg_int_res14; // 0x00000138 uint32_t apb_reg_int_res15; // 0x0000013c uint32_t __320[48]; // 0x00000140 uint32_t int_clear0; // 0x00000200 uint32_t int_clear1; // 0x00000204 uint32_t int2tmcu0; // 0x00000208 uint32_t int2tmcu1; // 0x0000020c uint32_t irq_enable0; // 0x00000210 uint32_t irq_enable1; // 0x00000214 uint32_t irq_raw0; // 0x00000218 uint32_t irq_raw1; // 0x0000021c uint32_t irq_select; // 0x00000220 uint32_t afc_freq_bbpll1; // 0x00000224 uint32_t afc_freq_bbpll12; // 0x00000228 uint32_t afc_freq_bbpll2; // 0x0000022c uint32_t afc_freq_offset_mode; // 0x00000230 uint32_t freq_offset_ini_bbpll1_reg1; // 0x00000234 uint32_t freq_offset_ini_bbpll1_reg2; // 0x00000238 uint32_t freq_offset_ini_bbpll2_reg1; // 0x0000023c uint32_t bbpll1_reg1; // 0x00000240 uint32_t bbpll1_reg2; // 0x00000244 uint32_t bbpll1_reg3; // 0x00000248 uint32_t bbpll1_reg5; // 0x0000024c uint32_t bbpll1_reg6; // 0x00000250 uint32_t bbpll1_reg7; // 0x00000254 uint32_t bbpll1_reg8; // 0x00000258 uint32_t bbpll1_reg9; // 0x0000025c uint32_t bbpll1_rega; // 0x00000260 uint32_t bbpll1_regb; // 0x00000264 uint32_t bbpll1_regd; // 0x00000268 uint32_t bbpll2_reg1; // 0x0000026c uint32_t bbpll2_reg2; // 0x00000270 uint32_t bbpll2_reg3; // 0x00000274 uint32_t bbpll2_reg5; // 0x00000278 uint32_t bbpll2_reg6; // 0x0000027c uint32_t bbpll2_reg7; // 0x00000280 uint32_t bbpll2_reg8; // 0x00000284 uint32_t bbpll2_reg9; // 0x00000288 uint32_t bbpll2_rega; // 0x0000028c uint32_t bbpll2_regb; // 0x00000290 uint32_t bbpll2_regd; // 0x00000294 uint32_t clk_gen_reg0; // 0x00000298 uint32_t clk_gen_reg1; // 0x0000029c uint32_t txpll_freq_l; // 0x000002a0 uint32_t txpll_freq_m; // 0x000002a4 uint32_t txpll_freq_h; // 0x000002a8 uint32_t txpll_sdm_ctrl; // 0x000002ac uint32_t txpll_freq_offset_l; // 0x000002b0 uint32_t txpll_freq_offset_h; // 0x000002b4 uint32_t txpll_freq_offset_ini_l; // 0x000002b8 uint32_t txpll_freq_offset_ini_h; // 0x000002bc uint32_t txpll_sx_ctrl1; // 0x000002c0 uint32_t txpll_sx_ctrl2; // 0x000002c4 uint32_t txpll_sx_ctrl3; // 0x000002c8 uint32_t txpll_sx_ctrl4; // 0x000002cc uint32_t txpll_sx_ctrl5; // 0x000002d0 uint32_t txpll_sx_ctrl6; // 0x000002d4 uint32_t txpll_sx_ctrl7; // 0x000002d8 uint32_t txpll_sx_stat1; // 0x000002dc uint32_t txpll_sx_stat2; // 0x000002e0 uint32_t txpll_sx_stat3; // 0x000002e4 uint32_t txpll_sx_stat4; // 0x000002e8 uint32_t txpll_sx_stat5; // 0x000002ec uint32_t txpll_sx_stat6; // 0x000002f0 uint32_t rxpll_freq_l; // 0x000002f4 uint32_t rxpll_freq_m; // 0x000002f8 uint32_t rxpll_freq_h; // 0x000002fc uint32_t rxpll_sdm_ctrl; // 0x00000300 uint32_t rxpll_freq_offset_l; // 0x00000304 uint32_t rxpll_freq_offset_h; // 0x00000308 uint32_t rxpll_freq_offset_ini_l; // 0x0000030c uint32_t rxpll_freq_offset_ini_h; // 0x00000310 uint32_t rxpll_sx_ctrl1; // 0x00000314 uint32_t rxpll_sx_ctrl2; // 0x00000318 uint32_t rxpll_sx_ctrl3; // 0x0000031c uint32_t rxpll_sx_ctrl4; // 0x00000320 uint32_t rxpll_sx_ctrl5; // 0x00000324 uint32_t rxpll_sx_ctrl6; // 0x00000328 uint32_t rxpll_sx_ctrl7; // 0x0000032c uint32_t rxpll_sx_stat1; // 0x00000330 uint32_t rxpll_sx_stat2; // 0x00000334 uint32_t rxpll_sx_stat3; // 0x00000338 uint32_t rxpll_sx_stat4; // 0x0000033c uint32_t rxpll_sx_stat5; // 0x00000340 uint32_t rxpll_sx_stat6; // 0x00000344 uint32_t peak_det_clr; // 0x00000348 uint32_t peak_det_sta; // 0x0000034c uint32_t peak_det_num1; // 0x00000350 uint32_t peak_det_num2; // 0x00000354 uint32_t peak_det_trig_num1; // 0x00000358 uint32_t peak_det_trig_num2; // 0x0000035c uint32_t __864[168]; // 0x00000360 uint32_t int_clear0_set; // 0x00000600 uint32_t int_clear1_set; // 0x00000604 uint32_t __1544[2]; // 0x00000608 uint32_t irq_enable0_set; // 0x00000610 uint32_t irq_enable1_set; // 0x00000614 uint32_t __1560[2]; // 0x00000618 uint32_t irq_select_set; // 0x00000620 uint32_t __1572[3]; // 0x00000624 uint32_t afc_freq_offset_mode_set; // 0x00000630 uint32_t __1588[3]; // 0x00000634 uint32_t bbpll1_reg1_set; // 0x00000640 uint32_t bbpll1_reg2_set; // 0x00000644 uint32_t __1608[3]; // 0x00000648 uint32_t bbpll1_reg7_set; // 0x00000654 uint32_t __1624[2]; // 0x00000658 uint32_t bbpll1_rega_set; // 0x00000660 uint32_t __1636[1]; // 0x00000664 uint32_t bbpll1_regd_set; // 0x00000668 uint32_t bbpll2_reg1_set; // 0x0000066c uint32_t bbpll2_reg2_set; // 0x00000670 uint32_t __1652[3]; // 0x00000674 uint32_t bbpll2_reg7_set; // 0x00000680 uint32_t __1668[2]; // 0x00000684 uint32_t bbpll2_rega_set; // 0x0000068c uint32_t __1680[1]; // 0x00000690 uint32_t bbpll2_regd_set; // 0x00000694 uint32_t clk_gen_reg0_set; // 0x00000698 uint32_t clk_gen_reg1_set; // 0x0000069c uint32_t __1696[3]; // 0x000006a0 uint32_t txpll_sdm_ctrl_set; // 0x000006ac uint32_t __1712[4]; // 0x000006b0 uint32_t txpll_sx_ctrl1_set; // 0x000006c0 uint32_t txpll_sx_ctrl2_set; // 0x000006c4 uint32_t __1736[4]; // 0x000006c8 uint32_t txpll_sx_ctrl7_set; // 0x000006d8 uint32_t __1756[9]; // 0x000006dc uint32_t rxpll_sdm_ctrl_set; // 0x00000700 uint32_t __1796[4]; // 0x00000704 uint32_t rxpll_sx_ctrl1_set; // 0x00000714 uint32_t rxpll_sx_ctrl2_set; // 0x00000718 uint32_t __1820[4]; // 0x0000071c uint32_t rxpll_sx_ctrl7_set; // 0x0000072c uint32_t __1840[6]; // 0x00000730 uint32_t peak_det_clr_set; // 0x00000748 uint32_t __1868[173]; // 0x0000074c uint32_t int_clear0_clr; // 0x00000a00 uint32_t int_clear1_clr; // 0x00000a04 uint32_t __2568[2]; // 0x00000a08 uint32_t irq_enable0_clr; // 0x00000a10 uint32_t irq_enable1_clr; // 0x00000a14 uint32_t __2584[2]; // 0x00000a18 uint32_t irq_select_clr; // 0x00000a20 uint32_t __2596[3]; // 0x00000a24 uint32_t afc_freq_offset_mode_clr; // 0x00000a30 uint32_t __2612[3]; // 0x00000a34 uint32_t bbpll1_reg1_clr; // 0x00000a40 uint32_t bbpll1_reg2_clr; // 0x00000a44 uint32_t __2632[3]; // 0x00000a48 uint32_t bbpll1_reg7_clr; // 0x00000a54 uint32_t __2648[2]; // 0x00000a58 uint32_t bbpll1_rega_clr; // 0x00000a60 uint32_t __2660[1]; // 0x00000a64 uint32_t bbpll1_regd_clr; // 0x00000a68 uint32_t bbpll2_reg1_clr; // 0x00000a6c uint32_t bbpll2_reg2_clr; // 0x00000a70 uint32_t __2676[3]; // 0x00000a74 uint32_t bbpll2_reg7_clr; // 0x00000a80 uint32_t __2692[2]; // 0x00000a84 uint32_t bbpll2_rega_clr; // 0x00000a8c uint32_t __2704[1]; // 0x00000a90 uint32_t bbpll2_regd_clr; // 0x00000a94 uint32_t clk_gen_reg0_clr; // 0x00000a98 uint32_t clk_gen_reg1_clr; // 0x00000a9c uint32_t __2720[3]; // 0x00000aa0 uint32_t txpll_sdm_ctrl_clr; // 0x00000aac uint32_t __2736[4]; // 0x00000ab0 uint32_t txpll_sx_ctrl1_clr; // 0x00000ac0 uint32_t txpll_sx_ctrl2_clr; // 0x00000ac4 uint32_t __2760[4]; // 0x00000ac8 uint32_t txpll_sx_ctrl7_clr; // 0x00000ad8 uint32_t __2780[9]; // 0x00000adc uint32_t rxpll_sdm_ctrl_clr; // 0x00000b00 uint32_t __2820[4]; // 0x00000b04 uint32_t rxpll_sx_ctrl1_clr; // 0x00000b14 uint32_t rxpll_sx_ctrl2_clr; // 0x00000b18 uint32_t __2844[4]; // 0x00000b1c uint32_t rxpll_sx_ctrl7_clr; // 0x00000b2c uint32_t __2864[6]; // 0x00000b30 uint32_t peak_det_clr_clr; // 0x00000b48 } HWP_RF_INTF_T; #define hwp_rfIntf ((HWP_RF_INTF_T *)REG_ACCESS_ADDRESS(REG_RF_INTF_BASE)) // apb_reg_int0 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int0 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT0_T; // apb_reg_int1 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int1 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT1_T; // apb_reg_int2 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int2 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT2_T; // apb_reg_int3 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int3 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT3_T; // apb_reg_int4 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int4 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT4_T; // apb_reg_int5 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int5 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT5_T; // apb_reg_int6 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int6 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT6_T; // apb_reg_int7 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int7 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT7_T; // apb_reg_int8 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int8 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT8_T; // apb_reg_int9 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int9 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT9_T; // apb_reg_int_res10 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res10 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES10_T; // apb_reg_int_res11 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res11 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES11_T; // apb_reg_int_res12 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res12 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES12_T; // apb_reg_int_res13 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res13 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES13_T; // apb_reg_int_res14 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res14 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES14_T; // apb_reg_int_res15 typedef union { uint32_t v; struct { uint32_t rg_apb_reg_int_res15 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_APB_REG_INT_RES15_T; // int_clear0 typedef union { uint32_t v; struct { uint32_t rg_irq_clr_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_INT_CLEAR0_T; // int_clear1 typedef union { uint32_t v; struct { uint32_t rg_irq_clr_h : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_INT_CLEAR1_T; // int2tmcu0 typedef union { uint32_t v; struct { uint32_t irq_out_l : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_INT2TMCU0_T; // int2tmcu1 typedef union { uint32_t v; struct { uint32_t irq_out_h : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_INT2TMCU1_T; // irq_enable0 typedef union { uint32_t v; struct { uint32_t rg_irq_en_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_IRQ_ENABLE0_T; // irq_enable1 typedef union { uint32_t v; struct { uint32_t rg_irq_en_h : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_IRQ_ENABLE1_T; // irq_raw0 typedef union { uint32_t v; struct { uint32_t irq_raw_l : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_IRQ_RAW0_T; // irq_raw1 typedef union { uint32_t v; struct { uint32_t irq_raw_h : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_IRQ_RAW1_T; // irq_select typedef union { uint32_t v; struct { uint32_t rg_irq_sel : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_IRQ_SELECT_T; // afc_freq_bbpll1 typedef union { uint32_t v; struct { uint32_t freq_offset_bbpll11 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_AFC_FREQ_BBPLL1_T; // afc_freq_bbpll12 typedef union { uint32_t v; struct { uint32_t freq_offset_bbpll22 : 8; // [7:0] uint32_t freq_offset_bbpll12 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_AFC_FREQ_BBPLL12_T; // afc_freq_bbpll2 typedef union { uint32_t v; struct { uint32_t freq_offset_bbpll21 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_AFC_FREQ_BBPLL2_T; // afc_freq_offset_mode typedef union { uint32_t v; struct { uint32_t freq_offset_mode_bbpll1 : 1; // [0] uint32_t freq_offset_mode_bbpll2 : 1; // [1] uint32_t freq_offset_enable_bbpll1 : 1; // [2] uint32_t freq_offset_enable_bbpll2 : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_RF_INTF_AFC_FREQ_OFFSET_MODE_T; // freq_offset_ini_bbpll1_reg1 typedef union { uint32_t v; struct { uint32_t freq_offset_ini_bbpll11 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_FREQ_OFFSET_INI_BBPLL1_REG1_T; // freq_offset_ini_bbpll1_reg2 typedef union { uint32_t v; struct { uint32_t freq_offset_ini_bbpll12 : 8; // [7:0] uint32_t freq_offset_ini_bbpll22 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_FREQ_OFFSET_INI_BBPLL1_REG2_T; // freq_offset_ini_bbpll2_reg1 typedef union { uint32_t v; struct { uint32_t freq_offset_ini_bbpll21 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_FREQ_OFFSET_INI_BBPLL2_REG1_T; // bbpll1_reg1 typedef union { uint32_t v; struct { uint32_t plls1_ldo_fast_charge_en_bb : 1; // [0] uint32_t plls1_ldo_en_bb : 1; // [1] uint32_t plls1_notch_en_bb : 1; // [2] uint32_t __3_3 : 1; // [3] uint32_t plls1_cpr_ibit_bb : 3; // [6:4] uint32_t plls1_cpc_ibit_bb : 3; // [9:7] uint32_t plls1_cpbias_bit_bb : 3; // [12:10] uint32_t plls1_ldo_out_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG1_T; // bbpll1_reg2 typedef union { uint32_t v; struct { uint32_t pu_pll_reg_rx : 1; // [0] uint32_t pu_pll_dr_rx : 1; // [1] uint32_t pll_sdm_clk_sel_nor_rx : 1; // [2] uint32_t pll_sdm_clk_sel_rst_rx : 1; // [3] uint32_t pll_sdm_clk_test_en_rx : 1; // [4] uint32_t pll_test_en_rx : 1; // [5] uint32_t pll_low_test_rx : 1; // [6] uint32_t pll_high_test_rx : 1; // [7] uint32_t pll_refmulti2_en_rx : 1; // [8] uint32_t pll_pcon_mode_rx : 1; // [9] uint32_t pll_lpmode_en_rx : 1; // [10] uint32_t pll_dly_num_pfd_rx : 3; // [13:11] uint32_t pll_ldo_fastcharge_cnt_rx : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG2_T; // bbpll1_reg5 typedef union { uint32_t v; struct { uint32_t pll_sdm_freq_rx1 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG5_T; // bbpll1_reg6 typedef union { uint32_t v; struct { uint32_t pll_sdm_freq_rx0 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG6_T; // bbpll1_reg7 typedef union { uint32_t v; struct { uint32_t pll_sdm_resetn_reg_rx : 1; // [0] uint32_t pll_sdm_resetn_dr_rx : 1; // [1] uint32_t ss_squre_tri_sel_rx : 1; // [2] uint32_t ss_en_rx : 1; // [3] uint32_t dither_bypass_rx : 1; // [4] uint32_t int_dec_sel_rx : 3; // [7:5] uint32_t reser_sdm_rx : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG7_T; // bbpll1_reg8 typedef union { uint32_t v; struct { uint32_t pll_ss_peri_ct_rx : 8; // [7:0] uint32_t pll_ss_devi_ct_rx : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REG8_T; // bbpll1_rega typedef union { uint32_t v; struct { uint32_t clk_gen_en_reg_rx : 1; // [0] uint32_t pll_clkout_en_reg_rx : 4; // [4:1] uint32_t pll_clk_adc_dfe_en_reg_rx : 1; // [5] uint32_t pll_clk_adc_en_reg_rx : 1; // [6] uint32_t pll_clk_adc_sel_reg_rx : 2; // [8:7] uint32_t pll_clk_dfe_sel_reg_rx : 2; // [10:9] uint32_t sdmclk_sel_time_sel_rx : 2; // [12:11] uint32_t sdm_reset_time_sel_rx : 2; // [14:13] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_INTF_BBPLL1_REGA_T; // bbpll1_regb typedef union { uint32_t v; struct { uint32_t __9_0 : 10; // [9:0] uint32_t pll_lock_steady_rx : 1; // [10], read only uint32_t rxpll_sx_cal_state : 3; // [13:11], read only uint32_t pll_lock_rx : 1; // [14], read only uint32_t pu_pll_rx : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL1_REGB_T; // bbpll1_regd typedef union { uint32_t v; struct { uint32_t lock_counter_sel_rx : 2; // [1:0] uint32_t pll_clkout_en_counter_sel_rx : 2; // [3:2] uint32_t vco_reset_dis_rx : 1; // [4] uint32_t resetn_spll_rx : 1; // [5] uint32_t plls1_ldo_cp_tune_bb : 2; // [7:6] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_BBPLL1_REGD_T; // bbpll2_reg1 typedef union { uint32_t v; struct { uint32_t plls2_ldo_fast_charge_en_bb : 1; // [0] uint32_t plls2_ldo_en_bb : 1; // [1] uint32_t plls2_notch_en_bb : 1; // [2] uint32_t __3_3 : 1; // [3] uint32_t plls2_cpr_ibit_bb : 3; // [6:4] uint32_t plls2_cpc_ibit_bb : 3; // [9:7] uint32_t plls2_cpbias_bit_bb : 3; // [12:10] uint32_t plls2_ldo_out_bb : 3; // [15:13] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG1_T; // bbpll2_reg2 typedef union { uint32_t v; struct { uint32_t pu_pll_reg_tx : 1; // [0] uint32_t pu_pll_dr_tx : 1; // [1] uint32_t pll_sdm_clk_sel_nor_tx : 1; // [2] uint32_t pll_sdm_clk_sel_rst_tx : 1; // [3] uint32_t pll_sdm_clk_test_en_tx : 1; // [4] uint32_t pll_test_en_tx : 1; // [5] uint32_t pll_low_test_tx : 1; // [6] uint32_t pll_high_test_tx : 1; // [7] uint32_t pll_refmulti2_en_tx : 1; // [8] uint32_t pll_pcon_mode_tx : 1; // [9] uint32_t pll_lpmode_en_tx : 1; // [10] uint32_t pll_dly_num_pfd_tx : 3; // [13:11] uint32_t pll_ldo_fastcharge_cnt_tx : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG2_T; // bbpll2_reg5 typedef union { uint32_t v; struct { uint32_t pll_sdm_freq_tx1 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG5_T; // bbpll2_reg6 typedef union { uint32_t v; struct { uint32_t pll_sdm_freq_tx0 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG6_T; // bbpll2_reg7 typedef union { uint32_t v; struct { uint32_t pll_sdm_resetn_reg_tx : 1; // [0] uint32_t pll_sdm_resetn_dr_tx : 1; // [1] uint32_t ss_squre_tri_sel_tx : 1; // [2] uint32_t ss_en_tx : 1; // [3] uint32_t dither_bypass_tx : 1; // [4] uint32_t int_dec_sel_tx : 3; // [7:5] uint32_t reser_sdm_tx : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG7_T; // bbpll2_reg8 typedef union { uint32_t v; struct { uint32_t pll_ss_peri_ct_tx : 8; // [7:0] uint32_t pll_ss_devi_ct_tx : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REG8_T; // bbpll2_rega typedef union { uint32_t v; struct { uint32_t clk_gen_en_reg_tx : 1; // [0] uint32_t pll_clkout_en_reg_tx : 4; // [4:1] uint32_t pll_clk_adc_dfe_en_reg_tx : 1; // [5] uint32_t pll_clk_adc_en_reg_tx : 1; // [6] uint32_t pll_clk_adc_sel_reg_tx : 2; // [8:7] uint32_t __10_9 : 2; // [10:9] uint32_t sdmclk_sel_time_sel_tx : 2; // [12:11] uint32_t sdm_reset_time_sel_tx : 2; // [14:13] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_INTF_BBPLL2_REGA_T; // bbpll2_regb typedef union { uint32_t v; struct { uint32_t __9_0 : 10; // [9:0] uint32_t pll_lock_steady_tx : 1; // [10], read only uint32_t pll_clk_ready_tx : 1; // [11], read only uint32_t pll_sdm_clk_sel_tx : 1; // [12], read only uint32_t pll_sdm_resetn_tx : 1; // [13], read only uint32_t pll_lock_tx : 1; // [14], read only uint32_t pu_pll_tx : 1; // [15], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_BBPLL2_REGB_T; // bbpll2_regd typedef union { uint32_t v; struct { uint32_t lock_counter_sel_tx : 2; // [1:0] uint32_t pll_clkout_en_counter_sel_tx : 2; // [3:2] uint32_t vco_reset_dis_tx : 1; // [4] uint32_t resetn_spll_tx : 1; // [5] uint32_t plls2_ldo_cp_tune_bb : 2; // [7:6] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_BBPLL2_REGD_T; // clk_gen_reg0 typedef union { uint32_t v; struct { uint32_t rg_freq_clk_div_0 : 3; // [2:0] uint32_t rg_freq_clk_div_1 : 3; // [5:3] uint32_t rg_freq_clk_div_2 : 3; // [8:6] uint32_t rg_freq_clk_div_3 : 3; // [11:9] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_INTF_CLK_GEN_REG0_T; // clk_gen_reg1 typedef union { uint32_t v; struct { uint32_t rg_enable_clk_div : 4; // [3:0] uint32_t rg_inv_clk_div : 4; // [7:4] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_CLK_GEN_REG1_T; // txpll_freq_l typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_FREQ_L_T; // txpll_freq_m typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_m : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_FREQ_M_T; // txpll_freq_h typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_h : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_RF_INTF_TXPLL_FREQ_H_T; // txpll_sdm_ctrl typedef union { uint32_t v; struct { uint32_t rg_txpll_int_dec_sel_reg : 3; // [2:0] uint32_t rg_txpll_fbc_inv_reg : 1; // [3] uint32_t rg_txpll_dither_bypass_reg : 1; // [4] uint32_t rg_txpll_freq_offset_enable : 1; // [5] uint32_t rg_txpll_sdm_soft_rst_n : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_RF_INTF_TXPLL_SDM_CTRL_T; // txpll_freq_offset_l typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_offset_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_FREQ_OFFSET_L_T; // txpll_freq_offset_h typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_offset_h : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_TXPLL_FREQ_OFFSET_H_T; // txpll_freq_offset_ini_l typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_offset_ini_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_FREQ_OFFSET_INI_L_T; // txpll_freq_offset_ini_h typedef union { uint32_t v; struct { uint32_t rg_txpll_freq_offset_ini_h : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_TXPLL_FREQ_OFFSET_INI_H_T; // txpll_sx_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_txpll_rf_sx_aac_cal_init_delay : 3; // [2:0] uint32_t rg_txpll_rf_sx_aac_adder_step_sel : 2; // [4:3] uint32_t rg_txpll_rf_sx_aac_pkd_delay : 2; // [6:5] uint32_t rg_txpll_rf_sx_aac_bypass : 1; // [7] uint32_t rg_txpll_rf_sx_cal_resetn : 1; // [8] uint32_t rg_txpll_rf_sx_afc_bypass : 1; // [9] uint32_t rg_txpll_afc_count_time : 2; // [11:10] uint32_t rg_txpll_afc_bit_num : 2; // [13:12] uint32_t rg_txpll_afc_delay_vco : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_SX_CTRL1_T; // txpll_sx_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_txpll_rf_sx_afc_startl2h : 1; // [0] uint32_t rg_txpll_afc_delay_charging : 3; // [3:1] uint32_t rg_txpll_afc_sdm_en : 1; // [4] uint32_t rg_txpll_rf_sx_agc_cnt_time : 2; // [6:5] uint32_t rg_txpll_rf_sx_agc_en : 1; // [7] uint32_t rg_txpll_rf_sx_agc_resetn : 1; // [8] uint32_t __31_9 : 23; // [31:9] } b; } REG_RF_INTF_TXPLL_SX_CTRL2_T; // txpll_sx_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_txpll_sx_lock_dly : 12; // [11:0] uint32_t rg_txpll_sx_caldone_lock_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_TXPLL_SX_CTRL3_T; // txpll_sx_ctrl4 typedef union { uint32_t v; struct { uint32_t rg_txpll_afc_cal_freq_in_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_SX_CTRL4_T; // txpll_sx_ctrl5 typedef union { uint32_t v; struct { uint32_t rg_txpll_afc_cal_freq_in_h : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_RF_INTF_TXPLL_SX_CTRL5_T; // txpll_sx_ctrl6 typedef union { uint32_t v; struct { uint32_t rg_txpll_afc_vco_cap : 11; // [10:0] uint32_t rg_txpll_afc_sel_reg : 1; // [11] uint32_t rg_txpll_afc_sel_dpll : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_TXPLL_SX_CTRL6_T; // txpll_sx_ctrl7 typedef union { uint32_t v; struct { uint32_t rg_txpll_rf_pu_vco_pkd : 1; // [0] uint32_t rg_txpll_rf_pu_vco_pkd_sel_reg : 1; // [1] uint32_t rg_txpll_rf_pll_cal_en : 1; // [2] uint32_t rg_txpll_rf_pll_cal_en_sel_reg : 1; // [3] uint32_t rg_txpll_rf_pll_cnt_en : 1; // [4] uint32_t rg_txpll_rf_pll_cnt_en_sel_reg : 1; // [5] uint32_t rg_txpll_rf_pll_open_en : 1; // [6] uint32_t rg_txpll_rf_pll_open_en_sel_reg : 1; // [7] uint32_t rg_txpll_vco_bias : 4; // [11:8] uint32_t rg_txpll_vco_bias_sel_reg : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_TXPLL_SX_CTRL7_T; // txpll_sx_stat1 typedef union { uint32_t v; struct { uint32_t txpll_cal_done_top : 1; // [0], read only uint32_t txpll_cal_done_aac : 1; // [1], read only uint32_t txpll_cal_done_afc : 1; // [2], read only uint32_t txpll_cal_done_agc : 1; // [3], read only uint32_t txpll_rf_sx_cal_state : 3; // [6:4], read only uint32_t txpll_rf_sx_aac_state : 2; // [8:7], read only uint32_t txpll_aac_start_ack : 1; // [9], read only uint32_t txpll_afc_start_ack : 1; // [10], read only uint32_t __31_11 : 21; // [31:11] } b; } REG_RF_INTF_TXPLL_SX_STAT1_T; // txpll_sx_stat2 typedef union { uint32_t v; struct { uint32_t txpll_afc_err_min : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_SX_STAT2_T; // txpll_sx_stat3 typedef union { uint32_t v; struct { uint32_t da_afc_vco_cap_tx : 11; // [10:0], read only uint32_t __31_11 : 21; // [31:11] } b; } REG_RF_INTF_TXPLL_SX_STAT3_T; // txpll_sx_stat4 typedef union { uint32_t v; struct { uint32_t da_rf_vco_bias_tx : 4; // [3:0], read only uint32_t da_rf_pu_vco_pkd_tx : 1; // [4], read only uint32_t da_rf_pll_cal_en_tx : 1; // [5], read only uint32_t da_rf_pll_cnt_en_tx : 1; // [6], read only uint32_t da_rf_pll_open_en_tx : 1; // [7], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_TXPLL_SX_STAT4_T; // txpll_sx_stat5 typedef union { uint32_t v; struct { uint32_t ad_rf_pll_cnt_tx : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_TXPLL_SX_STAT5_T; // txpll_sx_stat6 typedef union { uint32_t v; struct { uint32_t ad_rf_vco_pkd_out_tx : 1; // [0], read only uint32_t __31_1 : 31; // [31:1] } b; } REG_RF_INTF_TXPLL_SX_STAT6_T; // rxpll_freq_l typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_FREQ_L_T; // rxpll_freq_m typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_m : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_FREQ_M_T; // rxpll_freq_h typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_h : 3; // [2:0] uint32_t __31_3 : 29; // [31:3] } b; } REG_RF_INTF_RXPLL_FREQ_H_T; // rxpll_sdm_ctrl typedef union { uint32_t v; struct { uint32_t rg_rxpll_int_dec_sel_reg : 3; // [2:0] uint32_t rg_rxpll_fbc_inv_reg : 1; // [3] uint32_t rg_rxpll_dither_bypass_reg : 1; // [4] uint32_t rg_rxpll_freq_offset_enable : 1; // [5] uint32_t rg_rxpll_sdm_soft_rst_n : 1; // [6] uint32_t __31_7 : 25; // [31:7] } b; } REG_RF_INTF_RXPLL_SDM_CTRL_T; // rxpll_freq_offset_l typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_offset_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_FREQ_OFFSET_L_T; // rxpll_freq_offset_h typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_offset_h : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_RXPLL_FREQ_OFFSET_H_T; // rxpll_freq_offset_ini_l typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_offset_ini_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_FREQ_OFFSET_INI_L_T; // rxpll_freq_offset_ini_h typedef union { uint32_t v; struct { uint32_t rg_rxpll_freq_offset_ini_h : 8; // [7:0] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_RXPLL_FREQ_OFFSET_INI_H_T; // rxpll_sx_ctrl1 typedef union { uint32_t v; struct { uint32_t rg_rxpll_rf_sx_aac_cal_init_delay : 3; // [2:0] uint32_t rg_rxpll_rf_sx_aac_adder_step_sel : 2; // [4:3] uint32_t rg_rxpll_rf_sx_aac_pkd_delay : 2; // [6:5] uint32_t rg_rxpll_rf_sx_aac_bypass : 1; // [7] uint32_t rg_rxpll_rf_sx_cal_resetn : 1; // [8] uint32_t rg_rxpll_rf_sx_afc_bypass : 1; // [9] uint32_t rg_rxpll_afc_count_time : 2; // [11:10] uint32_t rg_rxpll_afc_bit_num : 2; // [13:12] uint32_t rg_rxpll_afc_delay_vco : 2; // [15:14] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_SX_CTRL1_T; // rxpll_sx_ctrl2 typedef union { uint32_t v; struct { uint32_t rg_rxpll_rf_sx_afc_startl2h : 1; // [0] uint32_t rg_rxpll_afc_delay_charging : 3; // [3:1] uint32_t rg_rxpll_afc_sdm_en : 1; // [4] uint32_t rg_rxpll_rf_sx_agc_cnt_time : 2; // [6:5] uint32_t rg_rxpll_rf_sx_agc_en : 1; // [7] uint32_t rg_rxpll_rf_sx_agc_resetn : 1; // [8] uint32_t __31_9 : 23; // [31:9] } b; } REG_RF_INTF_RXPLL_SX_CTRL2_T; // rxpll_sx_ctrl3 typedef union { uint32_t v; struct { uint32_t rg_rxpll_sx_lock_dly : 12; // [11:0] uint32_t rg_rxpll_sx_caldone_lock_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_RXPLL_SX_CTRL3_T; // rxpll_sx_ctrl4 typedef union { uint32_t v; struct { uint32_t rg_rxpll_afc_cal_freq_in_l : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_SX_CTRL4_T; // rxpll_sx_ctrl5 typedef union { uint32_t v; struct { uint32_t rg_rxpll_afc_cal_freq_in_h : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_RF_INTF_RXPLL_SX_CTRL5_T; // rxpll_sx_ctrl6 typedef union { uint32_t v; struct { uint32_t rg_rxpll_afc_vco_cap : 11; // [10:0] uint32_t rg_rxpll_afc_sel_reg : 1; // [11] uint32_t rg_rxpll_afc_sel_dpll : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_RXPLL_SX_CTRL6_T; // rxpll_sx_ctrl7 typedef union { uint32_t v; struct { uint32_t rg_rxpll_rf_pu_vco_pkd : 1; // [0] uint32_t rg_rxpll_rf_pu_vco_pkd_sel_reg : 1; // [1] uint32_t rg_rxpll_rf_pll_cal_en : 1; // [2] uint32_t rg_rxpll_rf_pll_cal_en_sel_reg : 1; // [3] uint32_t rg_rxpll_rf_pll_cnt_en : 1; // [4] uint32_t rg_rxpll_rf_pll_cnt_en_sel_reg : 1; // [5] uint32_t rg_rxpll_rf_pll_open_en : 1; // [6] uint32_t rg_rxpll_rf_pll_open_en_sel_reg : 1; // [7] uint32_t rg_rxpll_vco_bias : 4; // [11:8] uint32_t rg_rxpll_vco_bias_sel_reg : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_INTF_RXPLL_SX_CTRL7_T; // rxpll_sx_stat3 typedef union { uint32_t v; struct { uint32_t da_afc_vco_cap_rx : 11; // [10:0], read only uint32_t __31_11 : 21; // [31:11] } b; } REG_RF_INTF_RXPLL_SX_STAT3_T; // rxpll_sx_stat4 typedef union { uint32_t v; struct { uint32_t da_rf_vco_bias_rx : 4; // [3:0], read only uint32_t da_rf_pu_vco_pkd_rx : 1; // [4], read only uint32_t da_rf_pll_cal_en_rx : 1; // [5], read only uint32_t da_rf_pll_cnt_en_rx : 1; // [6], read only uint32_t da_rf_pll_open_en_rx : 1; // [7], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_INTF_RXPLL_SX_STAT4_T; // rxpll_sx_stat5 typedef union { uint32_t v; struct { uint32_t ad_rf_pll_cnt_rx : 16; // [15:0], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_RXPLL_SX_STAT5_T; // rxpll_sx_stat6 typedef union { uint32_t v; struct { uint32_t ad_rf_vco_pkd_out_rx : 1; // [0], read only uint32_t __31_1 : 31; // [31:1] } b; } REG_RF_INTF_RXPLL_SX_STAT6_T; // peak_det_clr typedef union { uint32_t v; struct { uint32_t rg_peak_det_en : 4; // [3:0] uint32_t rg_peak_det_clr : 4; // [7:4] uint32_t rg_peak_det_auto_ctrl_en : 4; // [11:8] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_INTF_PEAK_DET_CLR_T; // peak_det_sta typedef union { uint32_t v; struct { uint32_t ad_peak_det_flag : 4; // [3:0], read only uint32_t peak_det_flag_sync : 4; // [7:4], read only uint32_t peak_det_int : 4; // [11:8], read only uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_INTF_PEAK_DET_STA_T; // peak_det_num1 typedef union { uint32_t v; struct { uint32_t rg_peak_det_num0 : 8; // [7:0] uint32_t rg_peak_det_num1 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_PEAK_DET_NUM1_T; // peak_det_num2 typedef union { uint32_t v; struct { uint32_t rg_peak_det_num2 : 8; // [7:0] uint32_t rg_peak_det_num3 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_PEAK_DET_NUM2_T; // peak_det_trig_num1 typedef union { uint32_t v; struct { uint32_t rg_peak_det_trig_num0 : 8; // [7:0] uint32_t rg_peak_det_trig_num1 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_PEAK_DET_TRIG_NUM1_T; // peak_det_trig_num2 typedef union { uint32_t v; struct { uint32_t rg_peak_det_trig_num2 : 8; // [7:0] uint32_t rg_peak_det_trig_num3 : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_INTF_PEAK_DET_TRIG_NUM2_T; // apb_reg_int0 #define RF_INTF_RG_APB_REG_INT0(n) (((n)&0xffff) << 0) // apb_reg_int1 #define RF_INTF_RG_APB_REG_INT1(n) (((n)&0xffff) << 0) // apb_reg_int2 #define RF_INTF_RG_APB_REG_INT2(n) (((n)&0xffff) << 0) // apb_reg_int3 #define RF_INTF_RG_APB_REG_INT3(n) (((n)&0xffff) << 0) // apb_reg_int4 #define RF_INTF_RG_APB_REG_INT4(n) (((n)&0xffff) << 0) // apb_reg_int5 #define RF_INTF_RG_APB_REG_INT5(n) (((n)&0xffff) << 0) // apb_reg_int6 #define RF_INTF_RG_APB_REG_INT6(n) (((n)&0xffff) << 0) // apb_reg_int7 #define RF_INTF_RG_APB_REG_INT7(n) (((n)&0xffff) << 0) // apb_reg_int8 #define RF_INTF_RG_APB_REG_INT8(n) (((n)&0xffff) << 0) // apb_reg_int9 #define RF_INTF_RG_APB_REG_INT9(n) (((n)&0xffff) << 0) // apb_reg_int_res10 #define RF_INTF_RG_APB_REG_INT_RES10(n) (((n)&0xffff) << 0) // apb_reg_int_res11 #define RF_INTF_RG_APB_REG_INT_RES11(n) (((n)&0xffff) << 0) // apb_reg_int_res12 #define RF_INTF_RG_APB_REG_INT_RES12(n) (((n)&0xffff) << 0) // apb_reg_int_res13 #define RF_INTF_RG_APB_REG_INT_RES13(n) (((n)&0xffff) << 0) // apb_reg_int_res14 #define RF_INTF_RG_APB_REG_INT_RES14(n) (((n)&0xffff) << 0) // apb_reg_int_res15 #define RF_INTF_RG_APB_REG_INT_RES15(n) (((n)&0xffff) << 0) // int_clear0 #define RF_INTF_RG_IRQ_CLR_L(n) (((n)&0xffff) << 0) // int_clear1 #define RF_INTF_RG_IRQ_CLR_H(n) (((n)&0xffff) << 0) // int2tmcu0 #define RF_INTF_IRQ_OUT_L(n) (((n)&0xffff) << 0) // int2tmcu1 #define RF_INTF_IRQ_OUT_H(n) (((n)&0xffff) << 0) // irq_enable0 #define RF_INTF_RG_IRQ_EN_L(n) (((n)&0xffff) << 0) // irq_enable1 #define RF_INTF_RG_IRQ_EN_H(n) (((n)&0xffff) << 0) // irq_raw0 #define RF_INTF_IRQ_RAW_L(n) (((n)&0xffff) << 0) // irq_raw1 #define RF_INTF_IRQ_RAW_H(n) (((n)&0xffff) << 0) // irq_select #define RF_INTF_RG_IRQ_SEL(n) (((n)&0xffff) << 0) // afc_freq_bbpll1 #define RF_INTF_FREQ_OFFSET_BBPLL11(n) (((n)&0xffff) << 0) // afc_freq_bbpll12 #define RF_INTF_FREQ_OFFSET_BBPLL22(n) (((n)&0xff) << 0) #define RF_INTF_FREQ_OFFSET_BBPLL12(n) (((n)&0xff) << 8) // afc_freq_bbpll2 #define RF_INTF_FREQ_OFFSET_BBPLL21(n) (((n)&0xffff) << 0) // afc_freq_offset_mode #define RF_INTF_FREQ_OFFSET_MODE_BBPLL1 (1 << 0) #define RF_INTF_FREQ_OFFSET_MODE_BBPLL2 (1 << 1) #define RF_INTF_FREQ_OFFSET_ENABLE_BBPLL1 (1 << 2) #define RF_INTF_FREQ_OFFSET_ENABLE_BBPLL2 (1 << 3) // freq_offset_ini_bbpll1_reg1 #define RF_INTF_FREQ_OFFSET_INI_BBPLL11(n) (((n)&0xffff) << 0) // freq_offset_ini_bbpll1_reg2 #define RF_INTF_FREQ_OFFSET_INI_BBPLL12(n) (((n)&0xff) << 0) #define RF_INTF_FREQ_OFFSET_INI_BBPLL22(n) (((n)&0xff) << 8) // freq_offset_ini_bbpll2_reg1 #define RF_INTF_FREQ_OFFSET_INI_BBPLL21(n) (((n)&0xffff) << 0) // bbpll1_reg1 #define RF_INTF_PLLS1_LDO_FAST_CHARGE_EN_BB (1 << 0) #define RF_INTF_PLLS1_LDO_EN_BB (1 << 1) #define RF_INTF_PLLS1_NOTCH_EN_BB (1 << 2) #define RF_INTF_PLLS1_CPR_IBIT_BB(n) (((n)&0x7) << 4) #define RF_INTF_PLLS1_CPC_IBIT_BB(n) (((n)&0x7) << 7) #define RF_INTF_PLLS1_CPBIAS_BIT_BB(n) (((n)&0x7) << 10) #define RF_INTF_PLLS1_LDO_OUT_BB(n) (((n)&0x7) << 13) // bbpll1_reg2 #define RF_INTF_PU_PLL_REG_RX (1 << 0) #define RF_INTF_PU_PLL_DR_RX (1 << 1) #define RF_INTF_PLL_SDM_CLK_SEL_NOR_RX (1 << 2) #define RF_INTF_PLL_SDM_CLK_SEL_RST_RX (1 << 3) #define RF_INTF_PLL_SDM_CLK_TEST_EN_RX (1 << 4) #define RF_INTF_PLL_TEST_EN_RX (1 << 5) #define RF_INTF_PLL_LOW_TEST_RX (1 << 6) #define RF_INTF_PLL_HIGH_TEST_RX (1 << 7) #define RF_INTF_PLL_REFMULTI2_EN_RX (1 << 8) #define RF_INTF_PLL_PCON_MODE_RX (1 << 9) #define RF_INTF_PLL_LPMODE_EN_RX (1 << 10) #define RF_INTF_PLL_DLY_NUM_PFD_RX(n) (((n)&0x7) << 11) #define RF_INTF_PLL_LDO_FASTCHARGE_CNT_RX(n) (((n)&0x3) << 14) // bbpll1_reg5 #define RF_INTF_PLL_SDM_FREQ_RX1(n) (((n)&0xffff) << 0) // bbpll1_reg6 #define RF_INTF_PLL_SDM_FREQ_RX0(n) (((n)&0xffff) << 0) // bbpll1_reg7 #define RF_INTF_PLL_SDM_RESETN_REG_RX (1 << 0) #define RF_INTF_PLL_SDM_RESETN_DR_RX (1 << 1) #define RF_INTF_SS_SQURE_TRI_SEL_RX (1 << 2) #define RF_INTF_SS_EN_RX (1 << 3) #define RF_INTF_DITHER_BYPASS_RX (1 << 4) #define RF_INTF_INT_DEC_SEL_RX(n) (((n)&0x7) << 5) #define RF_INTF_RESER_SDM_RX(n) (((n)&0xff) << 8) // bbpll1_reg8 #define RF_INTF_PLL_SS_PERI_CT_RX(n) (((n)&0xff) << 0) #define RF_INTF_PLL_SS_DEVI_CT_RX(n) (((n)&0xff) << 8) // bbpll1_rega #define RF_INTF_CLK_GEN_EN_REG_RX (1 << 0) #define RF_INTF_PLL_CLKOUT_EN_REG_RX(n) (((n)&0xf) << 1) #define RF_INTF_PLL_CLK_ADC_DFE_EN_REG_RX (1 << 5) #define RF_INTF_PLL_CLK_ADC_EN_REG_RX (1 << 6) #define RF_INTF_PLL_CLK_ADC_SEL_REG_RX(n) (((n)&0x3) << 7) #define RF_INTF_PLL_CLK_DFE_SEL_REG_RX(n) (((n)&0x3) << 9) #define RF_INTF_SDMCLK_SEL_TIME_SEL_RX(n) (((n)&0x3) << 11) #define RF_INTF_SDM_RESET_TIME_SEL_RX(n) (((n)&0x3) << 13) // bbpll1_regb #define RF_INTF_PLL_LOCK_STEADY_RX (1 << 10) #define RF_INTF_RXPLL_SX_CAL_STATE(n) (((n)&0x7) << 11) #define RF_INTF_PLL_LOCK_RX (1 << 14) #define RF_INTF_PU_PLL_RX (1 << 15) // bbpll1_regd #define RF_INTF_LOCK_COUNTER_SEL_RX(n) (((n)&0x3) << 0) #define RF_INTF_PLL_CLKOUT_EN_COUNTER_SEL_RX(n) (((n)&0x3) << 2) #define RF_INTF_VCO_RESET_DIS_RX (1 << 4) #define RF_INTF_RESETN_SPLL_RX (1 << 5) #define RF_INTF_PLLS1_LDO_CP_TUNE_BB(n) (((n)&0x3) << 6) // bbpll2_reg1 #define RF_INTF_PLLS2_LDO_FAST_CHARGE_EN_BB (1 << 0) #define RF_INTF_PLLS2_LDO_EN_BB (1 << 1) #define RF_INTF_PLLS2_NOTCH_EN_BB (1 << 2) #define RF_INTF_PLLS2_CPR_IBIT_BB(n) (((n)&0x7) << 4) #define RF_INTF_PLLS2_CPC_IBIT_BB(n) (((n)&0x7) << 7) #define RF_INTF_PLLS2_CPBIAS_BIT_BB(n) (((n)&0x7) << 10) #define RF_INTF_PLLS2_LDO_OUT_BB(n) (((n)&0x7) << 13) // bbpll2_reg2 #define RF_INTF_PU_PLL_REG_TX (1 << 0) #define RF_INTF_PU_PLL_DR_TX (1 << 1) #define RF_INTF_PLL_SDM_CLK_SEL_NOR_TX (1 << 2) #define RF_INTF_PLL_SDM_CLK_SEL_RST_TX (1 << 3) #define RF_INTF_PLL_SDM_CLK_TEST_EN_TX (1 << 4) #define RF_INTF_PLL_TEST_EN_TX (1 << 5) #define RF_INTF_PLL_LOW_TEST_TX (1 << 6) #define RF_INTF_PLL_HIGH_TEST_TX (1 << 7) #define RF_INTF_PLL_REFMULTI2_EN_TX (1 << 8) #define RF_INTF_PLL_PCON_MODE_TX (1 << 9) #define RF_INTF_PLL_LPMODE_EN_TX (1 << 10) #define RF_INTF_PLL_DLY_NUM_PFD_TX(n) (((n)&0x7) << 11) #define RF_INTF_PLL_LDO_FASTCHARGE_CNT_TX(n) (((n)&0x3) << 14) // bbpll2_reg5 #define RF_INTF_PLL_SDM_FREQ_TX1(n) (((n)&0xffff) << 0) // bbpll2_reg6 #define RF_INTF_PLL_SDM_FREQ_TX0(n) (((n)&0xffff) << 0) // bbpll2_reg7 #define RF_INTF_PLL_SDM_RESETN_REG_TX (1 << 0) #define RF_INTF_PLL_SDM_RESETN_DR_TX (1 << 1) #define RF_INTF_SS_SQURE_TRI_SEL_TX (1 << 2) #define RF_INTF_SS_EN_TX (1 << 3) #define RF_INTF_DITHER_BYPASS_TX (1 << 4) #define RF_INTF_INT_DEC_SEL_TX(n) (((n)&0x7) << 5) #define RF_INTF_RESER_SDM_TX(n) (((n)&0xff) << 8) // bbpll2_reg8 #define RF_INTF_PLL_SS_PERI_CT_TX(n) (((n)&0xff) << 0) #define RF_INTF_PLL_SS_DEVI_CT_TX(n) (((n)&0xff) << 8) // bbpll2_rega #define RF_INTF_CLK_GEN_EN_REG_TX (1 << 0) #define RF_INTF_PLL_CLKOUT_EN_REG_TX(n) (((n)&0xf) << 1) #define RF_INTF_PLL_CLK_ADC_DFE_EN_REG_TX (1 << 5) #define RF_INTF_PLL_CLK_ADC_EN_REG_TX (1 << 6) #define RF_INTF_PLL_CLK_ADC_SEL_REG_TX(n) (((n)&0x3) << 7) #define RF_INTF_SDMCLK_SEL_TIME_SEL_TX(n) (((n)&0x3) << 11) #define RF_INTF_SDM_RESET_TIME_SEL_TX(n) (((n)&0x3) << 13) // bbpll2_regb #define RF_INTF_PLL_LOCK_STEADY_TX (1 << 10) #define RF_INTF_PLL_CLK_READY_TX (1 << 11) #define RF_INTF_PLL_SDM_CLK_SEL_TX (1 << 12) #define RF_INTF_PLL_SDM_RESETN_TX (1 << 13) #define RF_INTF_PLL_LOCK_TX (1 << 14) #define RF_INTF_PU_PLL_TX (1 << 15) // bbpll2_regd #define RF_INTF_LOCK_COUNTER_SEL_TX(n) (((n)&0x3) << 0) #define RF_INTF_PLL_CLKOUT_EN_COUNTER_SEL_TX(n) (((n)&0x3) << 2) #define RF_INTF_VCO_RESET_DIS_TX (1 << 4) #define RF_INTF_RESETN_SPLL_TX (1 << 5) #define RF_INTF_PLLS2_LDO_CP_TUNE_BB(n) (((n)&0x3) << 6) // clk_gen_reg0 #define RF_INTF_RG_FREQ_CLK_DIV_0(n) (((n)&0x7) << 0) #define RF_INTF_RG_FREQ_CLK_DIV_1(n) (((n)&0x7) << 3) #define RF_INTF_RG_FREQ_CLK_DIV_2(n) (((n)&0x7) << 6) #define RF_INTF_RG_FREQ_CLK_DIV_3(n) (((n)&0x7) << 9) // clk_gen_reg1 #define RF_INTF_RG_ENABLE_CLK_DIV(n) (((n)&0xf) << 0) #define RF_INTF_RG_INV_CLK_DIV(n) (((n)&0xf) << 4) // txpll_freq_l #define RF_INTF_RG_TXPLL_FREQ_L(n) (((n)&0xffff) << 0) // txpll_freq_m #define RF_INTF_RG_TXPLL_FREQ_M(n) (((n)&0xffff) << 0) // txpll_freq_h #define RF_INTF_RG_TXPLL_FREQ_H(n) (((n)&0x7) << 0) // txpll_sdm_ctrl #define RF_INTF_RG_TXPLL_INT_DEC_SEL_REG(n) (((n)&0x7) << 0) #define RF_INTF_RG_TXPLL_FBC_INV_REG (1 << 3) #define RF_INTF_RG_TXPLL_DITHER_BYPASS_REG (1 << 4) #define RF_INTF_RG_TXPLL_FREQ_OFFSET_ENABLE (1 << 5) #define RF_INTF_RG_TXPLL_SDM_SOFT_RST_N (1 << 6) // txpll_freq_offset_l #define RF_INTF_RG_TXPLL_FREQ_OFFSET_L(n) (((n)&0xffff) << 0) // txpll_freq_offset_h #define RF_INTF_RG_TXPLL_FREQ_OFFSET_H(n) (((n)&0xff) << 0) // txpll_freq_offset_ini_l #define RF_INTF_RG_TXPLL_FREQ_OFFSET_INI_L(n) (((n)&0xffff) << 0) // txpll_freq_offset_ini_h #define RF_INTF_RG_TXPLL_FREQ_OFFSET_INI_H(n) (((n)&0xff) << 0) // txpll_sx_ctrl1 #define RF_INTF_RG_TXPLL_RF_SX_AAC_CAL_INIT_DELAY(n) (((n)&0x7) << 0) #define RF_INTF_RG_TXPLL_RF_SX_AAC_ADDER_STEP_SEL(n) (((n)&0x3) << 3) #define RF_INTF_RG_TXPLL_RF_SX_AAC_PKD_DELAY(n) (((n)&0x3) << 5) #define RF_INTF_RG_TXPLL_RF_SX_AAC_BYPASS (1 << 7) #define RF_INTF_RG_TXPLL_RF_SX_CAL_RESETN (1 << 8) #define RF_INTF_RG_TXPLL_RF_SX_AFC_BYPASS (1 << 9) #define RF_INTF_RG_TXPLL_AFC_COUNT_TIME(n) (((n)&0x3) << 10) #define RF_INTF_RG_TXPLL_AFC_BIT_NUM(n) (((n)&0x3) << 12) #define RF_INTF_RG_TXPLL_AFC_DELAY_VCO(n) (((n)&0x3) << 14) // txpll_sx_ctrl2 #define RF_INTF_RG_TXPLL_RF_SX_AFC_STARTL2H (1 << 0) #define RF_INTF_RG_TXPLL_AFC_DELAY_CHARGING(n) (((n)&0x7) << 1) #define RF_INTF_RG_TXPLL_AFC_SDM_EN (1 << 4) #define RF_INTF_RG_TXPLL_RF_SX_AGC_CNT_TIME(n) (((n)&0x3) << 5) #define RF_INTF_RG_TXPLL_RF_SX_AGC_EN (1 << 7) #define RF_INTF_RG_TXPLL_RF_SX_AGC_RESETN (1 << 8) // txpll_sx_ctrl3 #define RF_INTF_RG_TXPLL_SX_LOCK_DLY(n) (((n)&0xfff) << 0) #define RF_INTF_RG_TXPLL_SX_CALDONE_LOCK_EN (1 << 12) // txpll_sx_ctrl4 #define RF_INTF_RG_TXPLL_AFC_CAL_FREQ_IN_L(n) (((n)&0xffff) << 0) // txpll_sx_ctrl5 #define RF_INTF_RG_TXPLL_AFC_CAL_FREQ_IN_H (1 << 0) // txpll_sx_ctrl6 #define RF_INTF_RG_TXPLL_AFC_VCO_CAP(n) (((n)&0x7ff) << 0) #define RF_INTF_RG_TXPLL_AFC_SEL_REG (1 << 11) #define RF_INTF_RG_TXPLL_AFC_SEL_DPLL (1 << 12) // txpll_sx_ctrl7 #define RF_INTF_RG_TXPLL_RF_PU_VCO_PKD (1 << 0) #define RF_INTF_RG_TXPLL_RF_PU_VCO_PKD_SEL_REG (1 << 1) #define RF_INTF_RG_TXPLL_RF_PLL_CAL_EN (1 << 2) #define RF_INTF_RG_TXPLL_RF_PLL_CAL_EN_SEL_REG (1 << 3) #define RF_INTF_RG_TXPLL_RF_PLL_CNT_EN (1 << 4) #define RF_INTF_RG_TXPLL_RF_PLL_CNT_EN_SEL_REG (1 << 5) #define RF_INTF_RG_TXPLL_RF_PLL_OPEN_EN (1 << 6) #define RF_INTF_RG_TXPLL_RF_PLL_OPEN_EN_SEL_REG (1 << 7) #define RF_INTF_RG_TXPLL_VCO_BIAS(n) (((n)&0xf) << 8) #define RF_INTF_RG_TXPLL_VCO_BIAS_SEL_REG (1 << 12) // txpll_sx_stat1 #define RF_INTF_TXPLL_CAL_DONE_TOP (1 << 0) #define RF_INTF_TXPLL_CAL_DONE_AAC (1 << 1) #define RF_INTF_TXPLL_CAL_DONE_AFC (1 << 2) #define RF_INTF_TXPLL_CAL_DONE_AGC (1 << 3) #define RF_INTF_TXPLL_RF_SX_CAL_STATE(n) (((n)&0x7) << 4) #define RF_INTF_TXPLL_RF_SX_AAC_STATE(n) (((n)&0x3) << 7) #define RF_INTF_TXPLL_AAC_START_ACK (1 << 9) #define RF_INTF_TXPLL_AFC_START_ACK (1 << 10) // txpll_sx_stat2 #define RF_INTF_TXPLL_AFC_ERR_MIN(n) (((n)&0xffff) << 0) // txpll_sx_stat3 #define RF_INTF_DA_AFC_VCO_CAP_TX(n) (((n)&0x7ff) << 0) // txpll_sx_stat4 #define RF_INTF_DA_RF_VCO_BIAS_TX(n) (((n)&0xf) << 0) #define RF_INTF_DA_RF_PU_VCO_PKD_TX (1 << 4) #define RF_INTF_DA_RF_PLL_CAL_EN_TX (1 << 5) #define RF_INTF_DA_RF_PLL_CNT_EN_TX (1 << 6) #define RF_INTF_DA_RF_PLL_OPEN_EN_TX (1 << 7) // txpll_sx_stat5 #define RF_INTF_AD_RF_PLL_CNT_TX(n) (((n)&0xffff) << 0) // txpll_sx_stat6 #define RF_INTF_AD_RF_VCO_PKD_OUT_TX (1 << 0) // rxpll_freq_l #define RF_INTF_RG_RXPLL_FREQ_L(n) (((n)&0xffff) << 0) // rxpll_freq_m #define RF_INTF_RG_RXPLL_FREQ_M(n) (((n)&0xffff) << 0) // rxpll_freq_h #define RF_INTF_RG_RXPLL_FREQ_H(n) (((n)&0x7) << 0) // rxpll_sdm_ctrl #define RF_INTF_RG_RXPLL_INT_DEC_SEL_REG(n) (((n)&0x7) << 0) #define RF_INTF_RG_RXPLL_FBC_INV_REG (1 << 3) #define RF_INTF_RG_RXPLL_DITHER_BYPASS_REG (1 << 4) #define RF_INTF_RG_RXPLL_FREQ_OFFSET_ENABLE (1 << 5) #define RF_INTF_RG_RXPLL_SDM_SOFT_RST_N (1 << 6) // rxpll_freq_offset_l #define RF_INTF_RG_RXPLL_FREQ_OFFSET_L(n) (((n)&0xffff) << 0) // rxpll_freq_offset_h #define RF_INTF_RG_RXPLL_FREQ_OFFSET_H(n) (((n)&0xff) << 0) // rxpll_freq_offset_ini_l #define RF_INTF_RG_RXPLL_FREQ_OFFSET_INI_L(n) (((n)&0xffff) << 0) // rxpll_freq_offset_ini_h #define RF_INTF_RG_RXPLL_FREQ_OFFSET_INI_H(n) (((n)&0xff) << 0) // rxpll_sx_ctrl1 #define RF_INTF_RG_RXPLL_RF_SX_AAC_CAL_INIT_DELAY(n) (((n)&0x7) << 0) #define RF_INTF_RG_RXPLL_RF_SX_AAC_ADDER_STEP_SEL(n) (((n)&0x3) << 3) #define RF_INTF_RG_RXPLL_RF_SX_AAC_PKD_DELAY(n) (((n)&0x3) << 5) #define RF_INTF_RG_RXPLL_RF_SX_AAC_BYPASS (1 << 7) #define RF_INTF_RG_RXPLL_RF_SX_CAL_RESETN (1 << 8) #define RF_INTF_RG_RXPLL_RF_SX_AFC_BYPASS (1 << 9) #define RF_INTF_RG_RXPLL_AFC_COUNT_TIME(n) (((n)&0x3) << 10) #define RF_INTF_RG_RXPLL_AFC_BIT_NUM(n) (((n)&0x3) << 12) #define RF_INTF_RG_RXPLL_AFC_DELAY_VCO(n) (((n)&0x3) << 14) // rxpll_sx_ctrl2 #define RF_INTF_RG_RXPLL_RF_SX_AFC_STARTL2H (1 << 0) #define RF_INTF_RG_RXPLL_AFC_DELAY_CHARGING(n) (((n)&0x7) << 1) #define RF_INTF_RG_RXPLL_AFC_SDM_EN (1 << 4) #define RF_INTF_RG_RXPLL_RF_SX_AGC_CNT_TIME(n) (((n)&0x3) << 5) #define RF_INTF_RG_RXPLL_RF_SX_AGC_EN (1 << 7) #define RF_INTF_RG_RXPLL_RF_SX_AGC_RESETN (1 << 8) // rxpll_sx_ctrl3 #define RF_INTF_RG_RXPLL_SX_LOCK_DLY(n) (((n)&0xfff) << 0) #define RF_INTF_RG_RXPLL_SX_CALDONE_LOCK_EN (1 << 12) // rxpll_sx_ctrl4 #define RF_INTF_RG_RXPLL_AFC_CAL_FREQ_IN_L(n) (((n)&0xffff) << 0) // rxpll_sx_ctrl5 #define RF_INTF_RG_RXPLL_AFC_CAL_FREQ_IN_H (1 << 0) // rxpll_sx_ctrl6 #define RF_INTF_RG_RXPLL_AFC_VCO_CAP(n) (((n)&0x7ff) << 0) #define RF_INTF_RG_RXPLL_AFC_SEL_REG (1 << 11) #define RF_INTF_RG_RXPLL_AFC_SEL_DPLL (1 << 12) // rxpll_sx_ctrl7 #define RF_INTF_RG_RXPLL_RF_PU_VCO_PKD (1 << 0) #define RF_INTF_RG_RXPLL_RF_PU_VCO_PKD_SEL_REG (1 << 1) #define RF_INTF_RG_RXPLL_RF_PLL_CAL_EN (1 << 2) #define RF_INTF_RG_RXPLL_RF_PLL_CAL_EN_SEL_REG (1 << 3) #define RF_INTF_RG_RXPLL_RF_PLL_CNT_EN (1 << 4) #define RF_INTF_RG_RXPLL_RF_PLL_CNT_EN_SEL_REG (1 << 5) #define RF_INTF_RG_RXPLL_RF_PLL_OPEN_EN (1 << 6) #define RF_INTF_RG_RXPLL_RF_PLL_OPEN_EN_SEL_REG (1 << 7) #define RF_INTF_RG_RXPLL_VCO_BIAS(n) (((n)&0xf) << 8) #define RF_INTF_RG_RXPLL_VCO_BIAS_SEL_REG (1 << 12) // rxpll_sx_stat3 #define RF_INTF_DA_AFC_VCO_CAP_RX(n) (((n)&0x7ff) << 0) // rxpll_sx_stat4 #define RF_INTF_DA_RF_VCO_BIAS_RX(n) (((n)&0xf) << 0) #define RF_INTF_DA_RF_PU_VCO_PKD_RX (1 << 4) #define RF_INTF_DA_RF_PLL_CAL_EN_RX (1 << 5) #define RF_INTF_DA_RF_PLL_CNT_EN_RX (1 << 6) #define RF_INTF_DA_RF_PLL_OPEN_EN_RX (1 << 7) // rxpll_sx_stat5 #define RF_INTF_AD_RF_PLL_CNT_RX(n) (((n)&0xffff) << 0) // rxpll_sx_stat6 #define RF_INTF_AD_RF_VCO_PKD_OUT_RX (1 << 0) // peak_det_clr #define RF_INTF_RG_PEAK_DET_EN(n) (((n)&0xf) << 0) #define RF_INTF_RG_PEAK_DET_CLR(n) (((n)&0xf) << 4) #define RF_INTF_RG_PEAK_DET_AUTO_CTRL_EN(n) (((n)&0xf) << 8) // peak_det_sta #define RF_INTF_AD_PEAK_DET_FLAG(n) (((n)&0xf) << 0) #define RF_INTF_PEAK_DET_FLAG_SYNC(n) (((n)&0xf) << 4) #define RF_INTF_PEAK_DET_INT(n) (((n)&0xf) << 8) // peak_det_num1 #define RF_INTF_RG_PEAK_DET_NUM0(n) (((n)&0xff) << 0) #define RF_INTF_RG_PEAK_DET_NUM1(n) (((n)&0xff) << 8) // peak_det_num2 #define RF_INTF_RG_PEAK_DET_NUM2(n) (((n)&0xff) << 0) #define RF_INTF_RG_PEAK_DET_NUM3(n) (((n)&0xff) << 8) // peak_det_trig_num1 #define RF_INTF_RG_PEAK_DET_TRIG_NUM0(n) (((n)&0xff) << 0) #define RF_INTF_RG_PEAK_DET_TRIG_NUM1(n) (((n)&0xff) << 8) // peak_det_trig_num2 #define RF_INTF_RG_PEAK_DET_TRIG_NUM2(n) (((n)&0xff) << 0) #define RF_INTF_RG_PEAK_DET_TRIG_NUM3(n) (((n)&0xff) << 8) #endif // _RF_INTF_H_