/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _RF_SYSCTRL_H_ #define _RF_SYSCTRL_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_RF_SYSCTRL_SET_OFFSET (1024) #define REG_RF_SYSCTRL_CLR_OFFSET (2048) #define REG_RF_SYSCTRL_BASE (0x50035000) typedef volatile struct { uint32_t sysctrl1; // 0x00000000 uint32_t sysctrl2; // 0x00000004 uint32_t sysctrl3; // 0x00000008 uint32_t sysctrl4; // 0x0000000c uint32_t sysctrl5; // 0x00000010 uint32_t sysctrl6; // 0x00000014 uint32_t sysctrl7; // 0x00000018 uint32_t sysctrl8; // 0x0000001c uint32_t sysctrl9; // 0x00000020 uint32_t sysctrl10; // 0x00000024 uint32_t sysctrl11; // 0x00000028 uint32_t sysctrl12; // 0x0000002c uint32_t sysctrl13; // 0x00000030 uint32_t sysctrl14; // 0x00000034 uint32_t sysctrl15; // 0x00000038 uint32_t sysctrl16; // 0x0000003c uint32_t sysctrl17; // 0x00000040 uint32_t sysctrl18; // 0x00000044 uint32_t sysctrl19; // 0x00000048 uint32_t sysctrl20; // 0x0000004c uint32_t sysctrl21; // 0x00000050 uint32_t sysctrl22; // 0x00000054 uint32_t sysctrl23; // 0x00000058 uint32_t sysctrl24; // 0x0000005c uint32_t sysctrl25; // 0x00000060 uint32_t sysstat1; // 0x00000064 uint32_t sysstat2; // 0x00000068 uint32_t sysctrl26; // 0x0000006c uint32_t sysctrl27; // 0x00000070 uint32_t sysctrl28; // 0x00000074 uint32_t sysctrl29; // 0x00000078 uint32_t sysctrl30; // 0x0000007c uint32_t sysctrl31; // 0x00000080 uint32_t sysctrl32; // 0x00000084 uint32_t sysctrl33; // 0x00000088 uint32_t sysctrl34; // 0x0000008c uint32_t sysctrl35; // 0x00000090 uint32_t sysctrl36; // 0x00000094 uint32_t sysctrl37; // 0x00000098 uint32_t sysctrl38; // 0x0000009c uint32_t sysctrl39; // 0x000000a0 uint32_t sysctrl40; // 0x000000a4 uint32_t sysctrl41; // 0x000000a8 uint32_t sysstat3; // 0x000000ac uint32_t sysctrl42; // 0x000000b0 uint32_t sysctrl43; // 0x000000b4 uint32_t sysctrl44; // 0x000000b8 uint32_t sysctrl45; // 0x000000bc uint32_t sysstat4; // 0x000000c0 uint32_t sysstat5; // 0x000000c4 uint32_t sysctrl46; // 0x000000c8 uint32_t sysctrl47; // 0x000000cc uint32_t sysctrl48; // 0x000000d0 uint32_t sysctrl49; // 0x000000d4 uint32_t sysctrl50; // 0x000000d8 uint32_t sysctrl51; // 0x000000dc uint32_t sysctrl52; // 0x000000e0 uint32_t sysctrl53; // 0x000000e4 uint32_t sysctrl54; // 0x000000e8 uint32_t sysctrl55; // 0x000000ec uint32_t sysctrl56; // 0x000000f0 uint32_t sysctrl57; // 0x000000f4 uint32_t sysctrl58; // 0x000000f8 uint32_t sysctrl59; // 0x000000fc uint32_t sysctrl60; // 0x00000100 uint32_t sysctrl61; // 0x00000104 uint32_t sysctrl62; // 0x00000108 uint32_t sysctrl63; // 0x0000010c uint32_t sysctrl64; // 0x00000110 uint32_t sysctrl65; // 0x00000114 uint32_t sysctrl66; // 0x00000118 uint32_t sysctrl67; // 0x0000011c uint32_t sysctrl68; // 0x00000120 uint32_t sysctrl69; // 0x00000124 uint32_t sysctrl70; // 0x00000128 uint32_t sysctrl71; // 0x0000012c uint32_t sysctrl72; // 0x00000130 uint32_t sysctrl73; // 0x00000134 uint32_t sysctrl74; // 0x00000138 uint32_t sysctrl75; // 0x0000013c uint32_t sysctrl76; // 0x00000140 uint32_t sysctrl77; // 0x00000144 uint32_t sysctrl78; // 0x00000148 uint32_t sysctrl79; // 0x0000014c uint32_t sysctrl80; // 0x00000150 uint32_t sysctrl81; // 0x00000154 uint32_t sysctrl82; // 0x00000158 uint32_t __348[169]; // 0x0000015c uint32_t sysctrl1_set; // 0x00000400 uint32_t sysctrl2_set; // 0x00000404 uint32_t sysctrl3_set; // 0x00000408 uint32_t sysctrl4_set; // 0x0000040c uint32_t sysctrl5_set; // 0x00000410 uint32_t sysctrl6_set; // 0x00000414 uint32_t sysctrl7_set; // 0x00000418 uint32_t sysctrl8_set; // 0x0000041c uint32_t sysctrl9_set; // 0x00000420 uint32_t sysctrl10_set; // 0x00000424 uint32_t sysctrl11_set; // 0x00000428 uint32_t sysctrl12_set; // 0x0000042c uint32_t sysctrl13_set; // 0x00000430 uint32_t sysctrl14_set; // 0x00000434 uint32_t sysctrl15_set; // 0x00000438 uint32_t sysctrl16_set; // 0x0000043c uint32_t sysctrl17_set; // 0x00000440 uint32_t sysctrl18_set; // 0x00000444 uint32_t sysctrl19_set; // 0x00000448 uint32_t sysctrl20_set; // 0x0000044c uint32_t sysctrl21_set; // 0x00000450 uint32_t sysctrl22_set; // 0x00000454 uint32_t sysctrl23_set; // 0x00000458 uint32_t sysctrl24_set; // 0x0000045c uint32_t sysctrl25_set; // 0x00000460 uint32_t __1124[19]; // 0x00000464 uint32_t sysctrl42_set; // 0x000004b0 uint32_t sysctrl43_set; // 0x000004b4 uint32_t __1208[4]; // 0x000004b8 uint32_t sysctrl46_set; // 0x000004c8 uint32_t sysctrl47_set; // 0x000004cc uint32_t sysctrl48_set; // 0x000004d0 uint32_t sysctrl49_set; // 0x000004d4 uint32_t sysctrl50_set; // 0x000004d8 uint32_t __1244[201]; // 0x000004dc uint32_t sysctrl1_clr; // 0x00000800 uint32_t sysctrl2_clr; // 0x00000804 uint32_t sysctrl3_clr; // 0x00000808 uint32_t sysctrl4_clr; // 0x0000080c uint32_t sysctrl5_clr; // 0x00000810 uint32_t sysctrl6_clr; // 0x00000814 uint32_t sysctrl7_clr; // 0x00000818 uint32_t sysctrl8_clr; // 0x0000081c uint32_t sysctrl9_clr; // 0x00000820 uint32_t sysctrl10_clr; // 0x00000824 uint32_t sysctrl11_clr; // 0x00000828 uint32_t sysctrl12_clr; // 0x0000082c uint32_t sysctrl13_clr; // 0x00000830 uint32_t sysctrl14_clr; // 0x00000834 uint32_t sysctrl15_clr; // 0x00000838 uint32_t sysctrl16_clr; // 0x0000083c uint32_t sysctrl17_clr; // 0x00000840 uint32_t sysctrl18_clr; // 0x00000844 uint32_t sysctrl19_clr; // 0x00000848 uint32_t sysctrl20_clr; // 0x0000084c uint32_t sysctrl21_clr; // 0x00000850 uint32_t sysctrl22_clr; // 0x00000854 uint32_t sysctrl23_clr; // 0x00000858 uint32_t sysctrl24_clr; // 0x0000085c uint32_t sysctrl25_clr; // 0x00000860 uint32_t __2148[19]; // 0x00000864 uint32_t sysctrl42_clr; // 0x000008b0 uint32_t sysctrl43_clr; // 0x000008b4 uint32_t __2232[4]; // 0x000008b8 uint32_t sysctrl46_clr; // 0x000008c8 uint32_t sysctrl47_clr; // 0x000008cc uint32_t sysctrl48_clr; // 0x000008d0 uint32_t sysctrl49_clr; // 0x000008d4 uint32_t sysctrl50_clr; // 0x000008d8 } HWP_RF_SYSCTRL_T; #define hwp_rfSysctrl ((HWP_RF_SYSCTRL_T *)REG_ACCESS_ADDRESS(REG_RF_SYSCTRL_BASE)) // sysctrl1 typedef union { uint32_t v; struct { uint32_t rg_sys_ctrl_pu_bbpll1 : 1; // [0] uint32_t rg_sys_ctrl_pu_bbpll2 : 1; // [1] uint32_t rg_sys_ctrl_pu_bbpll2_dr : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_RF_SYSCTRL_SYSCTRL1_T; // sysctrl2 typedef union { uint32_t v; struct { uint32_t rg_enable_clk26m_osc_thm : 1; // [0] uint32_t rg_enable_clk26m_tsx_thm : 1; // [1] uint32_t rg_enable_clk26m_aux1 : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_RF_SYSCTRL_SYSCTRL2_T; // sysctrl3 typedef union { uint32_t v; struct { uint32_t rg_gnss_iq_sel_0 : 1; // [0] uint32_t rg_wifi_iq_sel_0 : 1; // [1] uint32_t rg_lte_iq_sel_0 : 1; // [2] uint32_t rfdig_latch_gnss : 1; // [3] uint32_t cgm_gnss_bb_pp_wcn_clk_en : 1; // [4] uint32_t cgm_gnss_bb_pp_wcn_clk_sel : 1; // [5] uint32_t cgm_gnss_adc_wcn_clk_en : 1; // [6] uint32_t cgm_gnss_adc_wcn_clk_sel : 1; // [7] uint32_t gnss_int_mask_bit : 1; // [8] uint32_t gnss_coexist_ext : 1; // [9] uint32_t rg_bitmap_lte_rx_on : 1; // [10] uint32_t __31_11 : 21; // [31:11] } b; } REG_RF_SYSCTRL_SYSCTRL3_T; // sysctrl4 typedef union { uint32_t v; struct { uint32_t rg_rf2aon_nonbuf_early_resp_en : 1; // [0] uint32_t rg_rf2aon_mclk_auto_gate_en : 1; // [1] uint32_t rg_rf2aon_sclk_auto_gate_en : 1; // [2] uint32_t rg_aon2rf_nonbuf_early_resp_en : 1; // [3] uint32_t rg_aon2rf_mclk_auto_gate_en : 1; // [4] uint32_t rg_aon2rf_sclk_auto_gate_en : 1; // [5] uint32_t rg_ram_clk_auto_cg : 2; // [7:6] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_SYSCTRL_SYSCTRL4_T; // sysctrl5 typedef union { uint32_t v; struct { uint32_t rg_lte_dac_clk_en : 1; // [0] uint32_t rg_lte_dac_clkedge_sel : 1; // [1] uint32_t rg_rtc_clkedge_sel : 1; // [2] uint32_t rg_adc_clkedge_sel : 1; // [3] uint32_t rg_dfe_dump_sel_bit : 3; // [6:4] uint32_t rg_hresp_err_mask : 1; // [7] uint32_t rg_rf_test_pad_en : 1; // [8] uint32_t rg_tsx_adc_clkedge_sel : 1; // [9] uint32_t rg_osc_adc_clkedge_sel : 1; // [10] uint32_t rg_adda_test_sel_txdlpf_afc : 1; // [11] uint32_t rg_adda_test_sel_rxdlpf_afc : 1; // [12] uint32_t rg_pwd_adc_clkedge_sel : 1; // [13] uint32_t __31_14 : 18; // [31:14] } b; } REG_RF_SYSCTRL_SYSCTRL5_T; // sysctrl6 typedef union { uint32_t v; struct { uint32_t rg_dfe_cgu_soft_rst : 1; // [0] uint32_t rg_dfe_rxdp_soft_rst : 1; // [1] uint32_t rg_dfe_txdp_soft_rst : 1; // [2] uint32_t rg_dfe_pwd_soft_rst : 1; // [3] uint32_t rg_dfe_thm_tsx_soft_rst : 1; // [4] uint32_t rg_dfe_thm_osc_soft_rst : 1; // [5] uint32_t rg_txdlpf_soft_rst : 1; // [6] uint32_t rg_rxdlpf_soft_rst : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_SYSCTRL_SYSCTRL6_T; // sysctrl7 typedef union { uint32_t v; struct { uint32_t rg_usid_change_en : 1; // [0] uint32_t rg_mipi_clk_half_en : 1; // [1] uint32_t ptest_func_atspeed_sel : 1; // [2] uint32_t __31_3 : 29; // [31:3] } b; } REG_RF_SYSCTRL_SYSCTRL7_T; // sysctrl8 typedef union { uint32_t v; struct { uint32_t rg_cgm_ahb_sel : 2; // [1:0] uint32_t rg_ahb_freq_auto_sel : 1; // [2] uint32_t rg_cgm_ahb_en : 1; // [3] uint32_t rg_cgm_26m_interface_en : 1; // [4] uint32_t rg_cgm_dfe_245m76_en : 1; // [5] uint32_t rg_rf2aon_auto_gate_en : 1; // [6] uint32_t rg_aon2rf_auto_gate_en : 1; // [7] uint32_t __9_8 : 2; // [9:8] uint32_t rg_wcn_bbpll_80m_auto_gate_en : 1; // [10] uint32_t rg_bbpll_245m_auto_gate_en : 1; // [11] uint32_t rg_bbpll_122m_auto_gate_en : 1; // [12] uint32_t rg_thm_tsx_26m_auto_gate_en : 1; // [13] uint32_t rg_thm_osc_26m_auto_gate_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL8_T; // sysctrl9 typedef union { uint32_t v; struct { uint32_t rg_rtc_clk_en : 1; // [0] uint32_t rg_rffe_clk_en : 1; // [1] uint32_t rg_26m_interface_intf_en : 1; // [2] uint32_t rg_26m_interface_rxpll_cal_en : 1; // [3] uint32_t rg_26m_interface_txpll_cal_en : 1; // [4] uint32_t rg_26m_interface_bbpll1_en : 1; // [5] uint32_t rg_26m_interface_bbpll2_en : 1; // [6] uint32_t rg_26m_interface_peak_det_en : 1; // [7] uint32_t rg_pwd_dfe_pwd_en : 1; // [8] uint32_t rg_cgm_lte_adc_en : 1; // [9] uint32_t rg_cgm_thm_osc_en : 1; // [10] uint32_t rg_cgm_thm_osc_pad_en : 1; // [11] uint32_t rg_cgm_thm_tsx_dfe_en : 1; // [12] uint32_t rg_cgm_thm_tsx_pad_en : 1; // [13] uint32_t rg_cgm_thm_tsx_bist_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL9_T; // sysctrl10 typedef union { uint32_t v; struct { uint32_t rg_ahb_bus_en : 1; // [0] uint32_t rg_ahb_dfe_en : 1; // [1] uint32_t rg_ahb_intf_en : 1; // [2] uint32_t rg_ahb_ram_en : 1; // [3] uint32_t rg_ahb_spi2ahb_en : 1; // [4] uint32_t rg_ahb_rxdlpf_en : 1; // [5] uint32_t rg_ahb_txdlpf_en : 1; // [6] uint32_t rg_rf2aon_en : 1; // [7] uint32_t rg_aon2rf_en : 1; // [8] uint32_t rg_ahb_pulp_en : 1; // [9] uint32_t rg_ahb_timer0_en : 1; // [10] uint32_t rg_ahb_wdg_en : 1; // [11] uint32_t rg_cgm_rf_bitmap_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_SYSCTRL_SYSCTRL10_T; // sysctrl11 typedef union { uint32_t v; struct { uint32_t rg_cgm_wpll_sdm_en : 1; // [0] uint32_t rg_cgm_lpll_sdm_en : 1; // [1] uint32_t rg_txpll_sdm_txsdm_en : 1; // [2] uint32_t rg_rxpll_sdm_rxsdm_en : 1; // [3] uint32_t rg_tx_gro_out1_txdlpf_en : 1; // [4] uint32_t rg_tx_gro_out2_txdlpf_en : 1; // [5] uint32_t rg_rx_gro_out1_rxdlpf_en : 1; // [6] uint32_t rg_rx_gro_out2_rxdlpf_en : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_SYSCTRL_SYSCTRL11_T; // sysctrl12 typedef union { uint32_t v; struct { uint32_t gnss_pll_397m_soft_cnt_done : 1; // [0] uint32_t gnss_pll_198m_soft_cnt_done : 1; // [1] uint32_t wcn_bbpll_80m_soft_cnt_done : 1; // [2] uint32_t bbpll_245m_soft_cnt_done : 1; // [3] uint32_t bbpll_122m_soft_cnt_done : 1; // [4] uint32_t adc_122m_soft_cnt_done : 1; // [5] uint32_t thm_tsx_26m_soft_cnt_done : 1; // [6] uint32_t thm_osc_26m_soft_cnt_done : 1; // [7] uint32_t gnss_pll_397m_cnt_done_bypass : 1; // [8] uint32_t gnss_pll_198m_cnt_done_bypass : 1; // [9] uint32_t wcn_bbpll_80m_cnt_done_bypass : 1; // [10] uint32_t bbpll_245m_cnt_done_bypass : 1; // [11] uint32_t bbpll_122m_cnt_done_bypass : 1; // [12] uint32_t adc_122m_cnt_done_bypass : 1; // [13] uint32_t thm_tsx_26m_cnt_done_bypass : 1; // [14] uint32_t thm_osc_26m_cnt_done_bypass : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL12_T; // sysctrl13 typedef union { uint32_t v; struct { uint32_t gnss_pll_397m_wait_auto_gate_sel : 1; // [0] uint32_t gnss_pll_198m_wait_auto_gate_sel : 1; // [1] uint32_t wcn_bbpll_80m_wait_auto_gate_sel : 1; // [2] uint32_t bbpll_245m_wait_auto_gate_sel : 1; // [3] uint32_t bbpll_122m_wait_auto_gate_sel : 1; // [4] uint32_t adc_122m_wait_auto_gate_sel : 1; // [5] uint32_t thm_tsx_26m_wait_auto_gate_sel : 1; // [6] uint32_t thm_osc_26m_wait_auto_gate_sel : 1; // [7] uint32_t gnss_pll_397m_wait_force_en : 1; // [8] uint32_t gnss_pll_198m_wait_force_en : 1; // [9] uint32_t wcn_bbpll_80m_wait_force_en : 1; // [10] uint32_t bbpll_245m_wait_force_en : 1; // [11] uint32_t bbpll_122m_wait_force_en : 1; // [12] uint32_t adc_122m_wait_force_en : 1; // [13] uint32_t thm_tsx_26m_wait_force_en : 1; // [14] uint32_t thm_osc_26m_wait_force_en : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL13_T; // sysctrl14 typedef union { uint32_t v; struct { uint32_t gnss_div_pll_397m_158m8_force_en : 1; // [0] uint32_t gnss_div_pll_397m_132m3_force_en : 1; // [1] uint32_t gnss_div_pll_397m_56m7_force_en : 1; // [2] uint32_t gnss_div_pll_397m_33m1_force_en : 1; // [3] uint32_t gnss_div_pll_397m_158m8_auto_gate_sel : 1; // [4] uint32_t gnss_div_pll_397m_132m3_auto_gate_sel : 1; // [5] uint32_t gnss_div_pll_397m_56m7_auto_gate_sel : 1; // [6] uint32_t gnss_div_pll_397m_33m1_auto_gate_sel : 1; // [7] uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_SYSCTRL_SYSCTRL14_T; // sysctrl15 typedef union { uint32_t v; struct { uint32_t cgm_gnss_pll_397m_ap_auto_gate_sel : 1; // [0] uint32_t cgm_gnss_pll_198_5m_ap_auto_gate_sel : 1; // [1] uint32_t cgm_gnss_pll_133m_ap_auto_gate_sel : 1; // [2] uint32_t cgm_gnss_pll_57m_ap_auto_gate_sel : 1; // [3] uint32_t cgm_gnss_pll_397m_cp_auto_gate_sel : 1; // [4] uint32_t cgm_gnss_pll_198_5m_cp_auto_gate_sel : 1; // [5] uint32_t cgm_wcn_bbpll_80m_cp_auto_gate_sel : 1; // [6] uint32_t cgm_adc_iq_cp_auto_gate_sel : 1; // [7] uint32_t cgm_thm_tsx_26m_cp_auto_gate_sel : 1; // [8] uint32_t cgm_thm_osc_26m_cp_auto_gate_sel : 1; // [9] uint32_t cgm_bbpll_245_76m_lte_auto_gate_sel : 1; // [10] uint32_t cgm_bbpll_122_88m_lte_auto_gate_sel : 1; // [11] uint32_t cgm_gnss_pll_397m_pub_auto_gate_sel : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_SYSCTRL_SYSCTRL15_T; // sysctrl16 typedef union { uint32_t v; struct { uint32_t cgm_bbpll_245_76m_rf_auto_gate_sel : 1; // [0] uint32_t cgm_bbpll_122_88m_rf_auto_gate_sel : 1; // [1] uint32_t cgm_wcn_bbpll_80m_rf_auto_gate_sel : 1; // [2] uint32_t cgm_gnss_pll_133m_rf_auto_gate_sel : 1; // [3] uint32_t cgm_adc_iq_rf_auto_gate_sel : 1; // [4] uint32_t cgm_thm_tsx_26m_rf_auto_gate_sel : 1; // [5] uint32_t cgm_thm_osc_26m_rf_auto_gate_sel : 1; // [6] uint32_t cgm_gnss_pll_397m_aon_auto_gate_sel : 1; // [7] uint32_t cgm_gnss_pll_198_5m_aon_auto_gate_sel : 1; // [8] uint32_t cgm_gnss_pll_133m_aon_auto_gate_sel : 1; // [9] uint32_t cgm_gnss_pll_33m_aon_auto_gate_sel : 1; // [10] uint32_t cgm_gnss_pll_133m_gnss_auto_gate_sel : 1; // [11] uint32_t cgm_gnss_pll_158m_gnss_auto_gate_sel : 1; // [12] uint32_t cgm_wcn_bbpll_80m_gnss_auto_gate_sel : 1; // [13] uint32_t cgm_adc_iq_gnss_auto_gate_sel : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL16_T; // sysctrl17 typedef union { uint32_t v; struct { uint32_t cgm_gnss_pll_397m_ap_force_en : 1; // [0] uint32_t cgm_gnss_pll_198_5m_ap_force_en : 1; // [1] uint32_t cgm_gnss_pll_133m_ap_force_en : 1; // [2] uint32_t cgm_gnss_pll_57m_ap_force_en : 1; // [3] uint32_t cgm_gnss_pll_397m_cp_force_en : 1; // [4] uint32_t cgm_gnss_pll_198_5m_cp_force_en : 1; // [5] uint32_t cgm_wcn_bbpll_80m_cp_force_en : 1; // [6] uint32_t cgm_adc_iq_cp_force_en : 1; // [7] uint32_t cgm_thm_tsx_26m_cp_force_en : 1; // [8] uint32_t cgm_thm_osc_26m_cp_force_en : 1; // [9] uint32_t cgm_bbpll_245_76m_lte_force_en : 1; // [10] uint32_t cgm_bbpll_122_88m_lte_force_en : 1; // [11] uint32_t cgm_gnss_pll_397m_pub_force_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_SYSCTRL_SYSCTRL17_T; // sysctrl18 typedef union { uint32_t v; struct { uint32_t cgm_bbpll_245_76m_rf_force_en : 1; // [0] uint32_t cgm_bbpll_122_88m_rf_force_en : 1; // [1] uint32_t cgm_wcn_bbpll_80m_rf_force_en : 1; // [2] uint32_t cgm_gnss_pll_133m_rf_force_en : 1; // [3] uint32_t cgm_adc_iq_rf_force_en : 1; // [4] uint32_t cgm_thm_tsx_26m_rf_force_en : 1; // [5] uint32_t cgm_thm_osc_26m_rf_force_en : 1; // [6] uint32_t cgm_gnss_pll_397m_aon_force_en : 1; // [7] uint32_t cgm_gnss_pll_198_5m_aon_force_en : 1; // [8] uint32_t cgm_gnss_pll_133m_aon_force_en : 1; // [9] uint32_t cgm_gnss_pll_33m_aon_force_en : 1; // [10] uint32_t cgm_gnss_pll_133m_gnss_force_en : 1; // [11] uint32_t cgm_gnss_pll_158m_gnss_force_en : 1; // [12] uint32_t cgm_wcn_bbpll_80m_gnss_force_en : 1; // [13] uint32_t cgm_adc_iq_gnss_force_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL18_T; // sysctrl19 typedef union { uint32_t v; struct { uint32_t rg_aon2rf_soft_rst : 1; // [0] uint32_t rg_rf2aon_soft_rst : 1; // [1] uint32_t rg_rf_bitmap_soft_rst : 1; // [2] uint32_t rg_tsen_bist_soft_rst : 1; // [3] uint32_t __31_4 : 28; // [31:4] } b; } REG_RF_SYSCTRL_SYSCTRL19_T; // sysctrl20 typedef union { uint32_t v; struct { uint32_t rg_riscv_soft_rst : 1; // [0] uint32_t rg_dbg_soft_rst : 1; // [1] uint32_t rg_ram_soft_rst : 1; // [2] uint32_t rg_txdlpf_reg_soft_rst : 1; // [3] uint32_t rg_rxdlpf_reg_soft_rst : 1; // [4] uint32_t rg_timer0_soft_rst : 1; // [5] uint32_t rg_wdg_soft_rst : 1; // [6] uint32_t rg_rffe_soft_rst : 1; // [7] uint32_t rg_ana_regs_soft_rst : 1; // [8] uint32_t rg_rtc_soft_rst : 1; // [9] uint32_t rg_spi2ahb_soft_rst : 1; // [10] uint32_t rg_intf_apb_reg_soft_rst : 1; // [11] uint32_t rg_intf_peak_det_soft_rst : 1; // [12] uint32_t rg_intf_irq_ctrl_soft_rst : 1; // [13] uint32_t rg_intf_clkgen_soft_rst : 1; // [14] uint32_t rg_dfe_reg_soft_rst : 1; // [15] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL20_T; // sysctrl21 typedef union { uint32_t v; struct { uint32_t rg_rf_gpio_o : 10; // [9:0] uint32_t __31_10 : 22; // [31:10] } b; } REG_RF_SYSCTRL_SYSCTRL21_T; // sysctrl22 typedef union { uint32_t v; struct { uint32_t rg_rf_gpio_oen : 10; // [9:0] uint32_t __31_10 : 22; // [31:10] } b; } REG_RF_SYSCTRL_SYSCTRL22_T; // sysctrl23 typedef union { uint32_t v; struct { uint32_t rg_simc_pa_on_th : 10; // [9:0] uint32_t rg_simc_pa_en : 1; // [10] uint32_t rg_simc_pa_on : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_SYSCTRL_SYSCTRL23_T; // sysctrl24 typedef union { uint32_t v; struct { uint32_t rg_sysctrl_soft_rst : 1; // [0] uint32_t __31_1 : 31; // [31:1] } b; } REG_RF_SYSCTRL_SYSCTRL24_T; // sysctrl25 typedef union { uint32_t v; struct { uint32_t rg_adda_test_soft_rst : 1; // [0] uint32_t rg_adda_test_en : 1; // [1] uint32_t rg_adda_test_dac_sel : 1; // [2] uint32_t rg_adda_test_mode : 1; // [3] uint32_t rg_adda_test_mode_sel : 3; // [6:4] uint32_t rg_txpll_open_hw_ctrl_en : 1; // [7] uint32_t rg_txpll_pkden_hw_ctrl_en : 1; // [8] uint32_t rg_txpll_dlpf_rstn_hw_ctrl_en : 1; // [9] uint32_t rg_txpll_gro_rstn_hw_ctrl_en : 1; // [10] uint32_t rg_rxpll_open_hw_ctrl_en : 1; // [11] uint32_t rg_rxpll_pkden_hw_ctrl_en : 1; // [12] uint32_t rg_rxpll_dlpf_rstn_hw_ctrl_en : 1; // [13] uint32_t rg_rxpll_gro_rstn_hw_ctrl_en : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL25_T; // sysstat1 typedef union { uint32_t v; struct { uint32_t rf_gpio_i : 10; // [9:0], read only uint32_t __31_10 : 22; // [31:10] } b; } REG_RF_SYSCTRL_SYSSTAT1_T; // sysstat2 typedef union { uint32_t v; struct { uint32_t rf_dbg_monitor : 8; // [7:0], read only uint32_t __31_8 : 24; // [31:8] } b; } REG_RF_SYSCTRL_SYSSTAT2_T; // sysctrl26 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain0 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL26_T; // sysctrl27 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain1 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL27_T; // sysctrl28 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain2 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL28_T; // sysctrl29 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain3 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL29_T; // sysctrl30 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain4 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL30_T; // sysctrl31 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain5 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL31_T; // sysctrl32 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain6 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL32_T; // sysctrl33 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain7 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL33_T; // sysctrl34 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain8 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL34_T; // sysctrl35 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain9 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL35_T; // sysctrl36 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain10 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL36_T; // sysctrl37 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain11 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL37_T; // sysctrl38 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain12 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL38_T; // sysctrl39 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain13 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL39_T; // sysctrl40 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain14 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL40_T; // sysctrl41 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain15 : 16; // [15:0] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL41_T; // sysstat3 typedef union { uint32_t v; struct { uint32_t wlan_gain_index : 4; // [3:0], read only uint32_t __31_4 : 28; // [31:4] } b; } REG_RF_SYSCTRL_SYSSTAT3_T; // sysctrl42 typedef union { uint32_t v; struct { uint32_t rg_dc_ical_sel : 2; // [1:0] uint32_t rg_dc_qcal_sel : 2; // [3:2] uint32_t rg_gain_out_sel_wifi : 1; // [4] uint32_t __31_5 : 27; // [31:5] } b; } REG_RF_SYSCTRL_SYSCTRL42_T; // sysctrl43 typedef union { uint32_t v; struct { uint32_t rg_dc_ical_offset : 8; // [7:0] uint32_t rg_dc_qcal_offset : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL43_T; // sysstat5 typedef union { uint32_t v; struct { uint32_t adda_test_mem_full : 1; // [0], read only uint32_t __7_1 : 7; // [7:1] uint32_t cgm_ahb_sel_ac : 2; // [9:8], read only uint32_t __31_10 : 22; // [31:10] } b; } REG_RF_SYSCTRL_SYSSTAT5_T; // sysctrl46 typedef union { uint32_t v; struct { uint32_t rg_pll_gro_stab_time : 10; // [9:0] uint32_t rg_rxpll_gro_auto_ctrl_en : 1; // [10] uint32_t rg_txpll_gro_auto_ctrl_en : 1; // [11] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_SYSCTRL_SYSCTRL46_T; // sysctrl47 typedef union { uint32_t v; struct { uint32_t rg_adc_bias_en_cnt : 12; // [11:0] uint32_t rg_adc_auto_ctrl_en : 1; // [12] uint32_t rg_adc_clk_enh_bb_force : 1; // [13] uint32_t rg_adc_enh_bb_force : 1; // [14] uint32_t __31_15 : 17; // [31:15] } b; } REG_RF_SYSCTRL_SYSCTRL47_T; // sysctrl48 typedef union { uint32_t v; struct { uint32_t rg_adc_clk_enh_cnt : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_SYSCTRL_SYSCTRL48_T; // sysctrl49 typedef union { uint32_t v; struct { uint32_t rg_pwdadc_bias_en_cnt : 12; // [11:0] uint32_t rg_pwdadc_auto_ctrl_en : 1; // [12] uint32_t __31_13 : 19; // [31:13] } b; } REG_RF_SYSCTRL_SYSCTRL49_T; // sysctrl50 typedef union { uint32_t v; struct { uint32_t rg_pwdadc_clk_enh_cnt : 12; // [11:0] uint32_t __31_12 : 20; // [31:12] } b; } REG_RF_SYSCTRL_SYSCTRL50_T; // sysctrl51 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain0_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain0_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL51_T; // sysctrl52 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain1_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain1_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL52_T; // sysctrl53 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain2_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain2_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL53_T; // sysctrl54 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain3_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain3_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL54_T; // sysctrl55 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain4_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain4_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL55_T; // sysctrl56 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain5_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain5_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL56_T; // sysctrl57 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain6_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain6_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL57_T; // sysctrl58 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain7_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain7_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL58_T; // sysctrl59 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain8_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain8_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL59_T; // sysctrl60 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain9_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain9_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL60_T; // sysctrl61 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain10_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain10_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL61_T; // sysctrl62 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain11_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain11_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL62_T; // sysctrl63 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain12_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain12_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL63_T; // sysctrl64 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain13_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain13_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL64_T; // sysctrl65 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain14_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain14_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL65_T; // sysctrl66 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain15_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain15_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL66_T; // sysctrl67 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain0_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain0_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL67_T; // sysctrl68 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain1_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain1_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL68_T; // sysctrl69 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain2_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain2_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL69_T; // sysctrl70 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain3_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain3_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL70_T; // sysctrl71 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain4_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain4_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL71_T; // sysctrl72 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain5_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain5_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL72_T; // sysctrl73 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain6_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain6_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL73_T; // sysctrl74 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain7_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain7_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL74_T; // sysctrl75 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain8_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain8_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL75_T; // sysctrl76 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain9_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain9_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL76_T; // sysctrl77 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain10_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain10_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL77_T; // sysctrl78 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain11_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain11_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL78_T; // sysctrl79 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain12_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain12_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL79_T; // sysctrl80 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain13_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain13_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL80_T; // sysctrl81 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain14_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain14_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL81_T; // sysctrl82 typedef union { uint32_t v; struct { uint32_t rg_wifi_gain15_rxflt_dccal_i : 8; // [7:0] uint32_t rg_wifi_gain15_rxflt_dccal_q : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_RF_SYSCTRL_SYSCTRL82_T; // sysctrl1 #define RF_SYSCTRL_RG_SYS_CTRL_PU_BBPLL1 (1 << 0) #define RF_SYSCTRL_RG_SYS_CTRL_PU_BBPLL2 (1 << 1) #define RF_SYSCTRL_RG_SYS_CTRL_PU_BBPLL2_DR (1 << 2) // sysctrl2 #define RF_SYSCTRL_RG_ENABLE_CLK26M_OSC_THM (1 << 0) #define RF_SYSCTRL_RG_ENABLE_CLK26M_TSX_THM (1 << 1) #define RF_SYSCTRL_RG_ENABLE_CLK26M_AUX1 (1 << 2) // sysctrl3 #define RF_SYSCTRL_RG_GNSS_IQ_SEL_0 (1 << 0) #define RF_SYSCTRL_RG_WIFI_IQ_SEL_0 (1 << 1) #define RF_SYSCTRL_RG_LTE_IQ_SEL_0 (1 << 2) #define RF_SYSCTRL_RFDIG_LATCH_GNSS (1 << 3) #define RF_SYSCTRL_CGM_GNSS_BB_PP_WCN_CLK_EN (1 << 4) #define RF_SYSCTRL_CGM_GNSS_BB_PP_WCN_CLK_SEL (1 << 5) #define RF_SYSCTRL_CGM_GNSS_ADC_WCN_CLK_EN (1 << 6) #define RF_SYSCTRL_CGM_GNSS_ADC_WCN_CLK_SEL (1 << 7) #define RF_SYSCTRL_GNSS_INT_MASK_BIT (1 << 8) #define RF_SYSCTRL_GNSS_COEXIST_EXT (1 << 9) #define RF_SYSCTRL_RG_BITMAP_LTE_RX_ON (1 << 10) // sysctrl4 #define RF_SYSCTRL_RG_RF2AON_NONBUF_EARLY_RESP_EN (1 << 0) #define RF_SYSCTRL_RG_RF2AON_MCLK_AUTO_GATE_EN (1 << 1) #define RF_SYSCTRL_RG_RF2AON_SCLK_AUTO_GATE_EN (1 << 2) #define RF_SYSCTRL_RG_AON2RF_NONBUF_EARLY_RESP_EN (1 << 3) #define RF_SYSCTRL_RG_AON2RF_MCLK_AUTO_GATE_EN (1 << 4) #define RF_SYSCTRL_RG_AON2RF_SCLK_AUTO_GATE_EN (1 << 5) #define RF_SYSCTRL_RG_RAM_CLK_AUTO_CG(n) (((n)&0x3) << 6) // sysctrl5 #define RF_SYSCTRL_RG_LTE_DAC_CLK_EN (1 << 0) #define RF_SYSCTRL_RG_LTE_DAC_CLKEDGE_SEL (1 << 1) #define RF_SYSCTRL_RG_RTC_CLKEDGE_SEL (1 << 2) #define RF_SYSCTRL_RG_ADC_CLKEDGE_SEL (1 << 3) #define RF_SYSCTRL_RG_DFE_DUMP_SEL_BIT(n) (((n)&0x7) << 4) #define RF_SYSCTRL_RG_HRESP_ERR_MASK (1 << 7) #define RF_SYSCTRL_RG_RF_TEST_PAD_EN (1 << 8) #define RF_SYSCTRL_RG_TSX_ADC_CLKEDGE_SEL (1 << 9) #define RF_SYSCTRL_RG_OSC_ADC_CLKEDGE_SEL (1 << 10) #define RF_SYSCTRL_RG_ADDA_TEST_SEL_TXDLPF_AFC (1 << 11) #define RF_SYSCTRL_RG_ADDA_TEST_SEL_RXDLPF_AFC (1 << 12) #define RF_SYSCTRL_RG_PWD_ADC_CLKEDGE_SEL (1 << 13) // sysctrl6 #define RF_SYSCTRL_RG_DFE_CGU_SOFT_RST (1 << 0) #define RF_SYSCTRL_RG_DFE_RXDP_SOFT_RST (1 << 1) #define RF_SYSCTRL_RG_DFE_TXDP_SOFT_RST (1 << 2) #define RF_SYSCTRL_RG_DFE_PWD_SOFT_RST (1 << 3) #define RF_SYSCTRL_RG_DFE_THM_TSX_SOFT_RST (1 << 4) #define RF_SYSCTRL_RG_DFE_THM_OSC_SOFT_RST (1 << 5) #define RF_SYSCTRL_RG_TXDLPF_SOFT_RST (1 << 6) #define RF_SYSCTRL_RG_RXDLPF_SOFT_RST (1 << 7) // sysctrl7 #define RF_SYSCTRL_RG_USID_CHANGE_EN (1 << 0) #define RF_SYSCTRL_RG_MIPI_CLK_HALF_EN (1 << 1) #define RF_SYSCTRL_PTEST_FUNC_ATSPEED_SEL (1 << 2) // sysctrl8 #define RF_SYSCTRL_RG_CGM_AHB_SEL(n) (((n)&0x3) << 0) #define RF_SYSCTRL_RG_AHB_FREQ_AUTO_SEL (1 << 2) #define RF_SYSCTRL_RG_CGM_AHB_EN (1 << 3) #define RF_SYSCTRL_RG_CGM_26M_INTERFACE_EN (1 << 4) #define RF_SYSCTRL_RG_CGM_DFE_245M76_EN (1 << 5) #define RF_SYSCTRL_RG_RF2AON_AUTO_GATE_EN (1 << 6) #define RF_SYSCTRL_RG_AON2RF_AUTO_GATE_EN (1 << 7) #define RF_SYSCTRL_RG_WCN_BBPLL_80M_AUTO_GATE_EN (1 << 10) #define RF_SYSCTRL_RG_BBPLL_245M_AUTO_GATE_EN (1 << 11) #define RF_SYSCTRL_RG_BBPLL_122M_AUTO_GATE_EN (1 << 12) #define RF_SYSCTRL_RG_THM_TSX_26M_AUTO_GATE_EN (1 << 13) #define RF_SYSCTRL_RG_THM_OSC_26M_AUTO_GATE_EN (1 << 14) // sysctrl9 #define RF_SYSCTRL_RG_RTC_CLK_EN (1 << 0) #define RF_SYSCTRL_RG_RFFE_CLK_EN (1 << 1) #define RF_SYSCTRL_RG_26M_INTERFACE_INTF_EN (1 << 2) #define RF_SYSCTRL_RG_26M_INTERFACE_RXPLL_CAL_EN (1 << 3) #define RF_SYSCTRL_RG_26M_INTERFACE_TXPLL_CAL_EN (1 << 4) #define RF_SYSCTRL_RG_26M_INTERFACE_BBPLL1_EN (1 << 5) #define RF_SYSCTRL_RG_26M_INTERFACE_BBPLL2_EN (1 << 6) #define RF_SYSCTRL_RG_26M_INTERFACE_PEAK_DET_EN (1 << 7) #define RF_SYSCTRL_RG_PWD_DFE_PWD_EN (1 << 8) #define RF_SYSCTRL_RG_CGM_LTE_ADC_EN (1 << 9) #define RF_SYSCTRL_RG_CGM_THM_OSC_EN (1 << 10) #define RF_SYSCTRL_RG_CGM_THM_OSC_PAD_EN (1 << 11) #define RF_SYSCTRL_RG_CGM_THM_TSX_DFE_EN (1 << 12) #define RF_SYSCTRL_RG_CGM_THM_TSX_PAD_EN (1 << 13) #define RF_SYSCTRL_RG_CGM_THM_TSX_BIST_EN (1 << 14) // sysctrl10 #define RF_SYSCTRL_RG_AHB_BUS_EN (1 << 0) #define RF_SYSCTRL_RG_AHB_DFE_EN (1 << 1) #define RF_SYSCTRL_RG_AHB_INTF_EN (1 << 2) #define RF_SYSCTRL_RG_AHB_RAM_EN (1 << 3) #define RF_SYSCTRL_RG_AHB_SPI2AHB_EN (1 << 4) #define RF_SYSCTRL_RG_AHB_RXDLPF_EN (1 << 5) #define RF_SYSCTRL_RG_AHB_TXDLPF_EN (1 << 6) #define RF_SYSCTRL_RG_RF2AON_EN (1 << 7) #define RF_SYSCTRL_RG_AON2RF_EN (1 << 8) #define RF_SYSCTRL_RG_AHB_PULP_EN (1 << 9) #define RF_SYSCTRL_RG_AHB_TIMER0_EN (1 << 10) #define RF_SYSCTRL_RG_AHB_WDG_EN (1 << 11) #define RF_SYSCTRL_RG_CGM_RF_BITMAP_EN (1 << 12) // sysctrl11 #define RF_SYSCTRL_RG_CGM_WPLL_SDM_EN (1 << 0) #define RF_SYSCTRL_RG_CGM_LPLL_SDM_EN (1 << 1) #define RF_SYSCTRL_RG_TXPLL_SDM_TXSDM_EN (1 << 2) #define RF_SYSCTRL_RG_RXPLL_SDM_RXSDM_EN (1 << 3) #define RF_SYSCTRL_RG_TX_GRO_OUT1_TXDLPF_EN (1 << 4) #define RF_SYSCTRL_RG_TX_GRO_OUT2_TXDLPF_EN (1 << 5) #define RF_SYSCTRL_RG_RX_GRO_OUT1_RXDLPF_EN (1 << 6) #define RF_SYSCTRL_RG_RX_GRO_OUT2_RXDLPF_EN (1 << 7) // sysctrl12 #define RF_SYSCTRL_GNSS_PLL_397M_SOFT_CNT_DONE (1 << 0) #define RF_SYSCTRL_GNSS_PLL_198M_SOFT_CNT_DONE (1 << 1) #define RF_SYSCTRL_WCN_BBPLL_80M_SOFT_CNT_DONE (1 << 2) #define RF_SYSCTRL_BBPLL_245M_SOFT_CNT_DONE (1 << 3) #define RF_SYSCTRL_BBPLL_122M_SOFT_CNT_DONE (1 << 4) #define RF_SYSCTRL_ADC_122M_SOFT_CNT_DONE (1 << 5) #define RF_SYSCTRL_THM_TSX_26M_SOFT_CNT_DONE (1 << 6) #define RF_SYSCTRL_THM_OSC_26M_SOFT_CNT_DONE (1 << 7) #define RF_SYSCTRL_GNSS_PLL_397M_CNT_DONE_BYPASS (1 << 8) #define RF_SYSCTRL_GNSS_PLL_198M_CNT_DONE_BYPASS (1 << 9) #define RF_SYSCTRL_WCN_BBPLL_80M_CNT_DONE_BYPASS (1 << 10) #define RF_SYSCTRL_BBPLL_245M_CNT_DONE_BYPASS (1 << 11) #define RF_SYSCTRL_BBPLL_122M_CNT_DONE_BYPASS (1 << 12) #define RF_SYSCTRL_ADC_122M_CNT_DONE_BYPASS (1 << 13) #define RF_SYSCTRL_THM_TSX_26M_CNT_DONE_BYPASS (1 << 14) #define RF_SYSCTRL_THM_OSC_26M_CNT_DONE_BYPASS (1 << 15) // sysctrl13 #define RF_SYSCTRL_GNSS_PLL_397M_WAIT_AUTO_GATE_SEL (1 << 0) #define RF_SYSCTRL_GNSS_PLL_198M_WAIT_AUTO_GATE_SEL (1 << 1) #define RF_SYSCTRL_WCN_BBPLL_80M_WAIT_AUTO_GATE_SEL (1 << 2) #define RF_SYSCTRL_BBPLL_245M_WAIT_AUTO_GATE_SEL (1 << 3) #define RF_SYSCTRL_BBPLL_122M_WAIT_AUTO_GATE_SEL (1 << 4) #define RF_SYSCTRL_ADC_122M_WAIT_AUTO_GATE_SEL (1 << 5) #define RF_SYSCTRL_THM_TSX_26M_WAIT_AUTO_GATE_SEL (1 << 6) #define RF_SYSCTRL_THM_OSC_26M_WAIT_AUTO_GATE_SEL (1 << 7) #define RF_SYSCTRL_GNSS_PLL_397M_WAIT_FORCE_EN (1 << 8) #define RF_SYSCTRL_GNSS_PLL_198M_WAIT_FORCE_EN (1 << 9) #define RF_SYSCTRL_WCN_BBPLL_80M_WAIT_FORCE_EN (1 << 10) #define RF_SYSCTRL_BBPLL_245M_WAIT_FORCE_EN (1 << 11) #define RF_SYSCTRL_BBPLL_122M_WAIT_FORCE_EN (1 << 12) #define RF_SYSCTRL_ADC_122M_WAIT_FORCE_EN (1 << 13) #define RF_SYSCTRL_THM_TSX_26M_WAIT_FORCE_EN (1 << 14) #define RF_SYSCTRL_THM_OSC_26M_WAIT_FORCE_EN (1 << 15) // sysctrl14 #define RF_SYSCTRL_GNSS_DIV_PLL_397M_158M8_FORCE_EN (1 << 0) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_132M3_FORCE_EN (1 << 1) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_56M7_FORCE_EN (1 << 2) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_33M1_FORCE_EN (1 << 3) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_158M8_AUTO_GATE_SEL (1 << 4) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_132M3_AUTO_GATE_SEL (1 << 5) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_56M7_AUTO_GATE_SEL (1 << 6) #define RF_SYSCTRL_GNSS_DIV_PLL_397M_33M1_AUTO_GATE_SEL (1 << 7) // sysctrl15 #define RF_SYSCTRL_CGM_GNSS_PLL_397M_AP_AUTO_GATE_SEL (1 << 0) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_AP_AUTO_GATE_SEL (1 << 1) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_AP_AUTO_GATE_SEL (1 << 2) #define RF_SYSCTRL_CGM_GNSS_PLL_57M_AP_AUTO_GATE_SEL (1 << 3) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_CP_AUTO_GATE_SEL (1 << 4) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_CP_AUTO_GATE_SEL (1 << 5) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_CP_AUTO_GATE_SEL (1 << 6) #define RF_SYSCTRL_CGM_ADC_IQ_CP_AUTO_GATE_SEL (1 << 7) #define RF_SYSCTRL_CGM_THM_TSX_26M_CP_AUTO_GATE_SEL (1 << 8) #define RF_SYSCTRL_CGM_THM_OSC_26M_CP_AUTO_GATE_SEL (1 << 9) #define RF_SYSCTRL_CGM_BBPLL_245_76M_LTE_AUTO_GATE_SEL (1 << 10) #define RF_SYSCTRL_CGM_BBPLL_122_88M_LTE_AUTO_GATE_SEL (1 << 11) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_PUB_AUTO_GATE_SEL (1 << 12) // sysctrl16 #define RF_SYSCTRL_CGM_BBPLL_245_76M_RF_AUTO_GATE_SEL (1 << 0) #define RF_SYSCTRL_CGM_BBPLL_122_88M_RF_AUTO_GATE_SEL (1 << 1) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_RF_AUTO_GATE_SEL (1 << 2) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_RF_AUTO_GATE_SEL (1 << 3) #define RF_SYSCTRL_CGM_ADC_IQ_RF_AUTO_GATE_SEL (1 << 4) #define RF_SYSCTRL_CGM_THM_TSX_26M_RF_AUTO_GATE_SEL (1 << 5) #define RF_SYSCTRL_CGM_THM_OSC_26M_RF_AUTO_GATE_SEL (1 << 6) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_AON_AUTO_GATE_SEL (1 << 7) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_AON_AUTO_GATE_SEL (1 << 8) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_AON_AUTO_GATE_SEL (1 << 9) #define RF_SYSCTRL_CGM_GNSS_PLL_33M_AON_AUTO_GATE_SEL (1 << 10) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_GNSS_AUTO_GATE_SEL (1 << 11) #define RF_SYSCTRL_CGM_GNSS_PLL_158M_GNSS_AUTO_GATE_SEL (1 << 12) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_GNSS_AUTO_GATE_SEL (1 << 13) #define RF_SYSCTRL_CGM_ADC_IQ_GNSS_AUTO_GATE_SEL (1 << 14) // sysctrl17 #define RF_SYSCTRL_CGM_GNSS_PLL_397M_AP_FORCE_EN (1 << 0) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_AP_FORCE_EN (1 << 1) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_AP_FORCE_EN (1 << 2) #define RF_SYSCTRL_CGM_GNSS_PLL_57M_AP_FORCE_EN (1 << 3) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_CP_FORCE_EN (1 << 4) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_CP_FORCE_EN (1 << 5) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_CP_FORCE_EN (1 << 6) #define RF_SYSCTRL_CGM_ADC_IQ_CP_FORCE_EN (1 << 7) #define RF_SYSCTRL_CGM_THM_TSX_26M_CP_FORCE_EN (1 << 8) #define RF_SYSCTRL_CGM_THM_OSC_26M_CP_FORCE_EN (1 << 9) #define RF_SYSCTRL_CGM_BBPLL_245_76M_LTE_FORCE_EN (1 << 10) #define RF_SYSCTRL_CGM_BBPLL_122_88M_LTE_FORCE_EN (1 << 11) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_PUB_FORCE_EN (1 << 12) // sysctrl18 #define RF_SYSCTRL_CGM_BBPLL_245_76M_RF_FORCE_EN (1 << 0) #define RF_SYSCTRL_CGM_BBPLL_122_88M_RF_FORCE_EN (1 << 1) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_RF_FORCE_EN (1 << 2) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_RF_FORCE_EN (1 << 3) #define RF_SYSCTRL_CGM_ADC_IQ_RF_FORCE_EN (1 << 4) #define RF_SYSCTRL_CGM_THM_TSX_26M_RF_FORCE_EN (1 << 5) #define RF_SYSCTRL_CGM_THM_OSC_26M_RF_FORCE_EN (1 << 6) #define RF_SYSCTRL_CGM_GNSS_PLL_397M_AON_FORCE_EN (1 << 7) #define RF_SYSCTRL_CGM_GNSS_PLL_198_5M_AON_FORCE_EN (1 << 8) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_AON_FORCE_EN (1 << 9) #define RF_SYSCTRL_CGM_GNSS_PLL_33M_AON_FORCE_EN (1 << 10) #define RF_SYSCTRL_CGM_GNSS_PLL_133M_GNSS_FORCE_EN (1 << 11) #define RF_SYSCTRL_CGM_GNSS_PLL_158M_GNSS_FORCE_EN (1 << 12) #define RF_SYSCTRL_CGM_WCN_BBPLL_80M_GNSS_FORCE_EN (1 << 13) #define RF_SYSCTRL_CGM_ADC_IQ_GNSS_FORCE_EN (1 << 14) // sysctrl19 #define RF_SYSCTRL_RG_AON2RF_SOFT_RST (1 << 0) #define RF_SYSCTRL_RG_RF2AON_SOFT_RST (1 << 1) #define RF_SYSCTRL_RG_RF_BITMAP_SOFT_RST (1 << 2) #define RF_SYSCTRL_RG_TSEN_BIST_SOFT_RST (1 << 3) // sysctrl20 #define RF_SYSCTRL_RG_RISCV_SOFT_RST (1 << 0) #define RF_SYSCTRL_RG_DBG_SOFT_RST (1 << 1) #define RF_SYSCTRL_RG_RAM_SOFT_RST (1 << 2) #define RF_SYSCTRL_RG_TXDLPF_REG_SOFT_RST (1 << 3) #define RF_SYSCTRL_RG_RXDLPF_REG_SOFT_RST (1 << 4) #define RF_SYSCTRL_RG_TIMER0_SOFT_RST (1 << 5) #define RF_SYSCTRL_RG_WDG_SOFT_RST (1 << 6) #define RF_SYSCTRL_RG_RFFE_SOFT_RST (1 << 7) #define RF_SYSCTRL_RG_ANA_REGS_SOFT_RST (1 << 8) #define RF_SYSCTRL_RG_RTC_SOFT_RST (1 << 9) #define RF_SYSCTRL_RG_SPI2AHB_SOFT_RST (1 << 10) #define RF_SYSCTRL_RG_INTF_APB_REG_SOFT_RST (1 << 11) #define RF_SYSCTRL_RG_INTF_PEAK_DET_SOFT_RST (1 << 12) #define RF_SYSCTRL_RG_INTF_IRQ_CTRL_SOFT_RST (1 << 13) #define RF_SYSCTRL_RG_INTF_CLKGEN_SOFT_RST (1 << 14) #define RF_SYSCTRL_RG_DFE_REG_SOFT_RST (1 << 15) // sysctrl21 #define RF_SYSCTRL_RG_RF_GPIO_O(n) (((n)&0x3ff) << 0) // sysctrl22 #define RF_SYSCTRL_RG_RF_GPIO_OEN(n) (((n)&0x3ff) << 0) // sysctrl23 #define RF_SYSCTRL_RG_SIMC_PA_ON_TH(n) (((n)&0x3ff) << 0) #define RF_SYSCTRL_RG_SIMC_PA_EN (1 << 10) #define RF_SYSCTRL_RG_SIMC_PA_ON (1 << 11) // sysctrl24 #define RF_SYSCTRL_RG_SYSCTRL_SOFT_RST (1 << 0) // sysctrl25 #define RF_SYSCTRL_RG_ADDA_TEST_SOFT_RST (1 << 0) #define RF_SYSCTRL_RG_ADDA_TEST_EN (1 << 1) #define RF_SYSCTRL_RG_ADDA_TEST_DAC_SEL (1 << 2) #define RF_SYSCTRL_RG_ADDA_TEST_MODE (1 << 3) #define RF_SYSCTRL_RG_ADDA_TEST_MODE_SEL(n) (((n)&0x7) << 4) #define RF_SYSCTRL_RG_TXPLL_OPEN_HW_CTRL_EN (1 << 7) #define RF_SYSCTRL_RG_TXPLL_PKDEN_HW_CTRL_EN (1 << 8) #define RF_SYSCTRL_RG_TXPLL_DLPF_RSTN_HW_CTRL_EN (1 << 9) #define RF_SYSCTRL_RG_TXPLL_GRO_RSTN_HW_CTRL_EN (1 << 10) #define RF_SYSCTRL_RG_RXPLL_OPEN_HW_CTRL_EN (1 << 11) #define RF_SYSCTRL_RG_RXPLL_PKDEN_HW_CTRL_EN (1 << 12) #define RF_SYSCTRL_RG_RXPLL_DLPF_RSTN_HW_CTRL_EN (1 << 13) #define RF_SYSCTRL_RG_RXPLL_GRO_RSTN_HW_CTRL_EN (1 << 14) // sysstat1 #define RF_SYSCTRL_RF_GPIO_I(n) (((n)&0x3ff) << 0) // sysstat2 #define RF_SYSCTRL_RF_DBG_MONITOR(n) (((n)&0xff) << 0) // sysctrl26 #define RF_SYSCTRL_RG_WIFI_GAIN0(n) (((n)&0xffff) << 0) // sysctrl27 #define RF_SYSCTRL_RG_WIFI_GAIN1(n) (((n)&0xffff) << 0) // sysctrl28 #define RF_SYSCTRL_RG_WIFI_GAIN2(n) (((n)&0xffff) << 0) // sysctrl29 #define RF_SYSCTRL_RG_WIFI_GAIN3(n) (((n)&0xffff) << 0) // sysctrl30 #define RF_SYSCTRL_RG_WIFI_GAIN4(n) (((n)&0xffff) << 0) // sysctrl31 #define RF_SYSCTRL_RG_WIFI_GAIN5(n) (((n)&0xffff) << 0) // sysctrl32 #define RF_SYSCTRL_RG_WIFI_GAIN6(n) (((n)&0xffff) << 0) // sysctrl33 #define RF_SYSCTRL_RG_WIFI_GAIN7(n) (((n)&0xffff) << 0) // sysctrl34 #define RF_SYSCTRL_RG_WIFI_GAIN8(n) (((n)&0xffff) << 0) // sysctrl35 #define RF_SYSCTRL_RG_WIFI_GAIN9(n) (((n)&0xffff) << 0) // sysctrl36 #define RF_SYSCTRL_RG_WIFI_GAIN10(n) (((n)&0xffff) << 0) // sysctrl37 #define RF_SYSCTRL_RG_WIFI_GAIN11(n) (((n)&0xffff) << 0) // sysctrl38 #define RF_SYSCTRL_RG_WIFI_GAIN12(n) (((n)&0xffff) << 0) // sysctrl39 #define RF_SYSCTRL_RG_WIFI_GAIN13(n) (((n)&0xffff) << 0) // sysctrl40 #define RF_SYSCTRL_RG_WIFI_GAIN14(n) (((n)&0xffff) << 0) // sysctrl41 #define RF_SYSCTRL_RG_WIFI_GAIN15(n) (((n)&0xffff) << 0) // sysstat3 #define RF_SYSCTRL_WLAN_GAIN_INDEX(n) (((n)&0xf) << 0) // sysctrl42 #define RF_SYSCTRL_RG_DC_ICAL_SEL(n) (((n)&0x3) << 0) #define RF_SYSCTRL_RG_DC_QCAL_SEL(n) (((n)&0x3) << 2) #define RF_SYSCTRL_RG_GAIN_OUT_SEL_WIFI (1 << 4) // sysctrl43 #define RF_SYSCTRL_RG_DC_ICAL_OFFSET(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_DC_QCAL_OFFSET(n) (((n)&0xff) << 8) // sysstat5 #define RF_SYSCTRL_ADDA_TEST_MEM_FULL (1 << 0) #define RF_SYSCTRL_CGM_AHB_SEL_AC(n) (((n)&0x3) << 8) // sysctrl46 #define RF_SYSCTRL_RG_PLL_GRO_STAB_TIME(n) (((n)&0x3ff) << 0) #define RF_SYSCTRL_RG_RXPLL_GRO_AUTO_CTRL_EN (1 << 10) #define RF_SYSCTRL_RG_TXPLL_GRO_AUTO_CTRL_EN (1 << 11) // sysctrl47 #define RF_SYSCTRL_RG_ADC_BIAS_EN_CNT(n) (((n)&0xfff) << 0) #define RF_SYSCTRL_RG_ADC_AUTO_CTRL_EN (1 << 12) #define RF_SYSCTRL_RG_ADC_CLK_ENH_BB_FORCE (1 << 13) #define RF_SYSCTRL_RG_ADC_ENH_BB_FORCE (1 << 14) // sysctrl48 #define RF_SYSCTRL_RG_ADC_CLK_ENH_CNT(n) (((n)&0xfff) << 0) // sysctrl49 #define RF_SYSCTRL_RG_PWDADC_BIAS_EN_CNT(n) (((n)&0xfff) << 0) #define RF_SYSCTRL_RG_PWDADC_AUTO_CTRL_EN (1 << 12) // sysctrl50 #define RF_SYSCTRL_RG_PWDADC_CLK_ENH_CNT(n) (((n)&0xfff) << 0) // sysctrl51 #define RF_SYSCTRL_RG_WIFI_GAIN0_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN0_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl52 #define RF_SYSCTRL_RG_WIFI_GAIN1_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN1_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl53 #define RF_SYSCTRL_RG_WIFI_GAIN2_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN2_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl54 #define RF_SYSCTRL_RG_WIFI_GAIN3_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN3_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl55 #define RF_SYSCTRL_RG_WIFI_GAIN4_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN4_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl56 #define RF_SYSCTRL_RG_WIFI_GAIN5_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN5_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl57 #define RF_SYSCTRL_RG_WIFI_GAIN6_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN6_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl58 #define RF_SYSCTRL_RG_WIFI_GAIN7_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN7_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl59 #define RF_SYSCTRL_RG_WIFI_GAIN8_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN8_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl60 #define RF_SYSCTRL_RG_WIFI_GAIN9_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN9_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl61 #define RF_SYSCTRL_RG_WIFI_GAIN10_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN10_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl62 #define RF_SYSCTRL_RG_WIFI_GAIN11_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN11_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl63 #define RF_SYSCTRL_RG_WIFI_GAIN12_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN12_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl64 #define RF_SYSCTRL_RG_WIFI_GAIN13_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN13_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl65 #define RF_SYSCTRL_RG_WIFI_GAIN14_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN14_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl66 #define RF_SYSCTRL_RG_WIFI_GAIN15_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN15_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl67 #define RF_SYSCTRL_RG_WIFI_GAIN0_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN0_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl68 #define RF_SYSCTRL_RG_WIFI_GAIN1_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN1_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl69 #define RF_SYSCTRL_RG_WIFI_GAIN2_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN2_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl70 #define RF_SYSCTRL_RG_WIFI_GAIN3_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN3_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl71 #define RF_SYSCTRL_RG_WIFI_GAIN4_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN4_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl72 #define RF_SYSCTRL_RG_WIFI_GAIN5_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN5_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl73 #define RF_SYSCTRL_RG_WIFI_GAIN6_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN6_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl74 #define RF_SYSCTRL_RG_WIFI_GAIN7_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN7_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl75 #define RF_SYSCTRL_RG_WIFI_GAIN8_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN8_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl76 #define RF_SYSCTRL_RG_WIFI_GAIN9_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN9_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl77 #define RF_SYSCTRL_RG_WIFI_GAIN10_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN10_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl78 #define RF_SYSCTRL_RG_WIFI_GAIN11_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN11_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl79 #define RF_SYSCTRL_RG_WIFI_GAIN12_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN12_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl80 #define RF_SYSCTRL_RG_WIFI_GAIN13_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN13_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl81 #define RF_SYSCTRL_RG_WIFI_GAIN14_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN14_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) // sysctrl82 #define RF_SYSCTRL_RG_WIFI_GAIN15_RXFLT_DCCAL_I(n) (((n)&0xff) << 0) #define RF_SYSCTRL_RG_WIFI_GAIN15_RXFLT_DCCAL_Q(n) (((n)&0xff) << 8) #endif // _RF_SYSCTRL_H_