/* Copyright (C) 2018 RDA Technologies Limited and/or its affiliates("RDA"). * All rights reserved. * * This software is supplied "AS IS" without any warranties. * RDA assumes no responsibility or liability for the use of the software, * conveys no license or title under any patent, copyright, or mask work * right to the product. RDA reserves the right to make changes in the * software without notification. RDA also make no representation or * warranty that such application will be suitable for the specified use * without further testing or modification. */ #ifndef _SCC_H_ #define _SCC_H_ // Auto generated by dtools(see dtools.txt for its version). // Don't edit it manually! #define REG_SCC_BASE (0x51505000) typedef volatile struct { uint32_t scc_tune_lmt_cfg; // 0x00000000 uint32_t scc_tune_status; // 0x00000004 uint32_t scc_cfg; // 0x00000008 uint32_t scc_tune_step_cfg; // 0x0000000c uint32_t scc_wait_cfg; // 0x00000010 uint32_t scc_int_cfg; // 0x00000014 uint32_t scc_tune_mark; // 0x00000018 uint32_t scc_fsm_sts; // 0x0000001c uint32_t scc_rosc_mode; // 0x00000020 uint32_t scc_rosc_cfg; // 0x00000024 uint32_t scc_rosc_ctrl; // 0x00000028 uint32_t scc_rosc_rpt; // 0x0000002c uint32_t scc_rosc_sw_rst; // 0x00000030 } HWP_SCC_T; #define hwp_scc ((HWP_SCC_T *)REG_ACCESS_ADDRESS(REG_SCC_BASE)) // scc_tune_lmt_cfg typedef union { uint32_t v; struct { uint32_t volt_tune_val_min : 8; // [7:0] uint32_t volt_tune_val_max : 8; // [15:8] uint32_t __31_16 : 16; // [31:16] } b; } REG_SCC_SCC_TUNE_LMT_CFG_T; // scc_tune_status typedef union { uint32_t v; struct { uint32_t volt_obs_val : 8; // [7:0], read only uint32_t volt_tune_val : 8; // [15:8], read only uint32_t __31_16 : 16; // [31:16] } b; } REG_SCC_SCC_TUNE_STATUS_T; // scc_cfg typedef union { uint32_t v; struct { uint32_t volt_obs_forbid_en : 1; // [0] uint32_t __3_1 : 3; // [3:1] uint32_t volt_tune_forbid_en : 1; // [4] uint32_t __7_5 : 3; // [7:5] uint32_t pause_occur_err_en : 1; // [8] uint32_t __29_9 : 21; // [29:9] uint32_t volt1_select_override : 1; // [30] uint32_t volt0_select_override : 1; // [31] } b; } REG_SCC_SCC_CFG_T; // scc_tune_step_cfg typedef union { uint32_t v; struct { uint32_t volt_tune_up_step : 9; // [8:0] uint32_t __15_9 : 7; // [15:9] uint32_t volt_tune_down_step : 9; // [24:16] uint32_t __31_25 : 7; // [31:25] } b; } REG_SCC_SCC_TUNE_STEP_CFG_T; // scc_wait_cfg typedef union { uint32_t v; struct { uint32_t volt_stb_wait_num : 16; // [15:0] uint32_t rnd_intval_wait_num : 16; // [31:16] } b; } REG_SCC_SCC_WAIT_CFG_T; // scc_int_cfg typedef union { uint32_t v; struct { uint32_t scc_tune_err_int_en : 1; // [0] uint32_t scc_tune_done_int_en : 1; // [1] uint32_t __3_2 : 2; // [3:2] uint32_t scc_tune_err_int_clr : 1; // [4] uint32_t scc_tune_done_int_clr : 1; // [5] uint32_t __7_6 : 2; // [7:6] uint32_t scc_tune_err_int_raw_status : 1; // [8], read only uint32_t scc_tune_done_int_raw_status : 1; // [9], read only uint32_t __11_10 : 2; // [11:10] uint32_t scc_tune_err_int_mask_status : 1; // [12], read only uint32_t scc_tune_done_int_mask_status : 1; // [13], read only uint32_t __31_14 : 18; // [31:14] } b; } REG_SCC_SCC_INT_CFG_T; // scc_tune_mark typedef union { uint32_t v; struct { uint32_t scc_tune_up_mark : 16; // [15:0] uint32_t scc_tune_dwn_mark : 16; // [31:16] } b; } REG_SCC_SCC_TUNE_MARK_T; // scc_fsm_sts typedef union { uint32_t v; struct { uint32_t scc_fsm_sts : 5; // [4:0], read only uint32_t __31_5 : 27; // [31:5] } b; } REG_SCC_SCC_FSM_STS_T; // scc_rosc_mode typedef union { uint32_t v; struct { uint32_t scc_rosc_repeat_mode : 1; // [0] uint32_t scc_all_rosc_seq : 1; // [1] uint32_t scc_all_rosc_chain : 1; // [2] uint32_t __11_3 : 9; // [11:3] uint32_t scc_rpt_read_ctrl : 1; // [12] uint32_t __28_13 : 16; // [28:13] uint32_t scc_init_halt_bypass : 1; // [29] uint32_t scc_tune_bypass : 1; // [30] uint32_t scc_idle_mode : 1; // [31] } b; } REG_SCC_SCC_ROSC_MODE_T; // scc_rosc_cfg typedef union { uint32_t v; struct { uint32_t scc_rosc_sel_x : 4; // [3:0] uint32_t scc_rosc_sel_y : 4; // [7:4] uint32_t scc_rosc_sel_z : 4; // [11:8] uint32_t scc_rosc_duration : 20; // [31:12] } b; } REG_SCC_SCC_ROSC_CFG_T; // scc_rosc_ctrl typedef union { uint32_t v; struct { uint32_t scc_rosc_run : 1; // [0] uint32_t scc_rosc_gr_enable : 1; // [1] uint32_t __30_2 : 29; // [30:2] uint32_t scc_rpt_read_nxt : 1; // [31] } b; } REG_SCC_SCC_ROSC_CTRL_T; // scc_rosc_rpt typedef union { uint32_t v; struct { uint32_t scc_rosc_cnt : 20; // [19:0], read only uint32_t scc_rosc_setting : 5; // [24:20], read only uint32_t __29_25 : 5; // [29:25] uint32_t scc_rosc_rpt_valid : 1; // [30], read only uint32_t scc_init_pat_fail : 1; // [31], read only } b; } REG_SCC_SCC_ROSC_RPT_T; // scc_rosc_sw_rst typedef union { uint32_t v; struct { uint32_t scc_rosc_sw_rst : 2; // [1:0] uint32_t __31_2 : 30; // [31:2] } b; } REG_SCC_SCC_ROSC_SW_RST_T; // scc_tune_lmt_cfg #define SCC_VOLT_TUNE_VAL_MIN(n) (((n)&0xff) << 0) #define SCC_VOLT_TUNE_VAL_MAX(n) (((n)&0xff) << 8) // scc_tune_status #define SCC_VOLT_OBS_VAL(n) (((n)&0xff) << 0) #define SCC_VOLT_TUNE_VAL(n) (((n)&0xff) << 8) // scc_cfg #define SCC_VOLT_OBS_FORBID_EN (1 << 0) #define SCC_VOLT_TUNE_FORBID_EN (1 << 4) #define SCC_PAUSE_OCCUR_ERR_EN (1 << 8) #define SCC_VOLT1_SELECT_OVERRIDE (1 << 30) #define SCC_VOLT0_SELECT_OVERRIDE (1 << 31) // scc_tune_step_cfg #define SCC_VOLT_TUNE_UP_STEP(n) (((n)&0x1ff) << 0) #define SCC_VOLT_TUNE_DOWN_STEP(n) (((n)&0x1ff) << 16) // scc_wait_cfg #define SCC_VOLT_STB_WAIT_NUM(n) (((n)&0xffff) << 0) #define SCC_RND_INTVAL_WAIT_NUM(n) (((n)&0xffff) << 16) // scc_int_cfg #define SCC_SCC_TUNE_ERR_INT_EN (1 << 0) #define SCC_SCC_TUNE_DONE_INT_EN (1 << 1) #define SCC_SCC_TUNE_ERR_INT_CLR (1 << 4) #define SCC_SCC_TUNE_DONE_INT_CLR (1 << 5) #define SCC_SCC_TUNE_ERR_INT_RAW_STATUS (1 << 8) #define SCC_SCC_TUNE_DONE_INT_RAW_STATUS (1 << 9) #define SCC_SCC_TUNE_ERR_INT_MASK_STATUS (1 << 12) #define SCC_SCC_TUNE_DONE_INT_MASK_STATUS (1 << 13) // scc_tune_mark #define SCC_SCC_TUNE_UP_MARK(n) (((n)&0xffff) << 0) #define SCC_SCC_TUNE_DWN_MARK(n) (((n)&0xffff) << 16) // scc_fsm_sts #define SCC_SCC_FSM_STS(n) (((n)&0x1f) << 0) // scc_rosc_mode #define SCC_SCC_ROSC_REPEAT_MODE (1 << 0) #define SCC_SCC_ALL_ROSC_SEQ (1 << 1) #define SCC_SCC_ALL_ROSC_CHAIN (1 << 2) #define SCC_SCC_RPT_READ_CTRL (1 << 12) #define SCC_SCC_INIT_HALT_BYPASS (1 << 29) #define SCC_SCC_TUNE_BYPASS (1 << 30) #define SCC_SCC_IDLE_MODE (1 << 31) // scc_rosc_cfg #define SCC_SCC_ROSC_SEL_X(n) (((n)&0xf) << 0) #define SCC_SCC_ROSC_SEL_Y(n) (((n)&0xf) << 4) #define SCC_SCC_ROSC_SEL_Z(n) (((n)&0xf) << 8) #define SCC_SCC_ROSC_DURATION(n) (((n)&0xfffff) << 12) // scc_rosc_ctrl #define SCC_SCC_ROSC_RUN (1 << 0) #define SCC_SCC_ROSC_GR_ENABLE (1 << 1) #define SCC_SCC_RPT_READ_NXT (1 << 31) // scc_rosc_rpt #define SCC_SCC_ROSC_CNT(n) (((n)&0xfffff) << 0) #define SCC_SCC_ROSC_SETTING(n) (((n)&0x1f) << 20) #define SCC_SCC_ROSC_RPT_VALID (1 << 30) #define SCC_SCC_INIT_PAT_FAIL (1 << 31) // scc_rosc_sw_rst #define SCC_SCC_ROSC_SW_RST(n) (((n)&0x3) << 0) #endif // _SCC_H_